MCAUSE register holds wrong exception

[bantierr]

Type of issue: bug report
Hi,
Please, find the source files to reproduce the bug in this repository: https://github.com/bantierr/rocket_issue.git. If you cannot reproduce the experiments, I can make a docker file. I also have other examples, but the ones on the github seem to showcase the issue.

Impact: unknown

Other information

When running with translation activate to some mode, it seems like some exceptions do not have the rights' priority for exception. Some exception that should be misaligned addresses appear as other page fault exceptions, which should not be the case, as misaligned exception have higher priority.

If the current behavior is a bug, please provide the steps to reproduce the problem:

What is the current behavior?
Verilator output:

C0:        203 [1] pc=[000000008000014c] W[r 0=0000000080000150][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[0040006f] DASM(0040006f)
C0:        228 [0] pc=[0000000080000150] W[r 0=0000000000000000][0] R[r 1=000000008000896a] R[r 7=ffffffffffffffff] inst=[0070a023] DASM(0070a023)
C0:        253 [1] pc=[0000000080000440] W[r 1=000000000000000f][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[342020f3] DASM(342020f3)

What is the expected behavior?
Spike output:

core   0: >>>>  trigger_bug
core   0: 0x0000000080000150 (0x0070a023) sw      t2, 0(ra)
core   0: exception trap_store_address_misaligned, epc 0x0000000080000150
core   0:           tval 0x000000008000896a
(spike) 
core   0: >>>>  $xrv64i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0
core   0: 0x0000000080000440 (0x342020f3) csrr    ra, mcause
(spike) reg 0 ra
0x0000000000000006

Please, reach out if you need more information, like the chip setup I use or some waveforms,
Best,
Quentin :)

Please tell us about your environment:

• latest release of verilator and rocket

[zhangkanqi]

According to the spec, it's not a bug but a different implementation between Spike and Rocket.