From feed73c1c19fea49b7b10dd450a07218643ab93f Mon Sep 17 00:00:00 2001 From: Michael Norris <108370498+Nitsirks@users.noreply.github.com> Date: Tue, 20 Feb 2024 09:36:50 -0800 Subject: [PATCH] User/dev/michnorris/reg file x check (#400) * adding assertion for x check on all hwif in structs in rdl reg files * updating script to find reset name and include it in assertion * fixing script to use hard reset or powergood for assertion if it's found * fixing script to look for pwrgood instead of power * updating script again, error_reset_b is another name used for pwrgood/hard reset --------- Co-authored-by: Michael Norris --- src/datavault/rtl/dv_reg.sv | 3 +++ src/doe/rtl/doe_reg.sv | 3 +++ src/ecc/rtl/ecc_reg.sv | 3 +++ src/hmac/rtl/hmac_reg.sv | 3 +++ src/keyvault/rtl/kv_reg.sv | 3 +++ src/pcrvault/rtl/pv_reg.sv | 3 +++ src/sha256/rtl/sha256_reg.sv | 3 +++ src/sha512/rtl/sha512_reg.sv | 3 +++ src/soc_ifc/rtl/mbox_csr.sv | 3 +++ src/soc_ifc/rtl/sha512_acc_csr.sv | 3 +++ src/soc_ifc/rtl/soc_ifc_reg.sv | 3 +++ tools/scripts/rdl_post_process.py | 15 +++++++++++++++ 12 files changed, 48 insertions(+) diff --git a/src/datavault/rtl/dv_reg.sv b/src/datavault/rtl/dv_reg.sv index ded8e5d15..25a53d3aa 100644 --- a/src/datavault/rtl/dv_reg.sv +++ b/src/datavault/rtl/dv_reg.sv @@ -480,4 +480,7 @@ module dv_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.hard_reset_b) + endmodule \ No newline at end of file diff --git a/src/doe/rtl/doe_reg.sv b/src/doe/rtl/doe_reg.sv index 2f567cc7f..aefc74748 100644 --- a/src/doe/rtl/doe_reg.sv +++ b/src/doe/rtl/doe_reg.sv @@ -1408,4 +1408,7 @@ module doe_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.cptra_pwrgood) + endmodule \ No newline at end of file diff --git a/src/ecc/rtl/ecc_reg.sv b/src/ecc/rtl/ecc_reg.sv index 212ad6d15..b267ae09d 100644 --- a/src/ecc/rtl/ecc_reg.sv +++ b/src/ecc/rtl/ecc_reg.sv @@ -1813,4 +1813,7 @@ module ecc_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.hard_reset_b) + endmodule \ No newline at end of file diff --git a/src/hmac/rtl/hmac_reg.sv b/src/hmac/rtl/hmac_reg.sv index feabf783e..4a4364f74 100644 --- a/src/hmac/rtl/hmac_reg.sv +++ b/src/hmac/rtl/hmac_reg.sv @@ -2053,4 +2053,7 @@ module hmac_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.error_reset_b) + endmodule \ No newline at end of file diff --git a/src/keyvault/rtl/kv_reg.sv b/src/keyvault/rtl/kv_reg.sv index 56c24360c..4acca90fb 100644 --- a/src/keyvault/rtl/kv_reg.sv +++ b/src/keyvault/rtl/kv_reg.sv @@ -442,4 +442,7 @@ module kv_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.hard_reset_b) + endmodule \ No newline at end of file diff --git a/src/pcrvault/rtl/pv_reg.sv b/src/pcrvault/rtl/pv_reg.sv index d8483f2b2..59e068405 100644 --- a/src/pcrvault/rtl/pv_reg.sv +++ b/src/pcrvault/rtl/pv_reg.sv @@ -293,4 +293,7 @@ module pv_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.hard_reset_b) + endmodule \ No newline at end of file diff --git a/src/sha256/rtl/sha256_reg.sv b/src/sha256/rtl/sha256_reg.sv index d6c9e4749..c9bcba8a9 100644 --- a/src/sha256/rtl/sha256_reg.sv +++ b/src/sha256/rtl/sha256_reg.sv @@ -1425,4 +1425,7 @@ module sha256_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.error_reset_b) + endmodule \ No newline at end of file diff --git a/src/sha512/rtl/sha512_reg.sv b/src/sha512/rtl/sha512_reg.sv index bd97bf079..f462d1093 100644 --- a/src/sha512/rtl/sha512_reg.sv +++ b/src/sha512/rtl/sha512_reg.sv @@ -2024,4 +2024,7 @@ module sha512_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.error_reset_b) + endmodule \ No newline at end of file diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv index cefd5b73d..309a48831 100644 --- a/src/soc_ifc/rtl/mbox_csr.sv +++ b/src/soc_ifc/rtl/mbox_csr.sv @@ -580,4 +580,7 @@ module mbox_csr ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.cptra_rst_b) + endmodule \ No newline at end of file diff --git a/src/soc_ifc/rtl/sha512_acc_csr.sv b/src/soc_ifc/rtl/sha512_acc_csr.sv index 1188e3192..621d38d37 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr.sv @@ -1615,4 +1615,7 @@ module sha512_acc_csr ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.cptra_pwrgood) + endmodule \ No newline at end of file diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index c81364f56..a79a8b00c 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -5683,4 +5683,7 @@ module soc_ifc_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; + +`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.cptra_pwrgood) + endmodule \ No newline at end of file diff --git a/tools/scripts/rdl_post_process.py b/tools/scripts/rdl_post_process.py index 4c86f1091..bf350b2bb 100644 --- a/tools/scripts/rdl_post_process.py +++ b/tools/scripts/rdl_post_process.py @@ -25,6 +25,8 @@ def scrub_line_by_line(fname): mod_cnt = 0 mod_lines = "" + found_hard_reset = None + # Line by line manipulation # Look for unpacked arrays (could be struct arrays or signal arrays) # Look for unpacked struct types @@ -35,6 +37,14 @@ def scrub_line_by_line(fname): has_reg_strb = re.search(r'\bdecoded_reg_strb\b', line) has_unpacked = re.search(r'\[\d+\]', line) has_struct = re.search(r'\bstruct\b\s*(?:unpacked)?', line) + is_endmodule = re.search(r'\bendmodule\b', line) + has_reset = re.search(r'\bnegedge\b', line) + if (has_reset is not None and found_hard_reset is None): + substring = re.search(r"negedge (\w+.\w+)", line) + reset_name = substring.group(1) + # Find the hard reset if it exists + # hard_reset_b, error_reset_b and cptra_pwrgood are used interchangeably + found_hard_reset = re.search(r'hard_reset|pwrgood|error_reset',reset_name) # Skip lines with logic assignments or references to signals; we # only want to scrub signal definitions for unpacked arrays if (has_assign is not None or has_reg_strb is not None): @@ -55,6 +65,11 @@ def scrub_line_by_line(fname): has_unpacked = re.search(r'\[\d+\]', line) mod_lines+=line mod_cnt+=1 + elif (is_endmodule is not None): + mod_lines+="\n" + mod_lines+="`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, " + reset_name + ")\n" + mod_lines+="\n" + mod_lines+=line else: mod_lines+=line #print(f"modified {mod_cnt} lines with unpacked arrays in {fname}")