From fcada04d2d863f63605069515e26f8cfe5fbe074 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Tue, 26 Mar 2024 16:54:55 -0700 Subject: [PATCH] Only look at lower 8-bits when parsing writes to GENERIC_OUTPUT_WIRES in TB --- .../tb/caliptra_top_tb_services.sv | 22 ++++++++--------- .../soc_ifc_env_pkg/src/soc_ifc_predictor.svh | 24 +++++++++---------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv index a3f2582fc..5eaf68bd6 100644 --- a/src/integration/tb/caliptra_top_tb_services.sv +++ b/src/integration/tb/caliptra_top_tb_services.sv @@ -326,19 +326,19 @@ module caliptra_top_tb_services ras_test_ctrl.reset_ooo_done_flag <= 1'b0; ras_test_ctrl.reset_no_lock_done_flag <= 1'b0; end - else if((WriteData == 8'he5) && mailbox_write) begin + else if((WriteData[7:0] == 8'he5) && mailbox_write) begin ras_test_ctrl.do_no_lock_access <= 1'b1; ras_test_ctrl.do_ooo_access <= 1'b0; ras_test_ctrl.reset_ooo_done_flag <= 1'b0; ras_test_ctrl.reset_no_lock_done_flag <= 1'b0; end - else if((WriteData == 8'he6) && mailbox_write) begin + else if((WriteData[7:0] == 8'he6) && mailbox_write) begin ras_test_ctrl.do_no_lock_access <= 1'b0; ras_test_ctrl.do_ooo_access <= 1'b1; ras_test_ctrl.reset_ooo_done_flag <= 1'b0; ras_test_ctrl.reset_no_lock_done_flag <= 1'b0; end - else if ((WriteData == 8'he7) && mailbox_write) begin + else if ((WriteData[7:0] == 8'he7) && mailbox_write) begin ras_test_ctrl.do_no_lock_access <= 1'b0; ras_test_ctrl.do_ooo_access <= 1'b0; ras_test_ctrl.reset_ooo_done_flag <= 1'b1; @@ -631,13 +631,13 @@ endgenerate //IV_NO always@(negedge clk) begin - if((WriteData == 'hf2) && mailbox_write) begin + if((WriteData[7:0] == 8'hf2) && mailbox_write) begin force caliptra_top_dut.soc_ifc_top1.clk_gating_en = 1; end end always@(negedge clk) begin - if ((WriteData == 'he9) && mailbox_write) begin + if ((WriteData[7:0] == 8'he9) && mailbox_write) begin cycleCnt_ff <= cycleCnt; en_jtag_access <= 'b1; end @@ -659,7 +659,7 @@ endgenerate //IV_NO inject_zeroize_to_hmac <= 1'b0; inject_zeroize_to_hmac_cnt <= '0; end - else if((WriteData == 'h99) && mailbox_write) begin + else if((WriteData[7:0] == 8'h99) && mailbox_write) begin inject_zeroize_to_hmac_cmd <= 1'b1; end else if (inject_zeroize_to_hmac_cmd) begin @@ -687,7 +687,7 @@ endgenerate //IV_NO //Inject fatal error after a delay logic inject_fatal_error; always@(negedge clk) begin - if((WriteData == 'heb) && mailbox_write) begin + if((WriteData[7:0] == 8'heb) && mailbox_write) begin cycleCnt_ff <= cycleCnt; inject_fatal_error <= 'b1; end @@ -878,18 +878,18 @@ endgenerate //IV_NO always@(negedge clk) begin - if((WriteData == 'hf5) && mailbox_write) begin + if((WriteData[7:0] == 8'hf5) && mailbox_write) begin cold_rst <= 'b1; rst_cyclecnt <= cycleCnt; end - else if((WriteData == 'hf6) && mailbox_write) begin + else if((WriteData[7:0] == 8'hf6) && mailbox_write) begin warm_rst <= 'b1; rst_cyclecnt <= cycleCnt; end - else if((WriteData == 'hf7) && mailbox_write) begin + else if((WriteData[7:0] == 8'hf7) && mailbox_write) begin timed_warm_rst <= 'b1; end - else if((WriteData == 'hee) && mailbox_write) begin + else if((WriteData[7:0] == 8'hee) && mailbox_write) begin wait_time_to_rst = $urandom_range(5,100); prandom_warm_rst <= 'b1; rst_cyclecnt <= cycleCnt; diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh index e0457ac33..be0a4bd54 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh @@ -1228,28 +1228,28 @@ class soc_ifc_predictor #( end "CPTRA_GENERIC_OUTPUT_WIRES[0]": begin if (ahb_txn.RnW == AHB_WRITE) begin - case (data_active) inside - 32'h0,[32'h2:32'h5],32'h7F,[32'h80:32'hf7]: + case (data_active[7:0]) inside + 8'h0,[8'h2:8'h5],8'h7F,[8'h80:8'hf7]: `uvm_warning("PRED_AHB", $sformatf("Observed write to CPTRA_GENERIC_OUTPUT_WIRES with an unassigned value: 0x%x", data_active)) - 32'h1: + 8'h1: `uvm_fatal("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES to Kill Simulation with Error!") /* TODO put this in the scoreboard? */ - [32'h6:32'h7E]: + [8'h6:8'h7E]: `uvm_info("PRED_AHB", $sformatf("Observed write to CPTRA_GENERIC_OUTPUT_WIRES and translating as ASCII character: %c", data_active[7:0]), UVM_MEDIUM) - 32'hf8: + 8'hf8: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Assert interrupt flags at fixed intervals to wake up halted core]", UVM_MEDIUM) - 32'hf9: + 8'hf9: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Lock debug in security state]", UVM_MEDIUM) - 32'hfa: + 8'hfa: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Unlock debug in security state]", UVM_MEDIUM) - 32'hfb: + 8'hfb: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Set the isr_active bit]", UVM_MEDIUM) - 32'hfc: + 8'hfc: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Clear the isr_active bit]", UVM_MEDIUM) - 32'hfd: + 8'hfd: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Toggle random SRAM single bit flip injection]", UVM_MEDIUM) - 32'hfe: + 8'hfe: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Toggle random SRAM double bit flip injection]", UVM_MEDIUM) - 32'hff: + 8'hff: `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES to End the simulation with a Success status", UVM_LOW) endcase send_soc_ifc_sts_txn = data_active != generic_output_wires[31:0];