From b4737939608166b510d50dbac48996a46384df4f Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Thu, 24 Aug 2023 13:56:15 +0200 Subject: [PATCH 01/19] Add test for Mailbox JTAG accesses with clock gating Internal-tag: [#47908] --- .github/workflows/interactive-debugging.yml | 16 +++ .../test_suites/infinite_loop/common.tcl | 54 +++++++++ .../test_suites/infinite_loop/infinite_loop.s | 24 +++- .../test_suites/infinite_loop/jtag_cg.tcl | 107 ++++++++++++++++++ .../infinite_loop/peripheral_access.tcl | 21 +--- .../infinite_loop/regdump_golden.txt | 2 +- 6 files changed, 204 insertions(+), 20 deletions(-) create mode 100644 src/integration/test_suites/infinite_loop/common.tcl create mode 100644 src/integration/test_suites/infinite_loop/jtag_cg.tcl diff --git a/.github/workflows/interactive-debugging.yml b/.github/workflows/interactive-debugging.yml index 570323a50..8415e094d 100644 --- a/.github/workflows/interactive-debugging.yml +++ b/.github/workflows/interactive-debugging.yml @@ -315,3 +315,19 @@ jobs: ${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \ -f board/caliptra-verilator-rst.cfg \ -f ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop/peripheral_access.tcl + + - name: Build Verilated simulation + run: | + export CALIPTRA_ROOT=$(pwd) + rm -rf run/* + make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 \ + OBJCACHE="" CC=gcc CXX=g++ LINK=g++ + make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex TESTNAME=infinite_loop + + - name: Test JTAG access with clock gating + run: | + export CALIPTRA_ROOT=$(pwd) + cd run + ${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \ + -f board/caliptra-verilator.cfg \ + -f ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop/jtag_cg.tcl diff --git a/src/integration/test_suites/infinite_loop/common.tcl b/src/integration/test_suites/infinite_loop/common.tcl new file mode 100644 index 000000000..a95351407 --- /dev/null +++ b/src/integration/test_suites/infinite_loop/common.tcl @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +proc compare {x y} { + puts "'$x' vs. '$y'" + + if {[llength $y] != [llength $y]} { + puts "length mismatch!" + return -1 + } + + for {set i 0} {$i < [llength $x]} {incr i} { + if {[lindex $x $i] != [lindex $y $i]} { + puts "item $i mismatch!" + return -1 + } + } + + return 0 +} + +set STDOUT 0x300300cc + +set mbox_clk_gate_en 0xf2 +set mbox_lock_debug 0xf9 +set mbox_unlock_debug 0xfa + +set mbox_lock_mem_addr 0x30020000 +set mbox_user_mem_addr 0x30020004 +set mbox_cmd_mem_addr 0x30020008 +set mbox_dlen_mem_addr 0x3002000C +set mbox_datain_mem_addr 0x30020010 +set mbox_dataout_mem_addr 0x30020014 +set mbox_execute_mem_addr 0x30020018 +set mbox_status_mem_addr 0x3002001C +set mbox_unlock_mem_addr 0x30020020 + +set mbox_dlen_dmi_addr 0x50 +set mbox_dout_dmi_addr 0x51 +set mbox_status_dmi_addr 0x52 + +set dmstatus_addr 0x11 + diff --git a/src/integration/test_suites/infinite_loop/infinite_loop.s b/src/integration/test_suites/infinite_loop/infinite_loop.s index 4a3753157..fae20f79c 100644 --- a/src/integration/test_suites/infinite_loop/infinite_loop.s +++ b/src/integration/test_suites/infinite_loop/infinite_loop.s @@ -17,6 +17,13 @@ #include "caliptra_defines.h" .set mfdc, 0x7f9 +.set mfdht, 0x7ce +.set mstatus, 0x300 +.set mitcnt0, 0x7d2 +.set mitb0, 0x7d3 +.set mitctl0, 0x7d4 +.set mie, 0x304 +.set mpmc, 0x7c6 // Code to execute .section .text @@ -39,6 +46,7 @@ _start: li x6, 0xA0A0A0A0 li x7, 0x00FF00FF li x8, 0xCC00CC00 + li s1, 0xFEEDABED // Writing 0 to this register initiates CPU halt // Simple infinite loop program with inner and outer loop li t3, 0 @@ -46,9 +54,23 @@ outer: addi t3, t3, 1 li t4, 123 inner: + beq s1, zero, halt_cpu addi t4, t4, -1 bne t4, zero, inner - jal x0, outer + j outer + +halt_cpu: + // Set mit0 and halt core + li t5, 0xf0 + li t6, 0x20000800 + csrwi mitcnt0, 0x00 // Internal timer 0 counter + csrw mitb0, t5 // Internal timer 0 boundary + csrwi mitctl0, 0x01 // Internal timer 0 enable + csrw mie, t6 // Internal timer 0 local interrupt enable + csrwi mstatus, 0x08 // Internal timer 0 global interrupt enable + csrwi mpmc, 0x03 // Initiate core halt with disable on mit0 interrupt + li s1, 0xFEEDABED // Indicate halt init + j outer // Return to infinite loop .section .dccm .global stdout diff --git a/src/integration/test_suites/infinite_loop/jtag_cg.tcl b/src/integration/test_suites/infinite_loop/jtag_cg.tcl new file mode 100644 index 000000000..037e3c178 --- /dev/null +++ b/src/integration/test_suites/infinite_loop/jtag_cg.tcl @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +init + +set script_dir [file dirname [info script]] +source [file join $script_dir common.tcl] + +array set data { + 0 0x12345678 + 1 0xABBACDDC + 2 0xDEADBEEF + 3 0xFEEDBABE + 4 0xBEACCAEB +} +set dlen_words [array size data] +set dlen_bytes [expr {$dlen_words * 4}] + +puts "Read Debug Module Status Register..." +set val [riscv dmi_read $dmstatus_addr] +puts "dmstatus: $val" +if {($val & 0x00000c00) == 0} { + echo "The hart is halted!" + shutdown error +} +puts "" + +riscv set_mem_access sysbus +puts "Enable clock gating..." +write_memory $STDOUT 32 $mbox_clk_gate_en phys + +puts "Set debug security state to locked..." +write_memory $STDOUT 32 $mbox_lock_debug phys +puts "" + +puts "Retrieve mailbox lock..." +set golden {0x0} +set actual [read_memory $mbox_lock_mem_addr 32 1 phys] +if {[compare $actual $golden] != 0} { + shutdown error +} +puts "" + +puts "Write few bytes to mailbox..." +write_memory $mbox_cmd_mem_addr 32 0x12345678 phys +write_memory $mbox_dlen_mem_addr 32 $dlen_bytes phys +for {set i 0} {$i < $dlen_words} {incr i} { + write_memory $mbox_datain_mem_addr 32 $data($i) phys +} +write_memory $mbox_execute_mem_addr 32 1 phys +puts "" + +puts "Read mailbox status..." +set golden {0x100} +set actual [read_memory $mbox_status_mem_addr 32 1 phys] +if {[compare $actual $golden] != 0} { + shutdown error +} +puts "" + +puts "Halt CPU to access its registers..." +halt +puts "Initiate firmware halt (set register s1 to 0)..." +set_reg {s1 0} +puts "Resume CPU..." +resume +puts "" + +puts "Read Debug Module Status Register..." +set val [riscv dmi_read $dmstatus_addr] +puts "dmstatus: $val" +if {($val & 0x00000c00) == 0} { + echo "The hart is halted!" + shutdown error +} +puts "" + +puts "Read mailbox status and dlen..." +set golden $dlen_bytes +set actual [riscv dmi_read $mbox_dlen_dmi_addr] +if {[compare $actual $golden] != 0} { + shutdown error +} +puts "" + +puts "Read mailbox data..." +for {set i 0} {$i < $dlen_words} {incr i} { + set golden $data($i) + set actual [riscv dmi_read $mbox_dout_dmi_addr] + if {[compare $actual $golden] != 0} { + shutdown error + } +} + +# Success +shutdown diff --git a/src/integration/test_suites/infinite_loop/peripheral_access.tcl b/src/integration/test_suites/infinite_loop/peripheral_access.tcl index d6bf70d37..c2dbcbc16 100644 --- a/src/integration/test_suites/infinite_loop/peripheral_access.tcl +++ b/src/integration/test_suites/infinite_loop/peripheral_access.tcl @@ -14,28 +14,13 @@ # init -proc compare {x y} { - puts "'$x' vs. '$y'" - - if {[llength $y] != [llength $y]} { - puts "length mismatch!" - return -1 - } - - for {set i 0} {$i < [llength $x]} {incr i} { - if {[lindex $x $i] != [lindex $y $i]} { - puts "item $i mismatch!" - return -1 - } - } - - return 0 -} +set script_dir [file dirname [info script]] +source [file join $script_dir common.tcl] # Manually read dmstatus and check if the core is actually held in external # reset. In the expected state bits anyunavail allrunning anyrunning allhalted # and anyhalted should be cleared. -set val [riscv dmi_read 0x11] +set val [riscv dmi_read $dmstatus_addr] puts "dmstatus: $val" if { ($val & 0x00000F00) != 0 } { diff --git a/src/integration/test_suites/infinite_loop/regdump_golden.txt b/src/integration/test_suites/infinite_loop/regdump_golden.txt index 27196e7d5..b1913bb9d 100644 --- a/src/integration/test_suites/infinite_loop/regdump_golden.txt +++ b/src/integration/test_suites/infinite_loop/regdump_golden.txt @@ -5,7 +5,7 @@ tp 0xdeadbeef 0xdeadbeef t0 0x5050505 84215045 t1 0xa0a0a0a0 -1600085856 t2 0xff00ff 16711935 -s1 0x0 0 +s1 0xfeedabed -17978387 a0 0x0 0 a1 0x0 0 a2 0x0 0 From fa5e334eede1ee2213908c20ec19b61a143273fd Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 3 Nov 2023 19:11:03 +0000 Subject: [PATCH 02/19] Merged PR 132462: [UVM] Fix for regression failure caused by soc_ifc error injection sequence Adjust wait methodology when pausing the rand reg access routine to avoid errant termination of the task and subsequent deadlock Related work items: #584641 --- .../mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh | 1 + ...soc_ifc_env_cptra_mbox_interference_handler_sequence.svh | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh index 87fad7657..028f82379 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh @@ -454,6 +454,7 @@ task soc_ifc_env_cptra_mbox_handler_sequence::report_reg_sts(uvm_status_e reg_st // This prevents further bus transfers from being initiated, so the AHB // sequencer is in a clean state when we kill the ALL_TIME_CONSUMING_TASKS // process. + `uvm_info("CPTRA_MBOX_HANDLER", "in report_reg_sts: waiting due to seq_done = 1", UVM_DEBUG) in_report_reg_sts.wait_off(); end endtask diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh index 76a06bec8..8bb5490d6 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh @@ -141,7 +141,7 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_and_force_u if (inject_force_unlock) begin configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(force_unlock_delay_cycles); halt_rand_reg_accesses.trigger(); - while(rand_reg_axs_proc.status() != process::WAITING) + while(halt_rand_reg_accesses.get_num_waiters() == 0) configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); end else begin @@ -151,7 +151,7 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_and_force_u `uvm_info("CPTRA_MBOX_HANDLER", "Received soc_ifc_err_intr, clearing and (if needed) proceeding to mbox_unlock", UVM_MEDIUM) // Pause rand reg accesses while servicing interrupt halt_rand_reg_accesses.trigger(); - while(rand_reg_axs_proc.status() != process::WAITING) + while(halt_rand_reg_accesses.get_num_waiters() == 0) configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Read and clear any error interrupts reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); @@ -271,7 +271,7 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::burst_random_reg_acce `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize reg AHB transfer in burst_random_reg_accesses") end else begin - `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Doing random AHB access of type %p to %s, which has is_busy(): %d", rand_RnW, regs[reg_select].get_name(), regs[reg_select].is_busy()), UVM_DEBUG) + `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Doing random AHB access of type %p to %s, which has is_busy(): %d", rand_RnW, regs[reg_select].get_name(), regs[reg_select].is_busy()), UVM_FULL) if (rand_RnW == AHB_READ) regs[reg_select].read (rand_sts, rand_data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); else regs[reg_select].write(rand_sts, rand_data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); report_reg_sts(rand_sts, regs[reg_select].get_name()); From 052c39e53e43e426eaf3ea47421de48e3e1fafc1 Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Wed, 8 Nov 2023 01:05:21 +0000 Subject: [PATCH 03/19] Merged PR 133196: KV test content for coverage Added some interleaved operations like writes to random clients during debug/scan modes, after clear/locks, etc. Earlier, only a few of the clients were being exercised. Added a task to randomly select a combination of write clients Related work items: #586448 --- src/keyvault/coverage/keyvault_cov_if.sv | 11 +- src/keyvault/coverage/keyvault_cov_props.sv | 12 +- .../src/kv_rand_debug_test_sequence.svh | 12 ++ .../kv_env_pkg/kv_env_pkg.sv | 1 + .../src/kv_env_debug_off_sequence.svh | 117 ++++++++++++++++++ .../src/kv_env_debug_on_sequence.svh | 35 +----- .../kv_env_pkg/src/kv_env_sequence_base.svh | 115 ++++++++++++++--- .../kv_env_pkg/src/kv_predictor.svh | 72 ++++++++--- .../src/kv_wr_rd_debug_sequence.svh | 104 +++++++++++----- .../kv_env_pkg/src/kv_wr_rd_lock_sequence.svh | 107 ++++++++++------ .../kv_env_pkg/src/kv_wr_rd_sequence.svh | 32 +---- .../kv_rst_pkg/kv_rst_pkg.sv | 2 + .../src/kv_rst_scan_off_sequence.svh | 69 +++++++++++ .../src/kv_rst_scan_on_sequence.svh | 69 +++++++++++ .../src/kv_write_key_entry_sequence.svh | 4 + 15 files changed, 585 insertions(+), 177 deletions(-) create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_off_sequence.svh create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_off_sequence.svh create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh diff --git a/src/keyvault/coverage/keyvault_cov_if.sv b/src/keyvault/coverage/keyvault_cov_if.sv index 6d5020250..40f3c3548 100644 --- a/src/keyvault/coverage/keyvault_cov_if.sv +++ b/src/keyvault/coverage/keyvault_cov_if.sv @@ -25,7 +25,8 @@ interface keyvault_cov_if input logic rst_b, input logic core_only_rst_b, input logic cptra_pwrgood, - input logic debugUnlock_or_scan_mode_switch + input logic debugUnlock_or_scan_mode_switch, + input logic cptra_in_debug_scan_mode ); //Intermediate wires @@ -64,7 +65,7 @@ interface keyvault_cov_if covergroup keyvault_top_cov_grp @(posedge clk); option.per_instance = 1; - debug: coverpoint debugUnlock_or_scan_mode_switch; + debug: coverpoint cptra_in_debug_scan_mode; //debugUnlock_or_scan_mode_switch; //Note: Bit transitions and values for lock_wr, lock_use and clear are covered //in UVM reg coverage. This coverpoint bins the 32-bit lock/clear bus so that @@ -130,8 +131,10 @@ interface keyvault_cov_if clear_secretsXkv_write: cross kv_write_en, cp_clear_secrets_wr, cp_clear_secrets_sel; //Cover ahb write/read during crypto write and debug mode unlocked - ahbXkv_write: cross cp_ahb_write, cp_ahb_read, kv_write_en; - ahbXdebug: cross cp_ahb_write, cp_ahb_read, debug; //TODO: maybe not a real use case - revisit + ahb_writeXkv_write: cross cp_ahb_write, kv_write_en; + ahb_writeXdebug: cross cp_ahb_write, debug; + ahb_readXkv_write: cross cp_ahb_read, kv_write_en; + ahb_readXdebug: cross cp_ahb_read, debug; endgroup diff --git a/src/keyvault/coverage/keyvault_cov_props.sv b/src/keyvault/coverage/keyvault_cov_props.sv index ce8d437e9..91ed7d334 100644 --- a/src/keyvault/coverage/keyvault_cov_props.sv +++ b/src/keyvault/coverage/keyvault_cov_props.sv @@ -58,13 +58,13 @@ module keyvault_cov_props //------------------------------------------------------------------------------ property cover_prop_lock_wr_warmrst; @(posedge kv.clk) - (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !kv.rst_b); + ($rose(kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr) |-> ##[0:$] !kv.rst_b); endproperty covprop_lock_wr_warmrst: cover property(cover_prop_lock_wr_warmrst); property cover_prop_lock_use_warmrst; @(posedge kv.clk) - (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !kv.rst_b); + ($rose(kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use) |-> ##[0:$] !kv.rst_b); endproperty covprop_lock_use_warmrst: cover property(cover_prop_lock_use_warmrst); @@ -79,13 +79,13 @@ module keyvault_cov_props //------------------------------------------------------------------------------ property cover_prop_lock_wr_coldrst; @(posedge kv.clk) - (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !kv.cptra_pwrgood); + ($rose(kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr) |-> ##[0:$] !kv.cptra_pwrgood); endproperty covprop_lock_wr_coldrst: cover property(cover_prop_lock_wr_coldrst); property cover_prop_lock_use_coldrst; @(posedge kv.clk) - (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !kv.cptra_pwrgood); + ($rose(kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use) |-> ##[0:$] !kv.cptra_pwrgood); endproperty covprop_lock_use_coldrst: cover property(cover_prop_lock_use_coldrst); @@ -100,13 +100,13 @@ module keyvault_cov_props //------------------------------------------------------------------------------ property cover_prop_lock_wr_corerst; @(posedge kv.clk) - (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !kv.core_only_rst_b); + ($rose(kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr) |-> ##[0:$] !kv.core_only_rst_b); endproperty covprop_lock_wr_corerst: cover property(cover_prop_lock_wr_corerst); property cover_prop_lock_use_corerst; @(posedge kv.clk) - (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !kv.core_only_rst_b); + ($rose(kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use) |-> ##[0:$] !kv.core_only_rst_b); endproperty covprop_lock_use_corerst: cover property(cover_prop_lock_use_corerst); diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh index 2735d0063..7669faa34 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh @@ -68,6 +68,9 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; typedef kv_env_debug_on_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_env_debug_on_sequence_t; rand kv_env_debug_on_sequence_t kv_env_debug_on_seq; + typedef kv_env_debug_off_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_env_debug_off_sequence_t; + rand kv_env_debug_off_sequence_t kv_env_debug_off_seq; + typedef kv_wr_rd_debug_lock_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_lock_sequence_t; rand kv_wr_rd_debug_lock_sequence_t kv_wr_rd_debug_lock_seq; @@ -107,6 +110,7 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; kv_wr_rd_lock_core_rst_seq = kv_wr_rd_lock_core_rst_sequence_t::type_id::create("kv_wr_rd_lock_core_rst_seq"); kv_wr_rd_debug_seq = kv_wr_rd_debug_sequence_t::type_id::create("kv_wr_rd_debug_seq"); kv_env_debug_on_seq = kv_env_debug_on_sequence_t::type_id::create("kv_env_debug_on_seq"); + kv_env_debug_off_seq = kv_env_debug_off_sequence_t::type_id::create("kv_env_debug_off_seq"); kv_wr_rd_debug_lock_seq = kv_wr_rd_debug_lock_sequence_t::type_id::create("kv_wr_rd_debug_lock_seq"); kv_wr_rd_debug_lock_clear_rst_seq = kv_wr_rd_debug_lock_clear_rst_sequence_t::type_id::create("kv_wr_rd_debug_lock_clear_rst_seq"); kv_wr_rd_debug_warm_rst_seq = kv_wr_rd_debug_warm_rst_sequence_t::type_id::create("kv_wr_rd_debug_warm_rst_seq"); @@ -130,6 +134,8 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; `uvm_fatal("KV_AHB_SEQ", "kv_ahb_sequence::body() - kv_ahb_seq randomization failed"); if(!kv_env_debug_on_seq.randomize()) `uvm_fatal("KV_ENV_DEBUG_ON SEQ", "kv_rand_debug_test_sequence::body() - kv_env_debug_on_seq randomization failed"); + if(!kv_env_debug_off_seq.randomize()) + `uvm_fatal("KV_ENV_DEBUG_OFF SEQ", "kv_rand_debug_test_sequence::body() - kv_env_debug_off_seq randomization failed"); reg_model.reset(); `uvm_info("TOP", "AHB stop sequences", UVM_MEDIUM) @@ -144,6 +150,12 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; kv_env_debug_on_seq.start(top_configuration.vsqr); `uvm_info("TOP", "AHB sequence", UVM_MEDIUM) kv_ahb_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "DEBUG OFF sequence", UVM_MEDIUM) + kv_env_debug_off_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "DEBUG + WR/RD sequence",UVM_MEDIUM); + kv_wr_rd_debug_seq.start(top_configuration.vsqr); //has internal scan mode controls + `uvm_info("TOP", "DEBUG on sequence", UVM_MEDIUM) + kv_env_debug_on_seq.start(top_configuration.vsqr); `uvm_info("TOP", "DEBUG lock sequence",UVM_MEDIUM); kv_wr_rd_debug_lock_seq.start(top_configuration.vsqr); `uvm_info("TOP", "DEBUG warm rst sequence",UVM_MEDIUM); diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv index 5d8d7558e..8f729b766 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv @@ -118,6 +118,7 @@ package kv_env_pkg; `include "src/kv_wr_rd_lock_core_rst_sequence.svh" `include "src/kv_wr_rd_debug_sequence.svh" `include "src/kv_env_debug_on_sequence.svh" + `include "src/kv_env_debug_off_sequence.svh" `include "src/kv_wr_rd_debug_lock_sequence.svh" `include "src/kv_wr_rd_debug_lock_clear_rst_sequence.svh" `include "src/kv_wr_rd_debug_warm_rst_sequence.svh" diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_off_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_off_sequence.svh new file mode 100644 index 000000000..c0a475505 --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_off_sequence.svh @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Performs KV writes and reads while randomly issuing debug unlock +// via input pin or CLEAR_SECRETS reg. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class kv_env_debug_off_sequence #( + type CONFIG_T +) extends kv_env_sequence_base #(.CONFIG_T(CONFIG_T)); + + `uvm_object_param_utils(kv_env_debug_off_sequence #(CONFIG_T)); + + typedef kv_rst_poweron_sequence kv_rst_agent_poweron_sequence_t; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq_2; + + typedef kv_rst_debug_sequence kv_rst_agent_debug_sequence_t; + kv_rst_agent_debug_sequence_t kv_rst_agent_debug_seq; + typedef kv_rst_debug_on_sequence kv_rst_agent_debug_on_sequence_t; + kv_rst_agent_debug_on_sequence_t kv_rst_agent_debug_on_seq; + typedef kv_rst_debug_off_sequence kv_rst_agent_debug_off_sequence_t; + kv_rst_agent_debug_off_sequence_t kv_rst_agent_debug_off_seq; + + typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t; + kv_write_agent_key_entry_sequence_t hmac_write_seq; + kv_write_agent_key_entry_sequence_t sha512_write_seq; + kv_write_agent_key_entry_sequence_t ecc_write_seq; + kv_write_agent_key_entry_sequence_t doe_write_seq; + + typedef kv_read_key_entry_sequence kv_read_agent_key_entry_sequence_t; + kv_read_agent_key_entry_sequence_t hmac_key_read_seq; + kv_read_agent_key_entry_sequence_t hmac_block_read_seq; + kv_read_agent_key_entry_sequence_t sha512_block_read_seq; + kv_read_agent_key_entry_sequence_t ecc_privkey_read_seq; + kv_read_agent_key_entry_sequence_t ecc_seed_read_seq; + + rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry; + rand int unsigned wait_cycles_from_seq; + rand bit debug_type; + rand reg [1:0] clear_secrets_data; + + typedef enum {SECURITY_STATE, CLEAR_SECRETS} debug_inputs; + + function new(string name = ""); + super.new(name); + kv_rst_agent_poweron_seq = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV RST poweron seq"); + kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV RST poweron seq"); + + kv_rst_agent_debug_seq = kv_rst_agent_debug_sequence_t::type_id::create("kv_rst_agent_debug_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV RST debug seq"); + kv_rst_agent_debug_on_seq = kv_rst_agent_debug_on_sequence_t::type_id::create("kv_rst_agent_debug_on_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV RST debug on seq"); + kv_rst_agent_debug_off_seq = kv_rst_agent_debug_off_sequence_t::type_id::create("kv_rst_agent_debug_off_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV RST debug off seq"); + + hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV WRITE seq"); + sha512_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("sha512_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV WRITE seq"); + ecc_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("ecc_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV WRITE seq"); + doe_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("doe_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV WRITE seq"); + + hmac_key_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_key_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV READ seq"); + hmac_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV READ seq"); + sha512_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("sha512_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV READ seq"); + ecc_privkey_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_privkey_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV READ seq"); + ecc_seed_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_seed_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_debug_off", "Failed to randomize KV READ seq"); + //kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + endfunction + + virtual task body(); + uvm_status_e sts; + //uvm_reg_data_t rd_data; + int write_entry = 0; + int write_offset = 0; + int read_entry = 0; + int read_offset = 0; + reg [31:0] wr_data, rd_data; + reg_model = configuration.kv_rm; + + + kv_rst_agent_debug_off_seq.start(configuration.kv_rst_agent_config.sequencer); + + endtask +endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh index 08e441629..708b3566f 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh @@ -111,38 +111,7 @@ class kv_env_debug_on_sequence #( reg_model = configuration.kv_rm; - //Issue and wait for reset - // if(configuration.kv_rst_agent_config.sequencer != null) - // kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); - // else - // `uvm_error("KV_ENV_DEBUG_ON", "kv_rst_agent_config.sequencer is null!") - - - //Unlock debug mode or clear secrets randomly - - // std::randomize(debug_type); //0 - security state, 1 - clear secrets - debug_type = 0; - - std::randomize(wait_cycles_from_seq) with { - wait_cycles_from_seq >= 5; - wait_cycles_from_seq <= 100; - }; - - std::randomize(clear_secrets_data); //wren, debug_value0/1 - - //Wait for random delay before starting debug txn - configuration.kv_rst_agent_config.wait_for_num_clocks(wait_cycles_from_seq); - - case(debug_type) - SECURITY_STATE: begin - //start debug seq on rst agent - // kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer); - kv_rst_agent_debug_on_seq.start(configuration.kv_rst_agent_config.sequencer); - end - CLEAR_SECRETS: begin - reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); - assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!") - end - endcase + kv_rst_agent_debug_on_seq.start(configuration.kv_rst_agent_config.sequencer); + endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_sequence_base.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_sequence_base.svh index 66b1b7d84..9af627d82 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_sequence_base.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_sequence_base.svh @@ -35,10 +35,18 @@ class kv_env_sequence_base #( CONFIG_T ) ); + parameter int HMAC_WRITE = 0; + parameter int SHA512_WRITE = 1; + parameter int ECC_WRITE = 2; + parameter int DOE_WRITE = 3; + // Handle to the environments register model // This handle needs to be set before use. kv_reg_model_top reg_model; + rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry; + rand reg [KV_NUM_WRITE-1:0] wr_clients; + // This kv_env_sequence_base contains a handle to a kv_env_configuration object // named configuration. This configuration variable contains a handle to each // sequencer within each agent within this environment and any sub-environments. @@ -65,17 +73,11 @@ class kv_env_sequence_base #( typedef kv_rst_random_sequence kv_rst_agent_random_sequence_t; kv_rst_agent_random_sequence_t kv_rst_agent_rand_seq; - typedef kv_write_random_sequence kv_hmac_write_agent_random_sequence_t; - kv_hmac_write_agent_random_sequence_t kv_hmac_write_agent_rand_seq; - - typedef kv_write_random_sequence kv_sha512_write_agent_random_sequence_t; - kv_sha512_write_agent_random_sequence_t kv_sha512_write_agent_rand_seq; - - typedef kv_write_random_sequence kv_ecc_write_agent_random_sequence_t; - kv_ecc_write_agent_random_sequence_t kv_ecc_write_agent_rand_seq; - - typedef kv_write_random_sequence kv_doe_write_agent_random_sequence_t; - kv_doe_write_agent_random_sequence_t kv_doe_write_agent_rand_seq; + typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t; + kv_write_agent_key_entry_sequence_t hmac_write_seq; + kv_write_agent_key_entry_sequence_t sha512_write_seq; + kv_write_agent_key_entry_sequence_t ecc_write_seq; + kv_write_agent_key_entry_sequence_t doe_write_seq; typedef kv_read_random_sequence kv_hmac_key_read_agent_random_sequence_t; kv_hmac_key_read_agent_random_sequence_t kv_hmac_key_read_agent_rand_seq; @@ -101,10 +103,14 @@ class kv_env_sequence_base #( function new(string name = "" ); super.new(name); kv_rst_agent_rand_seq = kv_rst_agent_random_sequence_t::type_id::create("kv_rst_agent_rand_seq"); - kv_hmac_write_agent_rand_seq = kv_hmac_write_agent_random_sequence_t::type_id::create("kv_hmac_write_agent_rand_seq"); - kv_sha512_write_agent_rand_seq = kv_sha512_write_agent_random_sequence_t::type_id::create("kv_sha512_write_agent_rand_seq"); - kv_ecc_write_agent_rand_seq = kv_ecc_write_agent_random_sequence_t::type_id::create("kv_ecc_write_agent_rand_seq"); - kv_doe_write_agent_rand_seq = kv_doe_write_agent_random_sequence_t::type_id::create("kv_doe_write_agent_rand_seq"); + hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq"); + sha512_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("sha512_write_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq"); + ecc_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("ecc_write_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq"); + doe_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("doe_write_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq"); kv_hmac_key_read_agent_rand_seq = kv_hmac_key_read_agent_random_sequence_t::type_id::create("kv_hmac_key_read_agent_rand_seq"); kv_hmac_block_read_agent_rand_seq = kv_hmac_block_read_agent_random_sequence_t::type_id::create("kv_hmac_block_read_agent_rand_seq"); kv_sha512_block_read_agent_rand_seq = kv_sha512_block_read_agent_random_sequence_t::type_id::create("kv_sha512_block_read_agent_rand_seq"); @@ -114,18 +120,89 @@ class kv_env_sequence_base #( endfunction +virtual task gen_rand_entries(); + std::randomize(hmac_write_entry) with { + hmac_write_entry != sha512_write_entry; + hmac_write_entry != ecc_write_entry; + hmac_write_entry != doe_write_entry; + }; + + std::randomize(sha512_write_entry) with { + sha512_write_entry != hmac_write_entry; + sha512_write_entry != ecc_write_entry; + sha512_write_entry != doe_write_entry; + }; + + std::randomize(ecc_write_entry) with { + ecc_write_entry != hmac_write_entry; + ecc_write_entry != sha512_write_entry; + ecc_write_entry != doe_write_entry; + }; + + std::randomize(doe_write_entry) with { + doe_write_entry != hmac_write_entry; + doe_write_entry != sha512_write_entry; + doe_write_entry != ecc_write_entry; + }; + +endtask + +virtual task queue_writes(); + + repeat(20) begin + gen_rand_entries(); + std::randomize(wr_clients); + + fork + begin + if (wr_clients[HMAC_WRITE]) begin + `uvm_info("QUEUE_HMAC_WRITE", $sformatf("hmac write with entry = %h", hmac_write_entry), UVM_HIGH) + uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_entry",hmac_write_entry); + hmac_write_seq.start(configuration.kv_hmac_write_agent_config.sequencer); + end + end + begin + if (wr_clients[SHA512_WRITE]) begin + `uvm_info("QUEUE_SHA512_WRITE", $sformatf("sha512 write with entry = %h", sha512_write_entry), UVM_HIGH) + uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_sha512_write_agent.sequencer.sha512_write_seq", "local_write_entry",sha512_write_entry); + sha512_write_seq.start(configuration.kv_sha512_write_agent_config.sequencer); + end + end + begin + if (wr_clients[DOE_WRITE]) begin + `uvm_info("QUEUE_DOE_WRITE", $sformatf("doe write with entry = %h", doe_write_entry), UVM_HIGH) + uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_doe_write_agent.sequencer.doe_write_seq", "local_write_entry",doe_write_entry); + doe_write_seq.start(configuration.kv_doe_write_agent_config.sequencer); + end + end + begin + if (wr_clients[ECC_WRITE]) begin + `uvm_info("QUEUE_ECC_WRITE", $sformatf("ecc write with entry = %h", ecc_write_entry), UVM_HIGH) + uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_ecc_write_agent.sequencer.ecc_write_seq", "local_write_entry",ecc_write_entry); + ecc_write_seq.start(configuration.kv_ecc_write_agent_config.sequencer); + end + end + join + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(100); + end + endtask + virtual task body(); if ( configuration.kv_rst_agent_config.sequencer != null ) repeat (25) kv_rst_agent_rand_seq.start(configuration.kv_rst_agent_config.sequencer); if ( configuration.kv_hmac_write_agent_config.sequencer != null ) - repeat (25) kv_hmac_write_agent_rand_seq.start(configuration.kv_hmac_write_agent_config.sequencer); + repeat (25) hmac_write_seq.start(configuration.kv_hmac_write_agent_config.sequencer); if ( configuration.kv_sha512_write_agent_config.sequencer != null ) - repeat (25) kv_sha512_write_agent_rand_seq.start(configuration.kv_sha512_write_agent_config.sequencer); + repeat (25) sha512_write_seq.start(configuration.kv_sha512_write_agent_config.sequencer); if ( configuration.kv_ecc_write_agent_config.sequencer != null ) - repeat (25) kv_ecc_write_agent_rand_seq.start(configuration.kv_ecc_write_agent_config.sequencer); + repeat (25) ecc_write_seq.start(configuration.kv_ecc_write_agent_config.sequencer); if ( configuration.kv_doe_write_agent_config.sequencer != null ) - repeat (25) kv_doe_write_agent_rand_seq.start(configuration.kv_doe_write_agent_config.sequencer); + repeat (25) doe_write_seq.start(configuration.kv_doe_write_agent_config.sequencer); + if ( configuration.kv_hmac_key_read_agent_config.sequencer != null ) repeat (25) kv_hmac_key_read_agent_rand_seq.start(configuration.kv_hmac_key_read_agent_config.sequencer); if ( configuration.kv_hmac_block_read_agent_config.sequencer != null ) diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh index 4f787c534..caf1fe063 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh @@ -212,6 +212,11 @@ class kv_predictor #( // bit send_hmac_write_txn = 0; bit set_val_ctrl_derived = 0; logic [KV_NUM_KEYS-1:0] val_ctrl_derived_data = 0; + logic [KV_NUM_KEYS-1:0] key_entry_ctrl_we = 0; + + //Set when lock_wr/lock_use is 0 and set by AHB txn. Reset only during reset + logic [KV_NUM_KEYS-1:0] key_ctrl_lock_wr = 0; + logic [KV_NUM_KEYS-1:0] key_ctrl_lock_use = 0; extern function void populate_expected_kv_read_txn(ref kv_sb_ap_output_transaction_t t_expected, kv_read_transaction t_received, string client); extern function void populate_expected_kv_write_txn(ref kv_sb_ap_output_transaction_write_t t_expected, kv_write_transaction t_received); @@ -319,6 +324,8 @@ class kv_predictor #( for(entry = 0; entry < KV_NUM_KEYS; entry++) begin last_dword_written[entry] = 'h0; //Clear last dword on hard rst end + key_ctrl_lock_wr = 'h0; + key_ctrl_lock_use = 'h0; end else if (t.debug_mode | t.scan_mode) begin //Set val_reg to 1 for use in reg predictor @@ -368,6 +375,8 @@ class kv_predictor #( kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry)); kv_reg_data = kv_reg.get_mirrored_value(); end + key_ctrl_lock_wr = 'h0; + key_ctrl_lock_use = 'h0; end //If debug mode was unlocked, set a val register to let reg predictor know @@ -684,6 +693,16 @@ class kv_predictor #( val_ctrl = p_kv_rm.get_reg_by_name("val_ctrl"); val_ctrl_data = val_ctrl.get(); + //Once set, keep lock_wr set until a reset is issued. AHB txn with lock_wr = 0 should not have any effect on the reg + if (data_active[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_wr.get_lsb_pos()]) begin + key_ctrl_lock_wr[entry] = 'b1; + end + + //Once set, keep lock_use set until a reset is issued. AHB txn with lock_use = 0 should not have any effect on the reg + if (data_active[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_use.get_lsb_pos()]) begin + key_ctrl_lock_use[entry] = 'b1; + end + if(data_active[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].clear.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_wr.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_use.get_lsb_pos()] && !val_reg_data[p_kv_rm.val_reg.cptra_in_debug_scan_mode.get_lsb_pos()]) begin val_ctrl_data[entry] = 'b1; //In design, clear is a single pulse reg. This val_ctrl[*] will be reset in kv_reg_predictor // for (int i = 0; i < KV_NUM_KEYS; i++) begin @@ -803,8 +822,8 @@ endclass endfunction function void kv_predictor::populate_expected_kv_write_txn (ref kv_sb_ap_output_transaction_write_t t_expected, kv_write_transaction t_received); - uvm_reg kv_reg, val_ctrl_derived; - uvm_reg_data_t kv_reg_data, val_ctrl_derived_data; + uvm_reg kv_reg, val_ctrl_derived, val_ctrl; + uvm_reg_data_t kv_reg_data, val_ctrl_derived_data, val_ctrl_data; logic lock_use; logic lock_wr; logic clear; @@ -815,12 +834,17 @@ endclass kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",t_received.write_entry)); kv_reg_data = kv_reg.get_mirrored_value(); - lock_wr = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[t_received.write_entry].lock_wr.get_lsb_pos()]; - lock_use = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[t_received.write_entry].lock_use.get_lsb_pos()]; + // lock_wr = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[t_received.write_entry].lock_wr.get_lsb_pos()]; + // lock_use = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[t_received.write_entry].lock_use.get_lsb_pos()]; + lock_wr = key_ctrl_lock_wr[t_received.write_entry]; + lock_use = key_ctrl_lock_use[t_received.write_entry]; val_ctrl_derived = p_kv_rm.get_reg_by_name("val_ctrl_derived"); val_ctrl_derived_data = val_ctrl_derived.get(); + val_ctrl = p_kv_rm.get_reg_by_name("val_ctrl"); + val_ctrl_data = val_ctrl.get(); + //Copy received txn // t_expected = t_received; t_expected.write_en = t_received.write_en; @@ -835,19 +859,28 @@ endclass t_expected.error = 1'b1; `uvm_info("PRED", "Trying to write to a locked reg", UVM_MEDIUM) end - else if (/*this.write_in_progress[t_received.write_entry] &&*/ val_ctrl_derived_data[t_received.write_entry]) begin - t_expected.error = 1'b1; - `uvm_info("PRED","Attempts to clear a reg while write is in progress results in an err", UVM_MEDIUM) - `uvm_info("PRED", $sformatf("Write entry = %0d, val_ctrl_derived_data = %b", t_received.write_entry, val_ctrl_derived_data), UVM_MEDIUM) - end else begin - t_expected.error = 1'b0; - //Keep track of last dword written - last_dword_written[t_received.write_entry] = t_received.write_offset; + key_entry_ctrl_we[t_received.write_entry] = 1'b1; + if (/*this.write_in_progress[t_received.write_entry] &&*/ val_ctrl_derived_data[t_received.write_entry]) begin + t_expected.error = 1'b1; + `uvm_info("PRED","Attempts to clear a reg while write is in progress results in an err", UVM_MEDIUM) + end + else begin + t_expected.error = 1'b0; + //Keep track of last dword written + last_dword_written[t_received.write_entry] = t_received.write_offset; + end end end else begin t_expected.error = 1'b0; + //Reset all bits of val_ctrl_derived except current entry irrespective of locks + this.set_val_ctrl_derived = 'b1; + for (int i = 0; i < KV_NUM_KEYS; i++) begin + this.val_ctrl_derived_data[i] = 0; + key_entry_ctrl_we[i] = 1'b0; + end + end @@ -908,14 +941,23 @@ endclass task kv_predictor::poll_and_run_delay_jobs(); forever begin - while (this.set_val_ctrl_derived) begin + if (this.set_val_ctrl_derived) begin // fork - configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2); - `uvm_info("PRED", "Setting clear field of val_ctrl_derived register", UVM_MEDIUM) + //Delay by 2 clks to match the clear txn reaching predictor by then + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2); //2 + `uvm_info("PRED", $sformatf("Setting clear field of val_ctrl_derived register from %b to %b",p_kv_rm.val_ctrl_derived.get(), this.val_ctrl_derived_data), UVM_FULL) p_kv_rm.val_ctrl_derived.set(this.val_ctrl_derived_data); this.set_val_ctrl_derived = 'b0; // join_none end + else begin + for (int i = 0; i < KV_NUM_KEYS; i++) begin + if (!key_entry_ctrl_we[i]) begin + this.val_ctrl_derived_data[i] = 'b0; //reset clear bit if there's no write_en for it + end + this.set_val_ctrl_derived = 'b1; //update in next clk + end + end configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1); end endtask diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh index 1e7bb375a..a1c2d23ac 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh @@ -44,6 +44,11 @@ class kv_wr_rd_debug_sequence #( typedef kv_rst_debug_off_sequence kv_rst_agent_debug_off_sequence_t; kv_rst_agent_debug_off_sequence_t kv_rst_agent_debug_off_seq; + typedef kv_rst_scan_on_sequence kv_rst_agent_scan_on_sequence_t; + kv_rst_agent_scan_on_sequence_t kv_rst_agent_scan_on_seq; + typedef kv_rst_scan_off_sequence kv_rst_agent_scan_off_sequence_t; + kv_rst_agent_scan_off_sequence_t kv_rst_agent_scan_off_seq; + typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t; kv_write_agent_key_entry_sequence_t hmac_write_seq; kv_write_agent_key_entry_sequence_t sha512_write_seq; @@ -77,6 +82,11 @@ class kv_wr_rd_debug_sequence #( if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST debug on seq"); kv_rst_agent_debug_off_seq = kv_rst_agent_debug_off_sequence_t::type_id::create("kv_rst_agent_debug_off_seq"); if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST debug off seq"); + + kv_rst_agent_scan_on_seq = kv_rst_agent_scan_on_sequence_t::type_id::create("kv_rst_agent_scan_on_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST scan on seq"); + kv_rst_agent_scan_off_seq = kv_rst_agent_scan_off_sequence_t::type_id::create("kv_rst_agent_scan_off_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST scan off seq"); hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq"); if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq"); @@ -110,40 +120,30 @@ class kv_wr_rd_debug_sequence #( reg [31:0] wr_data, rd_data; reg_model = configuration.kv_rm; - - //Issue and wait for reset - // if(configuration.kv_rst_agent_config.sequencer != null) - // kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); - // else - // `uvm_error("KV WR RD", "kv_rst_agent_config.sequencer is null!") - + //Unlock debug mode or clear secrets randomly - //Unlock debug mode or clear secrets randomly - - // std::randomize(debug_type); //0 - security state, 1 - clear secrets - debug_type = 0; - - std::randomize(wait_cycles_from_seq) with { - wait_cycles_from_seq >= 5; - wait_cycles_from_seq <= 100; - }; - - std::randomize(clear_secrets_data); //wren, debug_value0/1 - - //Wait for random delay before starting debug txn - configuration.kv_rst_agent_config.wait_for_num_clocks(wait_cycles_from_seq); - - case(debug_type) - SECURITY_STATE: begin - //start debug seq on rst agent - // kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer); - kv_rst_agent_debug_on_seq.start(configuration.kv_rst_agent_config.sequencer); - end - CLEAR_SECRETS: begin - reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); - assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!") - end - endcase + std::randomize(debug_type); //0 - security state, 1 - clear secrets + // debug_type = 0; + + std::randomize(wait_cycles_from_seq) with { + wait_cycles_from_seq >= 5; + wait_cycles_from_seq <= 100; + }; + std::randomize(clear_secrets_data); //wren, debug_value0/1 + //Wait for random delay before starting debug txn + configuration.kv_rst_agent_config.wait_for_num_clocks(wait_cycles_from_seq); + case(debug_type) + SECURITY_STATE: begin + //start debug seq on rst agent + // kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer); + kv_rst_agent_debug_on_seq.start(configuration.kv_rst_agent_config.sequencer); + kv_rst_agent_debug_off_seq.start(configuration.kv_rst_agent_config.sequencer); + end + CLEAR_SECRETS: begin + reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!") + end + endcase fork begin @@ -177,5 +177,43 @@ class kv_wr_rd_debug_sequence #( configuration.kv_sha512_block_read_agent_config.wait_for_num_clocks(1000); configuration.kv_ecc_privkey_read_agent_config.wait_for_num_clocks(1000); configuration.kv_ecc_seed_read_agent_config.wait_for_num_clocks(1000); + + fork //debug mode + begin + kv_rst_agent_scan_on_seq.start(configuration.kv_rst_agent_config.sequencer); + end + begin + queue_writes(); + //Wait for these writes to finish before setting next CTRL reg to avoid collision (test trying to write to CTRL and predictor trying to read from CTRL) + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(100); + end + join + + fork //clear secrets + begin + repeat(20) begin + std::randomize(clear_secrets_data); //wren, debug_value0/1 + + reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!") + + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(2); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(2); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(2); + end //repeat + end + begin + queue_writes(); + //Wait for these writes to finish before setting next CTRL reg to avoid collision (test trying to write to CTRL and predictor trying to read from CTRL) + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(100); + end + join endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh index 630079dc5..7305ec891 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh @@ -49,13 +49,14 @@ class kv_wr_rd_lock_sequence #( kv_read_agent_key_entry_sequence_t ecc_privkey_read_seq; kv_read_agent_key_entry_sequence_t ecc_seed_read_seq; - rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry; - rand reg[2:0] lock_data; + rand reg[2:0] lock_data; + rand reg [1:0] clear_secrets_data; rand reg [1:0] write_id; rand reg [2:0] read_id; typedef enum {HMAC, SHA512, ECC, DOE} write_agents; typedef enum {HMAC_KEY, HMAC_BLOCK, SHA512_BLOCK, ECC_PRIVKEY, ECC_SEED} read_agents; + // rand reg [KV_NUM_WRITE-1:0] wr_clients; function new(string name = ""); @@ -95,29 +96,7 @@ class kv_wr_rd_lock_sequence #( reg [31:0] wr_data, rd_data; reg_model = configuration.kv_rm; - std::randomize(hmac_write_entry) with { - hmac_write_entry != sha512_write_entry; - hmac_write_entry != ecc_write_entry; - hmac_write_entry != doe_write_entry; - }; - - std::randomize(sha512_write_entry) with { - sha512_write_entry != hmac_write_entry; - sha512_write_entry != ecc_write_entry; - sha512_write_entry != doe_write_entry; - }; - - std::randomize(ecc_write_entry) with { - ecc_write_entry != hmac_write_entry; - ecc_write_entry != sha512_write_entry; - ecc_write_entry != doe_write_entry; - }; - - std::randomize(doe_write_entry) with { - doe_write_entry != hmac_write_entry; - doe_write_entry != sha512_write_entry; - doe_write_entry != ecc_write_entry; - }; + gen_rand_entries(); //Issue and wait for reset if(configuration.kv_rst_agent_config.sequencer != null) @@ -207,22 +186,74 @@ class kv_wr_rd_lock_sequence #( kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); else `uvm_error("KV_WR_RD_LOCK", "kv_rst_agent_config.sequencer is null!") - - //Set each CTRL reg with random lock data - for(int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin - lock_data = $urandom_range(1,7); //Can set one of lock_wr, lock_use, clear or all together - reg_model.kv_reg_rm.KEY_CTRL[write_entry_temp].write(sts, lock_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); - assert(sts == UVM_IS_OK) else `uvm_error("AHB_LOCK_SET", $sformatf("Failed when writing to KEY_CTRL[%d]",write_entry_temp)) - - for (int write_offset_temp = 0; write_offset_temp < KV_NUM_DWORDS; write_offset_temp++) begin - // Construct the transaction - uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_entry",write_entry_temp); - uvm_config_db#(reg [KV_ENTRY_SIZE_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_offset",write_offset_temp); - hmac_write_seq.start(configuration.kv_hmac_write_agent_config.sequencer); + fork + begin + repeat(20) begin + //Set each CTRL reg with random lock data + for(int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin + lock_data = $urandom_range(1,7); //Can set one of lock_wr, lock_use, clear or all together + reg_model.kv_reg_rm.KEY_CTRL[write_entry_temp].write(sts, lock_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("AHB_LOCK_SET", $sformatf("Failed when writing to KEY_CTRL[%d]",write_entry_temp)) + + //Wait for lock settings to go through - design is updated after 1 clk, predictor receives txn after 2 additional clks and flags are updated accordingly + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100);//(3); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100);//(3); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100);//(3); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(100);//(3); end - + end //repeat end + begin + queue_writes(); + //Wait for these writes to finish before setting next CTRL reg to avoid collision (test trying to write to CTRL and predictor trying to read from CTRL) + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(100); + + end + join + + fork + begin + repeat(20) begin + //Set each CTRL reg with random lock data + for(int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin + lock_data = $urandom_range(1,7); //Can set one of lock_wr, lock_use, clear or all together + reg_model.kv_reg_rm.KEY_CTRL[write_entry_temp].write(sts, lock_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("AHB_LOCK_SET", $sformatf("Failed when writing to KEY_CTRL[%d]",write_entry_temp)) + + //Wait for lock settings to go through - design is updated after 1 clk, predictor receives txn after 2 additional clks and flags are updated accordingly + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(3); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(3); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(3); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(3); + end + end //repeat + end + begin + repeat(20) begin + std::randomize(clear_secrets_data); //wren, debug_value0/1 + + reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!") + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(2); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(2); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(2); + end //repeat + end + begin + queue_writes(); + //Wait for these writes to finish before setting next CTRL reg to avoid collision (test trying to write to CTRL and predictor trying to read from CTRL) + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(100); + + end + join endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_sequence.svh index 180059e7f..e12a1ac9f 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_sequence.svh @@ -49,12 +49,6 @@ class kv_wr_rd_sequence #( kv_read_agent_key_entry_sequence_t ecc_privkey_read_seq; kv_read_agent_key_entry_sequence_t ecc_seed_read_seq; - rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry; - //constraint valid_entry {hmac_write_entry != sha512_write_entry != ecc_write_entry != doe_write_entry;} - - - - function new(string name = ""); super.new(name); @@ -93,29 +87,7 @@ class kv_wr_rd_sequence #( int offset = 0; reg [31:0] wr_data, rd_data; - std::randomize(hmac_write_entry) with { - hmac_write_entry != sha512_write_entry; - hmac_write_entry != ecc_write_entry; - hmac_write_entry != doe_write_entry; - }; - - std::randomize(sha512_write_entry) with { - sha512_write_entry != hmac_write_entry; - sha512_write_entry != ecc_write_entry; - sha512_write_entry != doe_write_entry; - }; - - std::randomize(ecc_write_entry) with { - ecc_write_entry != hmac_write_entry; - ecc_write_entry != sha512_write_entry; - ecc_write_entry != doe_write_entry; - }; - - std::randomize(doe_write_entry) with { - doe_write_entry != hmac_write_entry; - doe_write_entry != sha512_write_entry; - doe_write_entry != ecc_write_entry; - }; + gen_rand_entries(); //Issue and wait for reset if(configuration.kv_rst_agent_config.sequencer != null) @@ -193,6 +165,8 @@ class kv_wr_rd_sequence #( end join + + queue_writes(); endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv index 87a6a8f8b..bbdc826c9 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv @@ -81,6 +81,8 @@ package kv_rst_pkg; `include "src/kv_rst_debug_sequence.svh" `include "src/kv_rst_debug_on_sequence.svh" `include "src/kv_rst_debug_off_sequence.svh" + `include "src/kv_rst_scan_on_sequence.svh" + `include "src/kv_rst_scan_off_sequence.svh" `include "src/kv_rst_agent.svh" diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_off_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_off_sequence.svh new file mode 100644 index 000000000..8e0bea9ec --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_off_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the soc_ifc_ctrl transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a soc_ifc_ctrl_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class kv_rst_scan_off_sequence extends kv_rst_sequence_base; + + `uvm_object_utils( kv_rst_scan_off_sequence ) + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + + task body(); + + // Assert debug mode + req=kv_rst_transaction::type_id::create("pwr_req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("KV_RST_SCAN_OFF", "kv_rst_scan_off_sequence::body()-kv_rst_transaction randomization failed") + `uvm_info("KV_RST_SCAN_OFF", "Disabling scan mode", UVM_MEDIUM) + req.set_pwrgood = 1'b1; + req.assert_rst = 1'b0; + req.assert_core_rst = 1'b0; + req.debug_mode = 1'b0; + req.scan_mode = 1'b0; + + finish_item(req); + `uvm_info("KV_RST_SCAN_OFF", {"Response:",req.convert2string()},UVM_MEDIUM) + + + + +endtask + +endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh new file mode 100644 index 000000000..26d9db291 --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the soc_ifc_ctrl transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a soc_ifc_ctrl_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class kv_rst_scan_on_sequence extends kv_rst_sequence_base; + + `uvm_object_utils( kv_rst_scan_on_sequence ) + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + + task body(); + + // Assert debug mode + req=kv_rst_transaction::type_id::create("pwr_req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("KV_RST_SCAN_ON", "kv_rst_scan_on_sequence::body()-kv_rst_transaction randomization failed") + `uvm_info("KV_RST_SCAN_ON", "Enabling scan mode", UVM_MEDIUM) + req.set_pwrgood = 1'b1; + req.assert_rst = 1'b0; + req.assert_core_rst = 1'b0; + req.debug_mode = 1'b0; + req.scan_mode = 1'b1; + + finish_item(req); + `uvm_info("KV_RST_SCAN_ON", {"Response:",req.convert2string()},UVM_MEDIUM) + + + + +endtask + +endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_key_entry_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_key_entry_sequence.svh index a202578d5..fb0b28b66 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_key_entry_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_key_entry_sequence.svh @@ -69,6 +69,7 @@ task body(); if((local_write_entry !== 'x) && (local_write_offset !== 'x)) begin //Use write_entry and write_offset passed in from top level sequence + `uvm_info("KV_WRITE_KEY_ENTRY_SEQ", "Write entry and write offset were set by top level seq", UVM_HIGH) `uvm_do_with(req, { req.write_entry == local_write_entry; req.write_offset == local_write_offset; @@ -76,18 +77,21 @@ task body(); end else if((local_write_entry !== 'x)) begin //Use write entry passed in from top level sequence + `uvm_info("KV_WRITE_KEY_ENTRY_SEQ", "Write entry was set by top level seq", UVM_HIGH) `uvm_do_with(req, { req.write_entry == local_write_entry; }) end else if ((local_write_offset !== 'x)) begin //Use write offset passed in from top level sequence + `uvm_info("KV_WRITE_KEY_ENTRY_SEQ", "Write offset was set by top level seq", UVM_HIGH) `uvm_do_with(req, { req.write_offset == local_write_offset; }) end else begin //Use randomized transaction write entry + `uvm_info("KV_WRITE_KEY_ENTRY_SEQ", "Write entry and write offset were not set by top level seq, randomizing in kv_write_key_entry_seq", UVM_HIGH) `uvm_do(req); end From c3b817d6444dd811c5bc32a1fd614c7c64933c99 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Wed, 8 Nov 2023 03:25:48 +0000 Subject: [PATCH 04/19] Merged PR 132944: UVM val firmware bug fix: solve a possible error race condition * In UVM validation firmware for caliptra_top, fix the mbox_unlock procedure so internal firmware interrupts in the data structure are cleared before asserting mbox_unlock. This allows subsequent errors immediately after the unlock to trigger a whole new error handling flow instead of being masked. Related work items: #585880 --- src/integration/asserts/caliptra_top_sva.sv | 2 ++ .../test_suites/caliptra_rt/caliptra_rt.c | 21 ++++++++++++------- .../test_suites/libs/soc_ifc/soc_ifc.c | 3 +-- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv index b25b88d14..3b0797915 100644 --- a/src/integration/asserts/caliptra_top_sva.sv +++ b/src/integration/asserts/caliptra_top_sva.sv @@ -479,12 +479,14 @@ module caliptra_top_sva wdt_status_t1_check: assert property ( @(posedge `SVA_RDC_CLK) + disable iff (~`SVA_RST) $rose(`WDT_PATH.t1_timeout) |=> $rose(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_WDT_STATUS.t1_timeout.value) ) else $display("SVA ERROR: WDT Status bit not set on t1 expiry!"); wdt_status_t2_check: assert property ( @(posedge `SVA_RDC_CLK) + disable iff (~`SVA_RST) $rose(`WDT_PATH.t2_timeout) |=> $rose(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_WDT_STATUS.t2_timeout.value) ) else $display("SVA ERROR: WDT Status bit not set on t2 expiry!"); diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c index 7cbaccef8..b54dc54fc 100644 --- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c +++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c @@ -333,12 +333,13 @@ void caliptra_rt() { if (fsm_chk == 0xF) { if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) { CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) - VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n"); + VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) prior to servicing\n"); } else { - VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n"); + VPRINTF(ERROR, "After finding an error requiring mailbox reset with force unlock, RT firmware has not received an soc_ifc_err_intr!\n"); SEND_STDOUT_CTRL(0x1); while(1); } + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); // This oftens occurs alongside the cmd_fail bit in error injection tests... if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) { CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) @@ -362,7 +363,11 @@ void caliptra_rt() { ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) // Run the FSM check once more for late-arrival of errors // that may correlate with the observed error interrupt - if (soc_ifc_chk_execute_uc()) { + fsm_chk = soc_ifc_chk_execute_uc(); + if (fsm_chk) { + if (fsm_chk == 0xF) { + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); + } continue; } } @@ -494,12 +499,13 @@ void caliptra_rt() { if (fsm_chk == 0xF) { if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) { CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) - VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n"); + VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) prior to servicing\n"); } else { - VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n"); + VPRINTF(ERROR, "After finding an error requiring mailbox reset with force unlock, RT firmware has not received an soc_ifc_err_intr!\n"); SEND_STDOUT_CTRL(0x1); while(1); } + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); } continue; } @@ -536,12 +542,13 @@ void caliptra_rt() { if (fsm_chk == 0xF) { if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) { CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) - VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n"); + VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) prior to servicing\n"); } else { - VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n"); + VPRINTF(ERROR, "After finding an error requiring mailbox reset with force unlock, RT firmware has not received an soc_ifc_err_intr!\n"); SEND_STDOUT_CTRL(0x1); while(1); } + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); } continue; } diff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c index f3f26b260..c7270fb2d 100644 --- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c +++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c @@ -40,8 +40,7 @@ uint8_t soc_ifc_chk_execute_uc() { VPRINTF(WARNING,"SOC_IFC: Check mbox_status.mbox_fsm_ps found MBOX_IDLE\n"); return 1; } else if (state == MBOX_ERROR) { - VPRINTF(ERROR,"SOC_IFC: Check mbox_status.mbox_fsm_ps found MBOX_ERROR, executing mailbox force-unlock\n"); - lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); + VPRINTF(ERROR,"SOC_IFC: Check mbox_status.mbox_fsm_ps found MBOX_ERROR, mailbox force-unlock needed\n"); return 0xF; } else { VPRINTF(FATAL,"SOC_IFC: Check mbox_status.mbox_fsm_ps found unexpected state 0x%x\n", state); From 86d6ecf715ac890a6eab791e585e78613b078f7f Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 9 Nov 2023 02:28:22 +0000 Subject: [PATCH 05/19] Merged PR 133433: Add SV assertions to uvmf_caliptra_top testbench Add SV assertions to uvmf_caliptra_top testbench Related work items: #586843 --- src/integration/asserts/caliptra_top_sva.sv | 18 ++++++++++++++---- .../uvmf_caliptra_top/config/compile.yml | 2 ++ .../caliptra_top/tb/testbench/hdl_top.sv | 1 + 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv index 3b0797915..cdb92c125 100644 --- a/src/integration/asserts/caliptra_top_sva.sv +++ b/src/integration/asserts/caliptra_top_sva.sv @@ -19,12 +19,17 @@ `include "config_defines.svh" //`include "kv_defines_pkg.sv" //`include "doe_defines_pkg.sv" -`define CPTRA_TOP_PATH caliptra_top_tb.caliptra_top_dut +`ifdef UVMF_CALIPTRA_TOP +`define CPTRA_TB_TOP_NAME hdl_top +`else +`define CPTRA_TB_TOP_NAME caliptra_top_tb +`endif +`define CPTRA_TOP_PATH `CPTRA_TB_TOP_NAME.caliptra_top_dut `define KEYVAULT_PATH `CPTRA_TOP_PATH.key_vault1 `define DOE_INST_PATH `CPTRA_TOP_PATH.doe.doe_inst `define DOE_PATH `DOE_INST_PATH.doe_fsm1 `define DOE_REG_PATH `DOE_INST_PATH.i_doe_reg -`define SERVICES_PATH caliptra_top_tb.tb_services_i +`define SERVICES_PATH `CPTRA_TB_TOP_NAME.tb_services_i `define SHA512_PATH `CPTRA_TOP_PATH.sha512.sha512_inst `define HMAC_PATH `CPTRA_TOP_PATH.hmac.hmac_inst `define ECC_PATH `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i @@ -35,8 +40,13 @@ `define WDT_PATH `SOC_IFC_TOP_PATH.i_wdt `define SVA_RDC_CLK `CPTRA_TOP_PATH.rdc_clk_cg -`define SVA_CLK caliptra_top_tb.core_clk -`define SVA_RST caliptra_top_tb.cptra_rst_b +`ifdef UVMF_CALIPTRA_TOP + `define SVA_CLK `CPTRA_TB_TOP_NAME.clk + `define SVA_RST `CPTRA_TB_TOP_NAME.soc_ifc_subenv_soc_ifc_ctrl_agent_bus.cptra_rst_b +`else + `define SVA_CLK `CPTRA_TB_TOP_NAME.core_clk + `define SVA_RST `CPTRA_TB_TOP_NAME.cptra_rst_b +`endif module caliptra_top_sva import doe_defines_pkg::*; diff --git a/src/integration/uvmf_caliptra_top/config/compile.yml b/src/integration/uvmf_caliptra_top/config/compile.yml index 50326aaf1..e57f5cf60 100644 --- a/src/integration/uvmf_caliptra_top/config/compile.yml +++ b/src/integration/uvmf_caliptra_top/config/compile.yml @@ -15,6 +15,7 @@ provides: [uvmf_caliptra_top] schema_version: 2.4.0 requires: - uvmf_caliptra_top_vip + - asserts - caliptra_top - sha512_coverage - sha256_coverage @@ -57,6 +58,7 @@ global: default: - '-assert svaext' - +define+CLP_ASSERT_ON + - +define+UVMF_CALIPTRA_TOP #- '-v2k_generate' #- '-timescale=1ns/1ps' - '-noinherit_timescale=1ns/1ps' diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv index 3084672f4..ed10cc6da 100644 --- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv +++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv @@ -372,6 +372,7 @@ import uvmf_base_pkg_hdl::*; .int_flag(int_flag) ); + caliptra_top_sva sva(); // pragma uvmf custom dut_instantiation end initial begin // tbx vif_binding_block From 7c49c8c41f799a54e74d5909976a68a8de1a5119 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 10 Nov 2023 06:24:46 +0000 Subject: [PATCH 06/19] Merged PR 133575: Remove top port TODO comments * Remove TODO comments from the top portlist in caliptra_top * Resolves https://github.com/chipsalliance/caliptra-rtl/issues/284 * Fix uvmf_caliptra_top compilation with the iTRNG option by including the UVMF_CALIPTRA_TOP define (for SVA usage). * Add generated UVM compilation file lists (.vf) * The compilation file lists should provide clarity regarding https://github.com/chipsalliance/caliptra-rtl/issues/265 Related work items: #587032, #587095 --- src/aes/config/aes.vf | 1 - src/aes/config/aes_pkg.vf | 1 - src/ahb_lite_bus/config/ahb_lite_bus.vf | 1 - src/caliptra_prim/config/caliptra_prim.vf | 1 - src/caliptra_prim/config/caliptra_prim_pkg.vf | 1 - .../config/caliptra_prim_generic.vf | 1 - src/csrng/config/csrng.vf | 1 - src/csrng/config/csrng_pkg.vf | 1 - src/csrng/config/csrng_tb.vf | 1 - src/datavault/config/datavault.vf | 1 - src/datavault/config/dv_defines_pkg.vf | 1 - src/datavault/config/dv_uvm_pkg.vf | 1 - src/doe/config/doe_cbc_tb.vf | 1 - src/doe/config/doe_core_cbc_tb.vf | 1 - src/doe/config/doe_ctrl.vf | 1 - src/doe/config/doe_defines_pkg.vf | 1 - src/ecc/config/ecc_montgomerymultiplier_tb.vf | 1 - src/ecc/config/ecc_top.vf | 1 - src/ecc/config/ecc_top_tb.vf | 1 - src/ecc/uvmf_ecc/config/uvmf_ecc.vf | 173 +++++++ src/edn/config/edn_pkg.vf | 1 - src/entropy_src/config/entropy_src.vf | 1 - src/entropy_src/config/entropy_src_pkg.vf | 1 - src/entropy_src/config/entropy_src_tb.vf | 1 - src/hmac/config/hmac_ctrl.vf | 1 - src/hmac/config/hmac_ctrl_tb.vf | 1 - src/hmac/uvmf_2022/config/uvmf_hmac.vf | 146 ++++++ src/hmac_drbg/config/hmac_drbg.vf | 1 - src/hmac_drbg/config/hmac_drbg_tb.vf | 1 - src/integration/asserts/config/asserts.vf | 1 - src/integration/config/caliptra_top.vf | 1 - .../config/caliptra_top_defines.vf | 1 - src/integration/config/caliptra_top_tb.vf | 1 - .../config/caliptra_top_trng_tb.vf | 1 - src/integration/rtl/caliptra_top.sv | 4 +- .../uvmf_caliptra_top/config/compile.yml | 1 + .../config/uvmf_caliptra_top.vf | 452 ++++++++++++++++++ .../config/uvmf_caliptra_top_itrng.vf | 452 ++++++++++++++++++ .../config/uvmf_caliptra_top_vip.vf | 168 +++++++ src/keyvault/config/keyvault.vf | 1 - src/keyvault/config/keyvault_cov.vf | 1 - src/keyvault/config/kv_defines_pkg.vf | 1 - src/keyvault/config/kv_uvm_pkg.vf | 1 - src/keyvault/uvmf_kv/config/uvmf_kv.vf | 127 +++++ src/kmac/config/kmac.vf | 1 - src/kmac/config/kmac_pkg.vf | 1 - src/lc_ctrl/config/lc_ctrl_pkg.vf | 1 - src/libs/config/libs.vf | 1 - src/libs/config/mvc_lib.vf | 18 + src/libs/config/uvm_lib.vf | 3 + src/libs/config/uvmf_lib.vf | 64 +++ src/pcrvault/config/pcrvault.vf | 1 - src/pcrvault/config/pcrvault_cov.vf | 1 - src/pcrvault/config/pv_defines_pkg.vf | 1 - src/pcrvault/config/pv_uvm_pkg.vf | 1 - src/pcrvault/uvmf_pv/config/uvmf_pv.vf | 125 +++++ .../veer_el2/config/el2_veer_pkg.vf | 1 - .../veer_el2/config/el2_veer_wrapper.vf | 1 - .../veer_el2/config/el2_veer_wrapper_tb.vf | 1 - src/sha256/config/sha256_ctrl.vf | 1 - src/sha256/config/sha256_ctrl_tb.vf | 1 - src/sha256/config/sha256_random_test.vf | 1 - src/sha512/config/sha512_ctrl.vf | 1 - src/sha512/config/sha512_ctrl_32bit_tb.vf | 1 - src/sha512/uvmf_sha512/config/uvmf_sha512.vf | 135 ++++++ .../config/sha512_masked_core.vf | 1 - .../config/sha512_masked_core_tb.vf | 1 - src/soc_ifc/config/soc_ifc_pkg.vf | 1 - src/soc_ifc/config/soc_ifc_tb.vf | 1 - src/soc_ifc/config/soc_ifc_top.vf | 1 - src/soc_ifc/config/soc_ifc_uvm_pkg.vf | 1 - .../uvmf_soc_ifc/config/uvmf_soc_ifc.vf | 178 +++++++ .../uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf | 166 +++++++ src/spi_host/config/spi_host.vf | 1 - src/spi_host/config/spi_host_tb.vf | 1 - src/spi_host/config/spiflash.vf | 1 - src/uart/config/uart.vf | 1 - src/uart/config/uart_tb.vf | 1 - 78 files changed, 2209 insertions(+), 66 deletions(-) create mode 100644 src/ecc/uvmf_ecc/config/uvmf_ecc.vf create mode 100644 src/hmac/uvmf_2022/config/uvmf_hmac.vf create mode 100644 src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf create mode 100644 src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf create mode 100644 src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf create mode 100644 src/keyvault/uvmf_kv/config/uvmf_kv.vf create mode 100644 src/libs/config/mvc_lib.vf create mode 100644 src/libs/config/uvm_lib.vf create mode 100644 src/libs/config/uvmf_lib.vf create mode 100644 src/pcrvault/uvmf_pv/config/uvmf_pv.vf create mode 100644 src/sha512/uvmf_sha512/config/uvmf_sha512.vf create mode 100644 src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf create mode 100644 src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf diff --git a/src/aes/config/aes.vf b/src/aes/config/aes.vf index 97ae18b1e..9592049a5 100644 --- a/src/aes/config/aes.vf +++ b/src/aes/config/aes.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/aes/config/aes_pkg.vf b/src/aes/config/aes_pkg.vf index 4ae176a70..5c75eb1af 100644 --- a/src/aes/config/aes_pkg.vf +++ b/src/aes/config/aes_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/ahb_lite_bus/config/ahb_lite_bus.vf b/src/ahb_lite_bus/config/ahb_lite_bus.vf index 77806285c..86fbbb2e2 100644 --- a/src/ahb_lite_bus/config/ahb_lite_bus.vf +++ b/src/ahb_lite_bus/config/ahb_lite_bus.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl diff --git a/src/caliptra_prim/config/caliptra_prim.vf b/src/caliptra_prim/config/caliptra_prim.vf index 49501fa5e..59740aec8 100644 --- a/src/caliptra_prim/config/caliptra_prim.vf +++ b/src/caliptra_prim/config/caliptra_prim.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/caliptra_prim/config/caliptra_prim_pkg.vf b/src/caliptra_prim/config/caliptra_prim_pkg.vf index 4d5c4720b..dfed9ddd5 100644 --- a/src/caliptra_prim/config/caliptra_prim_pkg.vf +++ b/src/caliptra_prim/config/caliptra_prim_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv diff --git a/src/caliptra_prim_generic/config/caliptra_prim_generic.vf b/src/caliptra_prim_generic/config/caliptra_prim_generic.vf index 29d0649a4..38af67734 100644 --- a/src/caliptra_prim_generic/config/caliptra_prim_generic.vf +++ b/src/caliptra_prim_generic/config/caliptra_prim_generic.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv diff --git a/src/csrng/config/csrng.vf b/src/csrng/config/csrng.vf index 06245ddcc..ef06dd886 100644 --- a/src/csrng/config/csrng.vf +++ b/src/csrng/config/csrng.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/csrng/config/csrng_pkg.vf b/src/csrng/config/csrng_pkg.vf index 6d0386cb0..6badfdba1 100644 --- a/src/csrng/config/csrng_pkg.vf +++ b/src/csrng/config/csrng_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/csrng/rtl ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv diff --git a/src/csrng/config/csrng_tb.vf b/src/csrng/config/csrng_tb.vf index b54328edb..4793e52ec 100644 --- a/src/csrng/config/csrng_tb.vf +++ b/src/csrng/config/csrng_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/datavault/config/datavault.vf b/src/datavault/config/datavault.vf index ef7c7d194..829d888e8 100644 --- a/src/datavault/config/datavault.vf +++ b/src/datavault/config/datavault.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/datavault/rtl diff --git a/src/datavault/config/dv_defines_pkg.vf b/src/datavault/config/dv_defines_pkg.vf index 5caf89c26..e0f236757 100644 --- a/src/datavault/config/dv_defines_pkg.vf +++ b/src/datavault/config/dv_defines_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/datavault/rtl ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv \ No newline at end of file diff --git a/src/datavault/config/dv_uvm_pkg.vf b/src/datavault/config/dv_uvm_pkg.vf index d49e18a4d..16b523f56 100644 --- a/src/datavault/config/dv_uvm_pkg.vf +++ b/src/datavault/config/dv_uvm_pkg.vf @@ -1,3 +1,2 @@ - +incdir+${CALIPTRA_ROOT}/src/datavault/rtl ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_uvm.sv \ No newline at end of file diff --git a/src/doe/config/doe_cbc_tb.vf b/src/doe/config/doe_cbc_tb.vf index 57c5ab16d..343b1bc45 100644 --- a/src/doe/config/doe_cbc_tb.vf +++ b/src/doe/config/doe_cbc_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/doe/config/doe_core_cbc_tb.vf b/src/doe/config/doe_core_cbc_tb.vf index 4f252f2ab..be61bb115 100644 --- a/src/doe/config/doe_core_cbc_tb.vf +++ b/src/doe/config/doe_core_cbc_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/doe/config/doe_ctrl.vf b/src/doe/config/doe_ctrl.vf index 0b25365b2..09ff0b298 100644 --- a/src/doe/config/doe_ctrl.vf +++ b/src/doe/config/doe_ctrl.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/doe/config/doe_defines_pkg.vf b/src/doe/config/doe_defines_pkg.vf index a2f3e9ab8..2bd3dd260 100644 --- a/src/doe/config/doe_defines_pkg.vf +++ b/src/doe/config/doe_defines_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/doe/rtl ${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv ${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv \ No newline at end of file diff --git a/src/ecc/config/ecc_montgomerymultiplier_tb.vf b/src/ecc/config/ecc_montgomerymultiplier_tb.vf index 03ff15a97..0754d8f22 100644 --- a/src/ecc/config/ecc_montgomerymultiplier_tb.vf +++ b/src/ecc/config/ecc_montgomerymultiplier_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/ecc/config/ecc_top.vf b/src/ecc/config/ecc_top.vf index 2af9e7727..51e02138b 100644 --- a/src/ecc/config/ecc_top.vf +++ b/src/ecc/config/ecc_top.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/ecc/config/ecc_top_tb.vf b/src/ecc/config/ecc_top_tb.vf index 7c34bdeb3..ea081512c 100644 --- a/src/ecc/config/ecc_top_tb.vf +++ b/src/ecc/config/ecc_top_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/ecc/uvmf_ecc/config/uvmf_ecc.vf b/src/ecc/uvmf_ecc/config/uvmf_ecc.vf new file mode 100644 index 000000000..f53355d1a --- /dev/null +++ b/src/ecc/uvmf_ecc/config/uvmf_ecc.vf @@ -0,0 +1,173 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/ecc/coverage ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/../rtl ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/../../libs/rtl ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/src ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/src ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/environment_packages/ECC_env_pkg ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/tests ++incdir+${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl ++incdir+${CALIPTRA_ROOT}/src/ecc/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/ECC_in_pkg_hdl.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/ECC_in_pkg.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/src/ECC_in_driver_bfm.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/src/ECC_in_if.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/src/ECC_in_monitor_bfm.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/ECC_out_pkg_hdl.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/ECC_out_pkg.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/src/ECC_out_driver_bfm.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/src/ECC_out_if.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/src/ECC_out_monitor_bfm.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/environment_packages/ECC_env_pkg/ECC_env_pkg.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/parameters/ECC_parameters_pkg.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/sequences/ECC_sequences_pkg.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/tests/ECC_tests_pkg.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_lfsr.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv +${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg.sv +${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg_lfsr.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_defines_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_params_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_top.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_scalar_blinding.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_hmac_drbg_interface.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_arith_unit.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_ram_tdp_file.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_fau.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_montgomerymultiplier.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_first.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_final.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_mult_dsp.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_add_sub_mod_alter.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv \ No newline at end of file diff --git a/src/edn/config/edn_pkg.vf b/src/edn/config/edn_pkg.vf index 3da7239ed..cc750fdb6 100644 --- a/src/edn/config/edn_pkg.vf +++ b/src/edn/config/edn_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/edn/rtl ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv diff --git a/src/entropy_src/config/entropy_src.vf b/src/entropy_src/config/entropy_src.vf index d27b6f989..f8a916e71 100644 --- a/src/entropy_src/config/entropy_src.vf +++ b/src/entropy_src/config/entropy_src.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/entropy_src/config/entropy_src_pkg.vf b/src/entropy_src/config/entropy_src_pkg.vf index 21d2f59ff..8d4b48b40 100644 --- a/src/entropy_src/config/entropy_src_pkg.vf +++ b/src/entropy_src/config/entropy_src_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv diff --git a/src/entropy_src/config/entropy_src_tb.vf b/src/entropy_src/config/entropy_src_tb.vf index 895ea5b5d..f0f720b91 100644 --- a/src/entropy_src/config/entropy_src_tb.vf +++ b/src/entropy_src/config/entropy_src_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/hmac/config/hmac_ctrl.vf b/src/hmac/config/hmac_ctrl.vf index f4b3c6952..666c3371f 100644 --- a/src/hmac/config/hmac_ctrl.vf +++ b/src/hmac/config/hmac_ctrl.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/hmac/config/hmac_ctrl_tb.vf b/src/hmac/config/hmac_ctrl_tb.vf index ac588c35c..1ca5eaa69 100644 --- a/src/hmac/config/hmac_ctrl_tb.vf +++ b/src/hmac/config/hmac_ctrl_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/hmac/uvmf_2022/config/uvmf_hmac.vf b/src/hmac/uvmf_2022/config/uvmf_hmac.vf new file mode 100644 index 000000000..a11f61ac2 --- /dev/null +++ b/src/hmac/uvmf_2022/config/uvmf_hmac.vf @@ -0,0 +1,146 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/coverage ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/../rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/../../libs/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg/src ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg/src ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/environment_packages/HMAC_env_pkg ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/tests ++incdir+${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg/HMAC_in_pkg_hdl.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg/HMAC_in_pkg.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg/src/HMAC_in_driver_bfm.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg/src/HMAC_in_if.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg/src/HMAC_in_monitor_bfm.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg/HMAC_out_pkg_hdl.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg/HMAC_out_pkg.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg/src/HMAC_out_driver_bfm.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg/src/HMAC_out_if.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg/src/HMAC_out_monitor_bfm.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/verification_ip/environment_packages/HMAC_env_pkg/HMAC_env_pkg.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/parameters/HMAC_parameters_pkg.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/sequences/HMAC_sequences_pkg.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/tests/HMAC_tests_pkg.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_lfsr.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv \ No newline at end of file diff --git a/src/hmac_drbg/config/hmac_drbg.vf b/src/hmac_drbg/config/hmac_drbg.vf index 1c00130ee..2e7367213 100644 --- a/src/hmac_drbg/config/hmac_drbg.vf +++ b/src/hmac_drbg/config/hmac_drbg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/hmac_drbg/config/hmac_drbg_tb.vf b/src/hmac_drbg/config/hmac_drbg_tb.vf index 96d3675d1..9754c6784 100644 --- a/src/hmac_drbg/config/hmac_drbg_tb.vf +++ b/src/hmac_drbg/config/hmac_drbg_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/integration/asserts/config/asserts.vf b/src/integration/asserts/config/asserts.vf index af9a0394b..9e5fd10c5 100644 --- a/src/integration/asserts/config/asserts.vf +++ b/src/integration/asserts/config/asserts.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl +incdir+${CALIPTRA_ROOT}/src/integration/asserts diff --git a/src/integration/config/caliptra_top.vf b/src/integration/config/caliptra_top.vf index c25142575..44074db29 100644 --- a/src/integration/config/caliptra_top.vf +++ b/src/integration/config/caliptra_top.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/integration/config/caliptra_top_defines.vf b/src/integration/config/caliptra_top_defines.vf index c60a9363b..32aaeaef2 100644 --- a/src/integration/config/caliptra_top_defines.vf +++ b/src/integration/config/caliptra_top_defines.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh diff --git a/src/integration/config/caliptra_top_tb.vf b/src/integration/config/caliptra_top_tb.vf index b303a45c9..7848871bc 100644 --- a/src/integration/config/caliptra_top_tb.vf +++ b/src/integration/config/caliptra_top_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl +incdir+${CALIPTRA_ROOT}/src/integration/asserts diff --git a/src/integration/config/caliptra_top_trng_tb.vf b/src/integration/config/caliptra_top_trng_tb.vf index de2fbc67c..52c42d8ff 100644 --- a/src/integration/config/caliptra_top_trng_tb.vf +++ b/src/integration/config/caliptra_top_trng_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl +incdir+${CALIPTRA_ROOT}/src/integration/asserts diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index b72538605..1965d4350 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -40,7 +40,7 @@ module caliptra_top input logic jtag_tck, // JTAG clk input logic jtag_tms, // JTAG TMS input logic jtag_tdi, // JTAG tdi - input logic jtag_trst_n, // JTAG Reset //TODO optional needs review + input logic jtag_trst_n, // JTAG Reset output logic jtag_tdo, // JTAG TDO //APB Interface @@ -64,14 +64,12 @@ module caliptra_top output logic [`CALIPTRA_QSPI_IO_WIDTH-1:0] qspi_d_en_o, //UART Interface - // TODO: Determine if this should be set behind a ifdef `ifdef CALIPTRA_INTERNAL_UART output logic uart_tx, input logic uart_rx, `endif //I3C Interface - //TODO update with I3C interface signals // Caliptra Memory Export Interface el2_mem_if.veer_sram_src el2_mem_export, diff --git a/src/integration/uvmf_caliptra_top/config/compile.yml b/src/integration/uvmf_caliptra_top/config/compile.yml index e57f5cf60..a2f5c1c7e 100644 --- a/src/integration/uvmf_caliptra_top/config/compile.yml +++ b/src/integration/uvmf_caliptra_top/config/compile.yml @@ -104,6 +104,7 @@ global: default: - '-assert svaext' - +define+CLP_ASSERT_ON + - +define+UVMF_CALIPTRA_TOP - '-noinherit_timescale=1ns/1ps' - '+define+CALIPTRA_INTERNAL_TRNG' # Suppress a warning due to calling $fgets as task instead of function diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf new file mode 100644 index 000000000..219eb6217 --- /dev/null +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf @@ -0,0 +1,452 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg ++incdir+${CALIPTRA_ROOT}/src/doe/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/asserts ++incdir+${CALIPTRA_ROOT}/src/datavault/rtl ++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/entropy_src/tb ++incdir+${CALIPTRA_ROOT}/src/csrng/rtl ++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl ++incdir+${CALIPTRA_ROOT}/src/uart/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512/coverage ++incdir+${CALIPTRA_ROOT}/src/sha256/coverage ++incdir+${CALIPTRA_ROOT}/src/hmac/coverage ++incdir+${CALIPTRA_ROOT}/src/ecc/coverage ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage ++incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ++incdir+${CALIPTRA_ROOT}/src/keyvault/coverage ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl ++incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl ++incdir+${CALIPTRA_ROOT}/src/sha256/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl ++incdir+${CALIPTRA_ROOT}/src/ecc/rtl ++incdir+${CALIPTRA_ROOT}/src/kmac/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/edn/rtl ++incdir+${CALIPTRA_ROOT}/src/aes/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/caliptra_top_env_pkg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv +${CALIPTRA_ROOT}/src/integration/asserts/caliptra_top_sva.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_bind.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters/caliptra_top_parameters_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb/caliptra_top_tb_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb/caliptra_veer_sram_export.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb/caliptra_top_tb_services.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_if.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_props.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_bind.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg_pkg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_ctrl.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_decipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_encipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_inv_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_key_mem.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_core_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_fsm.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_lfsr.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv +${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg.sv +${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg_lfsr.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_defines_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_params_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_top.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_scalar_blinding.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_hmac_drbg_interface.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_arith_unit.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_ram_tdp_file.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_fau.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_montgomerymultiplier.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_first.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_final.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_mult_dsp.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_add_sub_mod_alter.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_enable_delay.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_markov_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_watermark_reg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnts_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_adaptp_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_core.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnt_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src.sv +${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_core.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_n.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_p.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_lut.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_columns.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_dom.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sub_bytes.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sel_buf_chk.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_core.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_main_sm.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_upd.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_cmd.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_top.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_gen.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_core.sv +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv \ No newline at end of file diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf new file mode 100644 index 000000000..219eb6217 --- /dev/null +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf @@ -0,0 +1,452 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg ++incdir+${CALIPTRA_ROOT}/src/doe/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/asserts ++incdir+${CALIPTRA_ROOT}/src/datavault/rtl ++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/entropy_src/tb ++incdir+${CALIPTRA_ROOT}/src/csrng/rtl ++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl ++incdir+${CALIPTRA_ROOT}/src/uart/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512/coverage ++incdir+${CALIPTRA_ROOT}/src/sha256/coverage ++incdir+${CALIPTRA_ROOT}/src/hmac/coverage ++incdir+${CALIPTRA_ROOT}/src/ecc/coverage ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage ++incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ++incdir+${CALIPTRA_ROOT}/src/keyvault/coverage ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl ++incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl ++incdir+${CALIPTRA_ROOT}/src/sha256/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl ++incdir+${CALIPTRA_ROOT}/src/ecc/rtl ++incdir+${CALIPTRA_ROOT}/src/kmac/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/edn/rtl ++incdir+${CALIPTRA_ROOT}/src/aes/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/caliptra_top_env_pkg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv +${CALIPTRA_ROOT}/src/integration/asserts/caliptra_top_sva.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_bind.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters/caliptra_top_parameters_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb/caliptra_top_tb_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb/caliptra_veer_sram_export.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb/caliptra_top_tb_services.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_if.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_props.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_bind.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg_pkg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_ctrl.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_decipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_encipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_inv_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_key_mem.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_core_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_fsm.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_lfsr.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv +${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg.sv +${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg_lfsr.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_defines_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_params_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_top.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_scalar_blinding.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_hmac_drbg_interface.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_arith_unit.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_ram_tdp_file.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_fau.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_montgomerymultiplier.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_first.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_final.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_mult_dsp.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_add_sub_mod_alter.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_enable_delay.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_markov_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_watermark_reg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnts_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_adaptp_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_core.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnt_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src.sv +${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_core.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_n.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_p.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_lut.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_columns.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_dom.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sub_bytes.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sel_buf_chk.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_core.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_main_sm.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_upd.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_cmd.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_top.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_gen.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_core.sv +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv \ No newline at end of file diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf new file mode 100644 index 000000000..28e7f44d0 --- /dev/null +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf @@ -0,0 +1,168 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers ++incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv +${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/caliptra_top_env_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv \ No newline at end of file diff --git a/src/keyvault/config/keyvault.vf b/src/keyvault/config/keyvault.vf index bbda10b87..40ef426e3 100644 --- a/src/keyvault/config/keyvault.vf +++ b/src/keyvault/config/keyvault.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/keyvault/config/keyvault_cov.vf b/src/keyvault/config/keyvault_cov.vf index b3eaabf81..b5d6ed794 100644 --- a/src/keyvault/config/keyvault_cov.vf +++ b/src/keyvault/config/keyvault_cov.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/keyvault/coverage ${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv ${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv diff --git a/src/keyvault/config/kv_defines_pkg.vf b/src/keyvault/config/kv_defines_pkg.vf index baa074186..a43072fdf 100644 --- a/src/keyvault/config/kv_defines_pkg.vf +++ b/src/keyvault/config/kv_defines_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh diff --git a/src/keyvault/config/kv_uvm_pkg.vf b/src/keyvault/config/kv_uvm_pkg.vf index 4dfee8f5c..994d2f5a3 100644 --- a/src/keyvault/config/kv_uvm_pkg.vf +++ b/src/keyvault/config/kv_uvm_pkg.vf @@ -1,3 +1,2 @@ - +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_uvm.sv \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/config/uvmf_kv.vf b/src/keyvault/uvmf_kv/config/uvmf_kv.vf new file mode 100644 index 000000000..5d4fe2ce3 --- /dev/null +++ b/src/keyvault/uvmf_kv/config/uvmf_kv.vf @@ -0,0 +1,127 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/coverage ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/tests ++incdir+${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/testbench +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_uvm.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_adapter_functions_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg_hdl.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_driver_bfm.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_if.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_monitor_bfm.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/kv_read_pkg_hdl.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/kv_read_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_driver_bfm.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_if.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_monitor_bfm.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/kv_write_pkg_hdl.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/kv_write_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_driver_bfm.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_if.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_monitor_bfm.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/parameters/kv_parameters_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/kv_sequences_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/tests/kv_tests_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv \ No newline at end of file diff --git a/src/kmac/config/kmac.vf b/src/kmac/config/kmac.vf index b0da634ae..21bfb92e0 100644 --- a/src/kmac/config/kmac.vf +++ b/src/kmac/config/kmac.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/kmac/rtl diff --git a/src/kmac/config/kmac_pkg.vf b/src/kmac/config/kmac_pkg.vf index 00f6c16cf..acf975fa5 100644 --- a/src/kmac/config/kmac_pkg.vf +++ b/src/kmac/config/kmac_pkg.vf @@ -1,3 +1,2 @@ - +incdir+${CALIPTRA_ROOT}/src/kmac/rtl ${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv \ No newline at end of file diff --git a/src/lc_ctrl/config/lc_ctrl_pkg.vf b/src/lc_ctrl/config/lc_ctrl_pkg.vf index e7120d98c..e41a7f442 100644 --- a/src/lc_ctrl/config/lc_ctrl_pkg.vf +++ b/src/lc_ctrl/config/lc_ctrl_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv diff --git a/src/libs/config/libs.vf b/src/libs/config/libs.vf index 90d291bb7..7c0d4c77b 100644 --- a/src/libs/config/libs.vf +++ b/src/libs/config/libs.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh diff --git a/src/libs/config/mvc_lib.vf b/src/libs/config/mvc_lib.vf new file mode 100644 index 000000000..a9d638c24 --- /dev/null +++ b/src/libs/config/mvc_lib.vf @@ -0,0 +1,18 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv \ No newline at end of file diff --git a/src/libs/config/uvm_lib.vf b/src/libs/config/uvm_lib.vf new file mode 100644 index 000000000..c12fb083e --- /dev/null +++ b/src/libs/config/uvm_lib.vf @@ -0,0 +1,3 @@ ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi +${UVM_HOME}/src/uvm_pkg.sv \ No newline at end of file diff --git a/src/libs/config/uvmf_lib.vf b/src/libs/config/uvmf_lib.vf new file mode 100644 index 000000000..6f0182070 --- /dev/null +++ b/src/libs/config/uvmf_lib.vf @@ -0,0 +1,64 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv \ No newline at end of file diff --git a/src/pcrvault/config/pcrvault.vf b/src/pcrvault/config/pcrvault.vf index 673bab586..5e59b1772 100644 --- a/src/pcrvault/config/pcrvault.vf +++ b/src/pcrvault/config/pcrvault.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl diff --git a/src/pcrvault/config/pcrvault_cov.vf b/src/pcrvault/config/pcrvault_cov.vf index 4cf22e5dc..e8172adeb 100644 --- a/src/pcrvault/config/pcrvault_cov.vf +++ b/src/pcrvault/config/pcrvault_cov.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv ${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv diff --git a/src/pcrvault/config/pv_defines_pkg.vf b/src/pcrvault/config/pv_defines_pkg.vf index 7e4f67eea..ab7aa0fd0 100644 --- a/src/pcrvault/config/pv_defines_pkg.vf +++ b/src/pcrvault/config/pv_defines_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl diff --git a/src/pcrvault/config/pv_uvm_pkg.vf b/src/pcrvault/config/pv_uvm_pkg.vf index cb4b5df57..8fb32e123 100644 --- a/src/pcrvault/config/pv_uvm_pkg.vf +++ b/src/pcrvault/config/pv_uvm_pkg.vf @@ -1,3 +1,2 @@ - +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_uvm.sv \ No newline at end of file diff --git a/src/pcrvault/uvmf_pv/config/uvmf_pv.vf b/src/pcrvault/uvmf_pv/config/uvmf_pv.vf new file mode 100644 index 000000000..4092d085e --- /dev/null +++ b/src/pcrvault/uvmf_pv/config/uvmf_pv.vf @@ -0,0 +1,125 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/environment_packages/pv_env_pkg ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/tests ++incdir+${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/testbench +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_uvm.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_bind.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/environment_packages/pv_env_pkg/registers/pv_reg_adapter_functions_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/pv_rst_pkg_hdl.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/pv_rst_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_driver_bfm.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_if.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_monitor_bfm.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/pv_read_pkg_hdl.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/pv_read_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src/pv_read_driver_bfm.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src/pv_read_if.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src/pv_read_monitor_bfm.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/pv_write_pkg_hdl.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/pv_write_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src/pv_write_driver_bfm.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src/pv_write_if.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src/pv_write_monitor_bfm.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/environment_packages/pv_env_pkg/registers/pv_reg_model_top_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/environment_packages/pv_env_pkg/pv_env_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/parameters/pv_parameters_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/sequences/pv_sequences_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/tests/pv_tests_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv \ No newline at end of file diff --git a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf index 95f06cacf..3e3824be2 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv diff --git a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf index 7bcf4091e..da326a7e7 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv diff --git a/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf b/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf index 594ea3a70..146b42520 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl diff --git a/src/sha256/config/sha256_ctrl.vf b/src/sha256/config/sha256_ctrl.vf index f8413b0e9..1a53cf1eb 100644 --- a/src/sha256/config/sha256_ctrl.vf +++ b/src/sha256/config/sha256_ctrl.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl diff --git a/src/sha256/config/sha256_ctrl_tb.vf b/src/sha256/config/sha256_ctrl_tb.vf index 9bc3eb6fd..7889eaad5 100644 --- a/src/sha256/config/sha256_ctrl_tb.vf +++ b/src/sha256/config/sha256_ctrl_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/coverage diff --git a/src/sha256/config/sha256_random_test.vf b/src/sha256/config/sha256_random_test.vf index 0820eeec7..1d5ed66c8 100644 --- a/src/sha256/config/sha256_random_test.vf +++ b/src/sha256/config/sha256_random_test.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/coverage diff --git a/src/sha512/config/sha512_ctrl.vf b/src/sha512/config/sha512_ctrl.vf index 0f4ae2e2c..71a30643d 100644 --- a/src/sha512/config/sha512_ctrl.vf +++ b/src/sha512/config/sha512_ctrl.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/sha512/config/sha512_ctrl_32bit_tb.vf b/src/sha512/config/sha512_ctrl_32bit_tb.vf index 9e274b18d..621c83d2e 100644 --- a/src/sha512/config/sha512_ctrl_32bit_tb.vf +++ b/src/sha512/config/sha512_ctrl_32bit_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/sha512/uvmf_sha512/config/uvmf_sha512.vf b/src/sha512/uvmf_sha512/config/uvmf_sha512.vf new file mode 100644 index 000000000..595312dde --- /dev/null +++ b/src/sha512/uvmf_sha512/config/uvmf_sha512.vf @@ -0,0 +1,135 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512/coverage ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/../rtl ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/../../libs/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg/src ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg/src ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/environment_packages/SHA512_env_pkg ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/tests ++incdir+${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg/SHA512_in_pkg_hdl.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg/SHA512_in_pkg.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg/src/SHA512_in_driver_bfm.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg/src/SHA512_in_if.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg/src/SHA512_in_monitor_bfm.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg/SHA512_out_pkg_hdl.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg/SHA512_out_pkg.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg/src/SHA512_out_driver_bfm.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg/src/SHA512_out_if.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg/src/SHA512_out_monitor_bfm.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/environment_packages/SHA512_env_pkg/SHA512_env_pkg.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/parameters/SHA512_parameters_pkg.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/sequences/SHA512_sequences_pkg.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/tests/SHA512_tests_pkg.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv \ No newline at end of file diff --git a/src/sha512_masked/config/sha512_masked_core.vf b/src/sha512_masked/config/sha512_masked_core.vf index 9816a2017..e9d04af99 100644 --- a/src/sha512_masked/config/sha512_masked_core.vf +++ b/src/sha512_masked/config/sha512_masked_core.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/sha512_masked/config/sha512_masked_core_tb.vf b/src/sha512_masked/config/sha512_masked_core_tb.vf index 10d6ce690..b9fa2a419 100644 --- a/src/sha512_masked/config/sha512_masked_core_tb.vf +++ b/src/sha512_masked/config/sha512_masked_core_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/soc_ifc/config/soc_ifc_pkg.vf b/src/soc_ifc/config/soc_ifc_pkg.vf index c8c03c8da..0ba5a33ba 100644 --- a/src/soc_ifc/config/soc_ifc_pkg.vf +++ b/src/soc_ifc/config/soc_ifc_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv diff --git a/src/soc_ifc/config/soc_ifc_tb.vf b/src/soc_ifc/config/soc_ifc_tb.vf index 0f6d2c09c..55dbfb700 100644 --- a/src/soc_ifc/config/soc_ifc_tb.vf +++ b/src/soc_ifc/config/soc_ifc_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl diff --git a/src/soc_ifc/config/soc_ifc_top.vf b/src/soc_ifc/config/soc_ifc_top.vf index 2367cc6f8..4e1965ce5 100644 --- a/src/soc_ifc/config/soc_ifc_top.vf +++ b/src/soc_ifc/config/soc_ifc_top.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl diff --git a/src/soc_ifc/config/soc_ifc_uvm_pkg.vf b/src/soc_ifc/config/soc_ifc_uvm_pkg.vf index ca9cf8b7e..ef4ec886b 100644 --- a/src/soc_ifc/config/soc_ifc_uvm_pkg.vf +++ b/src/soc_ifc/config/soc_ifc_uvm_pkg.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf new file mode 100644 index 000000000..46168ac64 --- /dev/null +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf @@ -0,0 +1,178 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/parameters ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/parameters/soc_ifc_parameters_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hvl_top.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv \ No newline at end of file diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf new file mode 100644 index 000000000..8f85c734a --- /dev/null +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf @@ -0,0 +1,166 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf ++incdir+${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_slave_params_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv +${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/cptra_status_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv \ No newline at end of file diff --git a/src/spi_host/config/spi_host.vf b/src/spi_host/config/spi_host.vf index 6d7b740ad..1b0661420 100644 --- a/src/spi_host/config/spi_host.vf +++ b/src/spi_host/config/spi_host.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/spi_host/config/spi_host_tb.vf b/src/spi_host/config/spi_host_tb.vf index 9e426f787..687e76aca 100644 --- a/src/spi_host/config/spi_host_tb.vf +++ b/src/spi_host/config/spi_host_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/spi_host/config/spiflash.vf b/src/spi_host/config/spiflash.vf index d08a0f326..6821ad3d0 100644 --- a/src/spi_host/config/spiflash.vf +++ b/src/spi_host/config/spiflash.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/uart/config/uart.vf b/src/uart/config/uart.vf index e352155c7..469205a79 100644 --- a/src/uart/config/uart.vf +++ b/src/uart/config/uart.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/uart/config/uart_tb.vf b/src/uart/config/uart_tb.vf index 78eb779e6..4332da0e6 100644 --- a/src/uart/config/uart_tb.vf +++ b/src/uart/config/uart_tb.vf @@ -1,4 +1,3 @@ - +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl From 1ce9ea6762bfabca6081a268ecd7d207a74ff9e5 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 14 Nov 2023 16:39:56 +0100 Subject: [PATCH 07/19] Update expected mailbox rdptr value Internal-Tag: [#51338] Signed-off-by: Maciej Kurc --- src/integration/test_suites/infinite_loop/jtag_cg.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/integration/test_suites/infinite_loop/jtag_cg.tcl b/src/integration/test_suites/infinite_loop/jtag_cg.tcl index 037e3c178..26d6f6888 100644 --- a/src/integration/test_suites/infinite_loop/jtag_cg.tcl +++ b/src/integration/test_suites/infinite_loop/jtag_cg.tcl @@ -62,7 +62,7 @@ write_memory $mbox_execute_mem_addr 32 1 phys puts "" puts "Read mailbox status..." -set golden {0x100} +set golden {0x500} set actual [read_memory $mbox_status_mem_addr 32 1 phys] if {[compare $actual $golden] != 0} { shutdown error From 4a89cff8d79dcb76b93f85f4f3f79b20f446f95e Mon Sep 17 00:00:00 2001 From: Caleb <11879229+calebofearth@users.noreply.github.com> Date: Wed, 15 Nov 2023 15:02:44 -0800 Subject: [PATCH 08/19] Remove I3C interface placeholder comment (#300) --- src/integration/rtl/caliptra_top.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 1965d4350..5f38a406f 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -69,8 +69,6 @@ module caliptra_top input logic uart_rx, `endif - //I3C Interface - // Caliptra Memory Export Interface el2_mem_if.veer_sram_src el2_mem_export, From 986b12ae2a2324fd198b81f88536fcbbd6c6be5c Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 14 Nov 2023 11:12:38 +0100 Subject: [PATCH 09/19] Remove support for JTAG read IDCODE instruction from VeeR TAP Internal-Tag: [#51306] Signed-off-by: Maciej Kurc --- src/integration/rtl/caliptra_top.sv | 5 ----- src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v | 2 -- src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v | 14 +------------- src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv | 2 -- src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv | 5 ----- 5 files changed, 1 insertion(+), 27 deletions(-) diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 3937626d9..353e7320e 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -354,16 +354,12 @@ end // RTL instance //=========================================================================- //FIXME TIE OFFS -logic [31:0] jtag_id; logic [31:0] reset_vector; logic [31:0] nmi_vector; logic nmi_int; logic soft_int; logic timer_int; -assign jtag_id[31:28] = 4'b1; -assign jtag_id[27:12] = '0; -assign jtag_id[11:1] = 11'h45; assign reset_vector = `RV_RESET_VEC; assign soft_int = 1'b0; @@ -415,7 +411,6 @@ el2_veer_wrapper rvtop ( .rst_vec ( reset_vector[31:1]), .nmi_int ( nmi_int ), .nmi_vec ( nmi_vector[31:1]), - .jtag_id ( jtag_id[31:1]), .haddr ( ic_haddr ), .hburst ( ic_hburst ), diff --git a/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v b/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v index d9fd74104..39fdccde2 100644 --- a/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v +++ b/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v @@ -34,7 +34,6 @@ module dmi_wrapper( // Processor Signals input core_rst_n, // Core reset input core_clk, // Core clock - input [31:1] jtag_id, // JTAG ID input [31:0] rd_data, // 32 bit Read data from Processor output [31:0] reg_wr_data, // 32 bit Write data to Processor output [6:0] reg_wr_addr, // 7 bit reg address to Processor @@ -70,7 +69,6 @@ module dmi_wrapper( .idle(3'h0), // no need to wait to sample data .dmi_stat(2'b0), // no need to wait or error possible .version(4'h1), // debug spec 0.13 compliant - .jtag_id(jtag_id), .dmi_hard_reset(dmi_hard_reset), .dmi_reset(dmireset) ); diff --git a/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v b/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v index 2553575ff..ef872999f 100644 --- a/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v +++ b/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v @@ -37,13 +37,6 @@ output reg dmi_hard_reset, input [2:0] idle, input [1:0] dmi_stat, -/* --- revisionCode : 4'h0; --- manufacturersIdCode : 11'h45; --- deviceIdCode : 16'h0001; --- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB] -*/ -input [31:1] jtag_id, input [3:0] version ); @@ -67,7 +60,6 @@ wire pause_ir ; wire update_ir ; wire capture_ir; wire[1:0] dr_en; -wire devid_sel; wire [5:0] abits; assign abits = AWIDTH[5:0]; @@ -143,7 +135,6 @@ always @ (negedge tck or negedge trst) begin end -assign devid_sel = ir == 5'b00001; assign dr_en[0] = ir == 5'b10000; assign dr_en[1] = ir == 5'b10001; @@ -166,9 +157,7 @@ always_comb begin shift_dr: begin case(1) dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]}; - - dr_en[0], - devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; + dr_en[0]: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass endcase end @@ -177,7 +166,6 @@ always_comb begin case(1) dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version}; dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status}; - devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1}; endcase end shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]}; diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv index cec4d24cf..d7d1d3841 100755 --- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv @@ -33,7 +33,6 @@ import soc_ifc_pkg::*; input logic [31:1] rst_vec, input logic nmi_int, input logic [31:1] nmi_vec, - input logic [31:1] jtag_id, output logic [31:0] trace_rv_i_insn_ip, @@ -724,7 +723,6 @@ import soc_ifc_pkg::*; // Processor Signals .core_rst_n (dbg_rst_l), // Debug reset, active low .core_clk (clk), // Core clock - .jtag_id (jtag_id), // JTAG ID .rd_data (dmi_reg_rdata_PostQ), // Read data from Processor .reg_wr_data (dmi_reg_wdata), // Write data to Processor .reg_wr_addr (dmi_reg_addr), // Write address to Processor diff --git a/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv b/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv index d979631e8..889c3735a 100755 --- a/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv +++ b/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv @@ -28,7 +28,6 @@ module el2_veer_wrapper_tb ( input bit core_clk ); logic [31:0] reset_vector; logic [31:0] nmi_vector; - logic [31:1] jtag_id; logic [31:0] ic_haddr ; logic [2:0] ic_hburst ; @@ -411,9 +410,6 @@ module el2_veer_wrapper_tb ( input bit core_clk ); abi_reg[30] = "t5"; abi_reg[31] = "t6"; // tie offs - jtag_id[31:28] = 4'b1; - jtag_id[27:12] = '0; - jtag_id[11:1] = 11'h45; reset_vector = `RV_RESET_VEC; nmi_vector = 32'hee000000; nmi_int = 0; @@ -448,7 +444,6 @@ el2_veer_wrapper rvtop ( .rst_vec ( reset_vector[31:1]), .nmi_int ( nmi_int ), .nmi_vec ( nmi_vector[31:1]), - .jtag_id ( jtag_id[31:1]), `ifdef RV_BUILD_AHB_LITE .haddr ( ic_haddr ), From cf4903dbb222467fabb5a2d80a843fe2b673a252 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 14 Nov 2023 12:06:35 +0100 Subject: [PATCH 10/19] Remove expected IDCODE from OpenOCD config Internal-Tag: [#51306] Signed-off-by: Maciej Kurc --- tools/scripts/openocd/target/veer-el2-rst.cfg | 8 +------- tools/scripts/openocd/target/veer-el2.cfg | 8 +------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/tools/scripts/openocd/target/veer-el2-rst.cfg b/tools/scripts/openocd/target/veer-el2-rst.cfg index 0f4c86fde..c90f24266 100644 --- a/tools/scripts/openocd/target/veer-el2-rst.cfg +++ b/tools/scripts/openocd/target/veer-el2-rst.cfg @@ -4,13 +4,7 @@ if { [info exists CHIPNAME] } { set _CHIPNAME riscv } -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1000008b -} - -jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME tap -irlen 5 set _TARGETNAME $_CHIPNAME.tap target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread diff --git a/tools/scripts/openocd/target/veer-el2.cfg b/tools/scripts/openocd/target/veer-el2.cfg index 45374886d..a8c092f2a 100644 --- a/tools/scripts/openocd/target/veer-el2.cfg +++ b/tools/scripts/openocd/target/veer-el2.cfg @@ -4,13 +4,7 @@ if { [info exists CHIPNAME] } { set _CHIPNAME riscv } -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1000008b -} - -jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME tap -irlen 5 set _TARGETNAME $_CHIPNAME.tap target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread From eeb0a57affb43fdb0160c43638602da4ca90b40e Mon Sep 17 00:00:00 2001 From: Caleb <11879229+calebofearth@users.noreply.github.com> Date: Wed, 22 Nov 2023 13:23:37 -0800 Subject: [PATCH 11/19] [README] Update VCS steps (#308) * Update VCS steps with instructions to copy test vector generator * Add Makefile VCS sim step to copy test vector gen scripts * Add steps for running UVM unit tests * VCS instructions for running unit tests --- README.md | 73 ++++++++++++++++++++++++++++++++++++++---- tools/scripts/Makefile | 4 +++ 2 files changed, 70 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index 5b5ade8f8..558ed7be4 100644 --- a/README.md +++ b/README.md @@ -55,7 +55,7 @@ Other: - Playbook (Microsoft Internal workflow management tool) ### **RISCV Toolchain installation** ### -Note that there is significant configurability when installing the RISCV toolchain. +There is significant configurability when installing the RISCV toolchain. These instructions may be used to create a RISCV installation that will be compatible with the provided Makefile for compiling test C programs. @@ -74,7 +74,7 @@ Required for simulation:
`CALIPTRA_ROOT`: Defines the absolute path to the Project repository root (called "Caliptra" or "caliptra-rtl"). Recommended to define as `${CALIPTRA_WORKSPACE}/Caliptra`.
Required for Firmware (i.e. Test suites) makefile:
- `TESTNAME`: Contains the name of one of the tests listed inside the `src/integration/test_suites` folder
+ `TESTNAME`: Contains the name of one of the tests listed inside the `src/integration/test_suites` folder; only used for `caliptra_top_tb` tests
## **Repository Overview** ## ``` @@ -143,20 +143,28 @@ Verilog file lists are generated via VCS and included in the config directory fo ## **Simulation Flow** ## -### VCS Steps: ### +### Caliptra Top VCS Steps: ### 1. Setup tools, add to PATH (ensure riscv64-unknown-elf-gcc is also available) 2. Define all environment variables above - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME - See [Regression Tests](#Regression-Tests) for information about available tests. 3. Create a run folder for build outputs (and cd to it) -4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test. +4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for [iccm_lock](src/integration/test_suites/iccm_lock) test). To do this, copy [iccm_lock.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) to the run directory and rename to `program.hex`. [dccm.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test. 5. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}` - E.g.: `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex` - NOTE: TESTNAME may also be overridden in the makefile command line invocation, e.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=iccm_lock program.hex` 6. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated. -7. Simulate project with `caliptra_top_tb` as the top target +7. Copy the test generator scripts to the run output directory: + - [src/ecc/tb/ecdsa_secp384r1.exe](src/ecc/tb/ecdsa_secp384r1.exe) + * Necessary for [randomized_pcr_signing](src/integration/test_suites/randomized_pcr_signing) + * OPTIONAL otherwise + - [src/doe/tb/doe_test_gen.py](src/doe/tb/doe_test_gen.py) + * Allows use of randomized secret field inputs during testing. + * Required when using the `+RAND_DOE_VALUES` plusarg during simulation + * Also required for several smoke tests that require randomized DOE IV, such as smoke_test_doe_scan, smoke_test_doe_rand, smoke_test_doe_cg +8. Simulate project with `caliptra_top_tb` as the top target -### Verilator Steps: ### +### Caliptra Top Verilator Steps: ### 1. Setup tools, add to PATH (ensure Verilator, GCC, and riscv64-unknown-elf-gcc are available) 2. Define all environment variables above - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME @@ -178,6 +186,18 @@ Verilog file lists are generated via VCS and included in the config directory fo 3. NOTE: The script automatically creates run output folders at `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator//` for each test run 4. NOTE: The output folder is populated with a run log that reports the run results and pass/fail status +### Unit Test VCS Steps: ### +1. Setup tools, add to PATH +1. Define all environment variables above +1. Create a run folder for build outputs (and cd to it) +1. Compile complete project using `src//config/_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated. +1. Copy the test generator scripts or test vectors to the run output directory: + - [src/ecc/tb/test_vectors/mm_test_vectors\*.hex](src/ecc/tb/test_vectors) + * Necessary for [ecc_montgomerymultiplier_tb](src/ecc/tb/ecc_montgomerymultiplier_tb.sv) + - [src/sha256/tb/sha256_test_gen.py](src/sha256/tb/sha256_test_gen.py) + * Necessary for [sha256_random_test](src/sha256/tb/sha256_random_test.sv) +1. Simulate project with `_tb` as the top target + ### UVM Testbench Steps for `caliptra_top`:
**Description**:
@@ -195,15 +215,54 @@ Steps:
1. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf 1. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc` 1. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top` -1. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system +1. ALL compilation steps may be completed by using the file-list found at `src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf` +1. NOTE: `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system 1. Compile the validation firmware (as described in [Regression Tests](#Regression-Tests)) that will run on Caliptra's embedded RISC-V core - The expected output products are `program.hex`, `caliptra_fmc.hex`, `caliptra_rt.hex` and must be placed in the simulation run directory - `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_top program.hex` - `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_fmc caliptra_fmc.hex` - `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_rt caliptra_rt.hex` +1. Copy the test vectors to the run output directory: + - [src/sha512/tb/vectors/SHA\*.rsp](src/sha512/tb/vectors/) + * Required for SHA512 UVM unittest 1. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src` 1. Provide `+UVM_TESTNAME=` argument to simulation +### UVM Unit Test Steps:
+ +**Description**:
+The UVM Framework generation tool was used to create the baseline UVM testbench for verification of each IP component inside Caliptra. The following IP blocks have supported UVM testbenches: +- [ECC](src/ecc/uvmf_ecc) +- [HMAC](src/hmac/uvmf_2022) +- [SHA512](src/sha512/uvmf_sha512) +- [KeyVault](src/keyvault/uvmf_kv) +- [PCRVault](src/pcrvault/uvmf_pv) +- [SOC_IFC](src/soc_ifc/uvmf_soc_ifc) + +**Prerequisites**:
+- QVIP 2021.2.1 for Mentor Graphics (provides the AHB/APB VIP) +- UVM 1.1d installation +- Mentor Graphics UVM-Framework installation + +Steps:
+1. Compile UVM 1.1d library +1. Compile the AHB/APB QVIP source +1. Compile the Mentor Graphics UVM-Frameworks base library +1. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf +1. Compile the `verification_ip` provided for the target testbench +1. ALL compilation steps may be completed by using the file-list found at `src//uvmf_/config/.vf` +1. NOTE: `Caliptra/src//uvmf_/uvmf_template_output/project_benches//tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system +1. Copy the test generator scripts to the run output directory: + - [src/ecc/tb/ecdsa_secp384r1.exe](src/ecc/tb/ecdsa_secp384r1.exe) + * Necessary for ECC unittest + - [src/hmac/tb/test_gen.py](src/hmac/tb/test_gen.py) + * Required for uvmf_hmac unittest + - [src/sha512/tb/vectors/SHA\*.rsp](src/sha512/tb/vectors/) + * Required for SHA512 UVM unittest +1. Select a test to run from the set of tests in `Caliptra/src//uvmf_/uvmf_template_output/project_benches//tb/tests/src` +1. Provide `+UVM_TESTNAME=` argument to simulation + + ## **Regression Tests** ## ### Standalone SystemVerilog Testbench Regression ### diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile index 3a629eb77..f986f38b8 100755 --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -70,6 +70,9 @@ HEADER_FILES := $(INCLUDES_DIR)/caliptra_defines.h \ $(ISR_DIR)/veer-csr.h \ $(foreach comp_lib, $(COMP_LIBS), $(wildcard $(comp_lib)/*.h)) +TEST_GEN_FILES := $(CALIPTRA_ROOT)/src/ecc/tb/ecdsa_secp384r1.exe \ + $(CALIPTRA_ROOT)/src/doe/tb/doe_test_gen.py + # Separate OFILE variable since this is not used to build remote images # (i.e. FMC or RunTime) ifeq (0,$(shell test -e $(TEST_DIR)/$(TESTNAME).c && echo $$?)) @@ -235,6 +238,7 @@ verilator: program.hex verilator-build ./obj_dir/Vcaliptra_top_tb $(VERILATOR_RUN_ARGS) vcs: program.hex vcs-build + cp $(TEST_GEN_FILES) $(BUILD_DIR) ./simv.caliptra_top_tb ############ TEST build ############################### From 63a40f06c414bc67ca981f20cd572c71bff1a735 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 30 Nov 2023 23:58:21 +0100 Subject: [PATCH 12/19] Fix VCS invocation in Makefile so that DPI functions get compiled. (#306) Internal-Tag: [#51415] Signed-off-by: Maciej Kurc --- tools/scripts/Makefile | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) mode change 100755 => 100644 tools/scripts/Makefile diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile old mode 100755 new mode 100644 index 6a7efb724..1b007812f --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -165,33 +165,35 @@ CFLAGS += -std=c++17 # compiles), or -O for balance. VERILATOR_MAKE_FLAGS = OPT_FAST="-Os" -# Testbench libs -VERILATOR_TB_LIBS = jtagdpi/jtagdpi.c \ - tcp_server/tcp_server.c +# Testbench DPI sources +TB_DPI_SRCS = jtagdpi/jtagdpi.c \ + tcp_server/tcp_server.c + +TB_DPI_INCS := $(addprefix -I$(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(dir $(TB_DPI_SRCS))) +TB_DPI_SRCS := $(addprefix $(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(TB_DPI_SRCS)) # Testbench sources -VERILATOR_TB_SRCS = $(TBDIR)/test_caliptra_top_tb.cpp \ - $(addprefix $(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(VERILATOR_TB_LIBS)) +TB_VERILATOR_SRCS = $(TBDIR)/test_caliptra_top_tb.cpp $(TB_DPI_SRCS) # Testbench defs -VERILATOR_TB_DEFS = +define+CALIPTRA_INTERNAL_QSPI+CALIPTRA_INTERNAL_TRNG+CALIPTRA_INTERNAL_UART +TB_DEFS = +define+CALIPTRA_INTERNAL_QSPI+CALIPTRA_INTERNAL_TRNG+CALIPTRA_INTERNAL_UART # By default debugging (JTAG) is locked in Caliptra. Add "DEBUG_UNLOCKED=1" to # enable it. ifdef DEBUG_UNLOCKED - VERILATOR_TB_DEFS += +define+CALIPTRA_DEBUG_UNLOCKED + TB_DEFS += +define+CALIPTRA_DEBUG_UNLOCKED endif # To enforce holding the RISC-V core in reset add "FORCE_CPU_RESET=1". ifdef FORCE_CPU_RESET - VERILATOR_TB_DEFS += +define+CALIPTRA_FORCE_CPU_RESET + TB_DEFS += +define+CALIPTRA_FORCE_CPU_RESET endif # Run time arguments from command line VERILATOR_RUN_ARGS ?= "" # Add testbench lib include paths -CFLAGS += $(addprefix -I$(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(dir $(VERILATOR_TB_LIBS))) +CFLAGS += $(TB_DPI_INCS) # Targets all: clean verilator @@ -207,8 +209,8 @@ clean_fw: ############ Model Builds ############################### -verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(VERILATOR_TB_SRCS) - $(VERILATOR) $(VERILATOR_TB_SRCS) --cc -CFLAGS "$(CFLAGS)" \ +verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_VERILATOR_SRCS) + $(VERILATOR) $(TB_VERILATOR_SRCS) --cc -CFLAGS "$(CFLAGS)" \ +libext+.v+.sv +define+RV_OPENSOURCE \ --timescale 1ns/1ps \ --timing \ @@ -217,16 +219,16 @@ verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(VERILATOR_TB_SRCS) -f $(TBDIR)/../config/caliptra_top_tb.vf --top-module caliptra_top_tb \ -f $(TBDIR)/../config/caliptra_top_tb.vlt \ -exe test_caliptra_top_tb.cpp --autoflush $(VERILATOR_DEBUG) \ - $(VERILATOR_TB_DEFS) + $(TB_DEFS) $(MAKE) -j`nproc` -e -C obj_dir/ -f Vcaliptra_top_tb.mk $(VERILATOR_MAKE_FLAGS) VM_PARALLEL_BUILDS=1 touch verilator-build -vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h +vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_DPI_SRCS) vlogan -full64 -sverilog -kdb -incr_vlogan +lint=IA_CHECKFAIL -assert svaext \ - +define+CLP_ASSERT_ON -noinherit_timescale=1ns/1ps \ + +define+CLP_ASSERT_ON $(TB_DEFS) -noinherit_timescale=1ns/1ps \ -f $(TBDIR)/../config/caliptra_top_tb.vf vcs -full64 -kdb -lca -debug_access+all -j8 +vcs+lic+wait -partcomp -fastpartcomp=j8 \ - -assert enable_hier caliptra_top_tb -o simv.caliptra_top_tb + -assert enable_hier caliptra_top_tb -o simv.caliptra_top_tb +dpi -cflags "$(TB_DPI_INCS)" $(TB_DPI_SRCS) ############ TEST Simulation ############################### From 8173b30c2285656d8498d0d15bc66c814d525b32 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Tue, 14 Nov 2023 20:07:23 +0000 Subject: [PATCH 13/19] Merged PR 133861: Filesystem merge from caliptra-rtl GitHub to MSFT internal Manual filesystem merge from GH repo (Bringing back to GH to include some file modifications - lic headers) Related work items: #587660 --- .../simulation_model/simulation/hmac_main.cpp | 17 +++++++++++++++++ .../simulation_model/simulation/hmac_tests.h | 17 +++++++++++++++++ src/hmac/formal/readme.md | 17 ++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/src/hmac/formal/model/simulation_model/simulation/hmac_main.cpp b/src/hmac/formal/model/simulation_model/simulation/hmac_main.cpp index f702df25f..98d68f0ce 100644 --- a/src/hmac/formal/model/simulation_model/simulation/hmac_main.cpp +++ b/src/hmac/formal/model/simulation_model/simulation/hmac_main.cpp @@ -1,3 +1,20 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Description: +// + #include "systemc.h" #include "Interfaces.h" #include "../../hmac_core.h" diff --git a/src/hmac/formal/model/simulation_model/simulation/hmac_tests.h b/src/hmac/formal/model/simulation_model/simulation/hmac_tests.h index f3e73e917..2dc0ba359 100644 --- a/src/hmac/formal/model/simulation_model/simulation/hmac_tests.h +++ b/src/hmac/formal/model/simulation_model/simulation/hmac_tests.h @@ -1,3 +1,20 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Description: +// + #ifndef HMAC_CORE_TESTS_H #define HMAC_CORE_TESTS_H diff --git a/src/hmac/formal/readme.md b/src/hmac/formal/readme.md index 82a97de80..2418aef3c 100644 --- a/src/hmac/formal/readme.md +++ b/src/hmac/formal/readme.md @@ -1,3 +1,18 @@ +_*SPDX-License-Identifier: Apache-2.0
+
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.*_
+ # HMAC Date: 28-07-2023 Author: LUBIS EDA @@ -67,4 +82,4 @@ cut u_sha512_core_h2.digest The sha512_masked core had been verified separately. By cutting the signal model complexity is drastically reduced. -Feel free to reach out to contact@lubis-eda.com to request the loadscripts. \ No newline at end of file +Feel free to reach out to contact@lubis-eda.com to request the loadscripts. From 3cc699ba637cc2dc24d2eb82ce0a3087bde2d7dd Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 30 Nov 2023 15:44:16 -0800 Subject: [PATCH 14/19] Commit minor tweaks to sync infrastructure with MSFT internal repo (hand-copied) --- src/csrng/config/csrng.vf | 1 - src/riscv_core/veer_el2/config/compile.yml | 2 -- src/soc_ifc/rtl/caliptra_top_reg.h | 2 +- src/uart/config/uart.vf | 1 - tools/scripts/Makefile | 3 --- 5 files changed, 1 insertion(+), 8 deletions(-) diff --git a/src/csrng/config/csrng.vf b/src/csrng/config/csrng.vf index ef06dd886..0a1c5d165 100644 --- a/src/csrng/config/csrng.vf +++ b/src/csrng/config/csrng.vf @@ -102,4 +102,3 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv -${CALIPTRA_ROOT}/src/csrng/tb/csrng_tb.sv diff --git a/src/riscv_core/veer_el2/config/compile.yml b/src/riscv_core/veer_el2/config/compile.yml index ee025269a..dad981819 100755 --- a/src/riscv_core/veer_el2/config/compile.yml +++ b/src/riscv_core/veer_el2/config/compile.yml @@ -24,8 +24,6 @@ targets: rtl: directories: [$COMPILE_ROOT/rtl] files: - - $COMPILE_ROOT/rtl/pic_map_auto.h - - $COMPILE_ROOT/rtl/el2_param.vh - $COMPILE_ROOT/rtl/el2_mem.sv - $COMPILE_ROOT/rtl/el2_dma_ctrl.sv - $COMPILE_ROOT/rtl/el2_pic_ctrl.sv diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index e2c597f16..553225858 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -15,6 +15,7 @@ #ifndef CALIPTRA_TOP_REG_HEADER #define CALIPTRA_TOP_REG_HEADER + #define CALIPTRA_TOP_REG_BASE_ADDR (0x0) #define CALIPTRA_TOP_REG_MBOX_CSR_BASE_ADDR (0x30020000) #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_LOCK (0x30020000) @@ -542,4 +543,3 @@ #endif - diff --git a/src/uart/config/uart.vf b/src/uart/config/uart.vf index 469205a79..5fb62f4db 100644 --- a/src/uart/config/uart.vf +++ b/src/uart/config/uart.vf @@ -63,7 +63,6 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv ${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv -${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv ${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv ${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv ${CALIPTRA_ROOT}/src/uart/rtl/uart.sv diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile index 3a629eb77..955784fc3 100755 --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -16,9 +16,6 @@ PLAYBOOK_RANDOM_SEED ?= $(shell date +%s) BUILD_CFLAGS ?= TEST_CFLAGS = -g -O3 -DMY_RANDOM_SEED=$(PLAYBOOK_RANDOM_SEED) $(BUILD_CFLAGS) - -ABI = -mabi=ilp32 -march=rv32imc - VERILATOR = verilator GCC_PREFIX = riscv64-unknown-elf BUILD_DIR = $(CURDIR) From 38d5fd74ee2c107a3472b77f3ad2c7a679251b62 Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Wed, 15 Nov 2023 19:49:20 +0000 Subject: [PATCH 15/19] Merged PR 134395: KV UVM fixes Addresses regression failures due to test setup issue and last dword clear logic Related work items: #588795 --- .../src/kv_rand_debug_test_sequence.svh | 24 +++- .../kv/tb/tests/src/kv_rand_debug_test.yml | 2 +- .../kv_env_pkg/kv_env_pkg.sv | 2 + .../src/kv_env_scan_off_sequence.svh | 117 ++++++++++++++++++ .../src/kv_env_scan_on_sequence.svh | 108 ++++++++++++++++ .../kv_env_pkg/src/kv_predictor.svh | 13 +- .../src/kv_wr_rd_debug_sequence.svh | 9 +- 7 files changed, 262 insertions(+), 13 deletions(-) create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_off_sequence.svh create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_on_sequence.svh diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh index 7669faa34..307257780 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh @@ -71,6 +71,12 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; typedef kv_env_debug_off_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_env_debug_off_sequence_t; rand kv_env_debug_off_sequence_t kv_env_debug_off_seq; + typedef kv_env_scan_on_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_env_scan_on_sequence_t; + rand kv_env_scan_on_sequence_t kv_env_scan_on_seq; + + typedef kv_env_scan_off_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_env_scan_off_sequence_t; + rand kv_env_scan_off_sequence_t kv_env_scan_off_seq; + typedef kv_wr_rd_debug_lock_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_lock_sequence_t; rand kv_wr_rd_debug_lock_sequence_t kv_wr_rd_debug_lock_seq; @@ -111,6 +117,8 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; kv_wr_rd_debug_seq = kv_wr_rd_debug_sequence_t::type_id::create("kv_wr_rd_debug_seq"); kv_env_debug_on_seq = kv_env_debug_on_sequence_t::type_id::create("kv_env_debug_on_seq"); kv_env_debug_off_seq = kv_env_debug_off_sequence_t::type_id::create("kv_env_debug_off_seq"); + kv_env_scan_on_seq = kv_env_scan_on_sequence_t::type_id::create("kv_env_scan_on_seq"); + kv_env_scan_off_seq = kv_env_scan_off_sequence_t::type_id::create("kv_env_scan_off_seq"); kv_wr_rd_debug_lock_seq = kv_wr_rd_debug_lock_sequence_t::type_id::create("kv_wr_rd_debug_lock_seq"); kv_wr_rd_debug_lock_clear_rst_seq = kv_wr_rd_debug_lock_clear_rst_sequence_t::type_id::create("kv_wr_rd_debug_lock_clear_rst_seq"); kv_wr_rd_debug_warm_rst_seq = kv_wr_rd_debug_warm_rst_sequence_t::type_id::create("kv_wr_rd_debug_warm_rst_seq"); @@ -136,6 +144,10 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; `uvm_fatal("KV_ENV_DEBUG_ON SEQ", "kv_rand_debug_test_sequence::body() - kv_env_debug_on_seq randomization failed"); if(!kv_env_debug_off_seq.randomize()) `uvm_fatal("KV_ENV_DEBUG_OFF SEQ", "kv_rand_debug_test_sequence::body() - kv_env_debug_off_seq randomization failed"); + if(!kv_env_scan_on_seq.randomize()) + `uvm_fatal("KV_ENV_SCAN_ON SEQ", "kv_rand_debug_test_sequence::body() - kv_env_scan_on_seq randomization failed"); + if(!kv_env_scan_off_seq.randomize()) + `uvm_fatal("KV_ENV_SCAN_OFF SEQ", "kv_rand_debug_test_sequence::body() - kv_env_scan_off_seq randomization failed"); reg_model.reset(); `uvm_info("TOP", "AHB stop sequences", UVM_MEDIUM) @@ -148,14 +160,16 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; `uvm_info("TOP", "DEBUG on sequence", UVM_MEDIUM) kv_env_debug_on_seq.start(top_configuration.vsqr); - `uvm_info("TOP", "AHB sequence", UVM_MEDIUM) - kv_ahb_seq.start(top_configuration.vsqr); `uvm_info("TOP", "DEBUG OFF sequence", UVM_MEDIUM) kv_env_debug_off_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "AHB sequence", UVM_MEDIUM) + kv_ahb_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "DEBUG + WR/RD sequence",UVM_MEDIUM); kv_wr_rd_debug_seq.start(top_configuration.vsqr); //has internal scan mode controls - `uvm_info("TOP", "DEBUG on sequence", UVM_MEDIUM) - kv_env_debug_on_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "SCAN on sequence", UVM_MEDIUM) + kv_env_scan_on_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "DEBUG lock sequence",UVM_MEDIUM); kv_wr_rd_debug_lock_seq.start(top_configuration.vsqr); `uvm_info("TOP", "DEBUG warm rst sequence",UVM_MEDIUM); @@ -167,6 +181,8 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; `uvm_info("TOP", "DEBUG lock clear rst sequence",UVM_MEDIUM); kv_wr_rd_debug_lock_clear_rst_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "SCAN OFF sequence", UVM_MEDIUM) + kv_env_scan_off_seq.start(top_configuration.vsqr); if(1) $display("** TESTCASE PASSED"); diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/tests/src/kv_rand_debug_test.yml b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/tests/src/kv_rand_debug_test.yml index 29f7aaa67..3a01eff3f 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/tests/src/kv_rand_debug_test.yml +++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/tests/src/kv_rand_debug_test.yml @@ -1,6 +1,6 @@ --- # Random seed desired... -seed: ${PLAYBOOK_RANDOM_SEED} +seed: ${PLAYBOOK_RANDOM_SEED} plusargs: - '+UVM_TESTNAME=kv_rand_debug_test' testname: kv_rand_debug_test diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv index 8f729b766..0d3e10c8a 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv @@ -119,6 +119,8 @@ package kv_env_pkg; `include "src/kv_wr_rd_debug_sequence.svh" `include "src/kv_env_debug_on_sequence.svh" `include "src/kv_env_debug_off_sequence.svh" + `include "src/kv_env_scan_on_sequence.svh" + `include "src/kv_env_scan_off_sequence.svh" `include "src/kv_wr_rd_debug_lock_sequence.svh" `include "src/kv_wr_rd_debug_lock_clear_rst_sequence.svh" `include "src/kv_wr_rd_debug_warm_rst_sequence.svh" diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_off_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_off_sequence.svh new file mode 100644 index 000000000..c2530046e --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_off_sequence.svh @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Performs KV writes and reads while randomly issuing debug unlock +// via input pin or CLEAR_SECRETS reg. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class kv_env_scan_off_sequence #( + type CONFIG_T +) extends kv_env_sequence_base #(.CONFIG_T(CONFIG_T)); + + `uvm_object_param_utils(kv_env_scan_off_sequence #(CONFIG_T)); + + typedef kv_rst_poweron_sequence kv_rst_agent_poweron_sequence_t; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq_2; + + typedef kv_rst_debug_sequence kv_rst_agent_debug_sequence_t; + kv_rst_agent_debug_sequence_t kv_rst_agent_debug_seq; + typedef kv_rst_debug_on_sequence kv_rst_agent_debug_on_sequence_t; + kv_rst_agent_debug_on_sequence_t kv_rst_agent_debug_on_seq; + typedef kv_rst_scan_off_sequence kv_rst_agent_scan_off_sequence_t; + kv_rst_agent_scan_off_sequence_t kv_rst_agent_scan_off_seq; + + typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t; + kv_write_agent_key_entry_sequence_t hmac_write_seq; + kv_write_agent_key_entry_sequence_t sha512_write_seq; + kv_write_agent_key_entry_sequence_t ecc_write_seq; + kv_write_agent_key_entry_sequence_t doe_write_seq; + + typedef kv_read_key_entry_sequence kv_read_agent_key_entry_sequence_t; + kv_read_agent_key_entry_sequence_t hmac_key_read_seq; + kv_read_agent_key_entry_sequence_t hmac_block_read_seq; + kv_read_agent_key_entry_sequence_t sha512_block_read_seq; + kv_read_agent_key_entry_sequence_t ecc_privkey_read_seq; + kv_read_agent_key_entry_sequence_t ecc_seed_read_seq; + + rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry; + rand int unsigned wait_cycles_from_seq; + rand bit debug_type; + rand reg [1:0] clear_secrets_data; + + typedef enum {SECURITY_STATE, CLEAR_SECRETS} debug_inputs; + + function new(string name = ""); + super.new(name); + kv_rst_agent_poweron_seq = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV RST poweron seq"); + kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV RST poweron seq"); + + kv_rst_agent_debug_seq = kv_rst_agent_debug_sequence_t::type_id::create("kv_rst_agent_debug_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV RST debug seq"); + kv_rst_agent_debug_on_seq = kv_rst_agent_debug_on_sequence_t::type_id::create("kv_rst_agent_debug_on_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV RST debug on seq"); + kv_rst_agent_scan_off_seq = kv_rst_agent_scan_off_sequence_t::type_id::create("kv_rst_agent_scan_off_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV RST debug off seq"); + + hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV WRITE seq"); + sha512_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("sha512_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV WRITE seq"); + ecc_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("ecc_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV WRITE seq"); + doe_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("doe_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV WRITE seq"); + + hmac_key_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_key_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV READ seq"); + hmac_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV READ seq"); + sha512_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("sha512_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV READ seq"); + ecc_privkey_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_privkey_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV READ seq"); + ecc_seed_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_seed_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_scan_off", "Failed to randomize KV READ seq"); + //kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + endfunction + + virtual task body(); + uvm_status_e sts; + //uvm_reg_data_t rd_data; + int write_entry = 0; + int write_offset = 0; + int read_entry = 0; + int read_offset = 0; + reg [31:0] wr_data, rd_data; + reg_model = configuration.kv_rm; + + + kv_rst_agent_scan_off_seq.start(configuration.kv_rst_agent_config.sequencer); + + endtask +endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_on_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_on_sequence.svh new file mode 100644 index 000000000..7c58aac19 --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_scan_on_sequence.svh @@ -0,0 +1,108 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Performs KV writes and reads while randomly issuing debug unlock +// via input pin or CLEAR_SECRETS reg. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class kv_env_scan_on_sequence #( + type CONFIG_T +) extends kv_env_sequence_base #(.CONFIG_T(CONFIG_T)); + + `uvm_object_param_utils(kv_env_scan_on_sequence #(CONFIG_T)); + + typedef kv_rst_poweron_sequence kv_rst_agent_poweron_sequence_t; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq_2; + + typedef kv_rst_debug_sequence kv_rst_agent_debug_sequence_t; + kv_rst_agent_debug_sequence_t kv_rst_agent_debug_seq; + typedef kv_rst_scan_on_sequence kv_rst_agent_scan_on_sequence_t; + kv_rst_agent_scan_on_sequence_t kv_rst_agent_scan_on_seq; + typedef kv_rst_debug_off_sequence kv_rst_agent_debug_off_sequence_t; + kv_rst_agent_debug_off_sequence_t kv_rst_agent_debug_off_seq; + + typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t; + kv_write_agent_key_entry_sequence_t hmac_write_seq; + kv_write_agent_key_entry_sequence_t sha512_write_seq; + kv_write_agent_key_entry_sequence_t ecc_write_seq; + kv_write_agent_key_entry_sequence_t doe_write_seq; + + typedef kv_read_key_entry_sequence kv_read_agent_key_entry_sequence_t; + kv_read_agent_key_entry_sequence_t hmac_key_read_seq; + kv_read_agent_key_entry_sequence_t hmac_block_read_seq; + kv_read_agent_key_entry_sequence_t sha512_block_read_seq; + kv_read_agent_key_entry_sequence_t ecc_privkey_read_seq; + kv_read_agent_key_entry_sequence_t ecc_seed_read_seq; + + rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry; + rand int unsigned wait_cycles_from_seq; + rand bit debug_type; + rand reg [1:0] clear_secrets_data; + + typedef enum {SECURITY_STATE, CLEAR_SECRETS} debug_inputs; + + function new(string name = ""); + super.new(name); + kv_rst_agent_poweron_seq = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV RST poweron seq"); + kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV RST poweron seq"); + + kv_rst_agent_debug_seq = kv_rst_agent_debug_sequence_t::type_id::create("kv_rst_agent_debug_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV RST debug seq"); + kv_rst_agent_scan_on_seq = kv_rst_agent_scan_on_sequence_t::type_id::create("kv_rst_agent_scan_on_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV RST debug on seq"); + kv_rst_agent_debug_off_seq = kv_rst_agent_debug_off_sequence_t::type_id::create("kv_rst_agent_debug_off_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV RST debug off seq"); + + hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV WRITE seq"); + sha512_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("sha512_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV WRITE seq"); + ecc_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("ecc_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV WRITE seq"); + doe_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("doe_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV WRITE seq"); + + hmac_key_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_key_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV READ seq"); + hmac_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV READ seq"); + sha512_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("sha512_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV READ seq"); + ecc_privkey_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_privkey_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV READ seq"); + ecc_seed_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_seed_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_SCAN_ON", "Failed to randomize KV READ seq"); + //kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + endfunction + + virtual task body(); + + kv_rst_agent_scan_on_seq.start(configuration.kv_rst_agent_config.sequencer); + + endtask +endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh index caf1fe063..e1d4146ff 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh @@ -703,15 +703,16 @@ class kv_predictor #( key_ctrl_lock_use[entry] = 'b1; end - if(data_active[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].clear.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_wr.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_use.get_lsb_pos()] && !val_reg_data[p_kv_rm.val_reg.cptra_in_debug_scan_mode.get_lsb_pos()]) begin + // if(data_active[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].clear.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_wr.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_use.get_lsb_pos()] && !val_reg_data[p_kv_rm.val_reg.cptra_in_debug_scan_mode.get_lsb_pos()]) begin + if (data_active[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].clear.get_lsb_pos()] && !key_ctrl_lock_wr[entry] && !key_ctrl_lock_use[entry] && !val_reg_data[p_kv_rm.val_reg.cptra_in_debug_scan_mode.get_lsb_pos()]) begin val_ctrl_data[entry] = 'b1; //In design, clear is a single pulse reg. This val_ctrl[*] will be reset in kv_reg_predictor // for (int i = 0; i < KV_NUM_KEYS; i++) begin this.val_ctrl_derived_data[entry] = 'b1; + last_dword_written[entry] = 'h0; //clear last dword of that entry // this.val_ctrl_derived_data[i] = (i == entry); // end // this.set_val_ctrl_derived = 'b1; //p_kv_rm.kv_reg_rm.kv_val_ctrl.predict(val_ctrl_data); - `uvm_info("PRED", "Setting clear field of val_ctrl register", UVM_MEDIUM) p_kv_rm.val_ctrl.set(val_ctrl_data); //`uvm_info("PRED", "Setting clear field of val_ctrl_derived register", UVM_MEDIUM) @@ -812,9 +813,11 @@ endclass t_expected.error = 'b0; end - if (val_ctrl_data[t_received.read_entry]) begin - last_dword_written[t_received.read_entry] = 'h0; - end + // if (val_ctrl_data[t_received.read_entry]) begin + // if (val_ctrl_derived_data[t_received.read_entry]) begin + // `uvm_info("KNU_DBG","Resetting last_dword because val_ctrl_data is set!", UVM_FULL) + // last_dword_written[t_received.read_entry] = 'h0; + // end t_expected.last = (last_dword_written[t_received.read_entry] == t_received.read_offset); t_expected.read_entry = t_received.read_entry; diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh index a1c2d23ac..319fb1c02 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh @@ -121,7 +121,6 @@ class kv_wr_rd_debug_sequence #( reg_model = configuration.kv_rm; //Unlock debug mode or clear secrets randomly - std::randomize(debug_type); //0 - security state, 1 - clear secrets // debug_type = 0; @@ -144,7 +143,7 @@ class kv_wr_rd_debug_sequence #( assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!") end endcase - + fork begin //Write to all entries @@ -166,7 +165,9 @@ class kv_wr_rd_debug_sequence #( end end end - join + join + + `uvm_info("DEBUG_WR_RD", "Waiting for sha512 write/read to finish", UVM_FULL) configuration.kv_rst_agent_config.wait_for_num_clocks(1000); configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1000); configuration.kv_sha512_write_agent_config.wait_for_num_clocks(1000); @@ -178,6 +179,7 @@ class kv_wr_rd_debug_sequence #( configuration.kv_ecc_privkey_read_agent_config.wait_for_num_clocks(1000); configuration.kv_ecc_seed_read_agent_config.wait_for_num_clocks(1000); + `uvm_info("DEBUG_WR_RD", "Scan mode and queue writes", UVM_FULL) fork //debug mode begin kv_rst_agent_scan_on_seq.start(configuration.kv_rst_agent_config.sequencer); @@ -192,6 +194,7 @@ class kv_wr_rd_debug_sequence #( end join + `uvm_info("DEBUG_WR_RD", "clear_secrets and queue writes", UVM_FULL) fork //clear secrets begin repeat(20) begin From a6226962594cd36bcd6406b8acfe4c5e8d141c80 Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Wed, 15 Nov 2023 23:09:23 +0000 Subject: [PATCH 16/19] Merged PR 134100: Update synthesis script with FC commands Migrate our synthesis setup to fusion compiler NOTE: MSFT internal synthesis flow is used as a pipe-cleaner to check for synthesizability, lint, timing. This may be different from tools used by other Caliptra developers for more rigorous physical analysis. Related work items: #589061 --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 5b5ade8f8..e49e74add 100644 --- a/README.md +++ b/README.md @@ -41,8 +41,8 @@ Simulation: - `2022.3` Synthesis: - - Synopsys DC - - `Version 2020.09-SP1` + - Synopsys Fusion Compiler + - `Version 2022.12-SP3` GCC: - RISCV Toolchain for generating memory initialization files From 340a3cd38de556e4b33b78d23293f32e7e90a148 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 17 Nov 2023 00:39:37 +0000 Subject: [PATCH 17/19] Merged PR 134598: UVM regression fixes for soc_ifc deadlock and AHB stall Fix three different regression errors caused by testbench bugs: * An edge case can cause AHB interface to stall up to 34 clock cycles when running SHA accelerator operations, previous TB code flags an error above 33 clock cycles * A multi-threaded sequence issue in the soc_ifc mailbox testcase with random register access injection can result in deadlock * A false-positive test pass might be reported for Caliptra-initiated mailbox tests - erroneous/unexpected MBOX_ERROR transitions are handled normally, even for non-error-injection scenarios. Related work items: #589323, #589324, #589546 --- .../ahb_lite_slave_0_config_policy.svh | 2 +- ...c_ifc_env_cptra_mbox_req_sequence_base.svh | 72 ++++++++++++++++--- ..._ifc_env_mbox_reg_axs_invalid_sequence.svh | 2 +- .../soc_ifc_env_mbox_sequence_base.svh | 2 +- .../soc_ifc_env_soc_mbox_handler_sequence.svh | 9 ++- ..._mbox_reg_axs_invalid_handler_sequence.svh | 14 +++- ...ra_mbox_reg_axs_invalid_small_sequence.svh | 9 +++ 7 files changed, 90 insertions(+), 20 deletions(-) diff --git a/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh b/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh index c242da515..1057eb119 100644 --- a/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh +++ b/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh @@ -121,7 +121,7 @@ class ahb_lite_slave_0_config_policy; // // If true, drives previous address when bus is IDLE // cfg.m_bfm.config_address_on_idle = 1'b0; // // Maximum number of successive wait states - cfg.m_bfm.config_max_wait_states_count = 33; + cfg.m_bfm.config_max_wait_states_count = 34; // // Data endianness // cfg.m_bfm.config_endianness = AHB_LITTLE_ENDIAN; // // Sets the domain diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh index 46863df42..3b720ac5e 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh @@ -40,6 +40,7 @@ class soc_ifc_env_cptra_mbox_req_sequence_base extends soc_ifc_env_sequence_base int sts_rsp_count; uvm_status_e reg_sts; bit mbox_sts_is_error = 0; + bit mbox_sts_exp_error = 0; // Indicates the SoC handler sequence will inject an error, which this sequence should expect to observe rand bit do_ahb_lock_check; rand bit retry_failed_reg_axs; // Certain random sequences force the command to be outside of the defined @@ -391,6 +392,9 @@ task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_poll_status(); if (data == DATA_READY) begin `uvm_info("CPTRA_MBOX_SEQ", $sformatf("Received status %p when not expecting any bytes of response data!", data), UVM_LOW) end + else if (data == CMD_FAILURE && !mbox_sts_exp_error) begin + `uvm_error("CPTRA_MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data)) + end else if (data == CMD_FAILURE) begin `uvm_info("CPTRA_MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data), UVM_LOW) end @@ -410,31 +414,79 @@ endtask //========================================== task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_clr_execute(); uvm_reg_data_t data; + bit error_intr_cmd_fail = 0; // We have to stall a couple clocks to allow interrupts to assert in case // we read the MBOX_ERROR status, since there is a small delay as the signal // propagates through registers. configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2); - // Now, check for the expected error interrupt + + // Catch the possibility that MBOX_ERROR was not yet observed by waiting for + // the associated interrupt to arrive (the SoC sequence may have a delay + // before injecting the error) + // If Caliptra already detected a MBOX_ERROR state, but did not see an + // error interrupt, that's an error condition that will be reported + // later on in the sequence with uvm_error + if (mbox_sts_exp_error && !mbox_sts_is_error) begin + fork + begin: WAIT_ERR_INTR + wait(sts_rsp_count > 0 && cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending); + disable WAIT_ERR_INTR_TIMEOUT; + end + begin: WAIT_ERR_INTR_TIMEOUT + configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(131072); + disable WAIT_ERR_INTR; + end + join + end + + // Now, do some error checking and handling if (sts_rsp_count > 0 && cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending) begin reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); report_reg_sts(reg_sts, "error_internal_intr_r"); reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); report_reg_sts(reg_sts, "error_internal_intr_r"); - if (data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_cmd_fail_sts.get_lsb_pos()]) begin - // Force unlock to recover from error and reset mailbox to IDLE state - reg_model.mbox_csr_rm.mbox_unlock.write(reg_sts, uvm_reg_data_t'(1 << reg_model.mbox_csr_rm.mbox_unlock.unlock.get_lsb_pos()), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); - report_reg_sts(reg_sts, "mbox_unlock"); - return; /* force unlock trumps the write to mbox_execute, so we're done at this point */ + error_intr_cmd_fail = data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_cmd_fail_sts.get_lsb_pos()]; + if (error_intr_cmd_fail) begin + if (!mbox_sts_is_error) begin + mbox_status_e data; + mbox_fsm_state_e state; + // Re-check mbox_status to see if FSM has changed to MBOX_ERROR since last check + mbox_check_status(data, state); + if (state == MBOX_ERROR) + mbox_sts_is_error = 1; + end end else if (mbox_sts_is_error) begin `uvm_error("CPTRA_MBOX_SEQ", "Error interrupt following cmd failure does not have cmd_fail bit set!") end end - else if (mbox_sts_is_error) begin - `uvm_error("CPTRA_MBOX_SEQ", "Error encountered but no interrupt received") + + // Error reporting based on sequence configuration and outcome + case ({mbox_sts_is_error,mbox_sts_exp_error,error_intr_cmd_fail}) inside + 3'b111: `uvm_info("CPTRA_MBOX_SEQ", "MBOX_ERROR state encountered as expected, along with the required error_interrupt", UVM_MEDIUM) + 3'b110: `uvm_error("CPTRA_MBOX_SEQ", "Mailbox error state encountered but no interrupt received") + 3'b10?: `uvm_error("CPTRA_MBOX_SEQ", "Mailbox error state encountered unexpectedly (the test case should not have an error injection)") + 3'b011: `uvm_error("CPTRA_MBOX_SEQ", "Invalid register access injection was expected for the test case, and error_interrupt was received, but MBOX_ERROR state was not observed") + // This case is acceptable, as the 'expected error' (such as invalid register accesses in the + // soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence) might either be clobbered in + // arb, or be an actual legal access (like a duplicate dataout read), + // neither of which will actually cause the MBOX_ERROR transition/error_interrupt combo. + 3'b010: `uvm_info("CPTRA_MBOX_SEQ", "Invalid register access injection was expected for the test case but MBOX_ERROR state was not observed - this might be OK", UVM_LOW) + 3'b001: `uvm_error("CPTRA_MBOX_SEQ", "Test case did not expect any error injection, but observed a command failure interrupt") + 3'b000: `uvm_info("CPTRA_MBOX_SEQ", "Test case completed normally as expected, with no observed failures or error_interrupt", UVM_MEDIUM) + endcase + + // Cmd failure interrupt triggers the force unlock, and + // force unlock trumps the write to mbox_execute + if (error_intr_cmd_fail && mbox_sts_is_error) begin + // Force unlock to recover from error and reset mailbox to IDLE state + reg_model.mbox_csr_rm.mbox_unlock.write(reg_sts, uvm_reg_data_t'(1 << reg_model.mbox_csr_rm.mbox_unlock.unlock.get_lsb_pos()), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); + report_reg_sts(reg_sts, "mbox_unlock"); + end + else begin + reg_model.mbox_csr_rm.mbox_execute.write(reg_sts, uvm_reg_data_t'(0), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); + report_reg_sts(reg_sts, "mbox_execute"); end - reg_model.mbox_csr_rm.mbox_execute.write(reg_sts, uvm_reg_data_t'(0), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); - report_reg_sts(reg_sts, "mbox_execute"); endtask //========================================== diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh index e0112ea05..2cde1d81f 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh @@ -70,7 +70,7 @@ class soc_ifc_env_mbox_reg_axs_invalid_sequence extends soc_ifc_env_mbox_sequenc mbox_set_cmd(mbox_op_rand); if (rand_delay_en) do_rand_delay(1, step_delay); mbox_push_datain(); if (rand_delay_en) do_rand_delay(1, step_delay); mbox_execute(); if (rand_delay_en) do_rand_delay(1, step_delay); - mbox_poll_status(); if (rand_delay_en) do_rand_delay(1, step_delay); + mbox_poll_status(); end begin: ERR_INJECT_FLOW wait(mbox_flow_proc != null); diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh index 2e7d04680..ceaee7f2a 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh @@ -527,7 +527,7 @@ task soc_ifc_env_mbox_sequence_base::mbox_read_resp_data(); reg_model.mbox_csr_rm.mbox_dataout.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER))); report_reg_sts(reg_sts, "mbox_dataout"); end - if (rand_delay_en) do_rand_delay(1, data_delay); + if (rand_delay_en && (ii+4) < dlen) do_rand_delay(1, data_delay); end endtask diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh index 028e280af..0a9217136 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh @@ -156,8 +156,10 @@ task soc_ifc_env_soc_mbox_handler_sequence::mbox_setup(); end // Pick a user and use throughout sequence - // FIXME randomize? - apb_user_obj.set_addr_user(mbox_valid_users[0]); + if (!apb_user_obj.randomize() with {addr_user inside {mbox_valid_users};}) + `uvm_error("SOC_MBOX_HANDLER", "Failed to randomize APB PAUSER override value") + else + `uvm_info("SOC_MBOX_HANDLER", $sformatf("Randomized APB PAUSER override value to 0x%x", apb_user_obj.addr_user), UVM_HIGH) endtask @@ -251,9 +253,6 @@ endtask task soc_ifc_env_soc_mbox_handler_sequence::mbox_set_status(); mbox_status_e status; uvm_reg_data_t data; - // Set mbox_dlen to resp size of 0 - reg_model.mbox_csr_rm.mbox_dlen.write(reg_sts, uvm_reg_data_t'(0), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj)); - report_reg_sts(reg_sts,"mbox_dlen"); // Determine which status to set and perform the write status = CMD_COMPLETE; data = uvm_reg_data_t'(status) << reg_model.mbox_csr_rm.mbox_status.status.get_lsb_pos(); diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh index 9c5b1a209..b886577f2 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh @@ -120,9 +120,19 @@ task soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence::mbox_do_random_reg_w if (!std::randomize(rand_idx) with {rand_idx < mbox_regs.size(); }) `uvm_fatal("SOC_MBOX_HANDLER", "Failed to randomize reg idx") - // Wait to do the reg write at some random point in the sequence + // Wait to do the reg write at some random point in the sequence, or do it + // very soon after the normal operation ends std::randomize(rand_delay) with {rand_delay dist {[1:255] :/ 5, [256:1023] :/ 3, [1024:65535] :/ 1};}; - configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(rand_delay); + fork + automatic int unsigned dly = rand_delay; + begin + configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(dly); + end + begin + mainline.await(); + configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(dly % 25); + end + join_any // Data used depends on which reg is being accessed to force invalid contents rand_wr_data = get_rand_wr_data(mbox_regs[rand_idx]); diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh index e97196520..f2370c915 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh @@ -32,6 +32,7 @@ class soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence extends soc_ifc_ `uvm_object_utils( soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence ) extern virtual function create_seqs(); + extern virtual function randomize_seqs(); endclass @@ -42,3 +43,11 @@ function soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::create_seqs( obj = soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence_t::get_type().create_object("soc_ifc_env_soc_handler_seq"); if(!$cast(soc_ifc_env_soc_handler_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID_SMALL", "soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::create_seqs() - .create_object() failed") endfunction + +function soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::randomize_seqs(); + if(!soc_ifc_env_cptra_mbox_seq.randomize()) + `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID_SMALL", $sformatf("soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::body() - %s randomization failed", soc_ifc_env_cptra_mbox_seq.get_type_name())); + soc_ifc_env_cptra_mbox_seq.mbox_sts_exp_error = 1; + if(!soc_ifc_env_soc_handler_seq.randomize()) + `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID_SMALL", $sformatf("soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::body() - %s randomization failed", soc_ifc_env_soc_handler_seq.get_type_name())); +endfunction From c5884b88769595ccff7409540d74c74e0c799ccd Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Sat, 18 Nov 2023 00:54:17 +0000 Subject: [PATCH 18/19] Merged PR 134981: Update kv scan sequence Update lower level scan mode sequence to make debugUnlock input to KV a pulse instead of a level Add some helpful prints to predictor Related work items: #591177 --- .../kv_env_pkg/src/kv_predictor.svh | 3 +++ .../src/kv_rst_scan_on_sequence.svh | 21 ++++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh index e1d4146ff..d17b1a2ac 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh @@ -332,6 +332,7 @@ class kv_predictor #( p_kv_rm.val_reg.debug_mode_unlocked.set(1'b1); p_kv_rm.val_reg.cptra_in_debug_scan_mode.set(1'b1); + `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode. Flushing KV", UVM_MEDIUM) if (clear_secrets_data[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()] == 'h1) begin for(entry = 0; entry < KV_NUM_KEYS; entry++) begin //Debug mode should flush all regs inspite of locks @@ -654,6 +655,7 @@ class kv_predictor #( //Only allow clear operation if in debug mode //if (data_active[1:0] == 'h1) begin if (data_active [p_kv_rm.kv_reg_rm.CLEAR_SECRETS.wr_debug_values.get_lsb_pos()] && !data_active[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()]) begin + `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode. Flushing KV with DEBUG0 values", UVM_MEDIUM) for(entry = 0; entry < KV_NUM_KEYS; entry++) begin //Read locks before clearing - do not clear if locked kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry)); @@ -668,6 +670,7 @@ class kv_predictor #( end //else if(data_active[1:0] == 'h3) begin else if (data_active [p_kv_rm.kv_reg_rm.CLEAR_SECRETS.wr_debug_values.get_lsb_pos()] && data_active[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()]) begin + `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode. Flushing KV with DEBUG1 values", UVM_MEDIUM) for(entry = 0; entry < KV_NUM_KEYS; entry++) begin //Read locks before clearing kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry)); diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh index 26d9db291..960931259 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh @@ -46,12 +46,27 @@ class kv_rst_scan_on_sequence extends kv_rst_sequence_base; task body(); - // Assert debug mode - req=kv_rst_transaction::type_id::create("pwr_req"); + // Assert scan mode, debugUnlock_or_scan_mode_switch + req=kv_rst_transaction::type_id::create("dbg_on_req"); start_item(req); // Randomize the transaction if(!req.randomize()) `uvm_fatal("KV_RST_SCAN_ON", "kv_rst_scan_on_sequence::body()-kv_rst_transaction randomization failed") - `uvm_info("KV_RST_SCAN_ON", "Enabling scan mode", UVM_MEDIUM) + `uvm_info("KV_RST_SCAN_ON", "Enabling scan mode, emulate pulse on debug_mode input", UVM_MEDIUM) + req.set_pwrgood = 1'b1; + req.assert_rst = 1'b0; + req.assert_core_rst = 1'b0; + req.debug_mode = 1'b1; + req.scan_mode = 1'b1; + + finish_item(req); + `uvm_info("KV_RST_SCAN_ON", {"Response:",req.convert2string()},UVM_MEDIUM) + + // Assert scan mode, deassert debugUnlock_or_scan_mode_switch + req=kv_rst_transaction::type_id::create("dbg_off_req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("KV_RST_SCAN_ON", "kv_rst_scan_on_sequence::body()-kv_rst_transaction randomization failed") + `uvm_info("KV_RST_SCAN_ON", "Reset debug_mode input", UVM_MEDIUM) req.set_pwrgood = 1'b1; req.assert_rst = 1'b0; req.assert_core_rst = 1'b0; From 15acd7b8aae3e39848b4e22e6c4027acb9da7567 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 30 Nov 2023 21:29:12 +0000 Subject: [PATCH 19/19] Merged PR 136182: Fix ICCM ECC error not reported * Fix the GH issue https://github.com/chipsalliance/caliptra-rtl/issues/295, which describes a scenario where ECC errors on reads from ICCM may not trigger the error signal and cause cptra_error_fatal to assert. * Fix a minor UVM issue in uvmf_soc_ifc that causes intermittent errors during nightly regression. Related work items: #597603, #597604, #597607 --- src/integration/tb/caliptra_top_tb.sv | 73 ++++ src/integration/tb/caliptra_top_tb_pkg.sv | 8 + .../tb/caliptra_top_tb_services.sv | 37 ++ .../smoke_test_ras/smoke_test_ras.c | 340 +++++++++++++----- src/riscv_core/veer_el2/rtl/el2_veer.sv | 3 +- src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv | 6 +- .../veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv | 4 + ..._mbox_reg_axs_invalid_handler_sequence.svh | 2 +- 8 files changed, 377 insertions(+), 96 deletions(-) diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv index ca7f5e21e..66de48009 100755 --- a/src/integration/tb/caliptra_top_tb.sv +++ b/src/integration/tb/caliptra_top_tb.sv @@ -165,6 +165,8 @@ module caliptra_top_tb ( logic cptra_error_fatal_dly_p; logic cptra_error_non_fatal_dly_p; + logic rv_dma_resp_error; + logic mbox_apb_dataout_read_ooo; logic mbox_ooo_read_done; logic mbox_apb_dataout_read_no_lock; @@ -232,7 +234,15 @@ module caliptra_top_tb ( end else if (ras_test_ctrl.reset_generic_input_wires) begin + `ifdef VERILATOR + generic_input_wires <= {32'h72746C76, ERROR_NONE_SET}; /* 32'h72746c76 is the big-endian ASCII representation of 'vltr' (r t l v) */ + `else generic_input_wires <= {32'h0, ERROR_NONE_SET}; + `endif + end + + else if (c_state_apb == S_APB_WAIT_ERROR_AXS && rv_dma_resp_error) begin + generic_input_wires <= {32'h0, DMA_ERROR_OBSERVED}; end else if (c_state_apb == S_APB_RD_HW_ERROR_FATAL && apb_xfer_end) begin @@ -1234,6 +1244,69 @@ caliptra_top_tb_services #( ); +`define RV_INST caliptra_top_dut.rvtop +`define RV_IDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_IDMA] +`define RV_DDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_DDMA] +task force_ahb_dma_read(input logic [31:0] address); + while(`RV_INST.dma_hsel) @(posedge core_clk); + force `RV_IDMA_RESP_INST.hreadyout = 1'b0; + force `RV_DDMA_RESP_INST.hreadyout = 1'b0; + + force `RV_INST.dma_haddr = address; + force `RV_INST.dma_hsize = 3'b010; // 4-bytes + force `RV_INST.dma_hwrite = 1'b0; + force `RV_INST.dma_hwdata = '0; + force `RV_INST.dma_hreadyin = 1'b1; + force `RV_INST.dma_hsel = 1'b1; + force `RV_INST.dma_htrans = 2'b10; + + // Wait for command to be accepted + do @(posedge core_clk); while(!`RV_INST.dma_hreadyout); + force `RV_INST.dma_htrans = 2'b00; + // Wait for response to be provided + do @(posedge core_clk); while(!`RV_INST.dma_hreadyout); + $display("[%t] AHB DMA FORCE READ: Address 0x%x Data 0x%x Resp 0x%x", $time, address, `RV_INST.dma_hrdata, `RV_INST.dma_hresp); + if (`RV_INST.dma_hresp) + rv_dma_resp_error = 1'b1; + release `RV_IDMA_RESP_INST.hreadyout; + release `RV_DDMA_RESP_INST.hreadyout; + + release `RV_INST.dma_htrans; + release `RV_INST.dma_haddr; + release `RV_INST.dma_hsize; + release `RV_INST.dma_hwrite; + release `RV_INST.dma_hwdata; + release `RV_INST.dma_hsel; + release `RV_INST.dma_hreadyin; +endtask + +task force_ahb_dma_loop_read(input logic [31:0] start_addr, input logic [19:0] count); + automatic logic [31:0] addr; + addr = start_addr; + $display("[%t] AHB DMA FORCE LOOP READ: Start Address 0x%x Count 0x%x", $time, addr, count); + if ($isunknown(start_addr) || $isunknown(addr)) + $error("[%t] Unknown signal found: start_addr 0x%x addr 0x%x", $time, start_addr, addr); + repeat(count) begin + force_ahb_dma_read(addr); + addr += 4; + end +endtask + +initial begin + fork + forever @(posedge core_clk) begin + if (ras_test_ctrl.dccm_read_burst.start) + force_ahb_dma_loop_read(ras_test_ctrl.dccm_read_burst.addr, ras_test_ctrl.dccm_read_burst.count); + if (ras_test_ctrl.iccm_read_burst.start) + force_ahb_dma_loop_read(ras_test_ctrl.iccm_read_burst.addr, ras_test_ctrl.iccm_read_burst.count); + end + forever @(posedge core_clk) begin + if (c_state_apb != S_APB_WAIT_ERROR_AXS) + rv_dma_resp_error = 1'b0; + end + join +end + caliptra_top_sva sva(); endmodule diff --git a/src/integration/tb/caliptra_top_tb_pkg.sv b/src/integration/tb/caliptra_top_tb_pkg.sv index 8a14afeb7..28f97e6f2 100644 --- a/src/integration/tb/caliptra_top_tb_pkg.sv +++ b/src/integration/tb/caliptra_top_tb_pkg.sv @@ -58,6 +58,13 @@ typedef struct packed { } veer_sram_error_injection_mode_t; typedef struct packed { + logic [31:0] addr; + logic [19:0] count; + logic start; +} rv_ccm_read_burst_pkt; +typedef struct packed { + rv_ccm_read_burst_pkt dccm_read_burst; + rv_ccm_read_burst_pkt iccm_read_burst; logic error_injection_seen; logic reset_generic_input_wires; logic do_no_lock_access; @@ -73,6 +80,7 @@ localparam PROT_OOO_NON_FATAL_OBSERVED = 32'h600dcafe; localparam ICCM_FATAL_OBSERVED = 32'hdeadaca1; localparam DCCM_FATAL_OBSERVED = 32'hdeadbeef; localparam NMI_FATAL_OBSERVED = 32'hdeadc0a7; +localparam DMA_ERROR_OBSERVED = 32'hfadebadd; localparam ERROR_NONE_SET = 32'hba5eba11; /* default value for a test with no activity observed by TB */ endpackage diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv index 817ae3129..8d167d0e7 100644 --- a/src/integration/tb/caliptra_top_tb_services.sv +++ b/src/integration/tb/caliptra_top_tb_services.sv @@ -240,6 +240,8 @@ module caliptra_top_tb_services // 8'h9a - Inject invalid zero sign_s into ECC // 8'ha0: 8'ha7 - Inject HMAC_KEY to kv_key register // 8'hc0: 8'hc7 - Inject SHA_BLOCK to kv_key register + // 8'hde - ICCM SRAM force loop read (requires read params written to other bytes of generic wires) + // 8'hdf - DCCM SRAM force loop read (requires read params written to other bytes of generic wires) // 8'he0 - Set random ICCM SRAM single bit error injection // 8'he1 - Set random ICCM SRAM double bit error injection // 8'he2 - Set random DCCM SRAM single bit error injection @@ -339,6 +341,41 @@ module caliptra_top_tb_services end end + always @(negedge clk or negedge cptra_rst_b) begin + if (!cptra_rst_b) begin + ras_test_ctrl.iccm_read_burst.start <= 1'b0; + ras_test_ctrl.iccm_read_burst.count <= '0; + ras_test_ctrl.iccm_read_burst.addr <= '0; + ras_test_ctrl.dccm_read_burst.start <= 1'b0; + ras_test_ctrl.dccm_read_burst.count <= '0; + ras_test_ctrl.dccm_read_burst.addr <= '0; + end + else if((WriteData[7:0] == 8'hde) && mailbox_write) begin + ras_test_ctrl.iccm_read_burst.start <= 1'b1; + ras_test_ctrl.iccm_read_burst.count <= WriteData[31:12]; + ras_test_ctrl.iccm_read_burst.addr <= caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[1].generic_wires.value; + ras_test_ctrl.dccm_read_burst.start <= 1'b0; + ras_test_ctrl.dccm_read_burst.count <= '0; + ras_test_ctrl.dccm_read_burst.addr <= '0; + end + else if((WriteData[7:0] == 8'hdf) && mailbox_write) begin + ras_test_ctrl.iccm_read_burst.start <= 1'b0; + ras_test_ctrl.iccm_read_burst.count <= '0; + ras_test_ctrl.iccm_read_burst.addr <= '0; + ras_test_ctrl.dccm_read_burst.start <= 1'b1; + ras_test_ctrl.dccm_read_burst.count <= WriteData[31:12]; + ras_test_ctrl.dccm_read_burst.addr <= caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[1].generic_wires.value; + end + else begin + ras_test_ctrl.iccm_read_burst.start <= 1'b0; + ras_test_ctrl.iccm_read_burst.count <= '0; + ras_test_ctrl.iccm_read_burst.addr <= '0; + ras_test_ctrl.dccm_read_burst.start <= 1'b0; + ras_test_ctrl.dccm_read_burst.count <= '0; + ras_test_ctrl.dccm_read_burst.addr <= '0; + end + end + initial ras_test_ctrl.error_injection_seen = 1'b0; always @(negedge clk) begin if (mailbox_write && WriteData[7:0] == 8'hfd) begin diff --git a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c index 593b92d3e..80602d475 100644 --- a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c +++ b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c @@ -72,6 +72,7 @@ enum tb_resp_value { ICCM_FATAL_OBSERVED = 0xdeadaca1, DCCM_FATAL_OBSERVED = 0xdeadbeef, NMI_FATAL_OBSERVED = 0xdeadc0a7, + DMA_ERROR_OBSERVED = 0xfadebadd, ERROR_NONE_SET = 0xba5eba11, /* default value for a test with no activity observed by TB */ }; @@ -80,6 +81,15 @@ enum mask_config { NO_MASK }; +enum read_config { + FROM_IFU, + FROM_LSU, +}; +enum dccm_read_config { + DATA_LOAD, + FORCE_DMA +}; + enum recovery_config { WARM_RESET, FORCE_UNLOCK @@ -98,6 +108,7 @@ enum test_status { enum test_progress { NOT_STARTED, + SKIPPED, RUN_NOT_CHECKED, RUN_AND_FAILED, RUN_AND_PASSED @@ -106,33 +117,44 @@ enum test_progress { // Used to index into the global array of test progress // TODO Test the FW FATAL/NON_FATAL regs enum test_list { - MBOX_SRAM_ECC_SINGLE_UNMASKED, - MBOX_SRAM_ECC_DOUBLE_UNMASKED, - MBOX_SRAM_ECC_SINGLE_MASKED , - MBOX_SRAM_ECC_DOUBLE_MASKED , - ICCM_SRAM_ECC_SINGLE_UNMASKED, - ICCM_SRAM_ECC_DOUBLE_UNMASKED, - ICCM_SRAM_ECC_SINGLE_MASKED , - ICCM_SRAM_ECC_DOUBLE_MASKED , - DCCM_SRAM_ECC_SINGLE_UNMASKED, - DCCM_SRAM_ECC_DOUBLE_UNMASKED, - DCCM_SRAM_ECC_SINGLE_MASKED , - DCCM_SRAM_ECC_DOUBLE_MASKED , - NMI_UNMASKED , - NMI_MASKED , - PROT_NO_LOCK_UNMASKED , - PROT_NO_LOCK_MASKED , - PROT_OOO_UNMASKED , - PROT_OOO_MASKED , - TEST_COUNT , + MBOX_SRAM_ECC_SINGLE_UNMASKED , + MBOX_SRAM_ECC_DOUBLE_UNMASKED , + MBOX_SRAM_ECC_SINGLE_MASKED , + MBOX_SRAM_ECC_DOUBLE_MASKED , + ICCM_SRAM_ECC_SINGLE_IFU_UNMASKED , + ICCM_SRAM_ECC_DOUBLE_IFU_UNMASKED , + ICCM_SRAM_ECC_SINGLE_IFU_MASKED , + ICCM_SRAM_ECC_DOUBLE_IFU_MASKED , + ICCM_SRAM_ECC_SINGLE_LSU_UNMASKED , + ICCM_SRAM_ECC_DOUBLE_LSU_UNMASKED , + ICCM_SRAM_ECC_SINGLE_LSU_MASKED , + ICCM_SRAM_ECC_DOUBLE_LSU_MASKED , + DCCM_SRAM_ECC_SINGLE_LOAD_UNMASKED, + DCCM_SRAM_ECC_DOUBLE_LOAD_UNMASKED, + DCCM_SRAM_ECC_SINGLE_LOAD_MASKED , + DCCM_SRAM_ECC_DOUBLE_LOAD_MASKED , + DCCM_SRAM_ECC_SINGLE_DMA_UNMASKED , + DCCM_SRAM_ECC_DOUBLE_DMA_UNMASKED , + DCCM_SRAM_ECC_SINGLE_DMA_MASKED , + DCCM_SRAM_ECC_DOUBLE_DMA_MASKED , + NMI_UNMASKED , + NMI_MASKED , + PROT_NO_LOCK_UNMASKED , + PROT_NO_LOCK_MASKED , + PROT_OOO_UNMASKED , + PROT_OOO_MASKED , + TEST_COUNT , }; enum boot_count_list { BEFORE_FIRST_ICCM_FAILURE = 1, BEFORE_SECOND_ICCM_FAILURE , + BEFORE_THIRD_ICCM_FAILURE , BEFORE_FIRST_DCCM_FAILURE , + BEFORE_SECOND_DCCM_FAILURE , BEFORE_FIRST_NMI_FAILURE , BEFORE_SECOND_NMI_FAILURE , - AFTER_SECOND_NMI_FAILURE , + BEFORE_THIRD_NMI_FAILURE , + AFTER_THIRD_NMI_FAILURE , AFTER_FIRST_MBOX_OOO_FAILURE , AFTER_SECOND_MBOX_OOO_FAILURE }; @@ -187,6 +209,18 @@ volatile uint32_t generic_input_wires_0_before_rst __attribute__((section(".dccm // Track test progress across resets by allocating the variable in DCCM, which // is initialized only once at time 0 enum test_progress test_progress_g[TEST_COUNT] __attribute__((section(".dccm.persistent"))) = { + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, + NOT_STARTED, NOT_STARTED, NOT_STARTED, NOT_STARTED, @@ -213,12 +247,12 @@ uint32_t check_mbox_sram_ecc(enum ecc_error_mode_type type, enum mask_config tes uint32_t test_mbox_sram_ecc (enum mask_config test_mask); /* ICCM ECC */ -uint32_t run_iccm_sram_ecc (enum mask_config test_mask); -uint32_t check_iccm_sram_ecc (enum mask_config test_mask); +uint32_t run_iccm_sram_ecc (enum mask_config test_mask, enum read_config read_mask); +uint32_t check_iccm_sram_ecc (enum mask_config test_mask, enum read_config read_mask); /* DCCM ECC */ -uint32_t run_dccm_sram_ecc (enum mask_config test_mask); -uint32_t check_dccm_sram_ecc (enum mask_config test_mask); +uint32_t run_dccm_sram_ecc (enum mask_config test_mask, enum dccm_read_config read_path); +uint32_t check_dccm_sram_ecc (enum mask_config test_mask, enum dccm_read_config read_path); /* MBOX PROT */ void run_mbox_no_lock_error (enum mask_config test_mask); @@ -296,7 +330,7 @@ uint32_t check_mbox_sram_ecc(enum ecc_error_mode_type type, enum mask_config tes sts |= UNEXP_ARG; } if (test_progress_g[cur_test] != RUN_NOT_CHECKED) { - VPRINTF(ERROR, "Mbox chkr hit unexpected state. Idx: %d Prog: %d", cur_test, test_progress_g[cur_test]); + VPRINTF(ERROR, "Mbox chkr hit unexpected state. Idx: %d Prog: %d\n", cur_test, test_progress_g[cur_test]); sts |= INV_STATE; } @@ -385,22 +419,26 @@ uint32_t test_mbox_sram_ecc (enum mask_config test_mask) { check_mbox_sram_ecc(MBOX_DOUBLE, test_mask); } -uint32_t run_iccm_sram_ecc (enum mask_config test_mask) { +uint32_t run_iccm_sram_ecc (enum mask_config test_mask, enum read_config read_mask) { enum test_list cur_test; uint32_t * ICCM = (uint32_t *) RV_ICCM_SADR; uint32_t * code_word = 0; uint32_t * iccm_dest = ICCM; void (* iccm_fn) (void) = (void*) ICCM; + uint32_t * actual_iccm_code_end = 0; uint32_t resp; + uint32_t tmp_reg; - VPRINTF(MEDIUM, "\n*** Run ICCM SRAM ECC Err ***\n Masked: %d\n\n", test_mask == WITH_MASK); + VPRINTF(MEDIUM, "\n*** Run ICCM SRAM ECC Err ***\n Masked: %d\n IFU: %d\n\n", test_mask == WITH_MASK, read_mask == FROM_IFU); // Grab test enum - if (test_mask == WITH_MASK) { cur_test = ICCM_SRAM_ECC_SINGLE_MASKED; } - else if (test_mask == NO_MASK) { cur_test = ICCM_SRAM_ECC_SINGLE_UNMASKED; } - else { cur_test = TEST_COUNT; } + if (test_mask == WITH_MASK && read_mask == FROM_IFU) { cur_test = ICCM_SRAM_ECC_SINGLE_IFU_MASKED; } + else if (test_mask == NO_MASK && read_mask == FROM_IFU) { cur_test = ICCM_SRAM_ECC_SINGLE_IFU_UNMASKED; } + else if (test_mask == WITH_MASK && read_mask == FROM_LSU) { cur_test = ICCM_SRAM_ECC_SINGLE_LSU_MASKED; } + else if (test_mask == NO_MASK && read_mask == FROM_LSU) { cur_test = ICCM_SRAM_ECC_SINGLE_LSU_UNMASKED; } + else { cur_test = TEST_COUNT; } // Request that TB inject ICCM SRAM single-bit errors // This should not result in any reset or reporting activity @@ -413,6 +451,7 @@ uint32_t run_iccm_sram_ecc (enum mask_config test_mask) { VPRINTF(ALL, "at %x: %x\n", (uintptr_t) code_word, *code_word); *iccm_dest++ = *code_word++; } + actual_iccm_code_end = iccm_dest; // Reset the Error Injection Function SEND_STDOUT_CTRL((uint32_t) ERROR_NONE); @@ -421,7 +460,18 @@ uint32_t run_iccm_sram_ecc (enum mask_config test_mask) { test_progress_g[cur_test] = RUN_NOT_CHECKED; // Run ICCM routine - iccm_fn(); + VPRINTF(MEDIUM, "Single-bit:\n"); + if (read_mask == FROM_IFU) { + iccm_fn(); + // Read from ICCM instead + } else if (read_mask == FROM_LSU) { + code_word = (uint32_t *) ICCM; + VPRINTF(LOW, "Read code from %x [through %x]\n", (uintptr_t) code_word, (uintptr_t) actual_iccm_code_end); + while (code_word < actual_iccm_code_end) { + tmp_reg ^= *code_word++; + } + VPRINTF(LOW, "Data in ICCM: 0x%x\n", tmp_reg); + } // Confirm TB reports no observed activity resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0); @@ -444,9 +494,11 @@ uint32_t run_iccm_sram_ecc (enum mask_config test_mask) { // Should return here after encountering single-bit (correctable) ECC errors // while running ICCM routine // Set new test enum - if (test_mask == WITH_MASK) { cur_test = ICCM_SRAM_ECC_DOUBLE_MASKED; } - else if (test_mask == NO_MASK) { cur_test = ICCM_SRAM_ECC_DOUBLE_UNMASKED; } - else { cur_test = TEST_COUNT; } + if (test_mask == WITH_MASK && read_mask == FROM_IFU) { cur_test = ICCM_SRAM_ECC_DOUBLE_IFU_MASKED; } + else if (test_mask == NO_MASK && read_mask == FROM_IFU) { cur_test = ICCM_SRAM_ECC_DOUBLE_IFU_UNMASKED; } + else if (test_mask == WITH_MASK && read_mask == FROM_LSU) { cur_test = ICCM_SRAM_ECC_DOUBLE_LSU_MASKED; } + else if (test_mask == NO_MASK && read_mask == FROM_LSU) { cur_test = ICCM_SRAM_ECC_DOUBLE_LSU_UNMASKED; } + else { cur_test = TEST_COUNT; } // Now, set the MASK (per arg) if (test_mask == WITH_MASK) { @@ -484,27 +536,53 @@ uint32_t run_iccm_sram_ecc (enum mask_config test_mask) { // Run ICCM routine // If FATAL error unmasked, this will trigger a reset. // Else, we'll observe a precise exception, which should do a firmware reset - iccm_fn(); + VPRINTF(MEDIUM, "Double-bit:\n"); + if (read_mask == FROM_IFU) { + iccm_fn(); + // Read from ICCM instead + } else if (read_mask == FROM_LSU) { + code_word = (uint32_t *) ICCM; + VPRINTF(LOW, "Read code from %x [through %x]\n", (uintptr_t) code_word, (uintptr_t) actual_iccm_code_end); + while (code_word < actual_iccm_code_end) { + tmp_reg = *code_word++; + VPRINTF(LOW, "Data in ICCM: 0x%x\n", tmp_reg); + } + } // Wait for the reset to occur if (test_mask == NO_MASK) { VPRINTF(HIGH, "...\n"); while(1); } } -uint32_t check_iccm_sram_ecc (enum mask_config test_mask) { +uint32_t check_iccm_sram_ecc (enum mask_config test_mask, enum read_config read_mask) { enum test_list cur_test; uint32_t resp; uint32_t sts = SUCCESS; - VPRINTF(MEDIUM, "\n*** Check ICCM SRAM ECC Err ***\n Masked: %d\n\n", test_mask == WITH_MASK); + VPRINTF(MEDIUM, "\n*** Check ICCM SRAM ECC Err ***\n Masked: %d\n IFU: %d\n\n", test_mask == WITH_MASK, read_mask == FROM_IFU); // Get test ID - if (test_mask == WITH_MASK) { cur_test = ICCM_SRAM_ECC_DOUBLE_MASKED; } - else { cur_test = ICCM_SRAM_ECC_DOUBLE_UNMASKED; } - + if (test_mask == WITH_MASK && read_mask == FROM_IFU) { cur_test = ICCM_SRAM_ECC_DOUBLE_IFU_MASKED; } + else if (test_mask == NO_MASK && read_mask == FROM_IFU ) { cur_test = ICCM_SRAM_ECC_DOUBLE_IFU_UNMASKED; } + else if (test_mask == WITH_MASK && read_mask == FROM_LSU) { cur_test = ICCM_SRAM_ECC_DOUBLE_LSU_MASKED; } + else if (test_mask == NO_MASK && read_mask == FROM_LSU ) { cur_test = ICCM_SRAM_ECC_DOUBLE_LSU_UNMASKED; } + else { cur_test = TEST_COUNT;} // Verify correct response path was taken resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0); - if (test_mask == WITH_MASK) { + + if (test_mask == WITH_MASK && read_mask == FROM_LSU) { + // No generic input toggle expected out of reset + if ((cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) && (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) != generic_input_wires_0_before_rst)) { + VPRINTF(ERROR, "ERROR: Gen-in tgl with bad val\n"); + sts |= BAD_CPTRA_SIG; + test_progress_g[cur_test] = RUN_AND_FAILED; + } else { + sts |= SUCCESS; + test_progress_g[cur_test] = RUN_AND_PASSED; + } + + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK); + } else if (test_mask == WITH_MASK && read_mask == FROM_IFU) { // For a MASKED error, we only expect the exception path and no response from TB if (exc_flag.exception_hit == 0) { test_progress_g[cur_test] = RUN_AND_FAILED; @@ -534,7 +612,7 @@ uint32_t check_iccm_sram_ecc (enum mask_config test_mask) { } // TODO should test both DMA slave and internal DCCM accesses? -uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { +uint32_t run_dccm_sram_ecc (enum mask_config test_mask, enum dccm_read_config read_path) { enum test_list cur_test; uint32_t array_in_dccm [10]; // stack is in DCCM, so this automatically goes there @@ -542,12 +620,27 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { uint32_t resp = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L); - VPRINTF(MEDIUM, "\n*** Run DCCM SRAM ECC Err ***\n Masked: %d\n\n", test_mask == WITH_MASK); + VPRINTF(MEDIUM, "\n*** Run DCCM SRAM ECC Err ***\n Masked: %d\n Path: %s\n\n", test_mask == WITH_MASK, read_path == DATA_LOAD ? "LOAD" : "DMA"); // Grab test enum - if (test_mask == WITH_MASK) { cur_test = DCCM_SRAM_ECC_SINGLE_MASKED; } - else if (test_mask == NO_MASK) { cur_test = DCCM_SRAM_ECC_SINGLE_UNMASKED; } - else { cur_test = TEST_COUNT; } + if (test_mask == WITH_MASK && read_path == DATA_LOAD) { cur_test = DCCM_SRAM_ECC_SINGLE_LOAD_MASKED; } + else if (test_mask == NO_MASK && read_path == DATA_LOAD) { cur_test = DCCM_SRAM_ECC_SINGLE_LOAD_UNMASKED; } + else if (test_mask == WITH_MASK && read_path == FORCE_DMA) { cur_test = DCCM_SRAM_ECC_SINGLE_DMA_MASKED; } + else if (test_mask == NO_MASK && read_path == FORCE_DMA) { cur_test = DCCM_SRAM_ECC_SINGLE_DMA_UNMASKED; } + else { cur_test = TEST_COUNT; } + + // Skip the FORCE_DMA test if running in Verilator - it's bugged FIXME + if (read_path == FORCE_DMA) { + SEND_STDOUT_CTRL((uint32_t) ERROR_NONE); + if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1) == ('v' | 'l' << 8 | 't' << 16 | 'r' << 24)) { + VPRINTF(LOW, "Skipping DMA path in Verilator\n"); + test_progress_g[cur_test] = SKIPPED; + if (test_mask == NO_MASK) { + SEND_STDOUT_CTRL(0xf6); // Warm reset + } + return 0; + } + } // Acquire the mailbox lock (to allow direct-mode use of safe_iter) while((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0) { @@ -560,7 +653,7 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { // Populate array in DCCM (should be corrupted) *safe_iter = 0; - while(*safe_iter < 10) { + while(*safe_iter < 10) { resp = (resp << 1) ^ lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L); array_in_dccm[*safe_iter] = resp; *safe_iter = (*safe_iter) + 1; @@ -574,10 +667,17 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { test_progress_g[cur_test] = RUN_NOT_CHECKED; // Read-back the array in DCCM + VPRINTF(MEDIUM, "Single-bit:\n"); *safe_iter = 0; - while(*safe_iter < 10) { - printf("[%d]:%x\n", *safe_iter, array_in_dccm[*safe_iter]); // no verbosity control -- dereferencing the array IS the test - *safe_iter = (*safe_iter) + 1; + if (read_path == DATA_LOAD) { + while(*safe_iter < 10) { + printf("[%d]:%x\n", *safe_iter, array_in_dccm[*safe_iter]); // no verbosity control -- dereferencing the array IS the test + *safe_iter = (*safe_iter) + 1; + } + } else if (read_path == FORCE_DMA) { + VPRINTF(LOW, "Trigger TB to force DMA burst\n"); + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1, (uint32_t) &array_in_dccm); + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0, (10 << 12) | 0xdf); } // Unlock Mailbox @@ -604,9 +704,11 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { // Should return here after encountering single-bit (correctable) ECC errors // while running DCCM routine // Set new test enum - if (test_mask == WITH_MASK) { cur_test = DCCM_SRAM_ECC_DOUBLE_MASKED; } - else if (test_mask == NO_MASK) { cur_test = DCCM_SRAM_ECC_DOUBLE_UNMASKED; } - else { cur_test = TEST_COUNT; } + if (test_mask == WITH_MASK && read_path == DATA_LOAD) { cur_test = DCCM_SRAM_ECC_DOUBLE_LOAD_MASKED; } + else if (test_mask == NO_MASK && read_path == DATA_LOAD) { cur_test = DCCM_SRAM_ECC_DOUBLE_LOAD_UNMASKED; } + else if (test_mask == WITH_MASK && read_path == FORCE_DMA) { cur_test = DCCM_SRAM_ECC_DOUBLE_DMA_MASKED; } + else if (test_mask == NO_MASK && read_path == FORCE_DMA) { cur_test = DCCM_SRAM_ECC_DOUBLE_DMA_UNMASKED; } + else { cur_test = TEST_COUNT; } // Now, set the MASK (per arg) if (test_mask == WITH_MASK) { @@ -629,7 +731,7 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { // Populate array in DCCM (should be corrupted) *safe_iter = 0; - while(*safe_iter < 10) { + while(*safe_iter < 10) { resp = (resp << 1) ^ lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L); array_in_dccm[*safe_iter] = resp; *safe_iter = (*safe_iter) + 1; @@ -651,11 +753,19 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { // Read-back the array in DCCM // If FATAL error unmasked, this will trigger a reset. + // If FATAL error masked, but using DMA path, this only results in generic input wire value // Else, we'll observe a precise exception + VPRINTF(MEDIUM, "Double-bit:\n"); *safe_iter = 0; - while(*safe_iter < 10) { - printf("[%d]:%x\n", *safe_iter, array_in_dccm[*safe_iter]); // no verbosity control -- dereferencing the array IS the test - *safe_iter = (*safe_iter) + 1; + if (read_path == DATA_LOAD) { + while(*safe_iter < 10) { + printf("[%d]:%x\n", *safe_iter, array_in_dccm[*safe_iter]); // no verbosity control -- dereferencing the array IS the test + *safe_iter = (*safe_iter) + 1; + } + } else if (read_path == FORCE_DMA) { + VPRINTF(LOW, "Trigger TB to force DMA burst\n"); + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1, (uint32_t) &array_in_dccm); + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0, (10 << 12) | 0xdf); } // Unlock Mailbox @@ -666,20 +776,32 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask) { } -uint32_t check_dccm_sram_ecc (enum mask_config test_mask) { +uint32_t check_dccm_sram_ecc (enum mask_config test_mask, enum dccm_read_config read_path) { enum test_list cur_test; uint32_t resp; uint32_t sts = SUCCESS; - VPRINTF(MEDIUM, "\n*** Check DCCM SRAM ECC Err ***\n Masked: %d\n\n", test_mask == WITH_MASK); + VPRINTF(MEDIUM, "\n*** Check DCCM SRAM ECC Err ***\n Masked: %d\n Path: %s\n\n", test_mask == WITH_MASK, read_path == DATA_LOAD ? "LOAD" : "DMA"); // Get test ID - if (test_mask == WITH_MASK) { cur_test = DCCM_SRAM_ECC_DOUBLE_MASKED; } - else { cur_test = DCCM_SRAM_ECC_DOUBLE_UNMASKED; } + if (test_mask == WITH_MASK && read_path == DATA_LOAD) { cur_test = DCCM_SRAM_ECC_DOUBLE_LOAD_MASKED; } + else if (test_mask == NO_MASK && read_path == DATA_LOAD) { cur_test = DCCM_SRAM_ECC_DOUBLE_LOAD_UNMASKED; } + else if (test_mask == WITH_MASK && read_path == FORCE_DMA) { cur_test = DCCM_SRAM_ECC_DOUBLE_DMA_MASKED; } + else if (test_mask == NO_MASK && read_path == FORCE_DMA) { cur_test = DCCM_SRAM_ECC_DOUBLE_DMA_UNMASKED; } + else { cur_test = TEST_COUNT; } + + // Skip the FORCE_DMA test if running in Verilator - it's bugged FIXME + if (read_path == FORCE_DMA) { + if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1) == ('v' | 'l' << 8 | 't' << 16 | 'r' << 24)) { + VPRINTF(LOW, "Skipping DMA path in Verilator\n"); + test_progress_g[cur_test] = SKIPPED; + return sts; + } + } // Verify correct response path was taken resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0); - if (test_mask == WITH_MASK) { + if (test_mask == WITH_MASK && read_path == DATA_LOAD) { // For a MASKED error, we only expect the exception path and no response from TB if (exc_flag.exception_hit == 0) { test_progress_g[cur_test] = RUN_AND_FAILED; @@ -698,6 +820,25 @@ uint32_t check_dccm_sram_ecc (enum mask_config test_mask) { test_progress_g[cur_test] = RUN_AND_PASSED; } lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK); + } else if (test_mask == WITH_MASK && read_path == FORCE_DMA) { + // For a MASKED error through the DMA force-access path, expect a TB response + // but no reset, no exceptions, and the FATAL error bit should be set + if (exc_flag.exception_hit == 1) { + test_progress_g[cur_test] = RUN_AND_FAILED; + sts |= BAD_EXCP_CODE; + VPRINTF(ERROR, "ERROR: Unexpected excpn\n"); + } else if (resp != DMA_ERROR_OBSERVED) { + test_progress_g[cur_test] = RUN_AND_FAILED; + sts |= BAD_CPTRA_SIG; + VPRINTF(ERROR, "ERROR: Wrong TB resp. Got 0x%x, exp 0x%x\n", resp, DMA_ERROR_OBSERVED); + } else if (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL) & SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK)) { + test_progress_g[cur_test] = RUN_AND_FAILED; + sts |= INV_STATE; + VPRINTF(ERROR, "ERROR: DCCM ECC UNC FATAL not set by TB\n"); + } else { + test_progress_g[cur_test] = RUN_AND_PASSED; + } + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK); } else { // For an UNMASKED error, we expect DCCM ECC FATAL Error to trigger TB reset and input val if (resp == DCCM_FATAL_OBSERVED) { @@ -715,7 +856,7 @@ uint32_t check_dccm_sram_ecc (enum mask_config test_mask) { void run_nmi_test (enum mask_config test_mask) { enum test_list cur_test; VPRINTF(MEDIUM, "\n*** Run Non-Maskable Intr ***\n Masked: %d\n\n", test_mask == WITH_MASK); - + // Get test ID if (test_mask == WITH_MASK) { cur_test = NMI_MASKED; } else { cur_test = NMI_UNMASKED; } @@ -757,7 +898,7 @@ uint32_t check_nmi_test (enum mask_config test_mask) { if (test_mask == WITH_MASK) { // No generic input toggle expected out of reset - if ((cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK) && (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) != generic_input_wires_0_before_rst)) { + if ((cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) && (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) != generic_input_wires_0_before_rst)) { VPRINTF(ERROR, "ERROR: Gen-in tgl with bad val\n"); sts |= BAD_CPTRA_SIG; test_progress_g[cur_test] = RUN_AND_FAILED; @@ -769,7 +910,7 @@ uint32_t check_nmi_test (enum mask_config test_mask) { lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK); } else { // Check for generic_input_wires activity - if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK)) { + if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK)) { VPRINTF(ERROR, "ERROR: Gen-in did not tgl\n"); sts |= BAD_CPTRA_SIG; test_progress_g[cur_test] = RUN_AND_FAILED; @@ -860,7 +1001,7 @@ uint32_t check_mbox_no_lock_error(enum mask_config test_mask) { test_progress_g[cur_test] = RUN_AND_FAILED; } else if (test_mask == WITH_MASK) { // Check for generic_input_wires activity - if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK) { + if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) { VPRINTF(ERROR, "ERROR: Gen-in tgl\n"); sts |= BAD_CPTRA_SIG; test_progress_g[cur_test] = RUN_AND_FAILED; @@ -871,7 +1012,7 @@ uint32_t check_mbox_no_lock_error(enum mask_config test_mask) { lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK); } else { // Check for generic_input_wires activity - if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK)) { + if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK)) { VPRINTF(ERROR, "ERROR: Gen-in did not tgl\n"); sts |= BAD_CPTRA_SIG; test_progress_g[cur_test] = RUN_AND_FAILED; @@ -907,7 +1048,7 @@ uint32_t check_mbox_ooo_error(enum mask_config test_mask) { test_progress_g[cur_test] = RUN_AND_FAILED; } else if (test_mask == WITH_MASK) { // Check for generic_input_wires activity - if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK) { + if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) { VPRINTF(ERROR, "ERROR: Gen-in tgl\n"); sts |= BAD_CPTRA_SIG; test_progress_g[cur_test] = RUN_AND_FAILED; @@ -921,7 +1062,7 @@ uint32_t check_mbox_ooo_error(enum mask_config test_mask) { SEND_STDOUT_CTRL(0xe7); } else { // Check for generic_input_wires activity - if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK)) { + if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK)) { VPRINTF(ERROR, "ERROR: Gen-in did not tgl\n"); sts |= BAD_CPTRA_SIG; test_progress_g[cur_test] = RUN_AND_FAILED; @@ -969,8 +1110,8 @@ void execute_from_iccm (void) { // ERROR_FATAL interrupt will only go to TB if running the unmasked // double-bit error test, so we expect to get here successfully and return // in other test cases - if (test_progress_g[ICCM_SRAM_ECC_DOUBLE_UNMASKED] == RUN_NOT_CHECKED && - test_progress_g[ICCM_SRAM_ECC_SINGLE_MASKED ] == NOT_STARTED) { + if (test_progress_g[ICCM_SRAM_ECC_DOUBLE_IFU_UNMASKED] == RUN_NOT_CHECKED && + test_progress_g[ICCM_SRAM_ECC_SINGLE_IFU_MASKED ] == NOT_STARTED) { while(1) { __asm__ volatile ("wfi"); // "Wait for interrupt" // Continuously loop to allow the ICCM ECC ERROR to trigger system reset @@ -987,28 +1128,30 @@ void execute_from_iccm (void) { // In the ROM .text section void nmi_handler (void) { VPRINTF(LOW, "**** NMI ****\n"); - if (boot_count != BEFORE_FIRST_NMI_FAILURE && boot_count != BEFORE_SECOND_NMI_FAILURE) { + if (boot_count != BEFORE_FIRST_NMI_FAILURE && boot_count != BEFORE_SECOND_NMI_FAILURE && boot_count != BEFORE_THIRD_NMI_FAILURE) { VPRINTF(ERROR, "ERROR: NMI unexpected. mcause [0x%x]!\n", csr_read_mcause()); // did not expect NMI VPRINTF(ERROR, " mepc [0x%x]\n", csr_read_mepc()); SEND_STDOUT_CTRL(0x1); while(1); } // If we got here via internal NMI, it's an error - kill the sim - if ((csr_read_mcause() & MCAUSE_NMI_BIT_MASK) == MCAUSE_NMI_BIT_MASK) { + if ((boot_count != BEFORE_THIRD_NMI_FAILURE) && ((csr_read_mcause() & MCAUSE_NMI_BIT_MASK) == MCAUSE_NMI_BIT_MASK)) { VPRINTF(ERROR, "ERROR: NMI w/ mcause [0x%x]!\n", csr_read_mcause()); VPRINTF(ERROR, " mepc [0x%x]\n", csr_read_mepc()); SEND_STDOUT_CTRL(0x1); while(1); } - // NMI occurred, but was caused by pin-assertion due to Watchdog Timer - else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL) & SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK) { + // NMI occurred, check if we had a fatal error + if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL) & (SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK | + SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK)) { //Save generic_input_wires value before reset to compare later. This is to avoid flagging the toggle during reset as an error generic_input_wires_0_before_rst = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0); VPRINTF(MEDIUM, "NMI w/ mcause [0x%x] during NMI test\n", csr_read_mcause()); VPRINTF(MEDIUM, "mepc [0x%x]\n", csr_read_mepc()); - // If the FATAL Error bit for NMI is masked, manually trigger firmware reset - if (lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK) & SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK) { - VPRINTF(LOW, "NMI bit masked, no rst exp from TB: rst core manually!\n"); + // If the FATAL Error bit for ECC UNC or NMI is masked, manually trigger firmware reset + if (lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK) & (SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK | + SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK)) { + VPRINTF(LOW, "FATAL_ERROR bit is masked, no rst exp from TB: rst core manually!\n"); //lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET, SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK); SEND_STDOUT_CTRL(0xf6); // Otherwise, wait for core reset @@ -1044,26 +1187,35 @@ void main(void) { // No reset expected following MBOX SRAM ECC Error injection // Test ICCM SRAM ECC - if (boot_count == BEFORE_FIRST_ICCM_FAILURE) { run_iccm_sram_ecc(NO_MASK ); } - else if (boot_count == BEFORE_SECOND_ICCM_FAILURE) { check_iccm_sram_ecc(NO_MASK ); - run_iccm_sram_ecc(WITH_MASK); } - else if (boot_count == BEFORE_FIRST_DCCM_FAILURE) { check_iccm_sram_ecc(WITH_MASK); } + if (boot_count == BEFORE_FIRST_ICCM_FAILURE) { run_iccm_sram_ecc(NO_MASK, FROM_IFU); } + else if (boot_count == BEFORE_SECOND_ICCM_FAILURE) { check_iccm_sram_ecc(NO_MASK, FROM_IFU); + run_iccm_sram_ecc(WITH_MASK, FROM_IFU); } + else if (boot_count == BEFORE_THIRD_ICCM_FAILURE) { check_iccm_sram_ecc(WITH_MASK, FROM_IFU); + run_iccm_sram_ecc(NO_MASK, FROM_LSU); } + else if (boot_count == BEFORE_FIRST_DCCM_FAILURE) { check_iccm_sram_ecc(NO_MASK, FROM_LSU); } // Test DCCM SRAM ECC - if (boot_count == BEFORE_FIRST_DCCM_FAILURE){ run_dccm_sram_ecc(NO_MASK ); } - else if (boot_count == BEFORE_FIRST_NMI_FAILURE) { check_dccm_sram_ecc(NO_MASK ); - run_dccm_sram_ecc(WITH_MASK); - check_dccm_sram_ecc(WITH_MASK); } + if (boot_count == BEFORE_FIRST_DCCM_FAILURE) { run_dccm_sram_ecc(NO_MASK , DATA_LOAD); } + else if (boot_count == BEFORE_SECOND_DCCM_FAILURE){ check_dccm_sram_ecc(NO_MASK , DATA_LOAD); + run_dccm_sram_ecc(WITH_MASK, DATA_LOAD); + check_dccm_sram_ecc(WITH_MASK, DATA_LOAD); + run_dccm_sram_ecc(NO_MASK , FORCE_DMA); } + else if (boot_count == BEFORE_FIRST_NMI_FAILURE) { check_dccm_sram_ecc(NO_MASK , FORCE_DMA); + run_dccm_sram_ecc(WITH_MASK, FORCE_DMA); + check_dccm_sram_ecc(WITH_MASK, FORCE_DMA); } // Test WDT Expiration - if (boot_count == BEFORE_FIRST_NMI_FAILURE) { run_nmi_test(NO_MASK ); } - else if (boot_count == BEFORE_SECOND_NMI_FAILURE){ check_nmi_test(NO_MASK ); - run_nmi_test(WITH_MASK); } - else if (boot_count == AFTER_SECOND_NMI_FAILURE) { check_nmi_test(WITH_MASK); } + if (boot_count == BEFORE_FIRST_NMI_FAILURE) { run_nmi_test(NO_MASK ); } + else if (boot_count == BEFORE_SECOND_NMI_FAILURE){ check_nmi_test(NO_MASK ); + run_nmi_test(WITH_MASK); } + else if (boot_count == BEFORE_THIRD_NMI_FAILURE) { check_nmi_test(WITH_MASK); + // Test NMI from Masked ICCM ECC through LSU + run_iccm_sram_ecc(WITH_MASK, FROM_LSU); } + else if (boot_count == AFTER_THIRD_NMI_FAILURE) { check_iccm_sram_ecc(WITH_MASK, FROM_LSU); } // Test Mailbox Protocol Violations (no reset expected) - if (boot_count == AFTER_SECOND_NMI_FAILURE) { run_mbox_no_lock_error ( NO_MASK); - check_mbox_no_lock_error ( NO_MASK); + if (boot_count == AFTER_THIRD_NMI_FAILURE) { run_mbox_no_lock_error ( NO_MASK); + check_mbox_no_lock_error ( NO_MASK); run_mbox_ooo_error ( NO_MASK); check_mbox_ooo_error ( NO_MASK); run_mbox_no_lock_error (WITH_MASK); @@ -1074,7 +1226,9 @@ void main(void) { // Final Report VPRINTF(MEDIUM, "Eval test progress...\n"); for (enum test_list tests = 0; tests < TEST_COUNT; tests++) { - if (test_progress_g[tests] != RUN_AND_PASSED) { + if (test_progress_g[tests] == SKIPPED) { + VPRINTF(WARNING, "Test [%d] skipped!\n", tests); + } else if (test_progress_g[tests] != RUN_AND_PASSED) { VPRINTF(ERROR, "Test [%d] failed! Progress: %d\n", tests, test_progress_g[tests]); test_fail = 1; } diff --git a/src/riscv_core/veer_el2/rtl/el2_veer.sv b/src/riscv_core/veer_el2/rtl/el2_veer.sv index 1ade17502..39590a63e 100644 --- a/src/riscv_core/veer_el2/rtl/el2_veer.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer.sv @@ -400,6 +400,7 @@ import el2_pkg::*; logic ifu_pmu_instr_aligned; logic ifu_ic_error_start; logic ifu_iccm_rd_ecc_single_err; + logic cptra_iccm_dma_rd_ecc_single_err; logic cptra_iccm_rd_ecc_double_err; logic lsu_axi_awready_ahb; @@ -884,7 +885,7 @@ import el2_pkg::*; .* ); - assign cptra_iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err; + assign cptra_iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || cptra_iccm_dma_rd_ecc_single_err; assign cptra_iccm_ecc_double_error = cptra_iccm_rd_ecc_double_err; diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv index ddd429b1d..0c1ed5f18 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv @@ -150,6 +150,7 @@ import el2_pkg::*; input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM. output logic ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error. + output logic cptra_iccm_dma_rd_ecc_single_err, // Active DMA access has a single ICCM ecc error. output logic cptra_iccm_rd_ecc_double_err, // Output added for Caliptra reporting // Perf counter sigs @@ -248,6 +249,8 @@ import el2_pkg::*; logic ifc_fetch_req_f; logic ifc_fetch_req_f_raw; logic [1:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error. + logic iccm_dma_rd_ecc_single_err; // Active DMA access has a single ICCM ecc error. + logic iccm_dma_rd_ecc_double_err; // Active DMA access has a double ICCM ecc error. logic ifu_async_error_start; @@ -282,7 +285,8 @@ import el2_pkg::*; assign ifu_bp_inst_mask_f = 1'b1; end - assign cptra_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err; + assign cptra_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err; + assign cptra_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err; // aligner diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv index 0d267f27e..99d537696 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv @@ -164,6 +164,8 @@ import el2_pkg::*; output logic [1:0] ic_access_fault_type_f, // Access fault types output logic iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error. output logic [1:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc error. + output logic iccm_dma_rd_ecc_single_err, // Active DMA access has a single ICCM ecc error. + output logic iccm_dma_rd_ecc_double_err, // Active DMA access has a double ICCM ecc error. output logic ic_error_start, // This has any I$ errors ( data/tag/ecc/parity ) output logic ifu_async_error_start, // Or of the sb iccm, and all the icache errors sent to aligner to stop @@ -1275,6 +1277,8 @@ ifc_dma_access_ok_prev,dma_iccm_req_f}) assign iccm_rw_addr[pt.ICCM_BITS-1:1] = ( ifc_dma_access_q_ok & dma_iccm_req & ~iccm_correct_ecc) ? dma_mem_addr[pt.ICCM_BITS-1:1] : (~(ifc_dma_access_q_ok & dma_iccm_req) & iccm_correct_ecc) ? {iccm_ecc_corr_index_ff[pt.ICCM_BITS-1:2],1'b0} : ifc_fetch_addr_bf[pt.ICCM_BITS-1:1] ; + assign iccm_dma_rd_ecc_single_err = iccm_dma_sb_error; + assign iccm_dma_rd_ecc_double_err = iccm_dma_rvalid && iccm_dma_ecc_error; diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh index b886577f2..16f79abe4 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh @@ -130,7 +130,7 @@ task soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence::mbox_do_random_reg_w end begin mainline.await(); - configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(dly % 25); + configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks((dly % 25)+1); end join_any