From ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb Mon Sep 17 00:00:00 2001 From: Mojtaba Bisheh-Niasar <102058313+mojtaba-bisheh@users.noreply.github.com> Date: Fri, 1 Nov 2024 10:57:52 -0700 Subject: [PATCH] fixed rdl bug (#624) * fixed rdl bug * updated sha512 top for tb and uvm * MICROSOFT AUTOMATED PIPELINE: Stamp 'fix-hmac512' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb Whitehead --- .github/workflow_metadata/pr_hash | 2 +- .github/workflow_metadata/pr_timestamp | 2 +- src/hmac/rtl/hmac_reg.rdl | 2 +- src/hmac/rtl/hmac_reg.sv | 2 +- src/hmac/rtl/hmac_reg_uvm.sv | 2 +- src/integration/rtl/caliptra_reg.h | 48 +++++++++---------- src/integration/rtl/caliptra_reg_defines.svh | 48 +++++++++---------- src/sha512/tb/sha512_ctrl_32bit_tb.sv | 10 ---- .../SHA512/tb/testbench/hdl_top.sv | 8 ---- 9 files changed, 53 insertions(+), 71 deletions(-) diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 0d87bf87a..6ca8f129a 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -426fad68287a654b7e3a594868725ab332e504264ad8bbac10778c144ee457056b1b323c81f86d149cefd24f1cd192d9 \ No newline at end of file +b7ce3b14f80888f2274dfad09eff6d9121ca131d4da8685481642253871832b5596daca53ba3d6cf3734cfa470e0fa8e \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index cd035814a..ec22341ab 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1730409602 \ No newline at end of file +1730421807 \ No newline at end of file diff --git a/src/hmac/rtl/hmac_reg.rdl b/src/hmac/rtl/hmac_reg.rdl index 18aacb59c..3c1c3f1b8 100644 --- a/src/hmac/rtl/hmac_reg.rdl +++ b/src/hmac/rtl/hmac_reg.rdl @@ -164,7 +164,7 @@ addrmap hmac_reg { default resetsignal = reset_b; field {desc = "Input lfsr seed field";} LFSR_SEED[32] = 32'h3CAB_FFB0; // a random value - } HMAC512_LFSR_SEED[12] @0x00000130; + } HMAC512_LFSR_SEED[12] @0x00000140; /* ---- HMAC Key Vault Control Reg ---- */ kv_read_ctrl_reg HMAC512_KV_RD_KEY_CTRL @0x00000600; diff --git a/src/hmac/rtl/hmac_reg.sv b/src/hmac/rtl/hmac_reg.sv index 7b4ada0c5..02a70c9e7 100644 --- a/src/hmac/rtl/hmac_reg.sv +++ b/src/hmac/rtl/hmac_reg.sv @@ -127,7 +127,7 @@ module hmac_reg ( decoded_reg_strb.HMAC512_TAG[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.HMAC512_LFSR_SEED[i0] = cpuif_req_masked & (cpuif_addr == 12'h130 + i0*12'h4); + decoded_reg_strb.HMAC512_LFSR_SEED[i0] = cpuif_req_masked & (cpuif_addr == 12'h140 + i0*12'h4); end decoded_reg_strb.HMAC512_KV_RD_KEY_CTRL = cpuif_req_masked & (cpuif_addr == 12'h600); decoded_reg_strb.HMAC512_KV_RD_KEY_STATUS = cpuif_req_masked & (cpuif_addr == 12'h604); diff --git a/src/hmac/rtl/hmac_reg_uvm.sv b/src/hmac/rtl/hmac_reg_uvm.sv index 8a98349a5..c68d7413c 100644 --- a/src/hmac/rtl/hmac_reg_uvm.sv +++ b/src/hmac/rtl/hmac_reg_uvm.sv @@ -1239,7 +1239,7 @@ package hmac_reg_uvm; this.HMAC512_LFSR_SEED[i0].configure(this); this.HMAC512_LFSR_SEED[i0].build(); - this.default_map.add_reg(this.HMAC512_LFSR_SEED[i0], 'h130 + i0*'h4); + this.default_map.add_reg(this.HMAC512_LFSR_SEED[i0], 'h140 + i0*'h4); end this.HMAC512_KV_RD_KEY_CTRL = new("HMAC512_KV_RD_KEY_CTRL"); this.HMAC512_KV_RD_KEY_CTRL.configure(this); diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index aa1d5ca02..d783b7a07 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -712,30 +712,30 @@ #define HMAC_REG_HMAC512_TAG_14 (0x138) #define CLP_HMAC_REG_HMAC512_TAG_15 (0x1001013c) #define HMAC_REG_HMAC512_TAG_15 (0x13c) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_0 (0x10010130) -#define HMAC_REG_HMAC512_LFSR_SEED_0 (0x130) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_1 (0x10010134) -#define HMAC_REG_HMAC512_LFSR_SEED_1 (0x134) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_2 (0x10010138) -#define HMAC_REG_HMAC512_LFSR_SEED_2 (0x138) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_3 (0x1001013c) -#define HMAC_REG_HMAC512_LFSR_SEED_3 (0x13c) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_4 (0x10010140) -#define HMAC_REG_HMAC512_LFSR_SEED_4 (0x140) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_5 (0x10010144) -#define HMAC_REG_HMAC512_LFSR_SEED_5 (0x144) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_6 (0x10010148) -#define HMAC_REG_HMAC512_LFSR_SEED_6 (0x148) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_7 (0x1001014c) -#define HMAC_REG_HMAC512_LFSR_SEED_7 (0x14c) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_8 (0x10010150) -#define HMAC_REG_HMAC512_LFSR_SEED_8 (0x150) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_9 (0x10010154) -#define HMAC_REG_HMAC512_LFSR_SEED_9 (0x154) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_10 (0x10010158) -#define HMAC_REG_HMAC512_LFSR_SEED_10 (0x158) -#define CLP_HMAC_REG_HMAC512_LFSR_SEED_11 (0x1001015c) -#define HMAC_REG_HMAC512_LFSR_SEED_11 (0x15c) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_0 (0x10010140) +#define HMAC_REG_HMAC512_LFSR_SEED_0 (0x140) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_1 (0x10010144) +#define HMAC_REG_HMAC512_LFSR_SEED_1 (0x144) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_2 (0x10010148) +#define HMAC_REG_HMAC512_LFSR_SEED_2 (0x148) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_3 (0x1001014c) +#define HMAC_REG_HMAC512_LFSR_SEED_3 (0x14c) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_4 (0x10010150) +#define HMAC_REG_HMAC512_LFSR_SEED_4 (0x150) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_5 (0x10010154) +#define HMAC_REG_HMAC512_LFSR_SEED_5 (0x154) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_6 (0x10010158) +#define HMAC_REG_HMAC512_LFSR_SEED_6 (0x158) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_7 (0x1001015c) +#define HMAC_REG_HMAC512_LFSR_SEED_7 (0x15c) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_8 (0x10010160) +#define HMAC_REG_HMAC512_LFSR_SEED_8 (0x160) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_9 (0x10010164) +#define HMAC_REG_HMAC512_LFSR_SEED_9 (0x164) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_10 (0x10010168) +#define HMAC_REG_HMAC512_LFSR_SEED_10 (0x168) +#define CLP_HMAC_REG_HMAC512_LFSR_SEED_11 (0x1001016c) +#define HMAC_REG_HMAC512_LFSR_SEED_11 (0x16c) #define CLP_HMAC_REG_HMAC512_KV_RD_KEY_CTRL (0x10010600) #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL (0x600) #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_LOW (0) diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index 62df7e76f..e3aadea0a 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -712,30 +712,30 @@ `define HMAC_REG_HMAC512_TAG_14 (32'h138) `define CLP_HMAC_REG_HMAC512_TAG_15 (32'h1001013c) `define HMAC_REG_HMAC512_TAG_15 (32'h13c) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_0 (32'h10010130) -`define HMAC_REG_HMAC512_LFSR_SEED_0 (32'h130) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_1 (32'h10010134) -`define HMAC_REG_HMAC512_LFSR_SEED_1 (32'h134) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_2 (32'h10010138) -`define HMAC_REG_HMAC512_LFSR_SEED_2 (32'h138) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_3 (32'h1001013c) -`define HMAC_REG_HMAC512_LFSR_SEED_3 (32'h13c) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_4 (32'h10010140) -`define HMAC_REG_HMAC512_LFSR_SEED_4 (32'h140) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_5 (32'h10010144) -`define HMAC_REG_HMAC512_LFSR_SEED_5 (32'h144) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_6 (32'h10010148) -`define HMAC_REG_HMAC512_LFSR_SEED_6 (32'h148) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_7 (32'h1001014c) -`define HMAC_REG_HMAC512_LFSR_SEED_7 (32'h14c) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_8 (32'h10010150) -`define HMAC_REG_HMAC512_LFSR_SEED_8 (32'h150) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_9 (32'h10010154) -`define HMAC_REG_HMAC512_LFSR_SEED_9 (32'h154) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_10 (32'h10010158) -`define HMAC_REG_HMAC512_LFSR_SEED_10 (32'h158) -`define CLP_HMAC_REG_HMAC512_LFSR_SEED_11 (32'h1001015c) -`define HMAC_REG_HMAC512_LFSR_SEED_11 (32'h15c) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_0 (32'h10010140) +`define HMAC_REG_HMAC512_LFSR_SEED_0 (32'h140) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_1 (32'h10010144) +`define HMAC_REG_HMAC512_LFSR_SEED_1 (32'h144) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_2 (32'h10010148) +`define HMAC_REG_HMAC512_LFSR_SEED_2 (32'h148) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_3 (32'h1001014c) +`define HMAC_REG_HMAC512_LFSR_SEED_3 (32'h14c) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_4 (32'h10010150) +`define HMAC_REG_HMAC512_LFSR_SEED_4 (32'h150) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_5 (32'h10010154) +`define HMAC_REG_HMAC512_LFSR_SEED_5 (32'h154) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_6 (32'h10010158) +`define HMAC_REG_HMAC512_LFSR_SEED_6 (32'h158) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_7 (32'h1001015c) +`define HMAC_REG_HMAC512_LFSR_SEED_7 (32'h15c) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_8 (32'h10010160) +`define HMAC_REG_HMAC512_LFSR_SEED_8 (32'h160) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_9 (32'h10010164) +`define HMAC_REG_HMAC512_LFSR_SEED_9 (32'h164) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_10 (32'h10010168) +`define HMAC_REG_HMAC512_LFSR_SEED_10 (32'h168) +`define CLP_HMAC_REG_HMAC512_LFSR_SEED_11 (32'h1001016c) +`define HMAC_REG_HMAC512_LFSR_SEED_11 (32'h16c) `define CLP_HMAC_REG_HMAC512_KV_RD_KEY_CTRL (32'h10010600) `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL (32'h600) `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_LOW (0) diff --git a/src/sha512/tb/sha512_ctrl_32bit_tb.sv b/src/sha512/tb/sha512_ctrl_32bit_tb.sv index f49058ae5..b62bbb224 100644 --- a/src/sha512/tb/sha512_ctrl_32bit_tb.sv +++ b/src/sha512/tb/sha512_ctrl_32bit_tb.sv @@ -77,10 +77,6 @@ module sha512_ctrl_32bit_tb wire hreadyout_o_tb; wire [AHB_DATA_WIDTH-1:0] hrdata_o_tb; - kv_read_t kv_read_tb; - kv_write_t kv_write_tb; - kv_rd_resp_t kv_rd_resp_tb; - kv_wr_resp_t kv_wr_resp_tb; pv_read_t pv_read_tb; pv_write_t pv_write_tb; pv_rd_resp_t pv_rd_resp_tb; @@ -120,10 +116,6 @@ module sha512_ctrl_32bit_tb .hreadyout_o(hreadyout_o_tb), .hrdata_o(hrdata_o_tb), - .kv_read(kv_read_tb), - .kv_write(kv_write_tb), - .kv_rd_resp(kv_rd_resp_tb), - .kv_wr_resp(kv_wr_resp_tb), .pcr_signing_hash(pcr_signing_hash_tb), .pv_read(pv_read_tb), .pv_rd_resp(pv_rd_resp_tb), @@ -200,8 +192,6 @@ module sha512_ctrl_32bit_tb htrans_i_tb = AHB_HTRANS_IDLE; hsize_i_tb = 3'b011; - kv_rd_resp_tb = '0; - kv_wr_resp_tb = '0; pv_wr_resp_tb = '0; pv_rd_resp_tb = '0; end diff --git a/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv b/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv index 6c0b3c384..35d320db1 100644 --- a/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv +++ b/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv @@ -86,13 +86,9 @@ import pv_defines_pkg::*; // Instantiate your DUT here // These DUT's instantiated to show verilog and vhdl instantiation -var kv_rd_resp_t kv_rd_resp; -var kv_wr_resp_t kv_wr_resp; var pv_rd_resp_t pv_rd_resp; var pv_wr_resp_t pv_wr_resp; initial begin - kv_rd_resp = '{default:0}; - kv_wr_resp = '{default:0}; pv_rd_resp = '{default:0}; pv_wr_resp = '{default:0}; end @@ -117,10 +113,6 @@ end .hresp_o(SHA512_out_agent_bus.hresp), .hreadyout_o(SHA512_out_agent_bus.hreadyout), .hrdata_o(SHA512_out_agent_bus.hrdata), - .kv_read (), - .kv_write (), - .kv_rd_resp(kv_rd_resp), - .kv_wr_resp(kv_wr_resp), .pv_read (), .pv_write (), .pv_rd_resp(pv_rd_resp),