From b4737939608166b510d50dbac48996a46384df4f Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Thu, 24 Aug 2023 13:56:15 +0200 Subject: [PATCH 1/5] Add test for Mailbox JTAG accesses with clock gating Internal-tag: [#47908] --- .github/workflows/interactive-debugging.yml | 16 +++ .../test_suites/infinite_loop/common.tcl | 54 +++++++++ .../test_suites/infinite_loop/infinite_loop.s | 24 +++- .../test_suites/infinite_loop/jtag_cg.tcl | 107 ++++++++++++++++++ .../infinite_loop/peripheral_access.tcl | 21 +--- .../infinite_loop/regdump_golden.txt | 2 +- 6 files changed, 204 insertions(+), 20 deletions(-) create mode 100644 src/integration/test_suites/infinite_loop/common.tcl create mode 100644 src/integration/test_suites/infinite_loop/jtag_cg.tcl diff --git a/.github/workflows/interactive-debugging.yml b/.github/workflows/interactive-debugging.yml index 570323a50..8415e094d 100644 --- a/.github/workflows/interactive-debugging.yml +++ b/.github/workflows/interactive-debugging.yml @@ -315,3 +315,19 @@ jobs: ${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \ -f board/caliptra-verilator-rst.cfg \ -f ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop/peripheral_access.tcl + + - name: Build Verilated simulation + run: | + export CALIPTRA_ROOT=$(pwd) + rm -rf run/* + make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 \ + OBJCACHE="" CC=gcc CXX=g++ LINK=g++ + make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex TESTNAME=infinite_loop + + - name: Test JTAG access with clock gating + run: | + export CALIPTRA_ROOT=$(pwd) + cd run + ${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \ + -f board/caliptra-verilator.cfg \ + -f ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop/jtag_cg.tcl diff --git a/src/integration/test_suites/infinite_loop/common.tcl b/src/integration/test_suites/infinite_loop/common.tcl new file mode 100644 index 000000000..a95351407 --- /dev/null +++ b/src/integration/test_suites/infinite_loop/common.tcl @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +proc compare {x y} { + puts "'$x' vs. '$y'" + + if {[llength $y] != [llength $y]} { + puts "length mismatch!" + return -1 + } + + for {set i 0} {$i < [llength $x]} {incr i} { + if {[lindex $x $i] != [lindex $y $i]} { + puts "item $i mismatch!" + return -1 + } + } + + return 0 +} + +set STDOUT 0x300300cc + +set mbox_clk_gate_en 0xf2 +set mbox_lock_debug 0xf9 +set mbox_unlock_debug 0xfa + +set mbox_lock_mem_addr 0x30020000 +set mbox_user_mem_addr 0x30020004 +set mbox_cmd_mem_addr 0x30020008 +set mbox_dlen_mem_addr 0x3002000C +set mbox_datain_mem_addr 0x30020010 +set mbox_dataout_mem_addr 0x30020014 +set mbox_execute_mem_addr 0x30020018 +set mbox_status_mem_addr 0x3002001C +set mbox_unlock_mem_addr 0x30020020 + +set mbox_dlen_dmi_addr 0x50 +set mbox_dout_dmi_addr 0x51 +set mbox_status_dmi_addr 0x52 + +set dmstatus_addr 0x11 + diff --git a/src/integration/test_suites/infinite_loop/infinite_loop.s b/src/integration/test_suites/infinite_loop/infinite_loop.s index 4a3753157..fae20f79c 100644 --- a/src/integration/test_suites/infinite_loop/infinite_loop.s +++ b/src/integration/test_suites/infinite_loop/infinite_loop.s @@ -17,6 +17,13 @@ #include "caliptra_defines.h" .set mfdc, 0x7f9 +.set mfdht, 0x7ce +.set mstatus, 0x300 +.set mitcnt0, 0x7d2 +.set mitb0, 0x7d3 +.set mitctl0, 0x7d4 +.set mie, 0x304 +.set mpmc, 0x7c6 // Code to execute .section .text @@ -39,6 +46,7 @@ _start: li x6, 0xA0A0A0A0 li x7, 0x00FF00FF li x8, 0xCC00CC00 + li s1, 0xFEEDABED // Writing 0 to this register initiates CPU halt // Simple infinite loop program with inner and outer loop li t3, 0 @@ -46,9 +54,23 @@ outer: addi t3, t3, 1 li t4, 123 inner: + beq s1, zero, halt_cpu addi t4, t4, -1 bne t4, zero, inner - jal x0, outer + j outer + +halt_cpu: + // Set mit0 and halt core + li t5, 0xf0 + li t6, 0x20000800 + csrwi mitcnt0, 0x00 // Internal timer 0 counter + csrw mitb0, t5 // Internal timer 0 boundary + csrwi mitctl0, 0x01 // Internal timer 0 enable + csrw mie, t6 // Internal timer 0 local interrupt enable + csrwi mstatus, 0x08 // Internal timer 0 global interrupt enable + csrwi mpmc, 0x03 // Initiate core halt with disable on mit0 interrupt + li s1, 0xFEEDABED // Indicate halt init + j outer // Return to infinite loop .section .dccm .global stdout diff --git a/src/integration/test_suites/infinite_loop/jtag_cg.tcl b/src/integration/test_suites/infinite_loop/jtag_cg.tcl new file mode 100644 index 000000000..037e3c178 --- /dev/null +++ b/src/integration/test_suites/infinite_loop/jtag_cg.tcl @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +init + +set script_dir [file dirname [info script]] +source [file join $script_dir common.tcl] + +array set data { + 0 0x12345678 + 1 0xABBACDDC + 2 0xDEADBEEF + 3 0xFEEDBABE + 4 0xBEACCAEB +} +set dlen_words [array size data] +set dlen_bytes [expr {$dlen_words * 4}] + +puts "Read Debug Module Status Register..." +set val [riscv dmi_read $dmstatus_addr] +puts "dmstatus: $val" +if {($val & 0x00000c00) == 0} { + echo "The hart is halted!" + shutdown error +} +puts "" + +riscv set_mem_access sysbus +puts "Enable clock gating..." +write_memory $STDOUT 32 $mbox_clk_gate_en phys + +puts "Set debug security state to locked..." +write_memory $STDOUT 32 $mbox_lock_debug phys +puts "" + +puts "Retrieve mailbox lock..." +set golden {0x0} +set actual [read_memory $mbox_lock_mem_addr 32 1 phys] +if {[compare $actual $golden] != 0} { + shutdown error +} +puts "" + +puts "Write few bytes to mailbox..." +write_memory $mbox_cmd_mem_addr 32 0x12345678 phys +write_memory $mbox_dlen_mem_addr 32 $dlen_bytes phys +for {set i 0} {$i < $dlen_words} {incr i} { + write_memory $mbox_datain_mem_addr 32 $data($i) phys +} +write_memory $mbox_execute_mem_addr 32 1 phys +puts "" + +puts "Read mailbox status..." +set golden {0x100} +set actual [read_memory $mbox_status_mem_addr 32 1 phys] +if {[compare $actual $golden] != 0} { + shutdown error +} +puts "" + +puts "Halt CPU to access its registers..." +halt +puts "Initiate firmware halt (set register s1 to 0)..." +set_reg {s1 0} +puts "Resume CPU..." +resume +puts "" + +puts "Read Debug Module Status Register..." +set val [riscv dmi_read $dmstatus_addr] +puts "dmstatus: $val" +if {($val & 0x00000c00) == 0} { + echo "The hart is halted!" + shutdown error +} +puts "" + +puts "Read mailbox status and dlen..." +set golden $dlen_bytes +set actual [riscv dmi_read $mbox_dlen_dmi_addr] +if {[compare $actual $golden] != 0} { + shutdown error +} +puts "" + +puts "Read mailbox data..." +for {set i 0} {$i < $dlen_words} {incr i} { + set golden $data($i) + set actual [riscv dmi_read $mbox_dout_dmi_addr] + if {[compare $actual $golden] != 0} { + shutdown error + } +} + +# Success +shutdown diff --git a/src/integration/test_suites/infinite_loop/peripheral_access.tcl b/src/integration/test_suites/infinite_loop/peripheral_access.tcl index d6bf70d37..c2dbcbc16 100644 --- a/src/integration/test_suites/infinite_loop/peripheral_access.tcl +++ b/src/integration/test_suites/infinite_loop/peripheral_access.tcl @@ -14,28 +14,13 @@ # init -proc compare {x y} { - puts "'$x' vs. '$y'" - - if {[llength $y] != [llength $y]} { - puts "length mismatch!" - return -1 - } - - for {set i 0} {$i < [llength $x]} {incr i} { - if {[lindex $x $i] != [lindex $y $i]} { - puts "item $i mismatch!" - return -1 - } - } - - return 0 -} +set script_dir [file dirname [info script]] +source [file join $script_dir common.tcl] # Manually read dmstatus and check if the core is actually held in external # reset. In the expected state bits anyunavail allrunning anyrunning allhalted # and anyhalted should be cleared. -set val [riscv dmi_read 0x11] +set val [riscv dmi_read $dmstatus_addr] puts "dmstatus: $val" if { ($val & 0x00000F00) != 0 } { diff --git a/src/integration/test_suites/infinite_loop/regdump_golden.txt b/src/integration/test_suites/infinite_loop/regdump_golden.txt index 27196e7d5..b1913bb9d 100644 --- a/src/integration/test_suites/infinite_loop/regdump_golden.txt +++ b/src/integration/test_suites/infinite_loop/regdump_golden.txt @@ -5,7 +5,7 @@ tp 0xdeadbeef 0xdeadbeef t0 0x5050505 84215045 t1 0xa0a0a0a0 -1600085856 t2 0xff00ff 16711935 -s1 0x0 0 +s1 0xfeedabed -17978387 a0 0x0 0 a1 0x0 0 a2 0x0 0 From 1ce9ea6762bfabca6081a268ecd7d207a74ff9e5 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 14 Nov 2023 16:39:56 +0100 Subject: [PATCH 2/5] Update expected mailbox rdptr value Internal-Tag: [#51338] Signed-off-by: Maciej Kurc --- src/integration/test_suites/infinite_loop/jtag_cg.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/integration/test_suites/infinite_loop/jtag_cg.tcl b/src/integration/test_suites/infinite_loop/jtag_cg.tcl index 037e3c178..26d6f6888 100644 --- a/src/integration/test_suites/infinite_loop/jtag_cg.tcl +++ b/src/integration/test_suites/infinite_loop/jtag_cg.tcl @@ -62,7 +62,7 @@ write_memory $mbox_execute_mem_addr 32 1 phys puts "" puts "Read mailbox status..." -set golden {0x100} +set golden {0x500} set actual [read_memory $mbox_status_mem_addr 32 1 phys] if {[compare $actual $golden] != 0} { shutdown error From 986b12ae2a2324fd198b81f88536fcbbd6c6be5c Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 14 Nov 2023 11:12:38 +0100 Subject: [PATCH 3/5] Remove support for JTAG read IDCODE instruction from VeeR TAP Internal-Tag: [#51306] Signed-off-by: Maciej Kurc --- src/integration/rtl/caliptra_top.sv | 5 ----- src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v | 2 -- src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v | 14 +------------- src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv | 2 -- src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv | 5 ----- 5 files changed, 1 insertion(+), 27 deletions(-) diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 3937626d9..353e7320e 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -354,16 +354,12 @@ end // RTL instance //=========================================================================- //FIXME TIE OFFS -logic [31:0] jtag_id; logic [31:0] reset_vector; logic [31:0] nmi_vector; logic nmi_int; logic soft_int; logic timer_int; -assign jtag_id[31:28] = 4'b1; -assign jtag_id[27:12] = '0; -assign jtag_id[11:1] = 11'h45; assign reset_vector = `RV_RESET_VEC; assign soft_int = 1'b0; @@ -415,7 +411,6 @@ el2_veer_wrapper rvtop ( .rst_vec ( reset_vector[31:1]), .nmi_int ( nmi_int ), .nmi_vec ( nmi_vector[31:1]), - .jtag_id ( jtag_id[31:1]), .haddr ( ic_haddr ), .hburst ( ic_hburst ), diff --git a/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v b/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v index d9fd74104..39fdccde2 100644 --- a/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v +++ b/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v @@ -34,7 +34,6 @@ module dmi_wrapper( // Processor Signals input core_rst_n, // Core reset input core_clk, // Core clock - input [31:1] jtag_id, // JTAG ID input [31:0] rd_data, // 32 bit Read data from Processor output [31:0] reg_wr_data, // 32 bit Write data to Processor output [6:0] reg_wr_addr, // 7 bit reg address to Processor @@ -70,7 +69,6 @@ module dmi_wrapper( .idle(3'h0), // no need to wait to sample data .dmi_stat(2'b0), // no need to wait or error possible .version(4'h1), // debug spec 0.13 compliant - .jtag_id(jtag_id), .dmi_hard_reset(dmi_hard_reset), .dmi_reset(dmireset) ); diff --git a/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v b/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v index 2553575ff..ef872999f 100644 --- a/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v +++ b/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v @@ -37,13 +37,6 @@ output reg dmi_hard_reset, input [2:0] idle, input [1:0] dmi_stat, -/* --- revisionCode : 4'h0; --- manufacturersIdCode : 11'h45; --- deviceIdCode : 16'h0001; --- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB] -*/ -input [31:1] jtag_id, input [3:0] version ); @@ -67,7 +60,6 @@ wire pause_ir ; wire update_ir ; wire capture_ir; wire[1:0] dr_en; -wire devid_sel; wire [5:0] abits; assign abits = AWIDTH[5:0]; @@ -143,7 +135,6 @@ always @ (negedge tck or negedge trst) begin end -assign devid_sel = ir == 5'b00001; assign dr_en[0] = ir == 5'b10000; assign dr_en[1] = ir == 5'b10001; @@ -166,9 +157,7 @@ always_comb begin shift_dr: begin case(1) dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]}; - - dr_en[0], - devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; + dr_en[0]: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass endcase end @@ -177,7 +166,6 @@ always_comb begin case(1) dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version}; dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status}; - devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1}; endcase end shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]}; diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv index cec4d24cf..d7d1d3841 100755 --- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv @@ -33,7 +33,6 @@ import soc_ifc_pkg::*; input logic [31:1] rst_vec, input logic nmi_int, input logic [31:1] nmi_vec, - input logic [31:1] jtag_id, output logic [31:0] trace_rv_i_insn_ip, @@ -724,7 +723,6 @@ import soc_ifc_pkg::*; // Processor Signals .core_rst_n (dbg_rst_l), // Debug reset, active low .core_clk (clk), // Core clock - .jtag_id (jtag_id), // JTAG ID .rd_data (dmi_reg_rdata_PostQ), // Read data from Processor .reg_wr_data (dmi_reg_wdata), // Write data to Processor .reg_wr_addr (dmi_reg_addr), // Write address to Processor diff --git a/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv b/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv index d979631e8..889c3735a 100755 --- a/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv +++ b/src/riscv_core/veer_el2/tb/el2_veer_wrapper_tb.sv @@ -28,7 +28,6 @@ module el2_veer_wrapper_tb ( input bit core_clk ); logic [31:0] reset_vector; logic [31:0] nmi_vector; - logic [31:1] jtag_id; logic [31:0] ic_haddr ; logic [2:0] ic_hburst ; @@ -411,9 +410,6 @@ module el2_veer_wrapper_tb ( input bit core_clk ); abi_reg[30] = "t5"; abi_reg[31] = "t6"; // tie offs - jtag_id[31:28] = 4'b1; - jtag_id[27:12] = '0; - jtag_id[11:1] = 11'h45; reset_vector = `RV_RESET_VEC; nmi_vector = 32'hee000000; nmi_int = 0; @@ -448,7 +444,6 @@ el2_veer_wrapper rvtop ( .rst_vec ( reset_vector[31:1]), .nmi_int ( nmi_int ), .nmi_vec ( nmi_vector[31:1]), - .jtag_id ( jtag_id[31:1]), `ifdef RV_BUILD_AHB_LITE .haddr ( ic_haddr ), From cf4903dbb222467fabb5a2d80a843fe2b673a252 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 14 Nov 2023 12:06:35 +0100 Subject: [PATCH 4/5] Remove expected IDCODE from OpenOCD config Internal-Tag: [#51306] Signed-off-by: Maciej Kurc --- tools/scripts/openocd/target/veer-el2-rst.cfg | 8 +------- tools/scripts/openocd/target/veer-el2.cfg | 8 +------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/tools/scripts/openocd/target/veer-el2-rst.cfg b/tools/scripts/openocd/target/veer-el2-rst.cfg index 0f4c86fde..c90f24266 100644 --- a/tools/scripts/openocd/target/veer-el2-rst.cfg +++ b/tools/scripts/openocd/target/veer-el2-rst.cfg @@ -4,13 +4,7 @@ if { [info exists CHIPNAME] } { set _CHIPNAME riscv } -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1000008b -} - -jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME tap -irlen 5 set _TARGETNAME $_CHIPNAME.tap target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread diff --git a/tools/scripts/openocd/target/veer-el2.cfg b/tools/scripts/openocd/target/veer-el2.cfg index 45374886d..a8c092f2a 100644 --- a/tools/scripts/openocd/target/veer-el2.cfg +++ b/tools/scripts/openocd/target/veer-el2.cfg @@ -4,13 +4,7 @@ if { [info exists CHIPNAME] } { set _CHIPNAME riscv } -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1000008b -} - -jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME tap -irlen 5 set _TARGETNAME $_CHIPNAME.tap target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread From 63a40f06c414bc67ca981f20cd572c71bff1a735 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 30 Nov 2023 23:58:21 +0100 Subject: [PATCH 5/5] Fix VCS invocation in Makefile so that DPI functions get compiled. (#306) Internal-Tag: [#51415] Signed-off-by: Maciej Kurc --- tools/scripts/Makefile | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) mode change 100755 => 100644 tools/scripts/Makefile diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile old mode 100755 new mode 100644 index 6a7efb724..1b007812f --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -165,33 +165,35 @@ CFLAGS += -std=c++17 # compiles), or -O for balance. VERILATOR_MAKE_FLAGS = OPT_FAST="-Os" -# Testbench libs -VERILATOR_TB_LIBS = jtagdpi/jtagdpi.c \ - tcp_server/tcp_server.c +# Testbench DPI sources +TB_DPI_SRCS = jtagdpi/jtagdpi.c \ + tcp_server/tcp_server.c + +TB_DPI_INCS := $(addprefix -I$(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(dir $(TB_DPI_SRCS))) +TB_DPI_SRCS := $(addprefix $(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(TB_DPI_SRCS)) # Testbench sources -VERILATOR_TB_SRCS = $(TBDIR)/test_caliptra_top_tb.cpp \ - $(addprefix $(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(VERILATOR_TB_LIBS)) +TB_VERILATOR_SRCS = $(TBDIR)/test_caliptra_top_tb.cpp $(TB_DPI_SRCS) # Testbench defs -VERILATOR_TB_DEFS = +define+CALIPTRA_INTERNAL_QSPI+CALIPTRA_INTERNAL_TRNG+CALIPTRA_INTERNAL_UART +TB_DEFS = +define+CALIPTRA_INTERNAL_QSPI+CALIPTRA_INTERNAL_TRNG+CALIPTRA_INTERNAL_UART # By default debugging (JTAG) is locked in Caliptra. Add "DEBUG_UNLOCKED=1" to # enable it. ifdef DEBUG_UNLOCKED - VERILATOR_TB_DEFS += +define+CALIPTRA_DEBUG_UNLOCKED + TB_DEFS += +define+CALIPTRA_DEBUG_UNLOCKED endif # To enforce holding the RISC-V core in reset add "FORCE_CPU_RESET=1". ifdef FORCE_CPU_RESET - VERILATOR_TB_DEFS += +define+CALIPTRA_FORCE_CPU_RESET + TB_DEFS += +define+CALIPTRA_FORCE_CPU_RESET endif # Run time arguments from command line VERILATOR_RUN_ARGS ?= "" # Add testbench lib include paths -CFLAGS += $(addprefix -I$(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(dir $(VERILATOR_TB_LIBS))) +CFLAGS += $(TB_DPI_INCS) # Targets all: clean verilator @@ -207,8 +209,8 @@ clean_fw: ############ Model Builds ############################### -verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(VERILATOR_TB_SRCS) - $(VERILATOR) $(VERILATOR_TB_SRCS) --cc -CFLAGS "$(CFLAGS)" \ +verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_VERILATOR_SRCS) + $(VERILATOR) $(TB_VERILATOR_SRCS) --cc -CFLAGS "$(CFLAGS)" \ +libext+.v+.sv +define+RV_OPENSOURCE \ --timescale 1ns/1ps \ --timing \ @@ -217,16 +219,16 @@ verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(VERILATOR_TB_SRCS) -f $(TBDIR)/../config/caliptra_top_tb.vf --top-module caliptra_top_tb \ -f $(TBDIR)/../config/caliptra_top_tb.vlt \ -exe test_caliptra_top_tb.cpp --autoflush $(VERILATOR_DEBUG) \ - $(VERILATOR_TB_DEFS) + $(TB_DEFS) $(MAKE) -j`nproc` -e -C obj_dir/ -f Vcaliptra_top_tb.mk $(VERILATOR_MAKE_FLAGS) VM_PARALLEL_BUILDS=1 touch verilator-build -vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h +vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_DPI_SRCS) vlogan -full64 -sverilog -kdb -incr_vlogan +lint=IA_CHECKFAIL -assert svaext \ - +define+CLP_ASSERT_ON -noinherit_timescale=1ns/1ps \ + +define+CLP_ASSERT_ON $(TB_DEFS) -noinherit_timescale=1ns/1ps \ -f $(TBDIR)/../config/caliptra_top_tb.vf vcs -full64 -kdb -lca -debug_access+all -j8 +vcs+lic+wait -partcomp -fastpartcomp=j8 \ - -assert enable_hier caliptra_top_tb -o simv.caliptra_top_tb + -assert enable_hier caliptra_top_tb -o simv.caliptra_top_tb +dpi -cflags "$(TB_DPI_INCS)" $(TB_DPI_SRCS) ############ TEST Simulation ###############################