diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 948a01a35..11d1153fe 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -e3bfed2d8c8064b0c6f21410b619238538c01ad39f9763b67af8a958799d38c578cf4a9ac278bad8e2c0f4d471998b1a \ No newline at end of file +d5e1ab0f36f14576ade1380aa9c6985bbe6762062f358409e3be50ae7529bde17f5a9610cd26f37bef77679b69befb0c \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index 8a5343a92..83f7710c3 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1726604628 \ No newline at end of file +1727315247 \ No newline at end of file diff --git a/README.md b/README.md index 33f7fe153..794dbc847 100644 --- a/README.md +++ b/README.md @@ -14,8 +14,16 @@ See the License for the specific language governing permissions and
limitations under the License.*_
# **Caliptra Hands-On Guide** # -_*Last Update: 2024/07/02*_ +_*Last Update: 2024/09/20*_ +:warning:**$${\textsf{\color{red}DISCLAIMER:\ This\ repository\ is\ under\ active\ development\ towards\ a\ Gen2\ release\ on\ branch\ main.}}$$**
+                            **$${\textsf{\color{red}Functionality\ or\ quality\ is\ not\ guaranteed.}}$$**
+                            **$${\textsf{\color{red}Do\ not\ integrate\ this\ into\ a\ production\ design!}}$$**
+ +## **Release Consumption and Integration** ## +Prior official releases are available at: https://github.com/chipsalliance/caliptra-rtl/releases
+Releases are published as a tag, and also contain downloadable assets (which should not be used). +Instead of downloading the assets attached to the published release, integrators should consume Caliptra releases by pulling code from the repository at the associated tag, due to https://github.com/chipsalliance/caliptra-rtl/issues/471. ## **Tools Used** ## diff --git a/src/axi/config/axi_dma.vf b/src/axi/config/axi_dma.vf index 48d23fe90..24dc6200c 100644 --- a/src/axi/config/axi_dma.vf +++ b/src/axi/config/axi_dma.vf @@ -1,6 +1,9 @@ +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh @@ -14,9 +17,53 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv diff --git a/src/axi/config/compile.yml b/src/axi/config/compile.yml index f79ba4ac6..d0ccd4b9c 100644 --- a/src/axi/config/compile.yml +++ b/src/axi/config/compile.yml @@ -45,6 +45,7 @@ provides: [axi_dma] schema_version: 2.4.0 requires: - libs + - caliptra_prim - axi_pkg targets: rtl: diff --git a/src/axi/rtl/axi_dma_ctrl.sv b/src/axi/rtl/axi_dma_ctrl.sv index 5792c1e27..a454606a2 100644 --- a/src/axi/rtl/axi_dma_ctrl.sv +++ b/src/axi/rtl/axi_dma_ctrl.sv @@ -74,6 +74,7 @@ import soc_ifc_pkg::*; // Imports // // --------------------------------------- // import axi_dma_reg_pkg::*; + `include "caliptra_prim_assert.sv" // --------------------------------------- // @@ -151,12 +152,14 @@ import soc_ifc_pkg::*; logic [DW-1:0] r_data_mask; logic [AW-1:0] src_addr, dst_addr; - logic [$clog2(FIFO_BC/BC+1)-1:0] rd_credits; - logic [$clog2(FIFO_BC/BC+1)-1:0] wr_credits; + logic [FIFO_BW-1:0] rd_credits; + logic [FIFO_BW-1:0] wr_credits; logic [AXI_LEN_BC_WIDTH-1:0] block_size_mask; // 1's based counters logic [31:0] rd_bytes_requested; + logic rd_bytes_rem_thresh; // Number of read bytes remaining to be requested is lower than the threshold of MAX_BLOCK_SIZE logic [31:0] wr_bytes_requested; + logic wr_bytes_rem_thresh; // Number of write bytes remaining to be requested is lower than the threshold of MAX_BLOCK_SIZE logic [AXI_LEN_BC_WIDTH-1:0] rd_align_req_byte_count; // byte-count in a request until nearest AXI boundary logic [AXI_LEN_BC_WIDTH-1:0] rd_final_req_byte_count; // byte-count in the final request, which may be smaller than a typical request logic [AXI_LEN_BC_WIDTH-1:0] rd_req_byte_count; // byte-count calculated for the current read request @@ -263,7 +266,7 @@ import soc_ifc_pkg::*; // Command Decode // // --------------------------------------- // generate - if (AW < 32) begin + if (AW <= 32) begin always_comb begin src_addr = hwif_out.src_addr_l.addr_l.value[AW-1:0]; dst_addr = hwif_out.dst_addr_l.addr_l.value[AW-1:0]; @@ -455,25 +458,27 @@ import soc_ifc_pkg::*; always_comb block_size_mask = hwif_out.block_size.size.value - 1; always_comb begin - rd_align_req_byte_count = ~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value) ? (MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) : - hwif_out.block_size.size.value - (r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask); - rd_final_req_byte_count = hwif_out.byte_count.count.value - rd_bytes_requested; + rd_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? AXI_LEN_BC_WIDTH'(MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) : + AXI_LEN_BC_WIDTH'(hwif_out.block_size.size.value - (AXI_LEN_BC_WIDTH'(r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask)); + rd_final_req_byte_count = rd_bytes_rem_thresh ? AXI_LEN_BC_WIDTH'(hwif_out.byte_count.count.value - rd_bytes_requested) : + {AXI_LEN_BC_WIDTH{1'b1}}; rd_req_byte_count = rd_final_req_byte_count < rd_align_req_byte_count ? rd_final_req_byte_count : rd_align_req_byte_count; - wr_align_req_byte_count = ~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value) ? (MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) : - hwif_out.block_size.size.value - (w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask); - wr_final_req_byte_count = hwif_out.byte_count.count.value - wr_bytes_requested; + wr_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? AXI_LEN_BC_WIDTH'(MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) : + AXI_LEN_BC_WIDTH'(hwif_out.block_size.size.value - (AXI_LEN_BC_WIDTH'(w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask)); + wr_final_req_byte_count = wr_bytes_rem_thresh ? AXI_LEN_BC_WIDTH'(hwif_out.byte_count.count.value - wr_bytes_requested) : + {AXI_LEN_BC_WIDTH{1'b1}}; wr_req_byte_count = wr_final_req_byte_count < wr_align_req_byte_count ? wr_final_req_byte_count : wr_align_req_byte_count; end always_comb begin - r_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !rd_req_hshake_bypass && (rd_bytes_requested < hwif_out.byte_count.count) && (rd_credits >= rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]) && !rd_req_stall; + r_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !rd_req_hshake_bypass && (rd_bytes_requested < hwif_out.byte_count.count.value) && ((AXI_LEN_BC_WIDTH-BW)'(rd_credits) >= rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]) && !rd_req_stall; r_req_if.addr = src_addr + rd_bytes_requested; r_req_if.byte_len = rd_req_byte_count - AXI_LEN_BC_WIDTH'(BC); r_req_if.fixed = hwif_out.ctrl.rd_fixed.value; r_req_if.lock = 1'b0; // TODO - w_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count) && (wr_credits >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]); + w_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count.value) && ((AXI_LEN_BC_WIDTH-BW)'(wr_credits) >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]); w_req_if.addr = dst_addr + wr_bytes_requested; w_req_if.byte_len = wr_req_byte_count - AXI_LEN_BC_WIDTH'(BC); w_req_if.fixed = hwif_out.ctrl.wr_fixed.value; @@ -508,30 +513,38 @@ import soc_ifc_pkg::*; always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin - rd_bytes_requested <= '0; + rd_bytes_requested <= '0; + rd_bytes_rem_thresh <= 1'b0; end else if (rd_req_hshake) begin - rd_bytes_requested <= rd_bytes_requested + rd_req_byte_count; + rd_bytes_requested <= rd_bytes_requested + rd_req_byte_count; + rd_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (rd_bytes_requested + rd_req_byte_count)) >> AXI_LEN_BC_WIDTH); end else if (mb_dv && !mb_data.write && !mb_hold) begin - rd_bytes_requested <= rd_bytes_requested + BC; + rd_bytes_requested <= rd_bytes_requested + BC; + rd_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (rd_bytes_requested + BC)) >> AXI_LEN_BC_WIDTH); end else if (ctrl_fsm_ps == DMA_IDLE) begin - rd_bytes_requested <= '0; + rd_bytes_requested <= '0; + rd_bytes_rem_thresh <= ~|hwif_out.byte_count.count.value[31:AXI_LEN_BC_WIDTH]; end end always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin - wr_bytes_requested <= '0; + wr_bytes_requested <= '0; + wr_bytes_rem_thresh <= 1'b0; end else if (wr_req_hshake) begin - wr_bytes_requested <= wr_bytes_requested + wr_req_byte_count; + wr_bytes_requested <= wr_bytes_requested + wr_req_byte_count; + wr_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (wr_bytes_requested + wr_req_byte_count)) >> AXI_LEN_BC_WIDTH); end else if (mb_dv && mb_data.write && !mb_hold) begin - wr_bytes_requested <= wr_bytes_requested + BC; + wr_bytes_requested <= wr_bytes_requested + BC; + wr_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (wr_bytes_requested + BC)) >> AXI_LEN_BC_WIDTH); end else if (ctrl_fsm_ps == DMA_IDLE) begin - wr_bytes_requested <= '0; + wr_bytes_requested <= '0; + wr_bytes_rem_thresh <= ~|hwif_out.byte_count.count.value[31:AXI_LEN_BC_WIDTH]; end end @@ -542,11 +555,13 @@ import soc_ifc_pkg::*; else if ((ctrl_fsm_ps == DMA_IDLE) || (rd_req_hshake_bypass)) begin rd_credits <= FIFO_BC/BC; end + // Request byte count is restricted to not exceed the credit capacity + // Assertions (below) enforce a legal byte_count for sims else if (rd_req_hshake && (fifo_r_valid && fifo_r_ready)) begin - rd_credits <= rd_credits + 1 - rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]; + rd_credits <= rd_credits + 1 - FIFO_BW'(rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]); end else if (rd_req_hshake) begin - rd_credits <= rd_credits - rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]; + rd_credits <= rd_credits - FIFO_BW'(rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]); end else if (fifo_r_valid && fifo_r_ready) begin rd_credits <= rd_credits + 1; @@ -560,11 +575,13 @@ import soc_ifc_pkg::*; else if ((ctrl_fsm_ps == DMA_IDLE) || (wr_req_hshake_bypass)) begin wr_credits <= 0; end + // Request byte count is restricted to not exceed the credit capacity + // Assertions (below) enforce a legal byte_count for sims else if (wr_req_hshake && (fifo_w_valid && fifo_w_ready)) begin - wr_credits <= wr_credits + 1 - wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]; + wr_credits <= wr_credits + 1 - FIFO_BW'(wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]); end else if (wr_req_hshake) begin - wr_credits <= wr_credits - wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]; + wr_credits <= wr_credits - FIFO_BW'(wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]); end else if (fifo_w_valid && fifo_w_ready) begin wr_credits <= wr_credits + 1; @@ -694,12 +711,16 @@ import soc_ifc_pkg::*; // Requests must not cross AXI boundary (4KiB) `CALIPTRA_ASSERT(AXI_DMA_VLD_RD_REQ_BND, rd_req_hshake |-> r_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((r_req_if.addr + r_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n) `CALIPTRA_ASSERT(AXI_DMA_VLD_WR_REQ_BND, wr_req_hshake |-> w_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((w_req_if.addr + w_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n) + // Proper configuration `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_32, DW == 32) `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_EQ_MB, DW == MBOX_DATA_W) + // FIFO must have space for all requested data `CALIPTRA_ASSERT(AXI_DMA_LIM_RD_CRED, rd_credits <= FIFO_BC/BC, clk, !rst_n) + `CALIPTRA_ASSERT(AXI_DMA_OFL_RD_CRED, rd_req_hshake |-> rd_req_byte_count <= FIFO_BC, clk, !rst_n) `CALIPTRA_ASSERT(AXI_DMA_MIN_RD_CRED, !((rd_credits < BC) && rd_req_hshake), clk, !rst_n) `CALIPTRA_ASSERT(AXI_DMA_RST_RD_CRED, (ctrl_fsm_ps == DMA_DONE) |-> (rd_credits == FIFO_BC/BC), clk, !rst_n) `CALIPTRA_ASSERT(AXI_DMA_LIM_WR_CRED, wr_credits <= FIFO_BC/BC, clk, !rst_n) + `CALIPTRA_ASSERT(AXI_DMA_UFL_WR_CRED, wr_req_hshake |-> wr_credits >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW], clk, !rst_n) `CALIPTRA_ASSERT(AXI_DMA_MIN_WR_CRED, !((wr_credits < BC) && wr_req_hshake), clk, !rst_n) `CALIPTRA_ASSERT(AXI_DMA_RST_WR_CRED, (ctrl_fsm_ps == DMA_DONE) |-> (wr_credits == 0), clk, !rst_n) diff --git a/src/axi/rtl/axi_if.sv b/src/axi/rtl/axi_if.sv index daa6d45c6..064643a37 100644 --- a/src/axi/rtl/axi_if.sv +++ b/src/axi/rtl/axi_if.sv @@ -16,7 +16,7 @@ // Signals for a standard AXI4 compliant interface // -interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 3, parameter integer UW = 32) (input logic clk, input logic rst_n); +interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 8, parameter integer UW = 32) (input logic clk, input logic rst_n); import axi_pkg::*; @@ -155,6 +155,8 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet input bready ); + // synopsys translate_off + // Tasks `ifdef VERILATOR `define EQ__ = @@ -361,4 +363,6 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet `undef EQ__ `undef TIME_ALGN + // synopsys translate_on + endinterface diff --git a/src/axi/rtl/axi_mgr_rd.sv b/src/axi/rtl/axi_mgr_rd.sv index 5e000fa3a..c00c524bc 100644 --- a/src/axi/rtl/axi_mgr_rd.sv +++ b/src/axi/rtl/axi_mgr_rd.sv @@ -45,6 +45,7 @@ module axi_mgr_rd import axi_pkg::*; #( // --------------------------------------- // // Imports // // --------------------------------------- // + `include "caliptra_prim_assert.sv" // --------------------------------------- // @@ -92,11 +93,10 @@ module axi_mgr_rd import axi_pkg::*; #( .OPT_OUTREG (0 ), // .OPT_PASSTHROUGH(0 ), - .DW ($bits(req_ctx_t)), - .OPT_INITIAL (1'b1) + .DW ($bits(req_ctx_t)) ) i_ctx_skd ( .i_clk (clk ), - .i_reset(!rst_n ), + .i_reset(rst_n ), .i_valid(req_if.valid ), .o_ready(req_if.ready ), .i_data (req_ctx ), @@ -107,13 +107,13 @@ module axi_mgr_rd import axi_pkg::*; #( always_ff@(posedge clk or negedge rst_n) begin if (!rst_n) begin - axi_ctx_sent = 1'b0; + axi_ctx_sent <= 1'b0; end else if (axi_ctx_valid && axi_ctx_ready) begin - axi_ctx_sent = 1'b0; + axi_ctx_sent <= 1'b0; end else if (m_axi_if.arvalid && m_axi_if.arready) begin - axi_ctx_sent = 1'b1; + axi_ctx_sent <= 1'b1; end end diff --git a/src/axi/rtl/axi_mgr_wr.sv b/src/axi/rtl/axi_mgr_wr.sv index 4ce67c0c1..59dba8466 100644 --- a/src/axi/rtl/axi_mgr_wr.sv +++ b/src/axi/rtl/axi_mgr_wr.sv @@ -45,6 +45,7 @@ module axi_mgr_wr import axi_pkg::*; #( // --------------------------------------- // // Imports // // --------------------------------------- // + `include "caliptra_prim_assert.sv" // --------------------------------------- // @@ -93,11 +94,10 @@ module axi_mgr_wr import axi_pkg::*; #( .OPT_OUTREG (0 ), // .OPT_PASSTHROUGH(0 ), - .DW ($bits(req_ctx_t)), - .OPT_INITIAL (1'b1) + .DW ($bits(req_ctx_t)) ) i_ctx_skd ( .i_clk (clk ), - .i_reset(!rst_n ), + .i_reset(rst_n ), .i_valid(req_if.valid ), .o_ready(req_if.ready ), .i_data (req_ctx ), @@ -108,13 +108,13 @@ module axi_mgr_wr import axi_pkg::*; #( always_ff@(posedge clk or negedge rst_n) begin if (!rst_n) begin - axi_ctx_sent = 1'b0; + axi_ctx_sent <= 1'b0; end else if (axi_ctx_valid && axi_ctx_ready) begin - axi_ctx_sent = 1'b0; + axi_ctx_sent <= 1'b0; end else if (m_axi_if.awvalid && m_axi_if.awready) begin - axi_ctx_sent = 1'b1; + axi_ctx_sent <= 1'b1; end end diff --git a/src/axi/rtl/axi_sub_arb.sv b/src/axi/rtl/axi_sub_arb.sv index 646dc6c47..ab47974d5 100644 --- a/src/axi/rtl/axi_sub_arb.sv +++ b/src/axi/rtl/axi_sub_arb.sv @@ -78,6 +78,8 @@ module axi_sub_arb import axi_pkg::*; #( input logic [DW-1:0] rdata // Requires: Component dwidth == AXI dwidth ); + `include "caliptra_prim_assert.sv" + logic r_pri; // Priority to reads logic r_win; diff --git a/src/axi/rtl/axi_sub_rd.sv b/src/axi/rtl/axi_sub_rd.sv index 3538984bc..746b2e8dd 100644 --- a/src/axi/rtl/axi_sub_rd.sv +++ b/src/axi/rtl/axi_sub_rd.sv @@ -66,6 +66,11 @@ module axi_sub_rd import axi_pkg::*; #( input logic [DW-1:0] rdata // Requires: Component dwidth == AXI dwidth ); + // --------------------------------------- // + // Imports // + // --------------------------------------- // + `include "caliptra_prim_assert.sv" + // --------------------------------------- // // Localparams/Typedefs // // --------------------------------------- // @@ -145,7 +150,7 @@ module axi_sub_rd import axi_pkg::*; #( txn_cnt <= '0; end else if (s_axi_if.arvalid && s_axi_if.arready) begin - txn_ctx.addr <= s_axi_if.araddr; + txn_ctx.addr <= s_axi_if.araddr[AW-1:0]; txn_ctx.burst <= axi_burst_e'(s_axi_if.arburst); txn_ctx.size <= s_axi_if.arsize; txn_ctx.len <= s_axi_if.arlen ; @@ -185,6 +190,7 @@ module axi_sub_rd import axi_pkg::*; #( always_comb addr = {txn_ctx.addr[AW-1:BW],BW'(0)}; always_comb user = txn_ctx.user; always_comb id = txn_ctx.id; + always_comb last = txn_cnt == 0; // Use full address to calculate next address (in case of arsize < data width) axi_addr #( @@ -328,11 +334,10 @@ module axi_sub_rd import axi_pkg::*; #( .OPT_OUTREG (0 ), // .OPT_PASSTHROUGH(0 ), - .DW (DW + $bits(xfer_ctx_t)), - .OPT_INITIAL (1'b1) + .DW (DW + $bits(xfer_ctx_t)) ) i_dp_skd ( .i_clk (clk ), - .i_reset(!rst_n ), + .i_reset(rst_n ), .i_valid(dp_rvalid[dp] ), .o_ready(dp_rready[dp] ), .i_data ({dp_rdata[dp], diff --git a/src/axi/rtl/axi_sub_wr.sv b/src/axi/rtl/axi_sub_wr.sv index f468dc66a..7701e2d31 100644 --- a/src/axi/rtl/axi_sub_wr.sv +++ b/src/axi/rtl/axi_sub_wr.sv @@ -63,6 +63,11 @@ module axi_sub_wr import axi_pkg::*; #( ); + // --------------------------------------- // + // Imports // + // --------------------------------------- // + `include "caliptra_prim_assert.sv" + // --------------------------------------- // // Localparams/Typedefs // // --------------------------------------- // @@ -117,7 +122,7 @@ module axi_sub_wr import axi_pkg::*; #( // --------------------------------------- // always_comb begin - s_axi_if_ctx.addr = s_axi_if.awaddr ; + s_axi_if_ctx.addr = s_axi_if.awaddr[AW-1:0] ; s_axi_if_ctx.burst = axi_burst_e'(s_axi_if.awburst); s_axi_if_ctx.size = s_axi_if.awsize ; s_axi_if_ctx.len = s_axi_if.awlen ; @@ -132,11 +137,10 @@ module axi_sub_wr import axi_pkg::*; #( .OPT_OUTREG (0 ), // .OPT_PASSTHROUGH(0 ), - .DW ($bits(axi_ctx_t)), - .OPT_INITIAL (1'b1) + .DW ($bits(axi_ctx_t)) ) i_req_skd ( .i_clk (clk ), - .i_reset(!rst_n ), + .i_reset(rst_n ), .i_valid(s_axi_if.awvalid), .o_ready(s_axi_if.awready), .i_data (s_axi_if_ctx ), @@ -170,7 +174,9 @@ module axi_sub_wr import axi_pkg::*; #( always_ff@(posedge clk or negedge rst_n) begin if (!rst_n) begin - txn_ctx <= '{default:0, burst:AXI_BURST_FIXED}; + txn_ctx <= '{default:0, burst:AXI_BURST_FIXED}; + txn_allow <= !EX_EN; + txn_err <= 1'b0; end else if (req_valid && req_ready) begin txn_ctx.addr <= req_ctx.addr; @@ -271,11 +277,10 @@ module axi_sub_wr import axi_pkg::*; #( .OPT_OUTREG (0 ), // .OPT_PASSTHROUGH(0 ), - .DW (DW + BC + 1), - .OPT_INITIAL (1'b1) + .DW (DW + BC + 1) ) i_dp_skd ( .i_clk (clk ), - .i_reset(!rst_n ), + .i_reset(rst_n ), .i_valid(txn_wvalid ), .o_ready(txn_wready ), .i_data ({s_axi_if.wdata, @@ -309,11 +314,10 @@ module axi_sub_wr import axi_pkg::*; #( .OPT_OUTREG (1 ), // .OPT_PASSTHROUGH(0 ), - .DW (IW + $bits(axi_resp_e)), - .OPT_INITIAL (1'b1) + .DW (IW + $bits(axi_resp_e)) ) i_rsp_skd ( .i_clk (clk ), - .i_reset(!rst_n ), + .i_reset(rst_n ), .i_valid(rp_valid ), .o_ready(rp_ready ), .i_data ({rp_resp, diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv index 82d0b902e..0533fb7d8 100644 --- a/src/integration/asserts/caliptra_top_sva.sv +++ b/src/integration/asserts/caliptra_top_sva.sv @@ -19,12 +19,16 @@ `include "config_defines.svh" //`include "kv_defines_pkg.sv" //`include "doe_defines_pkg.sv" -`ifdef UVMF_CALIPTRA_TOP -`define CPTRA_TB_TOP_NAME hdl_top -`else -`define CPTRA_TB_TOP_NAME caliptra_top_tb +`ifndef CPTRA_TB_TOP_NAME + `ifdef UVMF_CALIPTRA_TOP + `define CPTRA_TB_TOP_NAME hdl_top + `else + `define CPTRA_TB_TOP_NAME caliptra_top_tb + `endif +`endif +`ifndef CPTRA_TOP_PATH + `define CPTRA_TOP_PATH `CPTRA_TB_TOP_NAME.caliptra_top_dut `endif -`define CPTRA_TOP_PATH `CPTRA_TB_TOP_NAME.caliptra_top_dut `define KEYVAULT_PATH `CPTRA_TOP_PATH.key_vault1 `define KEYVAULT_REG_PATH `KEYVAULT_PATH.kv_reg1 `define PCRVAULT_PATH `CPTRA_TOP_PATH.pcr_vault1 diff --git a/src/integration/config/caliptra_top.vf b/src/integration/config/caliptra_top.vf index 051ee37fd..c0ade6f2e 100644 --- a/src/integration/config/caliptra_top.vf +++ b/src/integration/config/caliptra_top.vf @@ -6,9 +6,10 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl -+incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb +incdir+${CALIPTRA_ROOT}/src/csrng/rtl +incdir+${CALIPTRA_ROOT}/src/spi_host/rtl @@ -20,8 +21,8 @@ +incdir+${CALIPTRA_ROOT}/src/hmac/rtl +incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl +incdir+${CALIPTRA_ROOT}/src/ecc/rtl -+incdir+${CALIPTRA_ROOT}/src/kmac/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/kmac/rtl +incdir+${CALIPTRA_ROOT}/src/edn/rtl +incdir+${CALIPTRA_ROOT}/src/aes/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh @@ -49,10 +50,8 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv ${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv -${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv -${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv -${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv -${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv @@ -63,6 +62,10 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv @@ -194,20 +197,11 @@ ${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv -${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv -${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv -${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv -${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv -${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv -${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv @@ -242,6 +236,27 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv diff --git a/src/integration/config/caliptra_top_tb.vf b/src/integration/config/caliptra_top_tb.vf index b55c044cf..c940863e4 100644 --- a/src/integration/config/caliptra_top_tb.vf +++ b/src/integration/config/caliptra_top_tb.vf @@ -3,6 +3,7 @@ +incdir+${CALIPTRA_ROOT}/src/integration/asserts +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/spi_host/rtl @@ -52,6 +53,8 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv @@ -102,12 +105,19 @@ ${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv +${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_soc_bfm.sv ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_if.sv ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_props.sv ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_bind.sv ${CALIPTRA_ROOT}/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/axi/rtl/caliptra_axi_sram.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv @@ -275,6 +285,13 @@ ${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv diff --git a/src/integration/config/caliptra_top_tb_pkg.vf b/src/integration/config/caliptra_top_tb_pkg.vf new file mode 100644 index 000000000..5f5a82db1 --- /dev/null +++ b/src/integration/config/caliptra_top_tb_pkg.vf @@ -0,0 +1,358 @@ ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/doe/rtl ++incdir+${CALIPTRA_ROOT}/src/integration/asserts ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl ++incdir+${CALIPTRA_ROOT}/src/spi_host/tb ++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/datavault/rtl ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl ++incdir+${CALIPTRA_ROOT}/src/entropy_src/tb ++incdir+${CALIPTRA_ROOT}/src/csrng/rtl ++incdir+${CALIPTRA_ROOT}/src/uart/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512/coverage ++incdir+${CALIPTRA_ROOT}/src/sha256/coverage ++incdir+${CALIPTRA_ROOT}/src/hmac/coverage ++incdir+${CALIPTRA_ROOT}/src/ecc/coverage ++incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage ++incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ++incdir+${CALIPTRA_ROOT}/src/keyvault/coverage ++incdir+${CALIPTRA_ROOT}/src/integration/tb ++incdir+${CALIPTRA_ROOT}/src/integration/coverage ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ++incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512/rtl ++incdir+${CALIPTRA_ROOT}/src/sha256/rtl ++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac/rtl ++incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl ++incdir+${CALIPTRA_ROOT}/src/ecc/rtl ++incdir+${CALIPTRA_ROOT}/src/kmac/rtl ++incdir+${CALIPTRA_ROOT}/src/edn/rtl ++incdir+${CALIPTRA_ROOT}/src/aes/rtl +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv +${CALIPTRA_ROOT}/src/integration/asserts/caliptra_top_sva.sv +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv +${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/tb/spi_device_pkg.sv +${CALIPTRA_ROOT}/src/spi_host/tb/spiflash.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv +${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv +${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv +${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv +${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_bind.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv +${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv +${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv +${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv +${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_soc_bfm.sv +${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_if.sv +${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_props.sv +${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_bind.sv +${CALIPTRA_ROOT}/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/axi/rtl/caliptra_axi_sram.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv +${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv +${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv +${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv +${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v +${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v +${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg_pkg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_ctrl.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_decipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_encipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_inv_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_key_mem.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_core_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_fsm.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv +${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_w_mem.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv +${CALIPTRA_ROOT}/src/hmac/rtl/hmac_lfsr.sv +${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_defines_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_params_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_uop_pkg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_top.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_scalar_blinding.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_hmac_drbg_interface.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_arith_unit.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_ctrl.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_sequencer.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_ram_tdp_file.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_fau.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_montgomerymultiplier.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_first.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_final.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_mult_dsp.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_add_sub_mod_alter.sv +${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg.sv +${CALIPTRA_ROOT}/src/datavault/rtl/dv.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv +${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv +${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_enable_delay.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_markov_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_watermark_reg.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnts_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_adaptp_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_core.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnt_ht.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm.sv +${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src.sv +${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_core.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_n.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_p.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_lut.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_columns.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_dom.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sub_bytes.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_sel_buf_chk.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv +${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_core.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_main_sm.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_upd.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_cmd.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_top.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_gen.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv +${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart.sv +${CALIPTRA_ROOT}/src/uart/rtl/uart_core.sv +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv \ No newline at end of file diff --git a/src/integration/config/caliptra_top_trng_tb.vf b/src/integration/config/caliptra_top_trng_tb.vf index b55c044cf..c940863e4 100644 --- a/src/integration/config/caliptra_top_trng_tb.vf +++ b/src/integration/config/caliptra_top_trng_tb.vf @@ -3,6 +3,7 @@ +incdir+${CALIPTRA_ROOT}/src/integration/asserts +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/spi_host/rtl @@ -52,6 +53,8 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv @@ -102,12 +105,19 @@ ${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv +${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_soc_bfm.sv ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_if.sv ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_props.sv ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_bind.sv ${CALIPTRA_ROOT}/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/axi/rtl/caliptra_axi_sram.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv @@ -275,6 +285,13 @@ ${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index 47f8d136c..585739e35 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -48,6 +48,7 @@ targets: - $MSFT_REPO_ROOT/src/integration/config/design_lint/sglint_waivers options: - '+define+CALIPTRA_INTERNAL_TRNG' + - '+define+CALIPTRA_AXI_DMA_ADDR_WIDTH=32' cdc: tcl_files: - $COMPILE_ROOT/config/cdc/integration_top.constraints.tcl @@ -60,11 +61,12 @@ global: # - '+define+CALIPTRA_INTERNAL_TRNG' #- '-v2k_generate' --- -provides: [caliptra_top_tb] +provides: [caliptra_top_tb_pkg] schema_version: 2.4.0 requires: - asserts - libs + - caliptra_axi_sram - spiflash - caliptra_top - el2_veer_pkg @@ -102,10 +104,21 @@ targets: - $COMPILE_ROOT/tb/caliptra_top_tb_pkg.sv - $COMPILE_ROOT/tb/caliptra_veer_sram_export.sv - $COMPILE_ROOT/tb/caliptra_top_tb_services.sv + - $COMPILE_ROOT/tb/caliptra_top_tb_soc_bfm.sv - $COMPILE_ROOT/coverage/caliptra_top_cov_if.sv - $COMPILE_ROOT/coverage/caliptra_top_cov_props.sv - $COMPILE_ROOT/coverage/caliptra_top_cov_bind.sv - $COMPILE_ROOT/test_suites/libs/jtagdpi/jtagdpi.sv +--- +provides: [caliptra_top_tb] +schema_version: 2.4.0 +requires: + - caliptra_top_tb_pkg +targets: + tb: + directories: + - $COMPILE_ROOT/tb + files: - $COMPILE_ROOT/tb/caliptra_top_tb.sv tops: [caliptra_top_tb] sim: @@ -130,9 +143,13 @@ global: provides: [caliptra_top_trng_tb] schema_version: 2.4.0 requires: - - caliptra_top_tb + - caliptra_top_tb_pkg targets: tb: + directories: + - $COMPILE_ROOT/tb + files: + - $COMPILE_ROOT/tb/caliptra_top_tb.sv tops: [caliptra_top_tb] sim: pre_exec: '$MSFT_SCRIPTS_DIR/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../ecc/tb/ecc_secp384r1.exe . diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index 9d9edefe4..d400d477b 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -5227,8 +5227,8 @@ #define MBOX_CSR_MBOX_LOCK (0x0) #define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) #define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1) -#define CLP_MBOX_CSR_MBOX_USER (0x30020004) -#define MBOX_CSR_MBOX_USER (0x4) +#define CLP_MBOX_CSR_MBOX_ID (0x30020004) +#define MBOX_CSR_MBOX_ID (0x4) #define CLP_MBOX_CSR_MBOX_CMD (0x30020008) #define MBOX_CSR_MBOX_CMD (0x8) #define CLP_MBOX_CSR_MBOX_DLEN (0x3002000c) @@ -5264,8 +5264,8 @@ #define SHA512_ACC_CSR_LOCK (0x0) #define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) #define SHA512_ACC_CSR_LOCK_LOCK_MASK (0x1) -#define CLP_SHA512_ACC_CSR_USER (0x30021004) -#define SHA512_ACC_CSR_USER (0x4) +#define CLP_SHA512_ACC_CSR_ID (0x30021004) +#define SHA512_ACC_CSR_ID (0x4) #define CLP_SHA512_ACC_CSR_MODE (0x30021008) #define SHA512_ACC_CSR_MODE (0x8) #define SHA512_ACC_CSR_MODE_MODE_LOW (0) @@ -5411,6 +5411,246 @@ #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_BASE_ADDR (0x30022000) +#define CLP_AXI_DMA_REG_ID (0x30022000) +#define AXI_DMA_REG_ID (0x0) +#define CLP_AXI_DMA_REG_CAP (0x30022004) +#define AXI_DMA_REG_CAP (0x4) +#define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0) +#define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (0xfff) +#define AXI_DMA_REG_CAP_RSVD_LOW (12) +#define AXI_DMA_REG_CAP_RSVD_MASK (0xfffff000) +#define CLP_AXI_DMA_REG_CTRL (0x30022008) +#define AXI_DMA_REG_CTRL (0x8) +#define AXI_DMA_REG_CTRL_GO_LOW (0) +#define AXI_DMA_REG_CTRL_GO_MASK (0x1) +#define AXI_DMA_REG_CTRL_FLUSH_LOW (1) +#define AXI_DMA_REG_CTRL_FLUSH_MASK (0x2) +#define AXI_DMA_REG_CTRL_RSVD0_LOW (2) +#define AXI_DMA_REG_CTRL_RSVD0_MASK (0xfffc) +#define AXI_DMA_REG_CTRL_RD_ROUTE_LOW (16) +#define AXI_DMA_REG_CTRL_RD_ROUTE_MASK (0x30000) +#define AXI_DMA_REG_CTRL_RSVD1_LOW (18) +#define AXI_DMA_REG_CTRL_RSVD1_MASK (0xc0000) +#define AXI_DMA_REG_CTRL_RD_FIXED_LOW (20) +#define AXI_DMA_REG_CTRL_RD_FIXED_MASK (0x100000) +#define AXI_DMA_REG_CTRL_RSVD2_LOW (21) +#define AXI_DMA_REG_CTRL_RSVD2_MASK (0xe00000) +#define AXI_DMA_REG_CTRL_WR_ROUTE_LOW (24) +#define AXI_DMA_REG_CTRL_WR_ROUTE_MASK (0x3000000) +#define AXI_DMA_REG_CTRL_RSVD3_LOW (26) +#define AXI_DMA_REG_CTRL_RSVD3_MASK (0xc000000) +#define AXI_DMA_REG_CTRL_WR_FIXED_LOW (28) +#define AXI_DMA_REG_CTRL_WR_FIXED_MASK (0x10000000) +#define AXI_DMA_REG_CTRL_RSVD4_LOW (29) +#define AXI_DMA_REG_CTRL_RSVD4_MASK (0xe0000000) +#define CLP_AXI_DMA_REG_STATUS0 (0x3002200c) +#define AXI_DMA_REG_STATUS0 (0xc) +#define AXI_DMA_REG_STATUS0_BUSY_LOW (0) +#define AXI_DMA_REG_STATUS0_BUSY_MASK (0x1) +#define AXI_DMA_REG_STATUS0_ERROR_LOW (1) +#define AXI_DMA_REG_STATUS0_ERROR_MASK (0x2) +#define AXI_DMA_REG_STATUS0_RSVD0_LOW (2) +#define AXI_DMA_REG_STATUS0_RSVD0_MASK (0xc) +#define AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW (4) +#define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK (0xfff0) +#define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16) +#define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (0x30000) +#define AXI_DMA_REG_STATUS0_RSVD1_LOW (18) +#define AXI_DMA_REG_STATUS0_RSVD1_MASK (0xfffc0000) +#define CLP_AXI_DMA_REG_STATUS1 (0x30022010) +#define AXI_DMA_REG_STATUS1 (0x10) +#define CLP_AXI_DMA_REG_SRC_ADDR_L (0x30022014) +#define AXI_DMA_REG_SRC_ADDR_L (0x14) +#define CLP_AXI_DMA_REG_SRC_ADDR_H (0x30022018) +#define AXI_DMA_REG_SRC_ADDR_H (0x18) +#define CLP_AXI_DMA_REG_DST_ADDR_L (0x3002201c) +#define AXI_DMA_REG_DST_ADDR_L (0x1c) +#define CLP_AXI_DMA_REG_DST_ADDR_H (0x30022020) +#define AXI_DMA_REG_DST_ADDR_H (0x20) +#define CLP_AXI_DMA_REG_BYTE_COUNT (0x30022024) +#define AXI_DMA_REG_BYTE_COUNT (0x24) +#define CLP_AXI_DMA_REG_BLOCK_SIZE (0x30022028) +#define AXI_DMA_REG_BLOCK_SIZE (0x28) +#define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) +#define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (0xfff) +#define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) +#define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (0xfffff000) +#define CLP_AXI_DMA_REG_WRITE_DATA (0x3002202c) +#define AXI_DMA_REG_WRITE_DATA (0x2c) +#define CLP_AXI_DMA_REG_READ_DATA (0x30022030) +#define AXI_DMA_REG_READ_DATA (0x30) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_START (0x30022800) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x30022800) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x30022804) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_MASK (0x10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_LOW (5) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (0x20) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (0x40) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x30022808) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (0x10) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x3002280c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x30022810) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x30022814) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK (0x10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_LOW (5) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (0x20) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (0x40) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x30022818) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (0x10) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x3002281c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_MASK (0x10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_LOW (5) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (0x20) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (0x40) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x30022820) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (0x10) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (0x30022900) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (0x900) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (0x30022904) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (0x904) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (0x30022908) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (0x908) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (0x3002290c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (0x90c) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (0x30022910) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (0x910) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (0x30022914) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (0x914) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (0x30022918) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (0x918) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (0x30022980) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (0x980) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (0x30022984) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (0x984) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (0x30022988) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (0x988) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (0x3002298c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (0x98c) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (0x30022990) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (0x990) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (0x30022a00) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (0xa00) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (0x30022a04) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (0xa04) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (0x30022a08) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (0xa08) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (0x30022a0c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (0xa0c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (0x30022a10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (0xa10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (0x30022a14) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (0xa14) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (0x30022a18) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (0xa18) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (0x30022a1c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (0xa1c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (0x30022a20) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (0xa20) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (0x30022a24) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (0xa24) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (0x30022a28) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (0xa28) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (0x30022a2c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (0xa2c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) #define CLP_SOC_IFC_REG_BASE_ADDR (0x30030000) #define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (0x30030000) #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (0x0) @@ -5488,42 +5728,42 @@ #define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (0x30030048) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (0x48) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (0x3003004c) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (0x4c) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (0x30030050) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (0x50) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (0x30030054) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (0x54) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (0x30030058) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (0x58) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (0x3003005c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (0x5c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (0x30030060) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (0x60) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (0x30030064) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (0x64) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (0x30030068) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (0x68) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (0x3003006c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (0x6c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (0x30030070) -#define SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (0x70) -#define CLP_SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (0x30030074) -#define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (0x74) -#define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x30030048) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x48) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x3003004c) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x4c) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x30030050) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x50) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x30030054) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x54) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x30030058) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x58) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x3003005c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x5c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x30030060) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x60) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x30030064) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x64) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x30030068) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x68) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x3003006c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x6c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x30030070) +#define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x70) +#define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x30030074) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x74) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (0x1) #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x30030078) #define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x78) #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (0x3003007c) @@ -5634,12 +5874,12 @@ #define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2) -#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (0x30030108) -#define SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (0x108) -#define CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (0x3003010c) -#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (0x10c) -#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x30030108) +#define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x108) +#define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x3003010c) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x10c) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (0x1) #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x30030110) #define SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x110) #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (0x30030114) diff --git a/src/integration/rtl/caliptra_reg.rdl b/src/integration/rtl/caliptra_reg.rdl index e96c5ccf6..44307cc0f 100644 --- a/src/integration/rtl/caliptra_reg.rdl +++ b/src/integration/rtl/caliptra_reg.rdl @@ -53,6 +53,8 @@ addrmap clp { sha512_acc_csr sha512_acc_csr @ 0x3002_1000; + axi_dma_reg axi_dma_reg @ 0x3002_2000; + soc_ifc_reg soc_ifc_reg @ 0x3003_0000; }; diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index 6be34b771..2aacb2848 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -5227,8 +5227,8 @@ `define MBOX_CSR_MBOX_LOCK (32'h0) `define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) `define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) -`define CLP_MBOX_CSR_MBOX_USER (32'h30020004) -`define MBOX_CSR_MBOX_USER (32'h4) +`define CLP_MBOX_CSR_MBOX_ID (32'h30020004) +`define MBOX_CSR_MBOX_ID (32'h4) `define CLP_MBOX_CSR_MBOX_CMD (32'h30020008) `define MBOX_CSR_MBOX_CMD (32'h8) `define CLP_MBOX_CSR_MBOX_DLEN (32'h3002000c) @@ -5264,8 +5264,8 @@ `define SHA512_ACC_CSR_LOCK (32'h0) `define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) `define SHA512_ACC_CSR_LOCK_LOCK_MASK (32'h1) -`define CLP_SHA512_ACC_CSR_USER (32'h30021004) -`define SHA512_ACC_CSR_USER (32'h4) +`define CLP_SHA512_ACC_CSR_ID (32'h30021004) +`define SHA512_ACC_CSR_ID (32'h4) `define CLP_SHA512_ACC_CSR_MODE (32'h30021008) `define SHA512_ACC_CSR_MODE (32'h8) `define SHA512_ACC_CSR_MODE_MODE_LOW (0) @@ -5411,6 +5411,246 @@ `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_BASE_ADDR (32'h30022000) +`define CLP_AXI_DMA_REG_ID (32'h30022000) +`define AXI_DMA_REG_ID (32'h0) +`define CLP_AXI_DMA_REG_CAP (32'h30022004) +`define AXI_DMA_REG_CAP (32'h4) +`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0) +`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (32'hfff) +`define AXI_DMA_REG_CAP_RSVD_LOW (12) +`define AXI_DMA_REG_CAP_RSVD_MASK (32'hfffff000) +`define CLP_AXI_DMA_REG_CTRL (32'h30022008) +`define AXI_DMA_REG_CTRL (32'h8) +`define AXI_DMA_REG_CTRL_GO_LOW (0) +`define AXI_DMA_REG_CTRL_GO_MASK (32'h1) +`define AXI_DMA_REG_CTRL_FLUSH_LOW (1) +`define AXI_DMA_REG_CTRL_FLUSH_MASK (32'h2) +`define AXI_DMA_REG_CTRL_RSVD0_LOW (2) +`define AXI_DMA_REG_CTRL_RSVD0_MASK (32'hfffc) +`define AXI_DMA_REG_CTRL_RD_ROUTE_LOW (16) +`define AXI_DMA_REG_CTRL_RD_ROUTE_MASK (32'h30000) +`define AXI_DMA_REG_CTRL_RSVD1_LOW (18) +`define AXI_DMA_REG_CTRL_RSVD1_MASK (32'hc0000) +`define AXI_DMA_REG_CTRL_RD_FIXED_LOW (20) +`define AXI_DMA_REG_CTRL_RD_FIXED_MASK (32'h100000) +`define AXI_DMA_REG_CTRL_RSVD2_LOW (21) +`define AXI_DMA_REG_CTRL_RSVD2_MASK (32'he00000) +`define AXI_DMA_REG_CTRL_WR_ROUTE_LOW (24) +`define AXI_DMA_REG_CTRL_WR_ROUTE_MASK (32'h3000000) +`define AXI_DMA_REG_CTRL_RSVD3_LOW (26) +`define AXI_DMA_REG_CTRL_RSVD3_MASK (32'hc000000) +`define AXI_DMA_REG_CTRL_WR_FIXED_LOW (28) +`define AXI_DMA_REG_CTRL_WR_FIXED_MASK (32'h10000000) +`define AXI_DMA_REG_CTRL_RSVD4_LOW (29) +`define AXI_DMA_REG_CTRL_RSVD4_MASK (32'he0000000) +`define CLP_AXI_DMA_REG_STATUS0 (32'h3002200c) +`define AXI_DMA_REG_STATUS0 (32'hc) +`define AXI_DMA_REG_STATUS0_BUSY_LOW (0) +`define AXI_DMA_REG_STATUS0_BUSY_MASK (32'h1) +`define AXI_DMA_REG_STATUS0_ERROR_LOW (1) +`define AXI_DMA_REG_STATUS0_ERROR_MASK (32'h2) +`define AXI_DMA_REG_STATUS0_RSVD0_LOW (2) +`define AXI_DMA_REG_STATUS0_RSVD0_MASK (32'hc) +`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW (4) +`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK (32'hfff0) +`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16) +`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (32'h30000) +`define AXI_DMA_REG_STATUS0_RSVD1_LOW (18) +`define AXI_DMA_REG_STATUS0_RSVD1_MASK (32'hfffc0000) +`define CLP_AXI_DMA_REG_STATUS1 (32'h30022010) +`define AXI_DMA_REG_STATUS1 (32'h10) +`define CLP_AXI_DMA_REG_SRC_ADDR_L (32'h30022014) +`define AXI_DMA_REG_SRC_ADDR_L (32'h14) +`define CLP_AXI_DMA_REG_SRC_ADDR_H (32'h30022018) +`define AXI_DMA_REG_SRC_ADDR_H (32'h18) +`define CLP_AXI_DMA_REG_DST_ADDR_L (32'h3002201c) +`define AXI_DMA_REG_DST_ADDR_L (32'h1c) +`define CLP_AXI_DMA_REG_DST_ADDR_H (32'h30022020) +`define AXI_DMA_REG_DST_ADDR_H (32'h20) +`define CLP_AXI_DMA_REG_BYTE_COUNT (32'h30022024) +`define AXI_DMA_REG_BYTE_COUNT (32'h24) +`define CLP_AXI_DMA_REG_BLOCK_SIZE (32'h30022028) +`define AXI_DMA_REG_BLOCK_SIZE (32'h28) +`define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) +`define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (32'hfff) +`define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) +`define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (32'hfffff000) +`define CLP_AXI_DMA_REG_WRITE_DATA (32'h3002202c) +`define AXI_DMA_REG_WRITE_DATA (32'h2c) +`define CLP_AXI_DMA_REG_READ_DATA (32'h30022030) +`define AXI_DMA_REG_READ_DATA (32'h30) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_START (32'h30022800) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h30022800) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h30022804) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (32'h40) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h30022808) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (32'h10) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h3002280c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h30022810) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h30022814) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (32'h40) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h30022818) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (32'h10) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h3002281c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (32'h40) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h30022820) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (32'h10) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h30022900) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h900) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h30022904) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h904) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h30022908) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h908) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h3002290c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h90c) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h30022910) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h910) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h30022914) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h914) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h30022918) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h918) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h30022980) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h980) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h30022984) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h984) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h30022988) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h988) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h3002298c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h98c) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h30022990) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h990) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'h30022a00) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'ha00) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'h30022a04) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'ha04) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'h30022a08) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'ha08) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'h30022a0c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'ha0c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'h30022a10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'ha10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'h30022a14) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'ha14) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'h30022a18) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'ha18) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'h30022a1c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'ha1c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'h30022a20) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'ha20) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'h30022a24) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'ha24) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'h30022a28) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'ha28) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'h30022a2c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'ha2c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_BASE_ADDR (32'h30030000) `define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h30030000) `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h0) @@ -5488,42 +5728,42 @@ `define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (32'h30030048) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (32'h48) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (32'h3003004c) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (32'h4c) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (32'h30030050) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (32'h50) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (32'h30030054) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (32'h54) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (32'h30030058) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (32'h58) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (32'h3003005c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (32'h5c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (32'h30030060) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (32'h60) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (32'h30030064) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (32'h64) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (32'h30030068) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (32'h68) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (32'h3003006c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (32'h6c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (32'h30030070) -`define SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (32'h70) -`define CLP_SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (32'h30030074) -`define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (32'h74) -`define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h30030048) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h48) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h3003004c) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h4c) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h30030050) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h50) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h30030054) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h54) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h30030058) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h58) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h3003005c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h5c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h30030060) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h60) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h30030064) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h64) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h30030068) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h68) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h3003006c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h6c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (32'h30030070) +`define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (32'h70) +`define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h30030074) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h74) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h30030078) `define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h78) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (32'h3003007c) @@ -5634,12 +5874,12 @@ `define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) -`define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (32'h30030108) -`define SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (32'h108) -`define CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (32'h3003010c) -`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (32'h10c) -`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (32'h30030108) +`define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (32'h108) +`define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h3003010c) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h10c) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h30030110) `define SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h110) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (32'h30030114) diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 5bedde743..0ee9888a3 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -44,18 +44,13 @@ module caliptra_top output logic jtag_tdo, // JTAG TDO output logic jtag_tdoEn, // JTAG TDO enable - //APB Interface - input logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR, - input logic [2:0] PPROT, - input logic PSEL, - input logic PENABLE, - input logic PWRITE, - input logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PWDATA, - input logic [`CALIPTRA_APB_USER_WIDTH-1:0] PAUSER, - - output logic PREADY, - output logic PSLVERR, - output logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PRDATA, + //SoC AXI Interface + axi_if.w_sub s_axi_w_if, + axi_if.r_sub s_axi_r_if, + + // AXI Manager INF + axi_if.w_mgr m_axi_w_if, + axi_if.r_mgr m_axi_r_if, //QSPI Interface output logic qspi_clk_o, @@ -92,6 +87,8 @@ module caliptra_top output logic mailbox_data_avail, output logic mailbox_flow_done, + input logic recovery_data_avail, + input logic BootFSM_BrkPoint, //SoC Interrupts @@ -129,6 +126,8 @@ module caliptra_top logic rdc_clk_cg ; logic uc_clk_cg ; + logic [2:0] s_axi_active ; + logic [31:0] ic_haddr ; logic [2:0] ic_hburst ; logic ic_hmastlock ; @@ -224,7 +223,8 @@ module caliptra_top wire soc_ifc_notif_intr; wire sha_error_intr; wire sha_notif_intr; - + wire dma_error_intr; + wire dma_notif_intr; logic [NUM_INTR-1:0] intr; kv_read_t [KV_NUM_READ-1:0] kv_read; @@ -404,6 +404,8 @@ always_comb begin intr[`VEER_INTR_VEC_SOC_IFC_NOTIF-1] = soc_ifc_notif_intr; intr[`VEER_INTR_VEC_SHA_ERROR -1] = sha_error_intr; intr[`VEER_INTR_VEC_SHA_NOTIF -1] = sha_notif_intr; + intr[`VEER_INTR_VEC_AXI_DMA_ERROR-1] = dma_error_intr; + intr[`VEER_INTR_VEC_AXI_DMA_NOTIF-1] = dma_notif_intr; intr[NUM_INTR-1:`VEER_INTR_VEC_MAX_ASSIGNED] = '0; end @@ -646,10 +648,39 @@ el2_veer_wrapper rvtop ( //=========================================================================- // Clock gating instance //=========================================================================- +always_ff@(posedge clk or negedge cptra_rst_b) begin + if (!cptra_rst_b) begin + s_axi_active <= 2'd0; + end + else begin + case ({s_axi_r_if.rvalid && s_axi_r_if.rready && s_axi_r_if.rlast, + s_axi_r_if.arvalid && s_axi_r_if.arready, + s_axi_w_if.bvalid && s_axi_w_if.bready, + s_axi_w_if.awvalid && s_axi_w_if.awready}) inside + 4'b0000: s_axi_active <= s_axi_active ; + 4'b0001: s_axi_active <= s_axi_active + 3'd1; + 4'b0010: s_axi_active <= s_axi_active - 3'd1; + 4'b0011: s_axi_active <= s_axi_active ; + 4'b0100: s_axi_active <= s_axi_active + 3'd1; + 4'b0101: s_axi_active <= s_axi_active + 3'd2; + 4'b0110: s_axi_active <= s_axi_active ; + 4'b0111: s_axi_active <= s_axi_active + 3'd1; + 4'b1000: s_axi_active <= s_axi_active - 3'd1; + 4'b1001: s_axi_active <= s_axi_active ; + 4'b1010: s_axi_active <= s_axi_active - 3'd2; + 4'b1011: s_axi_active <= s_axi_active - 3'd1; + 4'b1100: s_axi_active <= s_axi_active ; + 4'b1101: s_axi_active <= s_axi_active + 3'd1; + 4'b1110: s_axi_active <= s_axi_active - 3'd1; + 4'b1111: s_axi_active <= s_axi_active ; + endcase + end +end + clk_gate cg ( .clk(clk), .cptra_rst_b(cptra_noncore_rst_b), - .psel(PSEL), + .psel(|s_axi_active || s_axi_r_if.arvalid || s_axi_w_if.awvalid), .clk_gate_en(clk_gating_en), .cpu_halt_status(o_cpu_halt_status), .rdc_clk_dis(rdc_clk_dis), @@ -1171,24 +1202,33 @@ uart #( soc_ifc_top #( .AHB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), .AHB_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE), - .APB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), - .APB_DATA_WIDTH(`CALIPTRA_APB_DATA_WIDTH), - .APB_USER_WIDTH(`CALIPTRA_APB_USER_WIDTH) + .AXI_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), + .AXI_DATA_WIDTH(`CALIPTRA_AXI_DATA_WIDTH), + .AXI_ID_WIDTH (`CALIPTRA_AXI_ID_WIDTH ), + .AXI_USER_WIDTH(`CALIPTRA_AXI_USER_WIDTH), + .AXIM_ADDR_WIDTH(`CALIPTRA_AXI_DMA_ADDR_WIDTH), + .AXIM_DATA_WIDTH(CPTRA_AXI_DMA_DATA_WIDTH), + .AXIM_ID_WIDTH (CPTRA_AXI_DMA_ID_WIDTH), + .AXIM_USER_WIDTH(CPTRA_AXI_DMA_USER_WIDTH) ) soc_ifc_top1 ( - .clk(clk), - .clk_cg(clk_cg), + .clk (clk ), + .clk_cg (clk_cg ), .soc_ifc_clk_cg(soc_ifc_clk_cg), - .rdc_clk_cg(rdc_clk_cg), - .cptra_pwrgood(cptra_pwrgood), - .cptra_rst_b(cptra_rst_b), + .rdc_clk_cg (rdc_clk_cg ), + + .cptra_pwrgood(cptra_pwrgood), + .cptra_rst_b (cptra_rst_b ), + .ready_for_fuses(ready_for_fuses), .ready_for_fw_push(ready_for_fw_push), .ready_for_runtime(ready_for_runtime), .mailbox_data_avail(mailbox_data_avail), .mailbox_flow_done(mailbox_flow_done), + .recovery_data_avail(recovery_data_avail), + .security_state(cptra_security_state_Latched), .BootFSM_BrkPoint (BootFSM_BrkPoint), @@ -1203,16 +1243,10 @@ soc_ifc_top1 // RV ECC Status Interface .rv_ecc_sts(rv_ecc_sts), - //APB Interface with SoC - .paddr_i(PADDR[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)-1:0]), - .psel_i(PSEL), - .penable_i(PENABLE), - .pwrite_i(PWRITE), - .pwdata_i(PWDATA), - .pauser_i(PAUSER), - .pready_o(PREADY), - .prdata_o(PRDATA), - .pslverr_o(PSLVERR), + //SoC AXI Interface + .s_axi_w_if(s_axi_w_if), + .s_axi_r_if(s_axi_r_if), + //AHB Interface with uC .haddr_i (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].haddr[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)-1:0]), .hwdata_i (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hwdata), @@ -1224,6 +1258,11 @@ soc_ifc_top1 .hresp_o (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hresp), .hreadyout_o(responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hreadyout), .hrdata_o (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hrdata), + + // AXI Manager INF + .m_axi_w_if(m_axi_w_if), + .m_axi_r_if(m_axi_r_if), + //SoC Interrupts .cptra_error_fatal (cptra_error_fatal), .cptra_error_non_fatal(cptra_error_non_fatal), @@ -1237,6 +1276,8 @@ soc_ifc_top1 .soc_ifc_notif_intr(soc_ifc_notif_intr), .sha_error_intr(sha_error_intr), .sha_notif_intr(sha_notif_intr), + .dma_error_intr(dma_error_intr), + .dma_notif_intr(dma_notif_intr), .timer_intr(timer_int), //Obfuscated UDS and FE .clear_obf_secrets(clear_obf_secrets_debugScanQ), //input - includes debug & scan modes to do the register clearing @@ -1321,17 +1362,4 @@ endgenerate `CALIPTRA_ASSERT_KNOWN(AHB_MASTER_HRDATA_X, initiator_inst.hready ? initiator_inst.hrdata : '0, clk, !cptra_noncore_rst_b) `CALIPTRA_ASSERT_NEVER(AHB_MASTER_HTRANS_BUSY, initiator_inst.htrans == 2'b01, clk, !cptra_noncore_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PADDR_X, PADDR, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PWDATA_X, PWDATA, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PWRITE_X, PWRITE, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PREADY_X, PREADY, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PENABLE_X, PENABLE, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PSEL_X, PSEL, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PPROT_X, PPROT, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PAUSER_X, PAUSER, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PSLVERR_X, PSLVERR, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PRDATA_X, PREADY ? PRDATA : '0, clk, !cptra_rst_b) - -`CALIPTRA_ASSERT_NEVER(APB_MASTER_PPROT_ACTIVE, PPROT !== 3'b000, clk, !cptra_rst_b) - endmodule diff --git a/src/integration/rtl/config_defines.svh b/src/integration/rtl/config_defines.svh index 1a52b4002..c77970473 100755 --- a/src/integration/rtl/config_defines.svh +++ b/src/integration/rtl/config_defines.svh @@ -22,9 +22,13 @@ `define CALIPTRA_AHB_MASTERS_NUM 4'd1 // Number of masters AHB `define CALIPTRA_AHB_HADDR_SIZE 32 // bit-width AHB address haddr `define CALIPTRA_AHB_HDATA_SIZE 64 // bit-width AHB data - `define CALIPTRA_APB_ADDR_WIDTH 32 // bit-width APB address - `define CALIPTRA_APB_DATA_WIDTH 32 // bit-width APB data - `define CALIPTRA_APB_USER_WIDTH 32 // bit-width APB PAUSER field + `define CALIPTRA_AXI_DATA_WIDTH 32 // bit-width AXI data + `define CALIPTRA_AXI_USER_WIDTH 32 // bit-width AXI USER field + `define CALIPTRA_AXI_ID_WIDTH 8 // bit-width AXI ID field + // Overrideable for lint checks + `ifndef CALIPTRA_AXI_DMA_ADDR_WIDTH + `define CALIPTRA_AXI_DMA_ADDR_WIDTH 48 + `endif `define CALIPTRA_QSPI_CS_WIDTH 2 `define CALIPTRA_QSPI_IO_WIDTH 4 `define CALIPTRA_SOC_SEC_STATE_WIDTH 3 @@ -77,8 +81,10 @@ `define VEER_INTR_VEC_SOC_IFC_NOTIF 20 `define VEER_INTR_VEC_SHA_ERROR 21 `define VEER_INTR_VEC_SHA_NOTIF 22 + `define VEER_INTR_VEC_AXI_DMA_ERROR 23 + `define VEER_INTR_VEC_AXI_DMA_NOTIF 24 // Used to tie-off unused upper intr bits - `define VEER_INTR_VEC_MAX_ASSIGNED `VEER_INTR_VEC_SHA_NOTIF + `define VEER_INTR_VEC_MAX_ASSIGNED `VEER_INTR_VEC_AXI_DMA_NOTIF //`define CALIPTRA_KV_NUM_READ 6 //`define CALIPTRA_KV_NUM_WRITE 4 diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv index 217227be5..44d6af6f5 100755 --- a/src/integration/tb/caliptra_top_tb.sv +++ b/src/integration/tb/caliptra_top_tb.sv @@ -28,6 +28,7 @@ module caliptra_top_tb ( ); `endif + import axi_pkg::*; import soc_ifc_pkg::*; import caliptra_top_tb_pkg::*; @@ -45,7 +46,6 @@ module caliptra_top_tb ( `endif int cycleCnt; - int cycleCnt_Flag = '0; logic cptra_pwrgood; @@ -54,57 +54,11 @@ module caliptra_top_tb ( logic scan_mode; logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key; - logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] cptra_obf_key_uds, cptra_obf_key_fe; - // logic [11:0][31:0] cptra_uds_tb; - // logic [7:0][31:0] cptra_fe_tb; - logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] cptra_uds_tb; - logic [0:`CLP_OBF_FE_DWORDS-1][31:0] cptra_fe_tb; - - // logic [11:0][31:0] cptra_uds_rand; - // logic [7:0][31:0] cptra_fe_rand; logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] cptra_uds_rand; logic [0:`CLP_OBF_FE_DWORDS-1][31:0] cptra_fe_rand; logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] cptra_obf_key_tb; - logic start_apb_fuse_sequence; - - enum logic [5:0] { - S_APB_IDLE, - S_APB_WR_UDS, - S_APB_WR_FE, - S_APB_WR_SOC_STEPPING_ID, - S_APB_WR_FUSE_DONE, - S_APB_POLL_FLOW_ST, - S_APB_WR_BOOT_GO, - S_APB_WAIT_FW_TEST, - S_APB_POLL_LOCK, - S_APB_PRE_WR_CMD, - S_APB_WR_CMD, - S_APB_WR_DLEN, - S_APB_WR_DATAIN, - S_APB_WR_STATUS, - S_APB_WR_EXEC, - S_APB_WAIT_ERROR_AXS, - S_APB_RD_HW_ERROR_FATAL, - S_APB_WR_HW_ERROR_FATAL, - S_APB_RD_HW_ERROR_NON_FATAL, - S_APB_WR_HW_ERROR_NON_FATAL, - S_APB_DONE, - S_APB_RD_DLEN, - S_APB_RD_DATAOUT, - S_APB_RST_EXEC, - S_APB_ERROR - } n_state_apb, c_state_apb; - - parameter FW_NUM_DWORDS = 256; - - logic [$clog2(FW_NUM_DWORDS)-1:0] apb_wr_count, apb_wr_count_nxt; - logic [31:0] apb_rd_count, apb_rd_count_nxt, dlen; - logic apb_enable_ph; - logic apb_xfer_end; - logic execute_mbox_rx_protocol; - //jtag interface logic jtag_tck; // JTAG clk logic jtag_tms; // JTAG TMS @@ -112,18 +66,26 @@ module caliptra_top_tb ( logic jtag_trst_n; // JTAG Reset logic jtag_tdo; // JTAG TDO logic jtag_tdoEn; // JTAG TDO enable - //APB Interface - logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR; - logic [2:0] PPROT; - logic PSEL; - logic PENABLE; - logic PWRITE; - logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PWDATA; - logic [`CALIPTRA_APB_USER_WIDTH-1:0] PAUSER; - - logic PREADY; - logic PSLVERR; - logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PRDATA; + + // AXI Interface + axi_if #( + .AW(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), + .DW(`CALIPTRA_AXI_DATA_WIDTH), + .IW(`CALIPTRA_AXI_ID_WIDTH), + .UW(`CALIPTRA_AXI_USER_WIDTH) + ) m_axi_bfm_if (.clk(core_clk), .rst_n(cptra_rst_b)); + axi_if #( + .AW(`CALIPTRA_AXI_DMA_ADDR_WIDTH), + .DW(CPTRA_AXI_DMA_DATA_WIDTH), + .IW(CPTRA_AXI_DMA_ID_WIDTH), + .UW(CPTRA_AXI_DMA_USER_WIDTH) + ) m_axi_if (.clk(core_clk), .rst_n(cptra_rst_b)); + axi_if #( + .AW(AXI_SRAM_ADDR_WIDTH), + .DW(CPTRA_AXI_DMA_DATA_WIDTH), + .IW(CPTRA_AXI_DMA_ID_WIDTH), + .UW(CPTRA_AXI_DMA_USER_WIDTH) + ) axi_sram_if (.clk(core_clk), .rst_n(cptra_rst_b)); // QSPI Interface logic qspi_clk; @@ -139,7 +101,6 @@ module caliptra_top_tb ( logic ready_for_fuses; logic ready_for_fw_push; logic mailbox_data_avail; - logic status_set; logic mbox_sram_cs; logic mbox_sram_we; logic [14:0] mbox_sram_addr; @@ -161,43 +122,19 @@ module caliptra_top_tb ( logic cptra_error_fatal; logic cptra_error_non_fatal; - logic [15:0] cptra_error_fatal_counter; - logic [15:0] cptra_error_non_fatal_counter; - logic cptra_error_fatal_dly_p; - logic cptra_error_non_fatal_dly_p; - - logic rv_dma_resp_error; - - logic mbox_apb_dataout_read_ooo; - logic mbox_ooo_read_done; - logic mbox_apb_dataout_read_no_lock; - logic mbox_no_lock_read_done; - - logic [`CALIPTRA_APB_DATA_WIDTH-1:0] soc_ifc_hw_error_wdata; //Interrupt flags - //logic nmi_int; - //logic soft_int; - //logic timer_int; logic int_flag; logic cycleCnt_smpl_en; - int cycleCnt_ff; //Reset flags logic assert_hard_rst_flag; logic deassert_hard_rst_flag; logic assert_rst_flag_from_service; - logic assert_rst_flag_from_fatal; - logic assert_rst_flag; logic deassert_rst_flag_from_service; - int count_deassert_rst_flag_from_fatal; - logic deassert_rst_flag_from_fatal; - logic deassert_rst_flag; el2_mem_if el2_mem_export (); - logic [FW_NUM_DWORDS-1:0][31:0] fw_blob; - `ifndef VERILATOR always begin : clk_gen @@ -205,854 +142,46 @@ module caliptra_top_tb ( end // clk_gen `endif - always@(negedge core_clk) begin - if(!cptra_rst_b) cycleCnt_ff <= 'h0; - else if(cycleCnt_smpl_en) cycleCnt_ff <= cycleCnt; - end - - always@(negedge core_clk) begin - if((cycleCnt == cycleCnt_ff + 2000) && int_flag) begin - force caliptra_top_dut.soft_int = 'b1; - end - - else if((cycleCnt == cycleCnt_ff + 7000) && int_flag) begin - force caliptra_top_dut.timer_int = 'b1; - end - - else if((c_state_apb == S_APB_WR_EXEC) && apb_xfer_end && int_flag) begin - //Wait for APB flow to be done before toggling generic_input_wires - generic_input_wires <= {$urandom, $urandom}; //Toggle wires - end - - else if((cycleCnt == cycleCnt_ff + 15000) && int_flag) begin - force caliptra_top_dut.soft_int = 'b1; - end - - else if (!ras_test_ctrl.error_injection_seen) begin - release caliptra_top_dut.soft_int; - release caliptra_top_dut.timer_int; - generic_input_wires <= 'h0; - end - - else if (ras_test_ctrl.reset_generic_input_wires) begin - `ifdef VERILATOR - generic_input_wires <= {32'h72746C76, ERROR_NONE_SET}; /* 32'h72746c76 is the big-endian ASCII representation of 'vltr' (r t l v) */ - `else - generic_input_wires <= {32'h0, ERROR_NONE_SET}; - `endif - end - - else if (c_state_apb == S_APB_WAIT_ERROR_AXS && rv_dma_resp_error) begin - generic_input_wires <= {32'h0, DMA_ERROR_OBSERVED}; - end - - else if (c_state_apb == S_APB_RD_HW_ERROR_FATAL && apb_xfer_end) begin - if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW]) begin - generic_input_wires <= {32'h0, ICCM_FATAL_OBSERVED}; - end - else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW]) begin - generic_input_wires <= {32'h0, DCCM_FATAL_OBSERVED}; - end - else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW]) begin - generic_input_wires <= {32'h0, NMI_FATAL_OBSERVED}; - end - else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW]) begin - generic_input_wires <= {32'h0, CRYPTO_ERROR_OBSERVED}; - end - else begin - generic_input_wires <= {32'h0, ERROR_NONE_SET}; - end - end - - else if (c_state_apb == S_APB_RD_HW_ERROR_NON_FATAL && apb_xfer_end) begin - if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW]) begin - generic_input_wires <= {32'h0, PROT_NO_LOCK_NON_FATAL_OBSERVED}; - end - else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW]) begin - generic_input_wires <= {32'h0, PROT_OOO_NON_FATAL_OBSERVED}; - end - else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW]) begin - generic_input_wires <= {32'h0, MBOX_NON_FATAL_OBSERVED}; - end - else begin - generic_input_wires <= {32'h0, ERROR_NONE_SET}; - end - end - - end - - always@(negedge core_clk or negedge cptra_pwrgood) begin - // This persists across soft reset - if (!cptra_pwrgood) begin - soc_ifc_hw_error_wdata <= '0; - end - else if (c_state_apb inside {S_APB_RD_HW_ERROR_FATAL, S_APB_RD_HW_ERROR_NON_FATAL} && apb_xfer_end) begin - // HW ERROR registers are W1C, capture the set bits - soc_ifc_hw_error_wdata <= PRDATA; - end - else if (c_state_apb inside {S_APB_WR_HW_ERROR_FATAL, S_APB_WR_HW_ERROR_NON_FATAL} && apb_xfer_end) begin - // Clear after completing the write - soc_ifc_hw_error_wdata <= 0; - end - end - - always@(negedge core_clk or negedge cptra_rst_b) begin - if (!cptra_rst_b) begin - cptra_error_fatal_counter <= 16'h0; - cptra_error_non_fatal_counter <= 16'h0; - end - else begin - cptra_error_fatal_counter <= cptra_error_fatal ? (cptra_error_fatal_counter + 16'h1) : 16'h0; - cptra_error_non_fatal_counter <= cptra_error_non_fatal ? (cptra_error_non_fatal_counter + 16'h1) : 16'h0; - end - end - // Pulse fires about 640ns after the original error interrupt occurs - always_comb cptra_error_fatal_dly_p = cptra_error_fatal_counter == 16'h0040; - always_comb cptra_error_non_fatal_dly_p = cptra_error_non_fatal_counter == 16'h0040; - - always_comb assert_rst_flag_from_fatal = c_state_apb == S_APB_ERROR; - always@(negedge core_clk) begin - if (!cptra_pwrgood) begin - count_deassert_rst_flag_from_fatal <= 0; - end - // Start counting after the fatal flag asserts reset, and continue - // counting until the reset is deasserted - else if (assert_rst_flag_from_fatal || (!cptra_rst_b && |count_deassert_rst_flag_from_fatal)) begin - count_deassert_rst_flag_from_fatal <= count_deassert_rst_flag_from_fatal + 1; - end - else begin - count_deassert_rst_flag_from_fatal <= 0; - end - end - // Leave reset asserted for 32 clock cycles - always_comb deassert_rst_flag_from_fatal = count_deassert_rst_flag_from_fatal == 31; - - assert property (@(posedge core_clk) c_state_apb == S_APB_WR_FUSE_DONE |-> !cptra_error_non_fatal) else begin - $error("cptra_error_non_fatal observed during boot up"); - $finish; - end - assert property (@(posedge core_clk) c_state_apb == S_APB_WR_FUSE_DONE |-> !cptra_error_fatal) else begin - $error("cptra_error_fatal observed during boot up"); - $finish; - end - - always@(negedge core_clk or negedge cptra_rst_b) begin - if(!cptra_rst_b) begin - mbox_apb_dataout_read_ooo <= 1'b0; - end - else if(ras_test_ctrl.do_ooo_access) begin - mbox_apb_dataout_read_ooo <= 1'b1; - end - else if (mbox_apb_dataout_read_ooo && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin - mbox_apb_dataout_read_ooo <= 1'b0; - end - end - - always@(negedge core_clk or negedge cptra_rst_b) begin - if(!cptra_rst_b) begin - mbox_apb_dataout_read_no_lock <= 1'b0; - end - else if(ras_test_ctrl.do_no_lock_access) begin - mbox_apb_dataout_read_no_lock <= 1'b1; - end - else if (mbox_apb_dataout_read_no_lock && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin - mbox_apb_dataout_read_no_lock <= 1'b0; - end - end - - always@(negedge core_clk or negedge cptra_rst_b) begin - if (!cptra_rst_b) begin - mbox_ooo_read_done <= 1'b0; - end - else if (mbox_apb_dataout_read_ooo && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin - mbox_ooo_read_done <= 1'b1; - end - else if (c_state_apb == S_APB_WR_HW_ERROR_NON_FATAL) - mbox_ooo_read_done <= 1'b0; - else if (ras_test_ctrl.reset_ooo_done_flag) - mbox_ooo_read_done <= 1'b0; - end - - always@(negedge core_clk or negedge cptra_rst_b) begin - if (!cptra_rst_b) begin - mbox_no_lock_read_done <= 1'b0; - end - else if (mbox_apb_dataout_read_no_lock && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin - mbox_no_lock_read_done <= 1'b1; - end - else if (c_state_apb == S_APB_WR_HW_ERROR_NON_FATAL) - mbox_no_lock_read_done <= 1'b0; - else if (ras_test_ctrl.reset_no_lock_done_flag) - mbox_no_lock_read_done <= 1'b0; - end - - always@(negedge core_clk or negedge cptra_rst_b) begin - if (!cptra_rst_b) begin - execute_mbox_rx_protocol <= 'b0; - end - else if (c_state_apb == S_APB_WR_EXEC) begin - execute_mbox_rx_protocol <= 'b1; - end - else if (execute_mbox_rx_protocol && ((c_state_apb == S_APB_RST_EXEC) && apb_xfer_end)) begin - execute_mbox_rx_protocol <= 'b0; - end - end - - initial begin - cptra_pwrgood = 1'b0; - BootFSM_BrkPoint = 1'b1; //Set to 1 even before anything starts - cptra_rst_b = 1'b0; - start_apb_fuse_sequence = 1'b0; - //TIE-OFF - PPROT = '0; -`ifndef VERILATOR - if($test$plusargs("dumpon")) $dumpvars; -`endif +caliptra_top_tb_soc_bfm soc_bfm_inst ( + .core_clk (core_clk ), - if($test$plusargs("RAND_DOE_VALUES")) begin - //cptra_obf_key = cptra_obf_key_tb; - for (int dword = 0; dword < $bits(cptra_obf_key/32); dword++) begin - cptra_obf_key[dword] = cptra_obf_key_tb[dword]; - end - - cptra_uds_tb = cptra_uds_rand; - cptra_fe_tb = cptra_fe_rand; - end - else begin - //Key for UDS - cptra_obf_key_uds = 256'h54682728db5035eb04b79645c64a95606abb6ba392b6633d79173c027c5acf77; - cptra_uds_tb = 384'he4046d05385ab789c6a72866e08350f93f583e2a005ca0faecc32b5cfc323d461c76c107307654db5566a5bd693e227c; - - //Key for FE - cptra_obf_key_fe = 256'h31358e8af34d6ac31c958bbd5c8fb33c334714bffb41700d28b07f11cfe891e7; - cptra_fe_tb = 256'hb32e2b171b63827034ebb0d1909f7ef1d51c5f82c1bb9bc26bc4ac4dccdee835; - /*256'h7dca6154c2510ae1c87b1b422b02b621bb06cac280023894fcff3406af08ee9b, - 256'he1dd72419beccddff77c722d992cdcc87e9c7486f56ab406ea608d8c6aeb060c, - 256'h64cf2785ad1a159147567e39e303370da445247526d95942bf4d7e88057178b0};*/ - - //swizzle the key so it matches the endianness of AES block - //used for visual inspection of uds/fe flow, manually switching keys and checking both - for (int dword = 0; dword < $bits(cptra_obf_key/32); dword++) begin - //cptra_obf_key[dword] = cptra_obf_key_uds[dword]; - cptra_obf_key[dword] = cptra_obf_key_fe[dword]; - end - end - - end - - assign assert_rst_flag = assert_rst_flag_from_service || assert_rst_flag_from_fatal; - assign deassert_rst_flag = deassert_rst_flag_from_service || deassert_rst_flag_from_fatal; - always @(posedge core_clk) begin - //Reset/pwrgood assertion during runtime - if (cycleCnt == 15 || deassert_hard_rst_flag) begin - $display ("\n\n\n\n\n\n"); - $display ("SoC: Asserting cptra_pwrgood and breakpoint\n"); - //assert power good - cptra_pwrgood <= 1'b1; - //BootFSM_BrkPoint <= 1'b1; - end - else if (cycleCnt == 20 || deassert_rst_flag) begin - $display ("SoC: De-Asserting cptra_rst_b\n"); - //de-assert reset - cptra_rst_b <= 1'b1; - end - else if (assert_hard_rst_flag) begin - cptra_pwrgood <= 'b0; - cptra_rst_b <= 'b0; - start_apb_fuse_sequence <= 1'b0; - end - else if (assert_rst_flag) begin - cptra_rst_b <= 'b0; - start_apb_fuse_sequence <= 1'b0; - end - //wait for fuse indication - else if (ready_for_fuses == 1'b0) begin - //nop - cycleCnt_Flag <= cycleCnt; - end - else if (cycleCnt == cycleCnt_Flag + 5) begin - start_apb_fuse_sequence <= 1'b1; - end - end - - always@(negedge core_clk or negedge cptra_rst_b) begin - if (!cptra_rst_b) begin - dlen <= '0; - end - else if ((c_state_apb == S_APB_RD_DLEN) && apb_xfer_end) begin - dlen <= PRDATA; - end - end - - always@(posedge core_clk or negedge cptra_rst_b) begin - if (!cptra_rst_b) begin - c_state_apb <= S_APB_IDLE; - apb_wr_count <= '0; - apb_rd_count <= '0; - apb_enable_ph <= 0; - end - else begin - c_state_apb <= n_state_apb; - apb_wr_count <= apb_wr_count_nxt; - apb_rd_count <= apb_rd_count_nxt; - //next phase is an access phase if this is setup phase OR it's access and responder isn't ready - apb_enable_ph <= (PSEL & ~PENABLE) | (PSEL & PENABLE & ~PREADY); - end - if (c_state_apb != n_state_apb) begin - case (n_state_apb) - S_APB_WR_UDS: begin - $display ("CLP: Ready for fuse download\n"); - $display ("SoC: Writing obfuscated UDS to fuse bank\n"); - end - S_APB_WR_FE: begin - $display ("SoC: Writing obfuscated Field Entropy to fuse bank\n"); - end - S_APB_WR_SOC_STEPPING_ID: begin - $display ("SoC: Writing SOC Stepping ID to fuse bank\n"); - end - S_APB_WR_FUSE_DONE: begin - $display ("SoC: Writing fuse done register\n"); - end - S_APB_POLL_FLOW_ST: begin - $display ("SoC: Polling Flow Status\n"); - end - S_APB_WR_BOOT_GO: begin - $display ("SoC: Writing BootGo register\n"); - end - S_APB_WAIT_FW_TEST: begin - $display ("CLP: ROM Flow in progress...\n"); - end - S_APB_POLL_LOCK: begin - $display ("CLP: Ready for firmware push\n"); - $display ("SoC: Requesting mailbox lock\n"); - end - S_APB_PRE_WR_CMD: begin - $display ("SoC: Lock granted\n"); - end - S_APB_WR_CMD: begin - $display ("SoC: Writing the Command Register\n"); - end - S_APB_WR_DLEN: begin - $display ("SoC: Writing the Data Length Register\n"); - end - S_APB_WR_DATAIN: begin - $display ("SoC: Writing the Firmware into Data-in Register\n"); - end - S_APB_WR_EXEC: begin - $display ("SoC: Setting the Execute Register\n"); - end - S_APB_WR_STATUS: begin - $display ("SoC: Writing the Mbox Status Register\n"); - end - S_APB_WAIT_ERROR_AXS: begin - $display("SoC: Waiting to see cptra_error_fatal/non_fatal\n"); - end - S_APB_RD_HW_ERROR_FATAL: begin - $display("SoC: Observed cptra_error_fatal; reading Caliptra register\n"); - end - S_APB_WR_HW_ERROR_FATAL: begin - $display("SoC: Observed cptra_error_fatal; writing to clear Caliptra register\n"); - end - S_APB_RD_HW_ERROR_NON_FATAL: begin - $display("SoC: Observed cptra_error_non_fatal; reading Caliptra register\n"); - end - S_APB_WR_HW_ERROR_NON_FATAL: begin - $display("SoC: Observed cptra_error_non_fatal; writing to clear Caliptra register\n"); - end - S_APB_DONE: begin - end - S_APB_RD_DLEN: begin - $display("SoC: Reading the Data Length Register\n"); - end - S_APB_RD_DATAOUT: begin - $display("SoC: Reading the Data Out Register\n"); - end - S_APB_RST_EXEC: begin - $display("SoC: Resetting the Execute Register\n"); - end - default: begin - $display("Entering unexpected APB state: %p", n_state_apb); - end - endcase - end - end - - always_comb begin - apb_wr_count_nxt = 0; - apb_rd_count_nxt = 0; - case (c_state_apb) inside - S_APB_IDLE: begin - if (start_apb_fuse_sequence) - n_state_apb = S_APB_WR_UDS; - else - n_state_apb = S_APB_IDLE; - end - //load fuses - S_APB_WR_UDS: begin - if (apb_xfer_end && apb_wr_count == (`CLP_OBF_UDS_DWORDS-1)) begin - n_state_apb = S_APB_WR_FE; - apb_wr_count_nxt = '0; - end - else if (apb_xfer_end) begin - n_state_apb = S_APB_WR_UDS; - apb_wr_count_nxt = apb_wr_count + 1; - end - else begin - n_state_apb = S_APB_WR_UDS; - apb_wr_count_nxt = apb_wr_count; - end - end - S_APB_WR_FE: begin - if (apb_xfer_end && apb_wr_count == (`CLP_OBF_FE_DWORDS-1)) begin - n_state_apb = S_APB_WR_SOC_STEPPING_ID; - apb_wr_count_nxt = '0; - end - else if (apb_xfer_end) begin - n_state_apb = S_APB_WR_FE; - apb_wr_count_nxt = apb_wr_count + 1; - end - else begin - n_state_apb = S_APB_WR_FE; - apb_wr_count_nxt = apb_wr_count; - end - end - S_APB_WR_SOC_STEPPING_ID: begin - if (apb_xfer_end) begin - n_state_apb = S_APB_WR_FUSE_DONE; - end - else begin - n_state_apb = S_APB_WR_SOC_STEPPING_ID; - end - end - //set fuse done - S_APB_WR_FUSE_DONE: begin - if (apb_xfer_end) begin - if(BootFSM_BrkPoint) begin - n_state_apb = S_APB_POLL_FLOW_ST; - end - else begin - n_state_apb = S_APB_WAIT_FW_TEST; - end - end - else begin - n_state_apb = S_APB_WR_FUSE_DONE; - end - end - S_APB_POLL_FLOW_ST: begin - if (apb_xfer_end && (PRDATA[`SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW] == 0)) begin - n_state_apb = S_APB_WR_BOOT_GO; - end - else begin - n_state_apb = S_APB_POLL_FLOW_ST; - end - end - //Write BootGo register - S_APB_WR_BOOT_GO: begin - if(apb_xfer_end) begin - n_state_apb = S_APB_WAIT_FW_TEST; - end - else begin - n_state_apb = S_APB_WR_BOOT_GO; - end - end - - //This is for Caliptra Demo, smoke tests will stop here since they don't set ready for fw - //wait for fw req - S_APB_WAIT_FW_TEST: begin - if (ready_for_fw_push & (apb_wr_count == 5)) begin - n_state_apb = S_APB_POLL_LOCK; - apb_wr_count_nxt = 0; - end - else if (ready_for_fw_push) begin - n_state_apb = S_APB_WAIT_FW_TEST; - apb_wr_count_nxt = apb_wr_count + 1; - end - else if (ras_test_ctrl.error_injection_seen) begin - n_state_apb = S_APB_WAIT_ERROR_AXS; - end - else begin - n_state_apb = S_APB_WAIT_FW_TEST; - apb_wr_count_nxt = 0; - end - end - // poll for lock register - S_APB_POLL_LOCK: begin - if (apb_xfer_end && (PRDATA != 0)) begin - n_state_apb = mbox_apb_dataout_read_ooo ? S_APB_RD_DLEN : S_APB_WR_CMD; - end - else begin - n_state_apb = S_APB_POLL_LOCK; - end - end - S_APB_PRE_WR_CMD: begin - if (apb_wr_count == 5) begin - n_state_apb = S_APB_WR_CMD; - apb_wr_count_nxt = 0; - end - else begin - n_state_apb = S_APB_PRE_WR_CMD; - apb_wr_count_nxt = apb_wr_count + 1; - end - end - //write to MBOX_ADDR_CMD - S_APB_WR_CMD: begin - if (apb_xfer_end) - n_state_apb = S_APB_WR_DLEN; - else - n_state_apb = S_APB_WR_CMD; - end - // write to MBOX_ADDR_DLEN - S_APB_WR_DLEN: begin - if (apb_xfer_end) - n_state_apb = S_APB_WR_DATAIN; - else - n_state_apb = S_APB_WR_DLEN; - end - // write a random block in - S_APB_WR_DATAIN: begin - if (apb_xfer_end && apb_wr_count == (FW_NUM_DWORDS-1)) begin - n_state_apb = S_APB_WR_EXEC; - apb_wr_count_nxt = '0; - end - else if (apb_xfer_end) begin - n_state_apb = S_APB_WR_DATAIN; - apb_wr_count_nxt = apb_wr_count + 1; - end - else begin - n_state_apb = S_APB_WR_DATAIN; - apb_wr_count_nxt = apb_wr_count; - end - end - // execute - S_APB_WR_EXEC: begin - if (apb_xfer_end) - n_state_apb = S_APB_DONE; - else - n_state_apb = S_APB_WR_EXEC; - end - // status - S_APB_WR_STATUS: begin - if (apb_xfer_end) - n_state_apb = S_APB_DONE; - else - n_state_apb = S_APB_WR_STATUS; - end - S_APB_WAIT_ERROR_AXS: begin - if (cptra_error_fatal_dly_p) begin - n_state_apb = S_APB_RD_HW_ERROR_FATAL; - end - else if (cptra_error_non_fatal_dly_p) begin - n_state_apb = S_APB_RD_HW_ERROR_NON_FATAL; - end - else if (soc_ifc_hw_error_wdata) begin - n_state_apb = S_APB_WR_HW_ERROR_FATAL; - end - else if (ras_test_ctrl.do_no_lock_access) begin - n_state_apb = S_APB_RD_DLEN; - end - else if (mbox_apb_dataout_read_ooo && !mbox_ooo_read_done) begin - n_state_apb = S_APB_POLL_LOCK; - end - else begin - n_state_apb = S_APB_WAIT_ERROR_AXS; - end - end - S_APB_RD_HW_ERROR_FATAL: begin - // Go to ERROR state to wait for cptra_rst_b to assert - if (apb_xfer_end) begin - n_state_apb = S_APB_ERROR; - end - else begin - n_state_apb = S_APB_RD_HW_ERROR_FATAL; - end - end - S_APB_WR_HW_ERROR_FATAL: begin - if (apb_xfer_end) begin - n_state_apb = S_APB_WAIT_ERROR_AXS; - end - else begin - n_state_apb = S_APB_WR_HW_ERROR_FATAL; - end - end - S_APB_RD_HW_ERROR_NON_FATAL: begin - if (apb_xfer_end) begin - n_state_apb = S_APB_WR_HW_ERROR_NON_FATAL; - end - else begin - n_state_apb = S_APB_RD_HW_ERROR_NON_FATAL; - end - end - S_APB_WR_HW_ERROR_NON_FATAL: begin - if (apb_xfer_end) begin - n_state_apb = S_APB_WAIT_ERROR_AXS; - end - else begin - n_state_apb = S_APB_WR_HW_ERROR_NON_FATAL; - end - end - S_APB_DONE: begin - apb_wr_count_nxt = '0; - apb_rd_count_nxt = '0; - if (mailbox_data_avail && execute_mbox_rx_protocol) - n_state_apb = S_APB_RD_DLEN; - else if (mailbox_data_avail && ~status_set && ~execute_mbox_rx_protocol) - n_state_apb = S_APB_WR_STATUS; - else - n_state_apb = S_APB_DONE; - end - S_APB_RD_DLEN: begin - if (apb_xfer_end) - n_state_apb = S_APB_RD_DATAOUT; - else - n_state_apb = S_APB_RD_DLEN; - end - S_APB_RD_DATAOUT: begin - if (apb_xfer_end && (apb_rd_count == dlen)) begin - n_state_apb = (mbox_no_lock_read_done || mbox_ooo_read_done) ? S_APB_WAIT_ERROR_AXS : S_APB_RST_EXEC; - apb_rd_count_nxt = '0; - end - else if (apb_xfer_end) begin - n_state_apb = S_APB_RD_DATAOUT; - apb_rd_count_nxt = apb_rd_count + 1; - end - else begin - n_state_apb = S_APB_RD_DATAOUT; - apb_rd_count_nxt = apb_rd_count; - end - end - S_APB_RST_EXEC: begin - if (apb_xfer_end) - n_state_apb = S_APB_DONE; - else - n_state_apb = S_APB_RST_EXEC; - end - default: begin - apb_wr_count_nxt = apb_wr_count; - apb_rd_count_nxt = apb_rd_count; - n_state_apb = S_APB_ERROR; - end - endcase - end + .cptra_pwrgood (cptra_pwrgood ), + .cptra_rst_b (cptra_rst_b ), + + .BootFSM_BrkPoint(BootFSM_BrkPoint), + .cycleCnt (cycleCnt ), + + .cptra_obf_key (cptra_obf_key ), + + .cptra_uds_rand (cptra_uds_rand ), + .cptra_fe_rand (cptra_fe_rand ), + .cptra_obf_key_tb(cptra_obf_key_tb), + + .m_axi_bfm_if(m_axi_bfm_if), + + .ready_for_fuses (ready_for_fuses ), + .ready_for_fw_push (ready_for_fw_push ), + .mailbox_data_avail(mailbox_data_avail), + + .ras_test_ctrl(ras_test_ctrl), + + .generic_input_wires(generic_input_wires), + + .cptra_error_fatal(cptra_error_fatal), + .cptra_error_non_fatal(cptra_error_non_fatal), - always@(posedge core_clk or negedge cptra_rst_b) begin - if (!cptra_rst_b) begin - status_set <= '0; - end else begin - status_set <= ~mailbox_data_avail ? '0 : - (c_state_apb == S_APB_WR_STATUS) ? '1 : status_set; - end - end - - assign apb_xfer_end = PSEL && PENABLE && PREADY; - always@(posedge core_clk) begin - if ((n_state_apb == S_APB_WR_DATAIN) && apb_xfer_end) - fw_blob[apb_wr_count_nxt] <= $urandom; - end - always_comb begin - case (c_state_apb) inside - S_APB_WR_UDS: begin - PADDR = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_0 + 4 * apb_wr_count; - PWDATA = cptra_uds_tb[apb_wr_count]; - end - S_APB_WR_FE: begin - PADDR = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 + 4 * apb_wr_count; - PWDATA = cptra_fe_tb[apb_wr_count]; - end - S_APB_WR_SOC_STEPPING_ID: begin - PADDR = `CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID; - PWDATA = $urandom(); - end - S_APB_WR_FUSE_DONE: begin - PADDR = `CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE; - PWDATA = 32'h00000001; - end - S_APB_POLL_FLOW_ST: begin - PADDR = `CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS; - PWDATA = '0; - end - S_APB_WR_BOOT_GO: begin - PADDR = `CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO; - PWDATA = 32'h00000001; - end - S_APB_POLL_LOCK: begin - PADDR = `CLP_MBOX_CSR_MBOX_LOCK; - PWDATA = '0; - end - S_APB_WR_CMD: begin - PADDR = `CLP_MBOX_CSR_MBOX_CMD; - PWDATA = 32'hBA5EBA11; - end - S_APB_WR_DLEN: begin - PADDR = `CLP_MBOX_CSR_MBOX_DLEN; - PWDATA = FW_NUM_DWORDS*4; - end - S_APB_WR_DATAIN: begin - PADDR = `CLP_MBOX_CSR_MBOX_DATAIN; - PWDATA = fw_blob[apb_wr_count]; - end - S_APB_WR_EXEC: begin - PADDR = `CLP_MBOX_CSR_MBOX_EXECUTE; - PWDATA = 32'h00000001; - end - S_APB_WR_STATUS: begin - PADDR = `CLP_MBOX_CSR_MBOX_STATUS; - PWDATA = 32'h00000001; - end - S_APB_RD_HW_ERROR_FATAL: begin - PADDR = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL; - PWDATA = soc_ifc_hw_error_wdata; - end - S_APB_WR_HW_ERROR_FATAL: begin - PADDR = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL; - PWDATA = soc_ifc_hw_error_wdata; - end - S_APB_RD_HW_ERROR_NON_FATAL: begin - PADDR = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL; - PWDATA = soc_ifc_hw_error_wdata; - end - S_APB_WR_HW_ERROR_NON_FATAL: begin - PADDR = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL; - PWDATA = soc_ifc_hw_error_wdata; - end - S_APB_DONE: begin - PADDR = '0; - PWDATA = '0; - end - S_APB_RD_DLEN: begin - PADDR = `CLP_MBOX_CSR_MBOX_DLEN; - PWDATA = dlen; - end - S_APB_RD_DATAOUT: begin - PADDR = `CLP_MBOX_CSR_MBOX_DATAOUT; - PWDATA = '0; - end - S_APB_RST_EXEC: begin - PADDR = `CLP_MBOX_CSR_MBOX_EXECUTE; - PWDATA = '0; - end - default: begin - PADDR = '0; - PWDATA = '0; - end - endcase - end - always_comb begin - PENABLE = apb_enable_ph; - case (c_state_apb) inside - S_APB_IDLE: begin - PSEL = 0; - PWRITE = 0; - PAUSER = 0; - end - S_APB_WR_UDS: begin - PSEL = 1; - PWRITE = 1; - PAUSER = 0; - end - S_APB_WR_FE: begin - PSEL = 1; - PWRITE = 1; - PAUSER = 0; - end - S_APB_WR_SOC_STEPPING_ID: begin - PSEL = 1; - PWRITE = 1; - PAUSER = 0; - end - S_APB_WR_FUSE_DONE: begin - PSEL = 1; - PWRITE = 1; - PAUSER = 0; - end - S_APB_POLL_FLOW_ST: begin - PSEL = 1; - PWRITE = 0; - PAUSER = 0; - end - S_APB_WR_BOOT_GO: begin - PSEL = 1; - PWRITE = 1; - PAUSER = 0; - end - S_APB_POLL_LOCK: begin - PSEL = 1; - PWRITE = 0; - PAUSER = '1; - end - S_APB_WR_CMD: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - S_APB_WR_DLEN: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - S_APB_WR_DATAIN: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - S_APB_WR_EXEC: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - S_APB_WR_STATUS: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - S_APB_RD_HW_ERROR_FATAL: begin - PSEL = 1; - PWRITE = 0; - PAUSER = '1; - end - S_APB_WR_HW_ERROR_FATAL: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - S_APB_RD_HW_ERROR_NON_FATAL: begin - PSEL = 1; - PWRITE = 0; - PAUSER = '1; - end - S_APB_WR_HW_ERROR_NON_FATAL: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - S_APB_DONE: begin - PSEL = 0; - PWRITE = 0; - PAUSER = 0; - end - S_APB_RD_DLEN: begin - PSEL = 1; - PWRITE = 0; - PAUSER = '1; //TODO - which value? - end - S_APB_RD_DATAOUT: begin - PSEL = 1; - PWRITE = 0; - PAUSER = '1; - end - S_APB_RST_EXEC: begin - PSEL = 1; - PWRITE = 1; - PAUSER = '1; - end - default: begin - PSEL = 0; - PWRITE = 0; - PAUSER = 0; - end - endcase - end + //Interrupt flags + .int_flag(int_flag), + .cycleCnt_smpl_en(cycleCnt_smpl_en), + + .assert_hard_rst_flag(assert_hard_rst_flag), + .deassert_hard_rst_flag(deassert_hard_rst_flag), + .assert_rst_flag_from_service(assert_rst_flag_from_service), + .deassert_rst_flag_from_service(deassert_rst_flag_from_service) +); + // JTAG DPI jtagdpi #( .Name ("jtag0"), @@ -1085,16 +214,13 @@ caliptra_top caliptra_top_dut ( .jtag_tdo(jtag_tdo), .jtag_tdoEn(jtag_tdoEn), - .PADDR(PADDR), - .PPROT(PPROT), - .PAUSER(PAUSER), - .PENABLE(PENABLE), - .PRDATA(PRDATA), - .PREADY(PREADY), - .PSEL(PSEL), - .PSLVERR(), - .PWDATA(PWDATA), - .PWRITE(PWRITE), + //SoC AXI Interface + .s_axi_w_if(m_axi_bfm_if.w_sub), + .s_axi_r_if(m_axi_bfm_if.r_sub), + + //AXI DMA Interface + .m_axi_w_if(m_axi_if.w_mgr), + .m_axi_r_if(m_axi_if.r_mgr), .qspi_clk_o (qspi_clk), .qspi_cs_no (qspi_cs_n), @@ -1127,6 +253,8 @@ caliptra_top caliptra_top_dut ( .mailbox_flow_done(), .BootFSM_BrkPoint(BootFSM_BrkPoint), + .recovery_data_avail(1'b1/*TODO*/), + //SoC Interrupts .cptra_error_fatal (cptra_error_fatal ), .cptra_error_non_fatal(cptra_error_non_fatal), @@ -1249,69 +377,73 @@ caliptra_top_tb_services #( ); -`define RV_INST caliptra_top_dut.rvtop -`define RV_IDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_IDMA] -`define RV_DDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_DDMA] -task force_ahb_dma_read(input logic [31:0] address); - while(`RV_INST.dma_hsel) @(posedge core_clk); - force `RV_IDMA_RESP_INST.hreadyout = 1'b0; - force `RV_DDMA_RESP_INST.hreadyout = 1'b0; - - force `RV_INST.dma_haddr = address; - force `RV_INST.dma_hsize = 3'b010; // 4-bytes - force `RV_INST.dma_hwrite = 1'b0; - force `RV_INST.dma_hwdata = '0; - force `RV_INST.dma_hreadyin = 1'b1; - force `RV_INST.dma_hsel = 1'b1; - force `RV_INST.dma_htrans = 2'b10; - - // Wait for command to be accepted - do @(posedge core_clk); while(!`RV_INST.dma_hreadyout); - force `RV_INST.dma_htrans = 2'b00; - // Wait for response to be provided - do @(posedge core_clk); while(!`RV_INST.dma_hreadyout); - $display("[%t] AHB DMA FORCE READ: Address 0x%x Data 0x%x Resp 0x%x", $time, address, `RV_INST.dma_hrdata, `RV_INST.dma_hresp); - if (`RV_INST.dma_hresp) - rv_dma_resp_error = 1'b1; - release `RV_IDMA_RESP_INST.hreadyout; - release `RV_DDMA_RESP_INST.hreadyout; - - release `RV_INST.dma_htrans; - release `RV_INST.dma_haddr; - release `RV_INST.dma_hsize; - release `RV_INST.dma_hwrite; - release `RV_INST.dma_hwdata; - release `RV_INST.dma_hsel; - release `RV_INST.dma_hreadyin; -endtask - -task force_ahb_dma_loop_read(input logic [31:0] start_addr, input logic [19:0] count); - automatic logic [31:0] addr; - addr = start_addr; - $display("[%t] AHB DMA FORCE LOOP READ: Start Address 0x%x Count 0x%x", $time, addr, count); - if ($isunknown(start_addr) || $isunknown(addr)) - $error("[%t] Unknown signal found: start_addr 0x%x addr 0x%x", $time, start_addr, addr); - repeat(count) begin - force_ahb_dma_read(addr); - addr += 4; - end -endtask - -initial begin - fork - forever @(posedge core_clk) begin - if (ras_test_ctrl.dccm_read_burst.start) - force_ahb_dma_loop_read(ras_test_ctrl.dccm_read_burst.addr, ras_test_ctrl.dccm_read_burst.count); - if (ras_test_ctrl.iccm_read_burst.start) - force_ahb_dma_loop_read(ras_test_ctrl.iccm_read_burst.addr, ras_test_ctrl.iccm_read_burst.count); - end - forever @(posedge core_clk) begin - if (c_state_apb != S_APB_WAIT_ERROR_AXS) - rv_dma_resp_error = 1'b0; - end - join +// Dummy interconnect +always_comb begin + // AXI AR + axi_sram_if.araddr = m_axi_if.araddr[AXI_SRAM_ADDR_WIDTH-1:0]; + axi_sram_if.arburst = m_axi_if.arburst; + axi_sram_if.arsize = m_axi_if.arsize ; + axi_sram_if.arlen = m_axi_if.arlen ; + axi_sram_if.aruser = m_axi_if.aruser ; + axi_sram_if.arid = m_axi_if.arid ; + axi_sram_if.arlock = m_axi_if.arlock ; + axi_sram_if.arvalid = m_axi_if.arvalid && m_axi_if.araddr[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH] == AXI_SRAM_BASE_ADDR[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH]; + m_axi_if.arready = axi_sram_if.arready; + + // AXI R + m_axi_if.rdata = axi_sram_if.rdata ; + m_axi_if.rresp = axi_sram_if.rresp ; + m_axi_if.rid = axi_sram_if.rid ; + m_axi_if.rlast = axi_sram_if.rlast ; + m_axi_if.rvalid = axi_sram_if.rvalid; + axi_sram_if.rready = m_axi_if.rready ; + + // AXI AW + axi_sram_if.awaddr = m_axi_if.awaddr[AXI_SRAM_ADDR_WIDTH-1:0]; + axi_sram_if.awburst = m_axi_if.awburst; + axi_sram_if.awsize = m_axi_if.awsize ; + axi_sram_if.awlen = m_axi_if.awlen ; + axi_sram_if.awuser = m_axi_if.awuser ; + axi_sram_if.awid = m_axi_if.awid ; + axi_sram_if.awlock = m_axi_if.awlock ; + axi_sram_if.awvalid = m_axi_if.awvalid && m_axi_if.awaddr[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH] == AXI_SRAM_BASE_ADDR[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH]; + m_axi_if.awready = axi_sram_if.awready; + + // AXI W + axi_sram_if.wdata = m_axi_if.wdata ; + axi_sram_if.wstrb = m_axi_if.wstrb ; + axi_sram_if.wvalid = m_axi_if.wvalid ; + axi_sram_if.wlast = m_axi_if.wlast ; + m_axi_if.wready = axi_sram_if.wready ; + + // AXI B + m_axi_if.bresp = axi_sram_if.bresp ; + m_axi_if.bid = axi_sram_if.bid ; + m_axi_if.bvalid = axi_sram_if.bvalid ; + axi_sram_if.bready = m_axi_if.bready ; end +// Fake "MCU" SRAM block +caliptra_axi_sram #( + .AW(AXI_SRAM_ADDR_WIDTH), + .DW(CPTRA_AXI_DMA_DATA_WIDTH), + .UW(CPTRA_AXI_DMA_USER_WIDTH), + .IW(CPTRA_AXI_DMA_ID_WIDTH), + .EX_EN(0) +) i_axi_sram ( + .clk(core_clk), + .rst_n(cptra_rst_b), + + // AXI INF + .s_axi_w_if(axi_sram_if.w_sub), + .s_axi_r_if(axi_sram_if.r_sub) +); +`ifdef VERILATOR +initial i_axi_sram.i_sram.ram = '{default:'{default:8'h00}}; +`else +initial i_axi_sram.i_sram.ram = '{default:8'h00}; +`endif + caliptra_top_sva sva(); endmodule diff --git a/src/integration/tb/caliptra_top_tb_pkg.sv b/src/integration/tb/caliptra_top_tb_pkg.sv index 3dc9a58f6..d98ff8899 100644 --- a/src/integration/tb/caliptra_top_tb_pkg.sv +++ b/src/integration/tb/caliptra_top_tb_pkg.sv @@ -14,6 +14,7 @@ // package caliptra_top_tb_pkg; +import soc_ifc_pkg::*; `ifndef VERILATOR class bitflip_mask_generator #(int MBOX_DATA_AND_ECC_W = 39); @@ -69,8 +70,6 @@ typedef struct packed { logic reset_generic_input_wires; logic do_no_lock_access; logic do_ooo_access; - logic reset_ooo_done_flag; - logic reset_no_lock_done_flag; } ras_test_ctrl_t; // Values to drive onto GENERIC INPUT WIRES in response to RAS testing @@ -84,4 +83,10 @@ localparam CRYPTO_ERROR_OBSERVED = 32'hdeadface; localparam DMA_ERROR_OBSERVED = 32'hfadebadd; localparam ERROR_NONE_SET = 32'hba5eba11; /* default value for a test with no activity observed by TB */ +// AXI SRAM config +localparam AXI_SRAM_SIZE_BYTES = 65536; +localparam AXI_SRAM_ADDR_WIDTH = $clog2(AXI_SRAM_SIZE_BYTES); +localparam AXI_SRAM_DEPTH = AXI_SRAM_SIZE_BYTES / (CPTRA_AXI_DMA_DATA_WIDTH/8); +localparam logic [`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:0] AXI_SRAM_BASE_ADDR = `CALIPTRA_AXI_DMA_ADDR_WIDTH'h0001_2345_0000; + endpackage diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv index e2861b2ae..8a965943c 100644 --- a/src/integration/tb/caliptra_top_tb_services.sv +++ b/src/integration/tb/caliptra_top_tb_services.sv @@ -262,7 +262,7 @@ module caliptra_top_tb_services // 8'he4 - Disable all SRAM error injection (Mailbox, ICCM, DCCM) // 8'he5 - Request TB to initiate Mailbox flow without lock (violation) // 8'he6 - Request TB to initiate Mailbox flow with out-of-order accesses (violation) - // 8'he7 - Reset mailbox out-of-order flag when non-fatal error is masked (allows the test to continue) + // 8'he7 - Reset mailbox out-of-order flag when non-fatal error is masked (allows the test to continue) [Deprecated] // 8'he8 - Enable scan mode when DOE fsm transitions to done state // 8'he9 - Force dmi_reg_en input to clk gate to emulate JTAG accesses // 8'hea - Set random values to WDT timer1 and timer2 @@ -325,32 +325,22 @@ module caliptra_top_tb_services if (!cptra_rst_b) begin ras_test_ctrl.do_no_lock_access <= 1'b0; ras_test_ctrl.do_ooo_access <= 1'b0; - ras_test_ctrl.reset_ooo_done_flag <= 1'b0; - ras_test_ctrl.reset_no_lock_done_flag <= 1'b0; end else if((WriteData[7:0] == 8'he5) && mailbox_write) begin ras_test_ctrl.do_no_lock_access <= 1'b1; ras_test_ctrl.do_ooo_access <= 1'b0; - ras_test_ctrl.reset_ooo_done_flag <= 1'b0; - ras_test_ctrl.reset_no_lock_done_flag <= 1'b0; end else if((WriteData[7:0] == 8'he6) && mailbox_write) begin ras_test_ctrl.do_no_lock_access <= 1'b0; ras_test_ctrl.do_ooo_access <= 1'b1; - ras_test_ctrl.reset_ooo_done_flag <= 1'b0; - ras_test_ctrl.reset_no_lock_done_flag <= 1'b0; end else if ((WriteData[7:0] == 8'he7) && mailbox_write) begin ras_test_ctrl.do_no_lock_access <= 1'b0; ras_test_ctrl.do_ooo_access <= 1'b0; - ras_test_ctrl.reset_ooo_done_flag <= 1'b1; - ras_test_ctrl.reset_no_lock_done_flag <= 1'b1; end else begin ras_test_ctrl.do_no_lock_access <= 1'b0; ras_test_ctrl.do_ooo_access <= 1'b0; - ras_test_ctrl.reset_ooo_done_flag <= 1'b0; - ras_test_ctrl.reset_no_lock_done_flag <= 1'b0; end end diff --git a/src/integration/tb/caliptra_top_tb_soc_bfm.sv b/src/integration/tb/caliptra_top_tb_soc_bfm.sv new file mode 100644 index 000000000..4968e34e7 --- /dev/null +++ b/src/integration/tb/caliptra_top_tb_soc_bfm.sv @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +`include "common_defines.sv" +`include "config_defines.svh" +`include "caliptra_reg_defines.svh" +`include "caliptra_macros.svh" + +module caliptra_top_tb_soc_bfm +import axi_pkg::*; +import soc_ifc_pkg::*; +import caliptra_top_tb_pkg::*; #( + parameter SKIP_BRINGUP = 0 +) ( + input logic core_clk, + output logic cptra_pwrgood, + output logic cptra_rst_b, + output logic BootFSM_BrkPoint, + input int cycleCnt, + + output logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key, + + input logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] cptra_uds_rand, + input logic [0:`CLP_OBF_FE_DWORDS-1] [31:0] cptra_fe_rand, + input logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] cptra_obf_key_tb, + + axi_if m_axi_bfm_if, + + input logic ready_for_fuses, + input logic ready_for_fw_push, + input logic mailbox_data_avail, + + input var ras_test_ctrl_t ras_test_ctrl, + + output logic [63:0] generic_input_wires, + + input logic cptra_error_fatal, + input logic cptra_error_non_fatal, + + //Interrupt flags + input logic int_flag, + input logic cycleCnt_smpl_en, + + input logic assert_hard_rst_flag, + input logic deassert_hard_rst_flag, + input logic assert_rst_flag_from_service, + input logic deassert_rst_flag_from_service + +); + localparam FW_NUM_DWORDS = 256; + + int poll_count; + + logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] cptra_obf_key_uds, cptra_obf_key_fe; + + logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] cptra_uds_tb; + logic [0:`CLP_OBF_FE_DWORDS-1][31:0] cptra_fe_tb; + + // AXI request signals + axi_resp_e wresp, rresp; + logic [`CALIPTRA_AXI_DATA_WIDTH-1:0] wdata, rdata; + logic [`CALIPTRA_AXI_DATA_WIDTH/8-1:0] wstrb_array[]; + logic [`CALIPTRA_AXI_DATA_WIDTH-1:0] rdata_array[]; + axi_resp_e rresp_array[]; + + int byte_count; + int dw_count; + + logic [15:0] cptra_error_fatal_counter; + logic [15:0] cptra_error_non_fatal_counter; + logic cptra_error_fatal_dly_p; + logic cptra_error_non_fatal_dly_p; + + logic rv_dma_resp_error; + + logic [`CALIPTRA_AXI_DATA_WIDTH-1:0] soc_ifc_hw_error_wdata; + + process boot_and_cmd_flow; + + logic assert_rst_flag_from_fatal; + logic assert_rst_flag; + int count_deassert_rst_flag_from_fatal; + logic deassert_rst_flag_from_fatal; + logic deassert_rst_flag; + + logic [31:0] fw_blob []; + + always@(negedge core_clk or negedge cptra_rst_b) begin + if (!cptra_rst_b) begin + cptra_error_fatal_counter <= 16'h0; + cptra_error_non_fatal_counter <= 16'h0; + end + else begin + cptra_error_fatal_counter <= cptra_error_fatal ? (cptra_error_fatal_counter + 16'h1) : 16'h0; + cptra_error_non_fatal_counter <= cptra_error_non_fatal ? (cptra_error_non_fatal_counter + 16'h1) : 16'h0; + end + end + // Pulse fires about 640ns after the original error interrupt occurs + always_comb cptra_error_fatal_dly_p = cptra_error_fatal_counter == 16'h0040; + always_comb cptra_error_non_fatal_dly_p = cptra_error_non_fatal_counter == 16'h0040; + + always@(negedge core_clk) begin + if (!cptra_pwrgood) begin + count_deassert_rst_flag_from_fatal <= 0; + end + // Start counting after the fatal flag asserts reset, and continue + // counting until the reset is deasserted + else if (assert_rst_flag_from_fatal || (!cptra_rst_b && |count_deassert_rst_flag_from_fatal)) begin + count_deassert_rst_flag_from_fatal <= count_deassert_rst_flag_from_fatal + 1; + end + else begin + count_deassert_rst_flag_from_fatal <= 0; + end + end + // Leave reset asserted for 32 clock cycles + always_comb deassert_rst_flag_from_fatal = count_deassert_rst_flag_from_fatal == 31; + + initial begin + cptra_pwrgood = 1'b0; + BootFSM_BrkPoint = 1'b1; //Set to 1 even before anything starts + cptra_rst_b = 1'b0; + assert_rst_flag_from_fatal = 1'b0; + m_axi_bfm_if.rst_mgr(); + +`ifndef VERILATOR + if($test$plusargs("dumpon")) $dumpvars; +`endif + + if($test$plusargs("RAND_DOE_VALUES")) begin + //cptra_obf_key = cptra_obf_key_tb; + for (int dword = 0; dword < $bits(cptra_obf_key)/32; dword++) begin + `ifndef VERILATOR + wait(cptra_obf_key_tb[dword] !== 32'hXXXXXXXX); + `endif + cptra_obf_key[dword] = cptra_obf_key_tb[dword]; + end + + cptra_uds_tb = cptra_uds_rand; + cptra_fe_tb = cptra_fe_rand; + end + else begin + //Key for UDS + cptra_obf_key_uds = 256'h54682728db5035eb04b79645c64a95606abb6ba392b6633d79173c027c5acf77; + cptra_uds_tb = 384'he4046d05385ab789c6a72866e08350f93f583e2a005ca0faecc32b5cfc323d461c76c107307654db5566a5bd693e227c; + + //Key for FE + cptra_obf_key_fe = 256'h31358e8af34d6ac31c958bbd5c8fb33c334714bffb41700d28b07f11cfe891e7; + cptra_fe_tb = 256'hb32e2b171b63827034ebb0d1909f7ef1d51c5f82c1bb9bc26bc4ac4dccdee835; + /*256'h7dca6154c2510ae1c87b1b422b02b621bb06cac280023894fcff3406af08ee9b, + 256'he1dd72419beccddff77c722d992cdcc87e9c7486f56ab406ea608d8c6aeb060c, + 256'h64cf2785ad1a159147567e39e303370da445247526d95942bf4d7e88057178b0};*/ + + //swizzle the key so it matches the endianness of AES block + //used for visual inspection of uds/fe flow, manually switching keys and checking both + for (int dword = 0; dword < $bits(cptra_obf_key)/32; dword++) begin + //cptra_obf_key[dword] = cptra_obf_key_uds[dword]; + cptra_obf_key[dword] = cptra_obf_key_fe[dword]; + end + end + + // Run the test stimulus + + soc_ifc_hw_error_wdata = 'h0; + generic_input_wires = 'h0; + $display ("\n\n\n\n\n\n"); + repeat(15) @(posedge core_clk); + $display("CLP: Waiting for cptra_rst_b deassertion\n"); + + forever begin + fork + begin: BOOT_AND_CMD_FLOW + boot_and_cmd_flow = process::self(); + + // Repeat this flow after every warm reset + @(posedge cptra_rst_b) + $display("CLP: Observed cptra_rst_b deassertion\n"); + + if (!SKIP_BRINGUP) begin: DO_BOOT_AND_CMD_FLOW + + // Fuse download sequence + wait(ready_for_fuses == 1); + $display ("CLP: Ready for fuse download\n"); + + repeat(5) @(posedge core_clk); + + $display ("SoC: Writing obfuscated UDS to fuse bank\n"); + for (int dw=0; dw < `CLP_OBF_UDS_DWORDS; dw++) begin + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_FUSE_UDS_SEED_0 + 4 * dw), .data(cptra_uds_tb[dw]), .resp(wresp)); + end + + $display ("SoC: Writing obfuscated Field Entropy to fuse bank\n"); + for (int dw=0; dw < `CLP_OBF_FE_DWORDS; dw++) begin + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 + 4 * dw), .data(cptra_fe_tb[dw]), .resp(wresp)); + end + + $display ("SoC: Writing SOC Stepping ID to fuse bank\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID), .data($urandom()), .resp(wresp)); + + $display ("SoC: Writing fuse done register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE), .data(32'h00000001), .resp(wresp)); + + assert (!cptra_error_non_fatal) else begin + $error("cptra_error_non_fatal observed during boot up"); + $finish; + end + assert (!cptra_error_fatal) else begin + $error("cptra_error_fatal observed during boot up"); + $finish; + end + + if (BootFSM_BrkPoint) begin + $write ("SoC: Polling Flow Status..."); + poll_count = 0; + do begin + m_axi_bfm_if.axi_read_single(.addr(`CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS), .data(rdata), .resp(rresp)); + poll_count++; + end while(rdata[`SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW] == 1); + $display("\n >>> SoC: Ready for Fuses deasserted after polling %d times\n", poll_count); + $display ("SoC: Writing BootGo register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO), .data(32'h00000001), .resp(wresp)); + end + + $display ("CLP: ROM Flow in progress...\n"); + + // Test sequence (Mailbox or error handling) + wait(ready_for_fw_push || ras_test_ctrl.error_injection_seen); + + // Mailbox flow + if (ready_for_fw_push) begin + repeat(5) @(posedge core_clk); + + $display ("CLP: Ready for firmware push\n"); + $write ("SoC: Requesting mailbox lock..."); + poll_count = 0; + do begin + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_LOCK), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + poll_count++; + end while (rdata[`MBOX_CSR_MBOX_LOCK_LOCK_LOW] == 1); + $display ("\n >>> SoC: Lock granted after polling %d times\n", poll_count); + + $display ("SoC: Writing the Command Register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_CMD), .id(32'hFFFF_FFFF), .data(32'hBA5EBA11), .resp(wresp)); + + $display ("SoC: Writing the Data Length Register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(FW_NUM_DWORDS*4), .resp(wresp)); + + $display ("SoC: Writing the Firmware into Data-in Register\n"); + fw_blob = new[FW_NUM_DWORDS]; + wstrb_array = new[FW_NUM_DWORDS]('{default: {`CALIPTRA_AXI_DATA_WIDTH/8{1'b1}}}); + for (int dw=0; dw < FW_NUM_DWORDS; dw++) + fw_blob[dw] = $urandom(); + m_axi_bfm_if.axi_write(.addr(`CLP_MBOX_CSR_MBOX_DATAIN), + .burst(AXI_BURST_FIXED), + .len (FW_NUM_DWORDS-1), + .id (32'hFFFF_FFFF), + .data (fw_blob), + .strb (wstrb_array), + .resp (wresp)); + + $display ("SoC: Setting the Execute Register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_EXECUTE), .id(32'hFFFF_FFFF), .data(32'h00000001), .resp(wresp)); + + $display("SoC: Waiting for Response Data availability\n"); + wait(mailbox_data_avail); + + $display("SoC: Reading the Status Register...\n"); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_STATUS), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + + if (((rdata & `MBOX_CSR_MBOX_STATUS_STATUS_MASK) >> `MBOX_CSR_MBOX_STATUS_STATUS_LOW) == DATA_READY) begin: READ_RESP_DATA + $display("SoC: Reading the Data Length Register...\n"); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + + $display("SoC: Reading the Data Out Register\n"); + for (int xfer4k = 0; xfer4k < rdata; xfer4k += 4096) begin + byte_count = (rdata - xfer4k) > 4096 ? 4096 : (rdata - xfer4k); + dw_count = byte_count/(`CALIPTRA_AXI_DATA_WIDTH/8) + |byte_count[$clog2(`CALIPTRA_AXI_DATA_WIDTH/8)-1:0]; + rdata_array = new[dw_count]; + rresp_array = new[dw_count]; + m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), + .burst(AXI_BURST_FIXED), + .len(dw_count-1), + .id (32'hFFFF_FFFF), + .data(rdata_array), + .resp(rresp_array)); + end + end: READ_RESP_DATA + + $display("SoC: Resetting the Execute Register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_EXECUTE), .id(32'hFFFF_FFFF), .data(32'h0), .resp(wresp)); + + //Wait for Mailbox flow to be done before toggling generic_input_wires + @(negedge core_clk); + generic_input_wires = {$urandom, $urandom}; //Toggle wires + end + + if (ras_test_ctrl.error_injection_seen) begin + $display("SoC: Waiting to see cptra_error_fatal/non_fatal\n"); + rv_dma_resp_error = 1'b0; + end + + // Mailbox response flow and RAS functionality + forever begin + if (cptra_error_fatal_dly_p) begin + $display("SoC: Observed cptra_error_fatal; reading Caliptra register\n"); + m_axi_bfm_if.axi_read_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW]) begin + generic_input_wires = {32'h0, ICCM_FATAL_OBSERVED}; + end + else if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW]) begin + generic_input_wires = {32'h0, DCCM_FATAL_OBSERVED}; + end + else if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW]) begin + generic_input_wires = {32'h0, NMI_FATAL_OBSERVED}; + end + else if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW]) begin + generic_input_wires = {32'h0, CRYPTO_ERROR_OBSERVED}; + end + else begin + generic_input_wires = {32'h0, ERROR_NONE_SET}; + end + // HW ERROR registers are W1C, capture the set bits + soc_ifc_hw_error_wdata = rdata; + //wait for reset stuff + assert_rst_flag_from_fatal = 1; + wait(cptra_rst_b == 0); + end + else if (cptra_error_non_fatal_dly_p) begin + $display("SoC: Observed cptra_error_non_fatal; reading Caliptra register\n"); + m_axi_bfm_if.axi_read_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW]) begin + generic_input_wires = {32'h0, PROT_NO_LOCK_NON_FATAL_OBSERVED}; + end + else if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW]) begin + generic_input_wires = {32'h0, PROT_OOO_NON_FATAL_OBSERVED}; + end + else if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW]) begin + generic_input_wires = {32'h0, MBOX_NON_FATAL_OBSERVED}; + end + else begin + generic_input_wires = {32'h0, ERROR_NONE_SET}; + end + $display("SoC: Observed cptra_error_non_fatal; writing to clear Caliptra register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL), .id(32'hFFFF_FFFF), .data(rdata), .resp(wresp)); + end + else if (soc_ifc_hw_error_wdata) begin + $display("SoC: Observed cptra_error_fatal; writing to clear Caliptra register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL), .id(32'hFFFF_FFFF), .data(soc_ifc_hw_error_wdata), .resp(wresp)); + soc_ifc_hw_error_wdata = '0; + end + else if (ras_test_ctrl.do_no_lock_access) begin + fork + begin + $display("SoC: Reading the Data Out Register without lock\n"); + dw_count = 1; + rdata_array = new[dw_count]; + rresp_array = new[dw_count]; + m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), + .burst(AXI_BURST_FIXED), + .len(dw_count-1), + .id (32'hFFFF_FFFF), + .data(rdata_array), + .resp(rresp_array)); + end + join + end + else if (ras_test_ctrl.do_ooo_access) begin + fork + begin + $write ("SoC: Requesting mailbox lock..."); + poll_count = 0; + do begin + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_LOCK), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + poll_count++; + end while (rdata[`MBOX_CSR_MBOX_LOCK_LOCK_LOW] == 1); + $display ("\n >>> SoC: Lock granted after polling %d times\n", poll_count); + + $display("SoC: Reading the Data Length Register...\n"); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + + $display("SoC: Reading the Data Out Register\n"); + dw_count = 1; + rdata_array = new[dw_count]; + rresp_array = new[dw_count]; + m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), + .burst(AXI_BURST_FIXED), + .len(dw_count-1), + .id (32'hFFFF_FFFF), + .data(rdata_array), + .resp(rresp_array)); + end + join + end + else if (ras_test_ctrl.reset_generic_input_wires) begin + `ifdef VERILATOR + generic_input_wires = {32'h72746C76, ERROR_NONE_SET}; /* 32'h72746c76 is the big-endian ASCII representation of 'vltr' (r t l v) */ + `else + generic_input_wires = {32'h0, ERROR_NONE_SET}; + `endif + end + else if (rv_dma_resp_error) begin + generic_input_wires = {32'h0, DMA_ERROR_OBSERVED}; + rv_dma_resp_error = 1'b0; + end + else if (mailbox_data_avail) begin + $display("SoC: Reading the Data Length Register\n"); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + + $display("SoC: Reading the Data Out Register\n"); + for (int xfer4k = 0; xfer4k < rdata; xfer4k += 4096) begin + byte_count = (rdata - xfer4k) > 4096 ? 4096 : (rdata - xfer4k); + dw_count = byte_count/(`CALIPTRA_AXI_DATA_WIDTH/8) + |byte_count[$clog2(`CALIPTRA_AXI_DATA_WIDTH/8)-1:0]; + rdata_array = new[dw_count]; + rresp_array = new[dw_count]; + m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), + .burst(AXI_BURST_FIXED), + .len(dw_count-1), + .id (32'hFFFF_FFFF), + .data(rdata_array), + .resp(rresp_array)); + end + + $display ("SoC: Writing the Mbox Status Register\n"); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_STATUS), .id(32'hFFFF_FFFF), .data(32'h1), .resp(wresp)); + end + @(posedge core_clk); + end + end: DO_BOOT_AND_CMD_FLOW + else begin: SKIP_BOOT_AND_CMD_FLOW + forever @(posedge core_clk); + end: SKIP_BOOT_AND_CMD_FLOW + end: BOOT_AND_CMD_FLOW + begin: CLK_GATE_FLOW + wait(cycleCnt_smpl_en); + repeat(2000) @(negedge core_clk); + + if (int_flag) + $display("SoC (clk_gate_flow): Forcing soft_int = 1. cycleCnt [%d]\n", cycleCnt); + force caliptra_top_dut.soft_int = 1'b1; + repeat(2) @(negedge core_clk); + $display("SoC (clk_gate_flow): Releasing soft_int = 1. cycleCnt [%d]\n", cycleCnt); + release caliptra_top_dut.soft_int; + + repeat(5000) @(negedge core_clk); + + if (int_flag) + $display("SoC (clk_gate_flow): Forcing timer_int = 1. cycleCnt [%d]\n", cycleCnt); + force caliptra_top_dut.timer_int = 1'b1; + repeat(2) @(negedge core_clk); + $display("SoC (clk_gate_flow): Releasing timer_int = 1. cycleCnt [%d]\n", cycleCnt); + release caliptra_top_dut.timer_int; + + repeat(8000) @(negedge core_clk); + + if (int_flag) + $display("SoC (clk_gate_flow): Forcing soft_int = 1. cycleCnt [%d]\n", cycleCnt); + force caliptra_top_dut.soft_int = 1'b1; + repeat(2) @(negedge core_clk); + $display("SoC (clk_gate_flow): Releasing soft_int = 1. cycleCnt [%d]\n", cycleCnt); + release caliptra_top_dut.soft_int; + + wait(cptra_rst_b == 0); + end: CLK_GATE_FLOW + begin: RESET_FLOW + @(negedge cptra_rst_b); + $display("CLP: Observed cptra_rst_b assertion\n"); +// disable BOOT_AND_CMD_FLOW; + if (boot_and_cmd_flow != null) boot_and_cmd_flow.kill(); + assert_rst_flag_from_fatal = 1'b0; + m_axi_bfm_if.rst_mgr(); + end: RESET_FLOW + join_any + end + end + + assign assert_rst_flag = assert_rst_flag_from_service || assert_rst_flag_from_fatal; + assign deassert_rst_flag = deassert_rst_flag_from_service || deassert_rst_flag_from_fatal; + always @(posedge core_clk) begin + //Reset/pwrgood assertion during runtime + if (cycleCnt == 15 || deassert_hard_rst_flag) begin + $display ("SoC: Asserting cptra_pwrgood and breakpoint. cycleCnt [%d] deassert_hard_rst_flag[%d]\n", cycleCnt, deassert_hard_rst_flag); + //assert power good + cptra_pwrgood <= 1'b1; + end + else if (cycleCnt == 20 || deassert_rst_flag) begin + $display ("SoC: De-Asserting cptra_rst_b. cycleCnt [%d] deassert_rst_flag[%d]\n", cycleCnt, deassert_rst_flag); + //de-assert reset + cptra_rst_b <= 1'b1; + end + else if (assert_hard_rst_flag) begin + cptra_pwrgood <= 'b0; + cptra_rst_b <= 'b0; + end + else if (assert_rst_flag) begin + cptra_rst_b <= 'b0; + end + end + +`define RV_INST caliptra_top_dut.rvtop +`define RV_IDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_IDMA] +`define RV_DDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_DDMA] +task force_ahb_dma_read(input logic [31:0] address); + while(`RV_INST.dma_hsel) @(posedge core_clk); + force `RV_IDMA_RESP_INST.hreadyout = 1'b0; + force `RV_DDMA_RESP_INST.hreadyout = 1'b0; + + force `RV_INST.dma_haddr = address; + force `RV_INST.dma_hsize = 3'b010; // 4-bytes + force `RV_INST.dma_hwrite = 1'b0; + force `RV_INST.dma_hwdata = '0; + force `RV_INST.dma_hreadyin = 1'b1; + force `RV_INST.dma_hsel = 1'b1; + force `RV_INST.dma_htrans = 2'b10; + + // Wait for command to be accepted + do @(posedge core_clk); while(!`RV_INST.dma_hreadyout); + force `RV_INST.dma_htrans = 2'b00; + // Wait for response to be provided + do @(posedge core_clk); while(!`RV_INST.dma_hreadyout); + $display("[%t] AHB DMA FORCE READ: Address 0x%x Data 0x%x Resp 0x%x", $time, address, `RV_INST.dma_hrdata, `RV_INST.dma_hresp); + if (`RV_INST.dma_hresp) + rv_dma_resp_error = 1'b1; + release `RV_IDMA_RESP_INST.hreadyout; + release `RV_DDMA_RESP_INST.hreadyout; + + release `RV_INST.dma_htrans; + release `RV_INST.dma_haddr; + release `RV_INST.dma_hsize; + release `RV_INST.dma_hwrite; + release `RV_INST.dma_hwdata; + release `RV_INST.dma_hsel; + release `RV_INST.dma_hreadyin; +endtask + +task force_ahb_dma_loop_read(input logic [31:0] start_addr, input logic [19:0] count); + automatic logic [31:0] addr; + addr = start_addr; + $display("[%t] AHB DMA FORCE LOOP READ: Start Address 0x%x Count 0x%x", $time, addr, count); + if ($isunknown(start_addr) || $isunknown(addr)) + $error("[%t] Unknown signal found: start_addr 0x%x addr 0x%x", $time, start_addr, addr); + repeat(count) begin + force_ahb_dma_read(addr); + addr += 4; + end +endtask + +initial begin + forever @(posedge core_clk) begin + if (ras_test_ctrl.dccm_read_burst.start) + force_ahb_dma_loop_read(ras_test_ctrl.dccm_read_burst.addr, ras_test_ctrl.dccm_read_burst.count); + if (ras_test_ctrl.iccm_read_burst.start) + force_ahb_dma_loop_read(ras_test_ctrl.iccm_read_burst.addr, ras_test_ctrl.iccm_read_burst.count); + end +end + +endmodule diff --git a/src/integration/tb/test_caliptra_top_tb.cpp b/src/integration/tb/test_caliptra_top_tb.cpp index 05b7f47db..3665ae00e 100644 --- a/src/integration/tb/test_caliptra_top_tb.cpp +++ b/src/integration/tb/test_caliptra_top_tb.cpp @@ -57,8 +57,9 @@ int main(int argc, char** argv) { #if VM_TRACE tfp->dump (main_time); #endif - main_time += 5; - tb->core_clk = !tb->core_clk; + main_time += 1; + // Toggle every 5ns (timescale precision is 100ps) + if (main_time % 50 == 0) tb->core_clk = !tb->core_clk; tb->eval(); } diff --git a/src/integration/test_suites/c_intr_handler/caliptra_isr.h b/src/integration/test_suites/c_intr_handler/caliptra_isr.h index 517e72b37..a2c87bcce 100644 --- a/src/integration/test_suites/c_intr_handler/caliptra_isr.h +++ b/src/integration/test_suites/c_intr_handler/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -222,5 +224,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/caliptra_fmc/caliptra_isr.h b/src/integration/test_suites/caliptra_fmc/caliptra_isr.h index 542d6572b..2700ad250 100644 --- a/src/integration/test_suites/caliptra_fmc/caliptra_isr.h +++ b/src/integration/test_suites/caliptra_fmc/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -251,5 +253,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/caliptra_rt/caliptra_isr.h b/src/integration/test_suites/caliptra_rt/caliptra_isr.h index 1f7d023bc..a0495a7f1 100644 --- a/src/integration/test_suites/caliptra_rt/caliptra_isr.h +++ b/src/integration/test_suites/caliptra_rt/caliptra_isr.h @@ -54,6 +54,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -247,5 +249,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/caliptra_top/caliptra_isr.h b/src/integration/test_suites/caliptra_top/caliptra_isr.h index 3fd30343d..075a3d421 100644 --- a/src/integration/test_suites/caliptra_top/caliptra_isr.h +++ b/src/integration/test_suites/caliptra_top/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -231,5 +233,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/hello_world_iccm/caliptra_isr.h b/src/integration/test_suites/hello_world_iccm/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/hello_world_iccm/caliptra_isr.h +++ b/src/integration/test_suites/hello_world_iccm/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/iccm_lock/caliptra_isr.h b/src/integration/test_suites/iccm_lock/caliptra_isr.h index 0bdef173f..07a5b39e8 100644 --- a/src/integration/test_suites/iccm_lock/caliptra_isr.h +++ b/src/integration/test_suites/iccm_lock/caliptra_isr.h @@ -54,6 +54,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -241,5 +243,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/iccm_lock/iccm_lock.c b/src/integration/test_suites/iccm_lock/iccm_lock.c index f56c9b953..f0dbe69e6 100644 --- a/src/integration/test_suites/iccm_lock/iccm_lock.c +++ b/src/integration/test_suites/iccm_lock/iccm_lock.c @@ -57,6 +57,8 @@ volatile caliptra_intr_received_s cptra_intr_rcv = { .soc_ifc_notif = 0, .sha512_acc_error = 0, .sha512_acc_notif = 0, + .axi_dma_notif = 0, + .axi_dma_notif = 0, }; extern uintptr_t iccm_code0_start, iccm_code0_end; diff --git a/src/integration/test_suites/includes/caliptra_defines.h b/src/integration/test_suites/includes/caliptra_defines.h index b44a71ce5..a81dce1b3 100644 --- a/src/integration/test_suites/includes/caliptra_defines.h +++ b/src/integration/test_suites/includes/caliptra_defines.h @@ -85,6 +85,10 @@ #define STATUS_READY_BIT 0x0 #define STATUS_VALID_BIT 0x1 +/* ---- AXI SRAM ---- */ +#define AXI_SRAM_BASE_ADDR (uint64_t) 0x000123450000ULL +#define AXI_SRAM_SIZE_BYTES 65536 + /* ---- Interrupts ---- */ #define VEER_INTR_VEC_DOE_ERROR 1 #define VEER_INTR_VEC_DOE_NOTIF 2 @@ -108,8 +112,10 @@ #define VEER_INTR_VEC_SOC_IFC_NOTIF 20 #define VEER_INTR_VEC_SHA512_ACC_ERROR 21 #define VEER_INTR_VEC_SHA512_ACC_NOTIF 22 +#define VEER_INTR_VEC_AXI_DMA_ERROR 23 +#define VEER_INTR_VEC_AXI_DMA_NOTIF 24 // Used to tie-off unused upper intr bits -#define VEER_INTR_VEC_MAX_ASSIGNED VEER_INTR_VEC_SHA512_ACC_NOTIF +#define VEER_INTR_VEC_MAX_ASSIGNED VEER_INTR_VEC_AXI_DMA_NOTIF #define VEER_INTR_PRIO_DOE_ERROR 8 #define VEER_INTR_PRIO_DOE_NOTIF 7 @@ -133,6 +139,8 @@ #define VEER_INTR_PRIO_I3C_NOTIF 3 #define VEER_INTR_PRIO_SOC_IFC_ERROR 8 #define VEER_INTR_PRIO_SOC_IFC_NOTIF 7 +#define VEER_INTR_PRIO_AXI_DMA_ERROR 8 +#define VEER_INTR_PRIO_AXI_DMA_NOTIF 7 #endif // CALIPTRA_DEFINES_H diff --git a/src/integration/test_suites/infinite_loop/caliptra_isr.h b/src/integration/test_suites/infinite_loop/caliptra_isr.h index 7bd443326..9ff1022ab 100644 --- a/src/integration/test_suites/infinite_loop/caliptra_isr.h +++ b/src/integration/test_suites/infinite_loop/caliptra_isr.h @@ -49,6 +49,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; ////////////////////////////////////////////////////////////////////////////// @@ -87,4 +89,8 @@ inline void service_soc_ifc_notif_intr () {return;} inline void service_sha512_acc_error_intr() {return;} inline void service_sha512_acc_notif_intr() {return;} +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c b/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c index 459b00eea..11acd94e3 100644 --- a/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c +++ b/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c @@ -76,6 +76,8 @@ static void nonstd_veer_isr_soc_ifc_error (void) __attribute__ ((interrupt ("mac static void nonstd_veer_isr_soc_ifc_notif (void) __attribute__ ((interrupt ("machine"))); static void nonstd_veer_isr_sha512_acc_error (void) __attribute__ ((interrupt ("machine"))); static void nonstd_veer_isr_sha512_acc_notif (void) __attribute__ ((interrupt ("machine"))); +static void nonstd_veer_isr_axi_dma_error (void) __attribute__ ((interrupt ("machine"))); +static void nonstd_veer_isr_axi_dma_notif (void) __attribute__ ((interrupt ("machine"))); // Could be much more fancy with C preprocessing to pair up the ISR with Vector // numbers as defined in caliptra_defines.h.... TODO @@ -101,13 +103,13 @@ static void (* const nonstd_veer_isr_18) (void) = std_rv_nop_machine ; static void (* const nonstd_veer_isr_19) (void) = nonstd_veer_isr_soc_ifc_error; // | static void (* const nonstd_veer_isr_20) (void) = nonstd_veer_isr_soc_ifc_notif; // | static void (* const nonstd_veer_isr_21) (void) = nonstd_veer_isr_sha512_acc_error;// | -static void (* const nonstd_veer_isr_22) (void) = nonstd_veer_isr_sha512_acc_notif;// -------' -static void (* const nonstd_veer_isr_23) (void) = std_rv_nop_machine; // --------| -static void (* const nonstd_veer_isr_24) (void) = std_rv_nop_machine; // | -static void (* const nonstd_veer_isr_25) (void) = std_rv_nop_machine; // | -static void (* const nonstd_veer_isr_26) (void) = std_rv_nop_machine; // Unimplemented ISR +static void (* const nonstd_veer_isr_22) (void) = nonstd_veer_isr_sha512_acc_notif;// | +static void (* const nonstd_veer_isr_23) (void) = nonstd_veer_isr_axi_dma_error; // | +static void (* const nonstd_veer_isr_24) (void) = nonstd_veer_isr_axi_dma_notif; // -------' +static void (* const nonstd_veer_isr_25) (void) = std_rv_nop_machine; // --------| +static void (* const nonstd_veer_isr_26) (void) = std_rv_nop_machine; // | static void (* const nonstd_veer_isr_27) (void) = std_rv_nop_machine; // | -static void (* const nonstd_veer_isr_28) (void) = std_rv_nop_machine; // | +static void (* const nonstd_veer_isr_28) (void) = std_rv_nop_machine; // Unimplemented ISR static void (* const nonstd_veer_isr_29) (void) = std_rv_nop_machine; // | static void (* const nonstd_veer_isr_30) (void) = std_rv_nop_machine; // | static void (* const nonstd_veer_isr_31) (void) = std_rv_nop_machine; // --------' @@ -177,6 +179,7 @@ void init_interrupts(void) { volatile uint32_t * const sha512_reg = (uint32_t*) CLP_SHA512_REG_BASE_ADDR; volatile uint32_t * const sha256_reg = (uint32_t*) CLP_SHA256_REG_BASE_ADDR; volatile uint32_t * const sha512_acc_csr = (uint32_t*) CLP_SHA512_ACC_CSR_BASE_ADDR; + volatile uint32_t * const axi_dma_reg = (uint32_t*) CLP_AXI_DMA_REG_BASE_ADDR; volatile uint32_t * const mtime_l = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L; volatile uint32_t * const mtime_h = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H; volatile uint32_t * const mtimecmp_l = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L; @@ -240,6 +243,8 @@ void init_interrupts(void) { meipls[VEER_INTR_VEC_SOC_IFC_NOTIF ] = VEER_INTR_PRIO_SOC_IFC_NOTIF ; __asm__ volatile ("fence"); meipls[VEER_INTR_VEC_SHA512_ACC_ERROR] = VEER_INTR_PRIO_SHA512_ACC_ERROR; __asm__ volatile ("fence"); meipls[VEER_INTR_VEC_SHA512_ACC_NOTIF] = VEER_INTR_PRIO_SHA512_ACC_NOTIF; __asm__ volatile ("fence"); + meipls[VEER_INTR_VEC_AXI_DMA_ERROR ] = VEER_INTR_PRIO_AXI_DMA_ERROR ; __asm__ volatile ("fence"); + meipls[VEER_INTR_VEC_AXI_DMA_NOTIF ] = VEER_INTR_PRIO_AXI_DMA_NOTIF ; __asm__ volatile ("fence"); for (uint8_t undef = VEER_INTR_VEC_MAX_ASSIGNED+1; undef <= RV_PIC_TOTAL_INT; undef++) { meipls[undef] = 0; __asm__ volatile ("fence"); // Set to 0 meaning NEVER interrupt } @@ -336,6 +341,23 @@ void init_interrupts(void) { sha512_acc_csr[SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R/sizeof(uint32_t)] = SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK | SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK; + // AXI DMA + // TODO + axi_dma_reg[AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R /sizeof(uint32_t)] = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK; + axi_dma_reg[AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R /sizeof(uint32_t)] = AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK; + axi_dma_reg[AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R/sizeof(uint32_t)] = AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK; + // Set mtimecmp to max value to avoid spurious timer interrupts *mtimecmp_l = 0xFFFFFFFF; *mtimecmp_h = 0xFFFFFFFF; @@ -704,6 +726,8 @@ static void nonstd_veer_isr_0 (void) { * service_soc_ifc_notif_intr \ * service_sha512_acc_error_intr \ * service_sha512_acc_notif_intr \ + * service_axi_dma_error_intr \ + * service_axi_dma_notif_intr \ */ \ service_##name##_intr(); \ \ @@ -774,4 +798,8 @@ nonstd_veer_isr(soc_ifc_notif) nonstd_veer_isr(sha512_acc_error) // Non-Standard Vectored Interrupt Handler (SHA Notification = vector 22) nonstd_veer_isr(sha512_acc_notif) +// Non-Standard Vectored Interrupt Handler (AXI DMA Error = vector 23) +nonstd_veer_isr(axi_dma_error) +// Non-Standard Vectored Interrupt Handler (AXI DMA Notification = vector 24) +nonstd_veer_isr(axi_dma_notif) diff --git a/src/integration/test_suites/libs/clk_gate/clk_gate.c b/src/integration/test_suites/libs/clk_gate/clk_gate.c index ad724e6e6..b28cbd489 100644 --- a/src/integration/test_suites/libs/clk_gate/clk_gate.c +++ b/src/integration/test_suites/libs/clk_gate/clk_gate.c @@ -19,7 +19,7 @@ #include "printf.h" void set_mit0_and_halt_core(uint32_t mitb0, uint32_t mie_en) { - VPRINTF(LOW, "Enabling internal timer0 and halting core\n"); + VPRINTF(LOW, "En int tmr0, hlt core\n"); //Enable internal timer0 __asm__ volatile ("csrwi %0, %1" \ : /* output: none */ \ @@ -96,4 +96,4 @@ void halt_core() { : /* output: none */ \ : "i" (0x7c6), "i" (0x03) /* input : immediate */ \ : /* clobbers: none */); -} \ No newline at end of file +} diff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c index 38a59154e..b5e7726a9 100644 --- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c +++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c @@ -306,3 +306,214 @@ void soc_ifc_sha_accel_clr_lock() { //Write one to clear lsu_write_32((CLP_SHA512_ACC_CSR_LOCK), SHA512_ACC_CSR_LOCK_LOCK_MASK); } + +// AXI DMA Functions +uint8_t soc_ifc_axi_dma_send_ahb_payload(uint64_t dst_addr, uint8_t fixed, uint32_t * payload, uint32_t byte_count, uint16_t block_size) { + uint32_t reg; + uint16_t mdepth; + + // Arm the command + while (lsu_read_32(CLP_AXI_DMA_REG_STATUS0) & AXI_DMA_REG_STATUS0_BUSY_MASK); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_L, dst_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_H, (dst_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_BYTE_COUNT, byte_count); + lsu_write_32(CLP_AXI_DMA_REG_BLOCK_SIZE, (uint32_t) block_size); + reg = AXI_DMA_REG_CTRL_GO_MASK | + (axi_dma_rd_route_DISABLE << AXI_DMA_REG_CTRL_RD_ROUTE_LOW) | + (axi_dma_wr_route_AHB_FIFO << AXI_DMA_REG_CTRL_WR_ROUTE_LOW) | + (fixed ? AXI_DMA_REG_CTRL_WR_FIXED_MASK : 0); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, reg); + + // Send data + mdepth = (lsu_read_32(CLP_AXI_DMA_REG_CAP) & AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK) >> AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW; + for (uint32_t dw_sent = 0; dw_sent < (byte_count>>2); dw_sent++) { + // Wait for there to be available space in the FIFO + while(((lsu_read_32(CLP_AXI_DMA_REG_STATUS0) & AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK) >> AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW) == mdepth); + lsu_write_32(CLP_AXI_DMA_REG_WRITE_DATA, payload[dw_sent]); + } + + // Check completion + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + while ((reg & AXI_DMA_REG_STATUS0_BUSY_MASK) && !(reg & AXI_DMA_REG_STATUS0_ERROR_MASK)) { + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + } + + if (reg & AXI_DMA_REG_STATUS0_ERROR_MASK) { + VPRINTF(FATAL, "FATAL: AXI DMA reports error status for FIFO-to-AXI xfer\n"); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, AXI_DMA_REG_CTRL_FLUSH_MASK); + SEND_STDOUT_CTRL(0x1); + } +} + +uint8_t soc_ifc_axi_dma_read_ahb_payload(uint64_t src_addr, uint8_t fixed, uint32_t * payload, uint32_t byte_count, uint16_t block_size) { + uint32_t reg; + uint16_t mdepth; + + // Arm the command + while (lsu_read_32(CLP_AXI_DMA_REG_STATUS0) & AXI_DMA_REG_STATUS0_BUSY_MASK); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_L, src_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_H, (src_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_BYTE_COUNT, byte_count); + lsu_write_32(CLP_AXI_DMA_REG_BLOCK_SIZE, (uint32_t) block_size); + reg = (AXI_DMA_REG_CTRL_GO_MASK) | + (axi_dma_rd_route_AHB_FIFO << AXI_DMA_REG_CTRL_RD_ROUTE_LOW) | + (axi_dma_wr_route_DISABLE << AXI_DMA_REG_CTRL_WR_ROUTE_LOW) | + (fixed ? AXI_DMA_REG_CTRL_RD_FIXED_MASK : 0); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, reg); + + // Read data + mdepth = (lsu_read_32(CLP_AXI_DMA_REG_CAP) & AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK) >> AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW; + for (uint32_t dw_rcv = 0; dw_rcv < (byte_count>>2); dw_rcv++) { + // Wait for there to be available data in the FIFO + while(((lsu_read_32(CLP_AXI_DMA_REG_STATUS0) & AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK) >> AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW) == 0); + payload[dw_rcv] = lsu_read_32(CLP_AXI_DMA_REG_READ_DATA); + } + + // Check completion + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + while ((reg & AXI_DMA_REG_STATUS0_BUSY_MASK) && !(reg & AXI_DMA_REG_STATUS0_ERROR_MASK)) { + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + } + + if (reg & AXI_DMA_REG_STATUS0_ERROR_MASK) { + VPRINTF(FATAL, "FATAL: AXI DMA reports error status for AXI-to-FIFO xfer\n"); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, AXI_DMA_REG_CTRL_FLUSH_MASK); + SEND_STDOUT_CTRL(0x1); + } +} + +uint8_t soc_ifc_axi_dma_send_mbox_payload(uint64_t src_addr, uint64_t dst_addr, uint8_t fixed, uint32_t byte_count, uint16_t block_size) { + uint32_t reg; + + // Acquire the mailbox lock + if (soc_ifc_mbox_acquire_lock(1)) { + VPRINTF(ERROR, "Acquire mailbox lock failed\n"); + return 1; + } + + // src_addr checks + if (src_addr & ~((uint64_t) (MBOX_DIR_SPAN-1))) { + VPRINTF(ERROR, "src_addr 0x%x is out of bounds for mbox span!\n", src_addr); + SEND_STDOUT_CTRL(0x1); + while(1); + } + if ((src_addr + byte_count) & ~((uint64_t) (MBOX_DIR_SPAN-1))) { + VPRINTF(ERROR, "reading 0x%x bytes from src_addr 0x%x goes out of bounds for mbox span!\n", src_addr, byte_count); + SEND_STDOUT_CTRL(0x1); + while(1); + } + + // Arm the command + while (lsu_read_32(CLP_AXI_DMA_REG_STATUS0) & AXI_DMA_REG_STATUS0_BUSY_MASK); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_L, src_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_H, (src_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_L, dst_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_H, (dst_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_BYTE_COUNT, byte_count); + lsu_write_32(CLP_AXI_DMA_REG_BLOCK_SIZE, (uint32_t) block_size); + reg = (AXI_DMA_REG_CTRL_GO_MASK) | + (axi_dma_rd_route_DISABLE << AXI_DMA_REG_CTRL_RD_ROUTE_LOW) | + (axi_dma_wr_route_MBOX << AXI_DMA_REG_CTRL_WR_ROUTE_LOW) | + (fixed ? AXI_DMA_REG_CTRL_WR_FIXED_MASK : 0); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, reg); + + // Check completion + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + while ((reg & AXI_DMA_REG_STATUS0_BUSY_MASK) && !(reg & AXI_DMA_REG_STATUS0_ERROR_MASK)) { + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + } + + // Check status + if (reg & AXI_DMA_REG_STATUS0_ERROR_MASK) { + VPRINTF(FATAL, "FATAL: AXI DMA reports error status for MBOX-to-AXI xfer\n"); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, AXI_DMA_REG_CTRL_FLUSH_MASK); + SEND_STDOUT_CTRL(0x1); + } + + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); + return 0; +} + +uint8_t soc_ifc_axi_dma_read_mbox_payload(uint64_t src_addr, uint64_t dst_addr, uint8_t fixed, uint32_t byte_count, uint16_t block_size) { + uint32_t reg; + + // Acquire the mailbox lock + if (soc_ifc_mbox_acquire_lock(1)) { + VPRINTF(ERROR, "Acquire mailbox lock failed\n"); + return 1; + } + + // dst_addr checks + if (dst_addr & ~((uint64_t) (MBOX_DIR_SPAN-1))) { + VPRINTF(ERROR, "dst_addr 0x%x is out of bounds for mbox span!\n", dst_addr); + SEND_STDOUT_CTRL(0x1); + while(1); + } + if ((dst_addr + byte_count) & ~((uint64_t) (MBOX_DIR_SPAN-1))) { + VPRINTF(ERROR, "writing 0x%x bytes to dst_addr 0x%x goes out of bounds for mbox span!\n", dst_addr, byte_count); + SEND_STDOUT_CTRL(0x1); + while(1); + } + + // Arm the command + while (lsu_read_32(CLP_AXI_DMA_REG_STATUS0) & AXI_DMA_REG_STATUS0_BUSY_MASK); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_L, src_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_H, (src_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_L, dst_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_H, (dst_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_BYTE_COUNT, byte_count); + lsu_write_32(CLP_AXI_DMA_REG_BLOCK_SIZE, (uint32_t) block_size); + reg = (AXI_DMA_REG_CTRL_GO_MASK) | + (axi_dma_rd_route_MBOX << AXI_DMA_REG_CTRL_RD_ROUTE_LOW) | + (axi_dma_wr_route_DISABLE << AXI_DMA_REG_CTRL_WR_ROUTE_LOW) | + (fixed ? AXI_DMA_REG_CTRL_RD_FIXED_MASK : 0); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, reg); + + // Check completion + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + while ((reg & AXI_DMA_REG_STATUS0_BUSY_MASK) && !(reg & AXI_DMA_REG_STATUS0_ERROR_MASK)) { + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + } + + // Check status + if (reg & AXI_DMA_REG_STATUS0_ERROR_MASK) { + VPRINTF(FATAL, "FATAL: AXI DMA reports error status for AXI-to-MBOX xfer\n"); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, AXI_DMA_REG_CTRL_FLUSH_MASK); + SEND_STDOUT_CTRL(0x1); + } + + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); + return 0; +} + +uint8_t soc_ifc_axi_dma_send_axi_to_axi(uint64_t src_addr, uint8_t src_fixed, uint64_t dst_addr, uint8_t dst_fixed, uint32_t byte_count, uint16_t block_size) { + uint32_t reg; + + // Arm the command + while (lsu_read_32(CLP_AXI_DMA_REG_STATUS0) & AXI_DMA_REG_STATUS0_BUSY_MASK); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_L, src_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_SRC_ADDR_H, (src_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_L, dst_addr & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_DST_ADDR_H, (dst_addr >> 32) & 0xffffffff); + lsu_write_32(CLP_AXI_DMA_REG_BYTE_COUNT, byte_count); + lsu_write_32(CLP_AXI_DMA_REG_BLOCK_SIZE, (uint32_t) block_size); + reg = (AXI_DMA_REG_CTRL_GO_MASK) | + (axi_dma_rd_route_AXI_WR << AXI_DMA_REG_CTRL_RD_ROUTE_LOW) | + (axi_dma_wr_route_AXI_RD << AXI_DMA_REG_CTRL_WR_ROUTE_LOW) | + (src_fixed ? AXI_DMA_REG_CTRL_RD_FIXED_MASK : 0) | + (dst_fixed ? AXI_DMA_REG_CTRL_WR_FIXED_MASK : 0); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, reg); + + // Check completion + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + while ((reg & AXI_DMA_REG_STATUS0_BUSY_MASK) && !(reg & AXI_DMA_REG_STATUS0_ERROR_MASK)) { + reg = lsu_read_32(CLP_AXI_DMA_REG_STATUS0); + } + + // Report any errors + if (reg & AXI_DMA_REG_STATUS0_ERROR_MASK) { + VPRINTF(FATAL, "FATAL: AXI DMA reports error status for AXI-to-AXI xfer\n"); + lsu_write_32(CLP_AXI_DMA_REG_CTRL, AXI_DMA_REG_CTRL_FLUSH_MASK); + SEND_STDOUT_CTRL(0x1); + } +} diff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h index 84f6ad365..6b50770d6 100644 --- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h +++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h @@ -22,6 +22,13 @@ #include "riscv_hw_if.h" /* --------------- symbols/typedefs --------------- */ +enum boot_fsm_state_e { + BOOT_IDLE = 0x0, + BOOT_FUSE = 0x1, + BOOT_FW_RST = 0x2, + BOOT_WAIT = 0x3, + BOOT_DONE = 0x4 +}; enum mbox_status_e { CMD_BUSY = 0, DATA_READY = 1, @@ -38,6 +45,27 @@ enum mbox_fsm_e { MBOX_ERROR = 0x7 }; +enum axi_dma_rd_route_e { + axi_dma_rd_route_DISABLE = 0x0, + axi_dma_rd_route_MBOX = 0x1, + axi_dma_rd_route_AHB_FIFO = 0x2, + axi_dma_rd_route_AXI_WR = 0x3 +}; + +enum axi_dma_wr_route_e { + axi_dma_wr_route_DISABLE = 0x0, + axi_dma_wr_route_MBOX = 0x1, + axi_dma_wr_route_AHB_FIFO = 0x2, + axi_dma_wr_route_AXI_RD = 0x3 +}; + +enum axi_dma_fsm_e { + axi_dma_fsm_DMA_IDLE = 0x0, + axi_dma_fsm_DMA_WAIT_DATA = 0x1, + axi_dma_fsm_DMA_DONE = 0x2, + axi_dma_fsm_DMA_ERROR = 0x3 +}; + /** * Decode: * [31]: Firmware command @@ -128,4 +156,11 @@ void soc_ifc_sha_accel_poll_status(); void soc_ifc_sha_accel_clr_lock(); void soc_ifc_w1clr_sha_lock_field(); +// AXI DMA Functions +uint8_t soc_ifc_axi_dma_send_ahb_payload(uint64_t dst_addr, uint8_t fixed, uint32_t * payload, uint32_t byte_count, uint16_t block_size); +uint8_t soc_ifc_axi_dma_read_ahb_payload(uint64_t src_addr, uint8_t fixed, uint32_t * payload, uint32_t byte_count, uint16_t block_size); +uint8_t soc_ifc_axi_dma_send_mbox_payload(uint64_t src_addr, uint64_t dst_addr, uint8_t fixed, uint32_t byte_count, uint16_t block_size); +uint8_t soc_ifc_axi_dma_read_mbox_payload(uint64_t src_addr, uint64_t dst_addr, uint8_t fixed, uint32_t byte_count, uint16_t block_size); +uint8_t soc_ifc_axi_dma_send_axi_to_axi(uint64_t src_addr, uint8_t src_fixed, uint64_t dst_addr, uint8_t dst_fixed, uint32_t byte_count, uint16_t block_size); + #endif diff --git a/src/integration/test_suites/memCpy_ROM_to_dccm/caliptra_isr.h b/src/integration/test_suites/memCpy_ROM_to_dccm/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/memCpy_ROM_to_dccm/caliptra_isr.h +++ b/src/integration/test_suites/memCpy_ROM_to_dccm/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/memCpy_dccm_to_iccm/caliptra_isr.h b/src/integration/test_suites/memCpy_dccm_to_iccm/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/memCpy_dccm_to_iccm/caliptra_isr.h +++ b/src/integration/test_suites/memCpy_dccm_to_iccm/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h b/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h +++ b/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/pv_hash_reset/caliptra_isr.h b/src/integration/test_suites/pv_hash_reset/caliptra_isr.h index 23b511c4b..54fd4f09a 100644 --- a/src/integration/test_suites/pv_hash_reset/caliptra_isr.h +++ b/src/integration/test_suites/pv_hash_reset/caliptra_isr.h @@ -65,6 +65,8 @@ inline void service_soc_ifc_error_intr () {printf("ERROR");} inline void service_soc_ifc_notif_intr () {printf("ERROR");} inline void service_sha512_acc_error_intr() {printf("ERROR");} inline void service_sha512_acc_notif_intr() {printf("ERROR");} +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h b/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h +++ b/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_ahb_mux/caliptra_isr.h b/src/integration/test_suites/smoke_test_ahb_mux/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_ahb_mux/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_ahb_mux/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_cg_wdt/caliptra_isr.h b/src/integration/test_suites/smoke_test_cg_wdt/caliptra_isr.h index 1663774c7..18223fe3a 100644 --- a/src/integration/test_suites/smoke_test_cg_wdt/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_cg_wdt/caliptra_isr.h @@ -58,6 +58,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -128,5 +130,8 @@ inline void service_soc_ifc_notif_intr () { inline void service_sha512_acc_error_intr() {printf("ERROR");} inline void service_sha512_acc_notif_intr() {printf("ERROR");} +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_clk_gating/caliptra_isr.h b/src/integration/test_suites/smoke_test_clk_gating/caliptra_isr.h index 1234bb450..376894794 100644 --- a/src/integration/test_suites/smoke_test_clk_gating/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_clk_gating/caliptra_isr.h @@ -58,6 +58,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -145,5 +147,8 @@ inline void service_soc_ifc_notif_intr () { inline void service_sha512_acc_error_intr() {printf("ERROR");} inline void service_sha512_acc_notif_intr() {printf("ERROR");} +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c index 438371b04..ac2fefe26 100644 --- a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c +++ b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c @@ -137,9 +137,9 @@ void main() { : /* clobbers: none */); //------------------------------------------------------ - //Wake SOC up for APB tx and core using timer int later + //Wake SOC up for AXI tx and core using timer int later //------------------------------------------------------ - printf("Wake up SOC clk on APB txns and later wake up core using timer interrupt\n"); + printf("Wake up SOC clk on AXI txns and later wake up core using timer interrupt\n"); //Machine intr enable reg (mie) - enable timer int __asm__ volatile ("csrw %0, %1" \ : /* output: none */ \ diff --git a/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_dma/caliptra_isr.h b/src/integration/test_suites/smoke_test_dma/caliptra_isr.h new file mode 100644 index 000000000..eeca30e9b --- /dev/null +++ b/src/integration/test_suites/smoke_test_dma/caliptra_isr.h @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// --------------------------------------------------------------------- +// File: caliptra_isr.h +// Description: +// Provides function declarations for use by external test files, so +// that the ISR functionality may behave like a library. +// TODO: +// This header file includes inline function definitions for event and +// test specific interrupt service behavior, so it should be copied and +// modified for each test. +// --------------------------------------------------------------------- + +#ifndef CALIPTRA_ISR_H + #define CALIPTRA_ISR_H + +#include "caliptra_defines.h" +#include +#include "printf.h" + +/* --------------- symbols/typedefs --------------- */ +typedef struct { + uint32_t doe_error; + uint32_t doe_notif; + uint32_t ecc_error; + uint32_t ecc_notif; + uint32_t hmac_error; + uint32_t hmac_notif; + uint32_t kv_error; + uint32_t kv_notif; + uint32_t sha512_error; + uint32_t sha512_notif; + uint32_t sha256_error; + uint32_t sha256_notif; + uint32_t qspi_error; + uint32_t qspi_notif; + uint32_t uart_error; + uint32_t uart_notif; + uint32_t i3c_error; + uint32_t i3c_notif; + uint32_t soc_ifc_error; + uint32_t soc_ifc_notif; + uint32_t sha512_acc_error; + uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; +} caliptra_intr_received_s; +extern volatile caliptra_intr_received_s cptra_intr_rcv; + +////////////////////////////////////////////////////////////////////////////// +// Function Declarations +// + +// Performs all the CSR setup to configure and enable vectored external interrupts +void init_interrupts(void); + +// These inline functions are used to insert event-specific functionality into the +// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr" +inline void service_doe_error_intr() {return;} +inline void service_doe_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_ecc_error_intr() {return;} +inline void service_ecc_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_hmac_error_intr() {return;} +inline void service_hmac_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_kv_error_intr() {return;} +inline void service_kv_notif_intr() {return;} +inline void service_sha512_error_intr() {return;} +inline void service_sha512_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_sha256_error_intr() {return;} +inline void service_sha256_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_qspi_error_intr() {return;} +inline void service_qspi_notif_intr() {return;} +inline void service_uart_error_intr() {return;} +inline void service_uart_notif_intr() {return;} +inline void service_i3c_error_intr() {return;} +inline void service_i3c_notif_intr() {return;} + +inline void service_soc_ifc_error_intr() { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_soc_ifc_notif_intr () { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_sha512_acc_error_intr() {return;} +inline void service_sha512_acc_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_axi_dma_error_intr() { + uint32_t * reg = (uint32_t *) (CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad axi_dma_error_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} +inline void service_axi_dma_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; +// VPRINTF(LOW, "ntf\n"); + /* Write 1 to Clear the pending interrupt */ + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK; + } + if (sts & AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK) { + *reg = AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad axi_dma_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + + +#endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_dma/smoke_test_dma.c b/src/integration/test_suites/smoke_test_dma/smoke_test_dma.c new file mode 100644 index 000000000..5c58441c4 --- /dev/null +++ b/src/integration/test_suites/smoke_test_dma/smoke_test_dma.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +#include "caliptra_defines.h" +#include "caliptra_isr.h" +#include "riscv-csr.h" +#include "veer-csr.h" +#include "riscv_hw_if.h" +#include +#include +#include "printf.h" +#include "soc_ifc.h" + + +volatile char* stdout = (char *)STDOUT; +volatile uint32_t intr_count = 0; +#ifdef CPT_VERBOSITY + enum printf_verbosity verbosity_g = CPT_VERBOSITY; +#else + enum printf_verbosity verbosity_g = LOW; +#endif + +volatile caliptra_intr_received_s cptra_intr_rcv = { + .doe_error = 0, + .doe_notif = 0, + .ecc_error = 0, + .ecc_notif = 0, + .hmac_error = 0, + .hmac_notif = 0, + .kv_error = 0, + .kv_notif = 0, + .sha512_error = 0, + .sha512_notif = 0, + .sha256_error = 0, + .sha256_notif = 0, + .qspi_error = 0, + .qspi_notif = 0, + .uart_error = 0, + .uart_notif = 0, + .i3c_error = 0, + .i3c_notif = 0, + .soc_ifc_error = 0, + .soc_ifc_notif = 0, + .sha512_acc_error = 0, + .sha512_acc_notif = 0, + .axi_dma_notif = 0, + .axi_dma_notif = 0, +}; + +void main(void) { + int argc=0; + char *argv[1]; + uint32_t reg; + uint8_t fail = 0; + uint32_t send_payload[16] = { + 0xabadface, + 0xba5eba11, + 0xcafebabe, + 0xdeadbeef, + 0xebbf1000, + 0xfadefee1, + 0x12344321, + 0xa5a5a5a5, + 0x14351375, + 0x8afdbe82, + 0xafb832ba, + 0x8843151a, + 0xbad831b1, + 0xf831ba83, + 0xad813451, + 0x67120ad3 + }; + uint32_t mbox_send_payload[16] = { + 0x0991c03c, + 0x7bc14838, + 0xb05f2c82, + 0x7b233274, + 0x01b7ba27, + 0x3f24db45, + 0xd945c472, + 0xabac3989, + 0x64af1d5e, + 0xda068da4, + 0xeb9102ab, + 0xf796de3e, + 0x88fc6af8, + 0x1a169287, + 0xc9a6e724, + 0x667f9dd5 + }; + uint32_t read_payload[16]; + uint32_t mbox_read_payload[16]; + + VPRINTF(LOW, "----------------------------------\nSmoke Test AXI DMA !!\n----------------------------------\n"); + + // Setup the interrupt CSR configuration + init_interrupts(); + reg = lsu_read_32(CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R); + lsu_write_32(CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R, reg & ~(AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK | + AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK)); + + // Test each malformed command check + // TODO + + // Send data through AHB interface to AXI_DMA, target the AXI SRAM + VPRINTF(LOW, "Sending payload via AHB i/f\n"); + soc_ifc_axi_dma_send_ahb_payload(AXI_SRAM_BASE_ADDR, 0, send_payload, 16*4, 0); + + // Send data through Mailbox to AXI_DMA, target the AXI SRAM + VPRINTF(LOW, "Writing payload to Mailbox via Direct Mode\n"); + // Acquire the mailbox lock + if (soc_ifc_mbox_acquire_lock(1)) { + VPRINTF(ERROR, "Acquire mailbox lock failed\n"); + fail = 1; + } + // Write data into mailbox using direct-mode + for (uint32_t dw = 0; dw < 16; dw++) { + lsu_write_32(MBOX_DIR_BASE_ADDR + 0x4400 + (dw << 2), mbox_send_payload[dw]); + } + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); + VPRINTF(LOW, "Sending payload from Mailbox\n"); + if (soc_ifc_axi_dma_send_mbox_payload(0x4400, AXI_SRAM_BASE_ADDR + 16*4, 0, 16*4, 0)) { + fail = 1; + } + + // Move data from one address to another in AXI SRAM + // Use the block-size feature + VPRINTF(LOW, "Moving payload at SRAM via axi-to-axi xfer\n"); + soc_ifc_axi_dma_send_axi_to_axi(AXI_SRAM_BASE_ADDR, 0, AXI_SRAM_BASE_ADDR + AXI_SRAM_SIZE_BYTES/2, 0, 2*16*4, 16*2); + + // Read data back from AXI SRAM and confirm it matches + VPRINTF(LOW, "Reading payload via AHB i/f\n"); + soc_ifc_axi_dma_read_ahb_payload(AXI_SRAM_BASE_ADDR + AXI_SRAM_SIZE_BYTES/2, 0, read_payload, 16*4, 0); + for (uint8_t ii = 0; ii < 16; ii++) { + if (read_payload[ii] != send_payload[ii]) { + VPRINTF(ERROR, "read_payload[%d] (0x%x) does not match send_payload[%d] (0x%x)\n", ii, read_payload[ii], ii, send_payload[ii]); + fail = 1; + } + } + + // Read data back through mailbox using direct-mode + VPRINTF(LOW, "Reading payload to Mailbox\n"); + if (soc_ifc_axi_dma_read_mbox_payload(AXI_SRAM_BASE_ADDR + AXI_SRAM_SIZE_BYTES/2 + 16*4, 0x8800, 0, 16*4, 0)) { + fail = 1; + } + VPRINTF(LOW, "Reading payload from Mailbox via Direct Mode\n"); + // Acquire the mailbox lock + if (soc_ifc_mbox_acquire_lock(1)) { + VPRINTF(ERROR, "Acquire mailbox lock failed\n"); + fail = 1; + } + for (uint32_t dw = 0; dw < 16; dw++) { + mbox_read_payload[dw] = lsu_read_32(MBOX_DIR_BASE_ADDR + 0x8800 + (dw << 2)); + if (mbox_read_payload[dw] != mbox_send_payload[dw]) { + VPRINTF(ERROR, "mbox_read_payload[%d] (0x%x) does not match mbox_send_payload[%d] (0x%x)\n", dw, mbox_read_payload[dw], dw, mbox_send_payload[dw]); + fail = 1; + } + } + lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); + + + if (fail) { + VPRINTF(FATAL, "smoke_test_dma failed!\n"); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} diff --git a/src/integration/test_suites/smoke_test_dma/smoke_test_dma.yml b/src/integration/test_suites/smoke_test_dma/smoke_test_dma.yml new file mode 100755 index 000000000..e4385609e --- /dev/null +++ b/src/integration/test_suites/smoke_test_dma/smoke_test_dma.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +seed: 1 +testname: smoke_test_dma diff --git a/src/integration/test_suites/smoke_test_doe_cg/caliptra_isr.h b/src/integration/test_suites/smoke_test_doe_cg/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_doe_cg/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_doe_cg/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_doe_rand/caliptra_isr.h b/src/integration/test_suites/smoke_test_doe_rand/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_doe_rand/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_doe_rand/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_doe_scan/caliptra_isr.h b/src/integration/test_suites/smoke_test_doe_scan/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_doe_scan/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_doe_scan/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h index d5a7efebb..5c6b2135e 100644 --- a/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -252,5 +254,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/caliptra_isr.h b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h b/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h b/src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h index 7bf456414..073409c01 100644 --- a/src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h @@ -55,6 +55,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -189,5 +191,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_iccm_reset/caliptra_isr.h b/src/integration/test_suites/smoke_test_iccm_reset/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_iccm_reset/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_iccm_reset/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_cg/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_cg/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_cg/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_cg/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/smoke_test_kv_hmac_multiblock_flow.c b/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/smoke_test_kv_hmac_multiblock_flow.c index f15512995..5e8e6f839 100644 --- a/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/smoke_test_kv_hmac_multiblock_flow.c +++ b/src/integration/test_suites/smoke_test_kv_hmac_multiblock_flow/smoke_test_kv_hmac_multiblock_flow.c @@ -56,6 +56,8 @@ volatile caliptra_intr_received_s cptra_intr_rcv = { .soc_ifc_notif = 0, .sha512_acc_error = 0, .sha512_acc_notif = 0, + .axi_dma_error = 0, + .axi_dma_notif = 0, }; void main() { diff --git a/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h index 8f5779e04..08c755bad 100644 --- a/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_mbox/caliptra_isr.h b/src/integration/test_suites/smoke_test_mbox/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_mbox/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_mbox/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c b/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c index 2a8a3f3ff..838730e0f 100644 --- a/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c +++ b/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c @@ -52,6 +52,8 @@ volatile caliptra_intr_received_s cptra_intr_rcv = { .soc_ifc_notif = 0, .sha512_acc_error = 0, .sha512_acc_notif = 0, + .axi_dma_error = 0, + .axi_dma_notif = 0, }; void main () { diff --git a/src/integration/test_suites/smoke_test_mbox_byte_read/caliptra_isr.h b/src/integration/test_suites/smoke_test_mbox_byte_read/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_mbox_byte_read/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_mbox_byte_read/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c b/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c index 7ae9b94bd..d5d61b46a 100644 --- a/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c +++ b/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c @@ -51,6 +51,8 @@ volatile caliptra_intr_received_s cptra_intr_rcv = { .soc_ifc_notif = 0, .sha512_acc_error = 0, .sha512_acc_notif = 0, + .axi_dma_error = 0, + .axi_dma_notif = 0, }; //#ifndef MY_RANDOM_SEED diff --git a/src/integration/test_suites/smoke_test_mbox_cg/caliptra_isr.h b/src/integration/test_suites/smoke_test_mbox_cg/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_mbox_cg/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_mbox_cg/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c index 0bf3924d9..03c3dd5d3 100644 --- a/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c +++ b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c @@ -28,7 +28,7 @@ volatile uint32_t intr_count = 0; enum printf_verbosity verbosity_g = LOW; #endif -#define MBOX_DLEN_VAL 0x00000020 +#define MBOX_DLEN_VAL 0x00000100 volatile caliptra_intr_received_s cptra_intr_rcv = { .doe_error = 0, @@ -53,6 +53,8 @@ volatile caliptra_intr_received_s cptra_intr_rcv = { .soc_ifc_notif = 0, .sha512_acc_error = 0, .sha512_acc_notif = 0, + .axi_dma_error = 0, + .axi_dma_notif = 0, }; void main () { @@ -68,7 +70,63 @@ void main () { 0x44444444, 0x55555555, 0x66666666, - 0x77777777 }; + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0xffffffff, + 0x00001111, + 0x11112222, + 0x22223333, + 0x33334444, + 0x44445555, + 0x55556666, + 0x66667777, + 0x77778888, + 0x88889999, + 0x9999aaaa, + 0xaaaabbbb, + 0xbbbbcccc, + 0xccccdddd, + 0xddddeeee, + 0xeeeeffff, + 0xffff0000, + 0x00001122, + 0x11112233, + 0x22223344, + 0x33334455, + 0x44445566, + 0x55556677, + 0x66667788, + 0x77778899, + 0x888899aa, + 0x9999aabb, + 0xaaaabbcc, + 0xbbbbccdd, + 0xccccddee, + 0xddddeeff, + 0xeeeeff00, + 0xffff0011, + 0x00001123, + 0x11112234, + 0x22223345, + 0x33334456, + 0x44445567, + 0x55556678, + 0x66667789, + 0x7777889a, + 0x888899ab, + 0x9999aabc, + 0xaaaabbcd, + 0xbbbbccde, + 0xccccddef, + 0xddddeef0, + 0xeeeeff01, + 0xffff0012 }; uint32_t read_data; uint32_t mitb0 = 0x000000F0; @@ -127,12 +185,14 @@ void main () { //check FSM state, should be in EXECUTE_SOC state = (lsu_read_32(CLP_MBOX_CSR_MBOX_STATUS) & MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK) >> MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW; - if (state != MBOX_EXECUTE_SOC) { + if (state != MBOX_EXECUTE_SOC && ((lsu_read_32(CLP_MBOX_CSR_MBOX_EXECUTE) & MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK) == 1)) { VPRINTF(ERROR, "ERROR: mailbox in unexpected state (%x) when expecting MBOX_EXECUTE_SOC (0x%x)\n", state, MBOX_EXECUTE_SOC); SEND_STDOUT_CTRL( 0x1); while(1); + } else if ((lsu_read_32(CLP_MBOX_CSR_MBOX_EXECUTE) & MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK) == 0) { + VPRINTF(LOW, "FW: Mailbox operation has ended, execute cleared to 0. Ending test with success\n"); } else { - VPRINTF(LOW, "FW: Mailbox in expected state, MBOX_EXECUTE_SOC, ending test with success\n"); + VPRINTF(LOW, "FW: Mailbox in expected state, MBOX_EXECUTE_SOC. Ending test with success\n"); } //-------------------------------------------------------------------------------------------- @@ -140,12 +200,10 @@ void main () { VPRINTF(LOW, "FW: Wait for SoC to reset execute register\n"); while((lsu_read_32(CLP_MBOX_CSR_MBOX_EXECUTE) & MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK) == 1); - //Force unlock - lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); - set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en); //poll for mbox lock + VPRINTF(LOW, "FW: Acquire lock to send mbox cmd\n"); while((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) == 1); set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en); diff --git a/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h b/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_pcr_zeroize/caliptra_isr.h b/src/integration/test_suites/smoke_test_pcr_zeroize/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_pcr_zeroize/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_pcr_zeroize/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h b/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h index fca82fef0..396bfa18d 100644 --- a/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -239,5 +241,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_ras/caliptra_isr.h b/src/integration/test_suites/smoke_test_ras/caliptra_isr.h index a245e2994..926e19966 100644 --- a/src/integration/test_suites/smoke_test_ras/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_ras/caliptra_isr.h @@ -55,6 +55,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; #define RV_EXCEPTION_STRUCT 1 @@ -195,5 +197,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c index e7be338f3..8c9b3d7c3 100644 --- a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c +++ b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c @@ -209,6 +209,8 @@ volatile caliptra_intr_received_s cptra_intr_rcv = { .soc_ifc_notif = 0, .sha512_acc_error = 0, .sha512_acc_notif = 0, + .axi_dma_notif = 0, + .axi_dma_notif = 0, }; volatile rv_exception_struct_s exc_flag __attribute__((section(".dccm.persistent"))); // WARNING: if DCCM ERROR injection is enabled, writes to this may be corrupted volatile uint32_t boot_count __attribute__((section(".dccm.persistent"))) = 0; diff --git a/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h index 1b9018b20..205798892 100644 --- a/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -251,5 +253,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_sha256_wntz/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha256_wntz/caliptra_isr.h index 257588cea..152f493be 100644 --- a/src/integration/test_suites/smoke_test_sha256_wntz/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_sha256_wntz/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -257,5 +259,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_sha256_wntz_rand/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha256_wntz_rand/caliptra_isr.h index 257588cea..152f493be 100644 --- a/src/integration/test_suites/smoke_test_sha256_wntz_rand/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_sha256_wntz_rand/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -257,5 +259,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h index 841da2048..72d975f9f 100644 --- a/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h @@ -57,6 +57,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -106,5 +108,8 @@ inline void service_sha512_acc_notif_intr() { sha_intr_status = *reg; } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} -#endif //CALIPTRA_ISR_H \ No newline at end of file + +#endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h b/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_trng/caliptra_isr.h b/src/integration/test_suites/smoke_test_trng/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_trng/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_trng/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_uart/caliptra_isr.h b/src/integration/test_suites/smoke_test_uart/caliptra_isr.h index fca82fef0..396bfa18d 100644 --- a/src/integration/test_suites/smoke_test_uart/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_uart/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -239,5 +241,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_veer/caliptra_isr.h b/src/integration/test_suites/smoke_test_veer/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_veer/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_veer/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h b/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h index bb60f9fb2..ae98951d1 100644 --- a/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h @@ -58,6 +58,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -104,5 +106,8 @@ inline void service_soc_ifc_notif_intr () {printf("ERROR");} inline void service_sha512_acc_error_intr() {printf("ERROR");} inline void service_sha512_acc_notif_intr() {printf("ERROR");} +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_wdt_rst/caliptra_isr.h b/src/integration/test_suites/smoke_test_wdt_rst/caliptra_isr.h index ddad5ade5..d6d491a63 100644 --- a/src/integration/test_suites/smoke_test_wdt_rst/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_wdt_rst/caliptra_isr.h @@ -58,6 +58,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -104,5 +106,8 @@ inline void service_soc_ifc_notif_intr () {printf("ERROR");} inline void service_sha512_acc_error_intr() {printf("ERROR");} inline void service_sha512_acc_notif_intr() {printf("ERROR");} +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_wdt_rst/smoke_test_wdt_rst.c b/src/integration/test_suites/smoke_test_wdt_rst/smoke_test_wdt_rst.c index 68c8d715c..451342b3a 100644 --- a/src/integration/test_suites/smoke_test_wdt_rst/smoke_test_wdt_rst.c +++ b/src/integration/test_suites/smoke_test_wdt_rst/smoke_test_wdt_rst.c @@ -168,10 +168,14 @@ void main() { SEND_STDOUT_CTRL(0xf1); configure_wdt_cascade(0x200, 0x00, 0xffffffff, 0xffffffff); VPRINTF(LOW, "Cascaded mode with timer2 timeout - NMI - cold rst\n"); + *wdt_timer1_en = 0x0; *wdt_timer2_en = 0x0; - *wdt_timer1_ctrl = 0x1; //restart counter so timer1 can start counting +// *wdt_timer1_ctrl = 0x1; //restart counter so timer1 can start counting set_t2_period(0x00000200, 0x00000000); + + *wdt_timer1_en = 0x1; + *wdt_timer1_ctrl = 0x1; //restart counter so timer1 can start counting VPRINTF(LOW, "Stall until timer1 times out\n"); VPRINTF(LOW, "Stall until timer2 times out\n"); diff --git a/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h b/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h index 8f5779e04..3b28f5e23 100644 --- a/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h +++ b/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h @@ -56,6 +56,8 @@ typedef struct { uint32_t soc_ifc_notif; uint32_t sha512_acc_error; uint32_t sha512_acc_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; } caliptra_intr_received_s; extern volatile caliptra_intr_received_s cptra_intr_rcv; @@ -243,5 +245,8 @@ inline void service_sha512_acc_notif_intr() { } } +inline void service_axi_dma_error_intr() {return;} +inline void service_axi_dma_notif_intr() {return;} + #endif //CALIPTRA_ISR_H diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf index 2b6bef894..c34272780 100644 --- a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf @@ -22,6 +22,9 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl @@ -42,8 +45,6 @@ +incdir+${CALIPTRA_ROOT}/src/integration/asserts +incdir+${CALIPTRA_ROOT}/src/datavault/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl -+incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl -+incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb +incdir+${CALIPTRA_ROOT}/src/csrng/rtl +incdir+${CALIPTRA_ROOT}/src/spi_host/rtl @@ -60,6 +61,7 @@ +incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests +incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench +incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl @@ -68,7 +70,6 @@ +incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl +incdir+${CALIPTRA_ROOT}/src/ecc/rtl +incdir+${CALIPTRA_ROOT}/src/kmac/rtl -+incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/edn/rtl +incdir+${CALIPTRA_ROOT}/src/aes/rtl ${UVM_HOME}/src/uvm_pkg.sv @@ -131,6 +132,18 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv @@ -175,16 +188,6 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv -${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv -${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv -${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv @@ -219,6 +222,52 @@ ${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_ ${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv ${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hvl_top.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv @@ -357,40 +406,6 @@ ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv ${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv ${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv -${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv -${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf index 2b6bef894..c34272780 100644 --- a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf @@ -22,6 +22,9 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl @@ -42,8 +45,6 @@ +incdir+${CALIPTRA_ROOT}/src/integration/asserts +incdir+${CALIPTRA_ROOT}/src/datavault/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl -+incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl -+incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb +incdir+${CALIPTRA_ROOT}/src/csrng/rtl +incdir+${CALIPTRA_ROOT}/src/spi_host/rtl @@ -60,6 +61,7 @@ +incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests +incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench +incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../tb ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl @@ -68,7 +70,6 @@ +incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl +incdir+${CALIPTRA_ROOT}/src/ecc/rtl +incdir+${CALIPTRA_ROOT}/src/kmac/rtl -+incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/edn/rtl +incdir+${CALIPTRA_ROOT}/src/aes/rtl ${UVM_HOME}/src/uvm_pkg.sv @@ -131,6 +132,18 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv @@ -175,16 +188,6 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv -${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv -${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv -${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv @@ -219,6 +222,52 @@ ${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/../coverage/caliptra_top_cov_ ${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv ${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hvl_top.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv @@ -357,40 +406,6 @@ ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv ${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv ${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv -${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv -${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv -${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf index 677423b08..579943ae7 100644 --- a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf @@ -22,6 +22,9 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl @@ -38,6 +41,7 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers +incdir+${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${UVM_HOME}/src/uvm_pkg.sv ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh @@ -99,6 +103,18 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv @@ -137,6 +153,52 @@ ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/e ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv ${CALIPTRA_ROOT}/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/caliptra_top_env_pkg.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv diff --git a/src/libs/rtl/skidbuffer.v b/src/libs/rtl/skidbuffer.v index b9bb20e2f..a589226a5 100644 --- a/src/libs/rtl/skidbuffer.v +++ b/src/libs/rtl/skidbuffer.v @@ -56,7 +56,11 @@ // Gisselquist Technology, LLC // // Caliptra Modifications: -// Revert the default_nettype assignment at file end +// * Revert the default_nettype assignment at file end +// * Convert i_reset from active-high synchronous reset to +// active-low asynchronous reset +// * Enable OPT_INITIAL behavior by default using async reset instead of +// initial block // //////////////////////////////////////////////////////////////////////////////// // }}} @@ -88,12 +92,11 @@ module skidbuffer #( parameter [0:0] OPT_OUTREG = 1, // parameter [0:0] OPT_PASSTHROUGH = 0, - parameter DW = 8, - parameter [0:0] OPT_INITIAL = 1'b1 + parameter DW = 8 // }}} ) ( // {{{ - input wire i_clk, i_reset, // fixme resetn, async + input wire i_clk, i_reset, // Changed to resetn, async input wire i_valid, output wire o_ready, input wire [DW-1:0] i_data, @@ -134,9 +137,8 @@ module skidbuffer #( // r_valid // {{{ - initial if (OPT_INITIAL) r_valid = 0; - always @(posedge i_clk) - if (i_reset) + always @(posedge i_clk or negedge i_reset) + if (!i_reset) r_valid <= 0; else if ((i_valid && o_ready) && (o_valid && !i_ready)) // We have incoming data, but the output is stalled @@ -147,9 +149,8 @@ module skidbuffer #( // r_data // {{{ - initial if (OPT_INITIAL) r_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && i_reset) + always @(posedge i_clk or negedge i_reset) + if (!i_reset) r_data <= 0; else if (OPT_LOWPOWER && (!o_valid || i_ready)) r_data <= 0; @@ -173,7 +174,8 @@ module skidbuffer #( // {{{ // o_valid // {{{ - assign o_valid = !i_reset && (i_valid || r_valid); + // NOTE: As i_reset is now asynchronous, omit from the equation + assign o_valid = /*i_reset && */(i_valid || r_valid); // }}} // o_data @@ -194,9 +196,8 @@ module skidbuffer #( // {{{ reg ro_valid; - initial if (OPT_INITIAL) ro_valid = 0; - always @(posedge i_clk) - if (i_reset) + always @(posedge i_clk or negedge i_reset) + if (!i_reset) ro_valid <= 0; else if (!o_valid || i_ready) ro_valid <= (i_valid || r_valid); @@ -206,9 +207,8 @@ module skidbuffer #( // o_data // {{{ - initial if (OPT_INITIAL) o_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && i_reset) + always @(posedge i_clk or negedge i_reset) + if (!i_reset) o_data <= 0; else if (!o_valid || i_ready) begin @@ -258,7 +258,7 @@ module skidbuffer #( always @(*) if (!f_past_valid) - assume(i_reset); + assume(!i_reset); //////////////////////////////////////////////////////////////////////// // @@ -269,19 +269,19 @@ module skidbuffer #( always @(posedge i_clk) if (!f_past_valid) begin - `ASSUME(!i_valid || !OPT_INITIAL); - end else if ($past(i_valid && !o_ready && !i_reset) && !i_reset) + `ASSUME(!i_valid); + end else if ($past(i_valid && !o_ready && i_reset) && i_reset) `ASSUME(i_valid && $stable(i_data)); `ifdef VERIFIC `define FORMAL_VERIFIC // Reset properties property RESET_CLEARS_IVALID; - @(posedge i_clk) i_reset |=> !i_valid; + @(posedge i_clk) !i_reset |=> !i_valid; endproperty property IDATA_HELD_WHEN_NOT_READY; - @(posedge i_clk) disable iff (i_reset) + @(posedge i_clk) disable iff (!i_reset) i_valid && !o_ready |=> i_valid && $stable(i_data); endproperty @@ -303,11 +303,11 @@ module skidbuffer #( begin always @(posedge i_clk) - if (!f_past_valid) // || $past(i_reset)) + if (!f_past_valid) // || $past(!i_reset)) begin // Following any reset, valid must be deasserted - assert(!o_valid || !OPT_INITIAL); - end else if ($past(o_valid && !i_ready && !i_reset) && !i_reset) + assert(!o_valid); + end else if ($past(o_valid && !i_ready && i_reset) && i_reset) // Following any stall, valid must remain high and // data must be preserved assert(o_valid && $stable(o_data)); @@ -328,7 +328,7 @@ module skidbuffer #( // ready for a new request // {{{ always @(posedge i_clk) - if (f_past_valid && $past(OPT_OUTREG && i_reset)) + if (f_past_valid && $past(OPT_OUTREG && !i_reset)) assert(o_ready); // }}} @@ -338,12 +338,12 @@ module skidbuffer #( // {{{ `ifndef VERIFIC always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && $past(i_valid && o_ready + if (f_past_valid && !$past(!i_reset) && $past(i_valid && o_ready && (!OPT_OUTREG || o_valid) && !i_ready)) assert(!o_ready && w_data == $past(i_data)); `else assert property (@(posedge i_clk) - disable iff (i_reset) + disable iff (!i_reset) (i_valid && o_ready && (!OPT_OUTREG || o_valid) && !i_ready) |=> (!o_ready && w_data == $past(i_data))); @@ -357,7 +357,7 @@ module skidbuffer #( begin // {{{ always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && !i_reset + if (f_past_valid && !$past(!i_reset) && i_reset && $past(i_ready)) begin assert(o_valid == i_valid); @@ -367,7 +367,7 @@ module skidbuffer #( end else begin // {{{ always @(posedge i_clk) - if (f_past_valid && !$past(i_reset)) + if (f_past_valid && !$past(!i_reset)) begin if ($past(i_valid && o_ready)) assert(o_valid); @@ -393,7 +393,7 @@ module skidbuffer #( if (OPT_LOWPOWER) begin always @(*) - if ((OPT_OUTREG || !i_reset) && !o_valid) + if ((OPT_OUTREG || i_reset) && !o_valid) assert(o_data == 0); always @(*) @@ -418,7 +418,7 @@ module skidbuffer #( initial f_changed_data = 0; always @(posedge i_clk) - if (i_reset) + if (!i_reset) f_changed_data <= 1; else if (i_valid && $past(!i_valid || o_ready)) begin @@ -432,7 +432,7 @@ module skidbuffer #( reg [3:0] cvr_steps, cvr_hold; always @(posedge i_clk) - if (i_reset) + if (!i_reset) begin cvr_steps <= 0; cvr_hold <= 0; @@ -479,7 +479,7 @@ module skidbuffer #( `else // Cover test cover property (@(posedge i_clk) - disable iff (i_reset) + disable iff (!i_reset) (!o_valid && !i_valid) ##1 i_valid && i_ready [*3] ##1 i_valid && !i_ready diff --git a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf index 3e3824be2..54545ff6b 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf @@ -1,5 +1,8 @@ ++incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh diff --git a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf index da326a7e7..8a16ea3fc 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf @@ -1,5 +1,8 @@ ++incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh diff --git a/src/soc_ifc/config/compile.yml b/src/soc_ifc/config/compile.yml index 4dd2b2a39..e1f819978 100644 --- a/src/soc_ifc/config/compile.yml +++ b/src/soc_ifc/config/compile.yml @@ -1,7 +1,8 @@ --- provides: [soc_ifc_pkg] schema_version: 2.4.0 -requires: [] +requires: + - caliptra_top_defines targets: rtl: directories: [$COMPILE_ROOT/rtl] @@ -33,6 +34,7 @@ provides: [soc_ifc_coverage] schema_version: 2.4.0 requires: - libs + - axi_pkg - soc_ifc_pkg targets: tb: @@ -46,11 +48,12 @@ provides: [soc_ifc_top] schema_version: 2.4.0 requires: - libs + - axi_sub + - axi_dma # for beh_lib with rvecc_encode/decode - el2_veer_pkg - soc_ifc_pkg - sha512_ctrl - - caliptra_top_defines targets: rtl: directories: @@ -77,7 +80,6 @@ schema_version: 2.4.0 requires: - soc_ifc_coverage - soc_ifc_top - - caliptra_top_defines targets: tb: directories: diff --git a/src/soc_ifc/config/soc_ifc_pkg.vf b/src/soc_ifc/config/soc_ifc_pkg.vf index 0ba5a33ba..ebb323b9f 100644 --- a/src/soc_ifc/config/soc_ifc_pkg.vf +++ b/src/soc_ifc/config/soc_ifc_pkg.vf @@ -1,4 +1,7 @@ ++incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv diff --git a/src/soc_ifc/config/soc_ifc_tb.vf b/src/soc_ifc/config/soc_ifc_tb.vf index 42461ba5d..0bb6c17fd 100644 --- a/src/soc_ifc/config/soc_ifc_tb.vf +++ b/src/soc_ifc/config/soc_ifc_tb.vf @@ -1,11 +1,15 @@ +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/tb ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh @@ -20,10 +24,22 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -37,6 +53,52 @@ ${CALIPTRA_ROOT}/src/soc_ifc/tb/soc_ifc_tb.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv diff --git a/src/soc_ifc/config/soc_ifc_top.vf b/src/soc_ifc/config/soc_ifc_top.vf index 9f8dfc453..66bec0f70 100644 --- a/src/soc_ifc/config/soc_ifc_top.vf +++ b/src/soc_ifc/config/soc_ifc_top.vf @@ -1,9 +1,13 @@ +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh @@ -18,6 +22,18 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh @@ -29,6 +45,52 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv diff --git a/src/soc_ifc/coverage/soc_ifc_cov_bind.sv b/src/soc_ifc/coverage/soc_ifc_cov_bind.sv index 47a39dbf2..1075c8d0b 100644 --- a/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +++ b/src/soc_ifc/coverage/soc_ifc_cov_bind.sv @@ -18,9 +18,14 @@ module soc_ifc_cov_bind; bind soc_ifc_top soc_ifc_cov_if #( .AHB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), .AHB_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE), - .APB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), - .APB_DATA_WIDTH(`CALIPTRA_APB_DATA_WIDTH), - .APB_USER_WIDTH(`CALIPTRA_APB_USER_WIDTH) + .AXI_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), + .AXI_DATA_WIDTH(`CALIPTRA_AXI_DATA_WIDTH), + .AXI_ID_WIDTH (`CALIPTRA_AXI_ID_WIDTH ), + .AXI_USER_WIDTH(`CALIPTRA_AXI_USER_WIDTH), + .AXIM_ADDR_WIDTH(`CALIPTRA_AXI_DMA_ADDR_WIDTH), + .AXIM_DATA_WIDTH(CPTRA_AXI_DMA_DATA_WIDTH), + .AXIM_ID_WIDTH (CPTRA_AXI_DMA_ID_WIDTH), + .AXIM_USER_WIDTH(CPTRA_AXI_DMA_USER_WIDTH) ) i_soc_ifc_cov_if (.*); `endif diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv index 52eac09ae..e31c77fea 100644 --- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv +++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv @@ -21,8 +21,8 @@ // // Coverpoints: // - Bins for total addressible space per register (including all fields) -// - Transition bins: An APB or AHB Write followed by APB or AHB Read within 1000 cycles -// - Ignore bins: IDLE (no read/write activity), simultaneous RD and WR over APB or AHB. +// - Transition bins: An AXI or AHB Write followed by AXI or AHB Read within 1000 cycles +// - Ignore bins: IDLE (no read/write activity), simultaneous RD and WR over AXI or AHB. // // Not covered and TODO. // - Bins for individual fields within a register for special behavior. @@ -37,25 +37,26 @@ interface soc_ifc_cov_if import soc_ifc_pkg::*; import soc_ifc_reg_pkg::*; #( - parameter APB_ADDR_WIDTH = 18 - ,parameter APB_DATA_WIDTH = 32 - ,parameter APB_USER_WIDTH = 32 - ,parameter AHB_ADDR_WIDTH = 18 - ,parameter AHB_DATA_WIDTH = 32 + parameter AXI_ADDR_WIDTH = 18 + ,parameter AXI_DATA_WIDTH = 32 + ,parameter AXI_ID_WIDTH = 32 + ,parameter AXI_USER_WIDTH = 32 + ,parameter AHB_ADDR_WIDTH = 18 + ,parameter AHB_DATA_WIDTH = 32 + ,parameter AXIM_ADDR_WIDTH = 48 + ,parameter AXIM_DATA_WIDTH = 32 + ,parameter AXIM_ID_WIDTH = 5 + ,parameter AXIM_USER_WIDTH = 32 ) ( input logic clk, input logic clk_cg, input logic soc_ifc_clk_cg, + input logic rdc_clk_cg, //SoC boot signals input logic cptra_pwrgood, input logic cptra_rst_b, - input logic uc_req_dv, - input soc_ifc_req_t uc_req, - input logic soc_req_dv, - input soc_ifc_req_t soc_req, - input soc_ifc_req_t soc_ifc_reg_req_data, input logic ready_for_fuses, input logic ready_for_fw_push, @@ -64,22 +65,17 @@ interface soc_ifc_cov_if input logic mailbox_data_avail, input logic mailbox_flow_done, + input logic recovery_data_avail, + input var security_state_t security_state, input logic [1:0][31:0] generic_input_wires, input logic BootFSM_BrkPoint, input logic [1:0][31:0] generic_output_wires, - //SoC APB Interface - input logic [APB_ADDR_WIDTH-1:0] paddr_i, - input logic psel_i, - input logic penable_i, - input logic pwrite_i, - input logic [APB_DATA_WIDTH-1:0] pwdata_i, - input logic [APB_USER_WIDTH-1:0] pauser_i, - input logic pready_o, - input logic [APB_DATA_WIDTH-1:0] prdata_o, - input logic pslverr_o, + //SoC AXI Interface + axi_if.w_sub s_axi_w_if, + axi_if.r_sub s_axi_r_if, //uC AHB Lite Interface input logic [AHB_ADDR_WIDTH-1:0] haddr_i, @@ -94,6 +90,10 @@ interface soc_ifc_cov_if input logic hreadyout_o, input logic [AHB_DATA_WIDTH-1:0] hrdata_o, + // AXI Manager INF + axi_if.w_mgr m_axi_w_if, + axi_if.r_mgr m_axi_r_if, + //SoC Interrupts input logic cptra_error_fatal, input logic cptra_error_non_fatal, @@ -104,11 +104,17 @@ interface soc_ifc_cov_if input wire soc_ifc_notif_intr, input wire sha_error_intr, input wire sha_notif_intr, + input wire dma_error_intr, + input wire dma_notif_intr, + input wire timer_intr, //SRAM interface input mbox_sram_req_t mbox_sram_req, input mbox_sram_resp_t mbox_sram_resp, + // RV ECC Status Interface + input rv_ecc_sts_t rv_ecc_sts, + //Obfuscated UDS and FE input logic clear_obf_secrets, input logic scan_mode_f, @@ -130,10 +136,19 @@ interface soc_ifc_cov_if //uC reset input logic cptra_uc_rst_b, //Clock gating - input logic clk_gating_en + input logic clk_gating_en, + input logic rdc_clk_dis, + input logic fw_update_rst_window, + + input logic uc_req_dv, + input soc_ifc_req_t uc_req, + input logic soc_req_dv, + input soc_ifc_req_t soc_req, + input soc_ifc_req_t soc_ifc_reg_req_data + ); - enum bit [3:0] {IDLE = '0, AHB_RD = 4'h8, AHB_WR = 4'h4, APB_RD = 4'h2, APB_WR = 4'h1} bus_event_e; + enum bit [3:0] {IDLE = '0, AHB_RD = 4'h8, AHB_WR = 4'h4, AXI_RD = 4'h2, AXI_WR = 4'h1} bus_event_e; logic uc_rd, uc_wr, soc_rd, soc_wr; @@ -149,13 +164,15 @@ interface soc_ifc_cov_if cptra_noncore_rst_b_cp: coverpoint cptra_noncore_rst_b; cptra_uc_rst_b_cp: coverpoint cptra_uc_rst_b; clk_gating_en_cp: coverpoint clk_gating_en; + rdc_clk_dis_cp: coverpoint rdc_clk_dis; + fw_update_rst_window_cp: coverpoint fw_update_rst_window; security_state_cp: coverpoint security_state; - scan_mode_f_cp: coverpoint scan_mode_f; ready_for_fuses_cp: coverpoint ready_for_fuses; ready_for_fw_push_cp: coverpoint ready_for_fw_push; ready_for_runtime_cp: coverpoint ready_for_runtime; mailbox_data_avail_cp: coverpoint mailbox_data_avail; mailbox_flow_done_cp: coverpoint mailbox_flow_done; + recovery_data_avail: coverpoint recovery_data_avail; cptra_error_fatal_cp: coverpoint cptra_error_fatal; cptra_error_non_fatal_cp: coverpoint cptra_error_non_fatal; trng_req_cp: coverpoint trng_req; @@ -168,9 +185,14 @@ interface soc_ifc_cov_if soc_ifc_notif_intr_cp: coverpoint soc_ifc_notif_intr; sha_error_intr_cp: coverpoint sha_error_intr; sha_notif_intr_cp: coverpoint sha_notif_intr; + dma_error_intr_cp: coverpoint dma_error_intr; + dma_notif_intr_cp: coverpoint dma_notif_intr; + timer_intr_cp: coverpoint timer_intr; mbox_sram_req_cp: coverpoint mbox_sram_req; mbox_sram_resp_cp: coverpoint mbox_sram_resp; + rv_ecc_sts_cp: coverpoint rv_ecc_sts; clear_obf_secrets_cp: coverpoint clear_obf_secrets; + scan_mode_f_cp: coverpoint scan_mode_f; cptra_obf_key_reg_cp: coverpoint cptra_obf_key_reg; obf_field_entropy_cp: coverpoint obf_field_entropy; obf_uds_seed_cp: coverpoint obf_uds_seed; @@ -190,11 +212,13 @@ interface soc_ifc_cov_if soc_mbox_req_ip_cp: coverpoint i_soc_ifc_arb.soc_mbox_req_ip; soc_sha_req_ip_cp: coverpoint i_soc_ifc_arb.soc_sha_req_ip; + soc_dma_req_ip_cp: coverpoint i_soc_ifc_arb.soc_dma_req_ip; //No stall here, so arbiter never hits these. We can put these back if we ever introduce a stall //soc_reg_req_ip_cp: coverpoint i_soc_ifc_arb.soc_reg_req_ip; uc_mbox_req_ip_cp: coverpoint i_soc_ifc_arb.uc_mbox_req_ip; uc_sha_req_ip_cp: coverpoint i_soc_ifc_arb.uc_sha_req_ip; + uc_dma_req_ip_cp: coverpoint i_soc_ifc_arb.uc_dma_req_ip; //No stall here, so arbiter never hits these. We can put these back if we ever introduce a stall //uc_reg_req_ip_cp: coverpoint i_soc_ifc_arb.uc_reg_req_ip; @@ -208,6 +232,9 @@ interface soc_ifc_cov_if uc_sha_req_cp: coverpoint i_soc_ifc_arb.uc_sha_req; soc_sha_req_cp: coverpoint i_soc_ifc_arb.soc_sha_req; + uc_dma_req_cp: coverpoint i_soc_ifc_arb.uc_dma_req; + soc_dma_req_cp: coverpoint i_soc_ifc_arb.soc_dma_req; + //Cover soc req to mbox addr range with and without valid pauser. soc_mbox_reqXvalid_mbox_req: cross soc_mbox_addr_cp, valid_mbox_req_cp; @@ -398,31 +425,31 @@ interface soc_ifc_cov_if // logic [3:0] bus_CPTRA_SECURITY_STATE; // logic [31:0] full_addr_CPTRA_SECURITY_STATE = `CLP_SOC_IFC_REG_CPTRA_SECURITY_STATE; - logic hit_CPTRA_MBOX_VALID_PAUSER[0:4]; - logic [3:0] bus_CPTRA_MBOX_VALID_PAUSER[0:4]; - logic [31:0] full_addr_CPTRA_MBOX_VALID_PAUSER[0:4]; - assign full_addr_CPTRA_MBOX_VALID_PAUSER[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0; - assign full_addr_CPTRA_MBOX_VALID_PAUSER[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1; - assign full_addr_CPTRA_MBOX_VALID_PAUSER[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2; - assign full_addr_CPTRA_MBOX_VALID_PAUSER[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3; - assign full_addr_CPTRA_MBOX_VALID_PAUSER[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4; - - logic hit_CPTRA_MBOX_PAUSER_LOCK[0:4]; - logic [3:0] bus_CPTRA_MBOX_PAUSER_LOCK[0:4]; - logic [31:0] full_addr_CPTRA_MBOX_PAUSER_LOCK[0:4]; - assign full_addr_CPTRA_MBOX_PAUSER_LOCK[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0; - assign full_addr_CPTRA_MBOX_PAUSER_LOCK[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1; - assign full_addr_CPTRA_MBOX_PAUSER_LOCK[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2; - assign full_addr_CPTRA_MBOX_PAUSER_LOCK[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3; - assign full_addr_CPTRA_MBOX_PAUSER_LOCK[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4; - - logic hit_CPTRA_TRNG_VALID_PAUSER; - logic [3:0] bus_CPTRA_TRNG_VALID_PAUSER; - logic [31:0] full_addr_CPTRA_TRNG_VALID_PAUSER = `CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER; - - logic hit_CPTRA_TRNG_PAUSER_LOCK; - logic [3:0] bus_CPTRA_TRNG_PAUSER_LOCK; - logic [31:0] full_addr_CPTRA_TRNG_PAUSER_LOCK = `CLP_SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK; + logic hit_CPTRA_MBOX_VALID_AXI_ID[0:4]; + logic [3:0] bus_CPTRA_MBOX_VALID_AXI_ID[0:4]; + logic [31:0] full_addr_CPTRA_MBOX_VALID_AXI_ID[0:4]; + assign full_addr_CPTRA_MBOX_VALID_AXI_ID[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0; + assign full_addr_CPTRA_MBOX_VALID_AXI_ID[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1; + assign full_addr_CPTRA_MBOX_VALID_AXI_ID[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2; + assign full_addr_CPTRA_MBOX_VALID_AXI_ID[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3; + assign full_addr_CPTRA_MBOX_VALID_AXI_ID[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4; + + logic hit_CPTRA_MBOX_AXI_ID_LOCK[0:4]; + logic [3:0] bus_CPTRA_MBOX_AXI_ID_LOCK[0:4]; + logic [31:0] full_addr_CPTRA_MBOX_AXI_ID_LOCK[0:4]; + assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0; + assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1; + assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2; + assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3; + assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4; + + logic hit_CPTRA_TRNG_VALID_AXI_ID; + logic [3:0] bus_CPTRA_TRNG_VALID_AXI_ID; + logic [31:0] full_addr_CPTRA_TRNG_VALID_AXI_ID = `CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID; + + logic hit_CPTRA_TRNG_AXI_ID_LOCK; + logic [3:0] bus_CPTRA_TRNG_AXI_ID_LOCK; + logic [31:0] full_addr_CPTRA_TRNG_AXI_ID_LOCK = `CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK; logic hit_CPTRA_TRNG_DATA[0:11]; logic [3:0] bus_CPTRA_TRNG_DATA[0:11]; @@ -526,13 +553,13 @@ interface soc_ifc_cov_if logic [3:0] bus_CPTRA_WDT_STATUS; logic [31:0] full_addr_CPTRA_WDT_STATUS = `CLP_SOC_IFC_REG_CPTRA_WDT_STATUS; - logic hit_CPTRA_FUSE_VALID_PAUSER; - logic [3:0] bus_CPTRA_FUSE_VALID_PAUSER; - logic [31:0] full_addr_CPTRA_FUSE_VALID_PAUSER = `CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER; + logic hit_CPTRA_FUSE_VALID_AXI_ID; + logic [3:0] bus_CPTRA_FUSE_VALID_AXI_ID; + logic [31:0] full_addr_CPTRA_FUSE_VALID_AXI_ID = `CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID; - logic hit_CPTRA_FUSE_PAUSER_LOCK; - logic [3:0] bus_CPTRA_FUSE_PAUSER_LOCK; - logic [31:0] full_addr_CPTRA_FUSE_PAUSER_LOCK = `CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK; + logic hit_CPTRA_FUSE_AXI_ID_LOCK; + logic [3:0] bus_CPTRA_FUSE_AXI_ID_LOCK; + logic [31:0] full_addr_CPTRA_FUSE_AXI_ID_LOCK = `CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK; logic hit_CPTRA_WDT_CFG[0:1]; logic [3:0] bus_CPTRA_WDT_CFG[0:1]; @@ -887,22 +914,22 @@ interface soc_ifc_cov_if logic [31:0] full_addr_intr_brf_notif_soc_req_lock_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R; - assign hit_CPTRA_HW_ERROR_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_FATAL[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_HW_ERROR_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_FATAL[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_HW_ERROR_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_ERROR_FATAL}}; - assign hit_CPTRA_HW_ERROR_NON_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_NON_FATAL[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_HW_ERROR_NON_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_NON_FATAL[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_HW_ERROR_NON_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_ERROR_NON_FATAL}}; - assign hit_CPTRA_FW_ERROR_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_FATAL[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_FW_ERROR_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_FATAL[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_FW_ERROR_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_ERROR_FATAL}}; - assign hit_CPTRA_FW_ERROR_NON_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_NON_FATAL[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_FW_ERROR_NON_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_NON_FATAL[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_FW_ERROR_NON_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_ERROR_NON_FATAL}}; - assign hit_CPTRA_HW_ERROR_ENC = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_ENC[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_HW_ERROR_ENC = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_ENC[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_HW_ERROR_ENC = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_ERROR_ENC}}; - assign hit_CPTRA_FW_ERROR_ENC = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_ENC[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_FW_ERROR_ENC = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_ENC[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_FW_ERROR_ENC = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_ERROR_ENC}}; assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[0][18-1:0]); @@ -929,53 +956,53 @@ interface soc_ifc_cov_if assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[7] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[7][18-1:0]); assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[7]}}; - assign hit_CPTRA_BOOT_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_BOOT_STATUS[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_BOOT_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_BOOT_STATUS[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_BOOT_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_BOOT_STATUS}}; - assign hit_CPTRA_FLOW_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FLOW_STATUS[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_FLOW_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FLOW_STATUS[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_FLOW_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FLOW_STATUS}}; - assign hit_CPTRA_RESET_REASON = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RESET_REASON[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_RESET_REASON = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RESET_REASON[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_RESET_REASON = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_RESET_REASON}}; - // assign hit_CPTRA_SECURITY_STATE = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_SECURITY_STATE[APB_ADDR_WIDTH-1:0]); + // assign hit_CPTRA_SECURITY_STATE = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_SECURITY_STATE[AXI_ADDR_WIDTH-1:0]); // assign bus_CPTRA_SECURITY_STATE = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_SECURITY_STATE}}; - assign hit_CPTRA_MBOX_VALID_PAUSER[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[0][18-1:0]); - assign bus_CPTRA_MBOX_VALID_PAUSER[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[0]}}; + assign hit_CPTRA_MBOX_VALID_AXI_ID[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[0][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_ID[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[0]}}; - assign hit_CPTRA_MBOX_VALID_PAUSER[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[1][18-1:0]); - assign bus_CPTRA_MBOX_VALID_PAUSER[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[1]}}; + assign hit_CPTRA_MBOX_VALID_AXI_ID[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[1][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_ID[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[1]}}; - assign hit_CPTRA_MBOX_VALID_PAUSER[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[2][18-1:0]); - assign bus_CPTRA_MBOX_VALID_PAUSER[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[2]}}; + assign hit_CPTRA_MBOX_VALID_AXI_ID[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[2][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_ID[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[2]}}; - assign hit_CPTRA_MBOX_VALID_PAUSER[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[3][18-1:0]); - assign bus_CPTRA_MBOX_VALID_PAUSER[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[3]}}; + assign hit_CPTRA_MBOX_VALID_AXI_ID[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[3][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_ID[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[3]}}; - assign hit_CPTRA_MBOX_VALID_PAUSER[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[4][18-1:0]); - assign bus_CPTRA_MBOX_VALID_PAUSER[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[4]}}; + assign hit_CPTRA_MBOX_VALID_AXI_ID[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[4][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_ID[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[4]}}; - assign hit_CPTRA_MBOX_PAUSER_LOCK[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[0][18-1:0]); - assign bus_CPTRA_MBOX_PAUSER_LOCK[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[0]}}; + assign hit_CPTRA_MBOX_AXI_ID_LOCK[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[0][18-1:0]); + assign bus_CPTRA_MBOX_AXI_ID_LOCK[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[0]}}; - assign hit_CPTRA_MBOX_PAUSER_LOCK[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[1][18-1:0]); - assign bus_CPTRA_MBOX_PAUSER_LOCK[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[1]}}; + assign hit_CPTRA_MBOX_AXI_ID_LOCK[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[1][18-1:0]); + assign bus_CPTRA_MBOX_AXI_ID_LOCK[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[1]}}; - assign hit_CPTRA_MBOX_PAUSER_LOCK[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[2][18-1:0]); - assign bus_CPTRA_MBOX_PAUSER_LOCK[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[2]}}; + assign hit_CPTRA_MBOX_AXI_ID_LOCK[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[2][18-1:0]); + assign bus_CPTRA_MBOX_AXI_ID_LOCK[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[2]}}; - assign hit_CPTRA_MBOX_PAUSER_LOCK[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[3][18-1:0]); - assign bus_CPTRA_MBOX_PAUSER_LOCK[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[3]}}; + assign hit_CPTRA_MBOX_AXI_ID_LOCK[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[3][18-1:0]); + assign bus_CPTRA_MBOX_AXI_ID_LOCK[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[3]}}; - assign hit_CPTRA_MBOX_PAUSER_LOCK[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[4][18-1:0]); - assign bus_CPTRA_MBOX_PAUSER_LOCK[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[4]}}; + assign hit_CPTRA_MBOX_AXI_ID_LOCK[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[4][18-1:0]); + assign bus_CPTRA_MBOX_AXI_ID_LOCK[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[4]}}; - assign hit_CPTRA_TRNG_VALID_PAUSER = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_VALID_PAUSER[APB_ADDR_WIDTH-1:0]); - assign bus_CPTRA_TRNG_VALID_PAUSER = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_VALID_PAUSER}}; + assign hit_CPTRA_TRNG_VALID_AXI_ID = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_VALID_AXI_ID[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_TRNG_VALID_AXI_ID = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_VALID_AXI_ID}}; - assign hit_CPTRA_TRNG_PAUSER_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_PAUSER_LOCK[APB_ADDR_WIDTH-1:0]); - assign bus_CPTRA_TRNG_PAUSER_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_PAUSER_LOCK}}; + assign hit_CPTRA_TRNG_AXI_ID_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_AXI_ID_LOCK[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_TRNG_AXI_ID_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_AXI_ID_LOCK}}; assign hit_CPTRA_TRNG_DATA[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[0][18-1:0]); assign bus_CPTRA_TRNG_DATA[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[0]}}; @@ -1013,25 +1040,25 @@ interface soc_ifc_cov_if assign hit_CPTRA_TRNG_DATA[11] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[11][18-1:0]); assign bus_CPTRA_TRNG_DATA[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[11]}}; - assign hit_CPTRA_TRNG_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_CTRL[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_TRNG_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_CTRL[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_TRNG_CTRL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_CTRL}}; - assign hit_CPTRA_TRNG_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_STATUS[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_TRNG_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_STATUS[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_TRNG_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_STATUS}}; - assign hit_CPTRA_FUSE_WR_DONE = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_WR_DONE[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_FUSE_WR_DONE = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_WR_DONE[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_FUSE_WR_DONE = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_WR_DONE}}; - assign hit_CPTRA_TIMER_CONFIG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TIMER_CONFIG[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_TIMER_CONFIG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TIMER_CONFIG[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_TIMER_CONFIG = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TIMER_CONFIG}}; - assign hit_CPTRA_BOOTFSM_GO = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_BOOTFSM_GO[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_BOOTFSM_GO = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_BOOTFSM_GO[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_BOOTFSM_GO = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_BOOTFSM_GO}}; - assign hit_CPTRA_DBG_MANUF_SERVICE_REG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_DBG_MANUF_SERVICE_REG[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_DBG_MANUF_SERVICE_REG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_DBG_MANUF_SERVICE_REG[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_DBG_MANUF_SERVICE_REG = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_DBG_MANUF_SERVICE_REG}}; - assign hit_CPTRA_CLK_GATING_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_CLK_GATING_EN[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_CLK_GATING_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_CLK_GATING_EN[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_CLK_GATING_EN = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_CLK_GATING_EN}}; assign hit_CPTRA_GENERIC_INPUT_WIRES[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_GENERIC_INPUT_WIRES[0][18-1:0]); @@ -1046,7 +1073,7 @@ interface soc_ifc_cov_if assign hit_CPTRA_GENERIC_OUTPUT_WIRES[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_GENERIC_OUTPUT_WIRES[1][18-1:0]); assign bus_CPTRA_GENERIC_OUTPUT_WIRES[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_GENERIC_OUTPUT_WIRES[1]}}; - // assign hit_CPTRA_HW_REV_ID = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_REV_ID[APB_ADDR_WIDTH-1:0]); + // assign hit_CPTRA_HW_REV_ID = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_REV_ID[AXI_ADDR_WIDTH-1:0]); // assign bus_CPTRA_HW_REV_ID = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_REV_ID}}; assign hit_CPTRA_FW_REV_ID[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_REV_ID[0][18-1:0]); @@ -1055,13 +1082,13 @@ interface soc_ifc_cov_if assign hit_CPTRA_FW_REV_ID[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_REV_ID[1][18-1:0]); assign bus_CPTRA_FW_REV_ID[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_REV_ID[1]}}; - // assign hit_CPTRA_HW_CONFIG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_CONFIG[APB_ADDR_WIDTH-1:0]); + // assign hit_CPTRA_HW_CONFIG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_CONFIG[AXI_ADDR_WIDTH-1:0]); // assign bus_CPTRA_HW_CONFIG = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_CONFIG}}; - assign hit_CPTRA_WDT_TIMER1_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_EN[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_WDT_TIMER1_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_EN[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_WDT_TIMER1_EN = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER1_EN}}; - assign hit_CPTRA_WDT_TIMER1_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_CTRL[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_WDT_TIMER1_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_CTRL[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_WDT_TIMER1_CTRL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER1_CTRL}}; assign hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0][18-1:0]); @@ -1070,10 +1097,10 @@ interface soc_ifc_cov_if assign hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1][18-1:0]); assign bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1]}}; - assign hit_CPTRA_WDT_TIMER2_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_EN[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_WDT_TIMER2_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_EN[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_WDT_TIMER2_EN = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER2_EN}}; - assign hit_CPTRA_WDT_TIMER2_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_CTRL[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_WDT_TIMER2_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_CTRL[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_WDT_TIMER2_CTRL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER2_CTRL}}; assign hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0][18-1:0]); @@ -1082,14 +1109,14 @@ interface soc_ifc_cov_if assign hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1][18-1:0]); assign bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1]}}; - assign hit_CPTRA_WDT_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_STATUS[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_WDT_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_STATUS[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_WDT_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_STATUS}}; - assign hit_CPTRA_FUSE_VALID_PAUSER = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_VALID_PAUSER[APB_ADDR_WIDTH-1:0]); - assign bus_CPTRA_FUSE_VALID_PAUSER = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_VALID_PAUSER}}; + assign hit_CPTRA_FUSE_VALID_AXI_ID = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_VALID_AXI_ID[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_FUSE_VALID_AXI_ID = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_VALID_AXI_ID}}; - assign hit_CPTRA_FUSE_PAUSER_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_PAUSER_LOCK[APB_ADDR_WIDTH-1:0]); - assign bus_CPTRA_FUSE_PAUSER_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_PAUSER_LOCK}}; + assign hit_CPTRA_FUSE_AXI_ID_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_AXI_ID_LOCK[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_FUSE_AXI_ID_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_AXI_ID_LOCK}}; assign hit_CPTRA_WDT_CFG[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_CFG[0][18-1:0]); assign bus_CPTRA_WDT_CFG[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_CFG[0]}}; @@ -1097,10 +1124,10 @@ interface soc_ifc_cov_if assign hit_CPTRA_WDT_CFG[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_CFG[1][18-1:0]); assign bus_CPTRA_WDT_CFG[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_CFG[1]}}; - assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_0 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_0[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_0 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_0[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_iTRNG_ENTROPY_CONFIG_0 = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_iTRNG_ENTROPY_CONFIG_0}}; - assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_1 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_1[APB_ADDR_WIDTH-1:0]); + assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_1 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_1[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_iTRNG_ENTROPY_CONFIG_1 = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_iTRNG_ENTROPY_CONFIG_1}}; assign hit_CPTRA_RSVD_REG[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RSVD_REG[0][18-1:0]); @@ -1205,7 +1232,7 @@ interface soc_ifc_cov_if assign hit_fuse_key_manifest_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[11][18-1:0]); assign bus_fuse_key_manifest_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[11]}}; - assign hit_fuse_key_manifest_pk_hash_mask = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[APB_ADDR_WIDTH-1:0]); + assign hit_fuse_key_manifest_pk_hash_mask = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_key_manifest_pk_hash_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask}}; assign hit_fuse_owner_pk_hash[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[0][18-1:0]); @@ -1244,7 +1271,7 @@ interface soc_ifc_cov_if assign hit_fuse_owner_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[11][18-1:0]); assign bus_fuse_owner_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[11]}}; - assign hit_fuse_fmc_key_manifest_svn = (soc_ifc_reg_req_data.addr == full_addr_fuse_fmc_key_manifest_svn[APB_ADDR_WIDTH-1:0]); + assign hit_fuse_fmc_key_manifest_svn = (soc_ifc_reg_req_data.addr == full_addr_fuse_fmc_key_manifest_svn[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_fmc_key_manifest_svn = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_fmc_key_manifest_svn}}; assign hit_fuse_runtime_svn[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_runtime_svn[0][18-1:0]); @@ -1259,7 +1286,7 @@ interface soc_ifc_cov_if assign hit_fuse_runtime_svn[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_runtime_svn[3][18-1:0]); assign bus_fuse_runtime_svn[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_runtime_svn[3]}}; - assign hit_fuse_anti_rollback_disable = (soc_ifc_reg_req_data.addr == full_addr_fuse_anti_rollback_disable[APB_ADDR_WIDTH-1:0]); + assign hit_fuse_anti_rollback_disable = (soc_ifc_reg_req_data.addr == full_addr_fuse_anti_rollback_disable[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_anti_rollback_disable = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_anti_rollback_disable}}; assign hit_fuse_idevid_cert_attr[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[0][18-1:0]); @@ -1346,16 +1373,16 @@ interface soc_ifc_cov_if assign hit_fuse_idevid_manuf_hsm_id[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_manuf_hsm_id[3][18-1:0]); assign bus_fuse_idevid_manuf_hsm_id[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_manuf_hsm_id[3]}}; - assign hit_fuse_life_cycle = (soc_ifc_reg_req_data.addr == full_addr_fuse_life_cycle[APB_ADDR_WIDTH-1:0]); + assign hit_fuse_life_cycle = (soc_ifc_reg_req_data.addr == full_addr_fuse_life_cycle[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_life_cycle = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_life_cycle}}; - assign hit_fuse_lms_verify = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_verify[APB_ADDR_WIDTH-1:0]); + assign hit_fuse_lms_verify = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_verify[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_lms_verify = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_verify}}; - assign hit_fuse_lms_revocation = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_revocation[APB_ADDR_WIDTH-1:0]); + assign hit_fuse_lms_revocation = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_revocation[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_lms_revocation = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_revocation}}; - assign hit_fuse_soc_stepping_id = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_stepping_id[APB_ADDR_WIDTH-1:0]); + assign hit_fuse_soc_stepping_id = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_stepping_id[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_soc_stepping_id = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_stepping_id}}; assign hit_internal_obf_key[0] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[0][18-1:0]); @@ -1382,153 +1409,153 @@ interface soc_ifc_cov_if assign hit_internal_obf_key[7] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[7][18-1:0]); assign bus_internal_obf_key[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[7]}}; - assign hit_internal_iccm_lock = (soc_ifc_reg_req_data.addr == full_addr_internal_iccm_lock[APB_ADDR_WIDTH-1:0]); + assign hit_internal_iccm_lock = (soc_ifc_reg_req_data.addr == full_addr_internal_iccm_lock[AXI_ADDR_WIDTH-1:0]); assign bus_internal_iccm_lock = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_iccm_lock}}; - assign hit_internal_fw_update_reset = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_update_reset[APB_ADDR_WIDTH-1:0]); + assign hit_internal_fw_update_reset = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_update_reset[AXI_ADDR_WIDTH-1:0]); assign bus_internal_fw_update_reset = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_update_reset}}; - assign hit_internal_fw_update_reset_wait_cycles = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_update_reset_wait_cycles[APB_ADDR_WIDTH-1:0]); + assign hit_internal_fw_update_reset_wait_cycles = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_update_reset_wait_cycles[AXI_ADDR_WIDTH-1:0]); assign bus_internal_fw_update_reset_wait_cycles = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_update_reset_wait_cycles}}; - assign hit_internal_nmi_vector = (soc_ifc_reg_req_data.addr == full_addr_internal_nmi_vector[APB_ADDR_WIDTH-1:0]); + assign hit_internal_nmi_vector = (soc_ifc_reg_req_data.addr == full_addr_internal_nmi_vector[AXI_ADDR_WIDTH-1:0]); assign bus_internal_nmi_vector = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_nmi_vector}}; - assign hit_internal_hw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_fatal_mask[APB_ADDR_WIDTH-1:0]); + assign hit_internal_hw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_fatal_mask[AXI_ADDR_WIDTH-1:0]); assign bus_internal_hw_error_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_hw_error_fatal_mask}}; - assign hit_internal_hw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_non_fatal_mask[APB_ADDR_WIDTH-1:0]); + assign hit_internal_hw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_non_fatal_mask[AXI_ADDR_WIDTH-1:0]); assign bus_internal_hw_error_non_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_hw_error_non_fatal_mask}}; - assign hit_internal_fw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_fatal_mask[APB_ADDR_WIDTH-1:0]); + assign hit_internal_fw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_fatal_mask[AXI_ADDR_WIDTH-1:0]); assign bus_internal_fw_error_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_error_fatal_mask}}; - assign hit_internal_fw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_non_fatal_mask[APB_ADDR_WIDTH-1:0]); + assign hit_internal_fw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_non_fatal_mask[AXI_ADDR_WIDTH-1:0]); assign bus_internal_fw_error_non_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_error_non_fatal_mask}}; - assign hit_internal_rv_mtime_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_l[APB_ADDR_WIDTH-1:0]); + assign hit_internal_rv_mtime_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_l[AXI_ADDR_WIDTH-1:0]); assign bus_internal_rv_mtime_l = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtime_l}}; - assign hit_internal_rv_mtime_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_h[APB_ADDR_WIDTH-1:0]); + assign hit_internal_rv_mtime_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_h[AXI_ADDR_WIDTH-1:0]); assign bus_internal_rv_mtime_h = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtime_h}}; - assign hit_internal_rv_mtimecmp_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_l[APB_ADDR_WIDTH-1:0]); + assign hit_internal_rv_mtimecmp_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_l[AXI_ADDR_WIDTH-1:0]); assign bus_internal_rv_mtimecmp_l = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtimecmp_l}}; - assign hit_internal_rv_mtimecmp_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_h[APB_ADDR_WIDTH-1:0]); + assign hit_internal_rv_mtimecmp_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_h[AXI_ADDR_WIDTH-1:0]); assign bus_internal_rv_mtimecmp_h = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtimecmp_h}}; - assign hit_intr_brf_global_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_global_intr_en_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_global_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_global_intr_en_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_global_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_global_intr_en_r}}; - assign hit_intr_brf_error_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_en_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_en_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_intr_en_r}}; - assign hit_intr_brf_notif_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_en_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_en_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_intr_en_r}}; - assign hit_intr_brf_error_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_global_intr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_global_intr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_global_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_global_intr_r}}; - assign hit_intr_brf_notif_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_global_intr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_global_intr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_global_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_global_intr_r}}; - assign hit_intr_brf_error_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_internal_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_r}}; - assign hit_intr_brf_notif_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_internal_intr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_internal_intr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_internal_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_internal_intr_r}}; - assign hit_intr_brf_error_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_trig_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_trig_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_intr_trig_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_intr_trig_r}}; - assign hit_intr_brf_notif_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_trig_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_trig_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_intr_trig_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_intr_trig_r}}; - assign hit_intr_brf_error_internal_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_internal_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_internal_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_count_r}}; - assign hit_intr_brf_error_inv_dev_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_inv_dev_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_inv_dev_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_inv_dev_intr_count_r}}; - assign hit_intr_brf_error_cmd_fail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_cmd_fail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_cmd_fail_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_cmd_fail_intr_count_r}}; - assign hit_intr_brf_error_bad_fuse_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_bad_fuse_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_bad_fuse_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_bad_fuse_intr_count_r}}; - assign hit_intr_brf_error_iccm_blocked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_iccm_blocked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_iccm_blocked_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_iccm_blocked_intr_count_r}}; - assign hit_intr_brf_error_mbox_ecc_unc_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_mbox_ecc_unc_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_mbox_ecc_unc_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_mbox_ecc_unc_intr_count_r}}; - assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_wdt_timer1_timeout_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer1_timeout_intr_count_r}}; - assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_wdt_timer2_timeout_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer2_timeout_intr_count_r}}; - assign hit_intr_brf_notif_cmd_avail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_cmd_avail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_cmd_avail_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_cmd_avail_intr_count_r}}; - assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_mbox_ecc_cor_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_mbox_ecc_cor_intr_count_r}}; - assign hit_intr_brf_notif_debug_locked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_debug_locked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_debug_locked_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_debug_locked_intr_count_r}}; - assign hit_intr_brf_notif_scan_mode_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_scan_mode_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_scan_mode_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_scan_mode_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_scan_mode_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_scan_mode_intr_count_r}}; - assign hit_intr_brf_notif_soc_req_lock_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_soc_req_lock_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_soc_req_lock_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_soc_req_lock_intr_count_r}}; - assign hit_intr_brf_notif_gen_in_toggle_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_gen_in_toggle_intr_count_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_gen_in_toggle_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_gen_in_toggle_intr_count_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_gen_in_toggle_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_gen_in_toggle_intr_count_r}}; - assign hit_intr_brf_error_internal_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_internal_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_internal_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_count_incr_r}}; - assign hit_intr_brf_error_inv_dev_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_inv_dev_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_inv_dev_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_inv_dev_intr_count_incr_r}}; - assign hit_intr_brf_error_cmd_fail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_cmd_fail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_cmd_fail_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_cmd_fail_intr_count_incr_r}}; - assign hit_intr_brf_error_bad_fuse_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_bad_fuse_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_bad_fuse_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_bad_fuse_intr_count_incr_r}}; - assign hit_intr_brf_error_iccm_blocked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_iccm_blocked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_iccm_blocked_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_iccm_blocked_intr_count_incr_r}}; - assign hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r}}; - assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r}}; - assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r}}; - assign hit_intr_brf_notif_cmd_avail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_cmd_avail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_cmd_avail_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_cmd_avail_intr_count_incr_r}}; - assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r}}; - assign hit_intr_brf_notif_debug_locked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_debug_locked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_debug_locked_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_debug_locked_intr_count_incr_r}}; - assign hit_intr_brf_notif_soc_req_lock_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_incr_r[APB_ADDR_WIDTH-1:0]); + assign hit_intr_brf_notif_soc_req_lock_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_incr_r[AXI_ADDR_WIDTH-1:0]); assign bus_intr_brf_notif_soc_req_lock_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_soc_req_lock_intr_count_incr_r}}; // ----------------------- COVERGROUP CPTRA_HW_ERROR_FATAL ----------------------- covergroup soc_ifc_CPTRA_HW_ERROR_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_HW_ERROR_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_ERROR_FATAL; bus_CPTRA_HW_ERROR_FATAL_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1536,8 +1563,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_HW_ERROR_NON_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_HW_ERROR_NON_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_ERROR_NON_FATAL; bus_CPTRA_HW_ERROR_NON_FATAL_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1545,8 +1572,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_FW_ERROR_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_FW_ERROR_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_ERROR_FATAL; bus_CPTRA_FW_ERROR_FATAL_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1554,8 +1581,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_FW_ERROR_NON_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_FW_ERROR_NON_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_ERROR_NON_FATAL; bus_CPTRA_FW_ERROR_NON_FATAL_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1563,8 +1590,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_HW_ERROR_ENC_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_HW_ERROR_ENC_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_ERROR_ENC; bus_CPTRA_HW_ERROR_ENC_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1572,8 +1599,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_FW_ERROR_ENC_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_FW_ERROR_ENC_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_ERROR_ENC; bus_CPTRA_FW_ERROR_ENC_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1581,43 +1608,43 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_FW_EXTENDED_ERROR_INFO_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk); CPTRA_FW_EXTENDED_ERROR_INFO0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[0]; bus_CPTRA_FW_EXTENDED_ERROR_INFO0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_EXTENDED_ERROR_INFO1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[1]; bus_CPTRA_FW_EXTENDED_ERROR_INFO1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_EXTENDED_ERROR_INFO2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[2]; bus_CPTRA_FW_EXTENDED_ERROR_INFO2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_EXTENDED_ERROR_INFO3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[3]; bus_CPTRA_FW_EXTENDED_ERROR_INFO3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_EXTENDED_ERROR_INFO4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[4]; bus_CPTRA_FW_EXTENDED_ERROR_INFO4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_EXTENDED_ERROR_INFO5_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[5]; bus_CPTRA_FW_EXTENDED_ERROR_INFO5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_EXTENDED_ERROR_INFO6_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[6]; bus_CPTRA_FW_EXTENDED_ERROR_INFO6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_EXTENDED_ERROR_INFO7_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[7]; bus_CPTRA_FW_EXTENDED_ERROR_INFO7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1625,8 +1652,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_BOOT_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_BOOT_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_BOOT_STATUS; bus_CPTRA_BOOT_STATUS_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1634,8 +1661,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_FLOW_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_FLOW_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FLOW_STATUS; bus_CPTRA_FLOW_STATUS_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1643,8 +1670,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_RESET_REASON_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_RESET_REASON_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RESET_REASON; bus_CPTRA_RESET_REASON_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1652,84 +1679,84 @@ interface soc_ifc_cov_if // covergroup soc_ifc_CPTRA_SECURITY_STATE_cg (ref logic [3:0] bus_event) @(posedge clk); // CPTRA_SECURITY_STATE_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_SECURITY_STATE; // bus_CPTRA_SECURITY_STATE_cp : coverpoint bus_event { - // bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - // ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + // ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; // } // endgroup - // ----------------------- COVERGROUP CPTRA_MBOX_VALID_PAUSER [0:4] ----------------------- - covergroup soc_ifc_CPTRA_MBOX_VALID_PAUSER_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); - CPTRA_MBOX_VALID_PAUSER0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[0]; - bus_CPTRA_MBOX_VALID_PAUSER0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // ----------------------- COVERGROUP CPTRA_MBOX_VALID_AXI_ID [0:4] ----------------------- + covergroup soc_ifc_CPTRA_MBOX_VALID_AXI_ID_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); + CPTRA_MBOX_VALID_AXI_ID0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[0]; + bus_CPTRA_MBOX_VALID_AXI_ID0_cp : coverpoint bus_event[0] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_PAUSER1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[1]; - bus_CPTRA_MBOX_VALID_PAUSER1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_VALID_AXI_ID1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[1]; + bus_CPTRA_MBOX_VALID_AXI_ID1_cp : coverpoint bus_event[1] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_PAUSER2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[2]; - bus_CPTRA_MBOX_VALID_PAUSER2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_VALID_AXI_ID2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[2]; + bus_CPTRA_MBOX_VALID_AXI_ID2_cp : coverpoint bus_event[2] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_PAUSER3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[3]; - bus_CPTRA_MBOX_VALID_PAUSER3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_VALID_AXI_ID3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[3]; + bus_CPTRA_MBOX_VALID_AXI_ID3_cp : coverpoint bus_event[3] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_PAUSER4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[4]; - bus_CPTRA_MBOX_VALID_PAUSER4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_VALID_AXI_ID4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[4]; + bus_CPTRA_MBOX_VALID_AXI_ID4_cp : coverpoint bus_event[4] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_MBOX_PAUSER_LOCK [0:4] ----------------------- - covergroup soc_ifc_CPTRA_MBOX_PAUSER_LOCK_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); - CPTRA_MBOX_PAUSER_LOCK0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[0]; - bus_CPTRA_MBOX_PAUSER_LOCK0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // ----------------------- COVERGROUP CPTRA_MBOX_AXI_ID_LOCK [0:4] ----------------------- + covergroup soc_ifc_CPTRA_MBOX_AXI_ID_LOCK_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); + CPTRA_MBOX_AXI_ID_LOCK0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[0]; + bus_CPTRA_MBOX_AXI_ID_LOCK0_cp : coverpoint bus_event[0] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_PAUSER_LOCK1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[1]; - bus_CPTRA_MBOX_PAUSER_LOCK1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_AXI_ID_LOCK1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[1]; + bus_CPTRA_MBOX_AXI_ID_LOCK1_cp : coverpoint bus_event[1] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_PAUSER_LOCK2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[2]; - bus_CPTRA_MBOX_PAUSER_LOCK2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_AXI_ID_LOCK2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[2]; + bus_CPTRA_MBOX_AXI_ID_LOCK2_cp : coverpoint bus_event[2] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_PAUSER_LOCK3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[3]; - bus_CPTRA_MBOX_PAUSER_LOCK3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_AXI_ID_LOCK3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[3]; + bus_CPTRA_MBOX_AXI_ID_LOCK3_cp : coverpoint bus_event[3] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_PAUSER_LOCK4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[4]; - bus_CPTRA_MBOX_PAUSER_LOCK4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + CPTRA_MBOX_AXI_ID_LOCK4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[4]; + bus_CPTRA_MBOX_AXI_ID_LOCK4_cp : coverpoint bus_event[4] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_TRNG_VALID_PAUSER ----------------------- - covergroup soc_ifc_CPTRA_TRNG_VALID_PAUSER_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_TRNG_VALID_PAUSER_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_VALID_PAUSER; - bus_CPTRA_TRNG_VALID_PAUSER_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // ----------------------- COVERGROUP CPTRA_TRNG_VALID_AXI_ID ----------------------- + covergroup soc_ifc_CPTRA_TRNG_VALID_AXI_ID_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_TRNG_VALID_AXI_ID_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_VALID_AXI_ID; + bus_CPTRA_TRNG_VALID_AXI_ID_cp : coverpoint bus_event { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_TRNG_PAUSER_LOCK ----------------------- - covergroup soc_ifc_CPTRA_TRNG_PAUSER_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_TRNG_PAUSER_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_PAUSER_LOCK; - bus_CPTRA_TRNG_PAUSER_LOCK_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // ----------------------- COVERGROUP CPTRA_TRNG_AXI_ID_LOCK ----------------------- + covergroup soc_ifc_CPTRA_TRNG_AXI_ID_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_TRNG_AXI_ID_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_AXI_ID_LOCK; + bus_CPTRA_TRNG_AXI_ID_LOCK_cp : coverpoint bus_event { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1737,63 +1764,63 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_TRNG_DATA_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk); CPTRA_TRNG_DATA0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[0]; bus_CPTRA_TRNG_DATA0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[1]; bus_CPTRA_TRNG_DATA1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[2]; bus_CPTRA_TRNG_DATA2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[3]; bus_CPTRA_TRNG_DATA3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[4]; bus_CPTRA_TRNG_DATA4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA5_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[5]; bus_CPTRA_TRNG_DATA5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA6_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[6]; bus_CPTRA_TRNG_DATA6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA7_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[7]; bus_CPTRA_TRNG_DATA7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA8_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[8]; bus_CPTRA_TRNG_DATA8_cp : coverpoint bus_event[8] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA9_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[9]; bus_CPTRA_TRNG_DATA9_cp : coverpoint bus_event[9] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA10_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[10]; bus_CPTRA_TRNG_DATA10_cp : coverpoint bus_event[10] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_TRNG_DATA11_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[11]; bus_CPTRA_TRNG_DATA11_cp : coverpoint bus_event[11] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1801,8 +1828,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_TRNG_CTRL_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_TRNG_CTRL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_CTRL; bus_CPTRA_TRNG_CTRL_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1810,8 +1837,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_TRNG_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_TRNG_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_STATUS; bus_CPTRA_TRNG_STATUS_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1819,8 +1846,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_FUSE_WR_DONE_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_FUSE_WR_DONE_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_WR_DONE; bus_CPTRA_FUSE_WR_DONE_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1828,8 +1855,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_TIMER_CONFIG_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_TIMER_CONFIG_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TIMER_CONFIG; bus_CPTRA_TIMER_CONFIG_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1837,8 +1864,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_BOOTFSM_GO_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_BOOTFSM_GO_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_BOOTFSM_GO; bus_CPTRA_BOOTFSM_GO_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1846,8 +1873,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_DBG_MANUF_SERVICE_REG_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_DBG_MANUF_SERVICE_REG_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_DBG_MANUF_SERVICE_REG; bus_CPTRA_DBG_MANUF_SERVICE_REG_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1855,8 +1882,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_CLK_GATING_EN_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_CLK_GATING_EN_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_CLK_GATING_EN; bus_CPTRA_CLK_GATING_EN_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1864,13 +1891,13 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_GENERIC_INPUT_WIRES_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk); CPTRA_GENERIC_INPUT_WIRES0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_INPUT_WIRES[0]; bus_CPTRA_GENERIC_INPUT_WIRES0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_GENERIC_INPUT_WIRES1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_INPUT_WIRES[1]; bus_CPTRA_GENERIC_INPUT_WIRES1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1878,13 +1905,13 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_GENERIC_OUTPUT_WIRES_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk); CPTRA_GENERIC_OUTPUT_WIRES0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[0]; bus_CPTRA_GENERIC_OUTPUT_WIRES0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_GENERIC_OUTPUT_WIRES1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[1]; bus_CPTRA_GENERIC_OUTPUT_WIRES1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1892,8 +1919,8 @@ interface soc_ifc_cov_if // covergroup soc_ifc_CPTRA_HW_REV_ID_cg (ref logic [3:0] bus_event) @(posedge clk); // CPTRA_HW_REV_ID_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_REV_ID; // bus_CPTRA_HW_REV_ID_cp : coverpoint bus_event { - // bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - // ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + // ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; // } // endgroup @@ -1901,13 +1928,13 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_FW_REV_ID_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk); CPTRA_FW_REV_ID0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_REV_ID[0]; bus_CPTRA_FW_REV_ID0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_FW_REV_ID1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_REV_ID[1]; bus_CPTRA_FW_REV_ID1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1915,8 +1942,8 @@ interface soc_ifc_cov_if // covergroup soc_ifc_CPTRA_HW_CONFIG_cg (ref logic [3:0] bus_event) @(posedge clk); // CPTRA_HW_CONFIG_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_CONFIG; // bus_CPTRA_HW_CONFIG_cp : coverpoint bus_event { - // bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - // ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + // ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; // } // endgroup @@ -1924,8 +1951,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_TIMER1_EN_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_WDT_TIMER1_EN_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_EN; bus_CPTRA_WDT_TIMER1_EN_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1933,8 +1960,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_TIMER1_CTRL_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_WDT_TIMER1_CTRL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_CTRL; bus_CPTRA_WDT_TIMER1_CTRL_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1942,13 +1969,13 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk); CPTRA_WDT_TIMER1_TIMEOUT_PERIOD0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0]; bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_WDT_TIMER1_TIMEOUT_PERIOD1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1]; bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1956,8 +1983,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_TIMER2_EN_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_WDT_TIMER2_EN_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_EN; bus_CPTRA_WDT_TIMER2_EN_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1965,8 +1992,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_TIMER2_CTRL_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_WDT_TIMER2_CTRL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_CTRL; bus_CPTRA_WDT_TIMER2_CTRL_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1974,13 +2001,13 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk); CPTRA_WDT_TIMER2_TIMEOUT_PERIOD0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0]; bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_WDT_TIMER2_TIMEOUT_PERIOD1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1]; bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -1988,26 +2015,26 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_WDT_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_STATUS; bus_CPTRA_WDT_STATUS_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_FUSE_VALID_PAUSER ----------------------- - covergroup soc_ifc_CPTRA_FUSE_VALID_PAUSER_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_FUSE_VALID_PAUSER_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_VALID_PAUSER; - bus_CPTRA_FUSE_VALID_PAUSER_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // ----------------------- COVERGROUP CPTRA_FUSE_VALID_AXI_ID ----------------------- + covergroup soc_ifc_CPTRA_FUSE_VALID_AXI_ID_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_FUSE_VALID_AXI_ID_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_VALID_AXI_ID; + bus_CPTRA_FUSE_VALID_AXI_ID_cp : coverpoint bus_event { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_FUSE_PAUSER_LOCK ----------------------- - covergroup soc_ifc_CPTRA_FUSE_PAUSER_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_FUSE_PAUSER_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_PAUSER_LOCK; - bus_CPTRA_FUSE_PAUSER_LOCK_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + // ----------------------- COVERGROUP CPTRA_FUSE_AXI_ID_LOCK ----------------------- + covergroup soc_ifc_CPTRA_FUSE_AXI_ID_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_FUSE_AXI_ID_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_AXI_ID_LOCK; + bus_CPTRA_FUSE_AXI_ID_LOCK_cp : coverpoint bus_event { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2015,13 +2042,13 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_WDT_CFG_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk); CPTRA_WDT_CFG0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_CFG[0]; bus_CPTRA_WDT_CFG0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_WDT_CFG1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_CFG[1]; bus_CPTRA_WDT_CFG1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2029,8 +2056,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_iTRNG_ENTROPY_CONFIG_0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0; bus_CPTRA_iTRNG_ENTROPY_CONFIG_0_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2038,8 +2065,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg (ref logic [3:0] bus_event) @(posedge clk); CPTRA_iTRNG_ENTROPY_CONFIG_1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1; bus_CPTRA_iTRNG_ENTROPY_CONFIG_1_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2047,13 +2074,13 @@ interface soc_ifc_cov_if covergroup soc_ifc_CPTRA_RSVD_REG_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk); CPTRA_RSVD_REG0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RSVD_REG[0]; bus_CPTRA_RSVD_REG0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } CPTRA_RSVD_REG1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RSVD_REG[1]; bus_CPTRA_RSVD_REG1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2061,63 +2088,63 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_uds_seed_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk); fuse_uds_seed0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[0]; bus_fuse_uds_seed0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[1]; bus_fuse_uds_seed1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[2]; bus_fuse_uds_seed2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[3]; bus_fuse_uds_seed3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[4]; bus_fuse_uds_seed4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[5]; bus_fuse_uds_seed5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[6]; bus_fuse_uds_seed6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[7]; bus_fuse_uds_seed7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[8]; bus_fuse_uds_seed8_cp : coverpoint bus_event[8] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[9]; bus_fuse_uds_seed9_cp : coverpoint bus_event[9] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[10]; bus_fuse_uds_seed10_cp : coverpoint bus_event[10] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_uds_seed11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[11]; bus_fuse_uds_seed11_cp : coverpoint bus_event[11] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2125,43 +2152,43 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_field_entropy_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk); fuse_field_entropy0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[0]; bus_fuse_field_entropy0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_field_entropy1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[1]; bus_fuse_field_entropy1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_field_entropy2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[2]; bus_fuse_field_entropy2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_field_entropy3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[3]; bus_fuse_field_entropy3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_field_entropy4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[4]; bus_fuse_field_entropy4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_field_entropy5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[5]; bus_fuse_field_entropy5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_field_entropy6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[6]; bus_fuse_field_entropy6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_field_entropy7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[7]; bus_fuse_field_entropy7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2169,63 +2196,63 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_key_manifest_pk_hash_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk); fuse_key_manifest_pk_hash0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[0]; bus_fuse_key_manifest_pk_hash0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[1]; bus_fuse_key_manifest_pk_hash1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[2]; bus_fuse_key_manifest_pk_hash2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[3]; bus_fuse_key_manifest_pk_hash3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[4]; bus_fuse_key_manifest_pk_hash4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[5]; bus_fuse_key_manifest_pk_hash5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[6]; bus_fuse_key_manifest_pk_hash6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[7]; bus_fuse_key_manifest_pk_hash7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[8]; bus_fuse_key_manifest_pk_hash8_cp : coverpoint bus_event[8] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[9]; bus_fuse_key_manifest_pk_hash9_cp : coverpoint bus_event[9] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[10]; bus_fuse_key_manifest_pk_hash10_cp : coverpoint bus_event[10] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_key_manifest_pk_hash11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[11]; bus_fuse_key_manifest_pk_hash11_cp : coverpoint bus_event[11] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2233,8 +2260,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_key_manifest_pk_hash_mask_cg (ref logic [3:0] bus_event) @(posedge clk); fuse_key_manifest_pk_hash_mask_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask; bus_fuse_key_manifest_pk_hash_mask_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2242,63 +2269,63 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_owner_pk_hash_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk); fuse_owner_pk_hash0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[0]; bus_fuse_owner_pk_hash0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[1]; bus_fuse_owner_pk_hash1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[2]; bus_fuse_owner_pk_hash2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[3]; bus_fuse_owner_pk_hash3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[4]; bus_fuse_owner_pk_hash4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[5]; bus_fuse_owner_pk_hash5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[6]; bus_fuse_owner_pk_hash6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[7]; bus_fuse_owner_pk_hash7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[8]; bus_fuse_owner_pk_hash8_cp : coverpoint bus_event[8] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[9]; bus_fuse_owner_pk_hash9_cp : coverpoint bus_event[9] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[10]; bus_fuse_owner_pk_hash10_cp : coverpoint bus_event[10] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_owner_pk_hash11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[11]; bus_fuse_owner_pk_hash11_cp : coverpoint bus_event[11] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2306,8 +2333,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_fmc_key_manifest_svn_cg (ref logic [3:0] bus_event) @(posedge clk); fuse_fmc_key_manifest_svn_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_fmc_key_manifest_svn; bus_fuse_fmc_key_manifest_svn_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2315,23 +2342,23 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_runtime_svn_cg (ref logic [3:0] bus_event[0:3]) @(posedge clk); fuse_runtime_svn0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[0]; bus_fuse_runtime_svn0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_runtime_svn1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[1]; bus_fuse_runtime_svn1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_runtime_svn2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[2]; bus_fuse_runtime_svn2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_runtime_svn3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[3]; bus_fuse_runtime_svn3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2339,8 +2366,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_anti_rollback_disable_cg (ref logic [3:0] bus_event) @(posedge clk); fuse_anti_rollback_disable_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_anti_rollback_disable; bus_fuse_anti_rollback_disable_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2348,123 +2375,123 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_idevid_cert_attr_cg (ref logic [3:0] bus_event[0:23]) @(posedge clk); fuse_idevid_cert_attr0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[0]; bus_fuse_idevid_cert_attr0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[1]; bus_fuse_idevid_cert_attr1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[2]; bus_fuse_idevid_cert_attr2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[3]; bus_fuse_idevid_cert_attr3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[4]; bus_fuse_idevid_cert_attr4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[5]; bus_fuse_idevid_cert_attr5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[6]; bus_fuse_idevid_cert_attr6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[7]; bus_fuse_idevid_cert_attr7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[8]; bus_fuse_idevid_cert_attr8_cp : coverpoint bus_event[8] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[9]; bus_fuse_idevid_cert_attr9_cp : coverpoint bus_event[9] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[10]; bus_fuse_idevid_cert_attr10_cp : coverpoint bus_event[10] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[11]; bus_fuse_idevid_cert_attr11_cp : coverpoint bus_event[11] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr12_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[12]; bus_fuse_idevid_cert_attr12_cp : coverpoint bus_event[12] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr13_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[13]; bus_fuse_idevid_cert_attr13_cp : coverpoint bus_event[13] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr14_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[14]; bus_fuse_idevid_cert_attr14_cp : coverpoint bus_event[14] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr15_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[15]; bus_fuse_idevid_cert_attr15_cp : coverpoint bus_event[15] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr16_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[16]; bus_fuse_idevid_cert_attr16_cp : coverpoint bus_event[16] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr17_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[17]; bus_fuse_idevid_cert_attr17_cp : coverpoint bus_event[17] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr18_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[18]; bus_fuse_idevid_cert_attr18_cp : coverpoint bus_event[18] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr19_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[19]; bus_fuse_idevid_cert_attr19_cp : coverpoint bus_event[19] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr20_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[20]; bus_fuse_idevid_cert_attr20_cp : coverpoint bus_event[20] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr21_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[21]; bus_fuse_idevid_cert_attr21_cp : coverpoint bus_event[21] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr22_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[22]; bus_fuse_idevid_cert_attr22_cp : coverpoint bus_event[22] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_cert_attr23_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[23]; bus_fuse_idevid_cert_attr23_cp : coverpoint bus_event[23] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2472,23 +2499,23 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_idevid_manuf_hsm_id_cg (ref logic [3:0] bus_event[0:3]) @(posedge clk); fuse_idevid_manuf_hsm_id0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[0]; bus_fuse_idevid_manuf_hsm_id0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_manuf_hsm_id1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[1]; bus_fuse_idevid_manuf_hsm_id1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_manuf_hsm_id2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[2]; bus_fuse_idevid_manuf_hsm_id2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } fuse_idevid_manuf_hsm_id3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[3]; bus_fuse_idevid_manuf_hsm_id3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2496,8 +2523,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_life_cycle_cg (ref logic [3:0] bus_event) @(posedge clk); fuse_life_cycle_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_life_cycle; bus_fuse_life_cycle_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2505,8 +2532,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_lms_verify_cg (ref logic [3:0] bus_event) @(posedge clk); fuse_lms_verify_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_verify; bus_fuse_lms_verify_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2514,8 +2541,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_lms_revocation_cg (ref logic [3:0] bus_event) @(posedge clk); fuse_lms_revocation_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_revocation; bus_fuse_lms_revocation_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2523,8 +2550,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_fuse_soc_stepping_id_cg (ref logic [3:0] bus_event) @(posedge clk); fuse_soc_stepping_id_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_stepping_id; bus_fuse_soc_stepping_id_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2532,43 +2559,43 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_obf_key_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk); internal_obf_key0_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[0]; bus_internal_obf_key0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } internal_obf_key1_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[1]; bus_internal_obf_key1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } internal_obf_key2_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[2]; bus_internal_obf_key2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } internal_obf_key3_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[3]; bus_internal_obf_key3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } internal_obf_key4_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[4]; bus_internal_obf_key4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } internal_obf_key5_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[5]; bus_internal_obf_key5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } internal_obf_key6_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[6]; bus_internal_obf_key6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } internal_obf_key7_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[7]; bus_internal_obf_key7_cp : coverpoint bus_event[7] { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2576,8 +2603,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_iccm_lock_cg (ref logic [3:0] bus_event) @(posedge clk); internal_iccm_lock_cp : coverpoint i_soc_ifc_reg.field_storage.internal_iccm_lock; bus_internal_iccm_lock_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2585,8 +2612,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_fw_update_reset_cg (ref logic [3:0] bus_event) @(posedge clk); internal_fw_update_reset_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_update_reset; bus_internal_fw_update_reset_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2594,8 +2621,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_fw_update_reset_wait_cycles_cg (ref logic [3:0] bus_event) @(posedge clk); internal_fw_update_reset_wait_cycles_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_update_reset_wait_cycles; bus_internal_fw_update_reset_wait_cycles_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2603,8 +2630,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_nmi_vector_cg (ref logic [3:0] bus_event) @(posedge clk); internal_nmi_vector_cp : coverpoint i_soc_ifc_reg.field_storage.internal_nmi_vector; bus_internal_nmi_vector_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2612,8 +2639,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_hw_error_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk); internal_hw_error_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_hw_error_fatal_mask; bus_internal_hw_error_fatal_mask_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2621,8 +2648,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_hw_error_non_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk); internal_hw_error_non_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_hw_error_non_fatal_mask; bus_internal_hw_error_non_fatal_mask_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2630,8 +2657,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_fw_error_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk); internal_fw_error_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_error_fatal_mask; bus_internal_fw_error_fatal_mask_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2639,8 +2666,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_fw_error_non_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk); internal_fw_error_non_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_error_non_fatal_mask; bus_internal_fw_error_non_fatal_mask_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2648,8 +2675,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_rv_mtime_l_cg (ref logic [3:0] bus_event) @(posedge clk); internal_rv_mtime_l_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtime_l; bus_internal_rv_mtime_l_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2657,8 +2684,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_rv_mtime_h_cg (ref logic [3:0] bus_event) @(posedge clk); internal_rv_mtime_h_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtime_h; bus_internal_rv_mtime_h_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2666,8 +2693,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_rv_mtimecmp_l_cg (ref logic [3:0] bus_event) @(posedge clk); internal_rv_mtimecmp_l_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtimecmp_l; bus_internal_rv_mtimecmp_l_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2675,8 +2702,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_internal_rv_mtimecmp_h_cg (ref logic [3:0] bus_event) @(posedge clk); internal_rv_mtimecmp_h_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtimecmp_h; bus_internal_rv_mtimecmp_h_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2684,8 +2711,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_global_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_global_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.global_intr_en_r; bus_intr_brf_global_intr_en_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2693,8 +2720,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r; bus_intr_brf_error_intr_en_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2702,8 +2729,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r; bus_intr_brf_notif_intr_en_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2711,8 +2738,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_global_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_global_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_global_intr_r; bus_intr_brf_error_global_intr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2720,8 +2747,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_global_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_global_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_global_intr_r; bus_intr_brf_notif_global_intr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2729,8 +2756,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_internal_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_internal_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r; bus_intr_brf_error_internal_intr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2738,8 +2765,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_internal_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_internal_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r; bus_intr_brf_notif_internal_intr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2747,8 +2774,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_intr_trig_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_intr_trig_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r; bus_intr_brf_error_intr_trig_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2756,8 +2783,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_intr_trig_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_intr_trig_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r; bus_intr_brf_notif_intr_trig_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2765,8 +2792,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_internal_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_internal_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_r; bus_intr_brf_error_internal_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2774,8 +2801,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_inv_dev_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_inv_dev_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_r; bus_intr_brf_error_inv_dev_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2783,8 +2810,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_cmd_fail_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_cmd_fail_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_r; bus_intr_brf_error_cmd_fail_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2792,8 +2819,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_bad_fuse_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_bad_fuse_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_r; bus_intr_brf_error_bad_fuse_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2801,8 +2828,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_iccm_blocked_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_iccm_blocked_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_r; bus_intr_brf_error_iccm_blocked_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2810,8 +2837,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_mbox_ecc_unc_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r; bus_intr_brf_error_mbox_ecc_unc_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2819,8 +2846,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_wdt_timer1_timeout_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r; bus_intr_brf_error_wdt_timer1_timeout_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2828,8 +2855,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_wdt_timer2_timeout_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r; bus_intr_brf_error_wdt_timer2_timeout_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2837,8 +2864,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_cmd_avail_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_cmd_avail_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_r; bus_intr_brf_notif_cmd_avail_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2846,8 +2873,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_mbox_ecc_cor_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r; bus_intr_brf_notif_mbox_ecc_cor_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2855,8 +2882,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_debug_locked_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_debug_locked_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_r; bus_intr_brf_notif_debug_locked_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2864,8 +2891,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_scan_mode_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_scan_mode_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_scan_mode_intr_count_r; bus_intr_brf_notif_scan_mode_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2873,8 +2900,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_soc_req_lock_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_soc_req_lock_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r; bus_intr_brf_notif_soc_req_lock_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2882,8 +2909,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_gen_in_toggle_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_gen_in_toggle_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r; bus_intr_brf_notif_gen_in_toggle_intr_count_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2891,8 +2918,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_internal_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_internal_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_incr_r; bus_intr_brf_error_internal_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2900,8 +2927,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_inv_dev_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_inv_dev_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r; bus_intr_brf_error_inv_dev_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2909,8 +2936,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_cmd_fail_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_cmd_fail_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r; bus_intr_brf_error_cmd_fail_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2918,8 +2945,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_bad_fuse_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_bad_fuse_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r; bus_intr_brf_error_bad_fuse_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2927,8 +2954,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_iccm_blocked_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_iccm_blocked_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r; bus_intr_brf_error_iccm_blocked_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2936,8 +2963,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r; bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2945,8 +2972,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r; bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2954,8 +2981,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r; bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2963,8 +2990,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_cmd_avail_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_cmd_avail_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r; bus_intr_brf_notif_cmd_avail_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2972,8 +2999,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r; bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2981,8 +3008,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_debug_locked_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_debug_locked_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r; bus_intr_brf_notif_debug_locked_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -2990,8 +3017,8 @@ interface soc_ifc_cov_if covergroup soc_ifc_intr_brf_notif_soc_req_lock_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk); intr_brf_notif_soc_req_lock_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r; bus_intr_brf_notif_soc_req_lock_intr_count_incr_r_cp : coverpoint bus_event { - bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD); - ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)}; + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup @@ -3009,10 +3036,10 @@ interface soc_ifc_cov_if soc_ifc_CPTRA_FLOW_STATUS_cg CPTRA_FLOW_STATUS_cg = new(bus_CPTRA_FLOW_STATUS); soc_ifc_CPTRA_RESET_REASON_cg CPTRA_RESET_REASON_cg = new(bus_CPTRA_RESET_REASON); // soc_ifc_CPTRA_SECURITY_STATE_cg CPTRA_SECURITY_STATE_cg = new(bus_CPTRA_SECURITY_STATE); - soc_ifc_CPTRA_MBOX_VALID_PAUSER_cg CPTRA_MBOX_VALID_PAUSER_cg = new(bus_CPTRA_MBOX_VALID_PAUSER); - soc_ifc_CPTRA_MBOX_PAUSER_LOCK_cg CPTRA_MBOX_PAUSER_LOCK_cg = new(bus_CPTRA_MBOX_PAUSER_LOCK); - soc_ifc_CPTRA_TRNG_VALID_PAUSER_cg CPTRA_TRNG_VALID_PAUSER_cg = new(bus_CPTRA_TRNG_VALID_PAUSER); - soc_ifc_CPTRA_TRNG_PAUSER_LOCK_cg CPTRA_TRNG_PAUSER_LOCK_cg = new(bus_CPTRA_TRNG_PAUSER_LOCK); + soc_ifc_CPTRA_MBOX_VALID_AXI_ID_cg CPTRA_MBOX_VALID_AXI_ID_cg = new(bus_CPTRA_MBOX_VALID_AXI_ID); + soc_ifc_CPTRA_MBOX_AXI_ID_LOCK_cg CPTRA_MBOX_AXI_ID_LOCK_cg = new(bus_CPTRA_MBOX_AXI_ID_LOCK); + soc_ifc_CPTRA_TRNG_VALID_AXI_ID_cg CPTRA_TRNG_VALID_AXI_ID_cg = new(bus_CPTRA_TRNG_VALID_AXI_ID); + soc_ifc_CPTRA_TRNG_AXI_ID_LOCK_cg CPTRA_TRNG_AXI_ID_LOCK_cg = new(bus_CPTRA_TRNG_AXI_ID_LOCK); soc_ifc_CPTRA_TRNG_DATA_cg CPTRA_TRNG_DATA_cg = new(bus_CPTRA_TRNG_DATA); soc_ifc_CPTRA_TRNG_CTRL_cg CPTRA_TRNG_CTRL_cg = new(bus_CPTRA_TRNG_CTRL); soc_ifc_CPTRA_TRNG_STATUS_cg CPTRA_TRNG_STATUS_cg = new(bus_CPTRA_TRNG_STATUS); @@ -3033,8 +3060,8 @@ interface soc_ifc_cov_if soc_ifc_CPTRA_WDT_TIMER2_CTRL_cg CPTRA_WDT_TIMER2_CTRL_cg = new(bus_CPTRA_WDT_TIMER2_CTRL); soc_ifc_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg = new(bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD); soc_ifc_CPTRA_WDT_STATUS_cg CPTRA_WDT_STATUS_cg = new(bus_CPTRA_WDT_STATUS); - soc_ifc_CPTRA_FUSE_VALID_PAUSER_cg CPTRA_FUSE_VALID_PAUSER_cg = new(bus_CPTRA_FUSE_VALID_PAUSER); - soc_ifc_CPTRA_FUSE_PAUSER_LOCK_cg CPTRA_FUSE_PAUSER_LOCK_cg = new(bus_CPTRA_FUSE_PAUSER_LOCK); + soc_ifc_CPTRA_FUSE_VALID_AXI_ID_cg CPTRA_FUSE_VALID_AXI_ID_cg = new(bus_CPTRA_FUSE_VALID_AXI_ID); + soc_ifc_CPTRA_FUSE_AXI_ID_LOCK_cg CPTRA_FUSE_AXI_ID_LOCK_cg = new(bus_CPTRA_FUSE_AXI_ID_LOCK); soc_ifc_CPTRA_WDT_CFG_cg CPTRA_WDT_CFG_cg = new(bus_CPTRA_WDT_CFG); soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg CPTRA_iTRNG_ENTROPY_CONFIG_0_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_0); soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg CPTRA_iTRNG_ENTROPY_CONFIG_1_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_1); diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index a731f292d..fd04f3081 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -22,8 +22,8 @@ #define MBOX_CSR_MBOX_LOCK (0x0) #define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) #define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_USER (0x30020004) -#define MBOX_CSR_MBOX_USER (0x4) +#define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_ID (0x30020004) +#define MBOX_CSR_MBOX_ID (0x4) #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_CMD (0x30020008) #define MBOX_CSR_MBOX_CMD (0x8) #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DLEN (0x3002000c) @@ -59,8 +59,8 @@ #define SHA512_ACC_CSR_LOCK (0x0) #define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) #define SHA512_ACC_CSR_LOCK_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_USER (0x30021004) -#define SHA512_ACC_CSR_USER (0x4) +#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_ID (0x30021004) +#define SHA512_ACC_CSR_ID (0x4) #define CALIPTRA_TOP_REG_SHA512_ACC_CSR_MODE (0x30021008) #define SHA512_ACC_CSR_MODE (0x8) #define SHA512_ACC_CSR_MODE_MODE_LOW (0) @@ -196,42 +196,42 @@ #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_0 (0x30030048) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_0 (0x48) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_1 (0x3003004c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_1 (0x4c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_2 (0x30030050) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_2 (0x50) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_3 (0x30030054) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_3 (0x54) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_4 (0x30030058) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_4 (0x58) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0 (0x3003005c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0 (0x5c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1 (0x30030060) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1 (0x60) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2 (0x30030064) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2 (0x64) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3 (0x30030068) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3 (0x68) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4 (0x3003006c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4 (0x6c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_PAUSER (0x30030070) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_PAUSER (0x70) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK (0x30030074) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK (0x74) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x30030048) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x48) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x3003004c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x4c) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x30030050) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x50) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x30030054) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x54) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x30030058) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x58) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x3003005c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x5c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x30030060) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x60) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x30030064) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x64) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x30030068) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x68) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x3003006c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x6c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (0x30030070) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (0x70) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (0x30030074) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (0x74) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (0x1) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (0x30030078) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (0x78) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (0x3003007c) @@ -342,12 +342,12 @@ #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER (0x30030108) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER (0x108) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK (0x3003010c) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK (0x10c) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (0x30030108) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (0x108) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (0x3003010c) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (0x10c) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (0x1) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (0x30030110) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (0x110) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (0x30030114) diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index 42d37dff7..e6445d61a 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -22,8 +22,8 @@ `define MBOX_CSR_MBOX_LOCK (32'h0) `define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) `define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_USER (32'h30020004) -`define MBOX_CSR_MBOX_USER (32'h4) +`define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_ID (32'h30020004) +`define MBOX_CSR_MBOX_ID (32'h4) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_CMD (32'h30020008) `define MBOX_CSR_MBOX_CMD (32'h8) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DLEN (32'h3002000c) @@ -59,8 +59,8 @@ `define SHA512_ACC_CSR_LOCK (32'h0) `define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) `define SHA512_ACC_CSR_LOCK_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_USER (32'h30021004) -`define SHA512_ACC_CSR_USER (32'h4) +`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_ID (32'h30021004) +`define SHA512_ACC_CSR_ID (32'h4) `define CALIPTRA_TOP_REG_SHA512_ACC_CSR_MODE (32'h30021008) `define SHA512_ACC_CSR_MODE (32'h8) `define SHA512_ACC_CSR_MODE_MODE_LOW (0) @@ -196,42 +196,42 @@ `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_0 (32'h30030048) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_0 (32'h48) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_1 (32'h3003004c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_1 (32'h4c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_2 (32'h30030050) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_2 (32'h50) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_3 (32'h30030054) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_3 (32'h54) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_4 (32'h30030058) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_PAUSER_4 (32'h58) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0 (32'h3003005c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0 (32'h5c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1 (32'h30030060) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1 (32'h60) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2 (32'h30030064) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2 (32'h64) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3 (32'h30030068) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3 (32'h68) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4 (32'h3003006c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4 (32'h6c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_PAUSER (32'h30030070) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_PAUSER (32'h70) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK (32'h30030074) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK (32'h74) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h30030048) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h48) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h3003004c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h4c) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h30030050) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h50) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h30030054) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h54) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h30030058) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h58) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h3003005c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h5c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h30030060) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h60) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h30030064) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h64) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h30030068) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h68) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h3003006c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h6c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (32'h30030070) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (32'h70) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h30030074) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h74) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h30030078) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h78) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (32'h3003007c) @@ -342,12 +342,12 @@ `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER (32'h30030108) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER (32'h108) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK (32'h3003010c) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK (32'h10c) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (32'h30030108) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (32'h108) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h3003010c) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h10c) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h30030110) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h110) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (32'h30030114) diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index a2d4adbed..a2e65c25e 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -40,6 +40,12 @@ module mbox output mbox_sram_resp_t sha_sram_resp, output logic sha_sram_hold, // Throttle the SRAM requests when writing corrected ECC + input logic dma_sram_req_dv, + input soc_ifc_req_t dma_sram_req_data, + output logic [MBOX_DATA_W-1:0] dma_sram_rdata, + output logic dma_sram_hold, // Throttle the SRAM requests when SHA accel has access. + output logic dma_sram_error, + //SRAM interface output mbox_sram_req_t mbox_sram_req, input mbox_sram_resp_t mbox_sram_resp, @@ -48,12 +54,15 @@ module mbox output logic sram_single_ecc_error, output logic sram_double_ecc_error, + // Status + output logic uc_mbox_lock, + //interrupts output logic uc_mbox_data_avail, output logic soc_mbox_data_avail, output logic soc_req_mbox_lock, output mbox_protocol_error_t mbox_protocol_error, - output logic mbox_inv_pauser_axs, + output logic mbox_inv_axi_id_axs, //DMI reg access input logic dmi_inc_rdptr, @@ -118,6 +127,7 @@ logic mbox_protocol_sram_we; logic mbox_protocol_sram_rd, mbox_protocol_sram_rd_f; logic dir_req_dv_q, dir_req_rd_phase; logic dir_req_wr_ph; +logic dma_sram_req_dv_q, dma_sram_req_rd_phase; logic mask_rdata; logic [DEPTH_LOG2-1:0] dir_req_addr; @@ -146,10 +156,10 @@ assign mbox_error = read_error | write_error; //Determine if this is a valid request from the requester side //1) uC requests are valid if uc has lock -//2) SoC requests are valid if soc has lock and it's the user that locked it +//2) SoC requests are valid if soc has lock and it's the AXI ID that locked it always_comb valid_requester = hwif_out.mbox_lock.lock.value & ((~req_data.soc_req & (~soc_has_lock || (mbox_fsm_ps == MBOX_EXECUTE_UC))) | - ( req_data.soc_req & soc_has_lock & (req_data.user == hwif_out.mbox_user.user.value))); + ( req_data.soc_req & soc_has_lock & (req_data.id == hwif_out.mbox_id.id.value[SOC_IFC_ID_W-1:0]))); //Determine if this is a valid request from the receiver side always_comb valid_receiver = hwif_out.mbox_lock.lock.value & @@ -162,7 +172,7 @@ always_comb valid_receiver = hwif_out.mbox_lock.lock.value & (~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC))))); //We want to mask read data when -//Invalid user is trying to access the mailbox data +//Invalid ID is trying to access the mailbox data always_comb mask_rdata = hwif_out.mbox_dataout.dataout.swacc & ~valid_receiver; //move from idle to rdy for command when lock is acquired @@ -191,7 +201,7 @@ always_comb arc_FORCE_MBOX_UNLOCK = hwif_out.mbox_unlock.unlock.value; // Any register write or read by an INVALID agent results in the access // being silently dropped. // Assumption: uC (ROM, FMC, RT) will never make an invalid request. -// NOTE: Any APB agent can trigger the error at any point during a uC->SOC flow +// NOTE: Any AXI agent can trigger the error at any point during a uC->SOC flow // by writing to mbox_status (since it's a valid_receiver). // FIXED! valid_receiver is restricted by FSM state now. always_comb arc_MBOX_RDY_FOR_CMD_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_CMD) && @@ -256,7 +266,7 @@ always_comb begin : mbox_fsm_combo end // Flag a non-fatal error, but don't change states, if mbox is already IDLE // when an unexpected SOC access happens - if (req_dv && req_data.soc_req && !req_hold && (req_data.write || hwif_out.mbox_dataout.dataout.swacc)) begin + if (req_dv && req_data.soc_req && ~req_hold && (req_data.write || hwif_out.mbox_dataout.dataout.swacc)) begin mbox_protocol_error_nxt.axs_without_lock = 1'b1; end end @@ -289,7 +299,7 @@ always_comb begin : mbox_fsm_combo end MBOX_RDY_FOR_DATA: begin //update the write pointers to sram when accessing datain register - inc_wrptr = hwif_out.mbox_datain.datain.swmod & valid_requester; + inc_wrptr = hwif_out.mbox_datain.datain.swmod & valid_requester & ~req_hold; if (arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC) begin mbox_fsm_ns = MBOX_EXECUTE_UC; //reset wrptr so receiver can write response @@ -318,8 +328,8 @@ always_comb begin : mbox_fsm_combo //only uC can write to datain here to respond to SoC MBOX_EXECUTE_UC: begin uc_mbox_data_avail = 1; - inc_rdptr = dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & ~req_data.soc_req); - inc_wrptr = hwif_out.mbox_datain.datain.swmod & ~req_data.soc_req; + inc_rdptr = dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & ~req_data.soc_req & ~req_hold); + inc_wrptr = hwif_out.mbox_datain.datain.swmod & ~req_data.soc_req & ~req_hold; if (arc_MBOX_EXECUTE_UC_MBOX_IDLE) begin mbox_fsm_ns = MBOX_IDLE; end @@ -340,12 +350,12 @@ always_comb begin : mbox_fsm_combo end end //uC set execute, data is for the SoC - //If we're here, restrict reading to the user that requested the data + //If we're here, restrict reading to the AXI ID that requested the data //Only SoC can read from mbox //Only SoC can write to datain here to respond to uC MBOX_EXECUTE_SOC: begin soc_mbox_data_avail = 1; - inc_rdptr = (dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & req_data.soc_req & valid_receiver)); + inc_rdptr = (dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & req_data.soc_req & valid_receiver & ~req_hold)); if (arc_MBOX_EXECUTE_SOC_MBOX_IDLE) begin mbox_fsm_ns = MBOX_IDLE; end @@ -379,10 +389,10 @@ always_comb begin : mbox_fsm_combo endcase end -// Any ol' PAUSER is fine for reg-reads (except dataout) -// NOTE: This only captures accesses by APB agents that are valid, but do not +// Any ol' AXI_ID is fine for reg-reads (except dataout) +// NOTE: This only captures accesses by AXI agents that are valid, but do not // have lock. Invalid agent accesses are blocked by arbiter. -assign mbox_inv_pauser_axs = req_dv && req_data.soc_req && !req_hold && +assign mbox_inv_axi_id_axs = req_dv && req_data.soc_req && !req_hold && !valid_requester && !valid_receiver && (req_data.write || hwif_out.mbox_dataout.dataout.swacc); @@ -397,6 +407,7 @@ always_ff @(posedge clk or negedge rst_b) begin mbox_fsm_ps <= MBOX_IDLE; soc_has_lock <= '0; dir_req_rd_phase <= '0; + dma_sram_req_rd_phase <= '0; mbox_wrptr <= '0; mbox_wr_full <= '0; mbox_rdptr <= '0; @@ -411,7 +422,8 @@ always_ff @(posedge clk or negedge rst_b) begin mbox_fsm_ps <= mbox_fsm_ns; soc_has_lock <= arc_MBOX_IDLE_MBOX_RDY_FOR_CMD ? soc_has_lock_nxt : hwif_out.mbox_lock.lock.value ? soc_has_lock : '0; - dir_req_rd_phase <= dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write; + dir_req_rd_phase <= dir_req_dv_q & ~sha_sram_req_dv & ~(dma_sram_req_dv_q & dma_sram_req_data.write) & ~req_data.write; + dma_sram_req_rd_phase <= dma_sram_req_dv_q & ~sha_sram_req_dv & ~dma_sram_req_data.write; mbox_wrptr <= ((inc_wrptr & wrptr_inc_valid) | rst_mbox_wrptr) ? mbox_wrptr_nxt : mbox_wrptr; mbox_wr_full <= (inc_wrptr | rst_mbox_wrptr) ? mbox_wr_full_nxt : mbox_wr_full; mbox_rdptr <= (mbox_protocol_sram_rd) ? mbox_rdptr_nxt : mbox_rdptr; @@ -422,29 +434,42 @@ always_ff @(posedge clk or negedge rst_b) begin dlen_in_dws <= latch_dlen_in_dws ? dlen_in_dws_nxt : dlen_in_dws; mbox_protocol_error <= mbox_protocol_error_nxt; //enable ecc for mbox protocol, direct reads, or SHA direct reads - sram_rd_ecc_en <= mbox_protocol_sram_rd | (dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write) | sha_sram_req_dv; + sram_rd_ecc_en <= mbox_protocol_sram_rd | (dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write) | (dma_sram_req_dv_q & ~dma_sram_req_data.write) | sha_sram_req_dv; end end +always_comb uc_mbox_lock = hwif_out.mbox_lock.lock.value && ~soc_has_lock; + +always_comb dma_sram_req_dv_q = dma_sram_req_dv & hwif_out.mbox_lock.lock.value & ~soc_has_lock & ~dma_sram_req_rd_phase; //need to hold direct read accesses for 1 clock to get response //create a qualified direct request signal that is masked during the data phase //hold the interface to insert wait state when direct request comes //mask the request and hold the interface if SHA is using the mailbox //hold when a read to dataout is coming and we haven't updated the data yet always_comb dir_req_dv_q = (dir_req_dv & ~dir_req_rd_phase & hwif_out.mbox_lock.lock.value & (~soc_has_lock | (mbox_fsm_ps == MBOX_EXECUTE_UC))) | + (dma_sram_req_dv_q) | sha_sram_req_dv; -always_comb dir_req_wr_ph = dir_req_dv_q & ~sha_sram_req_dv & req_data.write; -always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : req_data.addr[DEPTH_LOG2+1:2]; +always_comb dir_req_wr_ph = dir_req_dv_q & ~sha_sram_req_dv & ((~dma_sram_req_dv_q & req_data.write) | (dma_sram_req_dv_q & dma_sram_req_data.write)); +always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : + dma_sram_req_dv_q ? dma_sram_req_data.addr[DEPTH_LOG2+1:2] : + req_data.addr[DEPTH_LOG2+1:2]; + +// Arb precedence: +// SHA accelerator: highest +// DMA (with lock): next +// Direct request: lowest +// No arbitration/round-robin -- this is strictly observed for every txn //Direct read from uC, stall 1 clock dv_q will be de-asserted second clock -always_comb req_hold = (dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write) | - //Direct access from uC while sha accelerator is reading - (dir_req_dv & ~dir_req_rd_phase & sha_sram_req_dv) | +always_comb req_hold = (dir_req_dv_q & ~sha_sram_req_dv & ~dma_sram_req_dv_q & ~req_data.write) | + //Direct access from uC while sha accelerator or DMA is accessing + (dir_req_dv & ~dir_req_rd_phase & (sha_sram_req_dv | dma_sram_req_dv_q | dma_sram_req_rd_phase)) | //in an update cycle for dataout register (hwif_out.mbox_dataout.dataout.swacc & mbox_protocol_sram_rd_f); +always_comb dma_sram_hold = (sha_sram_req_dv && !dma_sram_req_rd_phase) || (dma_sram_req_dv_q && !dma_sram_req_data.write); always_comb sha_sram_hold = 1'b0; //SRAM interface @@ -457,6 +482,9 @@ always_comb sram_waddr = dir_req_dv_q ? dir_req_addr : mbox_wrptr; //We want to mask the read data for certain accesses always_comb rdata = ({DATA_W{~mask_rdata}} & csr_rdata); always_comb dir_rdata = dir_req_rd_phase ? sram_rdata_cor : '0; +always_comb dma_sram_rdata = dma_sram_req_rd_phase ? sram_rdata_cor : '0; + +always_comb dma_sram_error = 1'b0; // TODO: ecc error? always_comb begin: mbox_sram_inf //read live on direct access, or when pointer has been incremented, for pre-load on read pointer reset, or ecc correction @@ -498,7 +526,7 @@ rvecc_decode ecc_decode ( //control for sram write and read pointer //SoC access is controlled by mailbox, each subsequent read or write increments the pointer //uC accesses can specify the specific read or write address, or rely on mailbox to control -always_comb sram_wdata = req_data.wdata; +always_comb sram_wdata = (dma_sram_req_dv_q && dma_sram_req_data.write ) ? dma_sram_req_data.wdata : req_data.wdata; //in ready for data state we increment the pointer each time we write always_comb mbox_wrptr_nxt = rst_mbox_wrptr ? '0 : @@ -519,18 +547,18 @@ always_comb mbox_rd_full_nxt = rst_mbox_rdptr ? '0 : inc_rdptr & (mbox_rdptr == always_comb soc_req_mbox_lock = hwif_out.mbox_lock.lock.value & ~soc_has_lock & hwif_out.mbox_lock.lock.swmod & req_data.soc_req; always_comb hwif_in.cptra_rst_b = rst_b; -always_comb hwif_in.mbox_user.user.next = req_data.user; +always_comb hwif_in.mbox_id.id.next = 32'(req_data.id); always_comb hwif_in.mbox_status.mbox_fsm_ps.next = mbox_fsm_ps; always_comb hwif_in.soc_req = req_data.soc_req; -//check the requesting user: +//check the requesting ID: //don't update mailbox data if lock hasn't been acquired //if uc has the lock, check that this request is from uc -//if soc has the lock, check that this request is from soc and user attributes match +//if soc has the lock, check that this request is from soc and ID attributes match always_comb hwif_in.valid_requester = valid_requester; always_comb hwif_in.valid_receiver = valid_receiver; -//indicate that requesting user is setting the lock +//indicate that requesting ID is setting the lock always_comb hwif_in.lock_set = arc_MBOX_IDLE_MBOX_RDY_FOR_CMD; //update dataout @@ -576,7 +604,7 @@ mbox_csr1( .s_cpuif_req_is_wr(req_data.write), .s_cpuif_addr(req_data.addr[MBOX_CSR_ADDR_WIDTH-1:0]), .s_cpuif_wr_data(req_data.wdata), - .s_cpuif_wr_biten('1), + .s_cpuif_wr_biten('1), // FIXME .s_cpuif_req_stall_wr(s_cpuif_req_stall_wr_nc), .s_cpuif_req_stall_rd(s_cpuif_req_stall_rd_nc), .s_cpuif_rd_ack(s_cpuif_rd_ack_nc), diff --git a/src/soc_ifc/rtl/mbox_csr.rdl b/src/soc_ifc/rtl/mbox_csr.rdl index 8a67121be..b6a710714 100644 --- a/src/soc_ifc/rtl/mbox_csr.rdl +++ b/src/soc_ifc/rtl/mbox_csr.rdl @@ -39,15 +39,15 @@ addrmap mbox_csr { field {rset; sw=r; hw=r; hwclr=true; precedence=hw; swmod=true;} lock=0; } mbox_lock; - // user register - // store user from interface when setting lock + // ID register + // store AXI ID from interface when setting lock reg { - name="Mailbox User"; - desc="Stores the user that locked the mailbox + name="Mailbox ID"; + desc="Stores the AXI ID that locked the mailbox [br]Caliptra Access: RO [br]SOC Access: RO"; - field {sw=r; hw=rw; we=lock_set;} user[32]=0; - } mbox_user; + field {sw=r; hw=rw; we=lock_set;} id[32]=0; + } mbox_id; reg { name="Mailbox Command"; diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv index c58f79ea2..d99ba04d7 100644 --- a/src/soc_ifc/rtl/mbox_csr.sv +++ b/src/soc_ifc/rtl/mbox_csr.sv @@ -67,7 +67,7 @@ module mbox_csr ( //-------------------------------------------------------------------------- typedef struct packed{ logic mbox_lock; - logic mbox_user; + logic mbox_id; logic mbox_cmd; logic mbox_dlen; logic mbox_datain; @@ -84,7 +84,7 @@ module mbox_csr ( always_comb begin decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 6'h0); - decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 6'h4); + decoded_reg_strb.mbox_id = cpuif_req_masked & (cpuif_addr == 6'h4); decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 6'h8); decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 6'hc); decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 6'h10); @@ -114,8 +114,8 @@ module mbox_csr ( struct packed{ logic [31:0] next; logic load_next; - } user; - } mbox_user; + } id; + } mbox_id; struct packed{ struct packed{ logic [31:0] next; @@ -190,8 +190,8 @@ module mbox_csr ( struct packed{ struct packed{ logic [31:0] value; - } user; - } mbox_user; + } id; + } mbox_id; struct packed{ struct packed{ logic [31:0] value; @@ -270,27 +270,27 @@ module mbox_csr ( end assign hwif_out.mbox_lock.lock.value = field_storage.mbox_lock.lock.value; assign hwif_out.mbox_lock.lock.swmod = decoded_reg_strb.mbox_lock && !decoded_req_is_wr; - // Field: mbox_csr.mbox_user.user + // Field: mbox_csr.mbox_id.id always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.mbox_user.user.value; + next_c = field_storage.mbox_id.id.value; load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we - next_c = hwif_in.mbox_user.user.next; + next_c = hwif_in.mbox_id.id.next; load_next_c = '1; end - field_combo.mbox_user.user.next = next_c; - field_combo.mbox_user.user.load_next = load_next_c; + field_combo.mbox_id.id.next = next_c; + field_combo.mbox_id.id.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_user.user.value <= 32'h0; - end else if(field_combo.mbox_user.user.load_next) begin - field_storage.mbox_user.user.value <= field_combo.mbox_user.user.next; + field_storage.mbox_id.id.value <= 32'h0; + end else if(field_combo.mbox_id.id.load_next) begin + field_storage.mbox_id.id.value <= field_combo.mbox_id.id.next; end end - assign hwif_out.mbox_user.user.value = field_storage.mbox_user.user.value; + assign hwif_out.mbox_id.id.value = field_storage.mbox_id.id.value; // Field: mbox_csr.mbox_cmd.command always_comb begin automatic logic [31:0] next_c; @@ -585,7 +585,7 @@ module mbox_csr ( logic [9-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.mbox_lock && !decoded_req_is_wr) ? field_storage.mbox_lock.lock.value : '0; assign readback_array[0][31:1] = '0; - assign readback_array[1][31:0] = (decoded_reg_strb.mbox_user && !decoded_req_is_wr) ? field_storage.mbox_user.user.value : '0; + assign readback_array[1][31:0] = (decoded_reg_strb.mbox_id && !decoded_req_is_wr) ? field_storage.mbox_id.id.value : '0; assign readback_array[2][31:0] = (decoded_reg_strb.mbox_cmd && !decoded_req_is_wr) ? field_storage.mbox_cmd.command.value : '0; assign readback_array[3][31:0] = (decoded_reg_strb.mbox_dlen && !decoded_req_is_wr) ? field_storage.mbox_dlen.length.value : '0; assign readback_array[4][31:0] = (decoded_reg_strb.mbox_datain && !decoded_req_is_wr) ? field_storage.mbox_datain.datain.value : '0; diff --git a/src/soc_ifc/rtl/mbox_csr_covergroups.svh b/src/soc_ifc/rtl/mbox_csr_covergroups.svh index 3664e1fc3..7efb5ce3c 100644 --- a/src/soc_ifc/rtl/mbox_csr_covergroups.svh +++ b/src/soc_ifc/rtl/mbox_csr_covergroups.svh @@ -41,8 +41,8 @@ endgroup - /*----------------------- MBOX_CSR__MBOX_USER COVERGROUPS -----------------------*/ - covergroup mbox_csr__mbox_user_bit_cg with function sample(input bit reg_bit); + /*----------------------- MBOX_CSR__MBOX_ID COVERGROUPS -----------------------*/ + covergroup mbox_csr__mbox_id_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -53,11 +53,11 @@ } endgroup - covergroup mbox_csr__mbox_user_fld_cg with function sample( - input bit [32-1:0] user + covergroup mbox_csr__mbox_id_fld_cg with function sample( + input bit [32-1:0] id ); option.per_instance = 1; - user_cp : coverpoint user { + id_cp : coverpoint id { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -221,7 +221,8 @@ input bit [1-1:0] ecc_single_error, input bit [1-1:0] ecc_double_error, input bit [3-1:0] mbox_fsm_ps, - input bit [1-1:0] soc_has_lock + input bit [1-1:0] soc_has_lock, + input bit [15-1:0] mbox_rdptr ); option.per_instance = 1; status_cp : coverpoint status; @@ -278,6 +279,7 @@ // illegal_bins TRANSITION_ERROR_EXECUTE_SOC = (mbox_fsm_state_e'(MBOX_ERROR) => mbox_fsm_state_e'(MBOX_EXECUTE_SOC)); } soc_has_lock_cp : coverpoint soc_has_lock; + mbox_rdptr_cp : coverpoint mbox_rdptr; status_edge_cp : coverpoint status { bins rise = (0 => 1); bins fall = (1 => 0); diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv index 39f775c03..13341ef52 100644 --- a/src/soc_ifc/rtl/mbox_csr_pkg.sv +++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv @@ -16,11 +16,11 @@ package mbox_csr_pkg; typedef struct packed{ logic [31:0] next; - } mbox_csr__mbox_user__user__in_t; + } mbox_csr__mbox_id__id__in_t; typedef struct packed{ - mbox_csr__mbox_user__user__in_t user; - } mbox_csr__mbox_user__in_t; + mbox_csr__mbox_id__id__in_t id; + } mbox_csr__mbox_id__in_t; typedef struct packed{ logic [31:0] next; @@ -80,7 +80,7 @@ package mbox_csr_pkg; logic valid_requester; logic valid_receiver; mbox_csr__mbox_lock__in_t mbox_lock; - mbox_csr__mbox_user__in_t mbox_user; + mbox_csr__mbox_id__in_t mbox_id; mbox_csr__mbox_dataout__in_t mbox_dataout; mbox_csr__mbox_execute__in_t mbox_execute; mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t mbox_status; @@ -97,11 +97,11 @@ package mbox_csr_pkg; typedef struct packed{ logic [31:0] value; - } mbox_csr__mbox_user__user__out_t; + } mbox_csr__mbox_id__id__out_t; typedef struct packed{ - mbox_csr__mbox_user__user__out_t user; - } mbox_csr__mbox_user__out_t; + mbox_csr__mbox_id__id__out_t id; + } mbox_csr__mbox_id__out_t; typedef struct packed{ logic swmod; @@ -190,7 +190,7 @@ package mbox_csr_pkg; typedef struct packed{ mbox_csr__mbox_lock__out_t mbox_lock; - mbox_csr__mbox_user__out_t mbox_user; + mbox_csr__mbox_id__out_t mbox_id; mbox_csr__mbox_cmd__out_t mbox_cmd; mbox_csr__mbox_dlen__out_t mbox_dlen; mbox_csr__mbox_datain__out_t mbox_datain; diff --git a/src/soc_ifc/rtl/mbox_csr_sample.svh b/src/soc_ifc/rtl/mbox_csr_sample.svh index 29ef7be05..b061ddb12 100644 --- a/src/soc_ifc/rtl/mbox_csr_sample.svh +++ b/src/soc_ifc/rtl/mbox_csr_sample.svh @@ -40,8 +40,8 @@ end endfunction - /*----------------------- MBOX_CSR__MBOX_USER SAMPLE FUNCTIONS -----------------------*/ - function void mbox_csr__mbox_user::sample(uvm_reg_data_t data, + /*----------------------- MBOX_CSR__MBOX_ID SAMPLE FUNCTIONS -----------------------*/ + function void mbox_csr__mbox_id::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -49,19 +49,19 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(user_bit_cg[bt]) this.user_bit_cg[bt].sample(data[0 + bt]); + foreach(id_bit_cg[bt]) this.id_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*user*/ ); + this.fld_cg.sample( data[31:0]/*id*/ ); end endfunction - function void mbox_csr__mbox_user::sample_values(); + function void mbox_csr__mbox_id::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(user_bit_cg[bt]) this.user_bit_cg[bt].sample(user.get_mirrored_value() >> bt); + foreach(id_bit_cg[bt]) this.id_bit_cg[bt].sample(id.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( user.get_mirrored_value() ); + this.fld_cg.sample( id.get_mirrored_value() ); end endfunction @@ -204,9 +204,10 @@ foreach(ecc_double_error_bit_cg[bt]) this.ecc_double_error_bit_cg[bt].sample(data[5 + bt]); foreach(mbox_fsm_ps_bit_cg[bt]) this.mbox_fsm_ps_bit_cg[bt].sample(data[6 + bt]); foreach(soc_has_lock_bit_cg[bt]) this.soc_has_lock_bit_cg[bt].sample(data[9 + bt]); + foreach(mbox_rdptr_bit_cg[bt]) this.mbox_rdptr_bit_cg[bt].sample(data[10 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[3:0]/*status*/ , data[4:4]/*ecc_single_error*/ , data[5:5]/*ecc_double_error*/ , data[8:6]/*mbox_fsm_ps*/ , data[9:9]/*soc_has_lock*/ ); + this.fld_cg.sample( data[3:0]/*status*/ , data[4:4]/*ecc_single_error*/ , data[5:5]/*ecc_double_error*/ , data[8:6]/*mbox_fsm_ps*/ , data[9:9]/*soc_has_lock*/ , data[24:10]/*mbox_rdptr*/ ); end endfunction @@ -217,9 +218,10 @@ foreach(ecc_double_error_bit_cg[bt]) this.ecc_double_error_bit_cg[bt].sample(ecc_double_error.get_mirrored_value() >> bt); foreach(mbox_fsm_ps_bit_cg[bt]) this.mbox_fsm_ps_bit_cg[bt].sample(mbox_fsm_ps.get_mirrored_value() >> bt); foreach(soc_has_lock_bit_cg[bt]) this.soc_has_lock_bit_cg[bt].sample(soc_has_lock.get_mirrored_value() >> bt); + foreach(mbox_rdptr_bit_cg[bt]) this.mbox_rdptr_bit_cg[bt].sample(mbox_rdptr.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( status.get_mirrored_value() , ecc_single_error.get_mirrored_value() , ecc_double_error.get_mirrored_value() , mbox_fsm_ps.get_mirrored_value() , soc_has_lock.get_mirrored_value() ); + this.fld_cg.sample( status.get_mirrored_value() , ecc_single_error.get_mirrored_value() , ecc_double_error.get_mirrored_value() , mbox_fsm_ps.get_mirrored_value() , soc_has_lock.get_mirrored_value() , mbox_rdptr.get_mirrored_value() ); end endfunction diff --git a/src/soc_ifc/rtl/mbox_csr_uvm.sv b/src/soc_ifc/rtl/mbox_csr_uvm.sv index 760853a1a..ee50564b5 100644 --- a/src/soc_ifc/rtl/mbox_csr_uvm.sv +++ b/src/soc_ifc/rtl/mbox_csr_uvm.sv @@ -34,17 +34,17 @@ package mbox_csr_uvm; endfunction : build endclass : mbox_csr__mbox_lock - // Reg - mbox_csr::mbox_user - class mbox_csr__mbox_user extends uvm_reg; + // Reg - mbox_csr::mbox_id + class mbox_csr__mbox_id extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - mbox_csr__mbox_user_bit_cg user_bit_cg[32]; - mbox_csr__mbox_user_fld_cg fld_cg; - rand uvm_reg_field user; + mbox_csr__mbox_id_bit_cg id_bit_cg[32]; + mbox_csr__mbox_id_fld_cg fld_cg; + rand uvm_reg_field id; - function new(string name = "mbox_csr__mbox_user"); + function new(string name = "mbox_csr__mbox_id"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -54,15 +54,15 @@ package mbox_csr_uvm; uvm_reg_map map); virtual function void build(); - this.user = new("user"); - this.user.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); + this.id = new("id"); + this.id.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(user_bit_cg[bt]) user_bit_cg[bt] = new(); + foreach(id_bit_cg[bt]) id_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : mbox_csr__mbox_user + endclass : mbox_csr__mbox_id // Reg - mbox_csr::mbox_cmd class mbox_csr__mbox_cmd extends uvm_reg; @@ -302,7 +302,7 @@ package mbox_csr_uvm; // Addrmap - mbox_csr class mbox_csr extends uvm_reg_block; rand mbox_csr__mbox_lock mbox_lock; - rand mbox_csr__mbox_user mbox_user; + rand mbox_csr__mbox_id mbox_id; rand mbox_csr__mbox_cmd mbox_cmd; rand mbox_csr__mbox_dlen mbox_dlen; rand mbox_csr__mbox_datain mbox_datain; @@ -322,11 +322,11 @@ package mbox_csr_uvm; this.mbox_lock.build(); this.default_map.add_reg(this.mbox_lock, 'h0); - this.mbox_user = new("mbox_user"); - this.mbox_user.configure(this); + this.mbox_id = new("mbox_id"); + this.mbox_id.configure(this); - this.mbox_user.build(); - this.default_map.add_reg(this.mbox_user, 'h4); + this.mbox_id.build(); + this.default_map.add_reg(this.mbox_id, 'h4); this.mbox_cmd = new("mbox_cmd"); this.mbox_cmd.configure(this); diff --git a/src/soc_ifc/rtl/sha512_acc_csr.sv b/src/soc_ifc/rtl/sha512_acc_csr.sv index ba52bf8ec..78bfe43fa 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr.sv @@ -67,7 +67,7 @@ module sha512_acc_csr ( //-------------------------------------------------------------------------- typedef struct packed{ logic LOCK; - logic USER; + logic ID; logic MODE; logic START_ADDRESS; logic DLEN; @@ -106,7 +106,7 @@ module sha512_acc_csr ( always_comb begin decoded_reg_strb.LOCK = cpuif_req_masked & (cpuif_addr == 12'h0); - decoded_reg_strb.USER = cpuif_req_masked & (cpuif_addr == 12'h4); + decoded_reg_strb.ID = cpuif_req_masked & (cpuif_addr == 12'h4); decoded_reg_strb.MODE = cpuif_req_masked & (cpuif_addr == 12'h8); decoded_reg_strb.START_ADDRESS = cpuif_req_masked & (cpuif_addr == 12'hc); decoded_reg_strb.DLEN = cpuif_req_masked & (cpuif_addr == 12'h10); @@ -158,8 +158,8 @@ module sha512_acc_csr ( struct packed{ logic [31:0] next; logic load_next; - } USER; - } USER; + } ID; + } ID; struct packed{ struct packed{ logic [1:0] next; @@ -404,8 +404,8 @@ module sha512_acc_csr ( struct packed{ struct packed{ logic [31:0] value; - } USER; - } USER; + } ID; + } ID; struct packed{ struct packed{ logic [1:0] value; @@ -591,7 +591,7 @@ module sha512_acc_csr ( if(decoded_reg_strb.LOCK && !decoded_req_is_wr) begin // SW set on read next_c = '1; load_next_c = '1; - end else if(decoded_reg_strb.LOCK && decoded_req_is_wr && hwif_in.valid_user) begin // SW write 1 clear + end else if(decoded_reg_strb.LOCK && decoded_req_is_wr && hwif_in.valid_id) begin // SW write 1 clear next_c = field_storage.LOCK.LOCK.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end @@ -607,34 +607,34 @@ module sha512_acc_csr ( end assign hwif_out.LOCK.LOCK.value = field_storage.LOCK.LOCK.value; assign hwif_out.LOCK.LOCK.swmod = decoded_reg_strb.LOCK; - // Field: sha512_acc_csr.USER.USER + // Field: sha512_acc_csr.ID.ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.USER.USER.value; + next_c = field_storage.ID.ID.value; load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we - next_c = hwif_in.USER.USER.next; + next_c = hwif_in.ID.ID.next; load_next_c = '1; end - field_combo.USER.USER.next = next_c; - field_combo.USER.USER.load_next = load_next_c; + field_combo.ID.ID.next = next_c; + field_combo.ID.ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.USER.USER.value <= 32'h0; - end else if(field_combo.USER.USER.load_next) begin - field_storage.USER.USER.value <= field_combo.USER.USER.next; + field_storage.ID.ID.value <= 32'h0; + end else if(field_combo.ID.ID.load_next) begin + field_storage.ID.ID.value <= field_combo.ID.ID.next; end end - assign hwif_out.USER.USER.value = field_storage.USER.USER.value; + assign hwif_out.ID.ID.value = field_storage.ID.ID.value; // Field: sha512_acc_csr.MODE.MODE always_comb begin automatic logic [1:0] next_c; automatic logic load_next_c; next_c = field_storage.MODE.MODE.value; load_next_c = '0; - if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.MODE.MODE.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; end @@ -656,7 +656,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.MODE.ENDIAN_TOGGLE.value; load_next_c = '0; - if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.MODE.ENDIAN_TOGGLE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; end @@ -677,7 +677,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.START_ADDRESS.ADDR.value; load_next_c = '0; - if(decoded_reg_strb.START_ADDRESS && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.START_ADDRESS && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.START_ADDRESS.ADDR.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end @@ -698,7 +698,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.DLEN.LENGTH.value; load_next_c = '0; - if(decoded_reg_strb.DLEN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.DLEN && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.DLEN.LENGTH.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end @@ -719,7 +719,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.DATAIN.DATAIN.value; load_next_c = '0; - if(decoded_reg_strb.DATAIN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.DATAIN && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.DATAIN.DATAIN.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end @@ -740,7 +740,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.EXECUTE.EXECUTE.value; load_next_c = '0; - if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.EXECUTE.EXECUTE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end else if(hwif_in.EXECUTE.EXECUTE.hwclr) begin // HW Clear @@ -1630,7 +1630,7 @@ module sha512_acc_csr ( logic [44-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.LOCK && !decoded_req_is_wr) ? field_storage.LOCK.LOCK.value : '0; assign readback_array[0][31:1] = '0; - assign readback_array[1][31:0] = (decoded_reg_strb.USER && !decoded_req_is_wr) ? field_storage.USER.USER.value : '0; + assign readback_array[1][31:0] = (decoded_reg_strb.ID && !decoded_req_is_wr) ? field_storage.ID.ID.value : '0; assign readback_array[2][1:0] = (decoded_reg_strb.MODE && !decoded_req_is_wr) ? field_storage.MODE.MODE.value : '0; assign readback_array[2][2:2] = (decoded_reg_strb.MODE && !decoded_req_is_wr) ? field_storage.MODE.ENDIAN_TOGGLE.value : '0; assign readback_array[2][31:3] = '0; diff --git a/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh b/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh index 68cab6060..acc164a78 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh +++ b/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh @@ -35,8 +35,8 @@ endgroup - /*----------------------- SHA512_ACC_CSR__USER COVERGROUPS -----------------------*/ - covergroup sha512_acc_csr__USER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SHA512_ACC_CSR__ID COVERGROUPS -----------------------*/ + covergroup sha512_acc_csr__ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -47,11 +47,11 @@ } endgroup - covergroup sha512_acc_csr__USER_fld_cg with function sample( - input bit [32-1:0] USER + covergroup sha512_acc_csr__ID_fld_cg with function sample( + input bit [32-1:0] ID ); option.per_instance = 1; - USER_cp : coverpoint USER; + ID_cp : coverpoint ID; endgroup diff --git a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv index 71e0470dd..ae96e1e4e 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv @@ -8,11 +8,11 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic [31:0] next; - } sha512_acc_csr__USER__USER__in_t; + } sha512_acc_csr__ID__ID__in_t; typedef struct packed{ - sha512_acc_csr__USER__USER__in_t USER; - } sha512_acc_csr__USER__in_t; + sha512_acc_csr__ID__ID__in_t ID; + } sha512_acc_csr__ID__in_t; typedef struct packed{ logic hwclr; @@ -82,11 +82,11 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic lock_set; - logic valid_user; + logic valid_id; logic soc_req; logic cptra_rst_b; logic cptra_pwrgood; - sha512_acc_csr__USER__in_t USER; + sha512_acc_csr__ID__in_t ID; sha512_acc_csr__EXECUTE__in_t EXECUTE; sha512_acc_csr__STATUS__in_t STATUS; sha512_acc_csr__DIGEST__in_t [16-1:0]DIGEST; @@ -104,11 +104,11 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic [31:0] value; - } sha512_acc_csr__USER__USER__out_t; + } sha512_acc_csr__ID__ID__out_t; typedef struct packed{ - sha512_acc_csr__USER__USER__out_t USER; - } sha512_acc_csr__USER__out_t; + sha512_acc_csr__ID__ID__out_t ID; + } sha512_acc_csr__ID__out_t; typedef struct packed{ logic [1:0] value; @@ -202,7 +202,7 @@ package sha512_acc_csr_pkg; typedef struct packed{ sha512_acc_csr__LOCK__out_t LOCK; - sha512_acc_csr__USER__out_t USER; + sha512_acc_csr__ID__out_t ID; sha512_acc_csr__MODE__out_t MODE; sha512_acc_csr__START_ADDRESS__out_t START_ADDRESS; sha512_acc_csr__DLEN__out_t DLEN; diff --git a/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl b/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl index 7ae68c502..c538e477f 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl +++ b/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl @@ -23,7 +23,7 @@ default regwidth = 32; // reg property default accesswidth = 32; // reg property signal {} lock_set; -signal {} valid_user; +signal {} valid_id; //signal to indicate request is coming from soc side signal {} soc_req; diff --git a/src/soc_ifc/rtl/sha512_acc_csr_sample.svh b/src/soc_ifc/rtl/sha512_acc_csr_sample.svh index cb752d1e8..09e30dbc6 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_sample.svh +++ b/src/soc_ifc/rtl/sha512_acc_csr_sample.svh @@ -40,8 +40,8 @@ end endfunction - /*----------------------- SHA512_ACC_CSR__USER SAMPLE FUNCTIONS -----------------------*/ - function void sha512_acc_csr__USER::sample(uvm_reg_data_t data, + /*----------------------- SHA512_ACC_CSR__ID SAMPLE FUNCTIONS -----------------------*/ + function void sha512_acc_csr__ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -49,19 +49,19 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(USER_bit_cg[bt]) this.USER_bit_cg[bt].sample(data[0 + bt]); + foreach(ID_bit_cg[bt]) this.ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*USER*/ ); + this.fld_cg.sample( data[31:0]/*ID*/ ); end endfunction - function void sha512_acc_csr__USER::sample_values(); + function void sha512_acc_csr__ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(USER_bit_cg[bt]) this.USER_bit_cg[bt].sample(USER.get_mirrored_value() >> bt); + foreach(ID_bit_cg[bt]) this.ID_bit_cg[bt].sample(ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( USER.get_mirrored_value() ); + this.fld_cg.sample( ID.get_mirrored_value() ); end endfunction diff --git a/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv b/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv index d5f30e46e..49a28ec13 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv @@ -34,17 +34,17 @@ package sha512_acc_csr_uvm; endfunction : build endclass : sha512_acc_csr__LOCK - // Reg - sha512_acc_csr::USER - class sha512_acc_csr__USER extends uvm_reg; + // Reg - sha512_acc_csr::ID + class sha512_acc_csr__ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - sha512_acc_csr__USER_bit_cg USER_bit_cg[32]; - sha512_acc_csr__USER_fld_cg fld_cg; - rand uvm_reg_field USER; + sha512_acc_csr__ID_bit_cg ID_bit_cg[32]; + sha512_acc_csr__ID_fld_cg fld_cg; + rand uvm_reg_field ID; - function new(string name = "sha512_acc_csr__USER"); + function new(string name = "sha512_acc_csr__ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -54,15 +54,15 @@ package sha512_acc_csr_uvm; uvm_reg_map map); virtual function void build(); - this.USER = new("USER"); - this.USER.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); + this.ID = new("ID"); + this.ID.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(USER_bit_cg[bt]) USER_bit_cg[bt] = new(); + foreach(ID_bit_cg[bt]) ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : sha512_acc_csr__USER + endclass : sha512_acc_csr__ID // Reg - sha512_acc_csr::MODE class sha512_acc_csr__MODE extends uvm_reg; @@ -1063,7 +1063,7 @@ package sha512_acc_csr_uvm; // Addrmap - sha512_acc_csr class sha512_acc_csr extends uvm_reg_block; rand sha512_acc_csr__LOCK LOCK; - rand sha512_acc_csr__USER USER; + rand sha512_acc_csr__ID ID; rand sha512_acc_csr__MODE MODE; rand sha512_acc_csr__START_ADDRESS START_ADDRESS; rand sha512_acc_csr__DLEN DLEN; @@ -1085,11 +1085,11 @@ package sha512_acc_csr_uvm; this.LOCK.build(); this.default_map.add_reg(this.LOCK, 'h0); - this.USER = new("USER"); - this.USER.configure(this); + this.ID = new("ID"); + this.ID.configure(this); - this.USER.build(); - this.default_map.add_reg(this.USER, 'h4); + this.ID.build(); + this.default_map.add_reg(this.ID, 'h4); this.MODE = new("MODE"); this.MODE.configure(this); diff --git a/src/soc_ifc/rtl/sha512_acc_external_csr.rdl b/src/soc_ifc/rtl/sha512_acc_external_csr.rdl index 4f273224a..f0896f8e6 100644 --- a/src/soc_ifc/rtl/sha512_acc_external_csr.rdl +++ b/src/soc_ifc/rtl/sha512_acc_external_csr.rdl @@ -19,16 +19,16 @@ reg { desc="SHA lock register for SHA access, reading 0 will set the lock, Write 1 to clear the lock [br]Caliptra Access: RW [br]SOC Access: RW"; - field {rset; woclr; sw=rw; hw=r; swwe=valid_user; swmod=true;} LOCK=1; + field {rset; woclr; sw=rw; hw=r; swwe=valid_id; swmod=true;} LOCK=1; } LOCK; reg { - name="SHA Accelerator User"; - desc="Stores the user that locked the SHA + name="SHA Accelerator ID"; + desc="Stores the AXI ID that locked the SHA [br]Caliptra Access: RO [br]SOC Access: RO"; - field {sw=r; hw=rw; we=lock_set;} USER[32]=0; -} USER; + field {sw=r; hw=rw; we=lock_set;} ID[32]=0; +} ID; reg { name="SHA Accelerator Mode"; @@ -53,7 +53,7 @@ reg { desc = "SHA is in SHA512, mailbox mode"; }; }; - sw=rw; hw=r; swwe=valid_user; swmod=true; encode = sha_cmd_e;} MODE[2]=0; + sw=rw; hw=r; swwe=valid_id; swmod=true; encode = sha_cmd_e;} MODE[2]=0; field { name="Endianness Toggle for SHA in mailbox mode"; desc="Default behavior assumes that data in mailbox is little endian, @@ -61,7 +61,7 @@ reg { When set to 1, data from the mailbox will be loaded into SHA as-is. [br]Caliptra Access: RW [br]SOC Access: RW"; - sw=rw; hw=r; swwe=valid_user;} ENDIAN_TOGGLE=0; + sw=rw; hw=r; swwe=valid_id;} ENDIAN_TOGGLE=0; } MODE; reg { @@ -70,7 +70,7 @@ reg { Start Address must be dword aligned. [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=r; swwe=valid_user;} ADDR[32]=0; + field {sw=rw; hw=r; swwe=valid_id;} ADDR[32]=0; } START_ADDRESS; reg { @@ -78,7 +78,7 @@ reg { desc="The length of data to be processed in bytes. [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=r; swwe=valid_user;} LENGTH[32]=0; + field {sw=rw; hw=r; swwe=valid_id;} LENGTH[32]=0; } DLEN; reg { @@ -86,7 +86,7 @@ reg { desc="Data in register for SHA Streaming function [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=na; swwe=valid_user; swmod=true;} DATAIN[32]=0; + field {sw=rw; hw=na; swwe=valid_id; swmod=true;} DATAIN[32]=0; } DATAIN; reg { @@ -95,7 +95,7 @@ reg { For the Mailbox SHA Function, indicates that the SHA can begin execution. [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=r; hwclr; swwe=valid_user;} EXECUTE=0; + field {sw=rw; hw=r; hwclr; swwe=valid_id;} EXECUTE=0; } EXECUTE; reg { diff --git a/src/soc_ifc/rtl/sha512_acc_top.sv b/src/soc_ifc/rtl/sha512_acc_top.sv index 6445b4f7b..810fcc5c4 100644 --- a/src/soc_ifc/rtl/sha512_acc_top.sv +++ b/src/soc_ifc/rtl/sha512_acc_top.sv @@ -24,7 +24,7 @@ module sha512_acc_top input logic rst_b, input logic cptra_pwrgood, - // Incoming request from ahb or apb + // Incoming request from ahb or axi input logic req_dv, output logic req_hold, input soc_ifc_req_t req_data, @@ -164,19 +164,19 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); end // reg_update //SHA API - //Acquire the lock and store the user - always_comb hwif_in.USER.USER.next = req_data.user; + //Acquire the lock and store the id + always_comb hwif_in.ID.ID.next = 32'(req_data.id); //Detect the lock getting set when swmod is asserted and lock is 0 and it's not a write //Since this lock is cleared by writing, the swmod asserts on write attempts too, but we only want to set lock on read when value is 0 always_comb lock_set = ~hwif_out.LOCK.LOCK.value & hwif_out.LOCK.LOCK.swmod & ~req_data.write; always_comb hwif_in.lock_set = lock_set; - //check the requesting user: + //check the requesting id: //don't update SHA registers if lock hasn't been acquired //if uc has the lock, check that this request is from uc - //if soc has the lock, check that this request is from soc and user attributes match - always_comb hwif_in.valid_user = hwif_out.LOCK.LOCK.value & ((~soc_has_lock & ~req_data.soc_req) | - (soc_has_lock & req_data.soc_req & (req_data.user == hwif_out.USER.USER.value))); + //if soc has the lock, check that this request is from soc and id attributes match + always_comb hwif_in.valid_id = hwif_out.LOCK.LOCK.value & ((~soc_has_lock & ~req_data.soc_req) | + (soc_has_lock & req_data.soc_req & (req_data.id == hwif_out.ID.ID.value[SOC_IFC_ID_W-1:0]))); always_comb hwif_in.soc_req = req_data.soc_req; always_comb hwif_in.STATUS.SOC_HAS_LOCK.next = soc_has_lock; @@ -187,7 +187,7 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); always_comb streaming_mode = ~mode[1] | soc_has_lock; always_comb mailbox_mode = mode[1] & ~soc_has_lock; //Detect writes to datain register - always_comb datain_write = hwif_in.valid_user & hwif_out.DATAIN.DATAIN.swmod; + always_comb datain_write = hwif_in.valid_id & hwif_out.DATAIN.DATAIN.swmod; always_comb execute_set = hwif_out.EXECUTE.EXECUTE.value; //When we reach the end of a block we indicate block full @@ -400,7 +400,7 @@ sha512_acc_csr i_sha512_acc_csr ( .s_cpuif_req_is_wr (req_data.write), .s_cpuif_addr (req_data.addr[SHA512_ACC_CSR_ADDR_WIDTH-1:0]), .s_cpuif_wr_data (req_data.wdata), - .s_cpuif_wr_biten ('1), + .s_cpuif_wr_biten ('1),// FIXME .s_cpuif_req_stall_wr( ), .s_cpuif_req_stall_rd( ), .s_cpuif_rd_ack ( ), diff --git a/src/soc_ifc/rtl/soc_ifc_arb.sv b/src/soc_ifc/rtl/soc_ifc_arb.sv index 8660009a9..36913a531 100644 --- a/src/soc_ifc/rtl/soc_ifc_arb.sv +++ b/src/soc_ifc/rtl/soc_ifc_arb.sv @@ -15,13 +15,13 @@ module soc_ifc_arb import soc_ifc_pkg::*; #( - parameter APB_USER_WIDTH = 32 + parameter AXI_ID_WIDTH = 32 )( input logic clk, input logic rst_b, - input logic [4:0][APB_USER_WIDTH-1:0] valid_mbox_users, - input logic valid_fuse_user, + input logic [4:0][AXI_ID_WIDTH-1:0] valid_mbox_ids, + input logic valid_fuse_id, //UC inf input logic uc_req_dv, output logic uc_req_hold, @@ -48,6 +48,13 @@ module soc_ifc_arb output soc_ifc_req_t sha_req_data, input logic [SOC_IFC_DATA_W-1:0] sha_rdata, input logic sha_error, + // AXI DMA INF + output logic dma_reg_req_dv, + output soc_ifc_req_t dma_reg_req_data, + input logic dma_reg_req_hold, + input logic [SOC_IFC_DATA_W-1:0] dma_reg_rdata, + input logic dma_reg_error, + //SOC IFC REG inf output logic soc_ifc_reg_req_dv, input logic soc_ifc_reg_req_hold, @@ -66,32 +73,38 @@ logic req_collision; logic soc_mbox_req; logic soc_reg_req; logic soc_sha_req; +logic soc_dma_req; logic uc_mbox_req; logic uc_mbox_reg_req; logic uc_mbox_dir_req; logic uc_reg_req; logic uc_sha_req; +logic uc_dma_req; //grant for each request logic soc_mbox_gnt; logic soc_reg_gnt; logic soc_sha_gnt; +logic soc_dma_gnt; logic uc_mbox_gnt; logic uc_reg_gnt; logic uc_sha_gnt; +logic uc_dma_gnt; //track in-progress grants logic soc_mbox_req_ip; logic soc_reg_req_ip; logic soc_sha_req_ip; +logic soc_dma_req_ip; logic uc_mbox_req_ip; logic uc_reg_req_ip; logic uc_sha_req_ip; +logic uc_dma_req_ip; -//filter mailbox requests by pauser +//filter mailbox requests by id logic valid_mbox_req; @@ -104,10 +117,12 @@ always_ff @(posedge clk or negedge rst_b) begin soc_mbox_req_ip <= '0; soc_reg_req_ip <= '0; soc_sha_req_ip <= '0; + soc_dma_req_ip <= '0; uc_mbox_req_ip <= '0; uc_reg_req_ip <= '0; uc_sha_req_ip <= '0; + uc_dma_req_ip <= '0; end else begin soc_has_priority <= toggle_priority ? ~soc_has_priority : soc_has_priority; @@ -115,10 +130,12 @@ always_ff @(posedge clk or negedge rst_b) begin soc_mbox_req_ip <= soc_mbox_gnt & mbox_req_hold; soc_reg_req_ip <= soc_reg_gnt & soc_ifc_reg_req_hold; soc_sha_req_ip <= soc_sha_gnt & sha_req_hold; + soc_dma_req_ip <= soc_dma_gnt & dma_reg_req_hold; uc_mbox_req_ip <= uc_mbox_gnt & mbox_req_hold; uc_reg_req_ip <= uc_reg_gnt & soc_ifc_reg_req_hold; uc_sha_req_ip <= uc_sha_gnt & sha_req_hold; + uc_dma_req_ip <= uc_dma_gnt & dma_reg_req_hold; end end @@ -137,37 +154,43 @@ always_comb uc_mbox_dir_req = (uc_req_dv & (uc_req_data.addr inside {[MBOX_DIR_S //SoC requests to mailbox always_comb soc_mbox_req = (valid_mbox_req & (soc_req_data.addr inside {[MBOX_REG_START_ADDR:MBOX_REG_END_ADDR]})); //Requests to arch/fuse register block -//Ensure that requests to fuse block match the appropriate user value +//Ensure that requests to fuse block match the appropriate id value always_comb uc_reg_req = (uc_req_dv & (uc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]})); always_comb soc_reg_req = (soc_req_dv & (soc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]}) & - (~(soc_req_data.addr inside {[SOC_IFC_FUSE_START_ADDR:SOC_IFC_FUSE_END_ADDR]}) | valid_fuse_user)); + (~(soc_req_data.addr inside {[SOC_IFC_FUSE_START_ADDR:SOC_IFC_FUSE_END_ADDR]}) | valid_fuse_id)); //Requests to SHA always_comb uc_sha_req = (uc_req_dv & (uc_req_data.addr inside {[SHA_REG_START_ADDR:SHA_REG_END_ADDR]})); always_comb soc_sha_req = (soc_req_dv & (soc_req_data.addr inside {[SHA_REG_START_ADDR:SHA_REG_END_ADDR]})); -//Check if SoC request is coming from a valid user -//There are 5 valid pauser registers, check if user attribute matches any of them -//Check if user matches Default Valid User parameter - this user value is always valid +// Requests to DMA +always_comb uc_dma_req = (uc_req_dv & (uc_req_data.addr inside {[DMA_REG_START_ADDR:DMA_REG_END_ADDR]})); +always_comb soc_dma_req = (soc_req_dv & (soc_req_data.addr inside {[DMA_REG_START_ADDR:DMA_REG_END_ADDR]})); + +//Check if SoC request is coming from a valid id +//There are 5 valid id registers, check if id attribute matches any of them +//Check if id matches Default Valid id parameter - this id value is always valid always_comb begin valid_mbox_req = '0; for (int i=0; i < 5; i++) begin - valid_mbox_req |= soc_req_dv & (soc_req_data.user == valid_mbox_users[i]); + valid_mbox_req |= soc_req_dv & (soc_req_data.id == valid_mbox_ids[i]); end - valid_mbox_req |= soc_req_dv & (soc_req_data.user == CPTRA_DEF_MBOX_VALID_PAUSER); + valid_mbox_req |= soc_req_dv & (soc_req_data.id == CPTRA_DEF_MBOX_VALID_AXI_ID[SOC_IFC_ID_W-1:0]); end //check for collisions //don't toggle priority if the request was held always_comb req_collision = (uc_mbox_req & soc_mbox_req & ~mbox_req_hold) | (uc_reg_req & soc_reg_req & ~soc_ifc_reg_req_hold) | - (uc_sha_req & soc_sha_req & ~sha_req_hold); + (uc_sha_req & soc_sha_req & ~sha_req_hold) | + (uc_dma_req & soc_dma_req & ~dma_reg_req_hold); //drive the dv to the appropriate destination if either client is trying to always_comb mbox_req_dv = uc_mbox_reg_req | soc_mbox_req; always_comb mbox_dir_req_dv = uc_mbox_dir_req & uc_mbox_gnt; always_comb soc_ifc_reg_req_dv = uc_reg_req | soc_reg_req; always_comb sha_req_dv = uc_sha_req | soc_sha_req; +always_comb dma_reg_req_dv = uc_dma_req | soc_dma_req; //determine which requests get granted //if a request is colliding with another, grant the one with priority @@ -176,10 +199,12 @@ always_comb sha_req_dv = uc_sha_req | soc_sha_req; always_comb soc_mbox_gnt = soc_mbox_req & (~uc_mbox_req | soc_has_priority) & ~uc_mbox_req_ip; always_comb soc_reg_gnt = soc_reg_req & (~uc_reg_req | soc_has_priority) & ~uc_reg_req_ip; always_comb soc_sha_gnt = soc_sha_req & (~uc_sha_req | soc_has_priority) & ~uc_sha_req_ip; +always_comb soc_dma_gnt = soc_dma_req & (~uc_dma_req | soc_has_priority) & ~uc_dma_req_ip; always_comb uc_mbox_gnt = uc_mbox_req & (~soc_mbox_req | uc_has_priority) & ~soc_mbox_req_ip; always_comb uc_reg_gnt = uc_reg_req & (~soc_reg_req | uc_has_priority) & ~soc_reg_req_ip; always_comb uc_sha_gnt = uc_sha_req & (~soc_sha_req | uc_has_priority) & ~soc_sha_req_ip; +always_comb uc_dma_gnt = uc_dma_req & (~soc_dma_req | uc_has_priority) & ~soc_dma_req_ip; //drive the appropriate request to each destination always_comb mbox_req_data = ({$bits(soc_ifc_req_t){soc_mbox_gnt}} & soc_req_data) | @@ -191,36 +216,45 @@ always_comb soc_ifc_reg_req_data = ({$bits(soc_ifc_req_t){soc_reg_gnt}} & soc_re always_comb sha_req_data = ({$bits(soc_ifc_req_t){soc_sha_gnt}} & soc_req_data) | ({$bits(soc_ifc_req_t){uc_sha_gnt}} & uc_req_data); +always_comb dma_reg_req_data = ({$bits(soc_ifc_req_t){soc_dma_gnt}} & soc_req_data) | + ({$bits(soc_ifc_req_t){uc_dma_gnt}} & uc_req_data); + //drive the appropriate read data back to uc or soc //AND/OR mux here, assert that requests are always mutex always_comb uc_rdata = ({MBOX_DATA_W{uc_mbox_reg_req}} & mbox_rdata) | ({MBOX_DATA_W{uc_mbox_dir_req}} & mbox_dir_rdata) | ({MBOX_DATA_W{uc_reg_req}} & soc_ifc_reg_rdata) | - ({MBOX_DATA_W{uc_sha_req}} & sha_rdata); + ({MBOX_DATA_W{uc_sha_req}} & sha_rdata) | + ({MBOX_DATA_W{uc_dma_req}} & dma_reg_rdata); always_comb soc_rdata = ({MBOX_DATA_W{soc_mbox_req}} & mbox_rdata) | ({MBOX_DATA_W{soc_reg_req}} & soc_ifc_reg_rdata) | - ({MBOX_DATA_W{soc_sha_req}} & sha_rdata); + ({MBOX_DATA_W{soc_sha_req}} & sha_rdata) | + ({MBOX_DATA_W{soc_dma_req}} & dma_reg_rdata); //drive the appropraite holds back to uc or soc //AND/OR mux here, assert that requests are always mutex always_comb uc_req_hold = (uc_mbox_req & (~uc_mbox_gnt | mbox_req_hold)) | (uc_reg_req & (~uc_reg_gnt | soc_ifc_reg_req_hold)) | - (uc_sha_req & (~ uc_sha_gnt | sha_req_hold)); + (uc_sha_req & (~ uc_sha_gnt | sha_req_hold)) | + (uc_dma_req & (~ uc_dma_gnt | dma_reg_req_hold)); always_comb soc_req_hold = (soc_mbox_req & (~soc_mbox_gnt | mbox_req_hold)) | (soc_reg_req & (~soc_reg_gnt | soc_ifc_reg_req_hold)) | - (soc_sha_req & (~soc_sha_gnt | sha_req_hold)); + (soc_sha_req & (~soc_sha_gnt | sha_req_hold)) | + (soc_dma_req & (~soc_dma_gnt | dma_reg_req_hold)); //Assert error when requested client drives error back, or a request is made that doesn't map to any of the clients always_comb uc_error = (uc_mbox_gnt & mbox_error) | (uc_reg_gnt & soc_ifc_reg_error) | (uc_sha_gnt & sha_error) | - (uc_req_dv & ~(uc_mbox_req | uc_reg_req | uc_sha_req)); + (uc_dma_gnt & dma_reg_error) | + (uc_req_dv & ~(uc_mbox_req | uc_reg_req | uc_sha_req | uc_dma_req)); always_comb soc_error = (soc_mbox_gnt & mbox_error) | (soc_reg_gnt & soc_ifc_reg_error) | (soc_sha_gnt & sha_error) | - (soc_req_dv & ~(soc_mbox_req | soc_reg_req | soc_sha_req)); + (soc_dma_gnt & dma_reg_error) | + (soc_req_dv & ~(soc_mbox_req | soc_reg_req | soc_sha_req | soc_dma_req)); endmodule diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl index 048bcb6c4..7bcbb7dad 100644 --- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl @@ -165,46 +165,46 @@ reg { } CPTRA_SECURITY_STATE; reg { - name = "Valid User Registers"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. Only valid once LOCK is set. + name = "Valid ID Registers"; + desc = "Valid AXI ID attributes for requests from SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - Read-Only once locked by PAUSER_LOCK."; - field {sw=rw; hw=r; swwel;resetsignal = cptra_rst_b;} PAUSER[32]=0xFFFF_FFFF; - } CPTRA_MBOX_VALID_PAUSER[5]; + Read-Only once locked by AXI_ID_LOCK."; + field {sw=rw; hw=r; swwel;resetsignal = cptra_rst_b;} AXI_ID[32]=0xFFFF_FFFF; + } CPTRA_MBOX_VALID_AXI_ID[5]; //FIXME: Should LOCK be W1 here? reg { - name = "Valid User Register Lock"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. - [br]Each bit corresponds to locking the associated MBOX_VALID_PAUSER register. - [br]Associated MBOX_VALID_PAUSER register is only valid once locked by this bit. + name = "Valid ID Register Lock"; + desc = "Valid AXI_ID attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated MBOX_VALID_AXI_ID register. + [br]Associated MBOX_VALID_AXI_ID register is only valid once locked by this bit. [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} LOCK=0; - } CPTRA_MBOX_PAUSER_LOCK[5]; + } CPTRA_MBOX_AXI_ID_LOCK[5]; reg { - name = "Valid User for TRNG"; - desc = "Valid PAUSER attributes for TRNG on SoC APB Interface. Only valid once LOCK is set. + name = "Valid ID for TRNG"; + desc = "Valid AXI ID attributes for TRNG on SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - [br]Read-Only once locked by TRNG_PAUSER_LOCK."; - field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} PAUSER[32]=0xFFFF_FFFF; - } CPTRA_TRNG_VALID_PAUSER; + [br]Read-Only once locked by TRNG_AXI_ID_LOCK."; + field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} AXI_ID[32]=0xFFFF_FFFF; + } CPTRA_TRNG_VALID_AXI_ID; reg { - name = "Valid User for TRNG PAUSER Lock"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. - [br]Each bit corresponds to locking the associated TRNG_VALID_PAUSER register. - [br]Associated TRNG_VALID_PAUSER register is only valid once locked by this bit. + name = "Valid ID for TRNG AXI_ID Lock"; + desc = "Valid AXI ID attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated TRNG_VALID_AXI_ID register. + [br]Associated TRNG_VALID_AXI_ID register is only valid once locked by this bit. [br]Caliptra FW RW access for survivability but cannot unlock once locked [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal=cptra_rst_b;} LOCK=0; - } CPTRA_TRNG_PAUSER_LOCK; + } CPTRA_TRNG_AXI_ID_LOCK; reg { name = "TRNG Data"; @@ -397,25 +397,25 @@ reg { } CPTRA_WDT_STATUS; reg { - name = "Valid User for FUSE"; - desc = "Valid PAUSER attributes for FUSE on SoC APB Interface. Only valid once LOCK is set. + name = "Valid ID for FUSE"; + desc = "Valid AXI ID attributes for FUSE on SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - [br]Read-Only once locked by FUSE_PAUSER_LOCK."; - field {sw=rw; hw=r; swwel; resetsignal = cptra_pwrgood;} PAUSER[32]=0xFFFF_FFFF; - } CPTRA_FUSE_VALID_PAUSER; + [br]Read-Only once locked by FUSE_AXI_ID_LOCK."; + field {sw=rw; hw=r; swwel; resetsignal = cptra_pwrgood;} AXI_ID[32]=0xFFFF_FFFF; + } CPTRA_FUSE_VALID_AXI_ID; reg { - name = "Valid User for FUSE PAUSER Lock"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. - [br]Each bit corresponds to locking the associated FUSE_VALID_PAUSER register. - [br]Associated FUSE_VALID_PAUSER register is only valid once locked by this bit. + name = "Valid ID for FUSE AXI_ID Lock"; + desc = "Valid AXI_ID attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated FUSE_VALID_AXI_ID register. + [br]Associated FUSE_VALID_AXI_ID register is only valid once locked by this bit. [br]Caliptra FW RW access for survivability but cannot unlock once locked [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal=cptra_pwrgood;} LOCK=0; - } CPTRA_FUSE_PAUSER_LOCK; + } CPTRA_FUSE_AXI_ID_LOCK; reg { name = "Caliptra WDT1 Config"; diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv index 8934bdb55..96bafb17c 100644 --- a/src/soc_ifc/rtl/soc_ifc_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv @@ -15,13 +15,15 @@ `ifndef SOC_IFC_PKG `define SOC_IFC_PKG -`include "caliptra_top_reg_defines.svh" +`include "config_defines.svh" +`include "caliptra_reg_defines.svh" package soc_ifc_pkg; parameter SOC_IFC_ADDR_W = 18; parameter SOC_IFC_DATA_W = 32; parameter SOC_IFC_USER_W = 32; + parameter SOC_IFC_ID_W = `CALIPTRA_AXI_ID_WIDTH; parameter MBOX_SIZE_KB = 128; parameter MBOX_SIZE_BYTES = MBOX_SIZE_KB * 1024; @@ -32,6 +34,10 @@ package soc_ifc_pkg; parameter MBOX_DEPTH = (MBOX_SIZE_KB * 1024 * 8) / MBOX_DATA_W; parameter MBOX_ADDR_W = $clog2(MBOX_DEPTH); + parameter CPTRA_AXI_DMA_DATA_WIDTH = 32; + parameter CPTRA_AXI_DMA_ID_WIDTH = 5; // FIXME related to CALIPTRA_AXI_ID_WIDTH? + parameter CPTRA_AXI_DMA_USER_WIDTH = 32; + parameter WDT_TIMEOUT_PERIOD_NUM_DWORDS = 2; parameter WDT_TIMEOUT_PERIOD_W = WDT_TIMEOUT_PERIOD_NUM_DWORDS * 32; @@ -40,23 +46,25 @@ package soc_ifc_pkg; //memory map parameter MBOX_DIR_START_ADDR = 32'h0000_0000; parameter MBOX_DIR_END_ADDR = 32'h0001_FFFF; - parameter MBOX_REG_START_ADDR = `CALIPTRA_TOP_REG_MBOX_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET; + parameter MBOX_REG_START_ADDR = `CLP_MBOX_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET; parameter MBOX_REG_END_ADDR = MBOX_REG_START_ADDR + 32'h0000_0FFF; - parameter SHA_REG_START_ADDR = `CALIPTRA_TOP_REG_SHA512_ACC_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET; + parameter SHA_REG_START_ADDR = `CLP_SHA512_ACC_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET; parameter SHA_REG_END_ADDR = SHA_REG_START_ADDR + 32'h0000_0FFF; - parameter SOC_IFC_REG_START_ADDR = `CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR - SOC_IFC_REG_OFFSET; + parameter DMA_REG_START_ADDR = `CLP_AXI_DMA_REG_BASE_ADDR - SOC_IFC_REG_OFFSET; + parameter DMA_REG_END_ADDR = DMA_REG_START_ADDR + 32'h0000_0FFF; + parameter SOC_IFC_REG_START_ADDR = `CLP_SOC_IFC_REG_BASE_ADDR - SOC_IFC_REG_OFFSET; parameter SOC_IFC_REG_END_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_FFFF; parameter SOC_IFC_FUSE_START_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_0200; parameter SOC_IFC_FUSE_END_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_05FF; - //Valid PAUSER - //Lock the PAUSER values from integration time - parameter [4:0] CPTRA_SET_MBOX_PAUSER_INTEG = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; - parameter [4:0][31:0] CPTRA_MBOX_VALID_PAUSER = {32'h4444_4444, 32'h3333_3333, 32'h2222_2222, 32'h1111_1111, 32'h0000_0000}; - parameter [31:0] CPTRA_DEF_MBOX_VALID_PAUSER = 32'hFFFF_FFFF; + //Valid AXI_ID + //Lock the AXI_ID values from integration time + parameter [4:0] CPTRA_SET_MBOX_AXI_ID_INTEG = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; + parameter [4:0][31:0] CPTRA_MBOX_VALID_AXI_ID = {32'h4444_4444, 32'h3333_3333, 32'h2222_2222, 32'h1111_1111, 32'h0000_0000}; + parameter [31:0] CPTRA_DEF_MBOX_VALID_AXI_ID = 32'hFFFF_FFFF; - parameter CPTRA_SET_FUSE_PAUSER_INTEG = 1'b0; - parameter [31:0] CPTRA_FUSE_VALID_PAUSER = 32'h0000_0000; + parameter CPTRA_SET_FUSE_AXI_ID_INTEG = 1'b0; + parameter [31:0] CPTRA_FUSE_VALID_AXI_ID = 32'h0000_0000; //DMI Register encodings //Read only registers @@ -118,11 +126,13 @@ package soc_ifc_pkg; //Any request into soc ifc block typedef struct packed { - logic [SOC_IFC_ADDR_W-1:0] addr; - logic [SOC_IFC_DATA_W-1:0] wdata; - logic [SOC_IFC_USER_W-1:0] user; - logic write; - logic soc_req; + logic [SOC_IFC_ADDR_W-1:0] addr; + logic [SOC_IFC_DATA_W-1:0] wdata; + logic [SOC_IFC_DATA_W/8-1:0] wstrb; +// logic [SOC_IFC_USER_W-1:0] user; + logic [SOC_IFC_ID_W -1:0] id; + logic write; + logic soc_req; } soc_ifc_req_t; // ECC protected data typedef struct packed { diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index 60e85ee1f..353d469a6 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -77,10 +77,10 @@ module soc_ifc_reg ( logic CPTRA_FLOW_STATUS; logic CPTRA_RESET_REASON; logic CPTRA_SECURITY_STATE; - logic [5-1:0]CPTRA_MBOX_VALID_PAUSER; - logic [5-1:0]CPTRA_MBOX_PAUSER_LOCK; - logic CPTRA_TRNG_VALID_PAUSER; - logic CPTRA_TRNG_PAUSER_LOCK; + logic [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + logic [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + logic CPTRA_TRNG_VALID_AXI_ID; + logic CPTRA_TRNG_AXI_ID_LOCK; logic [12-1:0]CPTRA_TRNG_DATA; logic CPTRA_TRNG_CTRL; logic CPTRA_TRNG_STATUS; @@ -101,8 +101,8 @@ module soc_ifc_reg ( logic CPTRA_WDT_TIMER2_CTRL; logic [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD; logic CPTRA_WDT_STATUS; - logic CPTRA_FUSE_VALID_PAUSER; - logic CPTRA_FUSE_PAUSER_LOCK; + logic CPTRA_FUSE_VALID_AXI_ID; + logic CPTRA_FUSE_AXI_ID_LOCK; logic [2-1:0]CPTRA_WDT_CFG; logic CPTRA_iTRNG_ENTROPY_CONFIG_0; logic CPTRA_iTRNG_ENTROPY_CONFIG_1; @@ -195,13 +195,13 @@ module soc_ifc_reg ( decoded_reg_strb.CPTRA_RESET_REASON = cpuif_req_masked & (cpuif_addr == 12'h40); decoded_reg_strb.CPTRA_SECURITY_STATE = cpuif_req_masked & (cpuif_addr == 12'h44); for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); + decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); end for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); + decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); end - decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h70); - decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); + decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID = cpuif_req_masked & (cpuif_addr == 12'h70); + decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); for(int i0=0; i0<12; i0++) begin decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 12'h78 + i0*12'h4); end @@ -234,8 +234,8 @@ module soc_ifc_reg ( decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 12'hfc + i0*12'h4); end decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 12'h104); - decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h108); - decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); + decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID = cpuif_req_masked & (cpuif_addr == 12'h108); + decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); for(int i0=0; i0<2; i0++) begin decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 12'h110 + i0*12'h4); end @@ -440,26 +440,26 @@ module soc_ifc_reg ( struct packed{ logic [31:0] next; logic load_next; - } PAUSER; - } [5-1:0]CPTRA_MBOX_VALID_PAUSER; + } AXI_ID; + } [5-1:0]CPTRA_MBOX_VALID_AXI_ID; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } [5-1:0]CPTRA_MBOX_PAUSER_LOCK; + } [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] next; logic load_next; - } PAUSER; - } CPTRA_TRNG_VALID_PAUSER; + } AXI_ID; + } CPTRA_TRNG_VALID_AXI_ID; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } CPTRA_TRNG_PAUSER_LOCK; + } CPTRA_TRNG_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] next; @@ -580,14 +580,14 @@ module soc_ifc_reg ( struct packed{ logic [31:0] next; logic load_next; - } PAUSER; - } CPTRA_FUSE_VALID_PAUSER; + } AXI_ID; + } CPTRA_FUSE_VALID_AXI_ID; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } CPTRA_FUSE_PAUSER_LOCK; + } CPTRA_FUSE_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] next; @@ -1317,23 +1317,23 @@ module soc_ifc_reg ( struct packed{ struct packed{ logic [31:0] value; - } PAUSER; - } [5-1:0]CPTRA_MBOX_VALID_PAUSER; + } AXI_ID; + } [5-1:0]CPTRA_MBOX_VALID_AXI_ID; struct packed{ struct packed{ logic value; } LOCK; - } [5-1:0]CPTRA_MBOX_PAUSER_LOCK; + } [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] value; - } PAUSER; - } CPTRA_TRNG_VALID_PAUSER; + } AXI_ID; + } CPTRA_TRNG_VALID_AXI_ID; struct packed{ struct packed{ logic value; } LOCK; - } CPTRA_TRNG_PAUSER_LOCK; + } CPTRA_TRNG_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] value; @@ -1433,13 +1433,13 @@ module soc_ifc_reg ( struct packed{ struct packed{ logic [31:0] value; - } PAUSER; - } CPTRA_FUSE_VALID_PAUSER; + } AXI_ID; + } CPTRA_FUSE_VALID_AXI_ID; struct packed{ struct packed{ logic value; } LOCK; - } CPTRA_FUSE_PAUSER_LOCK; + } CPTRA_FUSE_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] value; @@ -2365,93 +2365,93 @@ module soc_ifc_reg ( end assign hwif_out.CPTRA_RESET_REASON.WARM_RESET.value = field_storage.CPTRA_RESET_REASON.WARM_RESET.value; for(genvar i0=0; i0<5; i0++) begin - // Field: soc_ifc_reg.CPTRA_MBOX_VALID_PAUSER[].PAUSER + // Field: soc_ifc_reg.CPTRA_MBOX_VALID_AXI_ID[].AXI_ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; + next_c = field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.swwel)) begin // SW write - next_c = (field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.swwel)) begin // SW write + next_c = (field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.next = next_c; - field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.load_next = load_next_c; + field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.next = next_c; + field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= 32'hffffffff; - end else if(field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.load_next) begin - field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.next; + field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value <= 32'hffffffff; + end else if(field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.load_next) begin + field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value <= field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.next; end end - assign hwif_out.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; + assign hwif_out.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value = field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value; end for(genvar i0=0; i0<5; i0++) begin - // Field: soc_ifc_reg.CPTRA_MBOX_PAUSER_LOCK[].LOCK + // Field: soc_ifc_reg.CPTRA_MBOX_AXI_ID_LOCK[].LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; + next_c = field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.next = next_c; - field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.load_next = load_next_c; + field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.next = next_c; + field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.load_next) begin - field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.next; + field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.load_next) begin + field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.next; end end - assign hwif_out.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; + assign hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value = field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value; end - // Field: soc_ifc_reg.CPTRA_TRNG_VALID_PAUSER.PAUSER + // Field: soc_ifc_reg.CPTRA_TRNG_VALID_AXI_ID.AXI_ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; + next_c = field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_PAUSER.PAUSER.swwel)) begin // SW write - next_c = (field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.swwel)) begin // SW write + next_c = (field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.next = next_c; - field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.load_next = load_next_c; + field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.next = next_c; + field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= 32'hffffffff; - end else if(field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.load_next) begin - field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.next; + field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value <= 32'hffffffff; + end else if(field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.load_next) begin + field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value <= field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.next; end end - assign hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; - // Field: soc_ifc_reg.CPTRA_TRNG_PAUSER_LOCK.LOCK + assign hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value = field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value; + // Field: soc_ifc_reg.CPTRA_TRNG_AXI_ID_LOCK.LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; + next_c = field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_PAUSER_LOCK.LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_AXI_ID_LOCK.LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.next = next_c; - field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.load_next = load_next_c; + field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.next = next_c; + field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.load_next) begin - field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.next; + field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.load_next) begin + field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.next; end end - assign hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; + assign hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value = field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.CPTRA_TRNG_DATA[].DATA always_comb begin @@ -2910,48 +2910,48 @@ module soc_ifc_reg ( end end assign hwif_out.CPTRA_WDT_STATUS.t2_timeout.value = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; - // Field: soc_ifc_reg.CPTRA_FUSE_VALID_PAUSER.PAUSER + // Field: soc_ifc_reg.CPTRA_FUSE_VALID_AXI_ID.AXI_ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; + next_c = field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel)) begin // SW write - next_c = (field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.swwel)) begin // SW write + next_c = (field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next = next_c; - field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next = load_next_c; + field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.next = next_c; + field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= 32'hffffffff; - end else if(field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next) begin - field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next; + field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value <= 32'hffffffff; + end else if(field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.load_next) begin + field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value <= field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.next; end end - assign hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; - // Field: soc_ifc_reg.CPTRA_FUSE_PAUSER_LOCK.LOCK + assign hwif_out.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value = field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value; + // Field: soc_ifc_reg.CPTRA_FUSE_AXI_ID_LOCK.LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; + next_c = field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_AXI_ID_LOCK.LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next = next_c; - field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next = load_next_c; + field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.next = next_c; + field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next) begin - field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next; + field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.load_next) begin + field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.next; end end - assign hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; + assign hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value = field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_CFG[].TIMEOUT always_comb begin @@ -5805,14 +5805,14 @@ module soc_ifc_reg ( assign readback_array[17][3:3] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.scan_mode.next : '0; assign readback_array[17][31:4] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? 28'h0 : '0; for(genvar i0=0; i0<5; i0++) begin - assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value : '0; + assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value : '0; end for(genvar i0=0; i0<5; i0++) begin - assign readback_array[i0*1 + 23][0:0] = (decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value : '0; + assign readback_array[i0*1 + 23][0:0] = (decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value : '0; assign readback_array[i0*1 + 23][31:1] = '0; end - assign readback_array[28][31:0] = (decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value : '0; - assign readback_array[29][0:0] = (decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value : '0; + assign readback_array[28][31:0] = (decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value : '0; + assign readback_array[29][0:0] = (decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value : '0; assign readback_array[29][31:1] = '0; for(genvar i0=0; i0<12; i0++) begin assign readback_array[i0*1 + 30][31:0] = (decoded_reg_strb.CPTRA_TRNG_DATA[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_DATA[i0].DATA.value : '0; @@ -5864,8 +5864,8 @@ module soc_ifc_reg ( assign readback_array[65][0:0] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t1_timeout.value : '0; assign readback_array[65][1:1] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t2_timeout.value : '0; assign readback_array[65][31:2] = '0; - assign readback_array[66][31:0] = (decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value : '0; - assign readback_array[67][0:0] = (decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value : '0; + assign readback_array[66][31:0] = (decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value : '0; + assign readback_array[67][0:0] = (decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value : '0; assign readback_array[67][31:1] = '0; for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 68][31:0] = (decoded_reg_strb.CPTRA_WDT_CFG[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value : '0; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh index c74221ba9..ebd06c48a 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh @@ -265,8 +265,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_PAUSER COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_ID COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -277,16 +277,16 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_fld_cg with function sample( - input bit [32-1:0] PAUSER + covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_fld_cg with function sample( + input bit [32-1:0] AXI_ID ); option.per_instance = 1; - PAUSER_cp : coverpoint PAUSER; + AXI_ID_cp : coverpoint AXI_ID; endgroup - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_PAUSER_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_ID_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -297,7 +297,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; @@ -305,8 +305,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_PAUSER COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_ID COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -317,11 +317,11 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_fld_cg with function sample( - input bit [32-1:0] PAUSER + covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_fld_cg with function sample( + input bit [32-1:0] AXI_ID ); option.per_instance = 1; - PAUSER_cp : coverpoint PAUSER { + AXI_ID_cp : coverpoint AXI_ID { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -331,8 +331,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_PAUSER_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_ID_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -343,7 +343,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; @@ -789,8 +789,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_PAUSER COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_ID COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -801,11 +801,11 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_fld_cg with function sample( - input bit [32-1:0] PAUSER + covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_fld_cg with function sample( + input bit [32-1:0] AXI_ID ); option.per_instance = 1; - PAUSER_cp : coverpoint PAUSER { + AXI_ID_cp : coverpoint AXI_ID { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -815,8 +815,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_PAUSER_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_ID_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -827,7 +827,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 15d1f534f..2172b382c 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -84,35 +84,35 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__in_t; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__in_t PAUSER; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__in_t; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__in_t AXI_ID; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__in_t; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__in_t; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__in_t PAUSER; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__in_t; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__in_t AXI_ID; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__in_t; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__in_t; typedef struct packed{ logic swwe; @@ -217,19 +217,19 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__in_t; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__in_t PAUSER; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__in_t; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__in_t AXI_ID; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__in_t; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__in_t; typedef struct packed{ logic swwel; @@ -439,10 +439,10 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_FLOW_STATUS__in_t CPTRA_FLOW_STATUS; soc_ifc_reg__CPTRA_RESET_REASON__in_t CPTRA_RESET_REASON; soc_ifc_reg__CPTRA_SECURITY_STATE__in_t CPTRA_SECURITY_STATE; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__in_t [5-1:0]CPTRA_MBOX_VALID_PAUSER; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__in_t [5-1:0]CPTRA_MBOX_PAUSER_LOCK; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__in_t CPTRA_TRNG_VALID_PAUSER; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__in_t CPTRA_TRNG_PAUSER_LOCK; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__in_t [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__in_t [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__in_t CPTRA_TRNG_VALID_AXI_ID; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__in_t CPTRA_TRNG_AXI_ID_LOCK; soc_ifc_reg__CPTRA_TRNG_DATA__in_t [12-1:0]CPTRA_TRNG_DATA; soc_ifc_reg__CPTRA_TRNG_STATUS__in_t CPTRA_TRNG_STATUS; soc_ifc_reg__CPTRA_FUSE_WR_DONE__in_t CPTRA_FUSE_WR_DONE; @@ -452,8 +452,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_HW_REV_ID__in_t CPTRA_HW_REV_ID; soc_ifc_reg__CPTRA_HW_CONFIG__in_t CPTRA_HW_CONFIG; soc_ifc_reg__CPTRA_WDT_STATUS__in_t CPTRA_WDT_STATUS; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__in_t CPTRA_FUSE_VALID_PAUSER; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__in_t CPTRA_FUSE_PAUSER_LOCK; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__in_t CPTRA_FUSE_VALID_AXI_ID; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__in_t CPTRA_FUSE_AXI_ID_LOCK; soc_ifc_reg__fuse_uds_seed__in_t [12-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__in_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__in_t [12-1:0]fuse_key_manifest_pk_hash; @@ -575,35 +575,35 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__out_t; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__out_t PAUSER; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__out_t; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__out_t AXI_ID; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__out_t; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__out_t; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__out_t; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__out_t PAUSER; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__out_t; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__out_t AXI_ID; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__out_t; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__out_t; typedef struct packed{ logic swacc; @@ -749,19 +749,19 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__out_t; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__out_t PAUSER; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__out_t; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__out_t AXI_ID; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__out_t; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__out_t; typedef struct packed{ logic [31:0] value; @@ -980,10 +980,10 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_BOOT_STATUS__out_t CPTRA_BOOT_STATUS; soc_ifc_reg__CPTRA_FLOW_STATUS__out_t CPTRA_FLOW_STATUS; soc_ifc_reg__CPTRA_RESET_REASON__out_t CPTRA_RESET_REASON; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__out_t [5-1:0]CPTRA_MBOX_VALID_PAUSER; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__out_t [5-1:0]CPTRA_MBOX_PAUSER_LOCK; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__out_t CPTRA_TRNG_VALID_PAUSER; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__out_t CPTRA_TRNG_PAUSER_LOCK; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__out_t [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__out_t [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__out_t CPTRA_TRNG_VALID_AXI_ID; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__out_t CPTRA_TRNG_AXI_ID_LOCK; soc_ifc_reg__CPTRA_TRNG_DATA__out_t [12-1:0]CPTRA_TRNG_DATA; soc_ifc_reg__CPTRA_TRNG_CTRL__out_t CPTRA_TRNG_CTRL; soc_ifc_reg__CPTRA_TRNG_STATUS__out_t CPTRA_TRNG_STATUS; @@ -1001,8 +1001,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL__out_t CPTRA_WDT_TIMER2_CTRL; soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD__out_t [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD; soc_ifc_reg__CPTRA_WDT_STATUS__out_t CPTRA_WDT_STATUS; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__out_t CPTRA_FUSE_VALID_PAUSER; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__out_t CPTRA_FUSE_PAUSER_LOCK; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__out_t CPTRA_FUSE_VALID_AXI_ID; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__out_t CPTRA_FUSE_AXI_ID_LOCK; soc_ifc_reg__fuse_uds_seed__out_t [12-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__out_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__out_t [12-1:0]fuse_key_manifest_pk_hash; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh index 4274380d0..ff26ec47f 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh @@ -320,8 +320,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -329,24 +329,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*PAUSER*/ ); + this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); end endfunction - function void soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER::sample_values(); + function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( PAUSER.get_mirrored_value() ); + this.fld_cg.sample( AXI_ID.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -361,7 +361,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end @@ -370,8 +370,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -379,24 +379,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*PAUSER*/ ); + this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); end endfunction - function void soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER::sample_values(); + function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( PAUSER.get_mirrored_value() ); + this.fld_cg.sample( AXI_ID.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -411,7 +411,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end @@ -934,8 +934,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -943,24 +943,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*PAUSER*/ ); + this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); end endfunction - function void soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER::sample_values(); + function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( PAUSER.get_mirrored_value() ); + this.fld_cg.sample( AXI_ID.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -975,7 +975,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index b111caa8c..da67c9fe0 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -409,17 +409,17 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__CPTRA_SECURITY_STATE - // Reg - soc_ifc_reg::CPTRA_MBOX_VALID_PAUSER - class soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_MBOX_VALID_AXI_ID + class soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_bit_cg PAUSER_bit_cg[32]; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_fld_cg fld_cg; - rand uvm_reg_field PAUSER; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_fld_cg fld_cg; + rand uvm_reg_field AXI_ID; - function new(string name = "soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER"); + function new(string name = "soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -429,27 +429,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.PAUSER = new("PAUSER"); - this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_ID = new("AXI_ID"); + this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new(); + foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER + endclass : soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID - // Reg - soc_ifc_reg::CPTRA_MBOX_PAUSER_LOCK - class soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_MBOX_AXI_ID_LOCK + class soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -467,19 +467,19 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK + endclass : soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK - // Reg - soc_ifc_reg::CPTRA_TRNG_VALID_PAUSER - class soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_TRNG_VALID_AXI_ID + class soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_bit_cg PAUSER_bit_cg[32]; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_fld_cg fld_cg; - rand uvm_reg_field PAUSER; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_fld_cg fld_cg; + rand uvm_reg_field AXI_ID; - function new(string name = "soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER"); + function new(string name = "soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -489,27 +489,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.PAUSER = new("PAUSER"); - this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_ID = new("AXI_ID"); + this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new(); + foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER + endclass : soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID - // Reg - soc_ifc_reg::CPTRA_TRNG_PAUSER_LOCK - class soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_TRNG_AXI_ID_LOCK + class soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -527,7 +527,7 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK + endclass : soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK // Reg - soc_ifc_reg::CPTRA_TRNG_DATA class soc_ifc_reg__CPTRA_TRNG_DATA extends uvm_reg; @@ -1164,17 +1164,17 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__CPTRA_WDT_STATUS - // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_PAUSER - class soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_AXI_ID + class soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_bit_cg PAUSER_bit_cg[32]; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_fld_cg fld_cg; - rand uvm_reg_field PAUSER; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_fld_cg fld_cg; + rand uvm_reg_field AXI_ID; - function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER"); + function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1184,27 +1184,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.PAUSER = new("PAUSER"); - this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_ID = new("AXI_ID"); + this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new(); + foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER + endclass : soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID - // Reg - soc_ifc_reg::CPTRA_FUSE_PAUSER_LOCK - class soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_FUSE_AXI_ID_LOCK + class soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1222,7 +1222,7 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK + endclass : soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK // Reg - soc_ifc_reg::CPTRA_WDT_CFG class soc_ifc_reg__CPTRA_WDT_CFG extends uvm_reg; @@ -3731,10 +3731,10 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__CPTRA_FLOW_STATUS CPTRA_FLOW_STATUS; rand soc_ifc_reg__CPTRA_RESET_REASON CPTRA_RESET_REASON; rand soc_ifc_reg__CPTRA_SECURITY_STATE CPTRA_SECURITY_STATE; - rand soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER CPTRA_MBOX_VALID_PAUSER[5]; - rand soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK CPTRA_MBOX_PAUSER_LOCK[5]; - rand soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER CPTRA_TRNG_VALID_PAUSER; - rand soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK CPTRA_TRNG_PAUSER_LOCK; + rand soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID CPTRA_MBOX_VALID_AXI_ID[5]; + rand soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK CPTRA_MBOX_AXI_ID_LOCK[5]; + rand soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID CPTRA_TRNG_VALID_AXI_ID; + rand soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK CPTRA_TRNG_AXI_ID_LOCK; rand soc_ifc_reg__CPTRA_TRNG_DATA CPTRA_TRNG_DATA[12]; rand soc_ifc_reg__CPTRA_TRNG_CTRL CPTRA_TRNG_CTRL; rand soc_ifc_reg__CPTRA_TRNG_STATUS CPTRA_TRNG_STATUS; @@ -3755,8 +3755,8 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL CPTRA_WDT_TIMER2_CTRL; rand soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[2]; rand soc_ifc_reg__CPTRA_WDT_STATUS CPTRA_WDT_STATUS; - rand soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER CPTRA_FUSE_VALID_PAUSER; - rand soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK CPTRA_FUSE_PAUSER_LOCK; + rand soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID CPTRA_FUSE_VALID_AXI_ID; + rand soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK CPTRA_FUSE_AXI_ID_LOCK; rand soc_ifc_reg__CPTRA_WDT_CFG CPTRA_WDT_CFG[2]; rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 CPTRA_iTRNG_ENTROPY_CONFIG_0; rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 CPTRA_iTRNG_ENTROPY_CONFIG_1; @@ -3853,30 +3853,30 @@ package soc_ifc_reg_uvm; this.CPTRA_SECURITY_STATE.build(); this.default_map.add_reg(this.CPTRA_SECURITY_STATE, 'h44); - foreach(this.CPTRA_MBOX_VALID_PAUSER[i0]) begin - this.CPTRA_MBOX_VALID_PAUSER[i0] = new($sformatf("CPTRA_MBOX_VALID_PAUSER[%0d]", i0)); - this.CPTRA_MBOX_VALID_PAUSER[i0].configure(this); + foreach(this.CPTRA_MBOX_VALID_AXI_ID[i0]) begin + this.CPTRA_MBOX_VALID_AXI_ID[i0] = new($sformatf("CPTRA_MBOX_VALID_AXI_ID[%0d]", i0)); + this.CPTRA_MBOX_VALID_AXI_ID[i0].configure(this); - this.CPTRA_MBOX_VALID_PAUSER[i0].build(); - this.default_map.add_reg(this.CPTRA_MBOX_VALID_PAUSER[i0], 'h48 + i0*'h4); + this.CPTRA_MBOX_VALID_AXI_ID[i0].build(); + this.default_map.add_reg(this.CPTRA_MBOX_VALID_AXI_ID[i0], 'h48 + i0*'h4); end - foreach(this.CPTRA_MBOX_PAUSER_LOCK[i0]) begin - this.CPTRA_MBOX_PAUSER_LOCK[i0] = new($sformatf("CPTRA_MBOX_PAUSER_LOCK[%0d]", i0)); - this.CPTRA_MBOX_PAUSER_LOCK[i0].configure(this); + foreach(this.CPTRA_MBOX_AXI_ID_LOCK[i0]) begin + this.CPTRA_MBOX_AXI_ID_LOCK[i0] = new($sformatf("CPTRA_MBOX_AXI_ID_LOCK[%0d]", i0)); + this.CPTRA_MBOX_AXI_ID_LOCK[i0].configure(this); - this.CPTRA_MBOX_PAUSER_LOCK[i0].build(); - this.default_map.add_reg(this.CPTRA_MBOX_PAUSER_LOCK[i0], 'h5c + i0*'h4); + this.CPTRA_MBOX_AXI_ID_LOCK[i0].build(); + this.default_map.add_reg(this.CPTRA_MBOX_AXI_ID_LOCK[i0], 'h5c + i0*'h4); end - this.CPTRA_TRNG_VALID_PAUSER = new("CPTRA_TRNG_VALID_PAUSER"); - this.CPTRA_TRNG_VALID_PAUSER.configure(this); + this.CPTRA_TRNG_VALID_AXI_ID = new("CPTRA_TRNG_VALID_AXI_ID"); + this.CPTRA_TRNG_VALID_AXI_ID.configure(this); - this.CPTRA_TRNG_VALID_PAUSER.build(); - this.default_map.add_reg(this.CPTRA_TRNG_VALID_PAUSER, 'h70); - this.CPTRA_TRNG_PAUSER_LOCK = new("CPTRA_TRNG_PAUSER_LOCK"); - this.CPTRA_TRNG_PAUSER_LOCK.configure(this); + this.CPTRA_TRNG_VALID_AXI_ID.build(); + this.default_map.add_reg(this.CPTRA_TRNG_VALID_AXI_ID, 'h70); + this.CPTRA_TRNG_AXI_ID_LOCK = new("CPTRA_TRNG_AXI_ID_LOCK"); + this.CPTRA_TRNG_AXI_ID_LOCK.configure(this); - this.CPTRA_TRNG_PAUSER_LOCK.build(); - this.default_map.add_reg(this.CPTRA_TRNG_PAUSER_LOCK, 'h74); + this.CPTRA_TRNG_AXI_ID_LOCK.build(); + this.default_map.add_reg(this.CPTRA_TRNG_AXI_ID_LOCK, 'h74); foreach(this.CPTRA_TRNG_DATA[i0]) begin this.CPTRA_TRNG_DATA[i0] = new($sformatf("CPTRA_TRNG_DATA[%0d]", i0)); this.CPTRA_TRNG_DATA[i0].configure(this); @@ -3989,16 +3989,16 @@ package soc_ifc_reg_uvm; this.CPTRA_WDT_STATUS.build(); this.default_map.add_reg(this.CPTRA_WDT_STATUS, 'h104); - this.CPTRA_FUSE_VALID_PAUSER = new("CPTRA_FUSE_VALID_PAUSER"); - this.CPTRA_FUSE_VALID_PAUSER.configure(this); + this.CPTRA_FUSE_VALID_AXI_ID = new("CPTRA_FUSE_VALID_AXI_ID"); + this.CPTRA_FUSE_VALID_AXI_ID.configure(this); - this.CPTRA_FUSE_VALID_PAUSER.build(); - this.default_map.add_reg(this.CPTRA_FUSE_VALID_PAUSER, 'h108); - this.CPTRA_FUSE_PAUSER_LOCK = new("CPTRA_FUSE_PAUSER_LOCK"); - this.CPTRA_FUSE_PAUSER_LOCK.configure(this); + this.CPTRA_FUSE_VALID_AXI_ID.build(); + this.default_map.add_reg(this.CPTRA_FUSE_VALID_AXI_ID, 'h108); + this.CPTRA_FUSE_AXI_ID_LOCK = new("CPTRA_FUSE_AXI_ID_LOCK"); + this.CPTRA_FUSE_AXI_ID_LOCK.configure(this); - this.CPTRA_FUSE_PAUSER_LOCK.build(); - this.default_map.add_reg(this.CPTRA_FUSE_PAUSER_LOCK, 'h10c); + this.CPTRA_FUSE_AXI_ID_LOCK.build(); + this.default_map.add_reg(this.CPTRA_FUSE_AXI_ID_LOCK, 'h10c); foreach(this.CPTRA_WDT_CFG[i0]) begin this.CPTRA_WDT_CFG[i0] = new($sformatf("CPTRA_WDT_CFG[%0d]", i0)); this.CPTRA_WDT_CFG[i0].configure(this); diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 119ebacc5..d2d46922a 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -20,11 +20,16 @@ module soc_ifc_top import soc_ifc_pkg::*; import soc_ifc_reg_pkg::*; #( - parameter APB_ADDR_WIDTH = 18 - ,parameter APB_DATA_WIDTH = 32 - ,parameter APB_USER_WIDTH = 32 + parameter AXI_ADDR_WIDTH = 18 + ,parameter AXI_DATA_WIDTH = 32 + ,parameter AXI_ID_WIDTH = 32 + ,parameter AXI_USER_WIDTH = 32 ,parameter AHB_ADDR_WIDTH = 18 ,parameter AHB_DATA_WIDTH = 32 + ,parameter AXIM_ADDR_WIDTH = 48 + ,parameter AXIM_DATA_WIDTH = 32 + ,parameter AXIM_ID_WIDTH = 5 + ,parameter AXIM_USER_WIDTH = 32 ) ( input logic clk, @@ -43,22 +48,17 @@ module soc_ifc_top output logic mailbox_data_avail, output logic mailbox_flow_done, + input logic recovery_data_avail, + input var security_state_t security_state, input logic [1:0][31:0] generic_input_wires, input logic BootFSM_BrkPoint, output logic [1:0][31:0] generic_output_wires, - //SoC APB Interface - input logic [APB_ADDR_WIDTH-1:0] paddr_i, - input logic psel_i, - input logic penable_i, - input logic pwrite_i, - input logic [APB_DATA_WIDTH-1:0] pwdata_i, - input logic [APB_USER_WIDTH-1:0] pauser_i, - output logic pready_o, - output logic [APB_DATA_WIDTH-1:0] prdata_o, - output logic pslverr_o, + //SoC AXI Interface + axi_if.w_sub s_axi_w_if, + axi_if.r_sub s_axi_r_if, //uC AHB Lite Interface input logic [AHB_ADDR_WIDTH-1:0] haddr_i, @@ -73,6 +73,10 @@ module soc_ifc_top output logic hreadyout_o, output logic [AHB_DATA_WIDTH-1:0] hrdata_o, + // AXI Manager INF + axi_if.w_mgr m_axi_w_if, + axi_if.r_mgr m_axi_r_if, + //SoC Interrupts output logic cptra_error_fatal, output logic cptra_error_non_fatal, @@ -83,6 +87,8 @@ module soc_ifc_top output wire soc_ifc_notif_intr, output wire sha_error_intr, output wire sha_notif_intr, + output wire dma_error_intr, + output wire dma_notif_intr, output wire timer_intr, //SRAM interface @@ -130,7 +136,7 @@ module soc_ifc_top //gasket to assemble mailbox request logic soc_req_dv, soc_req_hold; logic soc_req_error; -logic [APB_DATA_WIDTH-1:0] soc_req_rdata; +logic [AXI_DATA_WIDTH-1:0] soc_req_rdata; soc_ifc_req_t soc_req; //gasket to assemble mailbox request @@ -155,6 +161,13 @@ soc_ifc_req_t sha_req_data; logic [SOC_IFC_DATA_W-1:0] sha_rdata; logic sha_error; +//DMA reg inf +logic dma_reg_req_dv; +logic dma_reg_req_hold; +soc_ifc_req_t dma_reg_req_data; +logic [SOC_IFC_DATA_W-1:0] dma_reg_rdata; +logic dma_reg_error; + //mbox reg inf logic soc_ifc_reg_req_dv; logic soc_ifc_reg_req_hold; @@ -168,7 +181,14 @@ logic [MBOX_ADDR_W-1:0] sha_sram_req_addr; mbox_sram_resp_t sha_sram_resp; logic sha_sram_hold; -logic [4:0][APB_USER_WIDTH-1:0] valid_mbox_users; +//DMA SRAM direct inf +logic dma_sram_req_dv; +logic dma_sram_req_hold; +soc_ifc_req_t dma_sram_req_data; +logic [SOC_IFC_DATA_W-1:0] dma_sram_rdata; +logic dma_sram_error; + +logic [4:0][AXI_ID_WIDTH-1:0] valid_mbox_ids; // Pulse signals to trigger interrupts logic uc_mbox_data_avail; @@ -183,8 +203,9 @@ logic sram_double_ecc_error; logic soc_req_mbox_lock; logic [1:0] generic_input_toggle; mbox_protocol_error_t mbox_protocol_error; -logic mbox_inv_user_p; +logic mbox_inv_id_p; +logic uc_mbox_lock; logic iccm_unlock; logic fw_upd_rst_executed; logic fuse_wr_done_reg_write_observed; @@ -224,8 +245,8 @@ logic t2_timeout_p; logic wdt_error_t1_intr_serviced; logic wdt_error_t2_intr_serviced; -logic valid_trng_user; -logic valid_fuse_user; +logic valid_trng_id; +logic valid_fuse_id; boot_fsm_state_e boot_fsm_ps; @@ -260,42 +281,42 @@ soc_ifc_boot_fsm i_soc_ifc_boot_fsm ( always_comb soc_ifc_reg_hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.we = fw_upd_rst_executed; always_comb soc_ifc_reg_hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.next = 1; -//APB Interface -//This module contains the logic for interfacing with the SoC over the APB Interface -//The SoC sends read and write requests using APB Protocol -//This wrapper decodes that protocol and issues requests to the arbitration block -apb_slv_sif #( - .ADDR_WIDTH(APB_ADDR_WIDTH), - .DATA_WIDTH(APB_DATA_WIDTH), - .USER_WIDTH(APB_USER_WIDTH) -) -i_apb_slv_sif_soc_ifc ( - //AMBA APB INF - .PCLK(soc_ifc_clk_cg), - .PRESETn(cptra_noncore_rst_b), - .PADDR(paddr_i), - .PPROT('0), - .PSEL(psel_i), - .PENABLE(penable_i), - .PWRITE(pwrite_i), - .PWDATA(pwdata_i), - .PAUSER(pauser_i), - - .PREADY(pready_o), - .PSLVERR(pslverr_o), - .PRDATA(prdata_o), +//AXI Interface +//This module contains the logic for interfacing with the SoC over the AXI Interface +//The SoC sends read and write requests using AXI Protocol +//This wrapper decodes that protocol, collapses the full-duplex protocol to +// simplex, and issues requests to the soc_ifc arbitration block +axi_sub #( + .AW (AXI_ADDR_WIDTH), + .DW (AXI_DATA_WIDTH), + .UW (AXI_USER_WIDTH), + .IW (AXI_ID_WIDTH ), + .EX_EN(0 ), + .C_LAT(0 ) +) i_axi_sub_sif_soc_ifc ( + .clk (soc_ifc_clk_cg ), + .rst_n(cptra_noncore_rst_b), + + // AXI INF + .s_axi_w_if(s_axi_w_if), + .s_axi_r_if(s_axi_r_if), //COMPONENT INF - .dv(soc_req_dv), - .req_hold(soc_req_hold), - .write(soc_req.write), - .user(soc_req.user), - .wdata(soc_req.wdata), - .addr(soc_req.addr), - .slverr(soc_req_error), - .rdata(soc_req_rdata) + .dv (soc_req_dv ), + .addr (soc_req.addr ), // Byte address + .write (soc_req.write ), + .user (/*soc_req.user*/), + .id (soc_req.id ), + .wdata (soc_req.wdata ), // Requires: Component dwidth == AXI dwidth + .wstrb (soc_req.wstrb ), // Requires: Component dwidth == AXI dwidth + .rdata (soc_req_rdata ), // Requires: Component dwidth == AXI dwidth + .last ( ), // Asserted with final 'dv' of a burst + .hld (soc_req_hold ), + .rd_err(soc_req_error ), + .wr_err(soc_req_error ) ); -//req from apb is for soc always + +//req from axi is for soc always always_comb soc_req.soc_req = 1'b1; //AHB-Lite Interface @@ -335,21 +356,23 @@ i_ahb_slv_sif_soc_ifc ( .rdata(uc_req_rdata) ); -always_comb uc_req.user = '1; +//always_comb uc_req.user = '1; +always_comb uc_req.id = '1; always_comb uc_req.soc_req = 1'b0; +always_comb uc_req.wstrb = {AHB_DATA_WIDTH/8{1'b1}}; //mailbox_arb //This module contains the arbitration logic between SoC and Caliptra uC requests //Requests are serviced using round robin arbitration soc_ifc_arb #( - .APB_USER_WIDTH(APB_USER_WIDTH) + .AXI_ID_WIDTH(AXI_ID_WIDTH) ) i_soc_ifc_arb ( .clk(soc_ifc_clk_cg), .rst_b(cptra_noncore_rst_b), - .valid_mbox_users(valid_mbox_users), - .valid_fuse_user(valid_fuse_user), + .valid_mbox_ids(valid_mbox_ids), + .valid_fuse_id(valid_fuse_id), //UC inf .uc_req_dv(uc_req_dv), .uc_req_hold(uc_req_hold), @@ -376,6 +399,13 @@ soc_ifc_arb #( .sha_req_data(sha_req_data), .sha_rdata(sha_rdata), .sha_error(sha_error), + //DMA inf + .dma_reg_req_dv (dma_reg_req_dv ), + .dma_reg_req_data(dma_reg_req_data), + .dma_reg_req_hold(dma_reg_req_hold), + .dma_reg_rdata (dma_reg_rdata ), + .dma_reg_error (dma_reg_error ), + //FUNC reg inf .soc_ifc_reg_req_dv(soc_ifc_reg_req_dv), .soc_ifc_reg_req_hold(soc_ifc_reg_req_hold), @@ -546,27 +576,27 @@ end always_comb scan_mode_p = scan_mode & ~scan_mode_f; -//Filtering by PAUSER +//Filtering by ID always_comb begin for (int i=0; i<5; i++) begin //once locked, can't be cleared until reset - soc_ifc_reg_hwif_in.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.value; - //lock the writes to valid user field once lock is set - soc_ifc_reg_hwif_in.CPTRA_MBOX_VALID_PAUSER[i].PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.value; - //If integrator set PAUSER values at integration time, pick it up from the define - valid_mbox_users[i] = CPTRA_SET_MBOX_PAUSER_INTEG[i] ? CPTRA_MBOX_VALID_PAUSER[i][APB_USER_WIDTH-1:0] : - soc_ifc_reg_hwif_out.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.value ? - soc_ifc_reg_hwif_out.CPTRA_MBOX_VALID_PAUSER[i].PAUSER.value[APB_USER_WIDTH-1:0] : CPTRA_DEF_MBOX_VALID_PAUSER; + soc_ifc_reg_hwif_in.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value; + //lock the writes to valid id field once lock is set + soc_ifc_reg_hwif_in.CPTRA_MBOX_VALID_AXI_ID[i].AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value; + //If integrator set AXI_ID values at integration time, pick it up from the define + valid_mbox_ids[i] = CPTRA_SET_MBOX_AXI_ID_INTEG[i] ? CPTRA_MBOX_VALID_AXI_ID[i][AXI_ID_WIDTH-1:0] : + soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value ? + soc_ifc_reg_hwif_out.CPTRA_MBOX_VALID_AXI_ID[i].AXI_ID.value[AXI_ID_WIDTH-1:0] : CPTRA_DEF_MBOX_VALID_AXI_ID; end end -//can't write to trng valid user after it is locked -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_PAUSER.PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_PAUSER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; +//can't write to trng valid id after it is locked +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_AXI_ID_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; -//fuse register pauser fields -always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; -always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; +//fuse register AXI ID fields +always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; +always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_AXI_ID_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Can't write to RW-able fuses once fuse_done is set (implies the register is being locked using the fuse_wr_done) @@ -622,16 +652,16 @@ always_comb soc_ifc_reg_hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel = soc always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_WR_DONE.done.swwe = soc_ifc_reg_req_data.soc_req & ~soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//When TRNG_PAUSER_LOCK is one only allow valid users to write to TRNG -//If TRNG_PAUSER_LOCK is zero allow any user to write to TRNG -always_comb valid_trng_user = soc_ifc_reg_req_data.soc_req & (~soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value | - (soc_ifc_reg_req_data.user == soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value[APB_USER_WIDTH-1:0])); +//When TRNG_AXI_ID_LOCK is one only allow valid ids to write to TRNG +//If TRNG_AXI_ID_LOCK is zero allow any id to write to TRNG +always_comb valid_trng_id = soc_ifc_reg_req_data.soc_req & (~soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value | + (soc_ifc_reg_req_data.id == soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0])); -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe = valid_trng_user; +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe = valid_trng_id; always_comb begin for (int i = 0; i < 12; i++) begin - soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.swwe = valid_trng_user; + soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.swwe = valid_trng_id; soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.hwclr = soc_ifc_reg_hwif_out.CPTRA_TRNG_CTRL.clear.value; end end @@ -640,11 +670,11 @@ end always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.hwclr = ~soc_ifc_reg_hwif_out.CPTRA_TRNG_STATUS.DATA_REQ.value; generate - if (CPTRA_SET_FUSE_PAUSER_INTEG) begin - always_comb valid_fuse_user = soc_req_dv & (soc_req.user == CPTRA_FUSE_VALID_PAUSER); + if (CPTRA_SET_FUSE_AXI_ID_INTEG) begin + always_comb valid_fuse_id = soc_req_dv & (soc_req.id == CPTRA_FUSE_VALID_AXI_ID); end else begin - always_comb valid_fuse_user = soc_req_dv & (~soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value | - (soc_req.user == soc_ifc_reg_hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value[APB_USER_WIDTH-1:0])); + always_comb valid_fuse_id = soc_req_dv & (~soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value | + (soc_req.id == soc_ifc_reg_hwif_out.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0])); end endgenerate // Generate a pulse to set the interrupt bit @@ -660,7 +690,7 @@ end always_comb uc_cmd_avail_p = uc_mbox_data_avail & !uc_mbox_data_avail_d; // Pulse input to soc_ifc_reg to set the interrupt status bit and generate interrupt output (if enabled) always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset = 1'b0; // TODO -always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset = mbox_inv_user_p; // All invalid users, or only 'valid user but != mbox_user.user'? +always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset = mbox_inv_id_p; // All invalid ids, or only 'valid id but != mbox_id.id'? always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.hwset = |mbox_protocol_error; // Set by any protocol error violation (mirrors the bits in CPTRA_HW_ERROR_NON_FATAL) always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.hwset = 1'b0; // TODO always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.hwset = iccm_axs_blocked; @@ -692,7 +722,7 @@ soc_ifc_reg i_soc_ifc_reg ( .s_cpuif_req_is_wr(soc_ifc_reg_req_data.write), .s_cpuif_addr(soc_ifc_reg_req_data.addr[SOC_IFC_REG_ADDR_WIDTH-1:0]), .s_cpuif_wr_data(soc_ifc_reg_req_data.wdata), - .s_cpuif_wr_biten('1), + .s_cpuif_wr_biten('1), // FIXME .s_cpuif_req_stall_wr(s_cpuif_req_stall_wr_nc), .s_cpuif_req_stall_rd(s_cpuif_req_stall_rd_nc), .s_cpuif_rd_ack(s_cpuif_rd_ack_nc), @@ -705,13 +735,13 @@ soc_ifc_reg i_soc_ifc_reg ( .hwif_out(soc_ifc_reg_hwif_out) ); -//Mask read data to TRNG DATA when TRNG PAUSER is locked and the requester isn't the correct PAUSER +//Mask read data to TRNG DATA when TRNG AXI_ID is locked and the requester isn't the correct AXI_ID always_comb begin soc_ifc_reg_rdata_mask = 0; for (int i = 0; i < 12; i++) begin soc_ifc_reg_rdata_mask |= soc_ifc_reg_req_data.soc_req & soc_ifc_reg_hwif_out.CPTRA_TRNG_DATA[i].DATA.swacc & - soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value & - (soc_ifc_reg_req_data.user != soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value[APB_USER_WIDTH-1:0]); + soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value & + (soc_ifc_reg_req_data.id != soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0]); end end @@ -786,7 +816,7 @@ assign timer_intr = {soc_ifc_reg_hwif_out.internal_rv_mtime_h.count_h.value //SHA Accelerator sha512_acc_top #( - .DATA_WIDTH(APB_DATA_WIDTH) + .DATA_WIDTH(AXI_DATA_WIDTH) ) i_sha512_acc_top ( .clk(soc_ifc_clk_cg), @@ -831,19 +861,69 @@ i_mbox ( .sha_sram_req_addr(sha_sram_req_addr), .sha_sram_resp(sha_sram_resp), .sha_sram_hold(sha_sram_hold), + .dma_sram_req_dv (dma_sram_req_dv ), + .dma_sram_req_data(dma_sram_req_data), + .dma_sram_rdata (dma_sram_rdata ), + .dma_sram_hold (dma_sram_req_hold), + .dma_sram_error (dma_sram_error ), .mbox_sram_req(mbox_sram_req), .mbox_sram_resp(mbox_sram_resp), .sram_single_ecc_error(sram_single_ecc_error), .sram_double_ecc_error(sram_double_ecc_error), + .uc_mbox_lock(uc_mbox_lock), .soc_mbox_data_avail(mailbox_data_avail), .uc_mbox_data_avail(uc_mbox_data_avail), .soc_req_mbox_lock(soc_req_mbox_lock), .mbox_protocol_error(mbox_protocol_error), - .mbox_inv_pauser_axs(mbox_inv_user_p), + .mbox_inv_axi_id_axs(mbox_inv_id_p), .dmi_inc_rdptr(dmi_inc_rdptr), .dmi_reg(mbox_dmi_reg) ); +// AXI Manager (DMA) +axi_dma_top #( + .AW(AXIM_ADDR_WIDTH), // Addr Width + .DW(AXIM_DATA_WIDTH), // Data Width + .UW(AXIM_USER_WIDTH), // User Width + .IW(AXIM_ID_WIDTH) // ID Width +) i_axi_dma ( + .clk (clk ), + .cptra_pwrgood(cptra_pwrgood ), + .rst_n (cptra_noncore_rst_b), + + // Recovery INF Interrupt + // Should only assert when a full block_size of data is available at the + // recovery interface FIFO + .recovery_data_avail(recovery_data_avail), + + // SOC_IFC Internal Signaling + .mbox_lock(uc_mbox_lock), + .sha_lock (1'b0 /*FIXME*/ ), + + // AXI INF + .m_axi_w_if(m_axi_w_if), + .m_axi_r_if(m_axi_r_if), + + // Component INF + .dv (dma_reg_req_dv ), + .req_data(dma_reg_req_data), + .hold (dma_reg_req_hold), + .rdata (dma_reg_rdata ), + .error (dma_reg_error ), + + // Mailbox SRAM INF + .mb_dv (dma_sram_req_dv ), + .mb_hold (dma_sram_req_hold), + .mb_error(dma_sram_error ), + .mb_data (dma_sram_req_data), + .mb_rdata(dma_sram_rdata ), + + // Interrupt + .notif_intr(dma_notif_intr), + .error_intr(dma_error_intr) + +); + //------------------------- //Watchdog timer //------------------------- @@ -990,6 +1070,11 @@ always_ff @(posedge rdc_clk_cg or negedge cptra_pwrgood) begin end end +`CALIPTRA_ASSERT (AXI_SUB_ADDR_WIDTH, SOC_IFC_ADDR_W == AXI_ADDR_WIDTH, clk, !cptra_noncore_rst_b) +`CALIPTRA_ASSERT (AXI_SUB_DATA_WIDTH, SOC_IFC_DATA_W == AXI_DATA_WIDTH, clk, !cptra_noncore_rst_b) +`CALIPTRA_ASSERT (AXI_SUB_USER_WIDTH, SOC_IFC_USER_W == AXI_USER_WIDTH, clk, !cptra_noncore_rst_b) +`CALIPTRA_ASSERT (AXI_SUB_ID_WIDTH , SOC_IFC_ID_W == AXI_ID_WIDTH, clk, !cptra_noncore_rst_b) + `CALIPTRA_ASSERT_KNOWN(ERR_AHB_INF_X, {hreadyout_o,hresp_o}, clk, !cptra_noncore_rst_b) //this generates an NMI in the core, but we don't have a handler so it just hangs `CALIPTRA_ASSERT_NEVER(ERR_SOC_IFC_AHB_ERR, hresp_o, clk, !cptra_noncore_rst_b) diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf index b07a51d6d..bf8fff797 100644 --- a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf @@ -22,6 +22,9 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl @@ -42,6 +45,7 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${UVM_HOME}/src/uvm_pkg.sv ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh @@ -103,6 +107,18 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv @@ -147,6 +163,52 @@ ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/s ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hvl_top.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf index 3c0ba0e0b..830cb5d1e 100644 --- a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf @@ -22,6 +22,9 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/axi/rtl ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl @@ -37,6 +40,7 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg +incdir+${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers ++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl +incdir+${CALIPTRA_ROOT}/src/sha512/rtl ${UVM_HOME}/src/uvm_pkg.sv ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh @@ -98,6 +102,18 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv +${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv @@ -135,6 +151,52 @@ ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/i ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv +${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_rd.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_mgr_wr.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_ctrl.sv +${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_top.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile index 143486703..d54404c6e 100644 --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -13,6 +13,7 @@ # limitations under the License. # +SHELL=/bin/bash PLAYBOOK_RANDOM_SEED ?= $(shell date +%s) BUILD_CFLAGS ?= # Cflags to give fw visibility to expected hw configuration @@ -242,18 +243,18 @@ clean_fw: ############ Model Builds ############################### -verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_VERILATOR_SRCS) - $(VERILATOR) $(TB_VERILATOR_SRCS) --cc -CFLAGS "$(CFLAGS)" \ +verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_VERILATOR_SRCS) $(TBDIR)/../config/caliptra_top_tb.vf + set -eo pipefail; $(VERILATOR) $(TB_VERILATOR_SRCS) --cc -CFLAGS "$(CFLAGS)" \ +libext+.v+.sv +define+RV_OPENSOURCE \ - --timescale 1ns/1ps \ - --timing \ + --timescale 1ns/100ps \ + --timing \ $(includes) \ $(suppress) \ -f $(TBDIR)/../config/caliptra_top_tb.vf --top-module caliptra_top_tb \ -f $(TBDIR)/../config/caliptra_top_tb.vlt \ -exe test_caliptra_top_tb.cpp --autoflush $(VERILATOR_DEBUG) \ - $(TB_DEFS) - $(MAKE) -j`nproc` -e -C obj_dir/ -f Vcaliptra_top_tb.mk $(VERILATOR_MAKE_FLAGS) VM_PARALLEL_BUILDS=1 + $(TB_DEFS) 2>&1 | tee verilator_build.log + set -eo pipefail; $(MAKE) -j`nproc` -e -C obj_dir/ -f Vcaliptra_top_tb.mk $(VERILATOR_MAKE_FLAGS) VM_PARALLEL_BUILDS=1 2>&1 | tee verilator_make.log touch verilator-build vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_DPI_SRCS) @@ -266,7 +267,7 @@ vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(TB_DPI_SRCS) ############ TEST Simulation ############################### verilator: program.hex verilator-build - ./obj_dir/Vcaliptra_top_tb $(VERILATOR_RUN_ARGS) + set -eo pipefail; ./obj_dir/Vcaliptra_top_tb $(VERILATOR_RUN_ARGS) 2>&1 | tee verilator_sim.log vcs: program.hex vcs-build cp $(TEST_GEN_FILES) $(BUILD_DIR) diff --git a/tools/scripts/reg_doc_gen.sh b/tools/scripts/reg_doc_gen.sh index 367c77598..a0dba77cd 100755 --- a/tools/scripts/reg_doc_gen.sh +++ b/tools/scripts/reg_doc_gen.sh @@ -24,6 +24,7 @@ src/sha512/rtl/sha512_reg.rdl \ src/sha256/rtl/sha256_reg.rdl \ src/soc_ifc/rtl/mbox_csr.rdl \ src/soc_ifc/rtl/sha512_acc_csr.rdl \ +src/axi/rtl/axi_dma_reg.rdl \ src/soc_ifc/rtl/soc_ifc_reg.rdl \ src/hmac/rtl/hmac_reg.rdl \ src/doe/rtl/doe_reg.rdl \