diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index bbd3d8a57..df50a1693 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -e0a04a4e5783f4d92cda3bf8038ad5867d6ee7edb5bb8018db6c11b9171ad45284eeb77d114732c920fd48d834139395 \ No newline at end of file +8d77579899d273d139ab694b86e53b0ea7190c82c0657fe7662bdf277082b8ebebc199ba4e6716749af22f1cf0f22413 \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index 0424d1a90..ffb4a985e 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1724776472 \ No newline at end of file +1725477264 \ No newline at end of file diff --git a/src/ecc/rtl/ecc_dsa_ctrl.sv b/src/ecc/rtl/ecc_dsa_ctrl.sv index 3192a14ac..290b6c94c 100644 --- a/src/ecc/rtl/ecc_dsa_ctrl.sv +++ b/src/ecc/rtl/ecc_dsa_ctrl.sv @@ -317,7 +317,7 @@ module ecc_dsa_ctrl // read the registers written by sw always_comb begin //Mask the command if KV clients are not idle - cmd_reg = hwif_out.ECC_CTRL.CTRL.value & {3{kv_seed_ready}} & {3{kv_privkey_ready}}; + cmd_reg = {hwif_out.ECC_CTRL.DH_SHAREDKEY.value, hwif_out.ECC_CTRL.CTRL.value} & {3{kv_seed_ready}} & {3{kv_privkey_ready}}; zeroize_reg = hwif_out.ECC_CTRL.ZEROIZE.value || debugUnlock_or_scan_mode_switch; sca_point_rnd_en = 1'b1; @@ -477,6 +477,7 @@ module ecc_dsa_ctrl always_comb hwif_in.ECC_CTRL.CTRL.hwclr = |cmd_reg; + always_comb hwif_in.ECC_CTRL.DH_SHAREDKEY.hwclr = |cmd_reg; always_comb hwif_in.ECC_CTRL.PCR_SIGN.hwclr = hwif_out.ECC_CTRL.PCR_SIGN.value; // TODO add other interrupt hwset signals (errors) diff --git a/src/ecc/rtl/ecc_reg.rdl b/src/ecc/rtl/ecc_reg.rdl index 618cc9f15..e2278f3c2 100644 --- a/src/ecc/rtl/ecc_reg.rdl +++ b/src/ecc/rtl/ecc_reg.rdl @@ -71,16 +71,16 @@ addrmap ecc_reg { default hw = r; default resetsignal = reset_b; field {desc = "Control command field: This can be: - [br] 000 for NONE - [br] 001 for KEYGEN - [br] 010 for SIGNING - [br] 011 for VERIFYING - [br] 100 for ECDH SHARED KEY - [br] After each software write, hardware will erase the register"; swwe = ecc_ready; hwclr;} CTRL[3] = 3'b0; + [br] 00 for NONE + [br] 01 for KEYGEN + [br] 10 for SIGNING + [br] 11 for VERIFYING + [br] After each software write, hardware will erase the register"; swwe = ecc_ready; hwclr;} CTRL[2] = 2'b0; field {desc = "Zeroize all internal registers: Zeroize all internal registers after ECC process, to avoid SCA leakage. [br] Software write generates only a single-cycle pulse on the hardware interface and then will be erased"; singlepulse;} ZEROIZE = 1'b0; field {desc = "Run PCR Signing flow: Run ECC Signing flow to sign PCRs."; swwe = ecc_ready; hwclr;} PCR_SIGN = 1'b0; + field {desc = "Run ECDH for shared key generation."; swwe = ecc_ready; hwclr;} DH_SHAREDKEY = 1'b0; } ECC_CTRL @0x00000010; @@ -323,9 +323,9 @@ addrmap ecc_reg { default resetsignal = reset_b; field {desc = "DH Shared Key field"; hwclr;} DH_SHARED_KEY[32] = 32'b0; - } ECC_DH_SHARED_KEY[12] @0x00000600; + } ECC_DH_SHARED_KEY[12] @0x000005C0; - kv_read_ctrl_reg ecc_kv_rd_pkey_ctrl @0x00000700; + kv_read_ctrl_reg ecc_kv_rd_pkey_ctrl @0x00000600; kv_status_reg ecc_kv_rd_pkey_status; kv_read_ctrl_reg ecc_kv_rd_seed_ctrl; kv_status_reg ecc_kv_rd_seed_status; diff --git a/src/ecc/rtl/ecc_reg.sv b/src/ecc/rtl/ecc_reg.sv index 8cf61c0fc..6f3f9b58f 100644 --- a/src/ecc/rtl/ecc_reg.sv +++ b/src/ecc/rtl/ecc_reg.sv @@ -153,14 +153,14 @@ module ecc_reg ( decoded_reg_strb.ECC_PRIVKEY_IN[i0] = cpuif_req_masked & (cpuif_addr == 12'h580 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_DH_SHARED_KEY[i0] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h4); - end - decoded_reg_strb.ecc_kv_rd_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h700); - decoded_reg_strb.ecc_kv_rd_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h704); - decoded_reg_strb.ecc_kv_rd_seed_ctrl = cpuif_req_masked & (cpuif_addr == 12'h708); - decoded_reg_strb.ecc_kv_rd_seed_status = cpuif_req_masked & (cpuif_addr == 12'h70c); - decoded_reg_strb.ecc_kv_wr_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h710); - decoded_reg_strb.ecc_kv_wr_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h714); + decoded_reg_strb.ECC_DH_SHARED_KEY[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c0 + i0*12'h4); + end + decoded_reg_strb.ecc_kv_rd_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h600); + decoded_reg_strb.ecc_kv_rd_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h604); + decoded_reg_strb.ecc_kv_rd_seed_ctrl = cpuif_req_masked & (cpuif_addr == 12'h608); + decoded_reg_strb.ecc_kv_rd_seed_status = cpuif_req_masked & (cpuif_addr == 12'h60c); + decoded_reg_strb.ecc_kv_wr_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h610); + decoded_reg_strb.ecc_kv_wr_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h614); decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); @@ -188,7 +188,7 @@ module ecc_reg ( typedef struct packed{ struct packed{ struct packed{ - logic [2:0] next; + logic [1:0] next; logic load_next; } CTRL; struct packed{ @@ -199,6 +199,10 @@ module ecc_reg ( logic next; logic load_next; } PCR_SIGN; + struct packed{ + logic next; + logic load_next; + } DH_SHAREDKEY; } ECC_CTRL; struct packed{ struct packed{ @@ -458,7 +462,7 @@ module ecc_reg ( typedef struct packed{ struct packed{ struct packed{ - logic [2:0] value; + logic [1:0] value; } CTRL; struct packed{ logic value; @@ -466,6 +470,9 @@ module ecc_reg ( struct packed{ logic value; } PCR_SIGN; + struct packed{ + logic value; + } DH_SHAREDKEY; } ECC_CTRL; struct packed{ struct packed{ @@ -671,12 +678,12 @@ module ecc_reg ( // Field: ecc_reg.ECC_CTRL.CTRL always_comb begin - automatic logic [2:0] next_c; + automatic logic [1:0] next_c; automatic logic load_next_c; next_c = field_storage.ECC_CTRL.CTRL.value; load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write - next_c = (field_storage.ECC_CTRL.CTRL.value & ~decoded_wr_biten[2:0]) | (decoded_wr_data[2:0] & decoded_wr_biten[2:0]); + next_c = (field_storage.ECC_CTRL.CTRL.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; end else if(hwif_in.ECC_CTRL.CTRL.hwclr) begin // HW Clear next_c = '0; @@ -687,7 +694,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_CTRL.CTRL.value <= 3'h0; + field_storage.ECC_CTRL.CTRL.value <= 2'h0; end else if(field_combo.ECC_CTRL.CTRL.load_next) begin field_storage.ECC_CTRL.CTRL.value <= field_combo.ECC_CTRL.CTRL.next; end @@ -700,7 +707,7 @@ module ecc_reg ( next_c = field_storage.ECC_CTRL.ZEROIZE.value; load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr) begin // SW write - next_c = (field_storage.ECC_CTRL.ZEROIZE.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); + next_c = (field_storage.ECC_CTRL.ZEROIZE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; end else begin // singlepulse clears back to 0 next_c = '0; @@ -724,7 +731,7 @@ module ecc_reg ( next_c = field_storage.ECC_CTRL.PCR_SIGN.value; load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write - next_c = (field_storage.ECC_CTRL.PCR_SIGN.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); + next_c = (field_storage.ECC_CTRL.PCR_SIGN.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; end else if(hwif_in.ECC_CTRL.PCR_SIGN.hwclr) begin // HW Clear next_c = '0; @@ -741,6 +748,30 @@ module ecc_reg ( end end assign hwif_out.ECC_CTRL.PCR_SIGN.value = field_storage.ECC_CTRL.PCR_SIGN.value; + // Field: ecc_reg.ECC_CTRL.DH_SHAREDKEY + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_CTRL.DH_SHAREDKEY.value; + load_next_c = '0; + if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write + next_c = (field_storage.ECC_CTRL.DH_SHAREDKEY.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); + load_next_c = '1; + end else if(hwif_in.ECC_CTRL.DH_SHAREDKEY.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.ECC_CTRL.DH_SHAREDKEY.next = next_c; + field_combo.ECC_CTRL.DH_SHAREDKEY.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.ECC_CTRL.DH_SHAREDKEY.value <= 1'h0; + end else if(field_combo.ECC_CTRL.DH_SHAREDKEY.load_next) begin + field_storage.ECC_CTRL.DH_SHAREDKEY.value <= field_combo.ECC_CTRL.DH_SHAREDKEY.next; + end + end + assign hwif_out.ECC_CTRL.DH_SHAREDKEY.value = field_storage.ECC_CTRL.DH_SHAREDKEY.value; for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_SEED[].SEED always_comb begin diff --git a/src/ecc/rtl/ecc_reg_pkg.sv b/src/ecc/rtl/ecc_reg_pkg.sv index d74396c1e..44dde9e60 100644 --- a/src/ecc/rtl/ecc_reg_pkg.sv +++ b/src/ecc/rtl/ecc_reg_pkg.sv @@ -30,9 +30,14 @@ package ecc_reg_pkg; logic hwclr; } ecc_reg__ECC_CTRL__PCR_SIGN__in_t; + typedef struct packed{ + logic hwclr; + } ecc_reg__ECC_CTRL__DH_SHAREDKEY__in_t; + typedef struct packed{ ecc_reg__ECC_CTRL__CTRL__in_t CTRL; ecc_reg__ECC_CTRL__PCR_SIGN__in_t PCR_SIGN; + ecc_reg__ECC_CTRL__DH_SHAREDKEY__in_t DH_SHAREDKEY; } ecc_reg__ECC_CTRL__in_t; typedef struct packed{ @@ -252,7 +257,7 @@ package ecc_reg_pkg; } ecc_reg__in_t; typedef struct packed{ - logic [2:0] value; + logic [1:0] value; } ecc_reg__ECC_CTRL__CTRL__out_t; typedef struct packed{ @@ -263,10 +268,15 @@ package ecc_reg_pkg; logic value; } ecc_reg__ECC_CTRL__PCR_SIGN__out_t; + typedef struct packed{ + logic value; + } ecc_reg__ECC_CTRL__DH_SHAREDKEY__out_t; + typedef struct packed{ ecc_reg__ECC_CTRL__CTRL__out_t CTRL; ecc_reg__ECC_CTRL__ZEROIZE__out_t ZEROIZE; ecc_reg__ECC_CTRL__PCR_SIGN__out_t PCR_SIGN; + ecc_reg__ECC_CTRL__DH_SHAREDKEY__out_t DH_SHAREDKEY; } ecc_reg__ECC_CTRL__out_t; typedef struct packed{ diff --git a/src/ecc/rtl/ecc_reg_uvm.sv b/src/ecc/rtl/ecc_reg_uvm.sv index a47d047fb..459fa6263 100644 --- a/src/ecc/rtl/ecc_reg_uvm.sv +++ b/src/ecc/rtl/ecc_reg_uvm.sv @@ -70,13 +70,15 @@ package ecc_reg_uvm; protected uvm_reg_data_t m_data; protected bit m_is_read; - ecc_reg__ECC_CTRL_bit_cg CTRL_bit_cg[3]; + ecc_reg__ECC_CTRL_bit_cg CTRL_bit_cg[2]; ecc_reg__ECC_CTRL_bit_cg ZEROIZE_bit_cg[1]; ecc_reg__ECC_CTRL_bit_cg PCR_SIGN_bit_cg[1]; + ecc_reg__ECC_CTRL_bit_cg DH_SHAREDKEY_bit_cg[1]; ecc_reg__ECC_CTRL_fld_cg fld_cg; rand uvm_reg_field CTRL; rand uvm_reg_field ZEROIZE; rand uvm_reg_field PCR_SIGN; + rand uvm_reg_field DH_SHAREDKEY; function new(string name = "ecc_reg__ECC_CTRL"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); @@ -89,15 +91,18 @@ package ecc_reg_uvm; virtual function void build(); this.CTRL = new("CTRL"); - this.CTRL.configure(this, 3, 0, "WO", 1, 'h0, 1, 1, 0); + this.CTRL.configure(this, 2, 0, "WO", 1, 'h0, 1, 1, 0); this.ZEROIZE = new("ZEROIZE"); - this.ZEROIZE.configure(this, 1, 3, "WO", 0, 'h0, 1, 1, 0); + this.ZEROIZE.configure(this, 1, 2, "WO", 0, 'h0, 1, 1, 0); this.PCR_SIGN = new("PCR_SIGN"); - this.PCR_SIGN.configure(this, 1, 4, "WO", 1, 'h0, 1, 1, 0); + this.PCR_SIGN.configure(this, 1, 3, "WO", 1, 'h0, 1, 1, 0); + this.DH_SHAREDKEY = new("DH_SHAREDKEY"); + this.DH_SHAREDKEY.configure(this, 1, 4, "WO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin foreach(CTRL_bit_cg[bt]) CTRL_bit_cg[bt] = new(); foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new(); foreach(PCR_SIGN_bit_cg[bt]) PCR_SIGN_bit_cg[bt] = new(); + foreach(DH_SHAREDKEY_bit_cg[bt]) DH_SHAREDKEY_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); @@ -1272,38 +1277,38 @@ package ecc_reg_uvm; this.ECC_DH_SHARED_KEY[i0].configure(this); this.ECC_DH_SHARED_KEY[i0].build(); - this.default_map.add_reg(this.ECC_DH_SHARED_KEY[i0], 'h600 + i0*'h4); + this.default_map.add_reg(this.ECC_DH_SHARED_KEY[i0], 'h5c0 + i0*'h4); end this.ecc_kv_rd_pkey_ctrl = new("ecc_kv_rd_pkey_ctrl"); this.ecc_kv_rd_pkey_ctrl.configure(this); this.ecc_kv_rd_pkey_ctrl.build(); - this.default_map.add_reg(this.ecc_kv_rd_pkey_ctrl, 'h700); + this.default_map.add_reg(this.ecc_kv_rd_pkey_ctrl, 'h600); this.ecc_kv_rd_pkey_status = new("ecc_kv_rd_pkey_status"); this.ecc_kv_rd_pkey_status.configure(this); this.ecc_kv_rd_pkey_status.build(); - this.default_map.add_reg(this.ecc_kv_rd_pkey_status, 'h704); + this.default_map.add_reg(this.ecc_kv_rd_pkey_status, 'h604); this.ecc_kv_rd_seed_ctrl = new("ecc_kv_rd_seed_ctrl"); this.ecc_kv_rd_seed_ctrl.configure(this); this.ecc_kv_rd_seed_ctrl.build(); - this.default_map.add_reg(this.ecc_kv_rd_seed_ctrl, 'h708); + this.default_map.add_reg(this.ecc_kv_rd_seed_ctrl, 'h608); this.ecc_kv_rd_seed_status = new("ecc_kv_rd_seed_status"); this.ecc_kv_rd_seed_status.configure(this); this.ecc_kv_rd_seed_status.build(); - this.default_map.add_reg(this.ecc_kv_rd_seed_status, 'h70c); + this.default_map.add_reg(this.ecc_kv_rd_seed_status, 'h60c); this.ecc_kv_wr_pkey_ctrl = new("ecc_kv_wr_pkey_ctrl"); this.ecc_kv_wr_pkey_ctrl.configure(this); this.ecc_kv_wr_pkey_ctrl.build(); - this.default_map.add_reg(this.ecc_kv_wr_pkey_ctrl, 'h710); + this.default_map.add_reg(this.ecc_kv_wr_pkey_ctrl, 'h610); this.ecc_kv_wr_pkey_status = new("ecc_kv_wr_pkey_status"); this.ecc_kv_wr_pkey_status.configure(this); this.ecc_kv_wr_pkey_status.build(); - this.default_map.add_reg(this.ecc_kv_wr_pkey_status, 'h714); + this.default_map.add_reg(this.ecc_kv_wr_pkey_status, 'h614); this.intr_block_rf = new("intr_block_rf"); this.intr_block_rf.configure(this); this.intr_block_rf.build(); diff --git a/src/ecc/tb/ecc_top_tb.sv b/src/ecc/tb/ecc_top_tb.sv index 29bb56016..fef121d63 100644 --- a/src/ecc/tb/ecc_top_tb.sv +++ b/src/ecc/tb/ecc_top_tb.sv @@ -34,10 +34,10 @@ module ecc_top_tb string ecc_test_vector_file; // Input test vector file string ecc_test_to_run; // ECC tests - default, ECC_normal_test, ECC_otf_reset_test - localparam ECC_CMD_KEYGEN = 3'b001; - localparam ECC_CMD_SIGNING = 3'b010; - localparam ECC_CMD_VERIFYING = 3'b011; - localparam ECC_CMD_DH_SHARED = 3'b100; + localparam ECC_CMD_KEYGEN = 2'b01; + localparam ECC_CMD_SIGNING = 2'b10; + localparam ECC_CMD_VERIFYING = 2'b11; + localparam ECC_CMD_DH_SHARED = (1 << `ECC_REG_ECC_CTRL_DH_SHAREDKEY_LOW); parameter R_WIDTH = 384; typedef bit [R_WIDTH-1:0] r_t; @@ -449,7 +449,7 @@ module ecc_top_tb // // Write the given word to the DUT using the DUT interface. //---------------------------------------------------------------- - task trig_ECC(input [3 : 0] cmd); + task trig_ECC(input [31 : 0] cmd); begin write_single_word(`ECC_REG_ECC_CTRL, cmd); #(CLK_PERIOD); diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index c2c3dba55..c715af439 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -143,11 +143,13 @@ #define CLP_ECC_REG_ECC_CTRL (0x10008010) #define ECC_REG_ECC_CTRL (0x10) #define ECC_REG_ECC_CTRL_CTRL_LOW (0) -#define ECC_REG_ECC_CTRL_CTRL_MASK (0x7) -#define ECC_REG_ECC_CTRL_ZEROIZE_LOW (3) -#define ECC_REG_ECC_CTRL_ZEROIZE_MASK (0x8) -#define ECC_REG_ECC_CTRL_PCR_SIGN_LOW (4) -#define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (0x10) +#define ECC_REG_ECC_CTRL_CTRL_MASK (0x3) +#define ECC_REG_ECC_CTRL_ZEROIZE_LOW (2) +#define ECC_REG_ECC_CTRL_ZEROIZE_MASK (0x4) +#define ECC_REG_ECC_CTRL_PCR_SIGN_LOW (3) +#define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (0x8) +#define ECC_REG_ECC_CTRL_DH_SHAREDKEY_LOW (4) +#define ECC_REG_ECC_CTRL_DH_SHAREDKEY_MASK (0x10) #define CLP_ECC_REG_ECC_STATUS (0x10008018) #define ECC_REG_ECC_STATUS (0x18) #define ECC_REG_ECC_STATUS_READY_LOW (0) @@ -418,32 +420,32 @@ #define ECC_REG_ECC_PRIVKEY_IN_10 (0x5a8) #define CLP_ECC_REG_ECC_PRIVKEY_IN_11 (0x100085ac) #define ECC_REG_ECC_PRIVKEY_IN_11 (0x5ac) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_0 (0x10008600) -#define ECC_REG_ECC_DH_SHARED_KEY_0 (0x600) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_1 (0x10008604) -#define ECC_REG_ECC_DH_SHARED_KEY_1 (0x604) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_2 (0x10008608) -#define ECC_REG_ECC_DH_SHARED_KEY_2 (0x608) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_3 (0x1000860c) -#define ECC_REG_ECC_DH_SHARED_KEY_3 (0x60c) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_4 (0x10008610) -#define ECC_REG_ECC_DH_SHARED_KEY_4 (0x610) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_5 (0x10008614) -#define ECC_REG_ECC_DH_SHARED_KEY_5 (0x614) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_6 (0x10008618) -#define ECC_REG_ECC_DH_SHARED_KEY_6 (0x618) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_7 (0x1000861c) -#define ECC_REG_ECC_DH_SHARED_KEY_7 (0x61c) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_8 (0x10008620) -#define ECC_REG_ECC_DH_SHARED_KEY_8 (0x620) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_9 (0x10008624) -#define ECC_REG_ECC_DH_SHARED_KEY_9 (0x624) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_10 (0x10008628) -#define ECC_REG_ECC_DH_SHARED_KEY_10 (0x628) -#define CLP_ECC_REG_ECC_DH_SHARED_KEY_11 (0x1000862c) -#define ECC_REG_ECC_DH_SHARED_KEY_11 (0x62c) -#define CLP_ECC_REG_ECC_KV_RD_PKEY_CTRL (0x10008700) -#define ECC_REG_ECC_KV_RD_PKEY_CTRL (0x700) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_0 (0x100085c0) +#define ECC_REG_ECC_DH_SHARED_KEY_0 (0x5c0) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_1 (0x100085c4) +#define ECC_REG_ECC_DH_SHARED_KEY_1 (0x5c4) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_2 (0x100085c8) +#define ECC_REG_ECC_DH_SHARED_KEY_2 (0x5c8) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_3 (0x100085cc) +#define ECC_REG_ECC_DH_SHARED_KEY_3 (0x5cc) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_4 (0x100085d0) +#define ECC_REG_ECC_DH_SHARED_KEY_4 (0x5d0) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_5 (0x100085d4) +#define ECC_REG_ECC_DH_SHARED_KEY_5 (0x5d4) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_6 (0x100085d8) +#define ECC_REG_ECC_DH_SHARED_KEY_6 (0x5d8) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_7 (0x100085dc) +#define ECC_REG_ECC_DH_SHARED_KEY_7 (0x5dc) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_8 (0x100085e0) +#define ECC_REG_ECC_DH_SHARED_KEY_8 (0x5e0) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_9 (0x100085e4) +#define ECC_REG_ECC_DH_SHARED_KEY_9 (0x5e4) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_10 (0x100085e8) +#define ECC_REG_ECC_DH_SHARED_KEY_10 (0x5e8) +#define CLP_ECC_REG_ECC_DH_SHARED_KEY_11 (0x100085ec) +#define ECC_REG_ECC_DH_SHARED_KEY_11 (0x5ec) +#define CLP_ECC_REG_ECC_KV_RD_PKEY_CTRL (0x10008600) +#define ECC_REG_ECC_KV_RD_PKEY_CTRL (0x600) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_LOW (0) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_MASK (0x1) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_ENTRY_LOW (1) @@ -452,16 +454,16 @@ #define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_LOW (7) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_MASK (0xffffff80) -#define CLP_ECC_REG_ECC_KV_RD_PKEY_STATUS (0x10008704) -#define ECC_REG_ECC_KV_RD_PKEY_STATUS (0x704) +#define CLP_ECC_REG_ECC_KV_RD_PKEY_STATUS (0x10008604) +#define ECC_REG_ECC_KV_RD_PKEY_STATUS (0x604) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_LOW (0) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_MASK (0x1) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_LOW (1) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_MASK (0x2) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_LOW (2) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_MASK (0x3fc) -#define CLP_ECC_REG_ECC_KV_RD_SEED_CTRL (0x10008708) -#define ECC_REG_ECC_KV_RD_SEED_CTRL (0x708) +#define CLP_ECC_REG_ECC_KV_RD_SEED_CTRL (0x10008608) +#define ECC_REG_ECC_KV_RD_SEED_CTRL (0x608) #define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_LOW (0) #define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_MASK (0x1) #define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_ENTRY_LOW (1) @@ -470,16 +472,16 @@ #define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_LOW (7) #define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_MASK (0xffffff80) -#define CLP_ECC_REG_ECC_KV_RD_SEED_STATUS (0x1000870c) -#define ECC_REG_ECC_KV_RD_SEED_STATUS (0x70c) +#define CLP_ECC_REG_ECC_KV_RD_SEED_STATUS (0x1000860c) +#define ECC_REG_ECC_KV_RD_SEED_STATUS (0x60c) #define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_LOW (0) #define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_MASK (0x1) #define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_LOW (1) #define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_MASK (0x2) #define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_LOW (2) #define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_MASK (0x3fc) -#define CLP_ECC_REG_ECC_KV_WR_PKEY_CTRL (0x10008710) -#define ECC_REG_ECC_KV_WR_PKEY_CTRL (0x710) +#define CLP_ECC_REG_ECC_KV_WR_PKEY_CTRL (0x10008610) +#define ECC_REG_ECC_KV_WR_PKEY_CTRL (0x610) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_LOW (0) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_MASK (0x1) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_ENTRY_LOW (1) @@ -496,8 +498,8 @@ #define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_SEED_DEST_VALID_MASK (0x400) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_LOW (11) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_MASK (0xfffff800) -#define CLP_ECC_REG_ECC_KV_WR_PKEY_STATUS (0x10008714) -#define ECC_REG_ECC_KV_WR_PKEY_STATUS (0x714) +#define CLP_ECC_REG_ECC_KV_WR_PKEY_STATUS (0x10008614) +#define ECC_REG_ECC_KV_WR_PKEY_STATUS (0x614) #define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_LOW (0) #define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_MASK (0x1) #define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_LOW (1) diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index d8c910392..8461420a6 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -143,11 +143,13 @@ `define CLP_ECC_REG_ECC_CTRL (32'h10008010) `define ECC_REG_ECC_CTRL (32'h10) `define ECC_REG_ECC_CTRL_CTRL_LOW (0) -`define ECC_REG_ECC_CTRL_CTRL_MASK (32'h7) -`define ECC_REG_ECC_CTRL_ZEROIZE_LOW (3) -`define ECC_REG_ECC_CTRL_ZEROIZE_MASK (32'h8) -`define ECC_REG_ECC_CTRL_PCR_SIGN_LOW (4) -`define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (32'h10) +`define ECC_REG_ECC_CTRL_CTRL_MASK (32'h3) +`define ECC_REG_ECC_CTRL_ZEROIZE_LOW (2) +`define ECC_REG_ECC_CTRL_ZEROIZE_MASK (32'h4) +`define ECC_REG_ECC_CTRL_PCR_SIGN_LOW (3) +`define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (32'h8) +`define ECC_REG_ECC_CTRL_DH_SHAREDKEY_LOW (4) +`define ECC_REG_ECC_CTRL_DH_SHAREDKEY_MASK (32'h10) `define CLP_ECC_REG_ECC_STATUS (32'h10008018) `define ECC_REG_ECC_STATUS (32'h18) `define ECC_REG_ECC_STATUS_READY_LOW (0) @@ -418,32 +420,32 @@ `define ECC_REG_ECC_PRIVKEY_IN_10 (32'h5a8) `define CLP_ECC_REG_ECC_PRIVKEY_IN_11 (32'h100085ac) `define ECC_REG_ECC_PRIVKEY_IN_11 (32'h5ac) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_0 (32'h10008600) -`define ECC_REG_ECC_DH_SHARED_KEY_0 (32'h600) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_1 (32'h10008604) -`define ECC_REG_ECC_DH_SHARED_KEY_1 (32'h604) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_2 (32'h10008608) -`define ECC_REG_ECC_DH_SHARED_KEY_2 (32'h608) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_3 (32'h1000860c) -`define ECC_REG_ECC_DH_SHARED_KEY_3 (32'h60c) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_4 (32'h10008610) -`define ECC_REG_ECC_DH_SHARED_KEY_4 (32'h610) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_5 (32'h10008614) -`define ECC_REG_ECC_DH_SHARED_KEY_5 (32'h614) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_6 (32'h10008618) -`define ECC_REG_ECC_DH_SHARED_KEY_6 (32'h618) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_7 (32'h1000861c) -`define ECC_REG_ECC_DH_SHARED_KEY_7 (32'h61c) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_8 (32'h10008620) -`define ECC_REG_ECC_DH_SHARED_KEY_8 (32'h620) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_9 (32'h10008624) -`define ECC_REG_ECC_DH_SHARED_KEY_9 (32'h624) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_10 (32'h10008628) -`define ECC_REG_ECC_DH_SHARED_KEY_10 (32'h628) -`define CLP_ECC_REG_ECC_DH_SHARED_KEY_11 (32'h1000862c) -`define ECC_REG_ECC_DH_SHARED_KEY_11 (32'h62c) -`define CLP_ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h10008700) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h700) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_0 (32'h100085c0) +`define ECC_REG_ECC_DH_SHARED_KEY_0 (32'h5c0) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_1 (32'h100085c4) +`define ECC_REG_ECC_DH_SHARED_KEY_1 (32'h5c4) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_2 (32'h100085c8) +`define ECC_REG_ECC_DH_SHARED_KEY_2 (32'h5c8) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_3 (32'h100085cc) +`define ECC_REG_ECC_DH_SHARED_KEY_3 (32'h5cc) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_4 (32'h100085d0) +`define ECC_REG_ECC_DH_SHARED_KEY_4 (32'h5d0) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_5 (32'h100085d4) +`define ECC_REG_ECC_DH_SHARED_KEY_5 (32'h5d4) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_6 (32'h100085d8) +`define ECC_REG_ECC_DH_SHARED_KEY_6 (32'h5d8) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_7 (32'h100085dc) +`define ECC_REG_ECC_DH_SHARED_KEY_7 (32'h5dc) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_8 (32'h100085e0) +`define ECC_REG_ECC_DH_SHARED_KEY_8 (32'h5e0) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_9 (32'h100085e4) +`define ECC_REG_ECC_DH_SHARED_KEY_9 (32'h5e4) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_10 (32'h100085e8) +`define ECC_REG_ECC_DH_SHARED_KEY_10 (32'h5e8) +`define CLP_ECC_REG_ECC_DH_SHARED_KEY_11 (32'h100085ec) +`define ECC_REG_ECC_DH_SHARED_KEY_11 (32'h5ec) +`define CLP_ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h10008600) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h600) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_LOW (0) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_MASK (32'h1) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_ENTRY_LOW (1) @@ -452,16 +454,16 @@ `define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_LOW (7) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_MASK (32'hffffff80) -`define CLP_ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h10008704) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h704) +`define CLP_ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h10008604) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h604) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_LOW (0) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_MASK (32'h1) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_LOW (1) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_MASK (32'h2) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_LOW (2) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_MASK (32'h3fc) -`define CLP_ECC_REG_ECC_KV_RD_SEED_CTRL (32'h10008708) -`define ECC_REG_ECC_KV_RD_SEED_CTRL (32'h708) +`define CLP_ECC_REG_ECC_KV_RD_SEED_CTRL (32'h10008608) +`define ECC_REG_ECC_KV_RD_SEED_CTRL (32'h608) `define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_LOW (0) `define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_MASK (32'h1) `define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_ENTRY_LOW (1) @@ -470,16 +472,16 @@ `define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_LOW (7) `define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_MASK (32'hffffff80) -`define CLP_ECC_REG_ECC_KV_RD_SEED_STATUS (32'h1000870c) -`define ECC_REG_ECC_KV_RD_SEED_STATUS (32'h70c) +`define CLP_ECC_REG_ECC_KV_RD_SEED_STATUS (32'h1000860c) +`define ECC_REG_ECC_KV_RD_SEED_STATUS (32'h60c) `define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_LOW (0) `define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_MASK (32'h1) `define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_LOW (1) `define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_MASK (32'h2) `define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_LOW (2) `define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_MASK (32'h3fc) -`define CLP_ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h10008710) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h710) +`define CLP_ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h10008610) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h610) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_LOW (0) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_MASK (32'h1) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_ENTRY_LOW (1) @@ -496,8 +498,8 @@ `define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_SEED_DEST_VALID_MASK (32'h400) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_LOW (11) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_MASK (32'hfffff800) -`define CLP_ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h10008714) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h714) +`define CLP_ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h10008614) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h614) `define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_LOW (0) `define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_MASK (32'h1) `define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_LOW (1) diff --git a/src/integration/test_suites/includes/caliptra_defines.h b/src/integration/test_suites/includes/caliptra_defines.h index 0cab692ed..673153f90 100644 --- a/src/integration/test_suites/includes/caliptra_defines.h +++ b/src/integration/test_suites/includes/caliptra_defines.h @@ -76,7 +76,7 @@ #define ECC_CMD_KEYGEN 0x1 #define ECC_CMD_SIGNING 0x2 #define ECC_CMD_VERIFYING 0x3 -#define ECC_CMD_SHAREDKEY 0x4 +#define ECC_CMD_SHAREDKEY ECC_REG_ECC_CTRL_DH_SHAREDKEY_MASK #define STATUS_READY_BIT 0x0 #define STATUS_VALID_BIT 0x1