From 3171cda77a06363e9cd0987dbe10a989a7808a59 Mon Sep 17 00:00:00 2001 From: Michael Norris <108370498+Nitsirks@users.noreply.github.com> Date: Tue, 14 Jan 2025 10:11:11 -0800 Subject: [PATCH] Increased mbox size to 256KB, ROM to 96KB and DCCM/ICCM to 256KB (#681) * increase mbox to 256KB moved direct access to end of memory map to avoid moving existing registers * update rdptr size in status reg * fixing test params for new mbox size * fixing more uses of old param * shortening test so it passes in promote pipeline * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mbox_params' with updated timestamp and hash after successful run * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mbox_params' with updated timestamp and hash after successful run * updating some hard coded addresses that were missed after moving the mbox direct access address deriving params inside mbox for future re-use * fixing mistake in param derivation * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mbox_params' with updated timestamp and hash after successful run * updating ICCM/DCCM and ROM sizes for caliptra 2.0 * fixing missed param change * splitting ecc error trigger test into two tests * shortening ecc test * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mbox_params' with updated timestamp and hash after successful run * fixed split ecc test list in directed regression fixed parameters for mbox sram address change * using mbox pkg instead of soc ifc pkg for mbox defines for better mailbox reuse * updating file lists after creating new mbox pkg * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mbox_params' with updated timestamp and hash after successful run * better parameterized mbox * removing accidental commit of dvt files * fixing params in soc ifc tb * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mbox_params' with updated timestamp and hash after successful run * removing accidental commit * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mbox_params' with updated timestamp and hash after successful run --- .github/workflow_metadata/pr_hash | 2 +- .github/workflow_metadata/pr_timestamp | 2 +- src/axi/config/axi_dma.vf | 1 + src/axi/rtl/axi_dma_ctrl.sv | 4 +- src/integration/config/caliptra_top.vf | 1 + src/integration/config/caliptra_top_tb.vf | 1 + src/integration/config/caliptra_top_tb_pkg.vf | 1 + .../config/caliptra_top_trng_tb.vf | 1 + src/integration/rtl/caliptra_reg.h | 6 +- src/integration/rtl/caliptra_reg.rdl | 18 +- src/integration/rtl/caliptra_reg_defines.svh | 6 +- src/integration/rtl/caliptra_top.sv | 10 +- src/integration/rtl/config_defines.svh | 4 +- src/integration/stimulus/L0_regression.yml | 6 +- ...liptra_top_nightly_directed_regression.yml | 6 +- src/integration/tb/caliptra_top_tb.sv | 6 +- src/integration/tb/caliptra_top_tb_pkg.sv | 10 +- .../tb/caliptra_top_tb_services.sv | 66 +-- src/integration/tb/caliptra_top_tb_soc_bfm.sv | 1 + .../test_suites/caliptra_fmc/caliptra_fmc.ld | 6 +- .../test_suites/caliptra_rt/caliptra_rt.ld | 12 +- .../test_suites/includes/caliptra_defines.h | 3 +- .../test_suites/libs/riscv_hw_if/link.ld | 4 +- .../test_suites/libs/soc_ifc/soc_ifc.c | 2 +- .../pv_hash_and_sign/pv_hash_and_sign.ld | 4 +- .../smoke_test_dma/smoke_test_dma.c | 4 +- .../smoke_test_ecc/smoke_test_ecc.yml | 3 - .../caliptra_isr.h | 0 .../smoke_test_ecc_errortrigger1.c} | 209 --------- .../smoke_test_ecc_errortrigger1.yml | 3 + .../caliptra_isr.h | 253 +++++++++++ .../smoke_test_ecc_errortrigger2.c | 415 ++++++++++++++++++ .../smoke_test_ecc_errortrigger2.yml} | 0 .../caliptra_isr.h | 0 .../smoke_test_ecc_keygen_sign.c | 266 +++++++++++ .../smoke_test_ecc_keygen_sign.yml | 3 + .../smoke_test_ecc_verify_dh/caliptra_isr.h | 244 ++++++++++ .../smoke_test_ecc_verify_dh.c} | 6 - .../smoke_test_ecc_verify_dh.yml | 3 + .../smoke_test_kv_mldsa.ld | 4 +- .../smoke_test_mbox_byte_read.c | 25 +- .../smoke_test_mldsa/smoke_test_mldsa.ld | 6 +- .../smoke_test_mldsa_edge.ld | 4 +- .../smoke_test_mldsa_kat.ld | 4 +- .../smoke_test_mldsa_keygen_sign_vfy_rand.ld | 4 +- .../smoke_test_mldsa_rand.ld | 4 +- .../smoke_test_ras/smoke_test_ras.c | 4 +- .../smoke_test_ras/smoke_test_ras.ld | 4 +- .../smoke_test_sha_accel.s | 12 +- .../smoke_test_sram_ecc/smoke_test_sram_ecc.c | 2 +- .../config/uvmf_caliptra_top.vf | 1 + .../config/uvmf_caliptra_top_itrng.vf | 1 + .../config/uvmf_caliptra_top_vip.vf | 1 + src/riscv_core/veer_el2/rtl/common_defines.sv | 34 +- src/riscv_core/veer_el2/rtl/el2_param.vh | 16 +- src/soc_ifc/config/compile.yml | 3 + src/soc_ifc/config/soc_ifc_pkg.vf | 1 + src/soc_ifc/config/soc_ifc_tb.vf | 1 + src/soc_ifc/config/soc_ifc_top.vf | 1 + src/soc_ifc/config/soc_ifc_uvm_pkg.vf | 1 + src/soc_ifc/coverage/soc_ifc_cov_if.sv | 17 +- src/soc_ifc/rtl/caliptra_top_reg.h | 2 +- src/soc_ifc/rtl/caliptra_top_reg_defines.svh | 2 +- src/soc_ifc/rtl/mbox.sv | 203 +++++---- src/soc_ifc/rtl/mbox_csr.rdl | 2 +- src/soc_ifc/rtl/mbox_csr.sv | 12 +- src/soc_ifc/rtl/mbox_csr_pkg.sv | 4 +- src/soc_ifc/rtl/mbox_csr_uvm.sv | 4 +- src/soc_ifc/rtl/mbox_pkg.sv | 48 ++ src/soc_ifc/rtl/sha512_acc_top.sv | 19 +- src/soc_ifc/rtl/soc_ifc_arb.sv | 20 +- src/soc_ifc/rtl/soc_ifc_pkg.sv | 90 ++-- src/soc_ifc/rtl/soc_ifc_top.sv | 46 +- src/soc_ifc/tb/soc_ifc_tb.sv | 7 +- .../uvmf_soc_ifc/config/uvmf_soc_ifc.vf | 1 + .../uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf | 1 + .../registers/soc_ifc_reg_model_top_pkg.sv | 6 +- tools/scripts/Makefile | 18 +- 78 files changed, 1640 insertions(+), 587 deletions(-) delete mode 100644 src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.yml rename src/integration/test_suites/{smoke_test_ecc_errortrigger => smoke_test_ecc_errortrigger1}/caliptra_isr.h (100%) rename src/integration/test_suites/{smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c => smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.c} (70%) create mode 100644 src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml create mode 100644 src/integration/test_suites/smoke_test_ecc_errortrigger2/caliptra_isr.h create mode 100644 src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.c rename src/integration/test_suites/{smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml => smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml} (100%) rename src/integration/test_suites/{smoke_test_ecc => smoke_test_ecc_keygen_sign}/caliptra_isr.h (100%) create mode 100644 src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.c create mode 100644 src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml create mode 100644 src/integration/test_suites/smoke_test_ecc_verify_dh/caliptra_isr.h rename src/integration/test_suites/{smoke_test_ecc/smoke_test_ecc.c => smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.c} (98%) create mode 100644 src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml create mode 100644 src/soc_ifc/rtl/mbox_pkg.sv diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index b5d952261..9ea0d5314 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -7563196b9c5ba8be0297cf9b6d1655ef81b98fe018fbd4ad37d05a539e7d5effb280748ac7b019c205e2d15bbbe7254f \ No newline at end of file +e37ecacc8b5091ea5b9dbcf5518cc06d0fc077b044b9676a573221971ce88337bc0bcede06c51cd7e28ba62b5798b9fb \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index d3c7c7a38..0e4555c88 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1736449012 \ No newline at end of file +1736839580 \ No newline at end of file diff --git a/src/axi/config/axi_dma.vf b/src/axi/config/axi_dma.vf index 863063a4c..a7ddfc53c 100644 --- a/src/axi/config/axi_dma.vf +++ b/src/axi/config/axi_dma.vf @@ -21,6 +21,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv diff --git a/src/axi/rtl/axi_dma_ctrl.sv b/src/axi/rtl/axi_dma_ctrl.sv index 0ab8a1d46..4686ca861 100644 --- a/src/axi/rtl/axi_dma_ctrl.sv +++ b/src/axi/rtl/axi_dma_ctrl.sv @@ -354,7 +354,7 @@ import soc_ifc_pkg::*; endcase cmd_inv_byte_count = |hwif_out.byte_count.count.value[BW-1:0] || (hwif_out.byte_count.count.value > DMA_MAX_XFER_SIZE) || - (hwif_out.byte_count.count.value > MBOX_SIZE_BYTES && + (hwif_out.byte_count.count.value > CPTRA_MBOX_SIZE_BYTES && ((hwif_out.ctrl.rd_route.value == axi_dma_reg__ctrl__rd_route__rd_route_e__MBOX) || (hwif_out.ctrl.wr_route.value == axi_dma_reg__ctrl__wr_route__wr_route_e__MBOX))); // power of 2 and word-aligned @@ -716,7 +716,7 @@ import soc_ifc_pkg::*; `CALIPTRA_ASSERT(AXI_DMA_VLD_WR_REQ_BND, wr_req_hshake |-> w_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((w_req_if.addr + w_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n) // Proper configuration `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_32, DW == 32) - `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_EQ_MB, DW == MBOX_DATA_W) + `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_EQ_MB, DW == CPTRA_MBOX_DATA_W) // FIFO must have space for all requested data `CALIPTRA_ASSERT(AXI_DMA_LIM_RD_CRED, rd_credits <= FIFO_BC/BC, clk, !rst_n) `CALIPTRA_ASSERT(AXI_DMA_OFL_RD_CRED, rd_req_hshake |-> rd_req_byte_count <= FIFO_BC, clk, !rst_n) diff --git a/src/integration/config/caliptra_top.vf b/src/integration/config/caliptra_top.vf index 8976fdc4b..d39df01b4 100644 --- a/src/integration/config/caliptra_top.vf +++ b/src/integration/config/caliptra_top.vf @@ -113,6 +113,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_p ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv diff --git a/src/integration/config/caliptra_top_tb.vf b/src/integration/config/caliptra_top_tb.vf index bb962236e..a0aaadacb 100644 --- a/src/integration/config/caliptra_top_tb.vf +++ b/src/integration/config/caliptra_top_tb.vf @@ -125,6 +125,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_prim/rtl/abr_prim_sparse_fsm_pk ${CALIPTRA_ROOT}/submodules/adams-bridge/src/ntt_top/rtl/ntt_defines_pkg.sv ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv diff --git a/src/integration/config/caliptra_top_tb_pkg.vf b/src/integration/config/caliptra_top_tb_pkg.vf index 7d7f62568..827bff281 100644 --- a/src/integration/config/caliptra_top_tb_pkg.vf +++ b/src/integration/config/caliptra_top_tb_pkg.vf @@ -125,6 +125,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_prim/rtl/abr_prim_sparse_fsm_pk ${CALIPTRA_ROOT}/submodules/adams-bridge/src/ntt_top/rtl/ntt_defines_pkg.sv ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv diff --git a/src/integration/config/caliptra_top_trng_tb.vf b/src/integration/config/caliptra_top_trng_tb.vf index bb962236e..a0aaadacb 100644 --- a/src/integration/config/caliptra_top_trng_tb.vf +++ b/src/integration/config/caliptra_top_trng_tb.vf @@ -125,6 +125,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_prim/rtl/abr_prim_sparse_fsm_pk ${CALIPTRA_ROOT}/submodules/adams-bridge/src/ntt_top/rtl/ntt_defines_pkg.sv ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index 9bf028d88..9bb202352 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -5279,8 +5279,6 @@ #define ENTROPY_SRC_REG_MAIN_SM_STATE (0xe0) #define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) #define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (0x1ff) -#define CLP_MBOX_SRAM_BASE_ADDR (0x30000000) -#define CLP_MBOX_SRAM_END_ADDR (0x3001ffff) #define CLP_MBOX_CSR_BASE_ADDR (0x30020000) #define CLP_MBOX_CSR_MBOX_LOCK (0x30020000) #define MBOX_CSR_MBOX_LOCK (0x0) @@ -5313,7 +5311,7 @@ #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (0x200) #define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) -#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (0x1fffc00) +#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (0x3fffc00) #define CLP_MBOX_CSR_MBOX_UNLOCK (0x30020020) #define MBOX_CSR_MBOX_UNLOCK (0x20) #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) @@ -6516,6 +6514,8 @@ #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (0xa34) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_MBOX_SRAM_BASE_ADDR (0x30040000) +#define CLP_MBOX_SRAM_END_ADDR (0x3007ffff) #endif \ No newline at end of file diff --git a/src/integration/rtl/caliptra_reg.rdl b/src/integration/rtl/caliptra_reg.rdl index 9a3e00e29..eb028ba5f 100644 --- a/src/integration/rtl/caliptra_reg.rdl +++ b/src/integration/rtl/caliptra_reg.rdl @@ -42,15 +42,6 @@ addrmap clp { entropy_src entropy_src_reg @ 0x2000_3000; - mem {name="Mailbox SRAM"; - desc="Mailbox SRAM for Caliptra direct-mode accesses. Accessible to Caliptra only after acquiring mbox_lock. - [br]Caliptra Access: RW - [br]SOC Access: -"; - memwidth=32; - mementries=32768; - sw=rw; - } external mbox_sram @ 0x3000_0000; - mbox_csr mbox_csr @ 0x3002_0000; sha512_acc_csr sha512_acc_csr @ 0x3002_1000; @@ -59,4 +50,13 @@ addrmap clp { soc_ifc_reg soc_ifc_reg @ 0x3003_0000; + mem {name="Mailbox SRAM"; + desc="Mailbox SRAM for Caliptra direct-mode accesses. Accessible to Caliptra only after acquiring mbox_lock. + [br]Caliptra Access: RW + [br]SOC Access: -"; + memwidth=32; + mementries=65536; + sw=rw; + } external mbox_sram @ 0x3004_0000; + }; diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index f5e7a3914..ffc760a4e 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -5279,8 +5279,6 @@ `define ENTROPY_SRC_REG_MAIN_SM_STATE (32'he0) `define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) `define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'h1ff) -`define CLP_MBOX_SRAM_BASE_ADDR (32'h30000000) -`define CLP_MBOX_SRAM_END_ADDR (32'h3001ffff) `define CLP_MBOX_CSR_BASE_ADDR (32'h30020000) `define CLP_MBOX_CSR_MBOX_LOCK (32'h30020000) `define MBOX_CSR_MBOX_LOCK (32'h0) @@ -5313,7 +5311,7 @@ `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) `define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) -`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h1fffc00) +`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) `define CLP_MBOX_CSR_MBOX_UNLOCK (32'h30020020) `define MBOX_CSR_MBOX_UNLOCK (32'h20) `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) @@ -6516,6 +6514,8 @@ `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (32'ha34) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_MBOX_SRAM_BASE_ADDR (32'h30040000) +`define CLP_MBOX_SRAM_END_ADDR (32'h3007ffff) `endif \ No newline at end of file diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index bd1bd597d..7e4af19f9 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -59,9 +59,9 @@ module caliptra_top //SRAM interface for mbox output logic mbox_sram_cs, output logic mbox_sram_we, - output logic [MBOX_ADDR_W-1:0] mbox_sram_addr, - output logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata, - input logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata, + output logic [CPTRA_MBOX_ADDR_W-1:0] mbox_sram_addr, + output logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata, + input logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata, //SRAM interface for imem output logic imem_cs, @@ -252,8 +252,8 @@ module caliptra_top pcr_signing_t pcr_signing_data; //mailbox sram gasket - mbox_sram_req_t mbox_sram_req; - mbox_sram_resp_t mbox_sram_resp; + cptra_mbox_sram_req_t mbox_sram_req; + cptra_mbox_sram_resp_t mbox_sram_resp; logic clear_obf_secrets; logic scan_mode_switch; diff --git a/src/integration/rtl/config_defines.svh b/src/integration/rtl/config_defines.svh index c82c9c6a4..d20273b15 100755 --- a/src/integration/rtl/config_defines.svh +++ b/src/integration/rtl/config_defines.svh @@ -36,7 +36,7 @@ // AHB Address Map `define CALIPTRA_SLAVE_NAMES {"AES" , "MLDSA" , "ENTROPY_SRC", "CSRNG" , "IMEM" , "SHA256" , "VEER_ICCM_DMA", "VEER_DCCM_DMA", "SOC_IFC" , "SHA512" , "DATAVAULT" , "PCRVAULT" , "KEYVAULT" , "HMAC" , "ECC" , "DOE_CTRL" } /* Array of names for peripherals */ `define CALIPTRA_SLAVE_BASE_ADDR {32'h1001_1000, 32'h1003_0000, 32'h2000_3000, 32'h2000_2000, 32'h0000_0000, 32'h1002_8000, 32'h4000_0000 , 32'h5000_0000 , 32'h3000_0000, 32'h1002_0000, 32'h1001_C000, 32'h1001_A000, 32'h1001_8000, 32'h1001_0000, 32'h1000_8000, 32'h1000_0000} /* Array with slave base address */ - `define CALIPTRA_SLAVE_MASK_ADDR {32'h1001_1FFF, 32'h1003_FFFF, 32'h2000_3FFF, 32'h2000_2FFF, 32'h0000_BFFF, 32'h1002_FFFF, 32'h4001_FFFF , 32'h5001_FFFF , 32'h3003_FFFF, 32'h1002_7FFF, 32'h1001_DFFF, 32'h1001_BFFF, 32'h1001_9FFF, 32'h1001_0FFF, 32'h1000_FFFF, 32'h1000_7FFF} /* Array with slave offset address */ + `define CALIPTRA_SLAVE_MASK_ADDR {32'h1001_1FFF, 32'h1003_FFFF, 32'h2000_3FFF, 32'h2000_2FFF, 32'h0001_7FFF, 32'h1002_FFFF, 32'h4001_FFFF , 32'h5001_FFFF , 32'h3007_FFFF, 32'h1002_7FFF, 32'h1001_DFFF, 32'h1001_BFFF, 32'h1001_9FFF, 32'h1001_0FFF, 32'h1000_FFFF, 32'h1000_7FFF} /* Array with slave offset address */ `define CALIPTRA_SLAVE_ADDR_MASK (`CALIPTRA_SLAVE_BASE_ADDR ^ `CALIPTRA_SLAVE_MASK_ADDR) /* Array indicating meaningful address bits for each slave */ `define CALIPTRA_SLAVE_ADDR_WIDTH(n) $clog2((`CALIPTRA_SLAVE_ADDR_MASK >> (`CALIPTRA_AHB_HADDR_SIZE*n)) & {`CALIPTRA_AHB_HADDR_SIZE{1'b1}}) /* Decode address width for each slave from assigned BASE/MASK address */ `define CALIPTRA_SLAVE_SEL_DOE 0 @@ -90,7 +90,7 @@ //`define CALIPTRA_KV_NUM_READ 6 //`define CALIPTRA_KV_NUM_WRITE 4 - `define CALIPTRA_IMEM_BYTE_SIZE 49152 + `define CALIPTRA_IMEM_BYTE_SIZE 98304 `define CALIPTRA_IMEM_DATA_WIDTH 64 `define CALIPTRA_IMEM_DEPTH `CALIPTRA_IMEM_BYTE_SIZE / (`CALIPTRA_IMEM_DATA_WIDTH/8) `define CALIPTRA_IMEM_BYTE_ADDR_W $clog2(`CALIPTRA_IMEM_BYTE_SIZE) diff --git a/src/integration/stimulus/L0_regression.yml b/src/integration/stimulus/L0_regression.yml index 1873c95d7..978c05d32 100644 --- a/src/integration/stimulus/L0_regression.yml +++ b/src/integration/stimulus/L0_regression.yml @@ -22,7 +22,8 @@ contents: - ../test_suites/hello_world_iccm/hello_world_iccm.yml - ../test_suites/iccm_lock/iccm_lock.yml - ../test_suites/c_intr_handler/c_intr_handler.yml - - ../test_suites/smoke_test_ecc/smoke_test_ecc.yml + - ../test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml + - ../test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml - ../test_suites/smoke_test_hmac/smoke_test_hmac.yml - ../test_suites/smoke_test_mldsa/smoke_test_mldsa.yml - ../test_suites/smoke_test_aes/smoke_test_aes.yml @@ -47,7 +48,8 @@ contents: - ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml - ../test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml - ../test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml - - ../test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml + - ../test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml + - ../test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml - ../test_suites/smoke_test_hmac_errortrigger/smoke_test_hmac_errortrigger.yml - ../test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml - ../test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml index 658af9fce..f2cde9e56 100644 --- a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml +++ b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml @@ -26,7 +26,8 @@ contents: - ${CALIPTRA_ROOT}/src/integration/test_suites/hello_world_iccm/hello_world_iccm.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/iccm_lock/iccm_lock.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/c_intr_handler/c_intr_handler.yml - - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_hmac/smoke_test_hmac.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_hmac_errortrigger/smoke_test_hmac_errortrigger.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.yml @@ -50,7 +51,8 @@ contents: - ${CALIPTRA_ROOT}/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml - - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv index b4d504ff5..7e8d32ee1 100755 --- a/src/integration/tb/caliptra_top_tb.sv +++ b/src/integration/tb/caliptra_top_tb.sv @@ -94,9 +94,9 @@ module caliptra_top_tb ( logic mailbox_data_avail; logic mbox_sram_cs; logic mbox_sram_we; - logic [14:0] mbox_sram_addr; - logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata; - logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata; + logic [CPTRA_MBOX_ADDR_W-1:0] mbox_sram_addr; + logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata; + logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata; logic imem_cs; logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr; diff --git a/src/integration/tb/caliptra_top_tb_pkg.sv b/src/integration/tb/caliptra_top_tb_pkg.sv index d98ff8899..9ea5a4db4 100644 --- a/src/integration/tb/caliptra_top_tb_pkg.sv +++ b/src/integration/tb/caliptra_top_tb_pkg.sv @@ -17,9 +17,9 @@ package caliptra_top_tb_pkg; import soc_ifc_pkg::*; `ifndef VERILATOR -class bitflip_mask_generator #(int MBOX_DATA_AND_ECC_W = 39); +class bitflip_mask_generator #(int CPTRA_MBOX_DATA_AND_ECC_W = 39); - rand logic [MBOX_DATA_AND_ECC_W-1:0] rand_sram_bitflip_mask; + rand logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] rand_sram_bitflip_mask; logic do_double_bitflip; constraint bitflip_c { if (do_double_bitflip) { @@ -34,7 +34,7 @@ class bitflip_mask_generator #(int MBOX_DATA_AND_ECC_W = 39); this.do_double_bitflip = 1'b0; endfunction - function logic [MBOX_DATA_AND_ECC_W-1:0] get_mask(bit do_double_bit = 1'b0); + function logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] get_mask(bit do_double_bit = 1'b0); this.do_double_bitflip = do_double_bit; this.randomize(); return this.rand_sram_bitflip_mask; @@ -42,8 +42,8 @@ class bitflip_mask_generator #(int MBOX_DATA_AND_ECC_W = 39); endclass `else -function static logic [soc_ifc_pkg::MBOX_DATA_AND_ECC_W-1:0] get_bitflip_mask(bit do_double_bit = 1'b0); - return 2<<($urandom%(soc_ifc_pkg::MBOX_DATA_AND_ECC_W-2)) | soc_ifc_pkg::MBOX_DATA_AND_ECC_W'(do_double_bit); +function static logic [soc_ifc_pkg::CPTRA_MBOX_DATA_AND_ECC_W-1:0] get_bitflip_mask(bit do_double_bit = 1'b0); + return 2<<($urandom%(soc_ifc_pkg::CPTRA_MBOX_DATA_AND_ECC_W-2)) | soc_ifc_pkg::CPTRA_MBOX_DATA_AND_ECC_W'(do_double_bit); endfunction `endif diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv index de3e5bce2..5581934c6 100644 --- a/src/integration/tb/caliptra_top_tb_services.sv +++ b/src/integration/tb/caliptra_top_tb_services.sv @@ -34,7 +34,7 @@ module caliptra_top_tb_services - import soc_ifc_pkg::*; + import soc_ifc_pkg::*; import kv_defines_pkg::*; import caliptra_top_tb_pkg::*; #( @@ -50,9 +50,9 @@ module caliptra_top_tb_services //SRAM interface for mbox input wire logic mbox_sram_cs, input wire logic mbox_sram_we, - input wire logic [MBOX_ADDR_W-1:0] mbox_sram_addr, - input wire logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata, - output wire logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata, + input wire logic [CPTRA_MBOX_ADDR_W-1:0] mbox_sram_addr, + input wire logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata, + output wire logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata, //SRAM interface for imem input wire logic imem_cs, @@ -140,7 +140,7 @@ module caliptra_top_tb_services string abi_reg[32]; // ABI register names - logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata_bitflip; + logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata_bitflip; int cycleCntKillReq; int cycleCnt_ff; @@ -1385,7 +1385,7 @@ endgenerate //IV_NO `ifndef VERILATOR initial begin - automatic bitflip_mask_generator #(MBOX_DATA_AND_ECC_W) bitflip_gen = new(); + automatic bitflip_mask_generator #(CPTRA_MBOX_DATA_AND_ECC_W) bitflip_gen = new(); forever begin @(posedge clk) if (~|inject_mbox_sram_error) begin @@ -1450,7 +1450,7 @@ endgenerate //IV_NO $display("* TESTCASE PASSED"); $display("\nFinished : minstret = %0d, mcycle = %0d", `DEC.tlu.minstretl[31:0],`DEC.tlu.mcyclel[31:0]); $display("See \"exec.log\" for execution trace with register updates..\n"); - dump_memory_contents(MEMTYPE_LMEM, 32'h0000_0000, 32'h001_FFFF); + dump_memory_contents(MEMTYPE_LMEM, MBOX_DIR_START_ADDR, MBOX_DIR_END_ADDR); dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR); dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR); $finish; @@ -1466,7 +1466,7 @@ endgenerate //IV_NO end if (|cycleCntKillReq && (cycleCnt == (cycleCntKillReq + 100))) begin $error("Dumping memory contents at simulation end due to FAILURE"); - dump_memory_contents(MEMTYPE_LMEM, 32'h0000_0000, 32'h001_FFFF); + dump_memory_contents(MEMTYPE_LMEM, MBOX_DIR_START_ADDR, MBOX_DIR_END_ADDR); dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR); dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR); $finish; @@ -1582,11 +1582,11 @@ endgenerate //IV_NO hex_file_is_empty = $system("test -s program.hex"); if (!hex_file_is_empty) $readmemh("program.hex", imem_inst1.ram,0,`CALIPTRA_IMEM_BYTE_SIZE-1); hex_file_is_empty = $system("test -s mailbox.hex"); - if (!hex_file_is_empty) $readmemh("mailbox.hex", dummy_mbox_preloader.ram,0,32'h0001_FFFF); + if (!hex_file_is_empty) $readmemh("mailbox.hex", dummy_mbox_preloader.ram,0,MBOX_DIR_MEM_SIZE); hex_file_is_empty = $system("test -s dccm.hex"); - if (!hex_file_is_empty) $readmemh("dccm.hex", dummy_dccm_preloader.ram,0,32'h0001_FFFF); + if (!hex_file_is_empty) $readmemh("dccm.hex", dummy_dccm_preloader.ram,0,32'h0003_FFFF); hex_file_is_empty = $system("test -s iccm.hex"); - if (!hex_file_is_empty) $readmemh("iccm.hex", dummy_iccm_preloader.ram,0,32'h0001_FFFF); + if (!hex_file_is_empty) $readmemh("iccm.hex", dummy_iccm_preloader.ram,0,32'h0003_FFFF); if ($test$plusargs("CLP_BUS_LOGS")) begin tp = $fopen("trace_port.csv","w"); el = $fopen("exec.log","w"); @@ -1662,8 +1662,8 @@ caliptra_veer_sram_export veer_sram_export_inst ( //SRAM for mbox (preload raw data here) caliptra_sram #( - .DATA_WIDTH(MBOX_DATA_W), - .DEPTH (MBOX_DEPTH ) + .DATA_WIDTH(CPTRA_MBOX_DATA_W), + .DEPTH (CPTRA_MBOX_DEPTH ) ) dummy_mbox_preloader ( @@ -1679,8 +1679,8 @@ dummy_mbox_preloader // dummy_mbox_preloader with ECC bits appended caliptra_sram #( - .DATA_WIDTH(MBOX_DATA_AND_ECC_W), - .DEPTH (MBOX_DEPTH ) + .DATA_WIDTH(CPTRA_MBOX_DATA_AND_ECC_W), + .DEPTH (CPTRA_MBOX_DEPTH ) ) mbox_ram1 ( @@ -1712,9 +1712,9 @@ caliptra_sram #( // This is used to load the generated ICCM hexfile prior to // running slam_iccm_ram caliptra_sram #( - .DEPTH (16384 ), // 128KiB + .DEPTH (32768 ), // 256KiB .DATA_WIDTH(64 ), - .ADDR_WIDTH($clog2(16384)) + .ADDR_WIDTH($clog2(32768)) ) dummy_iccm_preloader ( .clk_i (clk), @@ -1730,9 +1730,9 @@ caliptra_sram #( // This is used to load the generated DCCM hexfile prior to // running slam_dccm_ram caliptra_sram #( - .DEPTH (16384 ), // 128KiB + .DEPTH (32768 ), // 256KiB .DATA_WIDTH(64 ), - .ADDR_WIDTH($clog2(16384)) + .ADDR_WIDTH($clog2(32768)) ) dummy_dccm_preloader ( .clk_i (clk), @@ -1750,10 +1750,10 @@ caliptra_sram #( //=========================================================================- task static preload_mbox; // Variables - mbox_sram_data_t ecc_data; - bit [MBOX_ADDR_W :0] addr; - int byt; - localparam NUM_BYTES = MBOX_DATA_AND_ECC_W / 8 + ((MBOX_DATA_AND_ECC_W%8) ? 1 : 0); + cptra_mbox_sram_data_t ecc_data; + bit [CPTRA_MBOX_ADDR_W:0] addr; + int byt; + localparam NUM_BYTES = CPTRA_MBOX_DATA_AND_ECC_W / 8 + ((CPTRA_MBOX_DATA_AND_ECC_W%8) ? 1 : 0); // Init `ifndef VERILATOR @@ -1761,8 +1761,8 @@ task static preload_mbox; `endif // Slam - $display("MBOX pre-load from %h to %h", 0, MBOX_DEPTH); - for (addr = 0; addr < MBOX_DEPTH; addr++) begin + $display("MBOX pre-load from %h to %h", 0, CPTRA_MBOX_DEPTH); + for (addr = 0; addr < CPTRA_MBOX_DEPTH; addr++) begin ecc_data.data = {dummy_mbox_preloader.ram[addr][3], dummy_mbox_preloader.ram[addr][2], dummy_mbox_preloader.ram[addr][1], @@ -1795,10 +1795,10 @@ task static preload_iccm; for(addr= saddr; addr <= eaddr; addr+=4) begin // FIXME hardcoded address indices? - data = {dummy_iccm_preloader.ram [addr[16:3]] [{addr[2],2'h3}], - dummy_iccm_preloader.ram [addr[16:3]] [{addr[2],2'h2}], - dummy_iccm_preloader.ram [addr[16:3]] [{addr[2],2'h1}], - dummy_iccm_preloader.ram [addr[16:3]] [{addr[2],2'h0}]}; + data = {dummy_iccm_preloader.ram [addr[17:3]] [{addr[2],2'h3}], + dummy_iccm_preloader.ram [addr[17:3]] [{addr[2],2'h2}], + dummy_iccm_preloader.ram [addr[17:3]] [{addr[2],2'h1}], + dummy_iccm_preloader.ram [addr[17:3]] [{addr[2],2'h0}]}; //data = {caliptra_top_dut.imem.mem[addr+3],caliptra_top_dut.imem.mem[addr+2],caliptra_top_dut.imem.mem[addr+1],caliptra_top_dut.imem.mem[addr]}; slam_iccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data}); end @@ -1827,10 +1827,10 @@ task static preload_dccm; for(addr=saddr; addr <= eaddr; addr+=4) begin // FIXME hardcoded address indices? - data = {dummy_dccm_preloader.ram [addr[16:3]] [{addr[2],2'h3}], - dummy_dccm_preloader.ram [addr[16:3]] [{addr[2],2'h2}], - dummy_dccm_preloader.ram [addr[16:3]] [{addr[2],2'h1}], - dummy_dccm_preloader.ram [addr[16:3]] [{addr[2],2'h0}]}; + data = {dummy_dccm_preloader.ram [addr[17:3]] [{addr[2],2'h3}], + dummy_dccm_preloader.ram [addr[17:3]] [{addr[2],2'h2}], + dummy_dccm_preloader.ram [addr[17:3]] [{addr[2],2'h1}], + dummy_dccm_preloader.ram [addr[17:3]] [{addr[2],2'h0}]}; slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data}); end $display("DCCM pre-load completed"); diff --git a/src/integration/tb/caliptra_top_tb_soc_bfm.sv b/src/integration/tb/caliptra_top_tb_soc_bfm.sv index 2b9edd627..cb6140801 100644 --- a/src/integration/tb/caliptra_top_tb_soc_bfm.sv +++ b/src/integration/tb/caliptra_top_tb_soc_bfm.sv @@ -21,6 +21,7 @@ module caliptra_top_tb_soc_bfm import axi_pkg::*; import soc_ifc_pkg::*; +import mbox_pkg::*; import caliptra_top_tb_pkg::*; #( parameter SKIP_BRINGUP = 0 ) ( diff --git a/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld b/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld index 7c093ba27..a80afd35a 100644 --- a/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld +++ b/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld @@ -28,7 +28,7 @@ SECTIONS { * data element in the instructions. This full 4-dword value should be * unique enough for ROM to identify the boundary between ICCM and DCCM contents */ _text_lma_end = _text_lma_start + SIZEOF(.text); - ASSERT(( _text_lma_end < 0x00010000), "ERROR: .text section overflows ICCM size -- FMC loaded to lower half of ICCM") + ASSERT(( _text_lma_end < 0x00020000), "ERROR: .text section overflows ICCM size -- FMC loaded to lower half of ICCM") /* Now, knowing the size of .text section, put that at address 0 for ROM to check */ .text.pre 0x0 : AT(0x0) { LONG(_text_lma_end - 0x10); LONG(0x00000000); LONG(0x00000000); LONG(0x00000000); } @@ -54,7 +54,7 @@ SECTIONS { _dccm_vma_end = .; _dccm_lma_end = _dccm_lma_start + SIZEOF(.dccm); - ASSERT(( _dccm_lma_end < 0x00020000), "ERROR: FMC firmware image overflows size of mailbox") + ASSERT(( _dccm_lma_end < 0x00040000), "ERROR: FMC firmware image overflows size of mailbox") /* Now, knowing the size of .dccm etc. sections, put that at next aligned address after .text for ROM to check */ .data.pre _text_lma_end : AT(_text_lma_end) { LONG(_dccm_lma_end - _data_lma_start); LONG(0x00000000); LONG(0x00000000); LONG(0x00000000); } @@ -65,5 +65,5 @@ SECTIONS { STACK = ALIGN(_dccm_vma_end,16) + 0x4000; ASSERT( (STACK > 0x50000000), "ERROR: Stack not in the expected address range") - ASSERT( (STACK < 0x50010000), "ERROR: Stack overflows the lower half of DCCM in FMC image -- note: upper half of DCCM is used by RT code") + ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the lower half of DCCM in FMC image -- note: upper half of DCCM is used by RT code") } diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.ld b/src/integration/test_suites/caliptra_rt/caliptra_rt.ld index ba2ca5e6e..51cc14f8c 100644 --- a/src/integration/test_suites/caliptra_rt/caliptra_rt.ld +++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.ld @@ -22,13 +22,13 @@ SECTIONS { /* --------------------- * Upper half of ICCM as VMA for Runtime * --------------------- */ - .text 0x40010000 : AT(_text_lma_start) { *(.text*) ; . = ALIGN(16); } =0x0000, + .text 0x40020000 : AT(_text_lma_start) { *(.text*) ; . = ALIGN(16); } =0x0000, /* Insert a unique value in memory (LMA) at the boundary between ICCM/DCCM * Dword of 0's is not a legal instruction, but could be a valid 'const' * data element in the instructions. This full 4-dword value should be * unique enough for ROM to identify the boundary between ICCM and DCCM contents */ _text_lma_end = _text_lma_start + SIZEOF(.text); - ASSERT(( _text_lma_end < 0x00010000), "ERROR: .text section overflows ICCM size -- RT loaded to upper half of ICCM") + ASSERT(( _text_lma_end < 0x00020000), "ERROR: .text section overflows ICCM size -- RT loaded to upper half of ICCM") /* Now, knowing the size of .text section, put that at address 0 for ROM to check */ .text.pre 0x0 : AT(0x0) { LONG(_text_lma_end - 0x10); LONG(0x00000000); LONG(0x00000000); LONG(0x00000000); } @@ -38,7 +38,7 @@ SECTIONS { * --------------------- */ /* Upper half of DCCM allocated (in val image) for remote RT FW */ . = _text_lma_end + 0x10; /* . (location counter) points to 0x0, force it back to next LMA here */ - _data_vma_start = 0x50010000; + _data_vma_start = 0x50020000; _data_lma_start = .; /* After this, . (location counter) goes back to holding VMA value */ .data _data_vma_start : AT(_data_lma_start) { *(.*data) *(.sdata*) *(.rodata*) *(.srodata*) ; . = ALIGN(4); } =0x0000, _data_lma_end = _data_lma_start + SIZEOF(.data); @@ -54,7 +54,7 @@ SECTIONS { _dccm_vma_end = .; _dccm_lma_end = _dccm_lma_start + SIZEOF(.dccm); - ASSERT(( _dccm_lma_end < 0x00020000), "ERROR: RT firmware image overflows size of mailbox") + ASSERT(( _dccm_lma_end < 0x00040000), "ERROR: RT firmware image overflows size of mailbox") /* Now, knowing the size of .dccm etc. sections, put that at next aligned address after .text for ROM to check */ .data.pre _text_lma_end : AT(_text_lma_end) { LONG(_dccm_lma_end - _data_lma_start); LONG(0x00000000); LONG(0x00000000); LONG(0x00000000); } @@ -64,6 +64,6 @@ SECTIONS { * --------------------- */ STACK = ALIGN(_dccm_vma_end,16) + 0x4000; - ASSERT( (STACK > 0x50010000), "ERROR: Stack not in the expected address range") - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM in runtime image -- note: lower half of DCCM is used by FMC code") + ASSERT( (STACK > 0x50020000), "ERROR: Stack not in the expected address range") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM in runtime image -- note: lower half of DCCM is used by FMC code") } diff --git a/src/integration/test_suites/includes/caliptra_defines.h b/src/integration/test_suites/includes/caliptra_defines.h index ad7cfd30c..d2639c6cd 100644 --- a/src/integration/test_suites/includes/caliptra_defines.h +++ b/src/integration/test_suites/includes/caliptra_defines.h @@ -73,8 +73,7 @@ #define HMAC512_MODE 0x1 /* ---- Mailbox ---- */ -#define MBOX_DIR_BASE_ADDR 0x30000000 -#define MBOX_DIR_SPAN 0x00020000 /* 128 KiB */ +#define MBOX_DIR_SPAN CLP_MBOX_SRAM_END_ADDR - CLP_MBOX_SRAM_BASE_ADDR + 1 /* 256 KiB */ #define STDOUT CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 /* ---- ECC ----*/ diff --git a/src/integration/test_suites/libs/riscv_hw_if/link.ld b/src/integration/test_suites/libs/riscv_hw_if/link.ld index 08c7b8dce..b783da210 100644 --- a/src/integration/test_suites/libs/riscv_hw_if/link.ld +++ b/src/integration/test_suites/libs/riscv_hw_if/link.ld @@ -39,7 +39,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -65,5 +65,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x4000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } diff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c index 075226f93..80b0097f6 100644 --- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c +++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c @@ -270,7 +270,7 @@ uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_coun lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R, notif_intr_en & ~(SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK | SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK)); for (uint32_t ii=0; ii < byte_count; ii+=4) { - lsu_write_32(MBOX_DIR_BASE_ADDR+ii, 0x0); + lsu_write_32(CLP_MBOX_SRAM_BASE_ADDR+ii, 0x0); } lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R, notif_intr_en); diff --git a/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.ld b/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.ld index a25d56523..5c31fd7ed 100644 --- a/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.ld +++ b/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.ld @@ -42,7 +42,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -68,5 +68,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x8000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_dma/smoke_test_dma.c b/src/integration/test_suites/smoke_test_dma/smoke_test_dma.c index 08790367e..c5cf69dca 100644 --- a/src/integration/test_suites/smoke_test_dma/smoke_test_dma.c +++ b/src/integration/test_suites/smoke_test_dma/smoke_test_dma.c @@ -103,7 +103,7 @@ void main(void) { } // Write data into mailbox using direct-mode for (uint32_t dw = 0; dw < 16; dw++) { - lsu_write_32(MBOX_DIR_BASE_ADDR + 0x4400 + (dw << 2), mbox_send_payload[dw]); + lsu_write_32(CLP_MBOX_SRAM_BASE_ADDR + 0x4400 + (dw << 2), mbox_send_payload[dw]); } lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); VPRINTF(LOW, "Sending payload from Mailbox\n"); @@ -138,7 +138,7 @@ void main(void) { fail = 1; } for (uint32_t dw = 0; dw < 16; dw++) { - mbox_read_payload[dw] = lsu_read_32(MBOX_DIR_BASE_ADDR + 0x8800 + (dw << 2)); + mbox_read_payload[dw] = lsu_read_32(CLP_MBOX_SRAM_BASE_ADDR + 0x8800 + (dw << 2)); if (mbox_read_payload[dw] != mbox_send_payload[dw]) { VPRINTF(ERROR, "mbox_read_payload[%d] (0x%x) does not match mbox_send_payload[%d] (0x%x)\n", dw, mbox_read_payload[dw], dw, mbox_send_payload[dw]); fail = 1; diff --git a/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.yml b/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.yml deleted file mode 100644 index 75e2fecea..000000000 --- a/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.yml +++ /dev/null @@ -1,3 +0,0 @@ ---- -seed: 1 -testname: smoke_test_ecc \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc_errortrigger1/caliptra_isr.h similarity index 100% rename from src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h rename to src/integration/test_suites/smoke_test_ecc_errortrigger1/caliptra_isr.h diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c b/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.c similarity index 70% rename from src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c rename to src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.c index 526421979..36db425f5 100644 --- a/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c +++ b/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.c @@ -421,215 +421,6 @@ void main() { rst_count++; printf("%c",0xf6); } - else if(rst_count == 6) { - // wait for ECC to be ready - while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); - - printf("\n TEST PCR WITH INVALID OUTPUT SIGN_R\n"); - - // Program ECC IV - reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; - offset = 0; - while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { - *reg_ptr++ = ecc_iv[offset++]; - } - - //Inject invalid zero sign_r - printf("%c",0x98); - - //inject seed to kv key reg (in RTL) - printf("Inject PRIVKEY into KV slot 7\n"); - privkey_inject_cmd = 0x88 + 0x7; - printf("%c", privkey_inject_cmd); - - printf("Inject MSG into SHA512 digest\n"); - printf("%c", 0x90); - - // Enable ECC PCR SIGNING core - printf("\nECC PCR SIGNING\n"); - lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | - ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); - - - // wait for ECC PCR SIGNING process to be done - wait_for_ecc_intr(); - if ((cptra_intr_rcv.ecc_error == 0)){ - printf("\nECC PCR r_output_outofrange error is not detected.\n"); - printf("%c", 0x1); - while(1); - } - - ecc_zeroize(); - //Issue warm reset - rst_count++; - printf("%c",0xf6); - } - else if(rst_count == 7) { - // wait for ECC to be ready - while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); - - printf("\n TEST PCR WITH INVALID INPUT COMMAND\n"); - - // Program ECC IV - reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; - offset = 0; - while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { - *reg_ptr++ = ecc_iv[offset++]; - } - - //inject seed to kv key reg (in RTL) - printf("Inject PRIVKEY into KV slot 7\n"); - privkey_inject_cmd = 0x88 + 0x7; - printf("%c", privkey_inject_cmd); - - printf("Inject MSG into SHA512 digest\n"); - printf("%c", 0x90); - - // Enable ECC PCR KEYGEN core - printf("\nECC PCR KEYGEN\n"); - lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_KEYGEN | - ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); - - - // wait for ECC KEYGEN process to be done - wait_for_ecc_intr(); - if ((cptra_intr_rcv.ecc_error == 0)){ - printf("\nECC PCR invalid command error is not detected.\n"); - printf("%c", 0x1); - while(1); - } - - ecc_zeroize(); - //Issue warm reset - rst_count++; - printf("%c",0xf6); - } - else if(rst_count == 8) { - // wait for ECC to be ready - while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); - - printf("\n TEST PCR WITH INVALID INPUT COMMAND\n"); - - // Program ECC IV - reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; - offset = 0; - while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { - *reg_ptr++ = ecc_iv[offset++]; - } - - //inject seed to kv key reg (in RTL) - printf("Inject PRIVKEY into KV slot 7\n"); - privkey_inject_cmd = 0x88 + 0x7; - printf("%c", privkey_inject_cmd); - - printf("Inject MSG into SHA512 digest\n"); - printf("%c", 0x90); - - // Enable ECC PCR VERIFYING core - printf("\nECC PCR VERIFYING\n"); - lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_VERIFYING | - ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); - - - // wait for ECC VERIFYING process to be done - wait_for_ecc_intr(); - if ((cptra_intr_rcv.ecc_error == 0)){ - printf("\nECC PCR invalid command error is not detected.\n"); - printf("%c", 0x1); - while(1); - } - - ecc_zeroize(); - //Issue warm reset - rst_count++; - printf("%c",0xf6); - } - else if(rst_count == 9) { - // wait for ECC to be ready - while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); - - printf("\n TEST INVALID OUTPUT SIGN_S\n"); - // Program ECC PRIVKEY - reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_0; - offset = 0; - while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_11) { - *reg_ptr++ = ecc_privkey[offset++]; - } - - // Program ECC MSG - reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_MSG_0; - offset = 0; - while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_MSG_11) { - *reg_ptr++ = ecc_msg[offset++]; - } - - // Program ECC IV - reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; - offset = 0; - while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { - *reg_ptr++ = ecc_iv[offset++]; - } - - //Inject invalid zero sign_s - printf("%c",0x9a); - - // Enable ECC SIGNING core - printf("\nECC SIGNING\n"); - lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING); - - // wait for ECC SIGNING process to be done - wait_for_ecc_intr(); - if ((cptra_intr_rcv.ecc_error == 0)){ - printf("\nECC s_output_outofrange error is not detected.\n"); - printf("%c", 0x1); - while(1); - } - - ecc_zeroize(); - //Issue warm reset - rst_count++; - printf("%c",0xf6); - } - else if(rst_count == 10) { - // wait for ECC to be ready - while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); - - printf("\n TEST PCR WITH INVALID OUTPUT SIGN_S\n"); - - // Program ECC IV - reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; - offset = 0; - while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { - *reg_ptr++ = ecc_iv[offset++]; - } - - //Inject invalid zero sign_s - printf("%c",0x9a); - - //inject seed to kv key reg (in RTL) - printf("Inject PRIVKEY into KV slot 7\n"); - privkey_inject_cmd = 0x88 + 0x7; - printf("%c", privkey_inject_cmd); - - printf("Inject MSG into SHA512 digest\n"); - printf("%c", 0x90); - - // Enable ECC PCR SIGNING core - printf("\nECC PCR SIGNING\n"); - lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | - ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); - - - // wait for ECC PCR SIGNING process to be done - wait_for_ecc_intr(); - if ((cptra_intr_rcv.ecc_error == 0)){ - printf("\nECC PCR s_output_outofrange error is not detected.\n"); - printf("%c", 0x1); - while(1); - } - - ecc_zeroize(); - } printf("%c",0xff); //End the test diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml b/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml new file mode 100644 index 000000000..3198e8fef --- /dev/null +++ b/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml @@ -0,0 +1,3 @@ +--- +seed: 1 +testname: smoke_test_ecc_errortrigger1 \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger2/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc_errortrigger2/caliptra_isr.h new file mode 100644 index 000000000..34b075976 --- /dev/null +++ b/src/integration/test_suites/smoke_test_ecc_errortrigger2/caliptra_isr.h @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// --------------------------------------------------------------------- +// File: caliptra_isr.h +// Description: +// Provides function declarations for use by external test files, so +// that the ISR functionality may behave like a library. +// TODO: +// This header file includes inline function definitions for event and +// test specific interrupt service behavior, so it should be copied and +// modified for each test. +// --------------------------------------------------------------------- + +#ifndef CALIPTRA_ISR_H + #define CALIPTRA_ISR_H + +#define EN_ISR_PRINTS 1 + +#include "caliptra_defines.h" +#include +#include "printf.h" + +/* --------------- symbols/typedefs --------------- */ +typedef struct { + uint32_t doe_error; + uint32_t doe_notif; + uint32_t ecc_error; + uint32_t ecc_notif; + uint32_t hmac_error; + uint32_t hmac_notif; + uint32_t kv_error; + uint32_t kv_notif; + uint32_t sha512_error; + uint32_t sha512_notif; + uint32_t sha256_error; + uint32_t sha256_notif; + uint32_t soc_ifc_error; + uint32_t soc_ifc_notif; + uint32_t sha512_acc_error; + uint32_t sha512_acc_notif; + uint32_t mldsa_error; + uint32_t mldsa_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; +} caliptra_intr_received_s; +extern volatile caliptra_intr_received_s cptra_intr_rcv; + +////////////////////////////////////////////////////////////////////////////// +// Function Declarations +// + +// Performs all the CSR setup to configure and enable vectored external interrupts +void init_interrupts(void); + +// These inline functions are used to insert event-specific functionality into the +// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr" +inline void service_doe_error_intr() {return;} +inline void service_doe_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_ecc_error_intr() { + uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) { + *reg = ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + cptra_intr_rcv.ecc_error |= ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad ecc_error_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} +inline void service_ecc_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_hmac_error_intr() {return;} +inline void service_hmac_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_kv_error_intr() {return;} +inline void service_kv_notif_intr() {return;} +inline void service_sha512_error_intr() {return;} +inline void service_sha512_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_sha256_error_intr() {return;} +inline void service_sha256_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + + +inline void service_soc_ifc_error_intr() { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_soc_ifc_notif_intr () { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_sha512_acc_error_intr() {return;} +inline void service_sha512_acc_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_mldsa_error_intr() {return;} +inline void service_mldsa_notif_intr() {return;} +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + + +#endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.c b/src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.c new file mode 100644 index 000000000..621bd8e46 --- /dev/null +++ b/src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +#include "caliptra_defines.h" +#include "caliptra_isr.h" +#include "riscv_hw_if.h" +#include "riscv-csr.h" +#include "printf.h" +#include "ecc.h" + +volatile uint32_t* stdout = (uint32_t *)STDOUT; +volatile uint32_t intr_count = 0; +volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0; +#ifdef CPT_VERBOSITY + enum printf_verbosity verbosity_g = CPT_VERBOSITY; +#else + enum printf_verbosity verbosity_g = LOW; +#endif + +volatile caliptra_intr_received_s cptra_intr_rcv = {0}; + +/* ECC test vector: + MSG = C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504DB98843548C5F623EE115F73D4C62ABC06D303B5D90D9A175087290D + PRIVKEY = F274F69D163B0C9F1FC3EBF4292AD1C4EB3CEC1C5A7DDE6F80C14292934C2055E087748D0A169C772483ADEE5EE70E17 + PUBKEY_X = D79C6D972B34A1DFC916A7B6E0A99B6B5387B34DA2187607C1AD0A4D1A8C2E4172AB5FA5D9AB58FE45E43F56BBB66BA4 + PUBKEY_Y = 5A7363932B06B4F223BEF0B60A6390265112DBBD0AAE67FEF26B465BE935B48E451E68D16F1118F2B32B4C28608749ED + SEED = 8FA8541C82A392CA74F23ED1DBFD73541C5966391B97EA73D744B0E34B9DF59ED0158063E39C09A5A055371EDF7A5441 + NONCE = 1B7EC5E548E8AAA92EC77097CA9551C9783CE682CA18FB1EDBD9F1E50BC382DB8AB39496C8EE423F8CA105CBBA7B6588 + Sign_R = 871E6EA4DDC5432CDDAA60FD7F055472D3C4DD41A5BFB26709E88C311A97093599A7C8F55B3974C19E4F5A7BFC1DD2AC + SIGN_S = 3E5552DE6403350EE70AD74E4B854D2DC4126BBF9C153A5D7A07BD4B85D06E45F850920E898FB7D34F80796DAE29365C + IV = 3401CEFAE20A737649073AC1A351E32926DB9ED0DB6B1CFFAB0493DAAFB93DDDD83EDEA28A803D0D003B2633B9D0F1BF +*/ + +void main() { + printf("----------------------------------------\n"); + printf(" Running ECC Smoke Test error_trigger !!\n"); + printf("----------------------------------------\n"); + + uint32_t ecc_msg[] = {0xC8F518D4, + 0xF3AA1BD4, + 0x6ED56C1C, + 0x3C9E16FB, + 0x800AF504, + 0xDB988435, + 0x48C5F623, + 0xEE115F73, + 0xD4C62ABC, + 0x06D303B5, + 0xD90D9A17, + 0x5087290D}; + + uint32_t ecc_privkey[] = {0xF274F69D, + 0x163B0C9F, + 0x1FC3EBF4, + 0x292AD1C4, + 0xEB3CEC1C, + 0x5A7DDE6F, + 0x80C14292, + 0x934C2055, + 0xE087748D, + 0x0A169C77, + 0x2483ADEE, + 0x5EE70E17}; + + uint32_t ecc_pubkey_x[] = {0xD79C6D97, + 0x2B34A1DF, + 0xC916A7B6, + 0xE0A99B6B, + 0x5387B34D, + 0xA2187607, + 0xC1AD0A4D, + 0x1A8C2E41, + 0x72AB5FA5, + 0xD9AB58FE, + 0x45E43F56, + 0xBBB66BA4}; + + uint32_t ecc_pubkey_y[] = {0x5A736393, + 0x2B06B4F2, + 0x23BEF0B6, + 0x0A639026, + 0x5112DBBD, + 0x0AAE67FE, + 0xF26B465B, + 0xE935B48E, + 0x451E68D1, + 0x6F1118F2, + 0xB32B4C28, + 0x608749ED}; + + uint32_t ecc_seed[] = {0x8FA8541C, + 0x82A392CA, + 0x74F23ED1, + 0xDBFD7354, + 0x1C596639, + 0x1B97EA73, + 0xD744B0E3, + 0x4B9DF59E, + 0xD0158063, + 0xE39C09A5, + 0xA055371E, + 0xDF7A5441}; + + uint32_t ecc_nonce[] = {0x1B7EC5E5, + 0x48E8AAA9, + 0x2EC77097, + 0xCA9551C9, + 0x783CE682, + 0xCA18FB1E, + 0xDBD9F1E5, + 0x0BC382DB, + 0x8AB39496, + 0xC8EE423F, + 0x8CA105CB, + 0xBA7B6588}; + + uint32_t ecc_sign_r[] = {0x871E6EA4, + 0xDDC5432C, + 0xDDAA60FD, + 0x7F055472, + 0xD3C4DD41, + 0xA5BFB267, + 0x09E88C31, + 0x1A970935, + 0x99A7C8F5, + 0x5B3974C1, + 0x9E4F5A7B, + 0xFC1DD2AC}; + + uint32_t ecc_sign_s[] = {0x3E5552DE, + 0x6403350E, + 0xE70AD74E, + 0x4B854D2D, + 0xC4126BBF, + 0x9C153A5D, + 0x7A07BD4B, + 0x85D06E45, + 0xF850920E, + 0x898FB7D3, + 0x4F80796D, + 0xAE29365C}; + + + uint32_t ecc_iv[] = {0x3401CEFA, + 0xE20A7376, + 0x49073AC1, + 0xA351E329, + 0x26DB9ED0, + 0xDB6B1CFF, + 0xAB0493DA, + 0xAFB93DDD, + 0xD83EDEA2, + 0x8A803D0D, + 0x003B2633, + 0xB9D0F1BF}; + + uint32_t value_greater_q[]= {0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xc7634d81, + 0xf4372ddf, + 0x5b1a0db2, //0x581a0db2, + 0x48b0a77a, + 0xecec196a, + 0xccc52973}; + + uint32_t value_greater_p[]= {0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xfffffffe, + 0xffffffff, + 0x0000c000, //0x00000000 + 0x00000000, + 0xffffffff}; + //Call interrupt init + init_interrupts(); + + uint8_t offset; + volatile uint32_t * reg_ptr; + uint8_t privkey_inject_cmd; + + if(rst_count == 0) { + // wait for ECC to be ready + while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); + + printf("\n TEST PCR WITH INVALID OUTPUT SIGN_R\n"); + + // Program ECC IV + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { + *reg_ptr++ = ecc_iv[offset++]; + } + + //Inject invalid zero sign_r + printf("%c",0x98); + + //inject seed to kv key reg (in RTL) + printf("Inject PRIVKEY into KV slot 7\n"); + privkey_inject_cmd = 0x88 + 0x7; + printf("%c", privkey_inject_cmd); + + printf("Inject MSG into SHA512 digest\n"); + printf("%c", 0x90); + + // Enable ECC PCR SIGNING core + printf("\nECC PCR SIGNING\n"); + lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | + ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); + + + // wait for ECC PCR SIGNING process to be done + wait_for_ecc_intr(); + if ((cptra_intr_rcv.ecc_error == 0)){ + printf("\nECC PCR r_output_outofrange error is not detected.\n"); + printf("%c", 0x1); + while(1); + } + + ecc_zeroize(); + //Issue warm reset + rst_count++; + printf("%c",0xf6); + } + else if(rst_count == 1) { + // wait for ECC to be ready + while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); + + printf("\n TEST PCR WITH INVALID INPUT COMMAND\n"); + + // Program ECC IV + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { + *reg_ptr++ = ecc_iv[offset++]; + } + + //inject seed to kv key reg (in RTL) + printf("Inject PRIVKEY into KV slot 7\n"); + privkey_inject_cmd = 0x88 + 0x7; + printf("%c", privkey_inject_cmd); + + printf("Inject MSG into SHA512 digest\n"); + printf("%c", 0x90); + + // Enable ECC PCR KEYGEN core + printf("\nECC PCR KEYGEN\n"); + lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_KEYGEN | + ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); + + + // wait for ECC KEYGEN process to be done + wait_for_ecc_intr(); + if ((cptra_intr_rcv.ecc_error == 0)){ + printf("\nECC PCR invalid command error is not detected.\n"); + printf("%c", 0x1); + while(1); + } + + ecc_zeroize(); + //Issue warm reset + rst_count++; + printf("%c",0xf6); + } + else if(rst_count == 2) { + // wait for ECC to be ready + while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); + + printf("\n TEST PCR WITH INVALID INPUT COMMAND\n"); + + // Program ECC IV + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { + *reg_ptr++ = ecc_iv[offset++]; + } + + //inject seed to kv key reg (in RTL) + printf("Inject PRIVKEY into KV slot 7\n"); + privkey_inject_cmd = 0x88 + 0x7; + printf("%c", privkey_inject_cmd); + + printf("Inject MSG into SHA512 digest\n"); + printf("%c", 0x90); + + // Enable ECC PCR VERIFYING core + printf("\nECC PCR VERIFYING\n"); + lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_VERIFYING | + ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); + + + // wait for ECC VERIFYING process to be done + wait_for_ecc_intr(); + if ((cptra_intr_rcv.ecc_error == 0)){ + printf("\nECC PCR invalid command error is not detected.\n"); + printf("%c", 0x1); + while(1); + } + + ecc_zeroize(); + //Issue warm reset + rst_count++; + printf("%c",0xf6); + } + else if(rst_count == 3) { + // wait for ECC to be ready + while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); + + printf("\n TEST INVALID OUTPUT SIGN_S\n"); + // Program ECC PRIVKEY + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_11) { + *reg_ptr++ = ecc_privkey[offset++]; + } + + // Program ECC MSG + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_MSG_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_MSG_11) { + *reg_ptr++ = ecc_msg[offset++]; + } + + // Program ECC IV + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { + *reg_ptr++ = ecc_iv[offset++]; + } + + //Inject invalid zero sign_s + printf("%c",0x9a); + + // Enable ECC SIGNING core + printf("\nECC SIGNING\n"); + lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING); + + // wait for ECC SIGNING process to be done + wait_for_ecc_intr(); + if ((cptra_intr_rcv.ecc_error == 0)){ + printf("\nECC s_output_outofrange error is not detected.\n"); + printf("%c", 0x1); + while(1); + } + + ecc_zeroize(); + //Issue warm reset + rst_count++; + printf("%c",0xf6); + } + else if(rst_count == 4) { + // wait for ECC to be ready + while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); + + printf("\n TEST PCR WITH INVALID OUTPUT SIGN_S\n"); + + // Program ECC IV + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { + *reg_ptr++ = ecc_iv[offset++]; + } + + //Inject invalid zero sign_s + printf("%c",0x9a); + + //inject seed to kv key reg (in RTL) + printf("Inject PRIVKEY into KV slot 7\n"); + privkey_inject_cmd = 0x88 + 0x7; + printf("%c", privkey_inject_cmd); + + printf("Inject MSG into SHA512 digest\n"); + printf("%c", 0x90); + + // Enable ECC PCR SIGNING core + printf("\nECC PCR SIGNING\n"); + lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | + ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); + + + // wait for ECC PCR SIGNING process to be done + wait_for_ecc_intr(); + if ((cptra_intr_rcv.ecc_error == 0)){ + printf("\nECC PCR s_output_outofrange error is not detected.\n"); + printf("%c", 0x1); + while(1); + } + + ecc_zeroize(); + } + + printf("%c",0xff); //End the test + +} + + diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml b/src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml similarity index 100% rename from src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml rename to src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml diff --git a/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc_keygen_sign/caliptra_isr.h similarity index 100% rename from src/integration/test_suites/smoke_test_ecc/caliptra_isr.h rename to src/integration/test_suites/smoke_test_ecc_keygen_sign/caliptra_isr.h diff --git a/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.c b/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.c new file mode 100644 index 000000000..e1b0f3b0a --- /dev/null +++ b/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +#include "caliptra_defines.h" +#include "caliptra_isr.h" +#include "riscv_hw_if.h" +#include "riscv-csr.h" +#include "printf.h" +#include "ecc.h" + +volatile uint32_t* stdout = (uint32_t *)STDOUT; +volatile uint32_t intr_count = 0; +#ifdef CPT_VERBOSITY + enum printf_verbosity verbosity_g = CPT_VERBOSITY; +#else + enum printf_verbosity verbosity_g = LOW; +#endif + +volatile caliptra_intr_received_s cptra_intr_rcv = {0}; + +/* ECC test vector: + MSG = C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504DB98843548C5F623EE115F73D4C62ABC06D303B5D90D9A175087290D + PRIVKEY = F274F69D163B0C9F1FC3EBF4292AD1C4EB3CEC1C5A7DDE6F80C14292934C2055E087748D0A169C772483ADEE5EE70E17 + PUBKEY_X = D79C6D972B34A1DFC916A7B6E0A99B6B5387B34DA2187607C1AD0A4D1A8C2E4172AB5FA5D9AB58FE45E43F56BBB66BA4 + PUBKEY_Y = 5A7363932B06B4F223BEF0B60A6390265112DBBD0AAE67FEF26B465BE935B48E451E68D16F1118F2B32B4C28608749ED + SEED = 8FA8541C82A392CA74F23ED1DBFD73541C5966391B97EA73D744B0E34B9DF59ED0158063E39C09A5A055371EDF7A5441 + NONCE = 1B7EC5E548E8AAA92EC77097CA9551C9783CE682CA18FB1EDBD9F1E50BC382DB8AB39496C8EE423F8CA105CBBA7B6588 + Sign_R = 871E6EA4DDC5432CDDAA60FD7F055472D3C4DD41A5BFB26709E88C311A97093599A7C8F55B3974C19E4F5A7BFC1DD2AC + SIGN_S = 3E5552DE6403350EE70AD74E4B854D2DC4126BBF9C153A5D7A07BD4B85D06E45F850920E898FB7D34F80796DAE29365C + IV = 3401CEFAE20A737649073AC1A351E32926DB9ED0DB6B1CFFAB0493DAAFB93DDDD83EDEA28A803D0D003B2633B9D0F1BF +*/ + +void main() { + printf("----------------------------------\n"); + printf(" Running ECC Smoke Test !!\n"); + printf("----------------------------------\n"); + + uint32_t ecc_msg[] = {0xC8F518D4, + 0xF3AA1BD4, + 0x6ED56C1C, + 0x3C9E16FB, + 0x800AF504, + 0xDB988435, + 0x48C5F623, + 0xEE115F73, + 0xD4C62ABC, + 0x06D303B5, + 0xD90D9A17, + 0x5087290D}; + + uint32_t ecc_privkey[] = {0xF274F69D, + 0x163B0C9F, + 0x1FC3EBF4, + 0x292AD1C4, + 0xEB3CEC1C, + 0x5A7DDE6F, + 0x80C14292, + 0x934C2055, + 0xE087748D, + 0x0A169C77, + 0x2483ADEE, + 0x5EE70E17}; + + uint32_t ecc_pubkey_x[] = {0xD79C6D97, + 0x2B34A1DF, + 0xC916A7B6, + 0xE0A99B6B, + 0x5387B34D, + 0xA2187607, + 0xC1AD0A4D, + 0x1A8C2E41, + 0x72AB5FA5, + 0xD9AB58FE, + 0x45E43F56, + 0xBBB66BA4}; + + uint32_t ecc_pubkey_y[] = {0x5A736393, + 0x2B06B4F2, + 0x23BEF0B6, + 0x0A639026, + 0x5112DBBD, + 0x0AAE67FE, + 0xF26B465B, + 0xE935B48E, + 0x451E68D1, + 0x6F1118F2, + 0xB32B4C28, + 0x608749ED}; + + uint32_t ecc_seed[] = {0x8FA8541C, + 0x82A392CA, + 0x74F23ED1, + 0xDBFD7354, + 0x1C596639, + 0x1B97EA73, + 0xD744B0E3, + 0x4B9DF59E, + 0xD0158063, + 0xE39C09A5, + 0xA055371E, + 0xDF7A5441}; + + uint32_t ecc_nonce[] = {0x1B7EC5E5, + 0x48E8AAA9, + 0x2EC77097, + 0xCA9551C9, + 0x783CE682, + 0xCA18FB1E, + 0xDBD9F1E5, + 0x0BC382DB, + 0x8AB39496, + 0xC8EE423F, + 0x8CA105CB, + 0xBA7B6588}; + + uint32_t ecc_sign_r[] = {0x871E6EA4, + 0xDDC5432C, + 0xDDAA60FD, + 0x7F055472, + 0xD3C4DD41, + 0xA5BFB267, + 0x09E88C31, + 0x1A970935, + 0x99A7C8F5, + 0x5B3974C1, + 0x9E4F5A7B, + 0xFC1DD2AC}; + + uint32_t ecc_sign_s[] = {0x3E5552DE, + 0x6403350E, + 0xE70AD74E, + 0x4B854D2D, + 0xC4126BBF, + 0x9C153A5D, + 0x7A07BD4B, + 0x85D06E45, + 0xF850920E, + 0x898FB7D3, + 0x4F80796D, + 0xAE29365C}; + + + uint32_t ecc_iv[] = {0x3401CEFA, + 0xE20A7376, + 0x49073AC1, + 0xA351E329, + 0x26DB9ED0, + 0xDB6B1CFF, + 0xAB0493DA, + 0xAFB93DDD, + 0xD83EDEA2, + 0x8A803D0D, + 0x003B2633, + 0xB9D0F1BF}; + + uint32_t ecc_privkey_dh[] = {0x52D1791F, + 0xDB4B70F8, + 0x9C0F00D4, + 0x56C2F702, + 0x3B612526, + 0x2C36A7DF, + 0x1F802311, + 0x21CCE3D3, + 0x9BE52E00, + 0xC194A413, + 0x2C4A6C76, + 0x8BCD94D2}; + + uint32_t ecc_pubkey_x_dh[] = {0x793148F1,0X787634D5,0XDA4C6D90,0X74417D05,0XE057AB62,0XF82054D1,0X0EE6B040,0X3D627954,0X7E6A8EA9,0XD1FD7742,0X7D016FE2,0X7A8B8C66}; + uint32_t ecc_pubkey_y_dh[] = {0xC6C41294,0X331D23E6,0XF480F4FB,0X4CD40504,0XC947392E,0X94F4C3F0,0X6B8F398B,0XB29E4236,0X8F7A6859,0X23DE3B67,0XBACED214,0XA1A1D128}; + uint32_t ecc_sharedkey_dh[] = {0x5EA1FC4A,0XF7256D20,0X55981B11,0X0575E0A8,0XCAE53160,0X137D904C,0X59D926EB,0X1B8456E4,0X27AA8A45,0X40884C37,0XDE159A58,0X028ABC0E}; + + //Call interrupt init + init_interrupts(); + + ecc_io seed; + ecc_io nonce; + ecc_io iv; + ecc_io privkey; + ecc_io pubkey_x; + ecc_io pubkey_y; + ecc_io msg; + ecc_io sign_r; + ecc_io sign_s; + ecc_io privkey_dh; + ecc_io pubkey_x_dh; + ecc_io pubkey_y_dh; + ecc_io sharedkey_dh; + + seed.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + seed.data[i] = ecc_seed[i]; + + nonce.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + nonce.data[i] = ecc_nonce[i]; + + iv.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + iv.data[i] = ecc_iv[i]; + + msg.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + msg.data[i] = ecc_msg[i]; + + privkey.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + privkey.data[i] = ecc_privkey[i]; + + pubkey_x.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + pubkey_x.data[i] = ecc_pubkey_x[i]; + + pubkey_y.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + pubkey_y.data[i] = ecc_pubkey_y[i]; + + sign_r.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + sign_r.data[i] = ecc_sign_r[i]; + + sign_s.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + sign_s.data[i] = ecc_sign_s[i]; + + privkey_dh.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + privkey_dh.data[i] = ecc_privkey_dh[i]; + + pubkey_x_dh.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + pubkey_x_dh.data[i] = ecc_pubkey_x_dh[i]; + + pubkey_y_dh.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + pubkey_y_dh.data[i] = ecc_pubkey_y_dh[i]; + + sharedkey_dh.kv_intf = FALSE; + for (int i = 0; i < 12; i++) + sharedkey_dh.data[i] = ecc_sharedkey_dh[i]; + + ecc_keygen_flow(seed, nonce, iv, privkey, pubkey_x, pubkey_y); + cptra_intr_rcv.ecc_notif = 0; + + ecc_signing_flow(privkey, msg, iv, sign_r, sign_s); + cptra_intr_rcv.ecc_notif = 0; + + ecc_zeroize(); + + printf("%c",0xff); //End the test + +} + + diff --git a/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml b/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml new file mode 100644 index 000000000..7bbe5f6f7 --- /dev/null +++ b/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml @@ -0,0 +1,3 @@ +--- +seed: 1 +testname: smoke_test_ecc_keygen_sign \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_ecc_verify_dh/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc_verify_dh/caliptra_isr.h new file mode 100644 index 000000000..e05ff1ce2 --- /dev/null +++ b/src/integration/test_suites/smoke_test_ecc_verify_dh/caliptra_isr.h @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// --------------------------------------------------------------------- +// File: caliptra_isr.h +// Description: +// Provides function declarations for use by external test files, so +// that the ISR functionality may behave like a library. +// TODO: +// This header file includes inline function definitions for event and +// test specific interrupt service behavior, so it should be copied and +// modified for each test. +// --------------------------------------------------------------------- + +#ifndef CALIPTRA_ISR_H + #define CALIPTRA_ISR_H + +#define EN_ISR_PRINTS 1 + +#include "caliptra_defines.h" +#include +#include "printf.h" + +/* --------------- symbols/typedefs --------------- */ +typedef struct { + uint32_t doe_error; + uint32_t doe_notif; + uint32_t ecc_error; + uint32_t ecc_notif; + uint32_t hmac_error; + uint32_t hmac_notif; + uint32_t kv_error; + uint32_t kv_notif; + uint32_t sha512_error; + uint32_t sha512_notif; + uint32_t sha256_error; + uint32_t sha256_notif; + uint32_t soc_ifc_error; + uint32_t soc_ifc_notif; + uint32_t sha512_acc_error; + uint32_t sha512_acc_notif; + uint32_t mldsa_error; + uint32_t mldsa_notif; + uint32_t axi_dma_error; + uint32_t axi_dma_notif; +} caliptra_intr_received_s; +extern volatile caliptra_intr_received_s cptra_intr_rcv; + +////////////////////////////////////////////////////////////////////////////// +// Function Declarations +// + +// Performs all the CSR setup to configure and enable vectored external interrupts +void init_interrupts(void); + +// These inline functions are used to insert event-specific functionality into the +// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr" +inline void service_doe_error_intr() {return;} +inline void service_doe_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_ecc_error_intr() {return;} +inline void service_ecc_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_hmac_error_intr() {return;} +inline void service_hmac_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_kv_error_intr() {return;} +inline void service_kv_notif_intr() {return;} +inline void service_sha512_error_intr() {return;} +inline void service_sha512_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_sha256_error_intr() {return;} +inline void service_sha256_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + + +inline void service_soc_ifc_error_intr() { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_soc_ifc_notif_intr () { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_sha512_acc_error_intr() {return;} +inline void service_sha512_acc_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_mldsa_error_intr() {return;} +inline void service_mldsa_notif_intr() {return;} +inline void service_axi_dma_error_intr() {printf("ERROR");} +inline void service_axi_dma_notif_intr() {printf("ERROR");} + + +#endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.c b/src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.c similarity index 98% rename from src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.c rename to src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.c index 602085341..c266ef765 100644 --- a/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.c +++ b/src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.c @@ -251,12 +251,6 @@ void main() { for (int i = 0; i < 12; i++) sharedkey_dh.data[i] = ecc_sharedkey_dh[i]; - ecc_keygen_flow(seed, nonce, iv, privkey, pubkey_x, pubkey_y); - cptra_intr_rcv.ecc_notif = 0; - - ecc_signing_flow(privkey, msg, iv, sign_r, sign_s); - cptra_intr_rcv.ecc_notif = 0; - ecc_verifying_flow(msg, pubkey_x, pubkey_y, sign_r, sign_s); cptra_intr_rcv.ecc_notif = 0; diff --git a/src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml b/src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml new file mode 100644 index 000000000..490bb64ca --- /dev/null +++ b/src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml @@ -0,0 +1,3 @@ +--- +seed: 1 +testname: smoke_test_ecc_verify_dh \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_kv_mldsa/smoke_test_kv_mldsa.ld b/src/integration/test_suites/smoke_test_kv_mldsa/smoke_test_kv_mldsa.ld index 9c304f2ac..0dd62632b 100644 --- a/src/integration/test_suites/smoke_test_kv_mldsa/smoke_test_kv_mldsa.ld +++ b/src/integration/test_suites/smoke_test_kv_mldsa/smoke_test_kv_mldsa.ld @@ -42,7 +42,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -68,5 +68,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x8000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } diff --git a/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c b/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c index 404afbef5..49a6b46b4 100644 --- a/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c +++ b/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c @@ -16,7 +16,7 @@ #include "riscv_hw_if.h" #include "soc_ifc.h" #include -//#include +#include #include "printf.h" #include "caliptra_isr.h" @@ -30,26 +30,17 @@ volatile uint32_t intr_count = 0; volatile caliptra_intr_received_s cptra_intr_rcv = {0}; -//#ifndef MY_RANDOM_SEED -//#define MY_RANDOM_SEED 17 -//#endif // MY_RANDOM_SEED -// -//const long seed = MY_RANDOM_SEED; - void main () { uint32_t data; uint8_t* read_addr; + uint8_t odd_offset; // Message VPRINTF(LOW, "----------------------------------\n"); VPRINTF(LOW, " Caliptra Mbox SRAM DIR Smoke Test!!\n" ); VPRINTF(LOW, "----------------------------------\n"); -// VPRINTF(LOW,"\nINFO. Using random seed = %d\n", seed); -// srand(seed); -// VPRINTF(MEDIUM, "srand done\n") - // Acquire Lock if (soc_ifc_mbox_acquire_lock(1)) { VPRINTF(ERROR, "ERROR: Failed to acquire mbox lock\n"); @@ -57,19 +48,22 @@ void main () { while(1); } + //Randomize odd or even entries to shorten test run time + odd_offset = (rand() % 2) * 4; + // Write data to fill mailbox - for (data = CLP_MBOX_SRAM_BASE_ADDR; data < CLP_MBOX_SRAM_END_ADDR; data+=4) { + for (data = CLP_MBOX_SRAM_BASE_ADDR + odd_offset; data < CLP_MBOX_SRAM_END_ADDR; data+=8) { // Data written is the address being written to lsu_write_32((uintptr_t) data, data); - if ((data & 0xfff) == 0) { + if ((data & 0xfff) == odd_offset) { VPRINTF(MEDIUM, "Writing [0x%x] to addr [0x%x]\n", data, data) } } // Read back one byte at a time and check values - read_addr = (uint8_t*) CLP_MBOX_SRAM_BASE_ADDR; + read_addr = (uint8_t*) CLP_MBOX_SRAM_BASE_ADDR + odd_offset; while(read_addr <= (uint8_t*) CLP_MBOX_SRAM_END_ADDR) { - if (((uintptr_t)read_addr & 0xfff) == 0) { + if (((uintptr_t)read_addr & 0xfff) == odd_offset) { VPRINTF(MEDIUM, "Reading from addr [0x%x]\n", read_addr) } // Data should match the address being read from @@ -97,6 +91,7 @@ void main () { while(1); } read_addr++; + read_addr += 4; } // Force unlock diff --git a/src/integration/test_suites/smoke_test_mldsa/smoke_test_mldsa.ld b/src/integration/test_suites/smoke_test_mldsa/smoke_test_mldsa.ld index a25d56523..3ad96202d 100644 --- a/src/integration/test_suites/smoke_test_mldsa/smoke_test_mldsa.ld +++ b/src/integration/test_suites/smoke_test_mldsa/smoke_test_mldsa.ld @@ -42,8 +42,8 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") - + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") + /* DCCM as VMA and LMA */ . = _bss_vma_end; _dccm_lma_start = _bss_vma_end; /* ----\___ SAME */ @@ -68,5 +68,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x8000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_mldsa_edge/smoke_test_mldsa_edge.ld b/src/integration/test_suites/smoke_test_mldsa_edge/smoke_test_mldsa_edge.ld index a25d56523..5c31fd7ed 100644 --- a/src/integration/test_suites/smoke_test_mldsa_edge/smoke_test_mldsa_edge.ld +++ b/src/integration/test_suites/smoke_test_mldsa_edge/smoke_test_mldsa_edge.ld @@ -42,7 +42,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -68,5 +68,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x8000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_mldsa_kat/smoke_test_mldsa_kat.ld b/src/integration/test_suites/smoke_test_mldsa_kat/smoke_test_mldsa_kat.ld index 83a09ceac..9a352a5ce 100644 --- a/src/integration/test_suites/smoke_test_mldsa_kat/smoke_test_mldsa_kat.ld +++ b/src/integration/test_suites/smoke_test_mldsa_kat/smoke_test_mldsa_kat.ld @@ -39,7 +39,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -65,5 +65,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x8000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } diff --git a/src/integration/test_suites/smoke_test_mldsa_keygen_sign_vfy_rand/smoke_test_mldsa_keygen_sign_vfy_rand.ld b/src/integration/test_suites/smoke_test_mldsa_keygen_sign_vfy_rand/smoke_test_mldsa_keygen_sign_vfy_rand.ld index 83a09ceac..9a352a5ce 100644 --- a/src/integration/test_suites/smoke_test_mldsa_keygen_sign_vfy_rand/smoke_test_mldsa_keygen_sign_vfy_rand.ld +++ b/src/integration/test_suites/smoke_test_mldsa_keygen_sign_vfy_rand/smoke_test_mldsa_keygen_sign_vfy_rand.ld @@ -39,7 +39,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -65,5 +65,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x8000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } diff --git a/src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.ld b/src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.ld index a25d56523..5c31fd7ed 100644 --- a/src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.ld +++ b/src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.ld @@ -42,7 +42,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -68,5 +68,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x8000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } \ No newline at end of file diff --git a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c index bade8ab0d..f04929a70 100644 --- a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c +++ b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c @@ -291,7 +291,7 @@ void run_mbox_sram_ecc(enum ecc_error_mode_type type, enum mask_config test_mask } // Allocate an array in Mailbox SRAM - volatile uint32_t* myarray = (uint32_t*) MBOX_DIR_BASE_ADDR; + volatile uint32_t* myarray = (uint32_t*) CLP_MBOX_SRAM_BASE_ADDR; for (uint32_t ii; ii < 64; ii++) { myarray[ii] = 64-ii; } @@ -607,7 +607,7 @@ uint32_t run_dccm_sram_ecc (enum mask_config test_mask, enum dccm_read_config re enum test_list cur_test; uint32_t array_in_dccm [10]; // stack is in DCCM, so this automatically goes there - uint32_t* safe_iter = (uint32_t*) MBOX_DIR_BASE_ADDR; // Pointer to mailbox memory allows us to define an iteration variable that will not be corrupted by DCCM error injection + uint32_t* safe_iter = (uint32_t*) CLP_MBOX_SRAM_BASE_ADDR; // Pointer to mailbox memory allows us to define an iteration variable that will not be corrupted by DCCM error injection uint32_t resp = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L); diff --git a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.ld b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.ld index fa12af225..512ee93ca 100644 --- a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.ld +++ b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.ld @@ -39,7 +39,7 @@ SECTIONS { _bss_vma_end = _bss_vma_start + SIZEOF(.bss); _end = _bss_lma_end; - ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB") + ASSERT( _end < 0x00018000, "ERROR: ROM size exceeds 96KiB") /* DCCM as VMA and LMA */ . = _bss_vma_end; @@ -65,5 +65,5 @@ SECTIONS { /* Stack is at the end of DCCM after .data_iccm2 */ . = ALIGN(iccm_code2_end,16); STACK = ALIGN(16) + 0x4000; - ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") + ASSERT( (STACK < 0x50040000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images") } diff --git a/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s b/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s index d345b8aee..bcf54b3af 100644 --- a/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s +++ b/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s @@ -295,9 +295,9 @@ _start: and x5, x5, x1 beq x5, x1, acquire_lock_loop0 // Load test vector from hw_data and write to Mailbox - li x8, MBOX_DIR_BASE_ADDR + li x8, CLP_MBOX_SRAM_BASE_ADDR add x8, x8, x7 /* ending destination address of test vector */ - li x6, MBOX_DIR_BASE_ADDR /* destination address to write in mailbox */ + li x6, CLP_MBOX_SRAM_BASE_ADDR /* destination address to write in mailbox */ cp_to_mbox_loop0: lw x5, 0(t3) sw x5, 0(x6) @@ -306,7 +306,7 @@ _start: bltu x6, x8, cp_to_mbox_loop0 //store the start address of the test vector //first shift it into a dword address - li x6, MBOX_DIR_BASE_ADDR + li x6, CLP_MBOX_SRAM_BASE_ADDR srli x6, x6, 2 sw x6, 0(x3) @@ -385,9 +385,9 @@ _start: and x5, x5, x1 beq x5, x1, acquire_lock_loop1 // Load test vector from hw_data and write to Mailbox - li x8, MBOX_DIR_BASE_ADDR + li x8, CLP_MBOX_SRAM_BASE_ADDR add x8, x8, x7 /* ending destination address of test vector */ - li x6, MBOX_DIR_BASE_ADDR /* destination address to write in mailbox */ + li x6, CLP_MBOX_SRAM_BASE_ADDR /* destination address to write in mailbox */ cp_to_mbox_loop1: lw x5, 0(t3) sw x5, 0(x6) @@ -396,7 +396,7 @@ _start: bltu x6, x8, cp_to_mbox_loop1 //store the start address of the test vector //first shift it into a dword address - li x6, MBOX_DIR_BASE_ADDR + li x6, CLP_MBOX_SRAM_BASE_ADDR srli x6, x6, 2 sw x6, 0(x3) diff --git a/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c b/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c index b999781fa..5067cfcd6 100644 --- a/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c +++ b/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c @@ -47,7 +47,7 @@ uint32_t test_mbox_sram_ecc() { while((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0); // Allocate a large array in Mailbox SRAM - volatile uint32_t* myarray = (uint32_t*) MBOX_DIR_BASE_ADDR; + volatile uint32_t* myarray = (uint32_t*) CLP_MBOX_SRAM_BASE_ADDR; for (uint32_t ii; ii < 64; ii++) { myarray[ii] = 64-ii; } diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf index 0d1245234..2fdf09d93 100644 --- a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf @@ -138,6 +138,7 @@ ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_sla ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf index 0d1245234..2fdf09d93 100644 --- a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_itrng.vf @@ -138,6 +138,7 @@ ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_sla ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv diff --git a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf index 1c840c016..2cd7fb9fb 100644 --- a/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf +++ b/src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top_vip.vf @@ -88,6 +88,7 @@ ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_sla ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv diff --git a/src/riscv_core/veer_el2/rtl/common_defines.sv b/src/riscv_core/veer_el2/rtl/common_defines.sv index 33a2ea04b..22bb06e48 100644 --- a/src/riscv_core/veer_el2/rtl/common_defines.sv +++ b/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -16,9 +16,9 @@ // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -// This is an automatically generated file by cwhitehead on Wed Nov 20 18:12:03 PST 2024 +// This is an automatically generated file by michnorris on Tue Jan 7 15:37:27 PST 2025 // -// cmd: veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241120_latest_fixes +// cmd: veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=256 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=256 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=Cores-VeeR-EL2 // `ifndef RV_COMMON_DEFINES `define RV_COMMON_DEFINES @@ -80,26 +80,26 @@ `define RV_LSU_STBUF_DEPTH 4 `define RV_TIMER_LEGAL_EN 1 `define RV_DCCM_BANK_BITS 2 -`define RV_DCCM_BITS 17 +`define RV_DCCM_BITS 18 `define RV_DCCM_BYTE_WIDTH 4 -`define RV_DCCM_DATA_CELL ram_8192x39 +`define RV_DCCM_DATA_CELL ram_16384x39 `define RV_DCCM_DATA_WIDTH 32 -`define RV_DCCM_EADR 32'h5001ffff +`define RV_DCCM_EADR 32'h5003ffff `define RV_DCCM_ECC_WIDTH 7 `define RV_DCCM_ENABLE 1 `define RV_DCCM_FDATA_WIDTH 39 -`define RV_DCCM_INDEX_BITS 13 +`define RV_DCCM_INDEX_BITS 14 `define RV_DCCM_NUM_BANKS 4 `define RV_DCCM_NUM_BANKS_4 `define RV_DCCM_OFFSET 28'h00000 `define RV_DCCM_REGION 4'h5 `define RV_DCCM_RESERVED 'h1400 -`define RV_DCCM_ROWS 8192 +`define RV_DCCM_ROWS 16384 `define RV_DCCM_SADR 32'h50000000 -`define RV_DCCM_SIZE 128 -`define RV_DCCM_SIZE_128 +`define RV_DCCM_SIZE 256 +`define RV_DCCM_SIZE_256 `define RV_DCCM_WIDTH_BITS 2 -`define RV_LSU_SB_BITS 17 +`define RV_LSU_SB_BITS 18 `define RV_ICACHE_2BANKS 1 `define RV_ICACHE_BANK_BITS 1 `define RV_ICACHE_BANK_HI 3 @@ -138,21 +138,21 @@ `define RV_ICCM_BANK_BITS 2 `define RV_ICCM_BANK_HI 3 `define RV_ICCM_BANK_INDEX_LO 4 -`define RV_ICCM_BITS 17 -`define RV_ICCM_DATA_CELL ram_8192x39 -`define RV_ICCM_EADR 32'h4001ffff +`define RV_ICCM_BITS 18 +`define RV_ICCM_DATA_CELL ram_16384x39 +`define RV_ICCM_EADR 32'h4003ffff `define RV_ICCM_ECC_WIDTH 7 `define RV_ICCM_ENABLE 1 -`define RV_ICCM_INDEX_BITS 13 +`define RV_ICCM_INDEX_BITS 14 `define RV_ICCM_NUM_BANKS 4 `define RV_ICCM_NUM_BANKS_4 `define RV_ICCM_OFFSET 10'h0 `define RV_ICCM_REGION 4'h4 `define RV_ICCM_RESERVED 'h1000 -`define RV_ICCM_ROWS 8192 +`define RV_ICCM_ROWS 16384 `define RV_ICCM_SADR 32'h40000000 -`define RV_ICCM_SIZE 128 -`define RV_ICCM_SIZE_128 +`define RV_ICCM_SIZE 256 +`define RV_ICCM_SIZE_256 `define RV_DEBUG_SB_MEM 'hc0580000 `define RV_EXTERNAL_DATA 'he0580000 `define RV_EXTERNAL_DATA_1 'hd0000000 diff --git a/src/riscv_core/veer_el2/rtl/el2_param.vh b/src/riscv_core/veer_el2/rtl/el2_param.vh index 36a7b1507..fec11cad1 100644 --- a/src/riscv_core/veer_el2/rtl/el2_param.vh +++ b/src/riscv_core/veer_el2/rtl/el2_param.vh @@ -75,17 +75,17 @@ parameter el2_param_t pt = '{ DATA_ACCESS_MASK6 : 36'h0FFFFFFFF , DATA_ACCESS_MASK7 : 36'h0FFFFFFFF , DCCM_BANK_BITS : 7'h02 , - DCCM_BITS : 9'h011 , + DCCM_BITS : 9'h012 , DCCM_BYTE_WIDTH : 7'h04 , DCCM_DATA_WIDTH : 10'h020 , DCCM_ECC_WIDTH : 7'h07 , DCCM_ENABLE : 5'h01 , DCCM_FDATA_WIDTH : 10'h027 , - DCCM_INDEX_BITS : 8'h0D , + DCCM_INDEX_BITS : 8'h0E , DCCM_NUM_BANKS : 9'h004 , DCCM_REGION : 8'h05 , DCCM_SADR : 36'h050000000 , - DCCM_SIZE : 14'h0080 , + DCCM_SIZE : 14'h0100 , DCCM_WIDTH_BITS : 6'h02 , DIV_BIT : 7'h04 , DIV_NEW : 5'h01 , @@ -129,16 +129,16 @@ parameter el2_param_t pt = '{ ICCM_BANK_BITS : 7'h02 , ICCM_BANK_HI : 9'h003 , ICCM_BANK_INDEX_LO : 9'h004 , - ICCM_BITS : 9'h011 , + ICCM_BITS : 9'h012 , ICCM_ECC_WIDTH : 7'h07 , ICCM_ENABLE : 5'h01 , ICCM_ICACHE : 5'h00 , - ICCM_INDEX_BITS : 8'h0D , + ICCM_INDEX_BITS : 8'h0E , ICCM_NUM_BANKS : 9'h004 , ICCM_ONLY : 5'h01 , ICCM_REGION : 8'h04 , ICCM_SADR : 36'h040000000 , - ICCM_SIZE : 14'h0080 , + ICCM_SIZE : 14'h0100 , IFU_BUS_ID : 5'h01 , IFU_BUS_PRTY : 6'h02 , IFU_BUS_TAG : 8'h03 , @@ -173,7 +173,7 @@ parameter el2_param_t pt = '{ LSU_BUS_TAG : 8'h03 , LSU_NUM_NBLOAD : 9'h004 , LSU_NUM_NBLOAD_WIDTH : 7'h02 , - LSU_SB_BITS : 9'h011 , + LSU_SB_BITS : 9'h012 , LSU_STBUF_DEPTH : 8'h04 , NO_ICCM_NO_ICACHE : 5'h00 , PIC_2CYCLE : 5'h00 , @@ -193,4 +193,4 @@ parameter el2_param_t pt = '{ TIMER_LEGAL_EN : 5'h01 , USER_MODE : 4'h0 } -// parameter el2_param_t pt = 2291'h04840400010040010840000020908200002840004808220A0C848200060410C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104420401C21386810141400000000800820428042010840830C2010281840200081002008E0C0801004040800C01002100400606810104100C08110E10068102080800000000400420300000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF000210181010441000060000000078083008007C04010020210082 +// parameter el2_param_t pt = 2291'h04840400010040010840000020908200002840004808220A0C848200060410C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104820401C21387010141400000001000820428042010840830C2010281840200081002008E0C0801004040800C01002100400606810104100C08120E10070102080800000000800420300000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF000210181010481000060000000078083008007C04010020210082 diff --git a/src/soc_ifc/config/compile.yml b/src/soc_ifc/config/compile.yml index e1f819978..85971cf8d 100644 --- a/src/soc_ifc/config/compile.yml +++ b/src/soc_ifc/config/compile.yml @@ -8,6 +8,7 @@ targets: directories: [$COMPILE_ROOT/rtl] files: - $COMPILE_ROOT/rtl/soc_ifc_pkg.sv + - $COMPILE_ROOT/rtl/mbox_pkg.sv - $COMPILE_ROOT/rtl/mbox_csr_pkg.sv - $COMPILE_ROOT/rtl/sha512_acc_csr_pkg.sv - $COMPILE_ROOT/rtl/soc_ifc_reg_pkg.sv @@ -16,6 +17,7 @@ targets: - $COMPILE_ROOT/rtl files: - $COMPILE_ROOT/rtl/soc_ifc_pkg.sv + - $COMPILE_ROOT/rtl/mbox_pkg.sv - $COMPILE_ROOT/rtl/soc_ifc_reg_pkg.sv --- provides: [soc_ifc_uvm_pkg] @@ -26,6 +28,7 @@ targets: directories: [$COMPILE_ROOT/rtl] files: - $COMPILE_ROOT/rtl/soc_ifc_pkg.sv + - $COMPILE_ROOT/rtl/mbox_pkg.sv - $COMPILE_ROOT/rtl/mbox_csr_uvm.sv - $COMPILE_ROOT/rtl/sha512_acc_csr_uvm.sv - $COMPILE_ROOT/rtl/soc_ifc_reg_uvm.sv diff --git a/src/soc_ifc/config/soc_ifc_pkg.vf b/src/soc_ifc/config/soc_ifc_pkg.vf index ebb323b9f..e14247d45 100644 --- a/src/soc_ifc/config/soc_ifc_pkg.vf +++ b/src/soc_ifc/config/soc_ifc_pkg.vf @@ -3,6 +3,7 @@ ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv diff --git a/src/soc_ifc/config/soc_ifc_tb.vf b/src/soc_ifc/config/soc_ifc_tb.vf index fa4b37f7d..47214c204 100644 --- a/src/soc_ifc/config/soc_ifc_tb.vf +++ b/src/soc_ifc/config/soc_ifc_tb.vf @@ -28,6 +28,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv diff --git a/src/soc_ifc/config/soc_ifc_top.vf b/src/soc_ifc/config/soc_ifc_top.vf index d549efc50..fcf7c1b1d 100644 --- a/src/soc_ifc/config/soc_ifc_top.vf +++ b/src/soc_ifc/config/soc_ifc_top.vf @@ -26,6 +26,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv diff --git a/src/soc_ifc/config/soc_ifc_uvm_pkg.vf b/src/soc_ifc/config/soc_ifc_uvm_pkg.vf index ef4ec886b..f5d4b191a 100644 --- a/src/soc_ifc/config/soc_ifc_uvm_pkg.vf +++ b/src/soc_ifc/config/soc_ifc_uvm_pkg.vf @@ -1,5 +1,6 @@ +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv \ No newline at end of file diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv index 92da80da6..6a08acf95 100644 --- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv +++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv @@ -33,8 +33,9 @@ `ifndef VERILATOR -interface soc_ifc_cov_if +interface soc_ifc_cov_if import soc_ifc_pkg::*; + import mbox_pkg::*; import soc_ifc_reg_pkg::*; #( parameter AXI_ADDR_WIDTH = 18 @@ -110,8 +111,8 @@ interface soc_ifc_cov_if input wire timer_intr, //SRAM interface - input mbox_sram_req_t mbox_sram_req, - input mbox_sram_resp_t mbox_sram_resp, + input cptra_mbox_sram_req_t mbox_sram_req, + input cptra_mbox_sram_resp_t mbox_sram_resp, // RV ECC Status Interface input rv_ecc_sts_t rv_ecc_sts, @@ -367,9 +368,9 @@ interface soc_ifc_cov_if dlen_in_dws_cp: coverpoint i_mbox.dlen_in_dws { bins zero = {0}; bins one = {1}; - bins range[32] = {[2:MBOX_SIZE_DWORDS-2]}; - bins almost_full = {MBOX_SIZE_DWORDS-1}; - bins full = {MBOX_SIZE_DWORDS};} + bins range[32] = {[2:CPTRA_MBOX_SIZE_DWORDS-2]}; + bins almost_full = {CPTRA_MBOX_SIZE_DWORDS-1}; + bins full = {CPTRA_MBOX_SIZE_DWORDS};} sram_single_ecc_error_cp: coverpoint i_mbox.sram_single_ecc_error; sram_double_ecc_error_cp: coverpoint i_mbox.sram_double_ecc_error; @@ -381,7 +382,7 @@ interface soc_ifc_cov_if sha_sram_hold_cp: coverpoint i_mbox.sha_sram_hold; //special scenarios - only care about bin of 1 - dlen_gt_mbox_size_cp: coverpoint i_mbox.hwif_out.mbox_dlen.length.value > MBOX_SIZE_BYTES { + dlen_gt_mbox_size_cp: coverpoint i_mbox.hwif_out.mbox_dlen.length.value > CPTRA_MBOX_SIZE_BYTES { option.comment = "DLEN is programmed greater than mailbox size"; bins one = {1};} req_wrptr_gt_dlen_cp: coverpoint (mbox_fsm_ps == MBOX_RDY_FOR_DATA) & (i_mbox.mbox_wrptr > i_mbox.dlen_in_dws) { @@ -396,7 +397,7 @@ interface soc_ifc_cov_if rdptr_gt_dlen_cp: coverpoint i_mbox.inc_rdptr & ~(i_mbox.mbox_rdptr <= i_mbox.dlen_in_dws) { option.comment = "Read pointer tried to increment passed DLEN"; bins one = {1};} - rdptr_rollover_cp: coverpoint i_mbox.inc_rdptr & ~(i_mbox.mbox_rdptr < (MBOX_SIZE_DWORDS-1)) { + rdptr_rollover_cp: coverpoint i_mbox.inc_rdptr & ~(i_mbox.mbox_rdptr < (CPTRA_MBOX_SIZE_DWORDS-1)) { option.comment = "Read pointer tried to increment passed mailbox size"; bins one = {1};} diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index dc296f49e..79ff4ee3a 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -49,7 +49,7 @@ #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (0x200) #define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) -#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (0x1fffc00) +#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (0x3fffc00) #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_UNLOCK (0x20020) #define MBOX_CSR_MBOX_UNLOCK (0x20) #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index d7ff4f947..78e952ae7 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -49,7 +49,7 @@ `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) `define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) -`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h1fffc00) +`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_UNLOCK (32'h20020) `define MBOX_CSR_MBOX_UNLOCK (32'h20) `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index 1044d9bc0..08c28216b 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -15,40 +15,67 @@ `include "caliptra_sva.svh" module mbox - import soc_ifc_pkg::*; + import mbox_pkg::*; import mbox_csr_pkg::*; #( - parameter DATA_W = 32 - ,parameter SIZE_KB = 128 + parameter DMI_REG_MBOX_DLEN_ADDR = 7'h50 + //Mailbox interface configuration + ,parameter MBOX_IFC_DATA_W = 32 + ,parameter MBOX_IFC_USER_W = 32 + ,parameter MBOX_IFC_ADDR_W = 32 + //Mailbox size configuration + ,parameter MBOX_SIZE_KB = 256 + ,parameter MBOX_DATA_W = 32 + ,parameter MBOX_ECC_DATA_W = 7 + ,localparam MBOX_SIZE_BYTES = MBOX_SIZE_KB * 1024 + ,localparam MBOX_SIZE_DWORDS = MBOX_SIZE_BYTES/4 + ,localparam MBOX_DATA_AND_ECC_W = MBOX_DATA_W + MBOX_ECC_DATA_W + ,localparam MBOX_DEPTH = (MBOX_SIZE_KB * 1024 * 8) / MBOX_DATA_W + ,localparam MBOX_ADDR_W = $clog2(MBOX_DEPTH) + ,localparam MBOX_DEPTH_LOG2 = $clog2(MBOX_DEPTH) ) ( input logic clk, input logic rst_b, //mailbox request - input logic req_dv, - output logic req_hold, - input logic dir_req_dv, - input soc_ifc_req_t req_data, + input logic req_dv, + output logic req_hold, + input logic dir_req_dv, + input logic [MBOX_IFC_ADDR_W-1:0] req_data_addr, + input logic [MBOX_IFC_DATA_W-1:0] req_data_wdata, + input logic [MBOX_IFC_USER_W-1:0] req_data_user, + input logic req_data_write, + input logic req_data_soc_req, + output logic mbox_error, - output logic [DATA_W-1:0] rdata, - output logic [DATA_W-1:0] dir_rdata, + output logic [MBOX_DATA_W-1:0] rdata, + output logic [MBOX_DATA_W-1:0] dir_rdata, input logic sha_sram_req_dv, input logic [MBOX_ADDR_W-1:0] sha_sram_req_addr, - output mbox_sram_resp_t sha_sram_resp, + output logic [MBOX_ECC_DATA_W-1:0] sha_sram_resp_ecc, + output logic [MBOX_DATA_W-1:0] sha_sram_resp_data, output logic sha_sram_hold, // Throttle the SRAM requests when writing corrected ECC + //dma req input logic dma_sram_req_dv, - input soc_ifc_req_t dma_sram_req_data, - output logic [MBOX_DATA_W-1:0] dma_sram_rdata, + input logic dma_sram_req_write, + input logic [MBOX_IFC_ADDR_W-1:0] dma_sram_req_addr, + input logic [MBOX_IFC_DATA_W-1:0] dma_sram_req_wdata, + output logic [MBOX_IFC_DATA_W-1:0] dma_sram_rdata, output logic dma_sram_hold, // Throttle the SRAM requests when SHA accel has access. output logic dma_sram_error, //SRAM interface - output mbox_sram_req_t mbox_sram_req, - input mbox_sram_resp_t mbox_sram_resp, + output logic mbox_sram_req_cs, + output logic mbox_sram_req_we, + output logic [MBOX_ADDR_W-1:0] mbox_sram_req_addr, + output logic [MBOX_ECC_DATA_W-1:0] mbox_sram_req_ecc, + output logic [MBOX_DATA_W-1:0] mbox_sram_req_wdata, + input logic [MBOX_ECC_DATA_W-1:0] mbox_sram_resp_ecc, + input logic [MBOX_DATA_W-1:0] mbox_sram_resp_data, // ECC Status output logic sram_single_ecc_error, @@ -74,11 +101,6 @@ module mbox ); -localparam MBOX_SIZE_IN_BYTES = SIZE_KB*1024; -localparam MBOX_SIZE_IN_DW = (MBOX_SIZE_IN_BYTES)/4; -localparam DEPTH = (MBOX_SIZE_IN_DW * 32) / DATA_W; -localparam DEPTH_LOG2 = $clog2(DEPTH); - //this module is used to instantiate a single mailbox instance //requests within the address space of this mailbox are routed here from the top level @@ -112,22 +134,22 @@ logic arc_MBOX_EXECUTE_UC_MBOX_ERROR; logic arc_MBOX_EXECUTE_SOC_MBOX_ERROR; logic arc_MBOX_EXECUTE_TAP_MBOX_ERROR; //sram -logic [DATA_W-1:0] sram_wdata; +logic [MBOX_DATA_W-1:0] sram_wdata; logic [MBOX_ECC_DATA_W-1:0] sram_wdata_ecc; -logic [DEPTH_LOG2-1:0] sram_waddr; -logic [DEPTH_LOG2-1:0] mbox_wrptr, mbox_wrptr_nxt; +logic [MBOX_DEPTH_LOG2-1:0] sram_waddr; +logic [MBOX_DEPTH_LOG2-1:0] mbox_wrptr, mbox_wrptr_nxt; logic mbox_wr_full, mbox_wr_full_nxt; logic inc_wrptr; -logic [DEPTH_LOG2-1:0] sram_rdaddr; -logic [DEPTH_LOG2-1:0] mbox_rdptr, mbox_rdptr_nxt; +logic [MBOX_DEPTH_LOG2-1:0] sram_rdaddr; +logic [MBOX_DEPTH_LOG2-1:0] mbox_rdptr, mbox_rdptr_nxt; logic mbox_rd_full, mbox_rd_full_nxt; logic inc_rdptr; logic rst_mbox_rdptr; logic rst_mbox_wrptr; logic sram_rd_ecc_en; -logic [DATA_W-1:0] sram_rdata; +logic [MBOX_DATA_W-1:0] sram_rdata; logic [MBOX_ECC_DATA_W-1:0] sram_rdata_ecc; -logic [DATA_W-1:0] sram_rdata_cor; +logic [MBOX_DATA_W-1:0] sram_rdata_cor; logic [MBOX_ECC_DATA_W-1:0] sram_rdata_cor_ecc; logic sram_we; logic mbox_protocol_sram_we; @@ -136,15 +158,15 @@ logic dir_req_dv_q, dir_req_rd_phase; logic dir_req_wr_ph; logic dma_sram_req_dv_q, dma_sram_req_rd_phase; logic mask_rdata; -logic [DEPTH_LOG2-1:0] dir_req_addr; +logic [MBOX_DEPTH_LOG2-1:0] dir_req_addr; logic soc_has_lock, soc_has_lock_nxt; logic valid_requester; logic valid_receiver; -logic [DEPTH_LOG2:0] mbox_dlen_in_dws; +logic [MBOX_DEPTH_LOG2:0] mbox_dlen_in_dws; logic latch_dlen_in_dws; -logic [DEPTH_LOG2:0] dlen_in_dws, dlen_in_dws_nxt; +logic [MBOX_DEPTH_LOG2:0] dlen_in_dws, dlen_in_dws_nxt; logic rdptr_inc_valid; logic mbox_rd_valid, mbox_rd_valid_f; logic wrptr_inc_valid; @@ -155,7 +177,7 @@ logic tap_mode; logic tap_mbox_data_avail; //csr -logic [DATA_W-1:0] csr_rdata; +logic [MBOX_DATA_W-1:0] csr_rdata; logic read_error; logic write_error; @@ -170,15 +192,15 @@ assign tap_mode = hwif_out.tap_mode.enabled.value; //1) uC requests are valid if uc has lock //2) SoC requests are valid if soc has lock and it's the AXI ID that locked it always_comb valid_requester = hwif_out.mbox_lock.lock.value & - ((~req_data.soc_req & (~soc_has_lock || (mbox_fsm_ps == MBOX_EXECUTE_UC))) | - ( req_data.soc_req & soc_has_lock & (req_data.user == hwif_out.mbox_user.user.value[SOC_IFC_USER_W-1:0]))); + ((~req_data_soc_req & (~soc_has_lock || (mbox_fsm_ps == MBOX_EXECUTE_UC))) | + ( req_data_soc_req & soc_has_lock & (req_data_user == hwif_out.mbox_user.user.value[MBOX_IFC_USER_W-1:0]))); //Determine if this is a valid request from the receiver side always_comb valid_receiver = hwif_out.mbox_lock.lock.value & //Receiver is valid when in their execute state //if they don't have the lock - ((~req_data.soc_req & soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC )) | - ( req_data.soc_req & ~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_SOC)) | + ((~req_data_soc_req & soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC )) | + ( req_data_soc_req & ~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_SOC)) | //Receiver is valid when they are reading a response to their request (valid_requester & ((soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_SOC)) | (~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC))))); @@ -221,24 +243,24 @@ always_comb arc_FORCE_MBOX_UNLOCK = hwif_out.mbox_unlock.unlock.value; // by writing to mbox_status (since it's a valid_receiver). // FIXED! valid_receiver is restricted by FSM state now. always_comb arc_MBOX_RDY_FOR_CMD_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_CMD) && - req_dv && req_data.soc_req && ~req_hold && valid_requester && - (req_data.write ? (!hwif_out.mbox_cmd.command.swmod) : + req_dv && req_data_soc_req && ~req_hold && valid_requester && + (req_data_write ? (!hwif_out.mbox_cmd.command.swmod) : (hwif_out.mbox_dataout.dataout.swacc)); always_comb arc_MBOX_RDY_FOR_DLEN_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_DLEN) && - req_dv && req_data.soc_req && ~req_hold && valid_requester && - (req_data.write ? (!hwif_out.mbox_dlen.length.swmod) : + req_dv && req_data_soc_req && ~req_hold && valid_requester && + (req_data_write ? (!hwif_out.mbox_dlen.length.swmod) : (hwif_out.mbox_dataout.dataout.swacc)); always_comb arc_MBOX_RDY_FOR_DATA_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_DATA) && - req_dv && req_data.soc_req && ~req_hold && valid_requester && - (req_data.write ? (!(hwif_out.mbox_datain.datain.swmod || hwif_out.mbox_execute.execute.swmod)) : + req_dv && req_data_soc_req && ~req_hold && valid_requester && + (req_data_write ? (!(hwif_out.mbox_datain.datain.swmod || hwif_out.mbox_execute.execute.swmod)) : (hwif_out.mbox_dataout.dataout.swacc)); always_comb arc_MBOX_EXECUTE_UC_MBOX_ERROR = (mbox_fsm_ps == MBOX_EXECUTE_UC) && - req_dv && req_data.soc_req && ~req_hold && valid_requester && - (req_data.write ? (1'b1/* any write by 'valid' soc is illegal here */) : + req_dv && req_data_soc_req && ~req_hold && valid_requester && + (req_data_write ? (1'b1/* any write by 'valid' soc is illegal here */) : (hwif_out.mbox_dataout.dataout.swacc)); always_comb arc_MBOX_EXECUTE_SOC_MBOX_ERROR = (mbox_fsm_ps == MBOX_EXECUTE_SOC) && - req_dv && req_data.soc_req && ~req_hold && - (req_data.write ? ((valid_requester && !(hwif_out.mbox_execute.execute.swmod)) || + req_dv && req_data_soc_req && ~req_hold && + (req_data_write ? ((valid_requester && !(hwif_out.mbox_execute.execute.swmod)) || (~soc_has_lock && !(hwif_out.mbox_status.status.swmod))) : (1'b0 /* any read allowed by SoC during this stage; dataout consumption is expected */)); always_comb arc_MBOX_EXECUTE_TAP_MBOX_ERROR = 1'b0; @@ -248,21 +270,21 @@ always_comb arc_MBOX_EXECUTE_TAP_MBOX_ERROR = 1'b0; //Store the dlen as a ptr to the last entry always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_TAP | arc_MBOX_EXECUTE_TAP_MBOX_EXECUTE_UC; -always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW[DEPTH_LOG2:0] : - (hwif_out.mbox_dlen.length.value[DEPTH_LOG2+2:2]) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]); +always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_BYTES) ? MBOX_SIZE_DWORDS[MBOX_DEPTH_LOG2:0] : + (hwif_out.mbox_dlen.length.value[MBOX_DEPTH_LOG2+2:2]) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]); //latched dlen is the smaller of the programmed dlen or the current wrptr //this avoids a case where a sender writes less than programmed and the receiver can read beyond that //if the mailbox is full (flag set when writing last entry), always take the programmed dlen always_comb dlen_in_dws_nxt = (~mbox_wr_full & ({1'b0,mbox_wrptr} < mbox_dlen_in_dws)) ? {1'b0,mbox_wrptr} : mbox_dlen_in_dws; // Restrict the read pointer from passing the dlen or rolling over -always_comb rdptr_inc_valid = ({1'b0,mbox_rdptr} < dlen_in_dws) & (mbox_rdptr < (MBOX_SIZE_IN_DW-1)); +always_comb rdptr_inc_valid = ({1'b0,mbox_rdptr} < dlen_in_dws) & (mbox_rdptr < (MBOX_SIZE_DWORDS-1)); // No more valid reads if we read the last entry // On pre-load of entry 0, ensure that next dlen isn't 0 // Restrict reads once read pointer has passed the dlen always_comb mbox_rd_valid = (rst_mbox_rdptr & (dlen_in_dws_nxt != 0)) | (~rst_mbox_rdptr & ~mbox_rd_full & ({1'b0,mbox_rdptr} < dlen_in_dws)); // Restrict the write pointer from rolling over -always_comb wrptr_inc_valid = mbox_wrptr < (MBOX_SIZE_IN_DW-1); +always_comb wrptr_inc_valid = mbox_wrptr < (MBOX_SIZE_DWORDS-1); always_comb begin : mbox_fsm_combo @@ -281,11 +303,11 @@ always_comb begin : mbox_fsm_combo MBOX_IDLE: begin if (arc_MBOX_IDLE_MBOX_RDY_FOR_CMD) begin mbox_fsm_ns = MBOX_RDY_FOR_CMD; - soc_has_lock_nxt = req_data.soc_req; //remember if soc or uc requested the lock + soc_has_lock_nxt = req_data_soc_req; //remember if soc or uc requested the lock end // Flag a non-fatal error, but don't change states, if mbox is already IDLE // when an unexpected SOC access happens - if (req_dv && req_data.soc_req && ~req_hold && (req_data.write || hwif_out.mbox_dataout.dataout.swacc)) begin + if (req_dv && req_data_soc_req && ~req_hold && (req_data_write || hwif_out.mbox_dataout.dataout.swacc)) begin mbox_protocol_error_nxt.axs_without_lock = 1'b1; end end @@ -347,8 +369,8 @@ always_comb begin : mbox_fsm_combo //only uC can write to datain here to respond to SoC MBOX_EXECUTE_UC: begin uc_mbox_data_avail = 1; - inc_rdptr = dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & ~req_data.soc_req & ~req_hold); - inc_wrptr = hwif_out.mbox_datain.datain.swmod & ~req_data.soc_req & ~req_hold; + inc_rdptr = dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & ~req_data_soc_req & ~req_hold); + inc_wrptr = hwif_out.mbox_datain.datain.swmod & ~req_data_soc_req & ~req_hold; if (arc_MBOX_EXECUTE_UC_MBOX_IDLE) begin mbox_fsm_ns = MBOX_IDLE; end @@ -379,7 +401,7 @@ always_comb begin : mbox_fsm_combo //Only SoC can write to datain here to respond to uC MBOX_EXECUTE_SOC: begin soc_mbox_data_avail = 1; - inc_rdptr = (dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & req_data.soc_req & valid_receiver & ~req_hold)); + inc_rdptr = (dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & req_data_soc_req & valid_receiver & ~req_hold)); if (arc_MBOX_EXECUTE_SOC_MBOX_IDLE) begin mbox_fsm_ns = MBOX_IDLE; end @@ -439,9 +461,9 @@ end // Any ol' AXI_USER is fine for reg-reads (except dataout) // NOTE: This only captures accesses by AXI agents that are valid, but do not // have lock. Invalid agent accesses are blocked by arbiter. -assign mbox_inv_axi_user_axs = req_dv && req_data.soc_req && !req_hold && +assign mbox_inv_axi_user_axs = req_dv && req_data_soc_req && !req_hold && !valid_requester && !valid_receiver && - (req_data.write || hwif_out.mbox_dataout.dataout.swacc); + (req_data_write || hwif_out.mbox_dataout.dataout.swacc); //increment read ptr only if its allowed @@ -469,8 +491,8 @@ always_ff @(posedge clk or negedge rst_b) begin mbox_fsm_ps <= mbox_fsm_ns; soc_has_lock <= arc_MBOX_IDLE_MBOX_RDY_FOR_CMD ? soc_has_lock_nxt : hwif_out.mbox_lock.lock.value ? soc_has_lock : '0; - dir_req_rd_phase <= dir_req_dv_q & ~sha_sram_req_dv & ~(dma_sram_req_dv_q & dma_sram_req_data.write) & ~req_data.write; - dma_sram_req_rd_phase <= dma_sram_req_dv_q & ~sha_sram_req_dv & ~dma_sram_req_data.write; + dir_req_rd_phase <= dir_req_dv_q & ~sha_sram_req_dv & ~(dma_sram_req_dv_q & dma_sram_req_write) & ~req_data_write; + dma_sram_req_rd_phase <= dma_sram_req_dv_q & ~sha_sram_req_dv & ~dma_sram_req_write; mbox_wrptr <= ((inc_wrptr & wrptr_inc_valid) | rst_mbox_wrptr) ? mbox_wrptr_nxt : mbox_wrptr; mbox_wr_full <= (inc_wrptr | rst_mbox_wrptr) ? mbox_wr_full_nxt : mbox_wr_full; mbox_rdptr <= (mbox_protocol_sram_rd) ? mbox_rdptr_nxt : mbox_rdptr; @@ -481,7 +503,7 @@ always_ff @(posedge clk or negedge rst_b) begin dlen_in_dws <= latch_dlen_in_dws ? dlen_in_dws_nxt : dlen_in_dws; mbox_protocol_error <= mbox_protocol_error_nxt; //enable ecc for mbox protocol, direct reads, or SHA direct reads - sram_rd_ecc_en <= mbox_protocol_sram_rd | (dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write) | (dma_sram_req_dv_q & ~dma_sram_req_data.write) | sha_sram_req_dv; + sram_rd_ecc_en <= mbox_protocol_sram_rd | (dir_req_dv_q & ~sha_sram_req_dv & ~req_data_write) | (dma_sram_req_dv_q & ~dma_sram_req_write) | sha_sram_req_dv; end end @@ -498,10 +520,10 @@ always_comb dma_sram_req_dv_q = dma_sram_req_dv & hwif_out.mbox_lock.lock.value always_comb dir_req_dv_q = (dir_req_dv & ~dir_req_rd_phase & hwif_out.mbox_lock.lock.value & (~soc_has_lock | (mbox_fsm_ps == MBOX_EXECUTE_UC))) | (dma_sram_req_dv_q) | sha_sram_req_dv; -always_comb dir_req_wr_ph = dir_req_dv_q & ~sha_sram_req_dv & ((~dma_sram_req_dv_q & req_data.write) | (dma_sram_req_dv_q & dma_sram_req_data.write)); +always_comb dir_req_wr_ph = dir_req_dv_q & ~sha_sram_req_dv & ((~dma_sram_req_dv_q & req_data_write) | (dma_sram_req_dv_q & dma_sram_req_write)); always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : - dma_sram_req_dv_q ? dma_sram_req_data.addr[DEPTH_LOG2+1:2] : - req_data.addr[DEPTH_LOG2+1:2]; + dma_sram_req_dv_q ? dma_sram_req_addr[MBOX_DEPTH_LOG2+1:2] : + req_data_addr[MBOX_DEPTH_LOG2+1:2]; // Arb precedence: // SHA accelerator: highest @@ -510,13 +532,13 @@ always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : // No arbitration/round-robin -- this is strictly observed for every txn //Direct read from uC, stall 1 clock dv_q will be de-asserted second clock -always_comb req_hold = (dir_req_dv_q & ~sha_sram_req_dv & ~dma_sram_req_dv_q & ~req_data.write) | +always_comb req_hold = (dir_req_dv_q & ~sha_sram_req_dv & ~dma_sram_req_dv_q & ~req_data_write) | //Direct access from uC while sha accelerator or DMA is accessing (dir_req_dv & ~dir_req_rd_phase & (sha_sram_req_dv | dma_sram_req_dv_q | dma_sram_req_rd_phase)) | //in an update cycle for dataout register (hwif_out.mbox_dataout.dataout.swacc & mbox_protocol_sram_rd_f); -always_comb dma_sram_hold = (sha_sram_req_dv && !dma_sram_req_rd_phase) || (dma_sram_req_dv_q && !dma_sram_req_data.write); +always_comb dma_sram_hold = (sha_sram_req_dv && !dma_sram_req_rd_phase) || (dma_sram_req_dv_q && !dma_sram_req_write); always_comb sha_sram_hold = 1'b0; //SRAM interface @@ -527,7 +549,7 @@ always_comb sram_rdaddr = dir_req_dv_q ? dir_req_addr : always_comb sram_waddr = dir_req_dv_q ? dir_req_addr : mbox_wrptr; //data phase after request for direct access //We want to mask the read data for certain accesses -always_comb rdata = ({DATA_W{~mask_rdata}} & csr_rdata); +always_comb rdata = ({MBOX_DATA_W{~mask_rdata}} & csr_rdata); always_comb dir_rdata = dir_req_rd_phase ? sram_rdata_cor : '0; always_comb dma_sram_rdata = dma_sram_req_rd_phase ? sram_rdata_cor : '0; @@ -535,15 +557,16 @@ always_comb dma_sram_error = 1'b0; // TODO: ecc error? always_comb begin: mbox_sram_inf //read live on direct access, or when pointer has been incremented, for pre-load on read pointer reset, or ecc correction - mbox_sram_req.cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd; - mbox_sram_req.we = sram_we; - mbox_sram_req.addr = sram_we ? sram_waddr : sram_rdaddr; - mbox_sram_req.wdata.data = sram_wdata; - mbox_sram_req.wdata.ecc = sram_wdata_ecc; - - sram_rdata = mbox_sram_resp.rdata.data; - sram_rdata_ecc = mbox_sram_resp.rdata.ecc; - sha_sram_resp = '{rdata: '{ecc:sram_rdata_cor_ecc , data:sram_rdata_cor}}; + mbox_sram_req_cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd; + mbox_sram_req_we = sram_we; + mbox_sram_req_addr = sram_we ? sram_waddr : sram_rdaddr; + mbox_sram_req_wdata = sram_wdata; + mbox_sram_req_ecc = sram_wdata_ecc; + + sram_rdata = mbox_sram_resp_data; + sram_rdata_ecc = mbox_sram_resp_ecc; + sha_sram_resp_ecc = sram_rdata_cor_ecc; + sha_sram_resp_data = sram_rdata_cor; end // From RISC-V core beh_lib.sv @@ -555,8 +578,8 @@ rvecc_encode mbox_ecc_encode ( ); // synthesis translate_off `ifdef CLP_ASSERT_ON -initial assert(DATA_W == 32) else - $error("%m::rvecc_encode supports 32-bit data width; must change SRAM ECC implementation to support DATA_W = %d", DATA_W); +initial assert(MBOX_DATA_W == 32) else + $error("%m::rvecc_encode supports 32-bit data width; must change SRAM ECC implementation to support MBOX_DATA_W = %d", MBOX_DATA_W); `endif // synthesis translate_on rvecc_decode ecc_decode ( @@ -573,32 +596,32 @@ rvecc_decode ecc_decode ( //control for sram write and read pointer //SoC access is controlled by mailbox, each subsequent read or write increments the pointer //uC accesses can specify the specific read or write address, or rely on mailbox to control -always_comb sram_wdata = (dma_sram_req_dv_q && dma_sram_req_data.write ) ? dma_sram_req_data.wdata : - dmi_inc_wrptr ? dmi_reg_wdata : req_data.wdata; +always_comb sram_wdata = (dma_sram_req_dv_q && dma_sram_req_write ) ? dma_sram_req_wdata : + dmi_inc_wrptr ? dmi_reg_wdata : req_data_wdata; //in ready for data state we increment the pointer each time we write always_comb mbox_wrptr_nxt = rst_mbox_wrptr ? '0 : (inc_wrptr & wrptr_inc_valid) ? mbox_wrptr + 'd1 : mbox_wrptr; -always_comb mbox_wr_full_nxt = rst_mbox_wrptr ? '0 : inc_wrptr & (mbox_wrptr == (DEPTH-1)); +always_comb mbox_wr_full_nxt = rst_mbox_wrptr ? '0 : inc_wrptr & (mbox_wrptr == (MBOX_DEPTH-1)); //in execute state we increment the pointer each time we write always_comb mbox_rdptr_nxt = rst_mbox_rdptr ? 'd1 : (inc_rdptr & rdptr_inc_valid) ? mbox_rdptr + 'd1 : mbox_rdptr; -always_comb mbox_rd_full_nxt = rst_mbox_rdptr ? '0 : inc_rdptr & (mbox_rdptr == (DEPTH-1)); +always_comb mbox_rd_full_nxt = rst_mbox_rdptr ? '0 : inc_rdptr & (mbox_rdptr == (MBOX_DEPTH-1)); //Intterupts //Notify uC when it has the lock and SoC is requesting the lock -always_comb soc_req_mbox_lock = hwif_out.mbox_lock.lock.value & ~soc_has_lock & hwif_out.mbox_lock.lock.swmod & req_data.soc_req; +always_comb soc_req_mbox_lock = hwif_out.mbox_lock.lock.value & ~soc_has_lock & hwif_out.mbox_lock.lock.swmod & req_data_soc_req; always_comb hwif_in.cptra_rst_b = rst_b; -always_comb hwif_in.mbox_user.user.next = 32'(req_data.user); +always_comb hwif_in.mbox_user.user.next = 32'(req_data_user); always_comb hwif_in.mbox_status.mbox_fsm_ps.next = mbox_fsm_ps; -always_comb hwif_in.soc_req = req_data.soc_req; +always_comb hwif_in.soc_req = req_data_soc_req; //check the requesting ID: //don't update mailbox data if lock hasn't been acquired //if uc has the lock, check that this request is from uc @@ -627,13 +650,13 @@ always_comb hwif_in.mbox_status.ecc_double_error.hwset = sram_double_ecc_error; always_comb hwif_in.mbox_status.soc_has_lock.next = soc_has_lock; always_comb hwif_in.mbox_status.mbox_rdptr.next = mbox_rdptr; -always_comb hwif_in.mbox_dlen.length.we = dmi_reg_wen & (dmi_reg_addr == DMI_REG_MBOX_DLEN); +always_comb hwif_in.mbox_dlen.length.we = dmi_reg_wen & (dmi_reg_addr == DMI_REG_MBOX_DLEN_ADDR); always_comb hwif_in.mbox_dlen.length.next = dmi_reg_wdata; always_comb dmi_reg.MBOX_DLEN = hwif_out.mbox_dlen.length.value; always_comb dmi_reg.MBOX_DOUT = hwif_out.mbox_dataout.dataout.value; -always_comb dmi_reg.MBOX_STATUS = {7'd0, /* [31:25] */ - hwif_out.mbox_status.mbox_rdptr.value, /* [24:10]*/ +always_comb dmi_reg.MBOX_STATUS = {6'd0, /* [31:26] */ + hwif_out.mbox_status.mbox_rdptr.value, /* [25:10]*/ hwif_out.mbox_status.soc_has_lock.value, /* [9] */ hwif_out.mbox_status.mbox_fsm_ps.value, /* [8:6] */ hwif_out.mbox_status.ecc_double_error.value, /* [5] */ @@ -651,10 +674,10 @@ mbox_csr1( .clk(clk), .rst('0), - .s_cpuif_req(req_dv & (req_data.addr[SOC_IFC_ADDR_W-1:MBOX_CSR_ADDR_WIDTH] == MBOX_REG_START_ADDR[SOC_IFC_ADDR_W-1:MBOX_CSR_ADDR_WIDTH])), - .s_cpuif_req_is_wr(req_data.write), - .s_cpuif_addr(req_data.addr[MBOX_CSR_ADDR_WIDTH-1:0]), - .s_cpuif_wr_data(req_data.wdata), + .s_cpuif_req(req_dv), + .s_cpuif_req_is_wr(req_data_write), + .s_cpuif_addr(req_data_addr[MBOX_CSR_ADDR_WIDTH-1:0]), + .s_cpuif_wr_data(req_data_wdata), .s_cpuif_wr_biten('1), // FIXME .s_cpuif_req_stall_wr(s_cpuif_req_stall_wr_nc), .s_cpuif_req_stall_rd(s_cpuif_req_stall_rd_nc), @@ -670,6 +693,6 @@ mbox_csr1( `CALIPTRA_ASSERT_MUTEX(ERR_MBOX_ACCESS_MUTEX, {dir_req_dv_q , mbox_protocol_sram_we , mbox_protocol_sram_rd }, clk, !rst_b) //`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_DIR_SHA_COLLISION, {dir_req_dv, sha_sram_req_dv}, clk, !rst_b) -`CALIPTRA_ASSERT_NEVER(ERR_MBOX_DIR_REQ_FROM_SOC, (dir_req_dv & req_data.soc_req), clk, !rst_b) +`CALIPTRA_ASSERT_NEVER(ERR_MBOX_DIR_REQ_FROM_SOC, (dir_req_dv & req_data_soc_req), clk, !rst_b) endmodule diff --git a/src/soc_ifc/rtl/mbox_csr.rdl b/src/soc_ifc/rtl/mbox_csr.rdl index 6878be2d9..524ea8cfe 100644 --- a/src/soc_ifc/rtl/mbox_csr.rdl +++ b/src/soc_ifc/rtl/mbox_csr.rdl @@ -184,7 +184,7 @@ addrmap mbox_csr { [br]Caliptra Access: RO [br]SOC Access: RO [br]TAP Access [in debug/manuf mode]: RO"; - sw=r; hw=rw;} mbox_rdptr[15] = 0; + sw=r; hw=rw;} mbox_rdptr[16] = 0; } mbox_status; reg { diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv index 3fdb1d920..e516b3061 100644 --- a/src/soc_ifc/rtl/mbox_csr.sv +++ b/src/soc_ifc/rtl/mbox_csr.sv @@ -170,7 +170,7 @@ module mbox_csr ( logic load_next; } soc_has_lock; struct packed{ - logic [14:0] next; + logic [15:0] next; logic load_next; } mbox_rdptr; } mbox_status; @@ -242,7 +242,7 @@ module mbox_csr ( logic value; } soc_has_lock; struct packed{ - logic [14:0] value; + logic [15:0] value; } mbox_rdptr; } mbox_status; struct packed{ @@ -538,7 +538,7 @@ module mbox_csr ( assign hwif_out.mbox_status.soc_has_lock.value = field_storage.mbox_status.soc_has_lock.value; // Field: mbox_csr.mbox_status.mbox_rdptr always_comb begin - automatic logic [14:0] next_c; + automatic logic [15:0] next_c; automatic logic load_next_c; next_c = field_storage.mbox_status.mbox_rdptr.value; load_next_c = '0; @@ -551,7 +551,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.mbox_rdptr.value <= 15'h0; + field_storage.mbox_status.mbox_rdptr.value <= 16'h0; end else if(field_combo.mbox_status.mbox_rdptr.load_next) begin field_storage.mbox_status.mbox_rdptr.value <= field_combo.mbox_status.mbox_rdptr.next; end @@ -634,8 +634,8 @@ module mbox_csr ( assign readback_array[7][5:5] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.ecc_double_error.value : '0; assign readback_array[7][8:6] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.mbox_fsm_ps.value : '0; assign readback_array[7][9:9] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.soc_has_lock.value : '0; - assign readback_array[7][24:10] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.mbox_rdptr.value : '0; - assign readback_array[7][31:25] = '0; + assign readback_array[7][25:10] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.mbox_rdptr.value : '0; + assign readback_array[7][31:26] = '0; assign readback_array[8][0:0] = (decoded_reg_strb.mbox_unlock && !decoded_req_is_wr) ? field_storage.mbox_unlock.unlock.value : '0; assign readback_array[8][31:1] = '0; assign readback_array[9][0:0] = (decoded_reg_strb.tap_mode && !decoded_req_is_wr) ? field_storage.tap_mode.enabled.value : '0; diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv index 18ac6cbf1..0736e2356 100644 --- a/src/soc_ifc/rtl/mbox_csr_pkg.sv +++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv @@ -70,7 +70,7 @@ package mbox_csr_pkg; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__in_t; typedef struct packed{ - logic [14:0] next; + logic [15:0] next; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__in_t; typedef struct packed{ @@ -178,7 +178,7 @@ package mbox_csr_pkg; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__out_t; typedef struct packed{ - logic [14:0] value; + logic [15:0] value; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__out_t; typedef struct packed{ diff --git a/src/soc_ifc/rtl/mbox_csr_uvm.sv b/src/soc_ifc/rtl/mbox_csr_uvm.sv index d5302eb3b..c02ed521e 100644 --- a/src/soc_ifc/rtl/mbox_csr_uvm.sv +++ b/src/soc_ifc/rtl/mbox_csr_uvm.sv @@ -225,7 +225,7 @@ package mbox_csr_uvm; mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg ecc_double_error_bit_cg[1]; mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg mbox_fsm_ps_bit_cg[3]; mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg soc_has_lock_bit_cg[1]; - mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg mbox_rdptr_bit_cg[15]; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg mbox_rdptr_bit_cg[16]; mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_fld_cg fld_cg; rand uvm_reg_field status; rand uvm_reg_field ecc_single_error; @@ -255,7 +255,7 @@ package mbox_csr_uvm; this.soc_has_lock = new("soc_has_lock"); this.soc_has_lock.configure(this, 1, 9, "RO", 1, 'h0, 1, 1, 0); this.mbox_rdptr = new("mbox_rdptr"); - this.mbox_rdptr.configure(this, 15, 10, "RO", 1, 'h0, 1, 1, 0); + this.mbox_rdptr.configure(this, 16, 10, "RO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin foreach(status_bit_cg[bt]) status_bit_cg[bt] = new(); foreach(ecc_single_error_bit_cg[bt]) ecc_single_error_bit_cg[bt] = new(); diff --git a/src/soc_ifc/rtl/mbox_pkg.sv b/src/soc_ifc/rtl/mbox_pkg.sv new file mode 100644 index 000000000..4f239045c --- /dev/null +++ b/src/soc_ifc/rtl/mbox_pkg.sv @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package mbox_pkg; + + //MAILBOX FSM + typedef enum logic [2:0] { + MBOX_IDLE = 3'b000, + MBOX_RDY_FOR_CMD = 3'b001, + MBOX_RDY_FOR_DLEN = 3'b011, + MBOX_RDY_FOR_DATA = 3'b010, + MBOX_EXECUTE_UC = 3'b110, + MBOX_EXECUTE_SOC = 3'b100, + MBOX_EXECUTE_TAP = 3'b101, + MBOX_ERROR = 3'b111 + } mbox_fsm_state_e; + + //MAILBOX Status + typedef enum logic [3:0] { + CMD_BUSY = 4'd0, + DATA_READY = 4'd1, + CMD_COMPLETE = 4'd2, + CMD_FAILURE = 4'd3 + } mbox_status_e; + + typedef struct packed { + logic axs_without_lock; + logic axs_incorrect_order; + } mbox_protocol_error_t; + + typedef struct packed { + logic [31:0] MBOX_DLEN; + logic [31:0] MBOX_DOUT; + logic [31:0] MBOX_STATUS; + } mbox_dmi_reg_t; + +endpackage \ No newline at end of file diff --git a/src/soc_ifc/rtl/sha512_acc_top.sv b/src/soc_ifc/rtl/sha512_acc_top.sv index f0856952f..444e28f4a 100644 --- a/src/soc_ifc/rtl/sha512_acc_top.sv +++ b/src/soc_ifc/rtl/sha512_acc_top.sv @@ -14,6 +14,7 @@ module sha512_acc_top import soc_ifc_pkg::*; + import mbox_pkg::*; import sha512_acc_csr_pkg::*; import sha512_params_pkg::*; #( @@ -33,8 +34,8 @@ module sha512_acc_top // Direct access to mailbox output logic sha_sram_req_dv, - output logic [MBOX_ADDR_W-1:0] sha_sram_req_addr, - input mbox_sram_resp_t sha_sram_resp, + output logic [CPTRA_MBOX_ADDR_W-1:0] sha_sram_req_addr, + input cptra_mbox_sram_resp_t sha_sram_resp, input logic sha_sram_hold, // Interrupts @@ -68,8 +69,8 @@ module sha512_acc_top logic extra_pad_block_required; //extra bit for roll over on full read - logic [MBOX_ADDR_W:0] mbox_rdptr; - logic [MBOX_ADDR_W-1:0] mbox_start_addr, mbox_end_addr; + logic [CPTRA_MBOX_ADDR_W:0] mbox_rdptr; + logic [CPTRA_MBOX_ADDR_W-1:0] mbox_start_addr, mbox_end_addr; logic mbox_read_to_end; logic mbox_read_en; logic mbox_read_done; @@ -205,7 +206,7 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); always_comb mbox_read_en = mailbox_mode & ~mbox_read_done & !sha_sram_hold & ~(mbox_mode_last_dword_wr | block_full); always_comb sha_sram_req_dv = mbox_read_en; - always_comb sha_sram_req_addr = mbox_rdptr[MBOX_ADDR_W-1:0]; + always_comb sha_sram_req_addr = mbox_rdptr[CPTRA_MBOX_ADDR_W-1:0]; //stall the write if we are trying to stream datain and it's the end of a block but the core isn't ready always_comb stall_write = datain_write & block_full; @@ -303,19 +304,19 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); end //byte address aligning to mailbox read pointer - always_comb mbox_start_addr = hwif_out.START_ADDRESS.ADDR.value[MBOX_ADDR_W+1:2]; + always_comb mbox_start_addr = hwif_out.START_ADDRESS.ADDR.value[CPTRA_MBOX_ADDR_W+1:2]; //Convert DLEN to an end address. DLEN is in bytes, address is in dwords //detect overflow of end address to indicate we want to read to the end of the mailbox always_comb {mbox_read_to_end, mbox_end_addr} = mbox_start_addr + - hwif_out.DLEN.LENGTH.value[MBOX_ADDR_W+2:2] + + hwif_out.DLEN.LENGTH.value[CPTRA_MBOX_ADDR_W+2:2] + (hwif_out.DLEN.LENGTH.value[1] | hwif_out.DLEN.LENGTH.value[0]); always_comb mbox_read_done = (sha_fsm_ps == SHA_IDLE) | ~mailbox_mode | //If the DLEN overflowed our end address, just read to the end of the mailbox and stop //Otherwise read until read pointer == end address - (~mbox_read_to_end & mbox_rdptr[MBOX_ADDR_W-1:0] == mbox_end_addr) | - (mbox_read_to_end & mbox_rdptr[MBOX_ADDR_W]); + (~mbox_read_to_end & mbox_rdptr[CPTRA_MBOX_ADDR_W-1:0] == mbox_end_addr) | + (mbox_read_to_end & mbox_rdptr[CPTRA_MBOX_ADDR_W]); //HW API State Machine //whenever lock is cleared, go back to idle diff --git a/src/soc_ifc/rtl/soc_ifc_arb.sv b/src/soc_ifc/rtl/soc_ifc_arb.sv index 7451ca887..44e78d9fe 100644 --- a/src/soc_ifc/rtl/soc_ifc_arb.sv +++ b/src/soc_ifc/rtl/soc_ifc_arb.sv @@ -221,16 +221,16 @@ always_comb dma_reg_req_data = ({$bits(soc_ifc_req_t){soc_dma_gnt}} & soc_req_da //drive the appropriate read data back to uc or soc //AND/OR mux here, assert that requests are always mutex -always_comb uc_rdata = ({MBOX_DATA_W{uc_mbox_reg_req}} & mbox_rdata) | - ({MBOX_DATA_W{uc_mbox_dir_req}} & mbox_dir_rdata) | - ({MBOX_DATA_W{uc_reg_req}} & soc_ifc_reg_rdata) | - ({MBOX_DATA_W{uc_sha_req}} & sha_rdata) | - ({MBOX_DATA_W{uc_dma_req}} & dma_reg_rdata); - -always_comb soc_rdata = ({MBOX_DATA_W{soc_mbox_req}} & mbox_rdata) | - ({MBOX_DATA_W{soc_reg_req}} & soc_ifc_reg_rdata) | - ({MBOX_DATA_W{soc_sha_req}} & sha_rdata) | - ({MBOX_DATA_W{soc_dma_req}} & dma_reg_rdata); +always_comb uc_rdata = ({SOC_IFC_DATA_W{uc_mbox_reg_req}} & mbox_rdata) | + ({SOC_IFC_DATA_W{uc_mbox_dir_req}} & mbox_dir_rdata) | + ({SOC_IFC_DATA_W{uc_reg_req}} & soc_ifc_reg_rdata) | + ({SOC_IFC_DATA_W{uc_sha_req}} & sha_rdata) | + ({SOC_IFC_DATA_W{uc_dma_req}} & dma_reg_rdata); + +always_comb soc_rdata = ({SOC_IFC_DATA_W{soc_mbox_req}} & mbox_rdata) | + ({SOC_IFC_DATA_W{soc_reg_req}} & soc_ifc_reg_rdata) | + ({SOC_IFC_DATA_W{soc_sha_req}} & sha_rdata) | + ({SOC_IFC_DATA_W{soc_dma_req}} & dma_reg_rdata); //drive the appropraite holds back to uc or soc //AND/OR mux here, assert that requests are always mutex diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv index b60dc0781..0f9c25e77 100644 --- a/src/soc_ifc/rtl/soc_ifc_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv @@ -20,19 +20,10 @@ package soc_ifc_pkg; - parameter SOC_IFC_ADDR_W = 18; + parameter SOC_IFC_ADDR_W = 19; parameter SOC_IFC_DATA_W = 32; parameter SOC_IFC_USER_W = 32; parameter SOC_IFC_ID_W = `CALIPTRA_AXI_ID_WIDTH; - - parameter MBOX_SIZE_KB = 128; - parameter MBOX_SIZE_BYTES = MBOX_SIZE_KB * 1024; - parameter MBOX_SIZE_DWORDS = MBOX_SIZE_BYTES/4; - parameter MBOX_DATA_W = 32; - parameter MBOX_ECC_DATA_W = 7; - parameter MBOX_DATA_AND_ECC_W = MBOX_DATA_W + MBOX_ECC_DATA_W; - parameter MBOX_DEPTH = (MBOX_SIZE_KB * 1024 * 8) / MBOX_DATA_W; - parameter MBOX_ADDR_W = $clog2(MBOX_DEPTH); parameter CPTRA_AXI_DMA_DATA_WIDTH = 32; parameter CPTRA_AXI_DMA_ID_WIDTH = 5; // FIXME related to CALIPTRA_AXI_ID_WIDTH? @@ -44,8 +35,6 @@ package soc_ifc_pkg; parameter SOC_IFC_REG_OFFSET = 32'h3000_0000; //memory map - parameter MBOX_DIR_START_ADDR = 32'h0000_0000; - parameter MBOX_DIR_END_ADDR = 32'h0001_FFFF; parameter MBOX_REG_START_ADDR = `CLP_MBOX_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET; parameter MBOX_REG_END_ADDR = MBOX_REG_START_ADDR + 32'h0000_0FFF; parameter SHA_REG_START_ADDR = `CLP_SHA512_ACC_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET; @@ -56,6 +45,20 @@ package soc_ifc_pkg; parameter SOC_IFC_REG_END_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_FFFF; parameter SOC_IFC_FUSE_START_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_0200; parameter SOC_IFC_FUSE_END_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_05FF; + parameter MBOX_DIR_START_ADDR = `CLP_MBOX_SRAM_BASE_ADDR - SOC_IFC_REG_OFFSET; + parameter MBOX_DIR_END_ADDR = `CLP_MBOX_SRAM_END_ADDR - SOC_IFC_REG_OFFSET; + parameter MBOX_DIR_MEM_SIZE = MBOX_DIR_END_ADDR - MBOX_DIR_START_ADDR; + + //Mailbox size configuration + parameter CPTRA_MBOX_SIZE_KB = 256; + parameter CPTRA_MBOX_DATA_W = 32; + parameter CPTRA_MBOX_ECC_DATA_W = 7; + parameter CPTRA_MBOX_SIZE_BYTES = CPTRA_MBOX_SIZE_KB * 1024; + parameter CPTRA_MBOX_SIZE_DWORDS = CPTRA_MBOX_SIZE_BYTES/4; + parameter CPTRA_MBOX_DATA_AND_ECC_W = CPTRA_MBOX_DATA_W + CPTRA_MBOX_ECC_DATA_W; + parameter CPTRA_MBOX_DEPTH = (CPTRA_MBOX_SIZE_KB * 1024 * 8) / CPTRA_MBOX_DATA_W; + parameter CPTRA_MBOX_ADDR_W = $clog2(CPTRA_MBOX_DEPTH); + parameter CPTRA_MBOX_DEPTH_LOG2 = $clog2(CPTRA_MBOX_DEPTH); //Valid AXI_USER //Lock the AXI_USER values from integration time @@ -120,18 +123,6 @@ package soc_ifc_pkg; BOOT_DONE = 3'b100 } boot_fsm_state_e; - //MAILBOX FSM - typedef enum logic [2:0] { - MBOX_IDLE = 3'b000, - MBOX_RDY_FOR_CMD = 3'b001, - MBOX_RDY_FOR_DLEN = 3'b011, - MBOX_RDY_FOR_DATA = 3'b010, - MBOX_EXECUTE_UC = 3'b110, - MBOX_EXECUTE_SOC = 3'b100, - MBOX_EXECUTE_TAP = 3'b101, - MBOX_ERROR = 3'b111 - } mbox_fsm_state_e; - //SHA FSM typedef enum logic [2:0] { SHA_IDLE = 3'b000, @@ -142,14 +133,6 @@ package soc_ifc_pkg; SHA_DONE = 3'b100 } sha_fsm_state_e; - //MAILBOX Status - typedef enum logic [3:0] { - CMD_BUSY = 4'd0, - DATA_READY = 4'd1, - CMD_COMPLETE = 4'd2, - CMD_FAILURE = 4'd3 - } mbox_status_e; - //Any request into soc ifc block typedef struct packed { logic [SOC_IFC_ADDR_W-1:0] addr; @@ -160,22 +143,6 @@ package soc_ifc_pkg; logic write; logic soc_req; } soc_ifc_req_t; - // ECC protected data - typedef struct packed { - logic [MBOX_ECC_DATA_W-1:0] ecc; - logic [MBOX_DATA_W-1:0] data; - } mbox_sram_data_t; - //Request to mbox sram - typedef struct packed { - logic cs; - logic we; - logic [MBOX_ADDR_W-1:0] addr; - mbox_sram_data_t wdata; - } mbox_sram_req_t; - //Response from mbox sram - typedef struct packed { - mbox_sram_data_t rdata; - } mbox_sram_resp_t; typedef struct packed { logic cptra_iccm_ecc_single_error; @@ -184,11 +151,6 @@ package soc_ifc_pkg; logic cptra_dccm_ecc_double_error; } rv_ecc_sts_t; - typedef struct packed { - logic axs_without_lock; - logic axs_incorrect_order; - } mbox_protocol_error_t; - typedef enum logic [1:0] { DEVICE_UNPROVISIONED = 2'b00, DEVICE_MANUFACTURING = 2'b01, @@ -200,11 +162,25 @@ package soc_ifc_pkg; device_lifecycle_e device_lifecycle; } security_state_t; + //Caliptra Mailbox + // ECC protected data + typedef struct packed { + logic [CPTRA_MBOX_ECC_DATA_W-1:0] ecc; + logic [CPTRA_MBOX_DATA_W-1:0] data; + } cptra_mbox_sram_data_t; + + //Request to mbox sram + typedef struct packed { + logic cs; + logic we; + logic [CPTRA_MBOX_ADDR_W-1:0] addr; + cptra_mbox_sram_data_t wdata; + } cptra_mbox_sram_req_t; + + //Response from mbox sram typedef struct packed { - logic [31:0] MBOX_DLEN; - logic [31:0] MBOX_DOUT; - logic [31:0] MBOX_STATUS; - } mbox_dmi_reg_t; + cptra_mbox_sram_data_t rdata; + } cptra_mbox_sram_resp_t; endpackage diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 52e5a159e..06d7c8f86 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -18,6 +18,7 @@ module soc_ifc_top import soc_ifc_pkg::*; + import mbox_pkg::*; import soc_ifc_reg_pkg::*; #( parameter AXI_ADDR_WIDTH = 18 @@ -93,8 +94,8 @@ module soc_ifc_top output wire timer_intr, //SRAM interface - output mbox_sram_req_t mbox_sram_req, - input mbox_sram_resp_t mbox_sram_resp, + output cptra_mbox_sram_req_t mbox_sram_req, + input cptra_mbox_sram_resp_t mbox_sram_resp, // RV ECC Status Interface input rv_ecc_sts_t rv_ecc_sts, @@ -200,8 +201,8 @@ logic soc_ifc_reg_error, soc_ifc_reg_read_error, soc_ifc_reg_write_error; logic soc_ifc_reg_rdata_mask; logic sha_sram_req_dv; -logic [MBOX_ADDR_W-1:0] sha_sram_req_addr; -mbox_sram_resp_t sha_sram_resp; +logic [CPTRA_MBOX_ADDR_W-1:0] sha_sram_req_addr; +cptra_mbox_sram_resp_t sha_sram_resp; logic sha_sram_hold; //DMA SRAM direct inf @@ -1060,35 +1061,52 @@ i_sha512_acc_top ( .notif_intr(sha_notif_intr) ); - //Mailbox //This module contains the Caliptra Mailbox and associated control logic //The SoC and uC can read and write to the mailbox by following the Caliptra Mailbox Protocol -mbox #( - .DATA_W(SOC_IFC_DATA_W), - .SIZE_KB(MBOX_SIZE_KB) - ) +mbox +#( + .DMI_REG_MBOX_DLEN_ADDR(soc_ifc_pkg::DMI_REG_MBOX_DLEN), + .MBOX_SIZE_KB(CPTRA_MBOX_SIZE_KB), + .MBOX_DATA_W(CPTRA_MBOX_DATA_W), + .MBOX_ECC_DATA_W(CPTRA_MBOX_ECC_DATA_W), + .MBOX_IFC_DATA_W(SOC_IFC_DATA_W), + .MBOX_IFC_USER_W(SOC_IFC_USER_W), + .MBOX_IFC_ADDR_W(SOC_IFC_ADDR_W) +) i_mbox ( .clk(soc_ifc_clk_cg), .rst_b(cptra_noncore_rst_b), .req_dv(mbox_req_dv), .req_hold(mbox_req_hold), .dir_req_dv(mbox_dir_req_dv), - .req_data(mbox_req_data), + .req_data_addr(mbox_req_data.addr), + .req_data_wdata(mbox_req_data.wdata), + .req_data_user(mbox_req_data.user), + .req_data_write(mbox_req_data.write), + .req_data_soc_req(mbox_req_data.soc_req), .mbox_error(mbox_error), .rdata(mbox_rdata), .dir_rdata(mbox_dir_rdata), .sha_sram_req_dv(sha_sram_req_dv), .sha_sram_req_addr(sha_sram_req_addr), - .sha_sram_resp(sha_sram_resp), + .sha_sram_resp_ecc(sha_sram_resp.rdata.ecc), + .sha_sram_resp_data(sha_sram_resp.rdata.data), .sha_sram_hold(sha_sram_hold), .dma_sram_req_dv (dma_sram_req_dv ), - .dma_sram_req_data(dma_sram_req_data), + .dma_sram_req_write(dma_sram_req_data.write), + .dma_sram_req_addr(dma_sram_req_data.addr), + .dma_sram_req_wdata(dma_sram_req_data.wdata), .dma_sram_rdata (dma_sram_rdata ), .dma_sram_hold (dma_sram_req_hold), .dma_sram_error (dma_sram_error ), - .mbox_sram_req(mbox_sram_req), - .mbox_sram_resp(mbox_sram_resp), + .mbox_sram_req_cs(mbox_sram_req.cs), + .mbox_sram_req_we(mbox_sram_req.we), + .mbox_sram_req_addr(mbox_sram_req.addr), + .mbox_sram_req_ecc(mbox_sram_req.wdata.ecc), + .mbox_sram_req_wdata(mbox_sram_req.wdata.data), + .mbox_sram_resp_ecc(mbox_sram_resp.rdata.ecc), + .mbox_sram_resp_data(mbox_sram_resp.rdata.data), .sram_single_ecc_error(sram_single_ecc_error), .sram_double_ecc_error(sram_double_ecc_error), .uc_mbox_lock(uc_mbox_lock), diff --git a/src/soc_ifc/tb/soc_ifc_tb.sv b/src/soc_ifc/tb/soc_ifc_tb.sv index 083658656..cc556c85f 100644 --- a/src/soc_ifc/tb/soc_ifc_tb.sv +++ b/src/soc_ifc/tb/soc_ifc_tb.sv @@ -37,6 +37,7 @@ import "DPI-C" function string getenv(input string env_name); module soc_ifc_tb import soc_ifc_pkg::*; + import mbox_pkg::*; import soc_ifc_tb_pkg::*; (); @@ -148,9 +149,9 @@ module soc_ifc_tb //SRAM interface for mbox logic mbox_sram_cs; logic mbox_sram_we; - logic [MBOX_ADDR_W-1:0] mbox_sram_addr; - logic [MBOX_DATA_W-1:0] mbox_sram_wdata; - logic [MBOX_DATA_W-1:0] mbox_sram_rdata; + logic [CPTRA_MBOX_ADDR_W-1:0] mbox_sram_addr; + logic [CPTRA_MBOX_DATA_W-1:0] mbox_sram_wdata; + logic [CPTRA_MBOX_DATA_W-1:0] mbox_sram_rdata; logic [0:11][31:0] cptra_uds_tb; logic [0:31][31:0] cptra_fe_tb; diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf index b890c40e4..ee670ddd5 100644 --- a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc.vf @@ -92,6 +92,7 @@ ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_sla ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv diff --git a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf index bd6e59922..330582a9f 100644 --- a/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf +++ b/src/soc_ifc/uvmf_soc_ifc/config/uvmf_soc_ifc_vip.vf @@ -87,6 +87,7 @@ ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/config_policies/qvip_apb5_sla ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/qvip_apb5_slave_pkg.sv ${CALIPTRA_ROOT}/src/libs/uvmf/qvip_apb5_slave_dir/uvmf/hdl_qvip_apb5_slave.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv +${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv index add769657..83440a910 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv @@ -884,7 +884,7 @@ package soc_ifc_reg_model_top_pkg; // inst all soc_ifc register blocks and memory model as single reg block /*mbox_mem_ahb_apb*/ - this.mbox_mem_rm = new("mbox_mem_rm", 18'h8000, 32, "RW", UVM_NO_COVERAGE); + this.mbox_mem_rm = new("mbox_mem_rm", 19'h1_0000, 32, "RW", UVM_NO_COVERAGE); this.mbox_mem_rm.configure(this); /*mbox_csr_ahb_apb*/ @@ -1125,13 +1125,13 @@ package soc_ifc_reg_model_top_pkg; this.soc_ifc_reg_rm.build_ext_maps(); /* Top register model APB map */ - this.soc_ifc_APB_map.add_mem(this.mbox_mem_rm, 0, "RW"); + this.soc_ifc_APB_map.add_mem(this.mbox_mem_rm, 'h4_0000, "RW"); this.soc_ifc_APB_map.add_submap(this.mbox_csr_rm.mbox_csr_APB_map, 'h2_0000); this.soc_ifc_APB_map.add_submap(this.sha512_acc_csr_rm.sha512_acc_csr_APB_map, 'h2_1000); this.soc_ifc_APB_map.add_submap(this.soc_ifc_reg_rm.soc_ifc_reg_APB_map, 'h3_0000); /* Top register model AHB map */ - this.soc_ifc_AHB_map.add_mem(this.mbox_mem_rm, 0, "RW"); + this.soc_ifc_AHB_map.add_mem(this.mbox_mem_rm, 'h4_0000, "RW"); this.soc_ifc_AHB_map.add_submap(this.mbox_csr_rm.mbox_csr_AHB_map, 'h2_0000); this.soc_ifc_AHB_map.add_submap(this.sha512_acc_csr_rm.sha512_acc_csr_AHB_map, 'h2_1000); this.soc_ifc_AHB_map.add_submap(this.soc_ifc_reg_rm.soc_ifc_reg_AHB_map, 'h3_0000); diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile index 826bed246..67f407550 100644 --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -275,18 +275,18 @@ else ifneq (,$(wildcard $(TEST_DIR)/$(TESTNAME))) # Build program.hex from RUST executable program.hex: @echo "Building program.hex from $(TESTNAME) using Crypto Test rules for pre-compiled RUST executables" - -$(GCC_PREFIX)-objcopy -O verilog -R .data -R .rodata -R .bss -R .sbss -R .iccm -R .dccm -R .eh_frame --pad-to 0xC000 --gap-fill 0xFF --no-change-warnings $(TEST_DIR)/$(TESTNAME) program.hex + -$(GCC_PREFIX)-objcopy -O verilog -R .data -R .rodata -R .bss -R .sbss -R .iccm -R .dccm -R .eh_frame --pad-to 0x18000 --gap-fill 0xFF --no-change-warnings $(TEST_DIR)/$(TESTNAME) program.hex -$(GCC_PREFIX)-objcopy -O verilog -j .data -j .rodata -j .bss -j .sbss -j .dccm \ --change-section-lma .data-0x50000000 \ --change-section-lma .rodata-0x50000000 \ --change-section-lma .bss-0x50000000 \ --change-section-lma .sbss-0x50000000 \ --change-section-lma .dccm-0x50000000 \ - --pad-to 0x20000 \ + --pad-to 0x40000 \ --no-change-warnings \ $(TEST_DIR)/$(TESTNAME) dccm.hex - -$(GCC_PREFIX)-objcopy -O verilog -j .iccm --change-section-address .iccm=0 --pad-to 0x20000 --no-change-warnings $(TEST_DIR)/$(TESTNAME) iccm.hex - -$(GCC_PREFIX)-objcopy -O verilog -j .mailbox --gap-fill 0x0 --change-section-address .mailbox=0 --pad-to 0x20000 --no-change-warnings $(TEST_DIR)/$(TESTNAME) mailbox.hex + -$(GCC_PREFIX)-objcopy -O verilog -j .iccm --change-section-address .iccm=0 --pad-to 0x40000 --no-change-warnings $(TEST_DIR)/$(TESTNAME) iccm.hex + -$(GCC_PREFIX)-objcopy -O verilog -j .mailbox --gap-fill 0x0 --change-section-address .mailbox=0 --pad-to 0x40000 --no-change-warnings $(TEST_DIR)/$(TESTNAME) mailbox.hex $(GCC_PREFIX)-objdump -S $(TEST_DIR)/$(TESTNAME) > $(TESTNAME).dis $(GCC_PREFIX)-size $(TEST_DIR)/$(TESTNAME) | tee $(TESTNAME).size @@ -295,17 +295,17 @@ else program.hex: $(OFILE_CRT) $(OFILES) $(LINK) @echo Building $(TESTNAME) $(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(TESTNAME).map -lgcc -T$(LINK) -o $(TESTNAME).exe $(OFILE_CRT) $(OFILES) -nostartfiles $(TEST_LIBS) - -$(GCC_PREFIX)-objcopy -O verilog -R .data_iccm0 -R .data_iccm1 -R .data_iccm2 -R .iccm -R .dccm -R .eh_frame --pad-to 0xC000 --no-change-warnings $(TESTNAME).exe program.hex + -$(GCC_PREFIX)-objcopy -O verilog -R .data_iccm0 -R .data_iccm1 -R .data_iccm2 -R .iccm -R .dccm -R .eh_frame --pad-to 0x18000 --no-change-warnings $(TESTNAME).exe program.hex -$(GCC_PREFIX)-objcopy -O verilog -j .data_iccm0 -j .data_iccm1 -j .data_iccm2 -j .dccm \ --change-section-lma .data_iccm0-0x50000000 \ --change-section-lma .data_iccm1-0x50000000 \ --change-section-lma .data_iccm2-0x50000000 \ --change-section-lma .dccm-0x50000000 \ - --pad-to 0x20000 \ + --pad-to 0x40000 \ --no-change-warnings \ $(TESTNAME).exe dccm.hex - -$(GCC_PREFIX)-objcopy -O verilog -j .iccm --change-section-address .iccm=0 --pad-to 0x20000 --no-change-warnings $(TESTNAME).exe iccm.hex - -$(GCC_PREFIX)-objcopy -O verilog -j .mailbox --gap-fill 0x0 --change-section-address .mailbox=0 --pad-to 0x20000 --no-change-warnings $(TESTNAME).exe mailbox.hex + -$(GCC_PREFIX)-objcopy -O verilog -j .iccm --change-section-address .iccm=0 --pad-to 0x40000 --no-change-warnings $(TESTNAME).exe iccm.hex + -$(GCC_PREFIX)-objcopy -O verilog -j .mailbox --gap-fill 0x0 --change-section-address .mailbox=0 --pad-to 0x40000 --no-change-warnings $(TESTNAME).exe mailbox.hex $(GCC_PREFIX)-objdump -S $(TESTNAME).exe > $(TESTNAME).dis $(GCC_PREFIX)-size $(TESTNAME).exe | tee $(TESTNAME).size @echo Completed building $(TESTNAME) @@ -315,7 +315,7 @@ program.hex: $(OFILE_CRT) $(OFILES) $(LINK) %.hex: $(OFILES) $(LINK) @echo Building $(TESTNAME) $(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(TESTNAME).map -lgcc -T$(LINK) -o $(TESTNAME).exe $(OFILES) -nostartfiles $(TEST_LIBS) - -$(GCC_PREFIX)-objcopy -O verilog -R .eh_frame --pad-to 0x20000 --no-change-warnings $(TESTNAME).exe $@ + -$(GCC_PREFIX)-objcopy -O verilog -R .eh_frame --pad-to 0x40000 --no-change-warnings $(TESTNAME).exe $@ $(GCC_PREFIX)-objdump -S $(TESTNAME).exe > $(TESTNAME).dis $(GCC_PREFIX)-size $(TESTNAME).exe | tee $(TESTNAME).size @echo Completed building $(TESTNAME)