diff --git a/src/Design/ModuleInstance.cpp b/src/Design/ModuleInstance.cpp index 4b12ae9b24..25f9c7790c 100644 --- a/src/Design/ModuleInstance.cpp +++ b/src/Design/ModuleInstance.cpp @@ -304,14 +304,25 @@ void ModuleInstance::overrideParentChild(ModuleInstance* parent, Netlist* netlist = interm->getNetlist(); if (netlist) { if (netlist->cont_assigns() || netlist->process_stmts() || - netlist->array_nets() || netlist->array_vars() || - netlist->param_assigns() || netlist->nets() || netlist->variables() || + netlist->array_nets() || netlist->param_assigns() || + netlist->array_vars() || netlist->nets() || netlist->variables() || netlist->interface_arrays() || netlist->interfaces()) return; } - // Loop indexes Netlist* child_netlist = child->getNetlist(); + if (netlist->param_assigns()) { + auto params = child_netlist->param_assigns(); + if (params == nullptr) { + params = s.MakeParam_assignVec(); + } + child_netlist->param_assigns(params); + for (auto p : *netlist->param_assigns()) { + params->push_back(p); + } + } + + // Loop indexes for (auto& param : interm->getMappedValues()) { const std::string_view name = param.first; Value* val = param.second.first; diff --git a/src/DesignCompile/DesignElaboration.cpp b/src/DesignCompile/DesignElaboration.cpp index 194fe2701e..16a06eac48 100644 --- a/src/DesignCompile/DesignElaboration.cpp +++ b/src/DesignCompile/DesignElaboration.cpp @@ -2512,6 +2512,7 @@ void DesignElaboration::reduceUnnamedBlocks_() { typeP == VObjectType::paLoop_generate_construct || typeP == VObjectType::paGenerate_module_loop_statement || typeP == VObjectType::paGenerate_interface_loop_statement || + typeP == VObjectType::paGenerate_begin_end_block || typeP == VObjectType::paGenerate_region || typeP == VObjectType::paGenerate_item)) { std::string_view fullModName = @@ -2522,16 +2523,22 @@ void DesignElaboration::reduceUnnamedBlocks_() { parent->getParent()->overrideParentChild(parent->getParent(), parent, current, s); } else if (fullModName.find("genblk") != std::string::npos) { - if (fullModName == fullModNameP) - parent->getParent()->overrideParentChild(parent->getParent(), - parent, current, s); + if (fullModName == fullModNameP) { + if (fullModNameP.find("[") == std::string::npos) { + parent->getParent()->overrideParentChild(parent->getParent(), + parent, current, s); + } + } } else { if (type == VObjectType::paGenerate_item && typeP == VObjectType::paGenerate_item) { } else { - if (fullModNameP.find("genblk") != std::string::npos) - parent->getParent()->overrideParentChild(parent->getParent(), - parent, current, s); + if (fullModNameP.find("genblk") != std::string::npos) { + if (fullModNameP.find("[") == std::string::npos) { + parent->getParent()->overrideParentChild(parent->getParent(), + parent, current, s); + } + } } } } diff --git a/tests/DoubleLoop/DoubleLoop.log b/tests/DoubleLoop/DoubleLoop.log index a15c6db9c3..60b47e7216 100644 --- a/tests/DoubleLoop/DoubleLoop.log +++ b/tests/DoubleLoop/DoubleLoop.log @@ -4,23 +4,23 @@ AST_DEBUG_BEGIN LIB: work FILE: ${SURELOG_DIR}/tests/DoubleLoop/dut.sv n<> u<0> t<_INVALID_> f<0> l<0:0> -n<> u<1> t p<144> s<143> l<2:1> el<1:2> +n<> u<1> t p<704> s<703> l<2:1> el<1:2> n u<2> t p<17> s<3> l<2:1> el<2:7> -n u<3> t p<17> s<16> l<2:8> el<2:18> -n u<4> t p<7> s<6> l<2:19> el<2:21> -n<> u<5> t p<6> l<2:21> el<2:21> -n<> u<6> t p<7> c<5> l<2:21> el<2:21> -n<> u<7> t p<8> c<4> l<2:19> el<2:21> -n<> u<8> t p<9> c<7> l<2:19> el<2:21> -n<> u<9> t p<16> c<8> s<15> l<2:19> el<2:21> -n u<10> t p<13> s<12> l<2:23> el<2:25> -n<> u<11> t p<12> l<2:25> el<2:25> -n<> u<12> t p<13> c<11> l<2:25> el<2:25> -n<> u<13> t p<14> c<10> l<2:23> el<2:25> -n<> u<14> t p<15> c<13> l<2:23> el<2:25> -n<> u<15> t p<16> c<14> l<2:23> el<2:25> -n<> u<16> t p<17> c<9> l<2:18> el<2:26> -n<> u<17> t p<141> c<2> s<35> l<2:1> el<2:27> +n u<3> t p<17> s<16> l<2:8> el<2:19> +n u<4> t p<7> s<6> l<2:20> el<2:22> +n<> u<5> t p<6> l<2:22> el<2:22> +n<> u<6> t p<7> c<5> l<2:22> el<2:22> +n<> u<7> t p<8> c<4> l<2:20> el<2:22> +n<> u<8> t p<9> c<7> l<2:20> el<2:22> +n<> u<9> t p<16> c<8> s<15> l<2:20> el<2:22> +n u<10> t p<13> s<12> l<2:24> el<2:26> +n<> u<11> t p<12> l<2:26> el<2:26> +n<> u<12> t p<13> c<11> l<2:26> el<2:26> +n<> u<13> t p<14> c<10> l<2:24> el<2:26> +n<> u<14> t p<15> c<13> l<2:24> el<2:26> +n<> u<15> t p<16> c<14> l<2:24> el<2:26> +n<> u<16> t p<17> c<9> l<2:19> el<2:27> +n<> u<17> t p<141> c<2> s<35> l<2:1> el<2:28> n<2> u<18> t p<19> l<4:9> el<4:10> n<> u<19> t p<20> c<18> l<4:9> el<4:10> n<> u<20> t p<21> c<19> l<4:9> el<4:10> @@ -145,84 +145,728 @@ n<> u<138> t p<139> c<137> l<8:1> el<15:12> n<> u<139> t p<141> c<138> s<140> l<8:1> el<15:12> n<> u<140> t p<141> l<17:1> el<17:10> n<> u<141> t p<142> c<17> l<2:1> el<17:10> -n<> u<142> t p<143> c<141> l<2:1> el<17:10> -n<> u<143> t p<144> c<142> l<2:1> el<17:10> -n<> u<144> t c<1> l<2:1> el<60:3> +n<> u<142> t p<703> c<141> s<282> l<2:1> el<17:10> +n u<143> t p<158> s<144> l<19:1> el<19:7> +n u<144> t p<158> s<157> l<19:8> el<19:19> +n u<145> t p<148> s<147> l<19:20> el<19:22> +n<> u<146> t p<147> l<19:22> el<19:22> +n<> u<147> t p<148> c<146> l<19:22> el<19:22> +n<> u<148> t p<149> c<145> l<19:20> el<19:22> +n<> u<149> t p<150> c<148> l<19:20> el<19:22> +n<> u<150> t p<157> c<149> s<156> l<19:20> el<19:22> +n u<151> t p<154> s<153> l<19:24> el<19:26> +n<> u<152> t p<153> l<19:26> el<19:26> +n<> u<153> t p<154> c<152> l<19:26> el<19:26> +n<> u<154> t p<155> c<151> l<19:24> el<19:26> +n<> u<155> t p<156> c<154> l<19:24> el<19:26> +n<> u<156> t p<157> c<155> l<19:24> el<19:26> +n<> u<157> t p<158> c<150> l<19:19> el<19:27> +n<> u<158> t p<281> c<143> s<176> l<19:1> el<19:28> +n<2> u<159> t p<160> l<21:9> el<21:10> +n<> u<160> t p<161> c<159> l<21:9> el<21:10> +n<> u<161> t p<162> c<160> l<21:9> el<21:10> +n<> u<162> t p<167> c<161> s<166> l<21:9> el<21:10> +n<0> u<163> t p<164> l<21:11> el<21:12> +n<> u<164> t p<165> c<163> l<21:11> el<21:12> +n<> u<165> t p<166> c<164> l<21:11> el<21:12> +n<> u<166> t p<167> c<165> l<21:11> el<21:12> +n<> u<167> t p<168> c<162> l<21:9> el<21:12> +n<> u<168> t p<169> c<167> l<21:8> el<21:13> +n<> u<169> t p<170> c<168> l<21:8> el<21:13> +n<> u<170> t p<174> c<169> s<173> l<21:8> el<21:13> +n u<171> t p<173> s<172> l<21:14> el<21:16> +n u<172> t p<173> l<21:18> el<21:20> +n<> u<173> t p<174> c<171> l<21:14> el<21:20> +n<> u<174> t p<175> c<170> l<21:1> el<21:20> +n<> u<175> t p<176> c<174> l<21:1> el<21:20> +n<> u<176> t p<281> c<175> s<185> l<21:1> el<21:21> +n u<177> t p<179> s<178> l<23:8> el<23:9> +n u<178> t p<179> l<23:11> el<23:12> +n<> u<179> t p<180> c<177> l<23:8> el<23:12> +n<> u<180> t p<181> c<179> l<23:1> el<23:13> +n<> u<181> t p<182> c<180> l<23:1> el<23:13> +n<> u<182> t p<183> c<181> l<23:1> el<23:13> +n<> u<183> t p<184> c<182> l<23:1> el<23:13> +n<> u<184> t p<185> c<183> l<23:1> el<23:13> +n<> u<185> t p<281> c<184> s<279> l<23:1> el<23:13> +n u<186> t p<191> s<190> l<26:7> el<26:8> +n<0> u<187> t p<188> l<26:11> el<26:12> +n<> u<188> t p<189> c<187> l<26:11> el<26:12> +n<> u<189> t p<190> c<188> l<26:11> el<26:12> +n<> u<190> t p<191> c<189> l<26:11> el<26:12> +n<> u<191> t p<272> c<186> s<201> l<26:7> el<26:12> +n u<192> t p<193> l<26:14> el<26:15> +n<> u<193> t p<194> c<192> l<26:14> el<26:15> +n<> u<194> t p<195> c<193> l<26:14> el<26:15> +n<> u<195> t p<201> c<194> s<200> l<26:14> el<26:15> +n<2> u<196> t p<197> l<26:18> el<26:19> +n<> u<197> t p<198> c<196> l<26:18> el<26:19> +n<> u<198> t p<199> c<197> l<26:18> el<26:19> +n<> u<199> t p<201> c<198> l<26:18> el<26:19> +n<> u<200> t p<201> s<199> l<26:16> el<26:17> +n<> u<201> t p<272> c<195> s<214> l<26:14> el<26:19> +n u<202> t p<214> s<203> l<26:21> el<26:22> +n<> u<203> t p<214> s<213> l<26:23> el<26:24> +n u<204> t p<205> l<26:25> el<26:26> +n<> u<205> t p<206> c<204> l<26:25> el<26:26> +n<> u<206> t p<207> c<205> l<26:25> el<26:26> +n<> u<207> t p<213> c<206> s<212> l<26:25> el<26:26> +n<1> u<208> t p<209> l<26:27> el<26:28> +n<> u<209> t p<210> c<208> l<26:27> el<26:28> +n<> u<210> t p<211> c<209> l<26:27> el<26:28> +n<> u<211> t p<213> c<210> l<26:27> el<26:28> +n<> u<212> t p<213> s<211> l<26:26> el<26:27> +n<> u<213> t p<214> c<207> l<26:25> el<26:28> +n<> u<214> t p<272> c<202> s<271> l<26:21> el<26:28> +n u<215> t p<220> s<219> l<27:7> el<27:8> +n<0> u<216> t p<217> l<27:11> el<27:12> +n<> u<217> t p<218> c<216> l<27:11> el<27:12> +n<> u<218> t p<219> c<217> l<27:11> el<27:12> +n<> u<219> t p<220> c<218> l<27:11> el<27:12> +n<> u<220> t p<268> c<215> s<230> l<27:7> el<27:12> +n u<221> t p<222> l<27:14> el<27:15> +n<> u<222> t p<223> c<221> l<27:14> el<27:15> +n<> u<223> t p<224> c<222> l<27:14> el<27:15> +n<> u<224> t p<230> c<223> s<229> l<27:14> el<27:15> +n<2> u<225> t p<226> l<27:18> el<27:19> +n<> u<226> t p<227> c<225> l<27:18> el<27:19> +n<> u<227> t p<228> c<226> l<27:18> el<27:19> +n<> u<228> t p<230> c<227> l<27:18> el<27:19> +n<> u<229> t p<230> s<228> l<27:16> el<27:17> +n<> u<230> t p<268> c<224> s<243> l<27:14> el<27:19> +n u<231> t p<243> s<232> l<27:21> el<27:22> +n<> u<232> t p<243> s<242> l<27:23> el<27:24> +n u<233> t p<234> l<27:25> el<27:26> +n<> u<234> t p<235> c<233> l<27:25> el<27:26> +n<> u<235> t p<236> c<234> l<27:25> el<27:26> +n<> u<236> t p<242> c<235> s<241> l<27:25> el<27:26> +n<1> u<237> t p<238> l<27:27> el<27:28> +n<> u<238> t p<239> c<237> l<27:27> el<27:28> +n<> u<239> t p<240> c<238> l<27:27> el<27:28> +n<> u<240> t p<242> c<239> l<27:27> el<27:28> +n<> u<241> t p<242> s<240> l<27:26> el<27:27> +n<> u<242> t p<243> c<236> l<27:25> el<27:28> +n<> u<243> t p<268> c<231> s<267> l<27:21> el<27:28> +n u<244> t p<245> l<28:10> el<28:12> +n<> u<245> t p<248> c<244> s<247> l<28:10> el<28:12> +n<> u<246> t p<247> l<28:12> el<28:12> +n<> u<247> t p<248> c<246> l<28:12> el<28:12> +n<> u<248> t p<259> c<245> s<258> l<28:10> el<28:12> +n u<249> t p<250> l<28:14> el<28:15> +n<> u<250> t p<251> c<249> l<28:14> el<28:15> +n<> u<251> t p<252> c<250> l<28:14> el<28:15> +n<> u<252> t p<258> c<251> s<257> l<28:14> el<28:15> +n u<253> t p<254> l<28:18> el<28:19> +n<> u<254> t p<255> c<253> l<28:18> el<28:19> +n<> u<255> t p<256> c<254> l<28:18> el<28:19> +n<> u<256> t p<258> c<255> l<28:18> el<28:19> +n<> u<257> t p<258> s<256> l<28:16> el<28:17> +n<> u<258> t p<259> c<252> l<28:14> el<28:19> +n<> u<259> t p<260> c<248> l<28:10> el<28:19> +n<> u<260> t p<261> c<259> l<28:10> el<28:19> +n<> u<261> t p<262> c<260> l<28:3> el<28:20> +n<> u<262> t p<263> c<261> l<28:3> el<28:20> +n<> u<263> t p<264> c<262> l<28:3> el<28:20> +n<> u<264> t p<266> c<263> s<265> l<28:3> el<28:20> +n<> u<265> t p<266> l<30:2> el<30:5> +n<> u<266> t p<267> c<264> l<27:30> el<30:5> +n<> u<267> t p<268> c<266> l<27:30> el<30:5> +n<> u<268> t p<269> c<220> l<27:2> el<30:5> +n<> u<269> t p<270> c<268> l<27:2> el<30:5> +n<> u<270> t p<271> c<269> l<27:2> el<30:5> +n<> u<271> t p<272> c<270> l<27:2> el<30:5> +n<> u<272> t p<273> c<191> l<26:2> el<30:5> +n<> u<273> t p<274> c<272> l<26:2> el<30:5> +n<> u<274> t p<275> c<273> l<26:2> el<30:5> +n<> u<275> t p<277> c<274> s<276> l<26:2> el<30:5> +n<> u<276> t p<277> l<32:1> el<32:12> +n<> u<277> t p<278> c<275> l<25:1> el<32:12> +n<> u<278> t p<279> c<277> l<25:1> el<32:12> +n<> u<279> t p<281> c<278> s<280> l<25:1> el<32:12> +n<> u<280> t p<281> l<34:1> el<34:10> +n<> u<281> t p<282> c<158> l<19:1> el<34:10> +n<> u<282> t p<703> c<281> s<422> l<19:1> el<34:10> +n u<283> t p<298> s<284> l<36:1> el<36:7> +n u<284> t p<298> s<297> l<36:8> el<36:19> +n u<285> t p<288> s<287> l<36:20> el<36:22> +n<> u<286> t p<287> l<36:22> el<36:22> +n<> u<287> t p<288> c<286> l<36:22> el<36:22> +n<> u<288> t p<289> c<285> l<36:20> el<36:22> +n<> u<289> t p<290> c<288> l<36:20> el<36:22> +n<> u<290> t p<297> c<289> s<296> l<36:20> el<36:22> +n u<291> t p<294> s<293> l<36:24> el<36:26> +n<> u<292> t p<293> l<36:26> el<36:26> +n<> u<293> t p<294> c<292> l<36:26> el<36:26> +n<> u<294> t p<295> c<291> l<36:24> el<36:26> +n<> u<295> t p<296> c<294> l<36:24> el<36:26> +n<> u<296> t p<297> c<295> l<36:24> el<36:26> +n<> u<297> t p<298> c<290> l<36:19> el<36:27> +n<> u<298> t p<421> c<283> s<316> l<36:1> el<36:28> +n<2> u<299> t p<300> l<38:9> el<38:10> +n<> u<300> t p<301> c<299> l<38:9> el<38:10> +n<> u<301> t p<302> c<300> l<38:9> el<38:10> +n<> u<302> t p<307> c<301> s<306> l<38:9> el<38:10> +n<0> u<303> t p<304> l<38:11> el<38:12> +n<> u<304> t p<305> c<303> l<38:11> el<38:12> +n<> u<305> t p<306> c<304> l<38:11> el<38:12> +n<> u<306> t p<307> c<305> l<38:11> el<38:12> +n<> u<307> t p<308> c<302> l<38:9> el<38:12> +n<> u<308> t p<309> c<307> l<38:8> el<38:13> +n<> u<309> t p<310> c<308> l<38:8> el<38:13> +n<> u<310> t p<314> c<309> s<313> l<38:8> el<38:13> +n u<311> t p<313> s<312> l<38:14> el<38:16> +n u<312> t p<313> l<38:18> el<38:20> +n<> u<313> t p<314> c<311> l<38:14> el<38:20> +n<> u<314> t p<315> c<310> l<38:1> el<38:20> +n<> u<315> t p<316> c<314> l<38:1> el<38:20> +n<> u<316> t p<421> c<315> s<325> l<38:1> el<38:21> +n u<317> t p<319> s<318> l<40:8> el<40:9> +n u<318> t p<319> l<40:11> el<40:12> +n<> u<319> t p<320> c<317> l<40:8> el<40:12> +n<> u<320> t p<321> c<319> l<40:1> el<40:13> +n<> u<321> t p<322> c<320> l<40:1> el<40:13> +n<> u<322> t p<323> c<321> l<40:1> el<40:13> +n<> u<323> t p<324> c<322> l<40:1> el<40:13> +n<> u<324> t p<325> c<323> l<40:1> el<40:13> +n<> u<325> t p<421> c<324> s<419> l<40:1> el<40:13> +n u<326> t p<331> s<330> l<43:7> el<43:8> +n<0> u<327> t p<328> l<43:11> el<43:12> +n<> u<328> t p<329> c<327> l<43:11> el<43:12> +n<> u<329> t p<330> c<328> l<43:11> el<43:12> +n<> u<330> t p<331> c<329> l<43:11> el<43:12> +n<> u<331> t p<412> c<326> s<341> l<43:7> el<43:12> +n u<332> t p<333> l<43:14> el<43:15> +n<> u<333> t p<334> c<332> l<43:14> el<43:15> +n<> u<334> t p<335> c<333> l<43:14> el<43:15> +n<> u<335> t p<341> c<334> s<340> l<43:14> el<43:15> +n<2> u<336> t p<337> l<43:18> el<43:19> +n<> u<337> t p<338> c<336> l<43:18> el<43:19> +n<> u<338> t p<339> c<337> l<43:18> el<43:19> +n<> u<339> t p<341> c<338> l<43:18> el<43:19> +n<> u<340> t p<341> s<339> l<43:16> el<43:17> +n<> u<341> t p<412> c<335> s<354> l<43:14> el<43:19> +n u<342> t p<354> s<343> l<43:21> el<43:22> +n<> u<343> t p<354> s<353> l<43:23> el<43:24> +n u<344> t p<345> l<43:25> el<43:26> +n<> u<345> t p<346> c<344> l<43:25> el<43:26> +n<> u<346> t p<347> c<345> l<43:25> el<43:26> +n<> u<347> t p<353> c<346> s<352> l<43:25> el<43:26> +n<1> u<348> t p<349> l<43:27> el<43:28> +n<> u<349> t p<350> c<348> l<43:27> el<43:28> +n<> u<350> t p<351> c<349> l<43:27> el<43:28> +n<> u<351> t p<353> c<350> l<43:27> el<43:28> +n<> u<352> t p<353> s<351> l<43:26> el<43:27> +n<> u<353> t p<354> c<347> l<43:25> el<43:28> +n<> u<354> t p<412> c<342> s<411> l<43:21> el<43:28> +n u<355> t p<360> s<359> l<44:7> el<44:8> +n<0> u<356> t p<357> l<44:11> el<44:12> +n<> u<357> t p<358> c<356> l<44:11> el<44:12> +n<> u<358> t p<359> c<357> l<44:11> el<44:12> +n<> u<359> t p<360> c<358> l<44:11> el<44:12> +n<> u<360> t p<405> c<355> s<370> l<44:7> el<44:12> +n u<361> t p<362> l<44:14> el<44:15> +n<> u<362> t p<363> c<361> l<44:14> el<44:15> +n<> u<363> t p<364> c<362> l<44:14> el<44:15> +n<> u<364> t p<370> c<363> s<369> l<44:14> el<44:15> +n<2> u<365> t p<366> l<44:18> el<44:19> +n<> u<366> t p<367> c<365> l<44:18> el<44:19> +n<> u<367> t p<368> c<366> l<44:18> el<44:19> +n<> u<368> t p<370> c<367> l<44:18> el<44:19> +n<> u<369> t p<370> s<368> l<44:16> el<44:17> +n<> u<370> t p<405> c<364> s<383> l<44:14> el<44:19> +n u<371> t p<383> s<372> l<44:21> el<44:22> +n<> u<372> t p<383> s<382> l<44:23> el<44:24> +n u<373> t p<374> l<44:25> el<44:26> +n<> u<374> t p<375> c<373> l<44:25> el<44:26> +n<> u<375> t p<376> c<374> l<44:25> el<44:26> +n<> u<376> t p<382> c<375> s<381> l<44:25> el<44:26> +n<1> u<377> t p<378> l<44:27> el<44:28> +n<> u<378> t p<379> c<377> l<44:27> el<44:28> +n<> u<379> t p<380> c<378> l<44:27> el<44:28> +n<> u<380> t p<382> c<379> l<44:27> el<44:28> +n<> u<381> t p<382> s<380> l<44:26> el<44:27> +n<> u<382> t p<383> c<376> l<44:25> el<44:28> +n<> u<383> t p<405> c<371> s<404> l<44:21> el<44:28> +n u<384> t p<385> l<45:10> el<45:12> +n<> u<385> t p<388> c<384> s<387> l<45:10> el<45:12> +n<> u<386> t p<387> l<45:12> el<45:12> +n<> u<387> t p<388> c<386> l<45:12> el<45:12> +n<> u<388> t p<399> c<385> s<398> l<45:10> el<45:12> +n u<389> t p<390> l<45:14> el<45:15> +n<> u<390> t p<391> c<389> l<45:14> el<45:15> +n<> u<391> t p<392> c<390> l<45:14> el<45:15> +n<> u<392> t p<398> c<391> s<397> l<45:14> el<45:15> +n u<393> t p<394> l<45:18> el<45:19> +n<> u<394> t p<395> c<393> l<45:18> el<45:19> +n<> u<395> t p<396> c<394> l<45:18> el<45:19> +n<> u<396> t p<398> c<395> l<45:18> el<45:19> +n<> u<397> t p<398> s<396> l<45:16> el<45:17> +n<> u<398> t p<399> c<392> l<45:14> el<45:19> +n<> u<399> t p<400> c<388> l<45:10> el<45:19> +n<> u<400> t p<401> c<399> l<45:10> el<45:19> +n<> u<401> t p<402> c<400> l<45:3> el<45:20> +n<> u<402> t p<403> c<401> l<45:3> el<45:20> +n<> u<403> t p<404> c<402> l<45:3> el<45:20> +n<> u<404> t p<405> c<403> l<45:3> el<45:20> +n<> u<405> t p<406> c<360> l<44:2> el<45:20> +n<> u<406> t p<407> c<405> l<44:2> el<45:20> +n<> u<407> t p<408> c<406> l<44:2> el<45:20> +n<> u<408> t p<410> c<407> s<409> l<44:2> el<45:20> +n<> u<409> t p<410> l<47:2> el<47:5> +n<> u<410> t p<411> c<408> l<43:30> el<47:5> +n<> u<411> t p<412> c<410> l<43:30> el<47:5> +n<> u<412> t p<413> c<331> l<43:2> el<47:5> +n<> u<413> t p<414> c<412> l<43:2> el<47:5> +n<> u<414> t p<415> c<413> l<43:2> el<47:5> +n<> u<415> t p<417> c<414> s<416> l<43:2> el<47:5> +n<> u<416> t p<417> l<49:1> el<49:12> +n<> u<417> t p<418> c<415> l<42:1> el<49:12> +n<> u<418> t p<419> c<417> l<42:1> el<49:12> +n<> u<419> t p<421> c<418> s<420> l<42:1> el<49:12> +n<> u<420> t p<421> l<51:1> el<51:10> +n<> u<421> t p<422> c<298> l<36:1> el<51:10> +n<> u<422> t p<703> c<421> s<565> l<36:1> el<51:10> +n u<423> t p<438> s<424> l<53:1> el<53:7> +n u<424> t p<438> s<437> l<53:8> el<53:19> +n u<425> t p<428> s<427> l<53:20> el<53:22> +n<> u<426> t p<427> l<53:22> el<53:22> +n<> u<427> t p<428> c<426> l<53:22> el<53:22> +n<> u<428> t p<429> c<425> l<53:20> el<53:22> +n<> u<429> t p<430> c<428> l<53:20> el<53:22> +n<> u<430> t p<437> c<429> s<436> l<53:20> el<53:22> +n u<431> t p<434> s<433> l<53:24> el<53:26> +n<> u<432> t p<433> l<53:26> el<53:26> +n<> u<433> t p<434> c<432> l<53:26> el<53:26> +n<> u<434> t p<435> c<431> l<53:24> el<53:26> +n<> u<435> t p<436> c<434> l<53:24> el<53:26> +n<> u<436> t p<437> c<435> l<53:24> el<53:26> +n<> u<437> t p<438> c<430> l<53:19> el<53:27> +n<> u<438> t p<564> c<423> s<456> l<53:1> el<53:28> +n<2> u<439> t p<440> l<55:9> el<55:10> +n<> u<440> t p<441> c<439> l<55:9> el<55:10> +n<> u<441> t p<442> c<440> l<55:9> el<55:10> +n<> u<442> t p<447> c<441> s<446> l<55:9> el<55:10> +n<0> u<443> t p<444> l<55:11> el<55:12> +n<> u<444> t p<445> c<443> l<55:11> el<55:12> +n<> u<445> t p<446> c<444> l<55:11> el<55:12> +n<> u<446> t p<447> c<445> l<55:11> el<55:12> +n<> u<447> t p<448> c<442> l<55:9> el<55:12> +n<> u<448> t p<449> c<447> l<55:8> el<55:13> +n<> u<449> t p<450> c<448> l<55:8> el<55:13> +n<> u<450> t p<454> c<449> s<453> l<55:8> el<55:13> +n u<451> t p<453> s<452> l<55:14> el<55:16> +n u<452> t p<453> l<55:18> el<55:20> +n<> u<453> t p<454> c<451> l<55:14> el<55:20> +n<> u<454> t p<455> c<450> l<55:1> el<55:20> +n<> u<455> t p<456> c<454> l<55:1> el<55:20> +n<> u<456> t p<564> c<455> s<465> l<55:1> el<55:21> +n u<457> t p<459> s<458> l<57:8> el<57:9> +n u<458> t p<459> l<57:11> el<57:12> +n<> u<459> t p<460> c<457> l<57:8> el<57:12> +n<> u<460> t p<461> c<459> l<57:1> el<57:13> +n<> u<461> t p<462> c<460> l<57:1> el<57:13> +n<> u<462> t p<463> c<461> l<57:1> el<57:13> +n<> u<463> t p<464> c<462> l<57:1> el<57:13> +n<> u<464> t p<465> c<463> l<57:1> el<57:13> +n<> u<465> t p<564> c<464> s<562> l<57:1> el<57:13> +n u<466> t p<471> s<470> l<60:7> el<60:8> +n<0> u<467> t p<468> l<60:11> el<60:12> +n<> u<468> t p<469> c<467> l<60:11> el<60:12> +n<> u<469> t p<470> c<468> l<60:11> el<60:12> +n<> u<470> t p<471> c<469> l<60:11> el<60:12> +n<> u<471> t p<555> c<466> s<481> l<60:7> el<60:12> +n u<472> t p<473> l<60:14> el<60:15> +n<> u<473> t p<474> c<472> l<60:14> el<60:15> +n<> u<474> t p<475> c<473> l<60:14> el<60:15> +n<> u<475> t p<481> c<474> s<480> l<60:14> el<60:15> +n<2> u<476> t p<477> l<60:18> el<60:19> +n<> u<477> t p<478> c<476> l<60:18> el<60:19> +n<> u<478> t p<479> c<477> l<60:18> el<60:19> +n<> u<479> t p<481> c<478> l<60:18> el<60:19> +n<> u<480> t p<481> s<479> l<60:16> el<60:17> +n<> u<481> t p<555> c<475> s<494> l<60:14> el<60:19> +n u<482> t p<494> s<483> l<60:21> el<60:22> +n<> u<483> t p<494> s<493> l<60:23> el<60:24> +n u<484> t p<485> l<60:25> el<60:26> +n<> u<485> t p<486> c<484> l<60:25> el<60:26> +n<> u<486> t p<487> c<485> l<60:25> el<60:26> +n<> u<487> t p<493> c<486> s<492> l<60:25> el<60:26> +n<1> u<488> t p<489> l<60:27> el<60:28> +n<> u<489> t p<490> c<488> l<60:27> el<60:28> +n<> u<490> t p<491> c<489> l<60:27> el<60:28> +n<> u<491> t p<493> c<490> l<60:27> el<60:28> +n<> u<492> t p<493> s<491> l<60:26> el<60:27> +n<> u<493> t p<494> c<487> l<60:25> el<60:28> +n<> u<494> t p<555> c<482> s<554> l<60:21> el<60:28> +n u<495> t p<500> s<499> l<61:7> el<61:8> +n<0> u<496> t p<497> l<61:11> el<61:12> +n<> u<497> t p<498> c<496> l<61:11> el<61:12> +n<> u<498> t p<499> c<497> l<61:11> el<61:12> +n<> u<499> t p<500> c<498> l<61:11> el<61:12> +n<> u<500> t p<548> c<495> s<510> l<61:7> el<61:12> +n u<501> t p<502> l<61:14> el<61:15> +n<> u<502> t p<503> c<501> l<61:14> el<61:15> +n<> u<503> t p<504> c<502> l<61:14> el<61:15> +n<> u<504> t p<510> c<503> s<509> l<61:14> el<61:15> +n<2> u<505> t p<506> l<61:18> el<61:19> +n<> u<506> t p<507> c<505> l<61:18> el<61:19> +n<> u<507> t p<508> c<506> l<61:18> el<61:19> +n<> u<508> t p<510> c<507> l<61:18> el<61:19> +n<> u<509> t p<510> s<508> l<61:16> el<61:17> +n<> u<510> t p<548> c<504> s<523> l<61:14> el<61:19> +n u<511> t p<523> s<512> l<61:21> el<61:22> +n<> u<512> t p<523> s<522> l<61:23> el<61:24> +n u<513> t p<514> l<61:25> el<61:26> +n<> u<514> t p<515> c<513> l<61:25> el<61:26> +n<> u<515> t p<516> c<514> l<61:25> el<61:26> +n<> u<516> t p<522> c<515> s<521> l<61:25> el<61:26> +n<1> u<517> t p<518> l<61:27> el<61:28> +n<> u<518> t p<519> c<517> l<61:27> el<61:28> +n<> u<519> t p<520> c<518> l<61:27> el<61:28> +n<> u<520> t p<522> c<519> l<61:27> el<61:28> +n<> u<521> t p<522> s<520> l<61:26> el<61:27> +n<> u<522> t p<523> c<516> l<61:25> el<61:28> +n<> u<523> t p<548> c<511> s<547> l<61:21> el<61:28> +n u<524> t p<525> l<62:10> el<62:12> +n<> u<525> t p<528> c<524> s<527> l<62:10> el<62:12> +n<> u<526> t p<527> l<62:12> el<62:12> +n<> u<527> t p<528> c<526> l<62:12> el<62:12> +n<> u<528> t p<539> c<525> s<538> l<62:10> el<62:12> +n u<529> t p<530> l<62:14> el<62:15> +n<> u<530> t p<531> c<529> l<62:14> el<62:15> +n<> u<531> t p<532> c<530> l<62:14> el<62:15> +n<> u<532> t p<538> c<531> s<537> l<62:14> el<62:15> +n u<533> t p<534> l<62:18> el<62:19> +n<> u<534> t p<535> c<533> l<62:18> el<62:19> +n<> u<535> t p<536> c<534> l<62:18> el<62:19> +n<> u<536> t p<538> c<535> l<62:18> el<62:19> +n<> u<537> t p<538> s<536> l<62:16> el<62:17> +n<> u<538> t p<539> c<532> l<62:14> el<62:19> +n<> u<539> t p<540> c<528> l<62:10> el<62:19> +n<> u<540> t p<541> c<539> l<62:10> el<62:19> +n<> u<541> t p<542> c<540> l<62:3> el<62:20> +n<> u<542> t p<543> c<541> l<62:3> el<62:20> +n<> u<543> t p<544> c<542> l<62:3> el<62:20> +n<> u<544> t p<546> c<543> s<545> l<62:3> el<62:20> +n<> u<545> t p<546> l<64:2> el<64:5> +n<> u<546> t p<547> c<544> l<61:30> el<64:5> +n<> u<547> t p<548> c<546> l<61:30> el<64:5> +n<> u<548> t p<549> c<500> l<61:2> el<64:5> +n<> u<549> t p<550> c<548> l<61:2> el<64:5> +n<> u<550> t p<551> c<549> l<61:2> el<64:5> +n<> u<551> t p<553> c<550> s<552> l<61:2> el<64:5> +n<> u<552> t p<553> l<65:9> el<65:12> +n<> u<553> t p<554> c<551> l<60:30> el<65:12> +n<> u<554> t p<555> c<553> l<60:30> el<65:12> +n<> u<555> t p<556> c<471> l<60:2> el<65:12> +n<> u<556> t p<557> c<555> l<60:2> el<65:12> +n<> u<557> t p<558> c<556> l<60:2> el<65:12> +n<> u<558> t p<560> c<557> s<559> l<60:2> el<65:12> +n<> u<559> t p<560> l<67:1> el<67:12> +n<> u<560> t p<561> c<558> l<59:1> el<67:12> +n<> u<561> t p<562> c<560> l<59:1> el<67:12> +n<> u<562> t p<564> c<561> s<563> l<59:1> el<67:12> +n<> u<563> t p<564> l<69:1> el<69:10> +n<> u<564> t p<565> c<438> l<53:1> el<69:10> +n<> u<565> t p<703> c<564> s<702> l<53:1> el<69:10> +n u<566> t p<581> s<567> l<72:1> el<72:7> +n u<567> t p<581> s<580> l<72:8> el<72:19> +n u<568> t p<571> s<570> l<72:20> el<72:22> +n<> u<569> t p<570> l<72:22> el<72:22> +n<> u<570> t p<571> c<569> l<72:22> el<72:22> +n<> u<571> t p<572> c<568> l<72:20> el<72:22> +n<> u<572> t p<573> c<571> l<72:20> el<72:22> +n<> u<573> t p<580> c<572> s<579> l<72:20> el<72:22> +n u<574> t p<577> s<576> l<72:24> el<72:26> +n<> u<575> t p<576> l<72:26> el<72:26> +n<> u<576> t p<577> c<575> l<72:26> el<72:26> +n<> u<577> t p<578> c<574> l<72:24> el<72:26> +n<> u<578> t p<579> c<577> l<72:24> el<72:26> +n<> u<579> t p<580> c<578> l<72:24> el<72:26> +n<> u<580> t p<581> c<573> l<72:19> el<72:27> +n<> u<581> t p<701> c<566> s<599> l<72:1> el<72:28> +n<2> u<582> t p<583> l<74:9> el<74:10> +n<> u<583> t p<584> c<582> l<74:9> el<74:10> +n<> u<584> t p<585> c<583> l<74:9> el<74:10> +n<> u<585> t p<590> c<584> s<589> l<74:9> el<74:10> +n<0> u<586> t p<587> l<74:11> el<74:12> +n<> u<587> t p<588> c<586> l<74:11> el<74:12> +n<> u<588> t p<589> c<587> l<74:11> el<74:12> +n<> u<589> t p<590> c<588> l<74:11> el<74:12> +n<> u<590> t p<591> c<585> l<74:9> el<74:12> +n<> u<591> t p<592> c<590> l<74:8> el<74:13> +n<> u<592> t p<593> c<591> l<74:8> el<74:13> +n<> u<593> t p<597> c<592> s<596> l<74:8> el<74:13> +n u<594> t p<596> s<595> l<74:14> el<74:16> +n u<595> t p<596> l<74:18> el<74:20> +n<> u<596> t p<597> c<594> l<74:14> el<74:20> +n<> u<597> t p<598> c<593> l<74:1> el<74:20> +n<> u<598> t p<599> c<597> l<74:1> el<74:20> +n<> u<599> t p<701> c<598> s<608> l<74:1> el<74:21> +n u<600> t p<602> s<601> l<76:8> el<76:9> +n u<601> t p<602> l<76:11> el<76:12> +n<> u<602> t p<603> c<600> l<76:8> el<76:12> +n<> u<603> t p<604> c<602> l<76:1> el<76:13> +n<> u<604> t p<605> c<603> l<76:1> el<76:13> +n<> u<605> t p<606> c<604> l<76:1> el<76:13> +n<> u<606> t p<607> c<605> l<76:1> el<76:13> +n<> u<607> t p<608> c<606> l<76:1> el<76:13> +n<> u<608> t p<701> c<607> s<699> l<76:1> el<76:13> +n u<609> t p<614> s<613> l<79:7> el<79:8> +n<0> u<610> t p<611> l<79:11> el<79:12> +n<> u<611> t p<612> c<610> l<79:11> el<79:12> +n<> u<612> t p<613> c<611> l<79:11> el<79:12> +n<> u<613> t p<614> c<612> l<79:11> el<79:12> +n<> u<614> t p<692> c<609> s<624> l<79:7> el<79:12> +n u<615> t p<616> l<79:14> el<79:15> +n<> u<616> t p<617> c<615> l<79:14> el<79:15> +n<> u<617> t p<618> c<616> l<79:14> el<79:15> +n<> u<618> t p<624> c<617> s<623> l<79:14> el<79:15> +n<2> u<619> t p<620> l<79:18> el<79:19> +n<> u<620> t p<621> c<619> l<79:18> el<79:19> +n<> u<621> t p<622> c<620> l<79:18> el<79:19> +n<> u<622> t p<624> c<621> l<79:18> el<79:19> +n<> u<623> t p<624> s<622> l<79:16> el<79:17> +n<> u<624> t p<692> c<618> s<637> l<79:14> el<79:19> +n u<625> t p<637> s<626> l<79:21> el<79:22> +n<> u<626> t p<637> s<636> l<79:23> el<79:24> +n u<627> t p<628> l<79:25> el<79:26> +n<> u<628> t p<629> c<627> l<79:25> el<79:26> +n<> u<629> t p<630> c<628> l<79:25> el<79:26> +n<> u<630> t p<636> c<629> s<635> l<79:25> el<79:26> +n<1> u<631> t p<632> l<79:27> el<79:28> +n<> u<632> t p<633> c<631> l<79:27> el<79:28> +n<> u<633> t p<634> c<632> l<79:27> el<79:28> +n<> u<634> t p<636> c<633> l<79:27> el<79:28> +n<> u<635> t p<636> s<634> l<79:26> el<79:27> +n<> u<636> t p<637> c<630> l<79:25> el<79:28> +n<> u<637> t p<692> c<625> s<691> l<79:21> el<79:28> +n u<638> t p<643> s<642> l<80:7> el<80:8> +n<0> u<639> t p<640> l<80:11> el<80:12> +n<> u<640> t p<641> c<639> l<80:11> el<80:12> +n<> u<641> t p<642> c<640> l<80:11> el<80:12> +n<> u<642> t p<643> c<641> l<80:11> el<80:12> +n<> u<643> t p<688> c<638> s<653> l<80:7> el<80:12> +n u<644> t p<645> l<80:14> el<80:15> +n<> u<645> t p<646> c<644> l<80:14> el<80:15> +n<> u<646> t p<647> c<645> l<80:14> el<80:15> +n<> u<647> t p<653> c<646> s<652> l<80:14> el<80:15> +n<2> u<648> t p<649> l<80:18> el<80:19> +n<> u<649> t p<650> c<648> l<80:18> el<80:19> +n<> u<650> t p<651> c<649> l<80:18> el<80:19> +n<> u<651> t p<653> c<650> l<80:18> el<80:19> +n<> u<652> t p<653> s<651> l<80:16> el<80:17> +n<> u<653> t p<688> c<647> s<666> l<80:14> el<80:19> +n u<654> t p<666> s<655> l<80:21> el<80:22> +n<> u<655> t p<666> s<665> l<80:23> el<80:24> +n u<656> t p<657> l<80:25> el<80:26> +n<> u<657> t p<658> c<656> l<80:25> el<80:26> +n<> u<658> t p<659> c<657> l<80:25> el<80:26> +n<> u<659> t p<665> c<658> s<664> l<80:25> el<80:26> +n<1> u<660> t p<661> l<80:27> el<80:28> +n<> u<661> t p<662> c<660> l<80:27> el<80:28> +n<> u<662> t p<663> c<661> l<80:27> el<80:28> +n<> u<663> t p<665> c<662> l<80:27> el<80:28> +n<> u<664> t p<665> s<663> l<80:26> el<80:27> +n<> u<665> t p<666> c<659> l<80:25> el<80:28> +n<> u<666> t p<688> c<654> s<687> l<80:21> el<80:28> +n u<667> t p<668> l<81:10> el<81:12> +n<> u<668> t p<671> c<667> s<670> l<81:10> el<81:12> +n<> u<669> t p<670> l<81:12> el<81:12> +n<> u<670> t p<671> c<669> l<81:12> el<81:12> +n<> u<671> t p<682> c<668> s<681> l<81:10> el<81:12> +n u<672> t p<673> l<81:14> el<81:15> +n<> u<673> t p<674> c<672> l<81:14> el<81:15> +n<> u<674> t p<675> c<673> l<81:14> el<81:15> +n<> u<675> t p<681> c<674> s<680> l<81:14> el<81:15> +n u<676> t p<677> l<81:18> el<81:19> +n<> u<677> t p<678> c<676> l<81:18> el<81:19> +n<> u<678> t p<679> c<677> l<81:18> el<81:19> +n<> u<679> t p<681> c<678> l<81:18> el<81:19> +n<> u<680> t p<681> s<679> l<81:16> el<81:17> +n<> u<681> t p<682> c<675> l<81:14> el<81:19> +n<> u<682> t p<683> c<671> l<81:10> el<81:19> +n<> u<683> t p<684> c<682> l<81:10> el<81:19> +n<> u<684> t p<685> c<683> l<81:3> el<81:20> +n<> u<685> t p<686> c<684> l<81:3> el<81:20> +n<> u<686> t p<687> c<685> l<81:3> el<81:20> +n<> u<687> t p<688> c<686> l<81:3> el<81:20> +n<> u<688> t p<689> c<643> l<80:2> el<81:20> +n<> u<689> t p<690> c<688> l<80:2> el<81:20> +n<> u<690> t p<691> c<689> l<80:2> el<81:20> +n<> u<691> t p<692> c<690> l<80:2> el<81:20> +n<> u<692> t p<693> c<614> l<79:2> el<81:20> +n<> u<693> t p<694> c<692> l<79:2> el<81:20> +n<> u<694> t p<695> c<693> l<79:2> el<81:20> +n<> u<695> t p<697> c<694> s<696> l<79:2> el<81:20> +n<> u<696> t p<697> l<86:1> el<86:12> +n<> u<697> t p<698> c<695> l<78:1> el<86:12> +n<> u<698> t p<699> c<697> l<78:1> el<86:12> +n<> u<699> t p<701> c<698> s<700> l<78:1> el<86:12> +n<> u<700> t p<701> l<88:1> el<88:10> +n<> u<701> t p<702> c<581> l<72:1> el<88:10> +n<> u<702> t p<703> c<701> l<72:1> el<88:10> +n<> u<703> t p<704> c<142> l<2:1> el<88:10> +n<> u<704> t c<1> l<2:1> el<89:1> AST_DEBUG_END -[WRN:PA0205] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:1: No timescale set for "constpower". +[WRN:PA0205] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:1: No timescale set for "constpower1". + +[WRN:PA0205] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:19:1: No timescale set for "constpower2". + +[WRN:PA0205] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:36:1: No timescale set for "constpower3". + +[WRN:PA0205] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:53:1: No timescale set for "constpower4". + +[WRN:PA0205] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:72:1: No timescale set for "constpower5". [INF:CP0300] Compilation... -[INF:CP0303] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:1: Compile module "work@constpower". +[INF:CP0303] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:1: Compile module "work@constpower1". + +[INF:CP0303] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:19:1: Compile module "work@constpower2". + +[INF:CP0303] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:36:1: Compile module "work@constpower3". + +[INF:CP0303] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:53:1: Compile module "work@constpower4". + +[INF:CP0303] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:72:1: Compile module "work@constpower5". + +[NTE:CP0309] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:20: Implicit port type (wire) for "ys", +there are 1 more instances of this message. + +[NTE:CP0309] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:19:20: Implicit port type (wire) for "ys", +there are 1 more instances of this message. + +[NTE:CP0309] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:36:20: Implicit port type (wire) for "ys", +there are 1 more instances of this message. + +[NTE:CP0309] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:53:20: Implicit port type (wire) for "ys", +there are 1 more instances of this message. -[NTE:CP0309] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:19: Implicit port type (wire) for "ys", +[NTE:CP0309] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:72:20: Implicit port type (wire) for "ys", there are 1 more instances of this message. [INF:EL0526] Design Elaboration... -[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:2: Compile generate block "work@constpower.genblk1[0]". +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:2: Compile generate block "work@constpower1.genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower1.genblk1[0].W[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower1.genblk1[0].W[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:2: Compile generate block "work@constpower1.genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower1.genblk1[1].W[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower1.genblk1[1].W[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:27:2: Compile generate block "work@constpower2.genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:27:30: Compile generate block "work@constpower2.genblk1[0].genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:27:30: Compile generate block "work@constpower2.genblk1[0].genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:27:2: Compile generate block "work@constpower2.genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:27:30: Compile generate block "work@constpower2.genblk1[1].genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:27:30: Compile generate block "work@constpower2.genblk1[1].genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:43:30: Compile generate block "work@constpower3.genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:45:3: Compile generate block "work@constpower3.genblk1[0].genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:45:3: Compile generate block "work@constpower3.genblk1[0].genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:43:30: Compile generate block "work@constpower3.genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:45:3: Compile generate block "work@constpower3.genblk1[1].genblk1[0]". -[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower.genblk1[0].W[0]". +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:45:3: Compile generate block "work@constpower3.genblk1[1].genblk1[1]". -[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower.genblk1[0].W[1]". +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:60:30: Compile generate block "work@constpower4.genblk1[0]". -[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:2: Compile generate block "work@constpower.genblk1[1]". +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:61:30: Compile generate block "work@constpower4.genblk1[0].genblk1[0]". -[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower.genblk1[1].W[0]". +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:61:30: Compile generate block "work@constpower4.genblk1[0].genblk1[1]". -[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:10:30: Compile generate block "work@constpower.genblk1[1].W[1]". +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:60:30: Compile generate block "work@constpower4.genblk1[1]". -[NTE:EL0503] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:1: Top level module "work@constpower". +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:61:30: Compile generate block "work@constpower4.genblk1[1].genblk1[0]". -[NTE:EL0508] Nb Top level modules: 1. +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:61:30: Compile generate block "work@constpower4.genblk1[1].genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:80:2: Compile generate block "work@constpower5.genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:81:3: Compile generate block "work@constpower5.genblk1[0].genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:81:3: Compile generate block "work@constpower5.genblk1[0].genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:80:2: Compile generate block "work@constpower5.genblk1[1]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:81:3: Compile generate block "work@constpower5.genblk1[1].genblk1[0]". + +[INF:CP0335] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:81:3: Compile generate block "work@constpower5.genblk1[1].genblk1[1]". + +[NTE:EL0503] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:2:1: Top level module "work@constpower1". + +[NTE:EL0503] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:19:1: Top level module "work@constpower2". + +[NTE:EL0503] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:36:1: Top level module "work@constpower3". + +[NTE:EL0503] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:53:1: Top level module "work@constpower4". + +[NTE:EL0503] ${SURELOG_DIR}/tests/DoubleLoop/dut.sv:72:1: Top level module "work@constpower5". + +[NTE:EL0504] Multiple top level modules in design. + +[NTE:EL0508] Nb Top level modules: 5. [NTE:EL0509] Max instance depth: 1. -[NTE:EL0510] Nb instances: 1. +[NTE:EL0510] Nb instances: 5. [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -begin 1 -constant 62 -cont_assign 8 +begin 5 +constant 330 +cont_assign 40 design 1 -gen_region 1 -gen_scope 10 -gen_scope_array 10 -int_typespec 8 -logic_net 4 -logic_typespec 4 -module_inst 5 -operation 17 -param_assign 4 -parameter 8 -port 4 -range 6 -ref_obj 28 +gen_region 5 +gen_scope 60 +gen_scope_array 60 +int_typespec 30 +logic_net 20 +logic_typespec 20 +module_inst 17 +operation 85 +parameter 30 +port 20 +range 30 +ref_obj 140 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -begin 1 -constant 62 -cont_assign 12 +begin 5 +constant 330 +cont_assign 60 design 1 -gen_region 1 -gen_scope 14 -gen_scope_array 14 -int_typespec 8 -logic_net 4 -logic_typespec 4 -module_inst 5 -operation 17 -param_assign 8 -parameter 8 -port 6 -range 6 -ref_obj 34 +gen_region 5 +gen_scope 90 +gen_scope_array 90 +int_typespec 30 +logic_net 20 +logic_typespec 20 +module_inst 17 +operation 85 +parameter 30 +port 30 +range 30 +ref_obj 170 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/DoubleLoop/slpp_all/surelog.uhdm ... @@ -233,41 +877,41 @@ ref_obj 34 [INF:UH0711] Decompiling UHDM... ====== UHDM ======= -design: (work@constpower) +design: (work@constpower1) |vpiElaborated:1 -|vpiName:work@constpower +|vpiName:work@constpower1 |uhdmallModules: -\_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 +\_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 |vpiParent: - \_design: (work@constpower) - |vpiFullName:work@constpower - |vpiDefName:work@constpower + \_design: (work@constpower1) + |vpiFullName:work@constpower1 + |vpiDefName:work@constpower1 |vpiNet: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 |vpiName:ys - |vpiFullName:work@constpower.ys + |vpiFullName:work@constpower1.ys |vpiNet: - \_logic_net: (work@constpower.yu), line:2:23, endln:2:25 + \_logic_net: (work@constpower1.yu), line:2:24, endln:2:26 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 |vpiName:yu - |vpiFullName:work@constpower.yu + |vpiFullName:work@constpower1.yu |vpiPort: - \_port: (ys), line:2:19, endln:2:21 + \_port: (ys), line:2:20, endln:2:22 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 |vpiName:ys |vpiDirection:2 |vpiLowConn: - \_ref_obj: (work@constpower.ys.ys), line:2:19, endln:2:21 + \_ref_obj: (work@constpower1.ys.ys), line:2:20, endln:2:22 |vpiParent: - \_port: (ys), line:2:19, endln:2:21 + \_port: (ys), line:2:20, endln:2:22 |vpiName:ys - |vpiFullName:work@constpower.ys.ys + |vpiFullName:work@constpower1.ys.ys |vpiActual: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 |vpiTypedef: \_logic_typespec: , line:4:8, endln:4:13 |vpiRange: @@ -291,19 +935,19 @@ design: (work@constpower) |UINT:0 |vpiConstType:9 |vpiPort: - \_port: (yu), line:2:23, endln:2:25 + \_port: (yu), line:2:24, endln:2:26 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 |vpiName:yu |vpiDirection:2 |vpiLowConn: - \_ref_obj: (work@constpower.yu.yu), line:2:23, endln:2:25 + \_ref_obj: (work@constpower1.yu.yu), line:2:24, endln:2:26 |vpiParent: - \_port: (yu), line:2:23, endln:2:25 + \_port: (yu), line:2:24, endln:2:26 |vpiName:yu - |vpiFullName:work@constpower.yu.yu + |vpiFullName:work@constpower1.yu.yu |vpiActual: - \_logic_net: (work@constpower.yu), line:2:23, endln:2:25 + \_logic_net: (work@constpower1.yu), line:2:24, endln:2:26 |vpiTypedef: \_logic_typespec: , line:4:8, endln:4:13 |vpiRange: @@ -329,348 +973,1894 @@ design: (work@constpower) |vpiGenStmt: \_gen_region: |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 |vpiStmt: - \_begin: (work@constpower) + \_begin: (work@constpower1) |vpiParent: \_gen_region: - |vpiFullName:work@constpower -|uhdmtopModules: -\_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiName:work@constpower - |vpiDefName:work@constpower - |vpiTop:1 + |vpiFullName:work@constpower1 +|uhdmallModules: +\_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiParent: + \_design: (work@constpower1) + |vpiFullName:work@constpower2 + |vpiDefName:work@constpower2 |vpiNet: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiTypespec: - \_logic_typespec: , line:4:8, endln:4:13 + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:ys + |vpiFullName:work@constpower2.ys + |vpiNet: + \_logic_net: (work@constpower2.yu), line:19:24, endln:19:26 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:yu + |vpiFullName:work@constpower2.yu + |vpiPort: + \_port: (ys), line:19:20, endln:19:22 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower2.ys.ys), line:19:20, endln:19:22 + |vpiParent: + \_port: (ys), line:19:20, endln:19:22 + |vpiName:ys + |vpiFullName:work@constpower2.ys.ys + |vpiActual: + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 + |vpiTypedef: + \_logic_typespec: , line:21:8, endln:21:13 |vpiRange: - \_range: , line:4:8, endln:4:13 + \_range: , line:21:8, endln:21:13 |vpiParent: - \_logic_typespec: , line:4:8, endln:4:13 + \_logic_typespec: , line:21:8, endln:21:13 |vpiLeftRange: - \_constant: , line:4:9, endln:4:10 + \_constant: , line:21:9, endln:21:10 |vpiParent: - \_range: , line:4:8, endln:4:13 + \_range: , line:21:8, endln:21:13 |vpiDecompile:2 |vpiSize:64 |UINT:2 |vpiConstType:9 |vpiRightRange: - \_constant: , line:4:11, endln:4:12 + \_constant: , line:21:11, endln:21:12 |vpiParent: - \_range: , line:4:8, endln:4:13 + \_range: , line:21:8, endln:21:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiPort: + \_port: (yu), line:19:24, endln:19:26 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower2.yu.yu), line:19:24, endln:19:26 + |vpiParent: + \_port: (yu), line:19:24, endln:19:26 + |vpiName:yu + |vpiFullName:work@constpower2.yu.yu + |vpiActual: + \_logic_net: (work@constpower2.yu), line:19:24, endln:19:26 + |vpiTypedef: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiRange: + \_range: , line:21:8, endln:21:13 + |vpiParent: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiLeftRange: + \_constant: , line:21:9, endln:21:10 + |vpiParent: + \_range: , line:21:8, endln:21:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:21:11, endln:21:12 + |vpiParent: + \_range: , line:21:8, endln:21:13 |vpiDecompile:0 |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiGenStmt: + \_gen_region: + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiStmt: + \_begin: (work@constpower2) + |vpiParent: + \_gen_region: + |vpiFullName:work@constpower2 +|uhdmallModules: +\_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiParent: + \_design: (work@constpower1) + |vpiFullName:work@constpower3 + |vpiDefName:work@constpower3 + |vpiNet: + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 + |vpiParent: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 |vpiName:ys - |vpiFullName:work@constpower.ys + |vpiFullName:work@constpower3.ys |vpiNet: - \_logic_net: (work@constpower.yu), line:2:23, endln:2:25 + \_logic_net: (work@constpower3.yu), line:36:24, endln:36:26 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiTypespec: - \_logic_typespec: , line:4:8, endln:4:13 + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 |vpiName:yu - |vpiFullName:work@constpower.yu - |vpiTopModule:1 + |vpiFullName:work@constpower3.yu |vpiPort: - \_port: (ys), line:2:19, endln:2:21 + \_port: (ys), line:36:20, endln:36:22 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 |vpiName:ys |vpiDirection:2 |vpiLowConn: - \_ref_obj: (work@constpower.ys), line:2:19, endln:2:21 + \_ref_obj: (work@constpower3.ys.ys), line:36:20, endln:36:22 |vpiParent: - \_port: (ys), line:2:19, endln:2:21 + \_port: (ys), line:36:20, endln:36:22 |vpiName:ys - |vpiFullName:work@constpower.ys + |vpiFullName:work@constpower3.ys.ys |vpiActual: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 |vpiTypedef: - \_logic_typespec: , line:4:8, endln:4:13 + \_logic_typespec: , line:38:8, endln:38:13 |vpiRange: - \_range: , line:4:8, endln:4:13 + \_range: , line:38:8, endln:38:13 |vpiParent: - \_logic_typespec: , line:4:8, endln:4:13 + \_logic_typespec: , line:38:8, endln:38:13 |vpiLeftRange: - \_constant: , line:4:9, endln:4:10 + \_constant: , line:38:9, endln:38:10 |vpiParent: - \_range: , line:4:8, endln:4:13 + \_range: , line:38:8, endln:38:13 |vpiDecompile:2 |vpiSize:64 |UINT:2 |vpiConstType:9 |vpiRightRange: - \_constant: , line:4:11, endln:4:12 + \_constant: , line:38:11, endln:38:12 |vpiParent: - \_range: , line:4:8, endln:4:13 + \_range: , line:38:8, endln:38:13 |vpiDecompile:0 |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiInstance: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 |vpiPort: - \_port: (yu), line:2:23, endln:2:25 + \_port: (yu), line:36:24, endln:36:26 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 |vpiName:yu |vpiDirection:2 |vpiLowConn: - \_ref_obj: (work@constpower.yu), line:2:23, endln:2:25 + \_ref_obj: (work@constpower3.yu.yu), line:36:24, endln:36:26 |vpiParent: - \_port: (yu), line:2:23, endln:2:25 + \_port: (yu), line:36:24, endln:36:26 |vpiName:yu - |vpiFullName:work@constpower.yu + |vpiFullName:work@constpower3.yu.yu |vpiActual: - \_logic_net: (work@constpower.yu), line:2:23, endln:2:25 + \_logic_net: (work@constpower3.yu), line:36:24, endln:36:26 |vpiTypedef: - \_logic_typespec: , line:4:8, endln:4:13 - |vpiInstance: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiGenScopeArray: - \_gen_scope_array: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiName:W[0] - |vpiFullName:work@constpower.W[0] - |vpiGenScope: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiParent: - \_gen_scope_array: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiFullName:work@constpower.W[0] - |vpiParameter: - \_parameter: (work@constpower.W[0].i), line:9:0 - |vpiParent: - \_param_assign: - |UINT:0 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:i - |vpiFullName:work@constpower.W[0].i - |vpiParameter: - \_parameter: (work@constpower.W[0].j), line:10:0 + \_logic_typespec: , line:38:8, endln:38:13 + |vpiRange: + \_range: , line:38:8, endln:38:13 |vpiParent: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 - |UINT:0 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:j - |vpiFullName:work@constpower.W[0].j - |vpiParamAssign: - \_param_assign: - |vpiParent: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: - |UINT:0 - |vpiLhs: - \_parameter: (work@constpower.W[0].i), line:9:0 - |vpiContAssign: - \_cont_assign: , line:11:10, endln:11:19 - |vpiParent: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: + \_logic_typespec: , line:38:8, endln:38:13 + |vpiLeftRange: + \_constant: , line:38:9, endln:38:10 + |vpiParent: + \_range: , line:38:8, endln:38:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:38:11, endln:38:12 + |vpiParent: + \_range: , line:38:8, endln:38:13 |vpiDecompile:0 - |vpiSize:3 + |vpiSize:64 |UINT:0 |vpiConstType:9 - |vpiLhs: - \_ref_obj: (work@constpower.W[0].ys), line:11:10, endln:11:12 - |vpiParent: - \_cont_assign: , line:11:10, endln:11:19 - |vpiName:ys - |vpiFullName:work@constpower.W[0].ys - |vpiActual: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 - |vpiGenScopeArray: - \_gen_scope_array: (work@constpower.W[1]), line:10:30, endln:13:5 + |vpiGenStmt: + \_gen_region: |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiName:W[1] - |vpiFullName:work@constpower.W[1] - |vpiGenScope: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiStmt: + \_begin: (work@constpower3) |vpiParent: - \_gen_scope_array: (work@constpower.W[1]), line:10:30, endln:13:5 - |vpiFullName:work@constpower.W[1] - |vpiParameter: - \_parameter: (work@constpower.W[1].i), line:9:0 - |vpiParent: - \_param_assign: - |UINT:0 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:i - |vpiFullName:work@constpower.W[1].i - |vpiParameter: - \_parameter: (work@constpower.W[1].j), line:10:0 - |vpiParent: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 - |UINT:1 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:j - |vpiFullName:work@constpower.W[1].j - |vpiParamAssign: - \_param_assign: - |vpiParent: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: - |UINT:0 - |vpiLhs: - \_parameter: (work@constpower.W[1].i), line:9:0 - |vpiContAssign: - \_cont_assign: , line:11:10, endln:11:19 - |vpiParent: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: - |vpiDecompile:1 - |vpiSize:3 - |UINT:1 - |vpiConstType:9 - |vpiLhs: - \_ref_obj: (work@constpower.W[1].ys), line:11:10, endln:11:12 - |vpiParent: - \_cont_assign: , line:11:10, endln:11:19 - |vpiName:ys - |vpiFullName:work@constpower.W[1].ys - |vpiActual: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 - |vpiGenScopeArray: - \_gen_scope_array: (work@constpower.W[0]), line:10:30, endln:13:5 + \_gen_region: + |vpiFullName:work@constpower3 +|uhdmallModules: +\_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiParent: + \_design: (work@constpower1) + |vpiFullName:work@constpower4 + |vpiDefName:work@constpower4 + |vpiNet: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiName:W[0] - |vpiFullName:work@constpower.W[0] - |vpiGenScope: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:ys + |vpiFullName:work@constpower4.ys + |vpiNet: + \_logic_net: (work@constpower4.yu), line:53:24, endln:53:26 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:yu + |vpiFullName:work@constpower4.yu + |vpiPort: + \_port: (ys), line:53:20, endln:53:22 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower4.ys.ys), line:53:20, endln:53:22 |vpiParent: - \_gen_scope_array: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiFullName:work@constpower.W[0] - |vpiParameter: - \_parameter: (work@constpower.W[0].i), line:9:0 - |vpiParent: - \_param_assign: - |UINT:1 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:i - |vpiFullName:work@constpower.W[0].i - |vpiParameter: - \_parameter: (work@constpower.W[0].j), line:10:0 + \_port: (ys), line:53:20, endln:53:22 + |vpiName:ys + |vpiFullName:work@constpower4.ys.ys + |vpiActual: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 + |vpiTypedef: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiRange: + \_range: , line:55:8, endln:55:13 |vpiParent: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 - |UINT:0 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:j - |vpiFullName:work@constpower.W[0].j - |vpiParamAssign: - \_param_assign: - |vpiParent: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: - |UINT:1 - |vpiLhs: - \_parameter: (work@constpower.W[0].i), line:9:0 - |vpiContAssign: - \_cont_assign: , line:11:10, endln:11:19 - |vpiParent: - \_gen_scope: (work@constpower.W[0]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: - |vpiDecompile:1 - |vpiSize:3 - |UINT:1 - |vpiConstType:9 - |vpiLhs: - \_ref_obj: (work@constpower.W[0].ys), line:11:10, endln:11:12 + \_logic_typespec: , line:55:8, endln:55:13 + |vpiLeftRange: + \_constant: , line:55:9, endln:55:10 |vpiParent: - \_cont_assign: , line:11:10, endln:11:19 - |vpiName:ys - |vpiFullName:work@constpower.W[0].ys - |vpiActual: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 - |vpiGenScopeArray: - \_gen_scope_array: (work@constpower.W[1]), line:10:30, endln:13:5 + \_range: , line:55:8, endln:55:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:55:11, endln:55:12 + |vpiParent: + \_range: , line:55:8, endln:55:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiPort: + \_port: (yu), line:53:24, endln:53:26 |vpiParent: - \_module_inst: work@constpower (work@constpower), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 - |vpiName:W[1] - |vpiFullName:work@constpower.W[1] - |vpiGenScope: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower4.yu.yu), line:53:24, endln:53:26 |vpiParent: - \_gen_scope_array: (work@constpower.W[1]), line:10:30, endln:13:5 - |vpiFullName:work@constpower.W[1] - |vpiParameter: - \_parameter: (work@constpower.W[1].i), line:9:0 - |vpiParent: - \_param_assign: - |UINT:1 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:i - |vpiFullName:work@constpower.W[1].i - |vpiParameter: - \_parameter: (work@constpower.W[1].j), line:10:0 + \_port: (yu), line:53:24, endln:53:26 + |vpiName:yu + |vpiFullName:work@constpower4.yu.yu + |vpiActual: + \_logic_net: (work@constpower4.yu), line:53:24, endln:53:26 + |vpiTypedef: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiRange: + \_range: , line:55:8, endln:55:13 |vpiParent: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 - |UINT:1 - |vpiTypespec: - \_int_typespec: - |vpiLocalParam:1 - |vpiName:j - |vpiFullName:work@constpower.W[1].j - |vpiParamAssign: - \_param_assign: - |vpiParent: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: - |UINT:1 - |vpiLhs: - \_parameter: (work@constpower.W[1].i), line:9:0 - |vpiContAssign: - \_cont_assign: , line:11:10, endln:11:19 - |vpiParent: - \_gen_scope: (work@constpower.W[1]), line:10:30, endln:13:5 - |vpiRhs: - \_constant: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiLeftRange: + \_constant: , line:55:9, endln:55:10 + |vpiParent: + \_range: , line:55:8, endln:55:13 |vpiDecompile:2 - |vpiSize:3 + |vpiSize:64 |UINT:2 |vpiConstType:9 - |vpiLhs: - \_ref_obj: (work@constpower.W[1].ys), line:11:10, endln:11:12 + |vpiRightRange: + \_constant: , line:55:11, endln:55:12 |vpiParent: - \_cont_assign: , line:11:10, endln:11:19 - |vpiName:ys - |vpiFullName:work@constpower.W[1].ys - |vpiActual: - \_logic_net: (work@constpower.ys), line:2:19, endln:2:21 + \_range: , line:55:8, endln:55:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiGenStmt: + \_gen_region: + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiStmt: + \_begin: (work@constpower4) + |vpiParent: + \_gen_region: + |vpiFullName:work@constpower4 +|uhdmallModules: +\_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiParent: + \_design: (work@constpower1) + |vpiFullName:work@constpower5 + |vpiDefName:work@constpower5 + |vpiNet: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:ys + |vpiFullName:work@constpower5.ys + |vpiNet: + \_logic_net: (work@constpower5.yu), line:72:24, endln:72:26 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:yu + |vpiFullName:work@constpower5.yu + |vpiPort: + \_port: (ys), line:72:20, endln:72:22 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower5.ys.ys), line:72:20, endln:72:22 + |vpiParent: + \_port: (ys), line:72:20, endln:72:22 + |vpiName:ys + |vpiFullName:work@constpower5.ys.ys + |vpiActual: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiTypedef: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiRange: + \_range: , line:74:8, endln:74:13 + |vpiParent: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiLeftRange: + \_constant: , line:74:9, endln:74:10 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:74:11, endln:74:12 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiPort: + \_port: (yu), line:72:24, endln:72:26 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower5.yu.yu), line:72:24, endln:72:26 + |vpiParent: + \_port: (yu), line:72:24, endln:72:26 + |vpiName:yu + |vpiFullName:work@constpower5.yu.yu + |vpiActual: + \_logic_net: (work@constpower5.yu), line:72:24, endln:72:26 + |vpiTypedef: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiRange: + \_range: , line:74:8, endln:74:13 + |vpiParent: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiLeftRange: + \_constant: , line:74:9, endln:74:10 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:74:11, endln:74:12 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiGenStmt: + \_gen_region: + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiStmt: + \_begin: (work@constpower5) + |vpiParent: + \_gen_region: + |vpiFullName:work@constpower5 +|uhdmtopModules: +\_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiName:work@constpower1 + |vpiDefName:work@constpower1 + |vpiTop:1 + |vpiNet: + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 + |vpiParent: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiTypespec: + \_logic_typespec: , line:4:8, endln:4:13 + |vpiRange: + \_range: , line:4:8, endln:4:13 + |vpiParent: + \_logic_typespec: , line:4:8, endln:4:13 + |vpiLeftRange: + \_constant: , line:4:9, endln:4:10 + |vpiParent: + \_range: , line:4:8, endln:4:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:4:11, endln:4:12 + |vpiParent: + \_range: , line:4:8, endln:4:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:ys + |vpiFullName:work@constpower1.ys + |vpiNet: + \_logic_net: (work@constpower1.yu), line:2:24, endln:2:26 + |vpiParent: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiTypespec: + \_logic_typespec: , line:4:8, endln:4:13 + |vpiName:yu + |vpiFullName:work@constpower1.yu + |vpiTopModule:1 + |vpiPort: + \_port: (ys), line:2:20, endln:2:22 + |vpiParent: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower1.ys), line:2:20, endln:2:22 + |vpiParent: + \_port: (ys), line:2:20, endln:2:22 + |vpiName:ys + |vpiFullName:work@constpower1.ys + |vpiActual: + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 + |vpiTypedef: + \_logic_typespec: , line:4:8, endln:4:13 + |vpiRange: + \_range: , line:4:8, endln:4:13 + |vpiParent: + \_logic_typespec: , line:4:8, endln:4:13 + |vpiLeftRange: + \_constant: , line:4:9, endln:4:10 + |vpiParent: + \_range: , line:4:8, endln:4:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:4:11, endln:4:12 + |vpiParent: + \_range: , line:4:8, endln:4:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiInstance: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiPort: + \_port: (yu), line:2:24, endln:2:26 + |vpiParent: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower1.yu), line:2:24, endln:2:26 + |vpiParent: + \_port: (yu), line:2:24, endln:2:26 + |vpiName:yu + |vpiFullName:work@constpower1.yu + |vpiActual: + \_logic_net: (work@constpower1.yu), line:2:24, endln:2:26 + |vpiTypedef: + \_logic_typespec: , line:4:8, endln:4:13 + |vpiInstance: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower1.genblk1[0]), line:10:2, endln:13:5 + |vpiParent: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiName:genblk1[0] + |vpiFullName:work@constpower1.genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower1.genblk1[0]), line:10:2, endln:13:5 + |vpiParent: + \_gen_scope_array: (work@constpower1.genblk1[0]), line:10:2, endln:13:5 + |vpiFullName:work@constpower1.genblk1[0] + |vpiParameter: + \_parameter: (work@constpower1.genblk1[0].i), line:9:0 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[0]), line:10:2, endln:13:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower1.genblk1[0].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower1.genblk1[0].W[0]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[0]), line:10:2, endln:13:5 + |vpiName:W[0] + |vpiFullName:work@constpower1.genblk1[0].W[0] + |vpiGenScope: + \_gen_scope: (work@constpower1.genblk1[0].W[0]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope_array: (work@constpower1.genblk1[0].W[0]), line:10:30, endln:13:5 + |vpiFullName:work@constpower1.genblk1[0].W[0] + |vpiParameter: + \_parameter: (work@constpower1.genblk1[0].W[0].j), line:10:0 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[0].W[0]), line:10:30, endln:13:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower1.genblk1[0].W[0].j + |vpiContAssign: + \_cont_assign: , line:11:10, endln:11:19 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[0].W[0]), line:10:30, endln:13:5 + |vpiRhs: + \_constant: + |vpiDecompile:0 + |vpiSize:3 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower1.genblk1[0].W[0].ys), line:11:10, endln:11:12 + |vpiParent: + \_cont_assign: , line:11:10, endln:11:19 + |vpiName:ys + |vpiFullName:work@constpower1.genblk1[0].W[0].ys + |vpiActual: + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower1.genblk1[0].W[1]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[0]), line:10:2, endln:13:5 + |vpiName:W[1] + |vpiFullName:work@constpower1.genblk1[0].W[1] + |vpiGenScope: + \_gen_scope: (work@constpower1.genblk1[0].W[1]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope_array: (work@constpower1.genblk1[0].W[1]), line:10:30, endln:13:5 + |vpiFullName:work@constpower1.genblk1[0].W[1] + |vpiParameter: + \_parameter: (work@constpower1.genblk1[0].W[1].j), line:10:0 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[0].W[1]), line:10:30, endln:13:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower1.genblk1[0].W[1].j + |vpiContAssign: + \_cont_assign: , line:11:10, endln:11:19 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[0].W[1]), line:10:30, endln:13:5 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower1.genblk1[0].W[1].ys), line:11:10, endln:11:12 + |vpiParent: + \_cont_assign: , line:11:10, endln:11:19 + |vpiName:ys + |vpiFullName:work@constpower1.genblk1[0].W[1].ys + |vpiActual: + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower1.genblk1[1]), line:10:2, endln:13:5 + |vpiParent: + \_module_inst: work@constpower1 (work@constpower1), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:2:1, endln:17:10 + |vpiName:genblk1[1] + |vpiFullName:work@constpower1.genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower1.genblk1[1]), line:10:2, endln:13:5 + |vpiParent: + \_gen_scope_array: (work@constpower1.genblk1[1]), line:10:2, endln:13:5 + |vpiFullName:work@constpower1.genblk1[1] + |vpiParameter: + \_parameter: (work@constpower1.genblk1[1].i), line:9:0 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[1]), line:10:2, endln:13:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower1.genblk1[1].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower1.genblk1[1].W[0]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[1]), line:10:2, endln:13:5 + |vpiName:W[0] + |vpiFullName:work@constpower1.genblk1[1].W[0] + |vpiGenScope: + \_gen_scope: (work@constpower1.genblk1[1].W[0]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope_array: (work@constpower1.genblk1[1].W[0]), line:10:30, endln:13:5 + |vpiFullName:work@constpower1.genblk1[1].W[0] + |vpiParameter: + \_parameter: (work@constpower1.genblk1[1].W[0].j), line:10:0 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[1].W[0]), line:10:30, endln:13:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower1.genblk1[1].W[0].j + |vpiContAssign: + \_cont_assign: , line:11:10, endln:11:19 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[1].W[0]), line:10:30, endln:13:5 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower1.genblk1[1].W[0].ys), line:11:10, endln:11:12 + |vpiParent: + \_cont_assign: , line:11:10, endln:11:19 + |vpiName:ys + |vpiFullName:work@constpower1.genblk1[1].W[0].ys + |vpiActual: + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower1.genblk1[1].W[1]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[1]), line:10:2, endln:13:5 + |vpiName:W[1] + |vpiFullName:work@constpower1.genblk1[1].W[1] + |vpiGenScope: + \_gen_scope: (work@constpower1.genblk1[1].W[1]), line:10:30, endln:13:5 + |vpiParent: + \_gen_scope_array: (work@constpower1.genblk1[1].W[1]), line:10:30, endln:13:5 + |vpiFullName:work@constpower1.genblk1[1].W[1] + |vpiParameter: + \_parameter: (work@constpower1.genblk1[1].W[1].j), line:10:0 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[1].W[1]), line:10:30, endln:13:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower1.genblk1[1].W[1].j + |vpiContAssign: + \_cont_assign: , line:11:10, endln:11:19 + |vpiParent: + \_gen_scope: (work@constpower1.genblk1[1].W[1]), line:10:30, endln:13:5 + |vpiRhs: + \_constant: + |vpiDecompile:2 + |vpiSize:3 + |UINT:2 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower1.genblk1[1].W[1].ys), line:11:10, endln:11:12 + |vpiParent: + \_cont_assign: , line:11:10, endln:11:19 + |vpiName:ys + |vpiFullName:work@constpower1.genblk1[1].W[1].ys + |vpiActual: + \_logic_net: (work@constpower1.ys), line:2:20, endln:2:22 +|uhdmtopModules: +\_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:work@constpower2 + |vpiDefName:work@constpower2 + |vpiTop:1 + |vpiNet: + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiTypespec: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiRange: + \_range: , line:21:8, endln:21:13 + |vpiParent: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiLeftRange: + \_constant: , line:21:9, endln:21:10 + |vpiParent: + \_range: , line:21:8, endln:21:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:21:11, endln:21:12 + |vpiParent: + \_range: , line:21:8, endln:21:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:ys + |vpiFullName:work@constpower2.ys + |vpiNet: + \_logic_net: (work@constpower2.yu), line:19:24, endln:19:26 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiTypespec: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiName:yu + |vpiFullName:work@constpower2.yu + |vpiTopModule:1 + |vpiPort: + \_port: (ys), line:19:20, endln:19:22 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower2.ys), line:19:20, endln:19:22 + |vpiParent: + \_port: (ys), line:19:20, endln:19:22 + |vpiName:ys + |vpiFullName:work@constpower2.ys + |vpiActual: + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 + |vpiTypedef: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiRange: + \_range: , line:21:8, endln:21:13 + |vpiParent: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiLeftRange: + \_constant: , line:21:9, endln:21:10 + |vpiParent: + \_range: , line:21:8, endln:21:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:21:11, endln:21:12 + |vpiParent: + \_range: , line:21:8, endln:21:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiInstance: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiPort: + \_port: (yu), line:19:24, endln:19:26 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower2.yu), line:19:24, endln:19:26 + |vpiParent: + \_port: (yu), line:19:24, endln:19:26 + |vpiName:yu + |vpiFullName:work@constpower2.yu + |vpiActual: + \_logic_net: (work@constpower2.yu), line:19:24, endln:19:26 + |vpiTypedef: + \_logic_typespec: , line:21:8, endln:21:13 + |vpiInstance: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower2.genblk1[0]), line:27:2, endln:30:5 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:genblk1[0] + |vpiFullName:work@constpower2.genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower2.genblk1[0]), line:27:2, endln:30:5 + |vpiParent: + \_gen_scope_array: (work@constpower2.genblk1[0]), line:27:2, endln:30:5 + |vpiFullName:work@constpower2.genblk1[0] + |vpiParameter: + \_parameter: (work@constpower2.genblk1[0].i), line:26:0 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[0]), line:27:2, endln:30:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower2.genblk1[0].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower2.genblk1[0].genblk1[0]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[0]), line:27:2, endln:30:5 + |vpiName:genblk1[0] + |vpiFullName:work@constpower2.genblk1[0].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower2.genblk1[0].genblk1[0]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope_array: (work@constpower2.genblk1[0].genblk1[0]), line:27:30, endln:30:5 + |vpiFullName:work@constpower2.genblk1[0].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower2.genblk1[0].genblk1[0].j), line:27:0 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[0].genblk1[0]), line:27:30, endln:30:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower2.genblk1[0].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:28:10, endln:28:19 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[0].genblk1[0]), line:27:30, endln:30:5 + |vpiRhs: + \_constant: + |vpiDecompile:0 + |vpiSize:3 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower2.genblk1[0].genblk1[0].ys), line:28:10, endln:28:12 + |vpiParent: + \_cont_assign: , line:28:10, endln:28:19 + |vpiName:ys + |vpiFullName:work@constpower2.genblk1[0].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower2.genblk1[0].genblk1[1]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[0]), line:27:2, endln:30:5 + |vpiName:genblk1[1] + |vpiFullName:work@constpower2.genblk1[0].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower2.genblk1[0].genblk1[1]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope_array: (work@constpower2.genblk1[0].genblk1[1]), line:27:30, endln:30:5 + |vpiFullName:work@constpower2.genblk1[0].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower2.genblk1[0].genblk1[1].j), line:27:0 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[0].genblk1[1]), line:27:30, endln:30:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower2.genblk1[0].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:28:10, endln:28:19 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[0].genblk1[1]), line:27:30, endln:30:5 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower2.genblk1[0].genblk1[1].ys), line:28:10, endln:28:12 + |vpiParent: + \_cont_assign: , line:28:10, endln:28:19 + |vpiName:ys + |vpiFullName:work@constpower2.genblk1[0].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower2.genblk1[1]), line:27:2, endln:30:5 + |vpiParent: + \_module_inst: work@constpower2 (work@constpower2), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:19:1, endln:34:10 + |vpiName:genblk1[1] + |vpiFullName:work@constpower2.genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower2.genblk1[1]), line:27:2, endln:30:5 + |vpiParent: + \_gen_scope_array: (work@constpower2.genblk1[1]), line:27:2, endln:30:5 + |vpiFullName:work@constpower2.genblk1[1] + |vpiParameter: + \_parameter: (work@constpower2.genblk1[1].i), line:26:0 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[1]), line:27:2, endln:30:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower2.genblk1[1].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower2.genblk1[1].genblk1[0]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[1]), line:27:2, endln:30:5 + |vpiName:genblk1[0] + |vpiFullName:work@constpower2.genblk1[1].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower2.genblk1[1].genblk1[0]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope_array: (work@constpower2.genblk1[1].genblk1[0]), line:27:30, endln:30:5 + |vpiFullName:work@constpower2.genblk1[1].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower2.genblk1[1].genblk1[0].j), line:27:0 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[1].genblk1[0]), line:27:30, endln:30:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower2.genblk1[1].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:28:10, endln:28:19 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[1].genblk1[0]), line:27:30, endln:30:5 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower2.genblk1[1].genblk1[0].ys), line:28:10, endln:28:12 + |vpiParent: + \_cont_assign: , line:28:10, endln:28:19 + |vpiName:ys + |vpiFullName:work@constpower2.genblk1[1].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower2.genblk1[1].genblk1[1]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[1]), line:27:2, endln:30:5 + |vpiName:genblk1[1] + |vpiFullName:work@constpower2.genblk1[1].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower2.genblk1[1].genblk1[1]), line:27:30, endln:30:5 + |vpiParent: + \_gen_scope_array: (work@constpower2.genblk1[1].genblk1[1]), line:27:30, endln:30:5 + |vpiFullName:work@constpower2.genblk1[1].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower2.genblk1[1].genblk1[1].j), line:27:0 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[1].genblk1[1]), line:27:30, endln:30:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower2.genblk1[1].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:28:10, endln:28:19 + |vpiParent: + \_gen_scope: (work@constpower2.genblk1[1].genblk1[1]), line:27:30, endln:30:5 + |vpiRhs: + \_constant: + |vpiDecompile:2 + |vpiSize:3 + |UINT:2 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower2.genblk1[1].genblk1[1].ys), line:28:10, endln:28:12 + |vpiParent: + \_cont_assign: , line:28:10, endln:28:19 + |vpiName:ys + |vpiFullName:work@constpower2.genblk1[1].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower2.ys), line:19:20, endln:19:22 +|uhdmtopModules: +\_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiName:work@constpower3 + |vpiDefName:work@constpower3 + |vpiTop:1 + |vpiNet: + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 + |vpiParent: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiTypespec: + \_logic_typespec: , line:38:8, endln:38:13 + |vpiRange: + \_range: , line:38:8, endln:38:13 + |vpiParent: + \_logic_typespec: , line:38:8, endln:38:13 + |vpiLeftRange: + \_constant: , line:38:9, endln:38:10 + |vpiParent: + \_range: , line:38:8, endln:38:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:38:11, endln:38:12 + |vpiParent: + \_range: , line:38:8, endln:38:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:ys + |vpiFullName:work@constpower3.ys + |vpiNet: + \_logic_net: (work@constpower3.yu), line:36:24, endln:36:26 + |vpiParent: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiTypespec: + \_logic_typespec: , line:38:8, endln:38:13 + |vpiName:yu + |vpiFullName:work@constpower3.yu + |vpiTopModule:1 + |vpiPort: + \_port: (ys), line:36:20, endln:36:22 + |vpiParent: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower3.ys), line:36:20, endln:36:22 + |vpiParent: + \_port: (ys), line:36:20, endln:36:22 + |vpiName:ys + |vpiFullName:work@constpower3.ys + |vpiActual: + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 + |vpiTypedef: + \_logic_typespec: , line:38:8, endln:38:13 + |vpiRange: + \_range: , line:38:8, endln:38:13 + |vpiParent: + \_logic_typespec: , line:38:8, endln:38:13 + |vpiLeftRange: + \_constant: , line:38:9, endln:38:10 + |vpiParent: + \_range: , line:38:8, endln:38:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:38:11, endln:38:12 + |vpiParent: + \_range: , line:38:8, endln:38:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiInstance: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiPort: + \_port: (yu), line:36:24, endln:36:26 + |vpiParent: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower3.yu), line:36:24, endln:36:26 + |vpiParent: + \_port: (yu), line:36:24, endln:36:26 + |vpiName:yu + |vpiFullName:work@constpower3.yu + |vpiActual: + \_logic_net: (work@constpower3.yu), line:36:24, endln:36:26 + |vpiTypedef: + \_logic_typespec: , line:38:8, endln:38:13 + |vpiInstance: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower3.genblk1[0]), line:43:30, endln:47:5 + |vpiParent: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiName:genblk1[0] + |vpiFullName:work@constpower3.genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower3.genblk1[0]), line:43:30, endln:47:5 + |vpiParent: + \_gen_scope_array: (work@constpower3.genblk1[0]), line:43:30, endln:47:5 + |vpiFullName:work@constpower3.genblk1[0] + |vpiParameter: + \_parameter: (work@constpower3.genblk1[0].i), line:43:0 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[0]), line:43:30, endln:47:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower3.genblk1[0].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower3.genblk1[0].genblk1[0]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[0]), line:43:30, endln:47:5 + |vpiName:genblk1[0] + |vpiFullName:work@constpower3.genblk1[0].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower3.genblk1[0].genblk1[0]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope_array: (work@constpower3.genblk1[0].genblk1[0]), line:45:3, endln:45:20 + |vpiFullName:work@constpower3.genblk1[0].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower3.genblk1[0].genblk1[0].j), line:44:0 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[0].genblk1[0]), line:45:3, endln:45:20 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower3.genblk1[0].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:45:10, endln:45:19 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[0].genblk1[0]), line:45:3, endln:45:20 + |vpiRhs: + \_constant: + |vpiDecompile:0 + |vpiSize:3 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower3.genblk1[0].genblk1[0].ys), line:45:10, endln:45:12 + |vpiParent: + \_cont_assign: , line:45:10, endln:45:19 + |vpiName:ys + |vpiFullName:work@constpower3.genblk1[0].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower3.genblk1[0].genblk1[1]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[0]), line:43:30, endln:47:5 + |vpiName:genblk1[1] + |vpiFullName:work@constpower3.genblk1[0].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower3.genblk1[0].genblk1[1]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope_array: (work@constpower3.genblk1[0].genblk1[1]), line:45:3, endln:45:20 + |vpiFullName:work@constpower3.genblk1[0].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower3.genblk1[0].genblk1[1].j), line:44:0 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[0].genblk1[1]), line:45:3, endln:45:20 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower3.genblk1[0].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:45:10, endln:45:19 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[0].genblk1[1]), line:45:3, endln:45:20 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower3.genblk1[0].genblk1[1].ys), line:45:10, endln:45:12 + |vpiParent: + \_cont_assign: , line:45:10, endln:45:19 + |vpiName:ys + |vpiFullName:work@constpower3.genblk1[0].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower3.genblk1[1]), line:43:30, endln:47:5 + |vpiParent: + \_module_inst: work@constpower3 (work@constpower3), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:36:1, endln:51:10 + |vpiName:genblk1[1] + |vpiFullName:work@constpower3.genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower3.genblk1[1]), line:43:30, endln:47:5 + |vpiParent: + \_gen_scope_array: (work@constpower3.genblk1[1]), line:43:30, endln:47:5 + |vpiFullName:work@constpower3.genblk1[1] + |vpiParameter: + \_parameter: (work@constpower3.genblk1[1].i), line:43:0 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[1]), line:43:30, endln:47:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower3.genblk1[1].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower3.genblk1[1].genblk1[0]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[1]), line:43:30, endln:47:5 + |vpiName:genblk1[0] + |vpiFullName:work@constpower3.genblk1[1].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower3.genblk1[1].genblk1[0]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope_array: (work@constpower3.genblk1[1].genblk1[0]), line:45:3, endln:45:20 + |vpiFullName:work@constpower3.genblk1[1].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower3.genblk1[1].genblk1[0].j), line:44:0 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[1].genblk1[0]), line:45:3, endln:45:20 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower3.genblk1[1].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:45:10, endln:45:19 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[1].genblk1[0]), line:45:3, endln:45:20 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower3.genblk1[1].genblk1[0].ys), line:45:10, endln:45:12 + |vpiParent: + \_cont_assign: , line:45:10, endln:45:19 + |vpiName:ys + |vpiFullName:work@constpower3.genblk1[1].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower3.genblk1[1].genblk1[1]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[1]), line:43:30, endln:47:5 + |vpiName:genblk1[1] + |vpiFullName:work@constpower3.genblk1[1].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower3.genblk1[1].genblk1[1]), line:45:3, endln:45:20 + |vpiParent: + \_gen_scope_array: (work@constpower3.genblk1[1].genblk1[1]), line:45:3, endln:45:20 + |vpiFullName:work@constpower3.genblk1[1].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower3.genblk1[1].genblk1[1].j), line:44:0 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[1].genblk1[1]), line:45:3, endln:45:20 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower3.genblk1[1].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:45:10, endln:45:19 + |vpiParent: + \_gen_scope: (work@constpower3.genblk1[1].genblk1[1]), line:45:3, endln:45:20 + |vpiRhs: + \_constant: + |vpiDecompile:2 + |vpiSize:3 + |UINT:2 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower3.genblk1[1].genblk1[1].ys), line:45:10, endln:45:12 + |vpiParent: + \_cont_assign: , line:45:10, endln:45:19 + |vpiName:ys + |vpiFullName:work@constpower3.genblk1[1].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower3.ys), line:36:20, endln:36:22 +|uhdmtopModules: +\_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:work@constpower4 + |vpiDefName:work@constpower4 + |vpiTop:1 + |vpiNet: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiTypespec: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiRange: + \_range: , line:55:8, endln:55:13 + |vpiParent: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiLeftRange: + \_constant: , line:55:9, endln:55:10 + |vpiParent: + \_range: , line:55:8, endln:55:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:55:11, endln:55:12 + |vpiParent: + \_range: , line:55:8, endln:55:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:ys + |vpiFullName:work@constpower4.ys + |vpiNet: + \_logic_net: (work@constpower4.yu), line:53:24, endln:53:26 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiTypespec: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiName:yu + |vpiFullName:work@constpower4.yu + |vpiTopModule:1 + |vpiPort: + \_port: (ys), line:53:20, endln:53:22 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower4.ys), line:53:20, endln:53:22 + |vpiParent: + \_port: (ys), line:53:20, endln:53:22 + |vpiName:ys + |vpiFullName:work@constpower4.ys + |vpiActual: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 + |vpiTypedef: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiRange: + \_range: , line:55:8, endln:55:13 + |vpiParent: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiLeftRange: + \_constant: , line:55:9, endln:55:10 + |vpiParent: + \_range: , line:55:8, endln:55:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:55:11, endln:55:12 + |vpiParent: + \_range: , line:55:8, endln:55:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiInstance: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiPort: + \_port: (yu), line:53:24, endln:53:26 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower4.yu), line:53:24, endln:53:26 + |vpiParent: + \_port: (yu), line:53:24, endln:53:26 + |vpiName:yu + |vpiFullName:work@constpower4.yu + |vpiActual: + \_logic_net: (work@constpower4.yu), line:53:24, endln:53:26 + |vpiTypedef: + \_logic_typespec: , line:55:8, endln:55:13 + |vpiInstance: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower4.genblk1[0]), line:60:30, endln:65:12 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:genblk1[0] + |vpiFullName:work@constpower4.genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower4.genblk1[0]), line:60:30, endln:65:12 + |vpiParent: + \_gen_scope_array: (work@constpower4.genblk1[0]), line:60:30, endln:65:12 + |vpiFullName:work@constpower4.genblk1[0] + |vpiParameter: + \_parameter: (work@constpower4.genblk1[0].i), line:60:0 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[0]), line:60:30, endln:65:12 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower4.genblk1[0].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower4.genblk1[0].genblk1[0]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[0]), line:60:30, endln:65:12 + |vpiName:genblk1[0] + |vpiFullName:work@constpower4.genblk1[0].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower4.genblk1[0].genblk1[0]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope_array: (work@constpower4.genblk1[0].genblk1[0]), line:61:30, endln:64:5 + |vpiFullName:work@constpower4.genblk1[0].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower4.genblk1[0].genblk1[0].j), line:61:0 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[0].genblk1[0]), line:61:30, endln:64:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower4.genblk1[0].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:62:10, endln:62:19 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[0].genblk1[0]), line:61:30, endln:64:5 + |vpiRhs: + \_constant: + |vpiDecompile:0 + |vpiSize:3 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower4.genblk1[0].genblk1[0].ys), line:62:10, endln:62:12 + |vpiParent: + \_cont_assign: , line:62:10, endln:62:19 + |vpiName:ys + |vpiFullName:work@constpower4.genblk1[0].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower4.genblk1[0].genblk1[1]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[0]), line:60:30, endln:65:12 + |vpiName:genblk1[1] + |vpiFullName:work@constpower4.genblk1[0].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower4.genblk1[0].genblk1[1]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope_array: (work@constpower4.genblk1[0].genblk1[1]), line:61:30, endln:64:5 + |vpiFullName:work@constpower4.genblk1[0].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower4.genblk1[0].genblk1[1].j), line:61:0 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[0].genblk1[1]), line:61:30, endln:64:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower4.genblk1[0].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:62:10, endln:62:19 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[0].genblk1[1]), line:61:30, endln:64:5 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower4.genblk1[0].genblk1[1].ys), line:62:10, endln:62:12 + |vpiParent: + \_cont_assign: , line:62:10, endln:62:19 + |vpiName:ys + |vpiFullName:work@constpower4.genblk1[0].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower4.genblk1[1]), line:60:30, endln:65:12 + |vpiParent: + \_module_inst: work@constpower4 (work@constpower4), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:53:1, endln:69:10 + |vpiName:genblk1[1] + |vpiFullName:work@constpower4.genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower4.genblk1[1]), line:60:30, endln:65:12 + |vpiParent: + \_gen_scope_array: (work@constpower4.genblk1[1]), line:60:30, endln:65:12 + |vpiFullName:work@constpower4.genblk1[1] + |vpiParameter: + \_parameter: (work@constpower4.genblk1[1].i), line:60:0 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[1]), line:60:30, endln:65:12 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower4.genblk1[1].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower4.genblk1[1].genblk1[0]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[1]), line:60:30, endln:65:12 + |vpiName:genblk1[0] + |vpiFullName:work@constpower4.genblk1[1].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower4.genblk1[1].genblk1[0]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope_array: (work@constpower4.genblk1[1].genblk1[0]), line:61:30, endln:64:5 + |vpiFullName:work@constpower4.genblk1[1].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower4.genblk1[1].genblk1[0].j), line:61:0 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[1].genblk1[0]), line:61:30, endln:64:5 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower4.genblk1[1].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:62:10, endln:62:19 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[1].genblk1[0]), line:61:30, endln:64:5 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower4.genblk1[1].genblk1[0].ys), line:62:10, endln:62:12 + |vpiParent: + \_cont_assign: , line:62:10, endln:62:19 + |vpiName:ys + |vpiFullName:work@constpower4.genblk1[1].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower4.genblk1[1].genblk1[1]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[1]), line:60:30, endln:65:12 + |vpiName:genblk1[1] + |vpiFullName:work@constpower4.genblk1[1].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower4.genblk1[1].genblk1[1]), line:61:30, endln:64:5 + |vpiParent: + \_gen_scope_array: (work@constpower4.genblk1[1].genblk1[1]), line:61:30, endln:64:5 + |vpiFullName:work@constpower4.genblk1[1].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower4.genblk1[1].genblk1[1].j), line:61:0 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[1].genblk1[1]), line:61:30, endln:64:5 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower4.genblk1[1].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:62:10, endln:62:19 + |vpiParent: + \_gen_scope: (work@constpower4.genblk1[1].genblk1[1]), line:61:30, endln:64:5 + |vpiRhs: + \_constant: + |vpiDecompile:2 + |vpiSize:3 + |UINT:2 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower4.genblk1[1].genblk1[1].ys), line:62:10, endln:62:12 + |vpiParent: + \_cont_assign: , line:62:10, endln:62:19 + |vpiName:ys + |vpiFullName:work@constpower4.genblk1[1].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower4.ys), line:53:20, endln:53:22 +|uhdmtopModules: +\_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:work@constpower5 + |vpiDefName:work@constpower5 + |vpiTop:1 + |vpiNet: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiTypespec: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiRange: + \_range: , line:74:8, endln:74:13 + |vpiParent: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiLeftRange: + \_constant: , line:74:9, endln:74:10 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:74:11, endln:74:12 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiName:ys + |vpiFullName:work@constpower5.ys + |vpiNet: + \_logic_net: (work@constpower5.yu), line:72:24, endln:72:26 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiTypespec: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiName:yu + |vpiFullName:work@constpower5.yu + |vpiTopModule:1 + |vpiPort: + \_port: (ys), line:72:20, endln:72:22 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:ys + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiParent: + \_port: (ys), line:72:20, endln:72:22 + |vpiName:ys + |vpiFullName:work@constpower5.ys + |vpiActual: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiTypedef: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiRange: + \_range: , line:74:8, endln:74:13 + |vpiParent: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiLeftRange: + \_constant: , line:74:9, endln:74:10 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:74:11, endln:74:12 + |vpiParent: + \_range: , line:74:8, endln:74:13 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiInstance: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiPort: + \_port: (yu), line:72:24, endln:72:26 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:yu + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@constpower5.yu), line:72:24, endln:72:26 + |vpiParent: + \_port: (yu), line:72:24, endln:72:26 + |vpiName:yu + |vpiFullName:work@constpower5.yu + |vpiActual: + \_logic_net: (work@constpower5.yu), line:72:24, endln:72:26 + |vpiTypedef: + \_logic_typespec: , line:74:8, endln:74:13 + |vpiInstance: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower5.genblk1[0]), line:80:2, endln:81:20 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:genblk1[0] + |vpiFullName:work@constpower5.genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower5.genblk1[0]), line:80:2, endln:81:20 + |vpiParent: + \_gen_scope_array: (work@constpower5.genblk1[0]), line:80:2, endln:81:20 + |vpiFullName:work@constpower5.genblk1[0] + |vpiParameter: + \_parameter: (work@constpower5.genblk1[0].i), line:79:0 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[0]), line:80:2, endln:81:20 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower5.genblk1[0].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower5.genblk1[0].genblk1[0]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[0]), line:80:2, endln:81:20 + |vpiName:genblk1[0] + |vpiFullName:work@constpower5.genblk1[0].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower5.genblk1[0].genblk1[0]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope_array: (work@constpower5.genblk1[0].genblk1[0]), line:81:3, endln:81:20 + |vpiFullName:work@constpower5.genblk1[0].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower5.genblk1[0].genblk1[0].j), line:80:0 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[0].genblk1[0]), line:81:3, endln:81:20 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower5.genblk1[0].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:81:10, endln:81:19 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[0].genblk1[0]), line:81:3, endln:81:20 + |vpiRhs: + \_constant: + |vpiDecompile:0 + |vpiSize:3 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower5.genblk1[0].genblk1[0].ys), line:81:10, endln:81:12 + |vpiParent: + \_cont_assign: , line:81:10, endln:81:19 + |vpiName:ys + |vpiFullName:work@constpower5.genblk1[0].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower5.genblk1[0].genblk1[1]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[0]), line:80:2, endln:81:20 + |vpiName:genblk1[1] + |vpiFullName:work@constpower5.genblk1[0].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower5.genblk1[0].genblk1[1]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope_array: (work@constpower5.genblk1[0].genblk1[1]), line:81:3, endln:81:20 + |vpiFullName:work@constpower5.genblk1[0].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower5.genblk1[0].genblk1[1].j), line:80:0 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[0].genblk1[1]), line:81:3, endln:81:20 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower5.genblk1[0].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:81:10, endln:81:19 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[0].genblk1[1]), line:81:3, endln:81:20 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower5.genblk1[0].genblk1[1].ys), line:81:10, endln:81:12 + |vpiParent: + \_cont_assign: , line:81:10, endln:81:19 + |vpiName:ys + |vpiFullName:work@constpower5.genblk1[0].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower5.genblk1[1]), line:80:2, endln:81:20 + |vpiParent: + \_module_inst: work@constpower5 (work@constpower5), file:${SURELOG_DIR}/tests/DoubleLoop/dut.sv, line:72:1, endln:88:10 + |vpiName:genblk1[1] + |vpiFullName:work@constpower5.genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower5.genblk1[1]), line:80:2, endln:81:20 + |vpiParent: + \_gen_scope_array: (work@constpower5.genblk1[1]), line:80:2, endln:81:20 + |vpiFullName:work@constpower5.genblk1[1] + |vpiParameter: + \_parameter: (work@constpower5.genblk1[1].i), line:79:0 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[1]), line:80:2, endln:81:20 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:i + |vpiFullName:work@constpower5.genblk1[1].i + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower5.genblk1[1].genblk1[0]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[1]), line:80:2, endln:81:20 + |vpiName:genblk1[0] + |vpiFullName:work@constpower5.genblk1[1].genblk1[0] + |vpiGenScope: + \_gen_scope: (work@constpower5.genblk1[1].genblk1[0]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope_array: (work@constpower5.genblk1[1].genblk1[0]), line:81:3, endln:81:20 + |vpiFullName:work@constpower5.genblk1[1].genblk1[0] + |vpiParameter: + \_parameter: (work@constpower5.genblk1[1].genblk1[0].j), line:80:0 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[1].genblk1[0]), line:81:3, endln:81:20 + |UINT:0 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower5.genblk1[1].genblk1[0].j + |vpiContAssign: + \_cont_assign: , line:81:10, endln:81:19 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[1].genblk1[0]), line:81:3, endln:81:20 + |vpiRhs: + \_constant: + |vpiDecompile:1 + |vpiSize:3 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower5.genblk1[1].genblk1[0].ys), line:81:10, endln:81:12 + |vpiParent: + \_cont_assign: , line:81:10, endln:81:19 + |vpiName:ys + |vpiFullName:work@constpower5.genblk1[1].genblk1[0].ys + |vpiActual: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 + |vpiGenScopeArray: + \_gen_scope_array: (work@constpower5.genblk1[1].genblk1[1]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[1]), line:80:2, endln:81:20 + |vpiName:genblk1[1] + |vpiFullName:work@constpower5.genblk1[1].genblk1[1] + |vpiGenScope: + \_gen_scope: (work@constpower5.genblk1[1].genblk1[1]), line:81:3, endln:81:20 + |vpiParent: + \_gen_scope_array: (work@constpower5.genblk1[1].genblk1[1]), line:81:3, endln:81:20 + |vpiFullName:work@constpower5.genblk1[1].genblk1[1] + |vpiParameter: + \_parameter: (work@constpower5.genblk1[1].genblk1[1].j), line:80:0 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[1].genblk1[1]), line:81:3, endln:81:20 + |UINT:1 + |vpiTypespec: + \_int_typespec: + |vpiLocalParam:1 + |vpiName:j + |vpiFullName:work@constpower5.genblk1[1].genblk1[1].j + |vpiContAssign: + \_cont_assign: , line:81:10, endln:81:19 + |vpiParent: + \_gen_scope: (work@constpower5.genblk1[1].genblk1[1]), line:81:3, endln:81:20 + |vpiRhs: + \_constant: + |vpiDecompile:2 + |vpiSize:3 + |UINT:2 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@constpower5.genblk1[1].genblk1[1].ys), line:81:10, endln:81:12 + |vpiParent: + \_cont_assign: , line:81:10, endln:81:19 + |vpiName:ys + |vpiFullName:work@constpower5.genblk1[1].genblk1[1].ys + |vpiActual: + \_logic_net: (work@constpower5.ys), line:72:20, endln:72:22 =================== [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 -[WARNING] : 1 -[ NOTE] : 6 +[WARNING] : 5 +[ NOTE] : 15 -[roundtrip]: ${SURELOG_DIR}/tests/DoubleLoop/dut.sv | ${SURELOG_DIR}/build/regression/DoubleLoop/roundtrip/dut_000.sv | 8 | 17 | \ No newline at end of file +[roundtrip]: ${SURELOG_DIR}/tests/DoubleLoop/dut.sv | ${SURELOG_DIR}/build/regression/DoubleLoop/roundtrip/dut_000.sv | 40 | 88 | \ No newline at end of file diff --git a/tests/DoubleLoop/dut.sv b/tests/DoubleLoop/dut.sv index f978642ce2..2b996e77d0 100644 --- a/tests/DoubleLoop/dut.sv +++ b/tests/DoubleLoop/dut.sv @@ -1,5 +1,5 @@ -module constpower(ys, yu); +module constpower1(ys, yu); output [2:0] ys, yu; @@ -16,45 +16,73 @@ endgenerate endmodule -/* +module constpower2(ys, yu); -interface rggen_register_if #( -); - - - logic valid; - logic [31:0] value; +output [2:0] ys, yu; - modport register ( - input valid, - output value - ); +genvar i, j; - modport monitor ( - input valid, - input value - ); -endinterface +generate + for (i = 0; i < 2; i = i+1) + for (j = 0; j < 2; j = j+1) begin + assign ys= i + j; + + end +endgenerate -module rggen_bit_field (input logic [31:0] o_value); endmodule -module top(); - rggen_register_if register_if[1](); +module constpower3(ys, yu); + +output [2:0] ys, yu; + +genvar i, j; +generate + for (i = 0; i < 2; i = i+1) begin + for (j = 0; j < 2; j = j+1) + assign ys= i + j; + + end - // assign o = register_if[0].value[8+:1]; - - rggen_bit_field i1 ( - .o_value (register_if) - ); +endgenerate - rggen_bit_field u_bit_field ( - .o_value (register_if[0].value[8+:1]) - ); - +endmodule // constpower3 -endmodule +module constpower4(ys, yu); + +output [2:0] ys, yu; + +genvar i, j; + +generate + for (i = 0; i < 2; i = i+1) begin + for (j = 0; j < 2; j = j+1) begin + assign ys= i + j; + + end + end + +endgenerate + +endmodule // constpower4 + + +module constpower5(ys, yu); + +output [2:0] ys, yu; + +genvar i, j; + +generate + for (i = 0; i < 2; i = i+1) + for (j = 0; j < 2; j = j+1) + assign ys= i + j; + + + + +endgenerate -*/ \ No newline at end of file +endmodule // constpower5 diff --git a/third_party/UHDM b/third_party/UHDM index 8c7074b6c9..65cba5da32 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 8c7074b6c952b17d8b6e0a89a679cce4448e9c8d +Subproject commit 65cba5da32483e93237b68a023595190480ac5e7 diff --git a/third_party/googletest b/third_party/googletest index e7fd109b53..89b25572db 160000 --- a/third_party/googletest +++ b/third_party/googletest @@ -1 +1 @@ -Subproject commit e7fd109b536a8e22cc9e8aad84b35221c3d36042 +Subproject commit 89b25572dbd7668499d2cfd01dea905f8c44e019 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 28a0354cce..9dc21024ce 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -134,22 +134,22 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): -- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 11_ifu_bp_ctl.sv +[ 6%] Generating 10_lsu_bus_intf.sv [ 12%] Generating 12_beh_lib.sv -[ 18%] Generating 13_ifu_mem_ctl.sv -[ 25%] Generating 10_lsu_bus_intf.sv +[ 18%] Generating 11_ifu_bp_ctl.sv +[ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv [ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv -[ 50%] Generating 2_ahb_to_axi4.sv -[ 56%] Generating 1_lsu_stbuf.sv +[ 50%] Generating 1_lsu_stbuf.sv +[ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv -[ 93%] Generating 9_tb_top.sv -[100%] Generating 8_ifu_aln_ctl.sv +[ 93%] Generating 8_ifu_aln_ctl.sv +[100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".