From c451499aee4fe6da672746c9b5b736a9d8d6de48 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Sun, 30 Jul 2023 16:18:32 -0700 Subject: [PATCH] rggen support --- third_party/UHDM | 2 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 10 +- third_party/tests/rggen/Rggen.log | 9543 +++++++++++++++++ third_party/tests/rggen/Rggen.sl | 1 + third_party/tests/rggen/rggen-sample/LICENSE | 21 + .../tests/rggen/rggen-sample/block_0.h | 330 + .../tests/rggen/rggen-sample/block_0.md | 268 + .../tests/rggen/rggen-sample/block_0.rb | 186 + .../tests/rggen/rggen-sample/block_0.sv | 2302 ++++ .../tests/rggen/rggen-sample/block_0.toml | 443 + .../tests/rggen/rggen-sample/block_0.v | 2748 +++++ .../tests/rggen/rggen-sample/block_0.vh | 296 + .../tests/rggen/rggen-sample/block_0.vhd | 3121 ++++++ .../tests/rggen/rggen-sample/block_0.xlsx | Bin 0 -> 14656 bytes .../tests/rggen/rggen-sample/block_0.yml | 167 + .../rggen/rggen-sample/block_0_ral_pkg.sv | 321 + .../rggen/rggen-sample/block_0_rtl_pkg.sv | 267 + .../tests/rggen/rggen-sample/block_1.h | 111 + .../tests/rggen/rggen-sample/block_1.md | 105 + .../tests/rggen/rggen-sample/block_1.rb | 76 + .../tests/rggen/rggen-sample/block_1.sv | 421 + .../tests/rggen/rggen-sample/block_1.toml | 100 + .../tests/rggen/rggen-sample/block_1.v | 558 + .../tests/rggen/rggen-sample/block_1.vh | 73 + .../tests/rggen/rggen-sample/block_1.vhd | 645 ++ .../tests/rggen/rggen-sample/block_1.yml | 65 + .../rggen/rggen-sample/block_1_ral_pkg.sv | 139 + .../rggen/rggen-sample/block_1_rtl_pkg.sv | 48 + .../tests/rggen/rggen-sample/config.json | 5 + .../tests/rggen/rggen-sample/config.toml | 3 + .../tests/rggen/rggen-sample/config.yml | 3 + .../tests/rggen/rggen-sample/uart_csr.h | 195 + .../tests/rggen/rggen-sample/uart_csr.md | 217 + .../tests/rggen/rggen-sample/uart_csr.sv | 1467 +++ .../tests/rggen/rggen-sample/uart_csr.v | 1795 ++++ .../tests/rggen/rggen-sample/uart_csr.vh | 171 + .../tests/rggen/rggen-sample/uart_csr.vhd | 2029 ++++ .../tests/rggen/rggen-sample/uart_csr.yml | 326 + .../rggen/rggen-sample/uart_csr_ral_pkg.sv | 224 + .../rggen/rggen-sample/uart_csr_rtl_pkg.sv | 170 + .../rggen-sv-rtl/.github/workflows/svlint.yml | 18 + .../tests/rggen/rggen-sv-rtl/.svlint.toml | 30 + third_party/tests/rggen/rggen-sv-rtl/LICENSE | 21 + .../tests/rggen/rggen-sv-rtl/compile.f | 25 + .../tests/rggen/rggen-sv-rtl/compile.rb | 30 + .../rggen/rggen-sv-rtl/compile_backdoor.f | 3 + .../rggen/rggen-sv-rtl/compile_backdoor.rb | 5 + .../rggen-sv-rtl/rggen_adapter_common.sv | 192 + .../rggen-sv-rtl/rggen_address_decoder.sv | 63 + .../rggen/rggen-sv-rtl/rggen_apb_adapter.sv | 64 + .../rggen/rggen-sv-rtl/rggen_apb_bridge.sv | 44 + .../tests/rggen/rggen-sv-rtl/rggen_apb_if.sv | 54 + .../rggen-sv-rtl/rggen_axi4lite_adapter.sv | 189 + .../rggen-sv-rtl/rggen_axi4lite_bridge.sv | 65 + .../rggen/rggen-sv-rtl/rggen_axi4lite_if.sv | 111 + .../rggen_axi4lite_skid_buffer.sv | 175 + .../rggen/rggen-sv-rtl/rggen_backdoor.sv | 44 + .../rggen/rggen-sv-rtl/rggen_backdoor_if.sv | 103 + .../rggen/rggen-sv-rtl/rggen_backdoor_pkg.sv | 78 + .../rggen/rggen-sv-rtl/rggen_bit_field.sv | 279 + .../rggen/rggen-sv-rtl/rggen_bit_field_if.sv | 37 + .../rggen-sv-rtl/rggen_bit_field_w01trg.sv | 42 + .../tests/rggen/rggen-sv-rtl/rggen_bus_if.sv | 48 + .../rggen-sv-rtl/rggen_default_register.sv | 30 + .../rggen-sv-rtl/rggen_external_register.sv | 74 + .../rggen-sv-rtl/rggen_indirect_register.sv | 36 + .../tests/rggen/rggen-sv-rtl/rggen_mux.sv | 33 + .../rggen/rggen-sv-rtl/rggen_or_reducer.sv | 103 + .../rggen-sv-rtl/rggen_register_common.sv | 140 + .../rggen/rggen-sv-rtl/rggen_register_if.sv | 56 + .../tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv | 48 + .../rggen-sv-rtl/rggen_wishbone_adapter.sv | 138 + .../rggen-sv-rtl/rggen_wishbone_bridge.sv | 55 + .../rggen/rggen-sv-rtl/rggen_wishbone_if.sv | 46 + .../rggen/tests/generated/rggen/rggen.sv | 292 + 75 files changed, 31737 insertions(+), 6 deletions(-) create mode 100644 third_party/tests/rggen/Rggen.log create mode 100644 third_party/tests/rggen/Rggen.sl create mode 100644 third_party/tests/rggen/rggen-sample/LICENSE create mode 100644 third_party/tests/rggen/rggen-sample/block_0.h create mode 100644 third_party/tests/rggen/rggen-sample/block_0.md create mode 100644 third_party/tests/rggen/rggen-sample/block_0.rb create mode 100644 third_party/tests/rggen/rggen-sample/block_0.sv create mode 100644 third_party/tests/rggen/rggen-sample/block_0.toml create mode 100644 third_party/tests/rggen/rggen-sample/block_0.v create mode 100644 third_party/tests/rggen/rggen-sample/block_0.vh create mode 100644 third_party/tests/rggen/rggen-sample/block_0.vhd create mode 100644 third_party/tests/rggen/rggen-sample/block_0.xlsx create mode 100644 third_party/tests/rggen/rggen-sample/block_0.yml create mode 100644 third_party/tests/rggen/rggen-sample/block_0_ral_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sample/block_0_rtl_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sample/block_1.h create mode 100644 third_party/tests/rggen/rggen-sample/block_1.md create mode 100644 third_party/tests/rggen/rggen-sample/block_1.rb create mode 100644 third_party/tests/rggen/rggen-sample/block_1.sv create mode 100644 third_party/tests/rggen/rggen-sample/block_1.toml create mode 100644 third_party/tests/rggen/rggen-sample/block_1.v create mode 100644 third_party/tests/rggen/rggen-sample/block_1.vh create mode 100644 third_party/tests/rggen/rggen-sample/block_1.vhd create mode 100644 third_party/tests/rggen/rggen-sample/block_1.yml create mode 100644 third_party/tests/rggen/rggen-sample/block_1_ral_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sample/block_1_rtl_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sample/config.json create mode 100644 third_party/tests/rggen/rggen-sample/config.toml create mode 100644 third_party/tests/rggen/rggen-sample/config.yml create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr.h create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr.md create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr.sv create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr.v create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr.vh create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr.vhd create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr.yml create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr_ral_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sample/uart_csr_rtl_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/.github/workflows/svlint.yml create mode 100644 third_party/tests/rggen/rggen-sv-rtl/.svlint.toml create mode 100644 third_party/tests/rggen/rggen-sv-rtl/LICENSE create mode 100644 third_party/tests/rggen/rggen-sv-rtl/compile.f create mode 100644 third_party/tests/rggen/rggen-sv-rtl/compile.rb create mode 100644 third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.f create mode 100644 third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.rb create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_adapter.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_bridge.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_if.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_skid_buffer.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_if.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_adapter.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_bridge.sv create mode 100644 third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_if.sv create mode 100644 third_party/tests/rggen/tests/generated/rggen/rggen.sv diff --git a/third_party/UHDM b/third_party/UHDM index 7d6dc1b923..c44abd6ff5 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 7d6dc1b92332537c8f76ccf366fb262e9cf7be30 +Subproject commit c44abd6ff5bfa335cc2cb6b65d596a1d0f35a9e1 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 2d63886ccc..6961d2f705 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -139,16 +139,16 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): [ 18%] Generating 12_beh_lib.sv [ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv -[ 37%] Generating 15_exu.sv -[ 43%] Generating 16_dec_decode_ctl.sv +[ 37%] Generating 16_dec_decode_ctl.sv [ 50%] Generating 1_lsu_stbuf.sv +[ 50%] Generating 15_exu.sv [ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv -[ 81%] Generating 8_ifu_aln_ctl.sv -[ 87%] Generating 7_axi4_to_ahb.sv -[ 93%] Generating 6_dbg.sv +[ 81%] Generating 7_axi4_to_ahb.sv +[ 87%] Generating 6_dbg.sv +[ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 diff --git a/third_party/tests/rggen/Rggen.log b/third_party/tests/rggen/Rggen.log new file mode 100644 index 0000000000..00c12c3e45 --- /dev/null +++ b/third_party/tests/rggen/Rggen.log @@ -0,0 +1,9543 @@ +[INF:CM0023] Creating log file ${SURELOG_DIR}/build/regression/Rggen/slpp_all/surelog.log. + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/rggen/tests/generated/rggen/rggen.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/rggen/tests/generated/rggen/rggen.sv". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv:1:1: No timescale set for "rggen_rtl_pkg". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:1:1: No timescale set for "rggen_or_reducer". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:1:1: No timescale set for "rggen_mux". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv:1:1: No timescale set for "rggen_bit_field_if". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:1:1: No timescale set for "rggen_bit_field". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv:1:1: No timescale set for "rggen_bit_field_w01trg". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv:1:1: No timescale set for "rggen_register_if". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:1:1: No timescale set for "rggen_address_decoder". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:1:1: No timescale set for "rggen_register_common". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv:1:1: No timescale set for "rggen_default_register". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv:1:1: No timescale set for "rggen_external_register". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv:1:1: No timescale set for "rggen_indirect_register". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv:1:1: No timescale set for "rggen_bus_if". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:1:1: No timescale set for "rggen_adapter_common". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv:1:1: No timescale set for "rggen_apb_if". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv:1:1: No timescale set for "rggen_apb_adapter". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv:1:1: No timescale set for "rggen_apb_bridge". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:22:1: No timescale set for "block_0". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:22:1: No timescale set for "block_1". + +[WRN:PA0205] ${SURELOG_DIR}/third_party/tests/rggen/tests/generated/rggen/rggen.sv:11:1: No timescale set for "rggen". + +[INF:CP0300] Compilation... + +[INF:CP0301] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv:1:1: Compile package "rggen_rtl_pkg". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:22:1: Compile module "work@block_0". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:22:1: Compile module "work@block_1". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/tests/generated/rggen/rggen.sv:11:1: Compile module "work@rggen". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:1:1: Compile module "work@rggen_adapter_common". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:1:1: Compile module "work@rggen_address_decoder". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv:1:1: Compile module "work@rggen_apb_adapter". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv:1:1: Compile module "work@rggen_apb_bridge". + +[INF:CP0304] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv:1:1: Compile interface "work@rggen_apb_if". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:1:1: Compile module "work@rggen_bit_field". + +[INF:CP0304] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv:1:1: Compile interface "work@rggen_bit_field_if". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv:1:1: Compile module "work@rggen_bit_field_w01trg". + +[INF:CP0304] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv:1:1: Compile interface "work@rggen_bus_if". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv:1:1: Compile module "work@rggen_default_register". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv:1:1: Compile module "work@rggen_external_register". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv:1:1: Compile module "work@rggen_indirect_register". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:1:1: Compile module "work@rggen_mux". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:1:1: Compile module "work@rggen_or_reducer". + +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:1:1: Compile module "work@rggen_register_common". + +[INF:CP0304] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv:1:1: Compile interface "work@rggen_register_if". + +[INF:CP0302] Compile class "work@mailbox". + +[INF:CP0302] Compile class "work@process". + +[INF:CP0302] Compile class "work@semaphore". + +[INF:EL0526] Design Elaboration... + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:67:24: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request_slicer". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_request[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.g_response[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.u_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.u_adapter.u_adapter_common.u_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:165:19: Compile generate block "work@rggen.u_block_0.g_register_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_0.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_0.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_0.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_0.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_0.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:182:12: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:208:12: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:234:12: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:260:12: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:207:42: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:286:12: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_4". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_4.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_4.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_4.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_4.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_4.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:311:12: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_5". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_5.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_5.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_5.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_5.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_5.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:336:12: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_6". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_6.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_6.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_6.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_6.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_0.g_bit_field_6.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:363:19: Compile generate block "work@rggen.u_block_0.g_register_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[1].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[2].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[3].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_1.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_1.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_1.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:380:12: Compile generate block "work@rggen.u_block_0.g_register_1.g_register_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_1.g_register_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_1.g_register_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_1.g_register_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_1.g_register_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_1.g_register_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:407:19: Compile generate block "work@rggen.u_block_0.g_register_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_2.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_2.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_2.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:55:7: Compile generate block "work@rggen.u_block_0.g_register_2.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_2.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:424:12: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:266:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:449:12: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:266:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:474:12: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:499:12: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_2.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:525:19: Compile generate block "work@rggen.u_block_0.g_register_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_3.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_3.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_3.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:57:10: Compile generate block "work@rggen.u_block_0.g_register_3.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_3.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:542:12: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:270:30: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:569:12: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:207:42: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:270:30: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:596:12: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:610:12: Compile generate block "work@rggen.u_block_0.g_register_3.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:625:19: Compile generate block "work@rggen.u_block_0.g_register_4". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_4.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_4.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_4.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:55:7: Compile generate block "work@rggen.u_block_0.g_register_4.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_4.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:642:12: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:668:12: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:694:12: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:266:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:719:12: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_4.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:746:19: Compile generate block "work@rggen.u_block_0.g_register_5". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_5.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_5.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_5.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_5.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_5.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:763:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:788:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:813:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:837:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:861:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_4". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_4.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_4.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_4.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_4.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_4.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:886:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_5". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_5.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_5.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_5.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_5.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_5.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:911:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_6". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_6.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_6.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_6.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_6.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_6.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:936:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_7". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_7.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_7.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_7.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_7.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_7.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:961:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_8". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_8.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_8.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_8.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_8.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_8.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:986:12: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_9". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_9.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_9.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_9.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_9.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_5.g_bit_field_9.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1012:19: Compile generate block "work@rggen.u_block_0.g_register_6". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[40].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[41].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[42].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[43].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[44].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[45].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[46].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[47].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[48].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[49].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[50].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[51].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[52].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[53].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[54].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[55].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[56].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[57].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[58].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[59].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[60].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[61].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[62].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_6.__g_tie_off.g[63].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_6.u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1029:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1055:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1081:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:266:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1106:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1132:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_4". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_4.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_4.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_4.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_4.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_4.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1158:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_5". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_5.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_5.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_5.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:266:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_5.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_5.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1183:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_6". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_6.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_6.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_6.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_6.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_6.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1209:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_7". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_7.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_7.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_7.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_7.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_7.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1235:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_8". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_8.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_8.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_8.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_8.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_8.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1260:12: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_9". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_9.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_9.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_9.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_9.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_6.g_bit_field_9.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1286:19: Compile generate block "work@rggen.u_block_0.g_register_7". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_7.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_7.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_7.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_7.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_7.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1303:12: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1329:12: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1355:12: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1381:12: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_7.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1408:19: Compile generate block "work@rggen.u_block_0.g_register_8". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[36].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[37].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[38].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[39].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[44].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[45].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[46].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[47].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[48].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[49].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[50].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[51].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[52].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[53].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[54].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[55].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[56].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[57].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[58].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[59].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[60].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[61].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[62].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_8.__g_tie_off.g[63].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_8.u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1425:12: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1451:12: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1477:12: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:270:30: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1503:12: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:270:30: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1529:12: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_4". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_4.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_4.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_4.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_4.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_4.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1555:12: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_5". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_5.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_5.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_5.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_5.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_8.g_bit_field_5.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1582:19: Compile generate block "work@rggen.u_block_0.g_register_9". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_9.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_9.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_9.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_9.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_9.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1599:12: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:221:66: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:235:64: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1625:12: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:221:66: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:235:64: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:266:8: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1650:12: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:221:66: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:270:30: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1677:12: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:221:66: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:235:64: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1703:12: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_4". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1717:12: Compile generate block "work@rggen.u_block_0.g_register_9.g_bit_field_5". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1732:19: Compile generate block "work@rggen.u_block_0.g_register_10". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1734:27: Compile generate block "work@rggen.u_block_0.g_register_10.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1751:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1780:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1808:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[0].g_bit_field_2.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1734:27: Compile generate block "work@rggen.u_block_0.g_register_10.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1751:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1780:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1808:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[1].g_bit_field_2.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1734:27: Compile generate block "work@rggen.u_block_0.g_register_10.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1751:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1780:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1808:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[2].g_bit_field_2.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1734:27: Compile generate block "work@rggen.u_block_0.g_register_10.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1751:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1753:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1780:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1782:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1808:14: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1810:31: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_10.g[3].g_bit_field_2.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1839:19: Compile generate block "work@rggen.u_block_0.g_register_11". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1842:27: Compile generate block "work@rggen.u_block_0.g_register_11.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[0].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[1].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[2].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[0].g[3].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1842:27: Compile generate block "work@rggen.u_block_0.g_register_11.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[0].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[1].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[2].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1843:29: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1865:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1867:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_0.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1894:16: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[2].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[2].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[2].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[2].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[2].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1896:33: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[3].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[3].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[3].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[3].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_11.g[1].g[3].g_bit_field_1.g[3].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1926:19: Compile generate block "work@rggen.u_block_0.g_register_12". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[1].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[2].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[3].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[32]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[33]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[33].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[34]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[34].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[35]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[35].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[36]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[36].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[37]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[37].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[38]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[38].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[39]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[39].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[40]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[40].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[41]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[41].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[42]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[42].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[43]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[43].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[44]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[44].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[45]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[45].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[46]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[46].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[47]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[47].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[48]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[48].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[49]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[49].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[50]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[50].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[51]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[51].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[52]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[52].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[53]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[53].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[54]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[54].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[55]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[55].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[56]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[56].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[57]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[57].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[58]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[58].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[59]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[59].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[60]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[60].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[61]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[61].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[62]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[62].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[63]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:55: Compile generate block "work@rggen.u_block_0.g_register_12.__g_tie_off.g[63].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.g_decoder[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.g_decoder[1].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.g_decoder[1].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_0.g_register_12.u_register.u_register_common.u_read_data_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1948:12: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1974:12: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_12.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2001:19: Compile generate block "work@rggen.u_block_0.g_register_13". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_0.g_register_13.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_0.g_register_13.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_0.g_register_13.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_13.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_0.g_register_13.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2018:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2048:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_1.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_1.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_1.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:266:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_1.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:274:5: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_1.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2077:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:207:42: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_2.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_2.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_2.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_2.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_2.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2107:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_3". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_3.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:221:66: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_3.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:235:64: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_3.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_3.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_3.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2137:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_4". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_4.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_4.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_4.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_4.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_4.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2167:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_5". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_5.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_5.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_5.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_5.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_5.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2197:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_6". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_6.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_6.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_6.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_6.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_6.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2227:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_7". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_7.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_7.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_7.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_7.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_7.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2257:12: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_8". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_8.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_8.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_8.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_8.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_0.g_register_13.g_bit_field_8.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:2288:19: Compile generate block "work@rggen.u_block_0.g_register_15". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:45:7: Compile generate block "work@rggen.u_block_0.g_register_15.u_register.u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_0.g_register_15.u_register.u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:95:10: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_no_request_slicer". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:103:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_request[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:141:35: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.g_response[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:10:23: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.u_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:97:10: Compile generate block "work@rggen.u_block_1.u_adapter.u_adapter_common.u_mux.g.u_reducer.g_reduce". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:62:19: Compile generate block "work@rggen.u_block_1.g_register_file_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:63:12: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:80:14: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_0.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:107:12: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:124:14: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_0.g_register_1.g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:152:19: Compile generate block "work@rggen.u_block_1.g_register_file_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:153:12: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:155:29: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:177:16: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[0].g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:155:29: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:177:16: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_0.g[1].g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:205:12: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:207:29: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:229:16: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[0].g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:207:29: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:229:16: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].g_bit_field_0.u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].g_bit_field_0.u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].g_bit_field_0.u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].g_bit_field_0.u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_1.g_register_1.g[1].g_bit_field_0.u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:258:19: Compile generate block "work@rggen.u_block_1.g_register_file_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:260:27: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:261:14: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:262:16: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:265:33: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:265:33: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:371:16: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[2].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[3].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:388:18: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:390:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:390:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[0].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:260:27: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:261:14: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:262:16: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:265:33: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[0].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[1].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[0].g[2].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:265:33: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[0].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[1].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:266:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:283:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:285:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_0.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:312:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:314:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_1.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:340:22: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:342:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_0.g[1].g[2].g_bit_field_2.g[1].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:371:16: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:12:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[2]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[2].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[3]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[3].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[4]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[4].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[5]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[5].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[6]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[6].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[7]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[7].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[8]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[8].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[9]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[9].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[10]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[10].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[11]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[11].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[12]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[12].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[13]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[13].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[14]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[14].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[15]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[15].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[16]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[16].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[17]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[17].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[18]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[18].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[19]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[19].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[20]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[20].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[21]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[21].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[22]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[22].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[23]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[23].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[24]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[24].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[25]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[25].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[26]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[26].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[27]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[27].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[28]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[28].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[29]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[29].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[30]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[30].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:14:34: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[31]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:15:47: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.__g_tie_off.g[31].g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv:32:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:33:39: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_address_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv:51:31: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.u_register.u_register_common.g_decoder[0].u_decoder.g_access_matcher". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv:27:10: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.u_register.u_register_common.u_read_data_mux.g". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:388:18: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:390:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[0]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[0].u_bit_field.g_read_data". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:390:35: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[1]". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:217:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_sw_write_done". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:231:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_write_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:245:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_read_trigger". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:249:25: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_value". + +[INF:CP0335] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv:276:8: Compile generate block "work@rggen.u_block_1.g_register_file_2.g[1].g_register_file_0.g_register_1.g_bit_field_0.g[1].u_bit_field.g_read_data". + +[NTE:EL0503] ${SURELOG_DIR}/third_party/tests/rggen/tests/generated/rggen/rggen.sv:11:1: Top level module "work@rggen". + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.u_adapter.u_adapter_common.u_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_6.u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_8.u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[0].g[0].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[0].g[1].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[0].g[2].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[0].g[3].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[1].g[0].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[1].g[1].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[1].g[2].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_11.g[1].g[3].u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_0.g_register_12.u_register.u_register_common.u_read_data_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0531] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv:66:10: Negative value in instance "work@rggen.u_block_1.u_adapter.u_adapter_common.u_mux.g.u_reducer" + text: logic [NEXT_N-1:0][WIDTH-1:0] next_data; + value: INT:-1. + +[NTE:EL0508] Nb Top level modules: 1. + +[NTE:EL0509] Max instance depth: 12. + +[NTE:EL0510] Nb instances: 473. + +[NTE:EL0511] Nb leaf instances: 0. + +[INF:UH0706] Creating UHDM Model... + +=== UHDM Object Stats Begin (Non-Elaborated Model) === +always 342 +array_typespec 203 +array_var 137 +assign_stmt 42 +assignment 726 +begin 991 +bit_select 5350 +bit_typespec 3251 +bit_var 8 +case_item 16 +case_stmt 3 +class_defn 8 +class_typespec 4 +class_var 3 +constant 135829 +cont_assign 7918 +design 1 +enum_const 8809 +enum_typespec 1300 +enum_var 357 +event_control 278 +for_stmt 19 +func_call 405 +function 25 +gen_if 105 +gen_if_else 13 +gen_region 29 +gen_scope 8816 +gen_scope_array 8816 +hier_path 8123 +if_else 296 +if_stmt 264 +immediate_assume 1 +import_typespec 12 +indexed_part_select 1186 +initial 1 +int_typespec 7649 +int_var 28 +integer_typespec 141 +interface_array 6 +interface_inst 1172 +interface_typespec 1848 +io_decl 17294 +logic_net 4413 +logic_typespec 17444 +logic_var 7678 +modport 2612 +module_array 3 +module_inst 3118 +module_typespec 3 +named_begin 127 +operation 34064 +package 4 +param_assign 10844 +parameter 13013 +part_select 184 +port 9957 +range 20954 +ref_module 861 +ref_obj 32961 +return_stmt 20 +sys_func_call 2 +task 9 +unsupported_typespec 1 +var_select 378 +while_stmt 1 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... + +=== UHDM Object Stats Begin (Elaborated Model) === +always 1459 +array_typespec 203 +array_var 4895 +assign_stmt 590 +assignment 29251 +begin 15961 +bit_select 48633 +bit_typespec 3251 +bit_var 1448 +case_item 12352 +case_stmt 2316 +class_defn 8 +class_typespec 4 +class_var 3 +constant 149864 +cont_assign 24865 +design 1 +enum_const 8814 +enum_typespec 1301 +enum_var 883 +event_control 1094 +for_stmt 567 +func_call 6133 +function 5981 +gen_if 105 +gen_if_else 13 +gen_region 29 +gen_scope 16726 +gen_scope_array 16726 +hier_path 21590 +if_else 4726 +if_stmt 1050 +immediate_assume 2 +import_typespec 12 +indexed_part_select 2325 +initial 2 +int_typespec 7649 +int_var 908 +integer_typespec 141 +interface_array 6 +interface_inst 1916 +interface_typespec 1848 +io_decl 48082 +logic_net 4413 +logic_typespec 17444 +logic_var 34716 +modport 3966 +module_array 3 +module_inst 3713 +module_typespec 3 +named_begin 127 +operation 92474 +package 4 +param_assign 18671 +parameter 13623 +part_select 2510 +port 24314 +range 29185 +ref_module 861 +ref_obj 192117 +return_stmt 7523 +sys_func_call 2 +task 18 +unsupported_typespec 1 +var_select 2484 +while_stmt 84 +=== UHDM Object Stats End === +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:16:17: Unresolved hierarchical reference "bit_field_if.read_data[__i]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:17:17: Unresolved hierarchical reference "bit_field_if.value[__i]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:3:11: Unresolved hierarchical reference "bit_field_sub_if.valid". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:3:52: Unresolved hierarchical reference "bit_field_if.valid". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:11: Unresolved hierarchical reference "bit_field_sub_if.read_mask". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:11: Unresolved hierarchical reference "bit_field_sub_if.write_mask". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:11: Unresolved hierarchical reference "bit_field_sub_if.write_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:7:11: Unresolved hierarchical reference "bit_field_if.read_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:7:42: Unresolved hierarchical reference "bit_field_sub_if.read_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:8:11: Unresolved hierarchical reference "bit_field_if.value". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:8:42: Unresolved hierarchical reference "bit_field_sub_if.value". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[4+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[4+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[4+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[9+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[9+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[9+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[11+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[11+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[11+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:7:43: Unresolved hierarchical reference "bit_field_sub_if.read_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:8:43: Unresolved hierarchical reference "bit_field_sub_if.value". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[13+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[13+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[13+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[15+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[15+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[15+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[8+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[8+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[8+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[16+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[16+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[16+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[20+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[20+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[20+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:514:30: Unresolved hierarchical reference "register_if[3].value[16+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[8+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[8+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[8+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:689:30: Unresolved hierarchical reference "register_if[0].value[0+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[12+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[12+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[12+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:713:30: Unresolved hierarchical reference "register_if[4].value[8+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[2+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[2+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[2+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:806:30: Unresolved hierarchical reference "register_if[3].value[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[4+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[4+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[4+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[6+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[6+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[6+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:851:30: Unresolved hierarchical reference "register_if[3].value[16+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[8+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[8+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[8+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[10+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[10+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[10+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:900:30: Unresolved hierarchical reference "register_if[0].value[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[12+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[12+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[12+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:925:30: Unresolved hierarchical reference "register_if[1].value[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[16+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[16+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[16+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[18+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[18+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[18+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:975:30: Unresolved hierarchical reference "register_if[0].value[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[20+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[20+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[20+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1000:30: Unresolved hierarchical reference "register_if[1].value[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1076:30: Unresolved hierarchical reference "register_if[0].value[0+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1100:30: Unresolved hierarchical reference "register_if[6].value[4+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1153:30: Unresolved hierarchical reference "register_if[0].value[0+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1177:30: Unresolved hierarchical reference "register_if[6].value[16+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[24+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[24+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[24+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[28+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[28+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[28+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[32+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[32+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[32+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[36+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[36+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[36+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[40+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[40+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[40+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:7:46: Unresolved hierarchical reference "bit_field_sub_if.read_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:8:46: Unresolved hierarchical reference "bit_field_sub_if.value". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[2 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[2 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[2 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[4 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[4 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[4 + 8 * j+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1847:34: Unresolved hierarchical reference "register_if[0].value[0+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1847:62: Unresolved hierarchical reference "register_if[0].value[4+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1847:90: Unresolved hierarchical reference "register_if[0].value[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0 + 16 * k+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0 + 16 * k+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0 + 16 * k+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:7:47: Unresolved hierarchical reference "bit_field_sub_if.read_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:8:47: Unresolved hierarchical reference "bit_field_sub_if.value". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[8 + 16 * k+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[8 + 16 * k+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[8 + 16 * k+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:1930:30: Unresolved hierarchical reference "register_if[0].value[8+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[32+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[32+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[32+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[14+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[14+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[14+:2]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:104:15: Unresolved hierarchical reference "register_if[i].valid". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:105:15: Unresolved hierarchical reference "register_if[i].access". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:106:15: Unresolved hierarchical reference "register_if[i].address". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:107:15: Unresolved hierarchical reference "register_if[i].write_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:108:15: Unresolved hierarchical reference "register_if[i].strobe". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:142:29: Unresolved hierarchical reference "register_if[i].active". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:143:29: Unresolved hierarchical reference "register_if[i].ready". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:144:30: Unresolved hierarchical reference "register_if[i].status". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv:144:53: Unresolved hierarchical reference "register_if[i].read_data". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv:13:30: Unresolved hierarchical reference "apb_if.ADDRESS_WIDTH". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:159:34: Unresolved hierarchical reference "register_if[0].value[0+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:159:62: Unresolved hierarchical reference "register_if[1].value[0+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:211:34: Unresolved hierarchical reference "register_if[0].value[0+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:211:62: Unresolved hierarchical reference "register_if[1].value[0+:8]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[8 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[8 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[8 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:328:42: Unresolved hierarchical reference "register_if[0].value[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[16 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[16 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[16 + 4 * l+:4]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:356:42: Unresolved hierarchical reference "register_if[12].value[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:356:42: Unresolved hierarchical reference "register_if[12].value[1+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:4:52: Unresolved hierarchical reference "bit_field_if.read_mask[0 + 1 * j+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:5:52: Unresolved hierarchical reference "bit_field_if.write_mask[0 + 1 * j+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_0.sv:6:52: Unresolved hierarchical reference "bit_field_if.write_data[0 + 1 * j+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:356:42: Unresolved hierarchical reference "register_if[19].value[0+:1]". + +[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/rggen/rggen-sample/block_1.sv:356:42: Unresolved hierarchical reference "register_if[19].value[1+:1]". + +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Rggen/slpp_all/surelog.uhdm ... + +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 173 +[WARNING] : 20 +[ NOTE] : 18 diff --git a/third_party/tests/rggen/Rggen.sl b/third_party/tests/rggen/Rggen.sl new file mode 100644 index 0000000000..40e98bdf3b --- /dev/null +++ b/third_party/tests/rggen/Rggen.sl @@ -0,0 +1 @@ +-elabuhdm -nopython -parse -verbose --top-module rggen -Itests/generated/rggen rggen-sv-rtl/rggen_rtl_pkg.sv rggen-sv-rtl/rggen_or_reducer.sv rggen-sv-rtl/rggen_mux.sv rggen-sv-rtl/rggen_bit_field_if.sv rggen-sv-rtl/rggen_bit_field.sv rggen-sv-rtl/rggen_bit_field_w01trg.sv rggen-sv-rtl/rggen_register_if.sv rggen-sv-rtl/rggen_address_decoder.sv rggen-sv-rtl/rggen_register_common.sv rggen-sv-rtl/rggen_default_register.sv rggen-sv-rtl/rggen_external_register.sv rggen-sv-rtl/rggen_indirect_register.sv rggen-sv-rtl/rggen_bus_if.sv rggen-sv-rtl/rggen_adapter_common.sv rggen-sv-rtl/rggen_apb_if.sv rggen-sv-rtl/rggen_apb_adapter.sv rggen-sv-rtl/rggen_apb_bridge.sv rggen-sample/block_0.sv rggen-sample/block_1.sv tests/generated/rggen/rggen.sv diff --git a/third_party/tests/rggen/rggen-sample/LICENSE b/third_party/tests/rggen/rggen-sample/LICENSE new file mode 100644 index 0000000000..83e0fdf4fe --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2019-2023 Taichi Ishitani + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/third_party/tests/rggen/rggen-sample/block_0.h b/third_party/tests/rggen/rggen-sample/block_0.h new file mode 100644 index 0000000000..e3d4daa487 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.h @@ -0,0 +1,330 @@ +#ifndef BLOCK_0_H +#define BLOCK_0_H +#include "stdint.h" +#define BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_0_BIT_FIELD_1_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_0_BIT_FIELD_1_BIT_MASK 0xf +#define BLOCK_0_REGISTER_0_BIT_FIELD_1_BIT_OFFSET 4 +#define BLOCK_0_REGISTER_0_BIT_FIELD_2_BIT_WIDTH 1 +#define BLOCK_0_REGISTER_0_BIT_FIELD_2_BIT_MASK 0x1 +#define BLOCK_0_REGISTER_0_BIT_FIELD_2_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_0_BIT_FIELD_3_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_0_BIT_FIELD_3_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_0_BIT_FIELD_3_BIT_OFFSET 9 +#define BLOCK_0_REGISTER_0_BIT_FIELD_4_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_0_BIT_FIELD_4_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_0_BIT_FIELD_4_BIT_OFFSET 11 +#define BLOCK_0_REGISTER_0_BIT_FIELD_5_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_0_BIT_FIELD_5_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_0_BIT_FIELD_5_BIT_OFFSET 13 +#define BLOCK_0_REGISTER_0_BIT_FIELD_6_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_0_BIT_FIELD_6_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_0_BIT_FIELD_6_BIT_OFFSET 15 +#define BLOCK_0_REGISTER_0_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_0_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_0_BYTE_OFFSET 0x0 +#define BLOCK_0_REGISTER_1_BIT_WIDTH 1 +#define BLOCK_0_REGISTER_1_BIT_MASK 0x1 +#define BLOCK_0_REGISTER_1_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_1_FOO 0x0 +#define BLOCK_0_REGISTER_1_BAR 0x1 +#define BLOCK_0_REGISTER_1_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_1_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_1_BYTE_OFFSET 0x4 +#define BLOCK_0_REGISTER_2_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_2_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_0_REGISTER_2_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_2_BIT_FIELD_1_BIT_WIDTH 8 +#define BLOCK_0_REGISTER_2_BIT_FIELD_1_BIT_MASK 0xff +#define BLOCK_0_REGISTER_2_BIT_FIELD_1_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_2_BIT_FIELD_2_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_2_BIT_FIELD_2_BIT_MASK 0xf +#define BLOCK_0_REGISTER_2_BIT_FIELD_2_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_2_BIT_FIELD_3_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_2_BIT_FIELD_3_BIT_MASK 0xf +#define BLOCK_0_REGISTER_2_BIT_FIELD_3_BIT_OFFSET 20 +#define BLOCK_0_REGISTER_2_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_2_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_2_BYTE_OFFSET 0x8 +#define BLOCK_0_REGISTER_3_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_3_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_0_REGISTER_3_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_3_BIT_FIELD_1_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_3_BIT_FIELD_1_BIT_MASK 0xf +#define BLOCK_0_REGISTER_3_BIT_FIELD_1_BIT_OFFSET 4 +#define BLOCK_0_REGISTER_3_BIT_FIELD_2_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_3_BIT_FIELD_2_BIT_MASK 0xf +#define BLOCK_0_REGISTER_3_BIT_FIELD_2_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_3_BIT_FIELD_3_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_3_BIT_FIELD_3_BIT_MASK 0xf +#define BLOCK_0_REGISTER_3_BIT_FIELD_3_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_3_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_3_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_3_BYTE_OFFSET 0x8 +#define BLOCK_0_REGISTER_4_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_4_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_0_REGISTER_4_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_4_BIT_FIELD_1_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_4_BIT_FIELD_1_BIT_MASK 0xf +#define BLOCK_0_REGISTER_4_BIT_FIELD_1_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_4_BIT_FIELD_2_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_4_BIT_FIELD_2_BIT_MASK 0xf +#define BLOCK_0_REGISTER_4_BIT_FIELD_2_BIT_OFFSET 12 +#define BLOCK_0_REGISTER_4_BIT_FIELD_3_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_4_BIT_FIELD_3_BIT_MASK 0xf +#define BLOCK_0_REGISTER_4_BIT_FIELD_3_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_4_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_4_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_4_BYTE_OFFSET 0xc +#define BLOCK_0_REGISTER_5_BIT_FIELD_0_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_0_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_5_BIT_FIELD_1_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_1_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_1_BIT_OFFSET 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_2_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_2_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_2_BIT_OFFSET 4 +#define BLOCK_0_REGISTER_5_BIT_FIELD_3_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_3_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_3_BIT_OFFSET 6 +#define BLOCK_0_REGISTER_5_BIT_FIELD_4_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_4_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_4_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_5_BIT_FIELD_5_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_5_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_5_BIT_OFFSET 10 +#define BLOCK_0_REGISTER_5_BIT_FIELD_6_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_6_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_6_BIT_OFFSET 12 +#define BLOCK_0_REGISTER_5_BIT_FIELD_7_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_7_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_7_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_5_BIT_FIELD_8_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_8_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_8_BIT_OFFSET 18 +#define BLOCK_0_REGISTER_5_BIT_FIELD_9_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_5_BIT_FIELD_9_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_5_BIT_FIELD_9_BIT_OFFSET 20 +#define BLOCK_0_REGISTER_5_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_5_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_5_BYTE_OFFSET 0x10 +#define BLOCK_0_REGISTER_6_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_6_BIT_FIELD_1_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_1_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_1_BIT_OFFSET 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_2_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_2_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_2_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_6_BIT_FIELD_3_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_3_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_3_BIT_OFFSET 12 +#define BLOCK_0_REGISTER_6_BIT_FIELD_4_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_4_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_4_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_6_BIT_FIELD_5_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_5_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_5_BIT_OFFSET 20 +#define BLOCK_0_REGISTER_6_BIT_FIELD_6_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_6_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_6_BIT_OFFSET 24 +#define BLOCK_0_REGISTER_6_BIT_FIELD_7_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_7_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_7_BIT_OFFSET 28 +#define BLOCK_0_REGISTER_6_BIT_FIELD_8_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_8_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_8_BIT_OFFSET 32 +#define BLOCK_0_REGISTER_6_BIT_FIELD_9_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_6_BIT_FIELD_9_BIT_MASK 0xf +#define BLOCK_0_REGISTER_6_BIT_FIELD_9_BIT_OFFSET 36 +#define BLOCK_0_REGISTER_6_BYTE_WIDTH 8 +#define BLOCK_0_REGISTER_6_BYTE_SIZE 8 +#define BLOCK_0_REGISTER_6_BYTE_OFFSET 0x14 +#define BLOCK_0_REGISTER_7_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_7_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_0_REGISTER_7_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_7_BIT_FIELD_1_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_7_BIT_FIELD_1_BIT_MASK 0xf +#define BLOCK_0_REGISTER_7_BIT_FIELD_1_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_7_BIT_FIELD_2_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_7_BIT_FIELD_2_BIT_MASK 0xf +#define BLOCK_0_REGISTER_7_BIT_FIELD_2_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_7_BIT_FIELD_3_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_7_BIT_FIELD_3_BIT_MASK 0xf +#define BLOCK_0_REGISTER_7_BIT_FIELD_3_BIT_OFFSET 24 +#define BLOCK_0_REGISTER_7_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_7_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_7_BYTE_OFFSET 0x1c +#define BLOCK_0_REGISTER_8_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_8_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_0_REGISTER_8_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_8_BIT_FIELD_1_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_8_BIT_FIELD_1_BIT_MASK 0xf +#define BLOCK_0_REGISTER_8_BIT_FIELD_1_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_8_BIT_FIELD_2_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_8_BIT_FIELD_2_BIT_MASK 0xf +#define BLOCK_0_REGISTER_8_BIT_FIELD_2_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_8_BIT_FIELD_3_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_8_BIT_FIELD_3_BIT_MASK 0xf +#define BLOCK_0_REGISTER_8_BIT_FIELD_3_BIT_OFFSET 24 +#define BLOCK_0_REGISTER_8_BIT_FIELD_4_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_8_BIT_FIELD_4_BIT_MASK 0xf +#define BLOCK_0_REGISTER_8_BIT_FIELD_4_BIT_OFFSET 32 +#define BLOCK_0_REGISTER_8_BIT_FIELD_5_BIT_WIDTH 4 +#define BLOCK_0_REGISTER_8_BIT_FIELD_5_BIT_MASK 0xf +#define BLOCK_0_REGISTER_8_BIT_FIELD_5_BIT_OFFSET 40 +#define BLOCK_0_REGISTER_8_BYTE_WIDTH 8 +#define BLOCK_0_REGISTER_8_BYTE_SIZE 8 +#define BLOCK_0_REGISTER_8_BYTE_OFFSET 0x20 +#define BLOCK_0_REGISTER_9_BIT_FIELD_0_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_9_BIT_FIELD_0_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_9_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_9_BIT_FIELD_1_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_9_BIT_FIELD_1_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_9_BIT_FIELD_1_BIT_OFFSET 2 +#define BLOCK_0_REGISTER_9_BIT_FIELD_2_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_9_BIT_FIELD_2_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_9_BIT_FIELD_2_BIT_OFFSET 4 +#define BLOCK_0_REGISTER_9_BIT_FIELD_3_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_9_BIT_FIELD_3_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_9_BIT_FIELD_3_BIT_OFFSET 6 +#define BLOCK_0_REGISTER_9_BIT_FIELD_4_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_9_BIT_FIELD_4_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_9_BIT_FIELD_4_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_9_BIT_FIELD_5_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_9_BIT_FIELD_5_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_9_BIT_FIELD_5_BIT_OFFSET 10 +#define BLOCK_0_REGISTER_9_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_9_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_9_BYTE_OFFSET 0x28 +#define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_0 0 +#define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_1 8 +#define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_2 16 +#define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_3 24 +#define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_0 2 +#define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_1 10 +#define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_2 18 +#define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_3 26 +#define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_0 4 +#define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_1 12 +#define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_2 20 +#define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_3 28 +#define BLOCK_0_REGISTER_10_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_10_BYTE_SIZE 32 +#define BLOCK_0_REGISTER_10_ARRAY_DIMENSION 1 +#define BLOCK_0_REGISTER_10_ARRAY_SIZE_0 4 +#define BLOCK_0_REGISTER_10_BYTE_OFFSET_0 0x30 +#define BLOCK_0_REGISTER_10_BYTE_OFFSET_1 0x38 +#define BLOCK_0_REGISTER_10_BYTE_OFFSET_2 0x40 +#define BLOCK_0_REGISTER_10_BYTE_OFFSET_3 0x48 +#define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_WIDTH 8 +#define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_MASK 0xff +#define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_0 0 +#define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_1 16 +#define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_2 32 +#define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_3 48 +#define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_WIDTH 8 +#define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_MASK 0xff +#define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_0 8 +#define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_1 24 +#define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_2 40 +#define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_3 56 +#define BLOCK_0_REGISTER_11_BYTE_WIDTH 8 +#define BLOCK_0_REGISTER_11_BYTE_SIZE 8 +#define BLOCK_0_REGISTER_11_ARRAY_DIMENSION 2 +#define BLOCK_0_REGISTER_11_ARRAY_SIZE_0 2 +#define BLOCK_0_REGISTER_11_ARRAY_SIZE_1 4 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_0 0x50 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_1 0x50 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_2 0x50 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_3 0x50 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_0 0x50 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_1 0x50 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_2 0x50 +#define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_3 0x50 +#define BLOCK_0_REGISTER_12_BIT_FIELD_0_BIT_WIDTH 1 +#define BLOCK_0_REGISTER_12_BIT_FIELD_0_BIT_MASK 0x1 +#define BLOCK_0_REGISTER_12_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_12_BIT_FIELD_1_BIT_WIDTH 1 +#define BLOCK_0_REGISTER_12_BIT_FIELD_1_BIT_MASK 0x1 +#define BLOCK_0_REGISTER_12_BIT_FIELD_1_BIT_OFFSET 32 +#define BLOCK_0_REGISTER_12_BYTE_WIDTH 8 +#define BLOCK_0_REGISTER_12_BYTE_SIZE 8 +#define BLOCK_0_REGISTER_12_BYTE_OFFSET 0x50 +#define BLOCK_0_REGISTER_13_BIT_FIELD_0_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_0_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_0_REGISTER_13_BIT_FIELD_1_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_1_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_1_BIT_OFFSET 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_2_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_2_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_2_BIT_OFFSET 4 +#define BLOCK_0_REGISTER_13_BIT_FIELD_3_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_3_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_3_BIT_OFFSET 6 +#define BLOCK_0_REGISTER_13_BIT_FIELD_4_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_4_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_4_BIT_OFFSET 8 +#define BLOCK_0_REGISTER_13_BIT_FIELD_5_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_5_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_5_BIT_OFFSET 10 +#define BLOCK_0_REGISTER_13_BIT_FIELD_6_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_6_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_6_BIT_OFFSET 12 +#define BLOCK_0_REGISTER_13_BIT_FIELD_7_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_7_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_7_BIT_OFFSET 14 +#define BLOCK_0_REGISTER_13_BIT_FIELD_8_BIT_WIDTH 2 +#define BLOCK_0_REGISTER_13_BIT_FIELD_8_BIT_MASK 0x3 +#define BLOCK_0_REGISTER_13_BIT_FIELD_8_BIT_OFFSET 16 +#define BLOCK_0_REGISTER_13_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_13_BYTE_SIZE 4 +#define BLOCK_0_REGISTER_13_BYTE_OFFSET 0x60 +#define BLOCK_0_REGISTER_15_BYTE_WIDTH 4 +#define BLOCK_0_REGISTER_15_BYTE_SIZE 128 +#define BLOCK_0_REGISTER_15_BYTE_OFFSET 0x80 +typedef union { + uint32_t register_2; + uint32_t register_3; +} block_0_reg_0x08_t; +typedef union { + uint64_t register_11; + uint64_t register_12; +} block_0_reg_0x50_t; +typedef struct { + uint32_t register_0; + uint32_t register_1; + block_0_reg_0x08_t reg_0x08; + uint32_t register_4; + uint32_t register_5; + uint64_t register_6; + uint32_t register_7; + uint64_t register_8; + uint32_t register_9; + uint32_t __reserved_0x2c; + uint64_t register_10[4]; + block_0_reg_0x50_t reg_0x50; + uint32_t __reserved_0x58; + uint32_t __reserved_0x5c; + uint32_t register_13; + uint32_t __reserved_0x64; + uint32_t __reserved_0x68; + uint32_t __reserved_0x6c; + uint32_t __reserved_0x70; + uint32_t __reserved_0x74; + uint32_t __reserved_0x78; + uint32_t __reserved_0x7c; + uint32_t register_15[32]; +} block_0_t; +#endif diff --git a/third_party/tests/rggen/rggen-sample/block_0.md b/third_party/tests/rggen/rggen-sample/block_0.md new file mode 100644 index 0000000000..7c88c23c72 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.md @@ -0,0 +1,268 @@ +## block_0 + +* byte_size + * 256 + +|name|offset_address| +|:--|:--| +|[register_0](#block_0-register_0)|0x00| +|[register_1](#block_0-register_1)|0x04| +|[register_2](#block_0-register_2)|0x08| +|[register_3](#block_0-register_3)|0x08| +|[register_4](#block_0-register_4)|0x0c| +|[register_5](#block_0-register_5)|0x10| +|[register_6](#block_0-register_6)|0x14| +|[register_7](#block_0-register_7)|0x1c| +|[register_8](#block_0-register_8)|0x20| +|[register_9](#block_0-register_9)|0x28| +|[register_10[4]](#block_0-register_10)|0x30
0x38
0x40
0x48| +|[register_11[2][4]](#block_0-register_11)|0x50
0x50
0x50
0x50
0x50
0x50
0x50
0x50| +|[register_12](#block_0-register_12)|0x50| +|[register_13](#block_0-register_13)|0x60| +|[register_14](#block_0-register_14)|0x70| +|[register_15](#block_0-register_15)|0x80| + +###
register_0 + +* offset_address + * 0x00 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[3:0]|rw|0x0|||this is register_0.bit_field_0| +|bit_field_1|[7:4]|rw|0x0|||| +|bit_field_2|[8]|rw|0x0|||| +|bit_field_3|[10:9]|w1|0x0|||| +|bit_field_4|[12:11]|wrc|0x0|||| +|bit_field_5|[14:13]|wrs|0x0|||| +|bit_field_6|[16:15]|rowo|0x0|||| + +###
register_1 + +* offset_address + * 0x04 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|register_1|[0]|rw|0x0||name: foo value: 0 comment: FOO value
name: bar value: 1 comment: BAR value|| + +###
register_2 + +* offset_address + * 0x08 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[3:0]|ro||||| +|bit_field_1|[15:8]|rof|0xab|||| +|bit_field_2|[19:16]|rol|0x0|||| +|bit_field_3|[23:20]|rol|0x0|register_3.bit_field_3||| +|bit_field_4|[31:24]|reserved||||| + +###
register_3 + +* offset_address + * 0x08 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[3:0]|wo|0x0|||| +|bit_field_1|[7:4]|wo1|0x0|||| +|bit_field_2|[11:8]|w0trg||||| +|bit_field_3|[19:16]|w1trg||||| + +###
register_4 + +* offset_address + * 0x0c +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[3:0]|rc|0x0|||| +|bit_field_1|[11:8]|rc|0x0|register_0.bit_field_0||| +|bit_field_2|[15:12]|ro||register_4.bit_field_1||| +|bit_field_3|[19:16]|rs|0x0|||| + +###
register_5 + +* offset_address + * 0x10 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[1:0]|rwc|0x0|||| +|bit_field_1|[3:2]|rwc|0x0|register_3.bit_field_2||| +|bit_field_2|[5:4]|rws|0x0|||| +|bit_field_3|[7:6]|rws|0x0|register_3.bit_field_3||| +|bit_field_4|[9:8]|rwe|0x0|||| +|bit_field_5|[11:10]|rwe|0x0|register_0.bit_field_2||| +|bit_field_6|[13:12]|rwe|0x0|register_1||| +|bit_field_7|[17:16]|rwl|0x0|||| +|bit_field_8|[19:18]|rwl|0x0|register_0.bit_field_2||| +|bit_field_9|[21:20]|rwl|0x0|register_1||| + +###
register_6 + +* offset_address + * 0x14 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[3:0]|w0c|0x0|||| +|bit_field_1|[7:4]|w0c|0x0|register_0.bit_field_0||| +|bit_field_2|[11:8]|ro||register_6.bit_field_1||| +|bit_field_3|[15:12]|w1c|0x0|||| +|bit_field_4|[19:16]|w1c|0x0|register_0.bit_field_0||| +|bit_field_5|[23:20]|ro||register_6.bit_field_4||| +|bit_field_6|[27:24]|w0s|0x0|||| +|bit_field_7|[31:28]|w1s|0x0|||| +|bit_field_8|[35:32]|w0t|0x0|||| +|bit_field_9|[39:36]|w1t|0x0|||| + +###
register_7 + +* offset_address + * 0x1c +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[3:0]|w0crs|0x0|||| +|bit_field_1|[11:8]|w1crs|0x0|||| +|bit_field_2|[19:16]|w0src|0x0|||| +|bit_field_3|[27:24]|w1src|0x0|||| + +###
register_8 + +* offset_address + * 0x20 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[3:0]|wc|0x0|||| +|bit_field_1|[11:8]|ws|0x0|||| +|bit_field_2|[19:16]|woc|0x0|||| +|bit_field_3|[27:24]|wos|0x0|||| +|bit_field_4|[35:32]|wcrs|0x0|||| +|bit_field_5|[43:40]|wsrc|0x0|||| + +###
register_9 + +* offset_address + * 0x28 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[1:0]|rwtrg|0x0|||| +|bit_field_1|[3:2]|rotrg||||| +|bit_field_2|[5:4]|wotrg|0x0|||| +|bit_field_3|[7:6]|rowotrg|0x0|||| +|bit_field_4|[9:8]|row0trg||||| +|bit_field_5|[11:10]|row1trg||||| + +###
register_10[4] + +* offset_address + * 0x30 + * 0x38 + * 0x40 + * 0x48 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0[4]|[1:0]
[9:8]
[17:16]
[25:24]|rw|0x0|||| +|bit_field_1[4]|[3:2]
[11:10]
[19:18]
[27:26]|rw|default: 0x0|||| +|bit_field_2[4]|[5:4]
[13:12]
[21:20]
[29:28]|rw|0x0
0x1
0x2
0x3|||| + +###
register_11[2][4] + +* offset_address + * 0x50 + * 0x50 + * 0x50 + * 0x50 + * 0x50 + * 0x50 + * 0x50 + * 0x50 +* type + * indirect +* index_bit_fields + * register_0.bit_field_0 + * register_0.bit_field_1 + * register_0.bit_field_2: 0 + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0[4]|[7:0]
[23:16]
[39:32]
[55:48]|rw|0x00|||| +|bit_field_1[4]|[15:8]
[31:24]
[47:40]
[63:56]|rw|0x00|||| + +###
register_12 + +* offset_address + * 0x50 +* type + * indirect +* index_bit_fields + * register_0.bit_field_2: 1 + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[0]|rw|0x0|||| +|bit_field_1|[32]|rw|0x0|||| + +###
register_13 + +* offset_address + * 0x60 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[1:0]|custom
sw_read: default
sw_write: default
sw_write_once: false
hw_write: false
hw_set: false
hw_clear: false|0x0|||| +|bit_field_1|[3:2]|custom
sw_read: default
sw_write: none
sw_write_once: false
hw_write: false
hw_set: false
hw_clear: false||||| +|bit_field_2|[5:4]|custom
sw_read: default
sw_write: default
sw_write_once: true
hw_write: false
hw_set: false
hw_clear: false|0x0|||| +|bit_field_3|[7:6]|custom
sw_read: default
sw_write: default
sw_write_once: false
hw_write: false
hw_set: false
hw_clear: false|0x0|||| +|bit_field_4|[9:8]|custom
sw_read: clear
sw_write: set_1
sw_write_once: false
hw_write: false
hw_set: false
hw_clear: false|0x0|||| +|bit_field_5|[11:10]|custom
sw_read: set
sw_write: clear_1
sw_write_once: false
hw_write: false
hw_set: false
hw_clear: false|0x0|||| +|bit_field_6|[13:12]|custom
sw_read: default
sw_write: set_1
sw_write_once: false
hw_write: false
hw_set: false
hw_clear: true|0x0|||| +|bit_field_7|[15:14]|custom
sw_read: default
sw_write: clear_1
sw_write_once: false
hw_write: false
hw_set: true
hw_clear: false|0x0|||| +|bit_field_8|[17:16]|custom
sw_read: default
sw_write: default
sw_write_once: false
hw_write: true
hw_set: false
hw_clear: false|0x0|||| + +###
register_14 + +* offset_address + * 0x70 +* type + * reserved + +###
register_15 + +* offset_address + * 0x80 +* type + * external +* byte_size + * 128 bytes diff --git a/third_party/tests/rggen/rggen-sample/block_0.rb b/third_party/tests/rggen/rggen-sample/block_0.rb new file mode 100644 index 0000000000..b3a3ae148d --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.rb @@ -0,0 +1,186 @@ +# frozen_string_literal: true + +register_block { + name 'block_0' + byte_size 256 + + register { + name 'register_0' + bit_field { name 'bit_field_0'; bit_assignment width: 4; type :rw ; initial_value 0; comment 'this is register_0.bit_field_0' } + bit_field { name 'bit_field_1'; bit_assignment width: 4; type :rw ; initial_value 0 } + bit_field { name 'bit_field_2'; bit_assignment width: 1; type :rw ; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment width: 2; type :w1 ; initial_value 0 } + bit_field { name 'bit_field_4'; bit_assignment width: 2; type :wrc ; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment width: 2; type :wrs ; initial_value 0 } + bit_field { name 'bit_field_6'; bit_assignment width: 2; type :rowo; initial_value 0 } + } + + register { + name 'register_1' + bit_field do + bit_assignment lsb: 0, width: 1 + type :rw + initial_value 0 + labels [ + { name: :foo, value: 0, comment: 'FOO value' }, + { name: :bar, value: 1, comment: 'BAR value' } + ] + end + } + + register { + name 'register_2' + offset_address 0x08 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :ro } + bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8; type :rof; initial_value 0xab } + bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 4; type :rol; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 20, width: 4; type :rol; initial_value 0; reference 'register_3.bit_field_3' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 24, width: 8; type :reserved } + } + + register { + name 'register_3' + offset_address 0x08 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :wo ; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 4, width: 4; type :wo1; initial_value 0 } + bit_field { name 'bit_field_2'; bit_assignment lsb: 8, width: 4; type :w0trg } + bit_field { name 'bit_field_3'; bit_assignment lsb: 16, width: 4; type :w1trg } + } + + register { + name 'register_4' + offset_address 0x0C + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :rc; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 4; type :rc; initial_value 0; reference 'register_0.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 12, width: 4; type :ro; reference 'register_4.bit_field_1' } + bit_field { name 'bit_field_3'; bit_assignment lsb: 16, width: 4; type :rs; initial_value 0 } + } + + register { + name 'register_5' + offset_address 0x10 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 2; type :rwc; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 2, width: 2; type :rwc; initial_value 0; reference 'register_3.bit_field_2' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rws; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rws; initial_value 0; reference 'register_3.bit_field_3' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 8, width: 2; type :rwe; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 10, width: 2; type :rwe; initial_value 0; reference 'register_0.bit_field_2' } + bit_field { name 'bit_field_6'; bit_assignment lsb: 12, width: 2; type :rwe; initial_value 0; reference 'register_1' } + bit_field { name 'bit_field_7'; bit_assignment lsb: 16, width: 2; type :rwl; initial_value 0 } + bit_field { name 'bit_field_8'; bit_assignment lsb: 18, width: 2; type :rwl; initial_value 0; reference 'register_0.bit_field_2' } + bit_field { name 'bit_field_9'; bit_assignment lsb: 20, width: 2; type :rwl; initial_value 0; reference 'register_1' } + } + + register { + name 'register_6' + offset_address 0x14 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :w0c; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 4, width: 4; type :w0c; initial_value 0; reference 'register_0.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 8, width: 4; type :ro ; reference 'register_6.bit_field_1' } + bit_field { name 'bit_field_3'; bit_assignment lsb: 12, width: 4; type :w1c; initial_value 0 } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4; type :w1c; initial_value 0; reference 'register_0.bit_field_0' } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4; type :ro ; reference 'register_6.bit_field_4' } + bit_field { name 'bit_field_6'; bit_assignment lsb: 24, width: 4; type :w0s; initial_value 0 } + bit_field { name 'bit_field_7'; bit_assignment lsb: 28, width: 4; type :w1s; initial_value 0 } + bit_field { name 'bit_field_8'; bit_assignment lsb: 32, width: 4; type :w0t; initial_value 0 } + bit_field { name 'bit_field_9'; bit_assignment lsb: 36, width: 4; type :w1t; initial_value 0 } + } + + register { + name 'register_7' + offset_address 0x1C + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :w0crs; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 4; type :w1crs; initial_value 0 } + bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 4; type :w0src; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 24, width: 4; type :w1src; initial_value 0 } + } + + register { + name 'register_8' + offset_address 0x20 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :wc ; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 4; type :ws ; initial_value 0 } + bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 4; type :woc ; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 24, width: 4; type :wos ; initial_value 0 } + bit_field { name 'bit_field_4'; bit_assignment lsb: 32, width: 4; type :wcrs; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 40, width: 4; type :wsrc; initial_value 0 } + } + + register { + name 'register_9' + offset_address 0x28 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 2; type :rwtrg ; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 2, width: 2; type :rotrg } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :wotrg ; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rowotrg; initial_value 0 } + bit_field { name 'bit_field_4'; bit_assignment lsb: 8, width: 2; type :row0trg } + bit_field { name 'bit_field_5'; bit_assignment lsb: 10, width: 2; type :row1trg } + } + + register { + name 'register_10' + offset_address 0x30 + size [4, step: 8] + # bit assignments: [1:0] [ 9: 8] [17:16] [25:24] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 2, sequence_size: 4, step: 8; type :rw; initial_value 0 } + # bit assignments: [3:2] [11:10] [19:18] [27:26] + bit_field { name 'bit_field_1'; bit_assignment lsb: 2, width: 2, sequence_size: 4, step: 8; type :rw; initial_value default: 0 } + # bit assignments: [5:4] [13:12] [21:20] [29:28] + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2, sequence_size: 4, step: 8; type :rw; initial_value [0, 1, 2, 3] } + } + + register { + name 'register_11' + offset_address 0x50 + size [2, 4] + type [:indirect, 'register_0.bit_field_0', 'register_0.bit_field_1', ['register_0.bit_field_2', 0]] + # bit assignments: [ 7:0] [23:16] [39:32] [55:48] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 } + # bit assignments: [15:8] [31:24] [47:40] [63:56] + bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 } + } + + register { + name 'register_12' + offset_address 0x50 + type [:indirect, ['register_0.bit_field_2', 1]] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 32, width: 1; type :rw; initial_value 0 } + } + + register { + name 'register_13' + offset_address 0x60 + # same with RW bit field type + bit_field { name 'bit_field_0'; bit_assignment width: 2; initial_value 0; type [:custom ] } + # same with RO bit filed type + bit_field { name 'bit_field_1'; bit_assignment width: 2; type [:custom, sw_write: :none ] } + # same with W1 bit field type + bit_field { name 'bit_field_2'; bit_assignment width: 2; initial_value 0; type [:custom, sw_write_once: true ] } + # same with RWTRG bit field type + bit_field { name 'bit_field_3'; bit_assignment width: 2; initial_value 0; type [:custom, write_trigger: true, read_trigger: true] } + # same with W1SRC bit field type + bit_field { name 'bit_field_4'; bit_assignment width: 2; initial_value 0; type [:custom, sw_write: :set_1 , sw_read: :clear ] } + # same with W1CRS bit field type + bit_field { name 'bit_field_5'; bit_assignment width: 2; initial_value 0; type [:custom, sw_write: :clear_1, sw_read: :set ] } + # same with W1S bit field type + bit_field { name 'bit_field_6'; bit_assignment width: 2; initial_value 0; type [:custom, sw_write: :set_1 , hw_clear: true ] } + # same with W1C bit field type + bit_field { name 'bit_field_7'; bit_assignment width: 2; initial_value 0; type [:custom, sw_write: :clear_1, hw_set: true ] } + # RW bit field with HW write + bit_field { name 'bit_field_8'; bit_assignment width: 2; initial_value 0; type [:custom, hw_write: true ] } + } + + register { + name 'register_14' + offset_address 0x70 + type :reserved + } + + register { + name 'register_15' + offset_address 0x80 + size 32 + type :external + } +} diff --git a/third_party/tests/rggen/rggen-sample/block_0.sv b/third_party/tests/rggen/rggen-sample/block_0.sv new file mode 100644 index 0000000000..207ee9eef0 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.sv @@ -0,0 +1,2302 @@ +`ifndef rggen_connect_bit_field_if + `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \ + assign FIF.valid = RIF.valid; \ + assign FIF.read_mask = RIF.read_mask[LSB+:WIDTH]; \ + assign FIF.write_mask = RIF.write_mask[LSB+:WIDTH]; \ + assign FIF.write_data = RIF.write_data[LSB+:WIDTH]; \ + assign RIF.read_data[LSB+:WIDTH] = FIF.read_data; \ + assign RIF.value[LSB+:WIDTH] = FIF.value; +`endif +`ifndef rggen_tie_off_unused_signals + `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \ + if (1) begin : __g_tie_off \ + genvar __i; \ + for (__i = 0;__i < WIDTH;++__i) begin : g \ + if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \ + assign RIF.read_data[__i] = 1'b0; \ + assign RIF.value[__i] = 1'b0; \ + end \ + end \ + end +`endif +module block_0 + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 8, + parameter bit PRE_DECODE = 0, + parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, + parameter bit ERROR_STATUS = 0, + parameter bit [31:0] DEFAULT_READ_DATA = '0, + parameter bit INSERT_SLICER = 0, + parameter bit [3:0][1:0] REGISTER_10_BIT_FIELD_1_INITIAL_VALUE = {4{2'h0}} +)( + input logic i_clk, + input logic i_rst_n, + rggen_apb_if.slave apb_if, + output logic [3:0] o_register_0_bit_field_0, + output logic [3:0] o_register_0_bit_field_1, + output logic o_register_0_bit_field_2, + output logic [1:0] o_register_0_bit_field_3, + output logic [1:0] o_register_0_bit_field_4, + output logic [1:0] o_register_0_bit_field_5, + output logic [1:0] o_register_0_bit_field_6, + input logic [1:0] i_register_0_bit_field_6, + output logic o_register_1, + input logic [3:0] i_register_2_bit_field_0, + input logic i_register_2_bit_field_2_latch, + input logic [3:0] i_register_2_bit_field_2, + output logic [3:0] o_register_2_bit_field_2, + input logic [3:0] i_register_2_bit_field_3, + output logic [3:0] o_register_2_bit_field_3, + output logic [3:0] o_register_3_bit_field_0, + output logic [3:0] o_register_3_bit_field_1, + output logic [3:0] o_register_3_bit_field_2_trigger, + output logic [3:0] o_register_3_bit_field_3_trigger, + input logic [3:0] i_register_4_bit_field_0_set, + output logic [3:0] o_register_4_bit_field_0, + input logic [3:0] i_register_4_bit_field_1_set, + output logic [3:0] o_register_4_bit_field_1, + output logic [3:0] o_register_4_bit_field_1_unmasked, + input logic [3:0] i_register_4_bit_field_3_clear, + output logic [3:0] o_register_4_bit_field_3, + input logic i_register_5_bit_field_0_clear, + output logic [1:0] o_register_5_bit_field_0, + output logic [1:0] o_register_5_bit_field_1, + input logic i_register_5_bit_field_2_set, + input logic [1:0] i_register_5_bit_field_2, + output logic [1:0] o_register_5_bit_field_2, + input logic [1:0] i_register_5_bit_field_3, + output logic [1:0] o_register_5_bit_field_3, + input logic i_register_5_bit_field_4_enable, + output logic [1:0] o_register_5_bit_field_4, + output logic [1:0] o_register_5_bit_field_5, + output logic [1:0] o_register_5_bit_field_6, + input logic i_register_5_bit_field_7_lock, + output logic [1:0] o_register_5_bit_field_7, + output logic [1:0] o_register_5_bit_field_8, + output logic [1:0] o_register_5_bit_field_9, + input logic [3:0] i_register_6_bit_field_0_set, + output logic [3:0] o_register_6_bit_field_0, + input logic [3:0] i_register_6_bit_field_1_set, + output logic [3:0] o_register_6_bit_field_1, + output logic [3:0] o_register_6_bit_field_1_unmasked, + input logic [3:0] i_register_6_bit_field_3_set, + output logic [3:0] o_register_6_bit_field_3, + input logic [3:0] i_register_6_bit_field_4_set, + output logic [3:0] o_register_6_bit_field_4, + output logic [3:0] o_register_6_bit_field_4_unmasked, + input logic [3:0] i_register_6_bit_field_6_clear, + output logic [3:0] o_register_6_bit_field_6, + input logic [3:0] i_register_6_bit_field_7_clear, + output logic [3:0] o_register_6_bit_field_7, + output logic [3:0] o_register_6_bit_field_8, + output logic [3:0] o_register_6_bit_field_9, + output logic [3:0] o_register_7_bit_field_0, + output logic [3:0] o_register_7_bit_field_1, + output logic [3:0] o_register_7_bit_field_2, + output logic [3:0] o_register_7_bit_field_3, + input logic [3:0] i_register_8_bit_field_0_set, + output logic [3:0] o_register_8_bit_field_0, + input logic [3:0] i_register_8_bit_field_1_clear, + output logic [3:0] o_register_8_bit_field_1, + input logic [3:0] i_register_8_bit_field_2_set, + output logic [3:0] o_register_8_bit_field_2, + input logic [3:0] i_register_8_bit_field_3_clear, + output logic [3:0] o_register_8_bit_field_3, + output logic [3:0] o_register_8_bit_field_4, + output logic [3:0] o_register_8_bit_field_5, + output logic [1:0] o_register_9_bit_field_0, + output logic o_register_9_bit_field_0_write_trigger, + output logic o_register_9_bit_field_0_read_trigger, + input logic [1:0] i_register_9_bit_field_1, + output logic o_register_9_bit_field_1_read_trigger, + output logic [1:0] o_register_9_bit_field_2, + output logic o_register_9_bit_field_2_write_trigger, + output logic [1:0] o_register_9_bit_field_3, + input logic [1:0] i_register_9_bit_field_3, + output logic o_register_9_bit_field_3_write_trigger, + output logic o_register_9_bit_field_3_read_trigger, + input logic [1:0] i_register_9_bit_field_4, + output logic [1:0] o_register_9_bit_field_4_trigger, + input logic [1:0] i_register_9_bit_field_5, + output logic [1:0] o_register_9_bit_field_5_trigger, + output logic [3:0][3:0][1:0] o_register_10_bit_field_0, + output logic [3:0][3:0][1:0] o_register_10_bit_field_1, + output logic [3:0][3:0][1:0] o_register_10_bit_field_2, + output logic [1:0][3:0][3:0][7:0] o_register_11_bit_field_0, + output logic [1:0][3:0][3:0][7:0] o_register_11_bit_field_1, + output logic o_register_12_bit_field_0, + output logic o_register_12_bit_field_1, + output logic [1:0] o_register_13_bit_field_0, + input logic [1:0] i_register_13_bit_field_1, + output logic [1:0] o_register_13_bit_field_2, + output logic [1:0] o_register_13_bit_field_3, + output logic o_register_13_bit_field_3_write_trigger, + output logic o_register_13_bit_field_3_read_trigger, + output logic [1:0] o_register_13_bit_field_4, + output logic [1:0] o_register_13_bit_field_5, + output logic [1:0] o_register_13_bit_field_6, + input logic [1:0] i_register_13_bit_field_6_hw_clear, + output logic [1:0] o_register_13_bit_field_7, + input logic [1:0] i_register_13_bit_field_7_hw_set, + output logic [1:0] o_register_13_bit_field_8, + input logic i_register_13_bit_field_8_hw_write_enable, + input logic [1:0] i_register_13_bit_field_8_hw_write_data, + rggen_bus_if.master register_15_bus_if +); + rggen_register_if #(8, 32, 64) register_if[25](); + rggen_apb_adapter #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .LOCAL_ADDRESS_WIDTH (8), + .BUS_WIDTH (32), + .REGISTERS (25), + .PRE_DECODE (PRE_DECODE), + .BASE_ADDRESS (BASE_ADDRESS), + .BYTE_SIZE (256), + .ERROR_STATUS (ERROR_STATUS), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA), + .INSERT_SLICER (INSERT_SLICER) + ) u_adapter ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .apb_if (apb_if), + .register_if (register_if) + ); + generate if (1) begin : g_register_0 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h0001ffff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[0]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 9, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 11, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 13, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_5), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_register_0_bit_field_6), + .i_mask ('1), + .o_value (o_register_0_bit_field_6), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_1 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h00000001, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[1]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_register_1 + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_1), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_2 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h00ffff0f, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[2]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4) + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_register_2_bit_field_0), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [7:0] INITIAL_VALUE = 8'hab; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 8) + rggen_bit_field #( + .WIDTH (8), + .STORAGE (0), + .EXTERNAL_READ_DATA (1) + ) u_bit_field ( + .i_clk ('0), + .i_rst_n ('0), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (INITIAL_VALUE), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ACTION (RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_2_bit_field_2_latch), + .i_hw_write_data (i_register_2_bit_field_2), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_2_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ACTION (RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[3].value[16+:1]), + .i_hw_write_data (i_register_2_bit_field_3), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_2_bit_field_3), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_3 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000f0fff, bit_field_if) + rggen_default_register #( + .READABLE (0), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[3]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_3_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ONCE (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_3_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4) + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b0), + .WIDTH (4) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .i_value ('0), + .o_trigger (o_register_3_bit_field_2_trigger) + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4) + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (4) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .i_value ('0), + .o_trigger (o_register_3_bit_field_3_trigger) + ); + end + end endgenerate + generate if (1) begin : g_register_4 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000fff0f, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h0c), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[4]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_4_bit_field_0_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_4_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_4_bit_field_1_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask (register_if[0].value[0+:4]), + .o_value (o_register_4_bit_field_1), + .o_value_unmasked (o_register_4_bit_field_1_unmasked) + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4) + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (register_if[4].value[8+:4]), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_SET), + .SW_WRITE_ACTION (RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (i_register_4_bit_field_3_clear), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_4_bit_field_3), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_5 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h003f3fff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[5]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_CLEAR_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (i_register_5_bit_field_0_clear), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_CLEAR_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (register_if[3].value[8+:1]), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_5_bit_field_2_set), + .i_hw_write_data (i_register_5_bit_field_2), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[3].value[16+:1]), + .i_hw_write_data (i_register_5_bit_field_3), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (i_register_5_bit_field_4_enable), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 10, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (register_if[0].value[8+:1]), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_5), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (register_if[1].value[0+:1]), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_6), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_7 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (i_register_5_bit_field_7_lock), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_7), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_8 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 18, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (register_if[0].value[8+:1]), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_8), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_9 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (register_if[1].value[0+:1]), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_5_bit_field_9), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_6 + rggen_bit_field_if #(64) bit_field_if(); + `rggen_tie_off_unused_signals(64, 64'h000000ffffffffff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h14), + .BUS_WIDTH (32), + .DATA_WIDTH (64), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[6]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_0_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_6_bit_field_0_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_6_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_0_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_6_bit_field_1_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask (register_if[0].value[0+:4]), + .o_value (o_register_6_bit_field_1), + .o_value_unmasked (o_register_6_bit_field_1_unmasked) + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4) + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (register_if[6].value[4+:4]), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_1_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_6_bit_field_3_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_6_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_1_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_6_bit_field_4_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask (register_if[0].value[0+:4]), + .o_value (o_register_6_bit_field_4), + .o_value_unmasked (o_register_6_bit_field_4_unmasked) + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 4) + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (register_if[6].value[16+:4]), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 24, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_0_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (i_register_6_bit_field_6_clear), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_6_bit_field_6), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_7 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 28, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_1_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (i_register_6_bit_field_7_clear), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_6_bit_field_7), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_8 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 32, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ACTION (RGGEN_WRITE_0_TOGGLE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_6_bit_field_8), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_9 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 36, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ACTION (RGGEN_WRITE_1_TOGGLE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_6_bit_field_9), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_7 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h0f0f0f0f, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h1c), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[7]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_SET), + .SW_WRITE_ACTION (RGGEN_WRITE_0_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_7_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_SET), + .SW_WRITE_ACTION (RGGEN_WRITE_1_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_7_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (RGGEN_WRITE_0_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_7_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 24, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (RGGEN_WRITE_1_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_7_bit_field_3), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_8 + rggen_bit_field_if #(64) bit_field_if(); + `rggen_tie_off_unused_signals(64, 64'h00000f0f0f0f0f0f, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h20), + .BUS_WIDTH (32), + .DATA_WIDTH (64), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[8]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_8_bit_field_0_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_8_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (i_register_8_bit_field_1_clear), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_8_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ACTION (RGGEN_WRITE_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_8_bit_field_2_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_8_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 24, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ACTION (RGGEN_WRITE_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (i_register_8_bit_field_3_clear), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_8_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 32, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_SET), + .SW_WRITE_ACTION (RGGEN_WRITE_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_8_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 40, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (RGGEN_WRITE_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_8_bit_field_5), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_9 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h00000fff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h28), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[9]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (o_register_9_bit_field_0_write_trigger), + .o_read_trigger (o_register_9_bit_field_0_read_trigger), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_9_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 2) + rggen_bit_field #( + .WIDTH (2), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_register_9_bit_field_1_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_register_9_bit_field_1), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (o_register_9_bit_field_2_write_trigger), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_9_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (o_register_9_bit_field_3_write_trigger), + .o_read_trigger (o_register_9_bit_field_3_read_trigger), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_register_9_bit_field_3), + .i_mask ('1), + .o_value (o_register_9_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 2) + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b0), + .WIDTH (2) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .i_value (i_register_9_bit_field_4), + .o_trigger (o_register_9_bit_field_4_trigger) + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 10, 2) + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (2) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .i_value (i_register_9_bit_field_5), + .o_trigger (o_register_9_bit_field_5_trigger) + ); + end + end endgenerate + generate if (1) begin : g_register_10 + genvar i; + for (i = 0;i < 4;++i) begin : g + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h3f3f3f3f, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h30+8'(8*i)), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[10+i]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + genvar j; + for (j = 0;j < 4;++j) begin : g + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+8*j, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_10_bit_field_0[i][j]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_1 + genvar j; + for (j = 0;j < 4;++j) begin : g + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2+8*j, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (REGISTER_10_BIT_FIELD_1_INITIAL_VALUE[j]), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_10_bit_field_1[i][j]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_2 + genvar j; + for (j = 0;j < 4;++j) begin : g + localparam bit [1:0] INITIAL_VALUE[4] = '{2'h0, 2'h1, 2'h2, 2'h3}; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4+8*j, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE[j]), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_10_bit_field_2[i][j]), + .o_value_unmasked () + ); + end + end + end + end endgenerate + generate if (1) begin : g_register_11 + genvar i; + genvar j; + for (i = 0;i < 2;++i) begin : g + for (j = 0;j < 4;++j) begin : g + rggen_bit_field_if #(64) bit_field_if(); + logic [8:0] indirect_index; + `rggen_tie_off_unused_signals(64, 64'hffffffffffffffff, bit_field_if) + assign indirect_index = {register_if[0].value[0+:4], register_if[0].value[4+:4], register_if[0].value[8+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h50), + .BUS_WIDTH (32), + .DATA_WIDTH (64), + .VALUE_WIDTH (64), + .INDIRECT_INDEX_WIDTH (9), + .INDIRECT_INDEX_VALUE ({i[0+:4], j[0+:4], 1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[14+4*i+j]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + genvar k; + for (k = 0;k < 4;++k) begin : g + localparam bit [7:0] INITIAL_VALUE = 8'h00; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*k, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_11_bit_field_0[i][j][k]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_1 + genvar k; + for (k = 0;k < 4;++k) begin : g + localparam bit [7:0] INITIAL_VALUE = 8'h00; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*k, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_11_bit_field_1[i][j][k]), + .o_value_unmasked () + ); + end + end + end + end + end endgenerate + generate if (1) begin : g_register_12 + rggen_bit_field_if #(64) bit_field_if(); + logic indirect_index; + `rggen_tie_off_unused_signals(64, 64'h0000000100000001, bit_field_if) + assign indirect_index = {register_if[0].value[8+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h50), + .BUS_WIDTH (32), + .DATA_WIDTH (64), + .VALUE_WIDTH (64), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h1}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[22]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_12_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 32, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_12_bit_field_1), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_13 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h0003ffff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h60), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[23]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE ('0), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_NONE), + .SW_WRITE_ONCE (0), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_register_13_bit_field_1), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (1), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (o_register_13_bit_field_3_write_trigger), + .o_read_trigger (o_register_13_bit_field_3_read_trigger), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (RGGEN_WRITE_1_SET), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 10, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_SET), + .SW_WRITE_ACTION (RGGEN_WRITE_1_CLEAR), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_5), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_1_SET), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear (i_register_13_bit_field_6_hw_clear), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_6), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_7 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 14, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_1_CLEAR), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_13_bit_field_7_hw_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_7), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_8 + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_13_bit_field_8_hw_write_enable), + .i_hw_write_data (i_register_13_bit_field_8_hw_write_data), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_13_bit_field_8), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_15 + rggen_external_register #( + .ADDRESS_WIDTH (8), + .BUS_WIDTH (32), + .VALUE_WIDTH (64), + .START_ADDRESS (8'h80), + .BYTE_SIZE (128) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[24]), + .bus_if (register_15_bus_if) + ); + end endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sample/block_0.toml b/third_party/tests/rggen/rggen-sample/block_0.toml new file mode 100644 index 0000000000..e8f6e18da8 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.toml @@ -0,0 +1,443 @@ +[[register_blocks]] +name = 'block_0' +byte_size = 256 + +[[register_blocks.registers]] +name = 'register_0' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { width = 4 } +type = 'rw' +initial_value = 0 +comment = 'this is register_0.bit_field_0' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { width = 4 } +type = 'rw' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { width = 1 } +type = 'rw' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { width = 2 } +type = 'w1' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_4' +bit_assignment = { width = 2 } +type = 'wrc' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_5' +bit_assignment = { width = 2 } +type = 'wrs' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_6' +bit_assignment = { width = 2 } +type = 'rowo' +initial_value = 0 + +[[register_blocks.registers]] +name = 'register_1' +[[register_blocks.registers.bit_fields]] +bit_assignment = { lsb = 0, width = 1 } +type = 'rw' +initial_value = 0 +labels = [ + { name = 'foo', value = 0, comment = 'FOO value' }, + { name = 'bar', value = 1, comment = 'BAR value' } +] + +[[register_blocks.registers]] +name = 'register_2' +offset_address = 0x08 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 4 } +type = 'ro' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 8, width = 8 } +type = 'rof' +initial_value = 0xab +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 16, width = 4 } +type = 'rol' +initial_value = 0x0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 20, width = 4 } +type = 'rol' +initial_value = 0x0 +reference = 'register_3.bit_field_3' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_4' +bit_assignment = { lsb = 24, width = 8 } +type = 'reserved' + +[[register_blocks.registers]] +name = 'register_3' +offset_address = 0x08 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 4 } +type = 'wo' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 4, width = 4 } +type = 'wo1' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 8, width = 4 } +type = 'w0trg' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 16, width = 4 } +type = 'w1trg' + +[[register_blocks.registers]] +name = 'register_4' +offset_address = 0x0C +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 4 } +type = 'rc' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 8, width = 4 } +type = 'rc' +initial_value = 0 +reference = 'register_0.bit_field_0' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 12, width = 4 } +type = 'ro' +reference = 'register_4.bit_field_1' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 16, width = 4 } +type = 'rs' +initial_value = 0 + +[[register_blocks.registers]] +name = 'register_5' +offset_address = 0x10 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 2 } +type = 'rwc' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 2, width = 2 } +type = 'rwc' +initial_value = 0 +reference = 'register_3.bit_field_2' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 4, width = 2 } +type = 'rws' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 6, width = 2 } +type = 'rws' +initial_value = 0 +reference = 'register_3.bit_field_3' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_4' +bit_assignment = { lsb = 8, width = 2 } +type = 'rwe' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_5' +bit_assignment = { lsb = 10, width = 2 } +type = 'rwe' +initial_value = 0 +reference = 'register_0.bit_field_2' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_6' +bit_assignment = { lsb = 12, width = 2 } +type = 'rwe' +initial_value = 0 +reference = 'register_1' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_7' +bit_assignment = { lsb = 16, width = 2 } +type = 'rwl' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_8' +bit_assignment = { lsb = 18, width = 2 } +type = 'rwl' +initial_value = 0 +reference = 'register_0.bit_field_2' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_9' +bit_assignment = { lsb = 20, width = 2 } +type = 'rwl' +initial_value = 0 +reference = 'register_1' + +[[register_blocks.registers]] +name = 'register_6' +offset_address = 0x14 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 4 } +type = 'w0c' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 4, width = 4 } +type = 'w0c' +initial_value = 0 +reference = 'register_0.bit_field_0' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 8, width = 4 } +type = 'ro' +reference = 'register_6.bit_field_1' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 12, width = 4 } +type = 'w1c' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_4' +bit_assignment = { lsb = 16, width = 4 } +type = 'w1c' +initial_value = 0 +reference = 'register_0.bit_field_0' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_5' +bit_assignment = { lsb = 20, width = 4 } +type = 'ro' +reference = 'register_6.bit_field_4' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_6' +bit_assignment = { lsb = 24, width = 4 } +type = 'w0s' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_7' +bit_assignment = { lsb = 28, width = 4 } +type = 'w1s' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_8' +bit_assignment = { lsb = 32, width = 4 } +type = 'w0t' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_9' +bit_assignment = { lsb = 36, width = 4 } +type = 'w1t' +initial_value = 0 + +[[register_blocks.registers]] +name = 'register_7' +offset_address = 0x1C +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 4 } +type = 'w0crs' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 8, width = 4 } +type = 'w1crs' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 16, width = 4 } +type = 'w0src' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 24, width = 4 } +type = 'w1src' +initial_value = 0 + +[[register_blocks.registers]] +name = 'register_8' +offset_address = 0x20 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 4 } +type = 'wc' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 8, width = 4 } +type = 'ws' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 16, width = 4 } +type = 'woc' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 24, width = 4 } +type = 'wos' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_4' +bit_assignment = { lsb = 32, width = 4 } +type = 'wcrs' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_5' +bit_assignment = { lsb = 40, width = 4 } +type = 'wsrc' +initial_value = 0 + +[[register_blocks.registers]] +name = 'register_9' +offset_address = 0x28 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 2 } +type = 'rwtrg' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 2, width = 2 } +type = 'rotrg' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 4, width = 2 } +type = 'wotrg' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { lsb = 6, width = 2 } +type = 'rowotrg' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_4' +bit_assignment = { lsb = 8, width = 2 } +type = 'row0trg' +[[register_blocks.registers.bit_fields]] +name = 'bit_field_5' +bit_assignment = { lsb = 10, width = 2 } +type = 'row1trg' + +[[register_blocks.registers]] +name = 'register_10' +offset_address = 0x30 +size = [4, { step = 8 }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 2, sequence_size = 4, step = 8 } +type = 'rw' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 2, width = 2, sequence_size = 4, step = 8 } +type = 'rw' +initial_value = { default = 0 } +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 4, width = 2, sequence_size = 4, step = 8 } +type = 'rw' +initial_value = [0, 1, 2, 3] + +[[register_blocks.registers]] +name = 'register_11' +offset_address = 0x50 +size = [2, 4] +type = ['indirect', 'register_0.bit_field_0', 'register_0.bit_field_1', ['register_0.bit_field_2', 0]] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 8, sequence_size = 4, step = 16 } +type = 'rw' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 8, width = 8, sequence_size = 4, step = 16 } +type = 'rw' +initial_value = 0 + +[[register_blocks.registers]] +name = 'register_12' +offset_address = 0x50 +type = ['indirect', ['register_0.bit_field_2', 1]] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 1 } +type = 'rw' +initial_value = 0 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 32, width = 1 } +type = 'rw' +initial_value = 0 + +[[register_blocks.registers]] +name = 'register_13' +offset_address = 0x60 +[[register_blocks.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom'] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { width = 2 } +type = ['custom', { sw_write = 'none' }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom', { sw_write_once = true }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_3' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom', { write_trigger = true, read_trigger = true }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_4' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom', { sw_write = 'set_1', sw_read = 'clear' }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_5' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom', { sw_write = 'clear_1', sw_read = 'set' }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_6' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom', { sw_write = 'set_1', hw_clear = true }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_7' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom', { sw_write = 'clear_1', hw_set = true }] +[[register_blocks.registers.bit_fields]] +name = 'bit_field_8' +bit_assignment = { width = 2 } +initial_value = 0 +type = ['custom', { hw_write = true }] + +[[register_blocks.registers]] +name = 'register_14' +offset_address = 0x70 +type = 'reserved' + +[[register_blocks.registers]] +name = 'register_15' +offset_address = 0x80 +size = 32 +type = 'external' diff --git a/third_party/tests/rggen/rggen-sample/block_0.v b/third_party/tests/rggen/rggen-sample/block_0.v new file mode 100644 index 0000000000..9980bad2eb --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.v @@ -0,0 +1,2748 @@ +`include "rggen_rtl_macros.vh" +module block_0 #( + parameter ADDRESS_WIDTH = 8, + parameter PRE_DECODE = 0, + parameter [ADDRESS_WIDTH-1:0] BASE_ADDRESS = 0, + parameter ERROR_STATUS = 0, + parameter [31:0] DEFAULT_READ_DATA = 0, + parameter INSERT_SLICER = 0, + parameter [7:0] REGISTER_10_BIT_FIELD_1_INITIAL_VALUE = {4{2'h0}} +)( + input i_clk, + input i_rst_n, + input i_psel, + input i_penable, + input [ADDRESS_WIDTH-1:0] i_paddr, + input [2:0] i_pprot, + input i_pwrite, + input [3:0] i_pstrb, + input [31:0] i_pwdata, + output o_pready, + output [31:0] o_prdata, + output o_pslverr, + output [3:0] o_register_0_bit_field_0, + output [3:0] o_register_0_bit_field_1, + output o_register_0_bit_field_2, + output [1:0] o_register_0_bit_field_3, + output [1:0] o_register_0_bit_field_4, + output [1:0] o_register_0_bit_field_5, + output [1:0] o_register_0_bit_field_6, + input [1:0] i_register_0_bit_field_6, + output o_register_1, + input [3:0] i_register_2_bit_field_0, + input i_register_2_bit_field_2_latch, + input [3:0] i_register_2_bit_field_2, + output [3:0] o_register_2_bit_field_2, + input [3:0] i_register_2_bit_field_3, + output [3:0] o_register_2_bit_field_3, + output [3:0] o_register_3_bit_field_0, + output [3:0] o_register_3_bit_field_1, + output [3:0] o_register_3_bit_field_2_trigger, + output [3:0] o_register_3_bit_field_3_trigger, + input [3:0] i_register_4_bit_field_0_set, + output [3:0] o_register_4_bit_field_0, + input [3:0] i_register_4_bit_field_1_set, + output [3:0] o_register_4_bit_field_1, + output [3:0] o_register_4_bit_field_1_unmasked, + input [3:0] i_register_4_bit_field_3_clear, + output [3:0] o_register_4_bit_field_3, + input i_register_5_bit_field_0_clear, + output [1:0] o_register_5_bit_field_0, + output [1:0] o_register_5_bit_field_1, + input i_register_5_bit_field_2_set, + input [1:0] i_register_5_bit_field_2, + output [1:0] o_register_5_bit_field_2, + input [1:0] i_register_5_bit_field_3, + output [1:0] o_register_5_bit_field_3, + input i_register_5_bit_field_4_enable, + output [1:0] o_register_5_bit_field_4, + output [1:0] o_register_5_bit_field_5, + output [1:0] o_register_5_bit_field_6, + input i_register_5_bit_field_7_lock, + output [1:0] o_register_5_bit_field_7, + output [1:0] o_register_5_bit_field_8, + output [1:0] o_register_5_bit_field_9, + input [3:0] i_register_6_bit_field_0_set, + output [3:0] o_register_6_bit_field_0, + input [3:0] i_register_6_bit_field_1_set, + output [3:0] o_register_6_bit_field_1, + output [3:0] o_register_6_bit_field_1_unmasked, + input [3:0] i_register_6_bit_field_3_set, + output [3:0] o_register_6_bit_field_3, + input [3:0] i_register_6_bit_field_4_set, + output [3:0] o_register_6_bit_field_4, + output [3:0] o_register_6_bit_field_4_unmasked, + input [3:0] i_register_6_bit_field_6_clear, + output [3:0] o_register_6_bit_field_6, + input [3:0] i_register_6_bit_field_7_clear, + output [3:0] o_register_6_bit_field_7, + output [3:0] o_register_6_bit_field_8, + output [3:0] o_register_6_bit_field_9, + output [3:0] o_register_7_bit_field_0, + output [3:0] o_register_7_bit_field_1, + output [3:0] o_register_7_bit_field_2, + output [3:0] o_register_7_bit_field_3, + input [3:0] i_register_8_bit_field_0_set, + output [3:0] o_register_8_bit_field_0, + input [3:0] i_register_8_bit_field_1_clear, + output [3:0] o_register_8_bit_field_1, + input [3:0] i_register_8_bit_field_2_set, + output [3:0] o_register_8_bit_field_2, + input [3:0] i_register_8_bit_field_3_clear, + output [3:0] o_register_8_bit_field_3, + output [3:0] o_register_8_bit_field_4, + output [3:0] o_register_8_bit_field_5, + output [1:0] o_register_9_bit_field_0, + output o_register_9_bit_field_0_write_trigger, + output o_register_9_bit_field_0_read_trigger, + input [1:0] i_register_9_bit_field_1, + output o_register_9_bit_field_1_read_trigger, + output [1:0] o_register_9_bit_field_2, + output o_register_9_bit_field_2_write_trigger, + output [1:0] o_register_9_bit_field_3, + input [1:0] i_register_9_bit_field_3, + output o_register_9_bit_field_3_write_trigger, + output o_register_9_bit_field_3_read_trigger, + input [1:0] i_register_9_bit_field_4, + output [1:0] o_register_9_bit_field_4_trigger, + input [1:0] i_register_9_bit_field_5, + output [1:0] o_register_9_bit_field_5_trigger, + output [31:0] o_register_10_bit_field_0, + output [31:0] o_register_10_bit_field_1, + output [31:0] o_register_10_bit_field_2, + output [255:0] o_register_11_bit_field_0, + output [255:0] o_register_11_bit_field_1, + output o_register_12_bit_field_0, + output o_register_12_bit_field_1, + output [1:0] o_register_13_bit_field_0, + input [1:0] i_register_13_bit_field_1, + output [1:0] o_register_13_bit_field_2, + output [1:0] o_register_13_bit_field_3, + output o_register_13_bit_field_3_write_trigger, + output o_register_13_bit_field_3_read_trigger, + output [1:0] o_register_13_bit_field_4, + output [1:0] o_register_13_bit_field_5, + output [1:0] o_register_13_bit_field_6, + input [1:0] i_register_13_bit_field_6_hw_clear, + output [1:0] o_register_13_bit_field_7, + input [1:0] i_register_13_bit_field_7_hw_set, + output [1:0] o_register_13_bit_field_8, + input i_register_13_bit_field_8_hw_write_enable, + input [1:0] i_register_13_bit_field_8_hw_write_data, + output o_register_15_valid, + output [1:0] o_register_15_access, + output [7:0] o_register_15_address, + output [31:0] o_register_15_data, + output [3:0] o_register_15_strobe, + input i_register_15_ready, + input [1:0] i_register_15_status, + input [31:0] i_register_15_data +); + wire w_register_valid; + wire [1:0] w_register_access; + wire [7:0] w_register_address; + wire [31:0] w_register_write_data; + wire [3:0] w_register_strobe; + wire [24:0] w_register_active; + wire [24:0] w_register_ready; + wire [49:0] w_register_status; + wire [799:0] w_register_read_data; + wire [1599:0] w_register_value; + rggen_apb_adapter #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .LOCAL_ADDRESS_WIDTH (8), + .BUS_WIDTH (32), + .REGISTERS (25), + .PRE_DECODE (PRE_DECODE), + .BASE_ADDRESS (BASE_ADDRESS), + .BYTE_SIZE (256), + .ERROR_STATUS (ERROR_STATUS), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA), + .INSERT_SLICER (INSERT_SLICER) + ) u_adapter ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_psel (i_psel), + .i_penable (i_penable), + .i_paddr (i_paddr), + .i_pprot (i_pprot), + .i_pwrite (i_pwrite), + .i_pstrb (i_pstrb), + .i_pwdata (i_pwdata), + .o_pready (o_pready), + .o_prdata (o_prdata), + .o_pslverr (o_pslverr), + .o_register_valid (w_register_valid), + .o_register_access (w_register_access), + .o_register_address (w_register_address), + .o_register_write_data (w_register_write_data), + .o_register_strobe (w_register_strobe), + .i_register_active (w_register_active), + .i_register_ready (w_register_ready), + .i_register_status (w_register_status), + .i_register_read_data (w_register_read_data) + ); + generate if (1) begin : g_register_0 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h0001ffff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[0+:1]), + .o_register_ready (w_register_ready[0+:1]), + .o_register_status (w_register_status[0+:2]), + .o_register_read_data (w_register_read_data[0+:32]), + .o_register_value (w_register_value[0+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:4]), + .i_sw_write_data (w_bit_field_write_data[0+:4]), + .o_sw_read_data (w_bit_field_read_data[0+:4]), + .o_sw_value (w_bit_field_value[0+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_0_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:4]), + .i_sw_write_data (w_bit_field_write_data[4+:4]), + .o_sw_read_data (w_bit_field_read_data[4+:4]), + .o_sw_value (w_bit_field_value[4+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_0_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[8+:1]), + .i_sw_write_data (w_bit_field_write_data[8+:1]), + .o_sw_read_data (w_bit_field_read_data[8+:1]), + .o_sw_value (w_bit_field_value[8+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_register_0_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ONCE (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[9+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[9+:2]), + .i_sw_write_data (w_bit_field_write_data[9+:2]), + .o_sw_read_data (w_bit_field_read_data[9+:2]), + .o_sw_value (w_bit_field_value[9+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_0_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[11+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[11+:2]), + .i_sw_write_data (w_bit_field_write_data[11+:2]), + .o_sw_read_data (w_bit_field_read_data[11+:2]), + .o_sw_value (w_bit_field_value[11+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_0_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[13+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[13+:2]), + .i_sw_write_data (w_bit_field_write_data[13+:2]), + .o_sw_read_data (w_bit_field_read_data[13+:2]), + .o_sw_value (w_bit_field_value[13+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_0_bit_field_5), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[15+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[15+:2]), + .i_sw_write_data (w_bit_field_write_data[15+:2]), + .o_sw_read_data (w_bit_field_read_data[15+:2]), + .o_sw_value (w_bit_field_value[15+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value (i_register_0_bit_field_6), + .i_mask ({2{1'b1}}), + .o_value (o_register_0_bit_field_6), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_1 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h00000001, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1+:1]), + .o_register_ready (w_register_ready[1+:1]), + .o_register_status (w_register_status[2+:2]), + .o_register_read_data (w_register_read_data[32+:32]), + .o_register_value (w_register_value[64+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_register_1 + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_register_1), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_2 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h00ffff0f, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[2+:1]), + .o_register_ready (w_register_ready[2+:1]), + .o_register_status (w_register_status[4+:2]), + .o_register_read_data (w_register_read_data[64+:32]), + .o_register_value (w_register_value[128+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:4]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[0+:4]), + .i_sw_write_data (w_bit_field_write_data[0+:4]), + .o_sw_read_data (w_bit_field_read_data[0+:4]), + .o_sw_value (w_bit_field_value[0+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value (i_register_2_bit_field_0), + .i_mask ({4{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (8), + .STORAGE (0), + .EXTERNAL_READ_DATA (1) + ) u_bit_field ( + .i_clk (1'b0), + .i_rst_n (1'b0), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:8]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[8+:8]), + .i_sw_write_data (w_bit_field_write_data[8+:8]), + .o_sw_read_data (w_bit_field_read_data[8+:8]), + .o_sw_value (w_bit_field_value[8+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value (8'hab), + .i_mask ({8{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ACTION (`RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[16+:4]), + .i_sw_write_data (w_bit_field_write_data[16+:4]), + .o_sw_read_data (w_bit_field_read_data[16+:4]), + .o_sw_value (w_bit_field_value[16+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (i_register_2_bit_field_2_latch), + .i_hw_write_data (i_register_2_bit_field_2), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_2_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ACTION (`RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[20+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[20+:4]), + .i_sw_write_data (w_bit_field_write_data[20+:4]), + .o_sw_read_data (w_bit_field_read_data[20+:4]), + .o_sw_value (w_bit_field_value[20+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (w_register_value[208+:1]), + .i_hw_write_data (i_register_2_bit_field_3), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_2_bit_field_3), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_3 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000f0fff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (0), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[3+:1]), + .o_register_ready (w_register_ready[3+:1]), + .o_register_status (w_register_status[6+:2]), + .o_register_read_data (w_register_read_data[96+:32]), + .o_register_value (w_register_value[192+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:4]), + .i_sw_write_data (w_bit_field_write_data[0+:4]), + .o_sw_read_data (w_bit_field_read_data[0+:4]), + .o_sw_value (w_bit_field_value[0+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_3_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ONCE (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:4]), + .i_sw_write_data (w_bit_field_write_data[4+:4]), + .o_sw_read_data (w_bit_field_read_data[4+:4]), + .o_sw_value (w_bit_field_value[4+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_3_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b0), + .WIDTH (4) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[8+:4]), + .i_sw_write_data (w_bit_field_write_data[8+:4]), + .o_sw_read_data (w_bit_field_read_data[8+:4]), + .o_sw_value (w_bit_field_value[8+:4]), + .i_value ({4{1'b0}}), + .o_trigger (o_register_3_bit_field_2_trigger) + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (4) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[16+:4]), + .i_sw_write_data (w_bit_field_write_data[16+:4]), + .o_sw_read_data (w_bit_field_read_data[16+:4]), + .o_sw_value (w_bit_field_value[16+:4]), + .i_value ({4{1'b0}}), + .o_trigger (o_register_3_bit_field_3_trigger) + ); + end + end endgenerate + generate if (1) begin : g_register_4 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000fff0f, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h0c), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[4+:1]), + .o_register_ready (w_register_ready[4+:1]), + .o_register_status (w_register_status[8+:2]), + .o_register_read_data (w_register_read_data[128+:32]), + .o_register_value (w_register_value[256+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (`RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:4]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[0+:4]), + .i_sw_write_data (w_bit_field_write_data[0+:4]), + .o_sw_read_data (w_bit_field_read_data[0+:4]), + .o_sw_value (w_bit_field_value[0+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_4_bit_field_0_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_4_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (`RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:4]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[8+:4]), + .i_sw_write_data (w_bit_field_write_data[8+:4]), + .o_sw_read_data (w_bit_field_read_data[8+:4]), + .o_sw_value (w_bit_field_value[8+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_4_bit_field_1_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask (w_register_value[0+:4]), + .o_value (o_register_4_bit_field_1), + .o_value_unmasked (o_register_4_bit_field_1_unmasked) + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[12+:4]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[12+:4]), + .i_sw_write_data (w_bit_field_write_data[12+:4]), + .o_sw_read_data (w_bit_field_read_data[12+:4]), + .o_sw_value (w_bit_field_value[12+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value (w_register_value[264+:4]), + .i_mask ({4{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_SET), + .SW_WRITE_ACTION (`RGGEN_WRITE_NONE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:4]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[16+:4]), + .i_sw_write_data (w_bit_field_write_data[16+:4]), + .o_sw_read_data (w_bit_field_read_data[16+:4]), + .o_sw_value (w_bit_field_value[16+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear (i_register_4_bit_field_3_clear), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_4_bit_field_3), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_5 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h003f3fff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[5+:1]), + .o_register_ready (w_register_ready[5+:1]), + .o_register_status (w_register_status[10+:2]), + .o_register_read_data (w_register_read_data[160+:32]), + .o_register_value (w_register_value[320+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .HW_CLEAR_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:2]), + .i_sw_write_data (w_bit_field_write_data[0+:2]), + .o_sw_read_data (w_bit_field_read_data[0+:2]), + .o_sw_value (w_bit_field_value[0+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear (i_register_5_bit_field_0_clear), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .HW_CLEAR_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[2+:2]), + .i_sw_write_data (w_bit_field_write_data[2+:2]), + .o_sw_read_data (w_bit_field_read_data[2+:2]), + .o_sw_value (w_bit_field_value[2+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear (w_register_value[200+:1]), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:2]), + .i_sw_write_data (w_bit_field_write_data[4+:2]), + .o_sw_read_data (w_bit_field_read_data[4+:2]), + .o_sw_value (w_bit_field_value[4+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (i_register_5_bit_field_2_set), + .i_hw_write_data (i_register_5_bit_field_2), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[6+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[6+:2]), + .i_sw_write_data (w_bit_field_write_data[6+:2]), + .o_sw_read_data (w_bit_field_read_data[6+:2]), + .o_sw_value (w_bit_field_value[6+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (w_register_value[208+:1]), + .i_hw_write_data (i_register_5_bit_field_3), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:2]), + .i_sw_write_enable (i_register_5_bit_field_4_enable), + .i_sw_write_mask (w_bit_field_write_mask[8+:2]), + .i_sw_write_data (w_bit_field_write_data[8+:2]), + .o_sw_read_data (w_bit_field_read_data[8+:2]), + .o_sw_value (w_bit_field_value[8+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[10+:2]), + .i_sw_write_enable (w_register_value[8+:1]), + .i_sw_write_mask (w_bit_field_write_mask[10+:2]), + .i_sw_write_data (w_bit_field_write_data[10+:2]), + .o_sw_read_data (w_bit_field_read_data[10+:2]), + .o_sw_value (w_bit_field_value[10+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_5), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[12+:2]), + .i_sw_write_enable (w_register_value[64+:1]), + .i_sw_write_mask (w_bit_field_write_mask[12+:2]), + .i_sw_write_data (w_bit_field_write_data[12+:2]), + .o_sw_read_data (w_bit_field_read_data[12+:2]), + .o_sw_value (w_bit_field_value[12+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_6), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_7 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:2]), + .i_sw_write_enable (i_register_5_bit_field_7_lock), + .i_sw_write_mask (w_bit_field_write_mask[16+:2]), + .i_sw_write_data (w_bit_field_write_data[16+:2]), + .o_sw_read_data (w_bit_field_read_data[16+:2]), + .o_sw_value (w_bit_field_value[16+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_7), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_8 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[18+:2]), + .i_sw_write_enable (w_register_value[8+:1]), + .i_sw_write_mask (w_bit_field_write_mask[18+:2]), + .i_sw_write_data (w_bit_field_write_data[18+:2]), + .o_sw_read_data (w_bit_field_read_data[18+:2]), + .o_sw_value (w_bit_field_value[18+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_8), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_9 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[20+:2]), + .i_sw_write_enable (w_register_value[64+:1]), + .i_sw_write_mask (w_bit_field_write_mask[20+:2]), + .i_sw_write_data (w_bit_field_write_data[20+:2]), + .o_sw_read_data (w_bit_field_read_data[20+:2]), + .o_sw_value (w_bit_field_value[20+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_5_bit_field_9), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_6 + wire w_bit_field_valid; + wire [63:0] w_bit_field_read_mask; + wire [63:0] w_bit_field_write_mask; + wire [63:0] w_bit_field_write_data; + wire [63:0] w_bit_field_read_data; + wire [63:0] w_bit_field_value; + `rggen_tie_off_unused_signals(64, 64'h000000ffffffffff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h14), + .BUS_WIDTH (32), + .DATA_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[6+:1]), + .o_register_ready (w_register_ready[6+:1]), + .o_register_status (w_register_status[12+:2]), + .o_register_read_data (w_register_read_data[192+:32]), + .o_register_value (w_register_value[384+:64]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_0_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:4]), + .i_sw_write_data (w_bit_field_write_data[0+:4]), + .o_sw_read_data (w_bit_field_read_data[0+:4]), + .o_sw_value (w_bit_field_value[0+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_6_bit_field_0_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_6_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_0_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:4]), + .i_sw_write_data (w_bit_field_write_data[4+:4]), + .o_sw_read_data (w_bit_field_read_data[4+:4]), + .o_sw_value (w_bit_field_value[4+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_6_bit_field_1_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask (w_register_value[0+:4]), + .o_value (o_register_6_bit_field_1), + .o_value_unmasked (o_register_6_bit_field_1_unmasked) + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:4]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[8+:4]), + .i_sw_write_data (w_bit_field_write_data[8+:4]), + .o_sw_read_data (w_bit_field_read_data[8+:4]), + .o_sw_value (w_bit_field_value[8+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value (w_register_value[388+:4]), + .i_mask ({4{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[12+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[12+:4]), + .i_sw_write_data (w_bit_field_write_data[12+:4]), + .o_sw_read_data (w_bit_field_read_data[12+:4]), + .o_sw_value (w_bit_field_value[12+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_6_bit_field_3_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_6_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[16+:4]), + .i_sw_write_data (w_bit_field_write_data[16+:4]), + .o_sw_read_data (w_bit_field_read_data[16+:4]), + .o_sw_value (w_bit_field_value[16+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_6_bit_field_4_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask (w_register_value[0+:4]), + .o_value (o_register_6_bit_field_4), + .o_value_unmasked (o_register_6_bit_field_4_unmasked) + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field #( + .WIDTH (4), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[20+:4]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[20+:4]), + .i_sw_write_data (w_bit_field_write_data[20+:4]), + .o_sw_read_data (w_bit_field_read_data[20+:4]), + .o_sw_value (w_bit_field_value[20+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value (w_register_value[400+:4]), + .i_mask ({4{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_0_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[24+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[24+:4]), + .i_sw_write_data (w_bit_field_write_data[24+:4]), + .o_sw_read_data (w_bit_field_read_data[24+:4]), + .o_sw_value (w_bit_field_value[24+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear (i_register_6_bit_field_6_clear), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_6_bit_field_6), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_7 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[28+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[28+:4]), + .i_sw_write_data (w_bit_field_write_data[28+:4]), + .o_sw_read_data (w_bit_field_read_data[28+:4]), + .o_sw_value (w_bit_field_value[28+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear (i_register_6_bit_field_7_clear), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_6_bit_field_7), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_8 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ACTION (`RGGEN_WRITE_0_TOGGLE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[32+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[32+:4]), + .i_sw_write_data (w_bit_field_write_data[32+:4]), + .o_sw_read_data (w_bit_field_read_data[32+:4]), + .o_sw_value (w_bit_field_value[32+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_6_bit_field_8), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_9 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_TOGGLE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[36+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[36+:4]), + .i_sw_write_data (w_bit_field_write_data[36+:4]), + .o_sw_read_data (w_bit_field_read_data[36+:4]), + .o_sw_value (w_bit_field_value[36+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_6_bit_field_9), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_7 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h0f0f0f0f, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h1c), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[7+:1]), + .o_register_ready (w_register_ready[7+:1]), + .o_register_status (w_register_status[14+:2]), + .o_register_read_data (w_register_read_data[224+:32]), + .o_register_value (w_register_value[448+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_SET), + .SW_WRITE_ACTION (`RGGEN_WRITE_0_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:4]), + .i_sw_write_data (w_bit_field_write_data[0+:4]), + .o_sw_read_data (w_bit_field_read_data[0+:4]), + .o_sw_value (w_bit_field_value[0+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_7_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_SET), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[8+:4]), + .i_sw_write_data (w_bit_field_write_data[8+:4]), + .o_sw_read_data (w_bit_field_read_data[8+:4]), + .o_sw_value (w_bit_field_value[8+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_7_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (`RGGEN_WRITE_0_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[16+:4]), + .i_sw_write_data (w_bit_field_write_data[16+:4]), + .o_sw_read_data (w_bit_field_read_data[16+:4]), + .o_sw_value (w_bit_field_value[16+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_7_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[24+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[24+:4]), + .i_sw_write_data (w_bit_field_write_data[24+:4]), + .o_sw_read_data (w_bit_field_read_data[24+:4]), + .o_sw_value (w_bit_field_value[24+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_7_bit_field_3), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_8 + wire w_bit_field_valid; + wire [63:0] w_bit_field_read_mask; + wire [63:0] w_bit_field_write_mask; + wire [63:0] w_bit_field_write_data; + wire [63:0] w_bit_field_read_data; + wire [63:0] w_bit_field_value; + `rggen_tie_off_unused_signals(64, 64'h00000f0f0f0f0f0f, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h20), + .BUS_WIDTH (32), + .DATA_WIDTH (64) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[8+:1]), + .o_register_ready (w_register_ready[8+:1]), + .o_register_status (w_register_status[16+:2]), + .o_register_read_data (w_register_read_data[256+:32]), + .o_register_value (w_register_value[512+:64]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:4]), + .i_sw_write_data (w_bit_field_write_data[0+:4]), + .o_sw_read_data (w_bit_field_read_data[0+:4]), + .o_sw_value (w_bit_field_value[0+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_8_bit_field_0_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_8_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[8+:4]), + .i_sw_write_data (w_bit_field_write_data[8+:4]), + .o_sw_read_data (w_bit_field_read_data[8+:4]), + .o_sw_value (w_bit_field_value[8+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear (i_register_8_bit_field_1_clear), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_8_bit_field_1), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ACTION (`RGGEN_WRITE_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[16+:4]), + .i_sw_write_data (w_bit_field_write_data[16+:4]), + .o_sw_read_data (w_bit_field_read_data[16+:4]), + .o_sw_value (w_bit_field_value[16+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set (i_register_8_bit_field_2_set), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_8_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ACTION (`RGGEN_WRITE_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[24+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[24+:4]), + .i_sw_write_data (w_bit_field_write_data[24+:4]), + .o_sw_read_data (w_bit_field_read_data[24+:4]), + .o_sw_value (w_bit_field_value[24+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear (i_register_8_bit_field_3_clear), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_8_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_SET), + .SW_WRITE_ACTION (`RGGEN_WRITE_CLEAR) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[32+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[32+:4]), + .i_sw_write_data (w_bit_field_write_data[32+:4]), + .o_sw_read_data (w_bit_field_read_data[32+:4]), + .o_sw_value (w_bit_field_value[32+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_8_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_READ_ACTION (`RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (`RGGEN_WRITE_SET) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[40+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[40+:4]), + .i_sw_write_data (w_bit_field_write_data[40+:4]), + .o_sw_read_data (w_bit_field_read_data[40+:4]), + .o_sw_value (w_bit_field_value[40+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_8_bit_field_5), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_9 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h00000fff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h28), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[9+:1]), + .o_register_ready (w_register_ready[9+:1]), + .o_register_status (w_register_status[18+:2]), + .o_register_read_data (w_register_read_data[288+:32]), + .o_register_value (w_register_value[576+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:2]), + .i_sw_write_data (w_bit_field_write_data[0+:2]), + .o_sw_read_data (w_bit_field_read_data[0+:2]), + .o_sw_value (w_bit_field_value[0+:2]), + .o_write_trigger (o_register_9_bit_field_0_write_trigger), + .o_read_trigger (o_register_9_bit_field_0_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_9_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (2), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:2]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[2+:2]), + .i_sw_write_data (w_bit_field_write_data[2+:2]), + .o_sw_read_data (w_bit_field_read_data[2+:2]), + .o_sw_value (w_bit_field_value[2+:2]), + .o_write_trigger (), + .o_read_trigger (o_register_9_bit_field_1_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value (i_register_9_bit_field_1), + .i_mask ({2{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:2]), + .i_sw_write_data (w_bit_field_write_data[4+:2]), + .o_sw_read_data (w_bit_field_read_data[4+:2]), + .o_sw_value (w_bit_field_value[4+:2]), + .o_write_trigger (o_register_9_bit_field_2_write_trigger), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_9_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[6+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[6+:2]), + .i_sw_write_data (w_bit_field_write_data[6+:2]), + .o_sw_read_data (w_bit_field_read_data[6+:2]), + .o_sw_value (w_bit_field_value[6+:2]), + .o_write_trigger (o_register_9_bit_field_3_write_trigger), + .o_read_trigger (o_register_9_bit_field_3_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value (i_register_9_bit_field_3), + .i_mask ({2{1'b1}}), + .o_value (o_register_9_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b0), + .WIDTH (2) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[8+:2]), + .i_sw_write_data (w_bit_field_write_data[8+:2]), + .o_sw_read_data (w_bit_field_read_data[8+:2]), + .o_sw_value (w_bit_field_value[8+:2]), + .i_value (i_register_9_bit_field_4), + .o_trigger (o_register_9_bit_field_4_trigger) + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (2) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[10+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[10+:2]), + .i_sw_write_data (w_bit_field_write_data[10+:2]), + .o_sw_read_data (w_bit_field_read_data[10+:2]), + .o_sw_value (w_bit_field_value[10+:2]), + .i_value (i_register_9_bit_field_5), + .o_trigger (o_register_9_bit_field_5_trigger) + ); + end + end endgenerate + generate if (1) begin : g_register_10 + genvar i; + for (i = 0;i < 4;i = i + 1) begin : g + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h3f3f3f3f, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h30+8*i), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1*(10+i)+:1]), + .o_register_ready (w_register_ready[1*(10+i)+:1]), + .o_register_status (w_register_status[2*(10+i)+:2]), + .o_register_read_data (w_register_read_data[32*(10+i)+:32]), + .o_register_value (w_register_value[64*(10+i)+0+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + genvar j; + for (j = 0;j < 4;j = j + 1) begin : g + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+8*j+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+8*j+:2]), + .i_sw_write_data (w_bit_field_write_data[0+8*j+:2]), + .o_sw_read_data (w_bit_field_read_data[0+8*j+:2]), + .o_sw_value (w_bit_field_value[0+8*j+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_10_bit_field_0[2*(4*i+j)+:2]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_1 + genvar j; + for (j = 0;j < 4;j = j + 1) begin : g + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (`rggen_slice(REGISTER_10_BIT_FIELD_1_INITIAL_VALUE, 8, 2, j)), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+8*j+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[2+8*j+:2]), + .i_sw_write_data (w_bit_field_write_data[2+8*j+:2]), + .o_sw_read_data (w_bit_field_read_data[2+8*j+:2]), + .o_sw_value (w_bit_field_value[2+8*j+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_10_bit_field_1[2*(4*i+j)+:2]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_2 + genvar j; + for (j = 0;j < 4;j = j + 1) begin : g + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (`rggen_slice(8'he4, 8, 2, j)), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+8*j+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+8*j+:2]), + .i_sw_write_data (w_bit_field_write_data[4+8*j+:2]), + .o_sw_read_data (w_bit_field_read_data[4+8*j+:2]), + .o_sw_value (w_bit_field_value[4+8*j+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_10_bit_field_2[2*(4*i+j)+:2]), + .o_value_unmasked () + ); + end + end + end + end endgenerate + generate if (1) begin : g_register_11 + genvar i; + genvar j; + for (i = 0;i < 2;i = i + 1) begin : g + for (j = 0;j < 4;j = j + 1) begin : g + wire w_bit_field_valid; + wire [63:0] w_bit_field_read_mask; + wire [63:0] w_bit_field_write_mask; + wire [63:0] w_bit_field_write_data; + wire [63:0] w_bit_field_read_data; + wire [63:0] w_bit_field_value; + wire [8:0] w_indirect_index; + `rggen_tie_off_unused_signals(64, 64'hffffffffffffffff, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[0+:4], w_register_value[4+:4], w_register_value[8+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h50), + .BUS_WIDTH (32), + .DATA_WIDTH (64), + .INDIRECT_INDEX_WIDTH (9), + .INDIRECT_INDEX_VALUE ({i[0+:4], j[0+:4], 1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1*(14+4*i+j)+:1]), + .o_register_ready (w_register_ready[1*(14+4*i+j)+:1]), + .o_register_status (w_register_status[2*(14+4*i+j)+:2]), + .o_register_read_data (w_register_read_data[32*(14+4*i+j)+:32]), + .o_register_value (w_register_value[64*(14+4*i+j)+0+:64]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + genvar k; + for (k = 0;k < 4;k = k + 1) begin : g + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'h00), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+16*k+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+16*k+:8]), + .i_sw_write_data (w_bit_field_write_data[0+16*k+:8]), + .o_sw_read_data (w_bit_field_read_data[0+16*k+:8]), + .o_sw_value (w_bit_field_value[0+16*k+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_register_11_bit_field_0[8*(16*i+4*j+k)+:8]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_1 + genvar k; + for (k = 0;k < 4;k = k + 1) begin : g + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'h00), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+16*k+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[8+16*k+:8]), + .i_sw_write_data (w_bit_field_write_data[8+16*k+:8]), + .o_sw_read_data (w_bit_field_read_data[8+16*k+:8]), + .o_sw_value (w_bit_field_value[8+16*k+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_register_11_bit_field_1[8*(16*i+4*j+k)+:8]), + .o_value_unmasked () + ); + end + end + end + end + end endgenerate + generate if (1) begin : g_register_12 + wire w_bit_field_valid; + wire [63:0] w_bit_field_read_mask; + wire [63:0] w_bit_field_write_mask; + wire [63:0] w_bit_field_write_data; + wire [63:0] w_bit_field_read_data; + wire [63:0] w_bit_field_value; + wire w_indirect_index; + `rggen_tie_off_unused_signals(64, 64'h0000000100000001, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[8+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h50), + .BUS_WIDTH (32), + .DATA_WIDTH (64), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h1}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[22+:1]), + .o_register_ready (w_register_ready[22+:1]), + .o_register_status (w_register_status[44+:2]), + .o_register_read_data (w_register_read_data[704+:32]), + .o_register_value (w_register_value[1408+:64]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_register_12_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[32+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[32+:1]), + .i_sw_write_data (w_bit_field_write_data[32+:1]), + .o_sw_read_data (w_bit_field_read_data[32+:1]), + .o_sw_value (w_bit_field_value[32+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_register_12_bit_field_1), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_13 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h0003ffff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (8), + .OFFSET_ADDRESS (8'h60), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[23+:1]), + .o_register_ready (w_register_ready[23+:1]), + .o_register_status (w_register_status[46+:2]), + .o_register_read_data (w_register_read_data[736+:32]), + .o_register_value (w_register_value[1472+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:2]), + .i_sw_write_data (w_bit_field_write_data[0+:2]), + .o_sw_read_data (w_bit_field_read_data[0+:2]), + .o_sw_value (w_bit_field_value[0+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_0), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_1 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE ({2{1'b0}}), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_NONE), + .SW_WRITE_ONCE (0), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[2+:2]), + .i_sw_write_data (w_bit_field_write_data[2+:2]), + .o_sw_read_data (w_bit_field_read_data[2+:2]), + .o_sw_value (w_bit_field_value[2+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value (i_register_13_bit_field_1), + .i_mask ({2{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_2 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (1), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:2]), + .i_sw_write_data (w_bit_field_write_data[4+:2]), + .o_sw_read_data (w_bit_field_read_data[4+:2]), + .o_sw_value (w_bit_field_value[4+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_2), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_3 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[6+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[6+:2]), + .i_sw_write_data (w_bit_field_write_data[6+:2]), + .o_sw_read_data (w_bit_field_read_data[6+:2]), + .o_sw_value (w_bit_field_value[6+:2]), + .o_write_trigger (o_register_13_bit_field_3_write_trigger), + .o_read_trigger (o_register_13_bit_field_3_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_3), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_4 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_CLEAR), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_SET), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[8+:2]), + .i_sw_write_data (w_bit_field_write_data[8+:2]), + .o_sw_read_data (w_bit_field_read_data[8+:2]), + .o_sw_value (w_bit_field_value[8+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_4), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_5 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_SET), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_CLEAR), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[10+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[10+:2]), + .i_sw_write_data (w_bit_field_write_data[10+:2]), + .o_sw_read_data (w_bit_field_read_data[10+:2]), + .o_sw_value (w_bit_field_value[10+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_5), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_6 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_SET), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[12+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[12+:2]), + .i_sw_write_data (w_bit_field_write_data[12+:2]), + .o_sw_read_data (w_bit_field_read_data[12+:2]), + .o_sw_value (w_bit_field_value[12+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear (i_register_13_bit_field_6_hw_clear), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_6), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_7 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_1_CLEAR), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[14+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[14+:2]), + .i_sw_write_data (w_bit_field_write_data[14+:2]), + .o_sw_read_data (w_bit_field_read_data[14+:2]), + .o_sw_value (w_bit_field_value[14+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set (i_register_13_bit_field_7_hw_set), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_7), + .o_value_unmasked () + ); + end + if (1) begin : g_bit_field_8 + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_DEFAULT), + .SW_WRITE_ACTION (`RGGEN_WRITE_DEFAULT), + .SW_WRITE_ONCE (0), + .STORAGE (1), + .EXTERNAL_READ_DATA (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[16+:2]), + .i_sw_write_data (w_bit_field_write_data[16+:2]), + .o_sw_read_data (w_bit_field_read_data[16+:2]), + .o_sw_value (w_bit_field_value[16+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (i_register_13_bit_field_8_hw_write_enable), + .i_hw_write_data (i_register_13_bit_field_8_hw_write_data), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_register_13_bit_field_8), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_register_15 + rggen_external_register #( + .ADDRESS_WIDTH (8), + .BUS_WIDTH (32), + .START_ADDRESS (8'h80), + .BYTE_SIZE (128) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[24+:1]), + .o_register_ready (w_register_ready[24+:1]), + .o_register_status (w_register_status[48+:2]), + .o_register_read_data (w_register_read_data[768+:32]), + .o_register_value (w_register_value[1536+:32]), + .o_external_valid (o_register_15_valid), + .o_external_access (o_register_15_access), + .o_external_address (o_register_15_address), + .o_external_data (o_register_15_data), + .o_external_strobe (o_register_15_strobe), + .i_external_ready (i_register_15_ready), + .i_external_status (i_register_15_status), + .i_external_data (i_register_15_data) + ); + end endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sample/block_0.vh b/third_party/tests/rggen/rggen-sample/block_0.vh new file mode 100644 index 0000000000..29cb65ad4e --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.vh @@ -0,0 +1,296 @@ +`ifndef BLOCK_0_VH +`define BLOCK_0_VH +`define BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_0_BIT_FIELD_1_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_0_BIT_FIELD_1_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_0_BIT_FIELD_1_BIT_OFFSET 4 +`define BLOCK_0_REGISTER_0_BIT_FIELD_2_BIT_WIDTH 1 +`define BLOCK_0_REGISTER_0_BIT_FIELD_2_BIT_MASK 1'h1 +`define BLOCK_0_REGISTER_0_BIT_FIELD_2_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_0_BIT_FIELD_3_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_0_BIT_FIELD_3_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_0_BIT_FIELD_3_BIT_OFFSET 9 +`define BLOCK_0_REGISTER_0_BIT_FIELD_4_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_0_BIT_FIELD_4_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_0_BIT_FIELD_4_BIT_OFFSET 11 +`define BLOCK_0_REGISTER_0_BIT_FIELD_5_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_0_BIT_FIELD_5_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_0_BIT_FIELD_5_BIT_OFFSET 13 +`define BLOCK_0_REGISTER_0_BIT_FIELD_6_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_0_BIT_FIELD_6_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_0_BIT_FIELD_6_BIT_OFFSET 15 +`define BLOCK_0_REGISTER_0_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_0_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_0_BYTE_OFFSET 8'h00 +`define BLOCK_0_REGISTER_1_BIT_WIDTH 1 +`define BLOCK_0_REGISTER_1_BIT_MASK 1'h1 +`define BLOCK_0_REGISTER_1_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_1_FOO 1'h0 +`define BLOCK_0_REGISTER_1_BAR 1'h1 +`define BLOCK_0_REGISTER_1_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_1_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_1_BYTE_OFFSET 8'h04 +`define BLOCK_0_REGISTER_2_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_2_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_2_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_2_BIT_FIELD_1_BIT_WIDTH 8 +`define BLOCK_0_REGISTER_2_BIT_FIELD_1_BIT_MASK 8'hff +`define BLOCK_0_REGISTER_2_BIT_FIELD_1_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_2_BIT_FIELD_2_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_2_BIT_FIELD_2_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_2_BIT_FIELD_2_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_2_BIT_FIELD_3_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_2_BIT_FIELD_3_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_2_BIT_FIELD_3_BIT_OFFSET 20 +`define BLOCK_0_REGISTER_2_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_2_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_2_BYTE_OFFSET 8'h08 +`define BLOCK_0_REGISTER_3_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_3_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_3_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_3_BIT_FIELD_1_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_3_BIT_FIELD_1_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_3_BIT_FIELD_1_BIT_OFFSET 4 +`define BLOCK_0_REGISTER_3_BIT_FIELD_2_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_3_BIT_FIELD_2_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_3_BIT_FIELD_2_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_3_BIT_FIELD_3_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_3_BIT_FIELD_3_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_3_BIT_FIELD_3_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_3_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_3_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_3_BYTE_OFFSET 8'h08 +`define BLOCK_0_REGISTER_4_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_4_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_4_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_4_BIT_FIELD_1_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_4_BIT_FIELD_1_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_4_BIT_FIELD_1_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_4_BIT_FIELD_2_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_4_BIT_FIELD_2_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_4_BIT_FIELD_2_BIT_OFFSET 12 +`define BLOCK_0_REGISTER_4_BIT_FIELD_3_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_4_BIT_FIELD_3_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_4_BIT_FIELD_3_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_4_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_4_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_4_BYTE_OFFSET 8'h0c +`define BLOCK_0_REGISTER_5_BIT_FIELD_0_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_0_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_5_BIT_FIELD_1_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_1_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_1_BIT_OFFSET 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_2_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_2_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_2_BIT_OFFSET 4 +`define BLOCK_0_REGISTER_5_BIT_FIELD_3_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_3_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_3_BIT_OFFSET 6 +`define BLOCK_0_REGISTER_5_BIT_FIELD_4_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_4_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_4_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_5_BIT_FIELD_5_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_5_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_5_BIT_OFFSET 10 +`define BLOCK_0_REGISTER_5_BIT_FIELD_6_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_6_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_6_BIT_OFFSET 12 +`define BLOCK_0_REGISTER_5_BIT_FIELD_7_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_7_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_7_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_5_BIT_FIELD_8_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_8_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_8_BIT_OFFSET 18 +`define BLOCK_0_REGISTER_5_BIT_FIELD_9_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_5_BIT_FIELD_9_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_5_BIT_FIELD_9_BIT_OFFSET 20 +`define BLOCK_0_REGISTER_5_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_5_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_5_BYTE_OFFSET 8'h10 +`define BLOCK_0_REGISTER_6_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_6_BIT_FIELD_1_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_1_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_1_BIT_OFFSET 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_2_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_2_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_2_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_6_BIT_FIELD_3_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_3_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_3_BIT_OFFSET 12 +`define BLOCK_0_REGISTER_6_BIT_FIELD_4_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_4_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_4_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_6_BIT_FIELD_5_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_5_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_5_BIT_OFFSET 20 +`define BLOCK_0_REGISTER_6_BIT_FIELD_6_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_6_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_6_BIT_OFFSET 24 +`define BLOCK_0_REGISTER_6_BIT_FIELD_7_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_7_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_7_BIT_OFFSET 28 +`define BLOCK_0_REGISTER_6_BIT_FIELD_8_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_8_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_8_BIT_OFFSET 32 +`define BLOCK_0_REGISTER_6_BIT_FIELD_9_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_6_BIT_FIELD_9_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_6_BIT_FIELD_9_BIT_OFFSET 36 +`define BLOCK_0_REGISTER_6_BYTE_WIDTH 8 +`define BLOCK_0_REGISTER_6_BYTE_SIZE 8 +`define BLOCK_0_REGISTER_6_BYTE_OFFSET 8'h14 +`define BLOCK_0_REGISTER_7_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_7_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_7_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_7_BIT_FIELD_1_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_7_BIT_FIELD_1_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_7_BIT_FIELD_1_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_7_BIT_FIELD_2_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_7_BIT_FIELD_2_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_7_BIT_FIELD_2_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_7_BIT_FIELD_3_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_7_BIT_FIELD_3_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_7_BIT_FIELD_3_BIT_OFFSET 24 +`define BLOCK_0_REGISTER_7_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_7_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_7_BYTE_OFFSET 8'h1c +`define BLOCK_0_REGISTER_8_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_8_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_8_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_8_BIT_FIELD_1_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_8_BIT_FIELD_1_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_8_BIT_FIELD_1_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_8_BIT_FIELD_2_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_8_BIT_FIELD_2_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_8_BIT_FIELD_2_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_8_BIT_FIELD_3_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_8_BIT_FIELD_3_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_8_BIT_FIELD_3_BIT_OFFSET 24 +`define BLOCK_0_REGISTER_8_BIT_FIELD_4_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_8_BIT_FIELD_4_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_8_BIT_FIELD_4_BIT_OFFSET 32 +`define BLOCK_0_REGISTER_8_BIT_FIELD_5_BIT_WIDTH 4 +`define BLOCK_0_REGISTER_8_BIT_FIELD_5_BIT_MASK 4'hf +`define BLOCK_0_REGISTER_8_BIT_FIELD_5_BIT_OFFSET 40 +`define BLOCK_0_REGISTER_8_BYTE_WIDTH 8 +`define BLOCK_0_REGISTER_8_BYTE_SIZE 8 +`define BLOCK_0_REGISTER_8_BYTE_OFFSET 8'h20 +`define BLOCK_0_REGISTER_9_BIT_FIELD_0_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_9_BIT_FIELD_0_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_9_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_9_BIT_FIELD_1_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_9_BIT_FIELD_1_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_9_BIT_FIELD_1_BIT_OFFSET 2 +`define BLOCK_0_REGISTER_9_BIT_FIELD_2_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_9_BIT_FIELD_2_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_9_BIT_FIELD_2_BIT_OFFSET 4 +`define BLOCK_0_REGISTER_9_BIT_FIELD_3_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_9_BIT_FIELD_3_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_9_BIT_FIELD_3_BIT_OFFSET 6 +`define BLOCK_0_REGISTER_9_BIT_FIELD_4_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_9_BIT_FIELD_4_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_9_BIT_FIELD_4_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_9_BIT_FIELD_5_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_9_BIT_FIELD_5_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_9_BIT_FIELD_5_BIT_OFFSET 10 +`define BLOCK_0_REGISTER_9_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_9_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_9_BYTE_OFFSET 8'h28 +`define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_0 0 +`define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_1 8 +`define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_2 16 +`define BLOCK_0_REGISTER_10_BIT_FIELD_0_BIT_OFFSET_3 24 +`define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_0 2 +`define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_1 10 +`define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_2 18 +`define BLOCK_0_REGISTER_10_BIT_FIELD_1_BIT_OFFSET_3 26 +`define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_0 4 +`define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_1 12 +`define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_2 20 +`define BLOCK_0_REGISTER_10_BIT_FIELD_2_BIT_OFFSET_3 28 +`define BLOCK_0_REGISTER_10_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_10_BYTE_SIZE 32 +`define BLOCK_0_REGISTER_10_ARRAY_DIMENSION 1 +`define BLOCK_0_REGISTER_10_ARRAY_SIZE_0 4 +`define BLOCK_0_REGISTER_10_BYTE_OFFSET_0 8'h30 +`define BLOCK_0_REGISTER_10_BYTE_OFFSET_1 8'h38 +`define BLOCK_0_REGISTER_10_BYTE_OFFSET_2 8'h40 +`define BLOCK_0_REGISTER_10_BYTE_OFFSET_3 8'h48 +`define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_WIDTH 8 +`define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_MASK 8'hff +`define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_0 0 +`define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_1 16 +`define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_2 32 +`define BLOCK_0_REGISTER_11_BIT_FIELD_0_BIT_OFFSET_3 48 +`define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_WIDTH 8 +`define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_MASK 8'hff +`define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_0 8 +`define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_1 24 +`define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_2 40 +`define BLOCK_0_REGISTER_11_BIT_FIELD_1_BIT_OFFSET_3 56 +`define BLOCK_0_REGISTER_11_BYTE_WIDTH 8 +`define BLOCK_0_REGISTER_11_BYTE_SIZE 8 +`define BLOCK_0_REGISTER_11_ARRAY_DIMENSION 2 +`define BLOCK_0_REGISTER_11_ARRAY_SIZE_0 2 +`define BLOCK_0_REGISTER_11_ARRAY_SIZE_1 4 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_0 8'h50 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_1 8'h50 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_2 8'h50 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_0_3 8'h50 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_0 8'h50 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_1 8'h50 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_2 8'h50 +`define BLOCK_0_REGISTER_11_BYTE_OFFSET_1_3 8'h50 +`define BLOCK_0_REGISTER_12_BIT_FIELD_0_BIT_WIDTH 1 +`define BLOCK_0_REGISTER_12_BIT_FIELD_0_BIT_MASK 1'h1 +`define BLOCK_0_REGISTER_12_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_12_BIT_FIELD_1_BIT_WIDTH 1 +`define BLOCK_0_REGISTER_12_BIT_FIELD_1_BIT_MASK 1'h1 +`define BLOCK_0_REGISTER_12_BIT_FIELD_1_BIT_OFFSET 32 +`define BLOCK_0_REGISTER_12_BYTE_WIDTH 8 +`define BLOCK_0_REGISTER_12_BYTE_SIZE 8 +`define BLOCK_0_REGISTER_12_BYTE_OFFSET 8'h50 +`define BLOCK_0_REGISTER_13_BIT_FIELD_0_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_0_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_0_REGISTER_13_BIT_FIELD_1_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_1_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_1_BIT_OFFSET 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_2_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_2_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_2_BIT_OFFSET 4 +`define BLOCK_0_REGISTER_13_BIT_FIELD_3_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_3_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_3_BIT_OFFSET 6 +`define BLOCK_0_REGISTER_13_BIT_FIELD_4_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_4_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_4_BIT_OFFSET 8 +`define BLOCK_0_REGISTER_13_BIT_FIELD_5_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_5_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_5_BIT_OFFSET 10 +`define BLOCK_0_REGISTER_13_BIT_FIELD_6_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_6_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_6_BIT_OFFSET 12 +`define BLOCK_0_REGISTER_13_BIT_FIELD_7_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_7_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_7_BIT_OFFSET 14 +`define BLOCK_0_REGISTER_13_BIT_FIELD_8_BIT_WIDTH 2 +`define BLOCK_0_REGISTER_13_BIT_FIELD_8_BIT_MASK 2'h3 +`define BLOCK_0_REGISTER_13_BIT_FIELD_8_BIT_OFFSET 16 +`define BLOCK_0_REGISTER_13_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_13_BYTE_SIZE 4 +`define BLOCK_0_REGISTER_13_BYTE_OFFSET 8'h60 +`define BLOCK_0_REGISTER_15_BYTE_WIDTH 4 +`define BLOCK_0_REGISTER_15_BYTE_SIZE 128 +`define BLOCK_0_REGISTER_15_BYTE_OFFSET 8'h80 +`endif diff --git a/third_party/tests/rggen/rggen-sample/block_0.vhd b/third_party/tests/rggen/rggen-sample/block_0.vhd new file mode 100644 index 0000000000..7c63cf0c8f --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.vhd @@ -0,0 +1,3121 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.rggen_rtl.all; + +entity block_0 is + generic ( + ADDRESS_WIDTH: positive := 8; + PRE_DECODE: boolean := false; + BASE_ADDRESS: unsigned := x"0"; + ERROR_STATUS: boolean := false; + INSERT_SLICER: boolean := false; + REGISTER_10_BIT_FIELD_1_INITIAL_VALUE: unsigned(7 downto 0) := repeat(x"0", 2, 4) + ); + port ( + i_clk: in std_logic; + i_rst_n: in std_logic; + i_psel: in std_logic; + i_penable: in std_logic; + i_paddr: in std_logic_vector(ADDRESS_WIDTH-1 downto 0); + i_pprot: in std_logic_vector(2 downto 0); + i_pwrite: in std_logic; + i_pstrb: in std_logic_vector(3 downto 0); + i_pwdata: in std_logic_vector(31 downto 0); + o_pready: out std_logic; + o_prdata: out std_logic_vector(31 downto 0); + o_pslverr: out std_logic; + o_register_0_bit_field_0: out std_logic_vector(3 downto 0); + o_register_0_bit_field_1: out std_logic_vector(3 downto 0); + o_register_0_bit_field_2: out std_logic_vector(0 downto 0); + o_register_0_bit_field_3: out std_logic_vector(1 downto 0); + o_register_0_bit_field_4: out std_logic_vector(1 downto 0); + o_register_0_bit_field_5: out std_logic_vector(1 downto 0); + o_register_0_bit_field_6: out std_logic_vector(1 downto 0); + i_register_0_bit_field_6: in std_logic_vector(1 downto 0); + o_register_1: out std_logic_vector(0 downto 0); + i_register_2_bit_field_0: in std_logic_vector(3 downto 0); + i_register_2_bit_field_2_latch: in std_logic_vector(0 downto 0); + i_register_2_bit_field_2: in std_logic_vector(3 downto 0); + o_register_2_bit_field_2: out std_logic_vector(3 downto 0); + i_register_2_bit_field_3: in std_logic_vector(3 downto 0); + o_register_2_bit_field_3: out std_logic_vector(3 downto 0); + o_register_3_bit_field_0: out std_logic_vector(3 downto 0); + o_register_3_bit_field_1: out std_logic_vector(3 downto 0); + o_register_3_bit_field_2_trigger: out std_logic_vector(3 downto 0); + o_register_3_bit_field_3_trigger: out std_logic_vector(3 downto 0); + i_register_4_bit_field_0_set: in std_logic_vector(3 downto 0); + o_register_4_bit_field_0: out std_logic_vector(3 downto 0); + i_register_4_bit_field_1_set: in std_logic_vector(3 downto 0); + o_register_4_bit_field_1: out std_logic_vector(3 downto 0); + o_register_4_bit_field_1_unmasked: out std_logic_vector(3 downto 0); + i_register_4_bit_field_3_clear: in std_logic_vector(3 downto 0); + o_register_4_bit_field_3: out std_logic_vector(3 downto 0); + i_register_5_bit_field_0_clear: in std_logic_vector(0 downto 0); + o_register_5_bit_field_0: out std_logic_vector(1 downto 0); + o_register_5_bit_field_1: out std_logic_vector(1 downto 0); + i_register_5_bit_field_2_set: in std_logic_vector(0 downto 0); + i_register_5_bit_field_2: in std_logic_vector(1 downto 0); + o_register_5_bit_field_2: out std_logic_vector(1 downto 0); + i_register_5_bit_field_3: in std_logic_vector(1 downto 0); + o_register_5_bit_field_3: out std_logic_vector(1 downto 0); + i_register_5_bit_field_4_enable: in std_logic_vector(0 downto 0); + o_register_5_bit_field_4: out std_logic_vector(1 downto 0); + o_register_5_bit_field_5: out std_logic_vector(1 downto 0); + o_register_5_bit_field_6: out std_logic_vector(1 downto 0); + i_register_5_bit_field_7_lock: in std_logic_vector(0 downto 0); + o_register_5_bit_field_7: out std_logic_vector(1 downto 0); + o_register_5_bit_field_8: out std_logic_vector(1 downto 0); + o_register_5_bit_field_9: out std_logic_vector(1 downto 0); + i_register_6_bit_field_0_set: in std_logic_vector(3 downto 0); + o_register_6_bit_field_0: out std_logic_vector(3 downto 0); + i_register_6_bit_field_1_set: in std_logic_vector(3 downto 0); + o_register_6_bit_field_1: out std_logic_vector(3 downto 0); + o_register_6_bit_field_1_unmasked: out std_logic_vector(3 downto 0); + i_register_6_bit_field_3_set: in std_logic_vector(3 downto 0); + o_register_6_bit_field_3: out std_logic_vector(3 downto 0); + i_register_6_bit_field_4_set: in std_logic_vector(3 downto 0); + o_register_6_bit_field_4: out std_logic_vector(3 downto 0); + o_register_6_bit_field_4_unmasked: out std_logic_vector(3 downto 0); + i_register_6_bit_field_6_clear: in std_logic_vector(3 downto 0); + o_register_6_bit_field_6: out std_logic_vector(3 downto 0); + i_register_6_bit_field_7_clear: in std_logic_vector(3 downto 0); + o_register_6_bit_field_7: out std_logic_vector(3 downto 0); + o_register_6_bit_field_8: out std_logic_vector(3 downto 0); + o_register_6_bit_field_9: out std_logic_vector(3 downto 0); + o_register_7_bit_field_0: out std_logic_vector(3 downto 0); + o_register_7_bit_field_1: out std_logic_vector(3 downto 0); + o_register_7_bit_field_2: out std_logic_vector(3 downto 0); + o_register_7_bit_field_3: out std_logic_vector(3 downto 0); + i_register_8_bit_field_0_set: in std_logic_vector(3 downto 0); + o_register_8_bit_field_0: out std_logic_vector(3 downto 0); + i_register_8_bit_field_1_clear: in std_logic_vector(3 downto 0); + o_register_8_bit_field_1: out std_logic_vector(3 downto 0); + i_register_8_bit_field_2_set: in std_logic_vector(3 downto 0); + o_register_8_bit_field_2: out std_logic_vector(3 downto 0); + i_register_8_bit_field_3_clear: in std_logic_vector(3 downto 0); + o_register_8_bit_field_3: out std_logic_vector(3 downto 0); + o_register_8_bit_field_4: out std_logic_vector(3 downto 0); + o_register_8_bit_field_5: out std_logic_vector(3 downto 0); + o_register_9_bit_field_0: out std_logic_vector(1 downto 0); + o_register_9_bit_field_0_write_trigger: out std_logic_vector(0 downto 0); + o_register_9_bit_field_0_read_trigger: out std_logic_vector(0 downto 0); + i_register_9_bit_field_1: in std_logic_vector(1 downto 0); + o_register_9_bit_field_1_read_trigger: out std_logic_vector(0 downto 0); + o_register_9_bit_field_2: out std_logic_vector(1 downto 0); + o_register_9_bit_field_2_write_trigger: out std_logic_vector(0 downto 0); + o_register_9_bit_field_3: out std_logic_vector(1 downto 0); + i_register_9_bit_field_3: in std_logic_vector(1 downto 0); + o_register_9_bit_field_3_write_trigger: out std_logic_vector(0 downto 0); + o_register_9_bit_field_3_read_trigger: out std_logic_vector(0 downto 0); + i_register_9_bit_field_4: in std_logic_vector(1 downto 0); + o_register_9_bit_field_4_trigger: out std_logic_vector(1 downto 0); + i_register_9_bit_field_5: in std_logic_vector(1 downto 0); + o_register_9_bit_field_5_trigger: out std_logic_vector(1 downto 0); + o_register_10_bit_field_0: out std_logic_vector(31 downto 0); + o_register_10_bit_field_1: out std_logic_vector(31 downto 0); + o_register_10_bit_field_2: out std_logic_vector(31 downto 0); + o_register_11_bit_field_0: out std_logic_vector(255 downto 0); + o_register_11_bit_field_1: out std_logic_vector(255 downto 0); + o_register_12_bit_field_0: out std_logic_vector(0 downto 0); + o_register_12_bit_field_1: out std_logic_vector(0 downto 0); + o_register_13_bit_field_0: out std_logic_vector(1 downto 0); + i_register_13_bit_field_1: in std_logic_vector(1 downto 0); + o_register_13_bit_field_2: out std_logic_vector(1 downto 0); + o_register_13_bit_field_3: out std_logic_vector(1 downto 0); + o_register_13_bit_field_3_write_trigger: out std_logic_vector(0 downto 0); + o_register_13_bit_field_3_read_trigger: out std_logic_vector(0 downto 0); + o_register_13_bit_field_4: out std_logic_vector(1 downto 0); + o_register_13_bit_field_5: out std_logic_vector(1 downto 0); + o_register_13_bit_field_6: out std_logic_vector(1 downto 0); + i_register_13_bit_field_6_hw_clear: in std_logic_vector(1 downto 0); + o_register_13_bit_field_7: out std_logic_vector(1 downto 0); + i_register_13_bit_field_7_hw_set: in std_logic_vector(1 downto 0); + o_register_13_bit_field_8: out std_logic_vector(1 downto 0); + i_register_13_bit_field_8_hw_write_enable: in std_logic_vector(0 downto 0); + i_register_13_bit_field_8_hw_write_data: in std_logic_vector(1 downto 0); + o_register_15_valid: out std_logic; + o_register_15_access: out std_logic_vector(1 downto 0); + o_register_15_address: out std_logic_vector(7 downto 0); + o_register_15_data: out std_logic_vector(31 downto 0); + o_register_15_strobe: out std_logic_vector(3 downto 0); + i_register_15_ready: in std_logic; + i_register_15_status: in std_logic_vector(1 downto 0); + i_register_15_data: in std_logic_vector(31 downto 0) + ); +end block_0; + +architecture rtl of block_0 is + signal register_valid: std_logic; + signal register_access: std_logic_vector(1 downto 0); + signal register_address: std_logic_vector(7 downto 0); + signal register_write_data: std_logic_vector(31 downto 0); + signal register_strobe: std_logic_vector(3 downto 0); + signal register_active: std_logic_vector(24 downto 0); + signal register_ready: std_logic_vector(24 downto 0); + signal register_status: std_logic_vector(49 downto 0); + signal register_read_data: std_logic_vector(799 downto 0); + signal register_value: std_logic_vector(1599 downto 0); +begin + u_adapter: entity work.rggen_apb_adaper + generic map ( + ADDRESS_WIDTH => ADDRESS_WIDTH, + LOCAL_ADDRESS_WIDTH => 8, + BUS_WIDTH => 32, + REGISTERS => 25, + PRE_DECODE => PRE_DECODE, + BASE_ADDRESS => BASE_ADDRESS, + BYTE_SIZE => 256, + ERROR_STATUS => ERROR_STATUS, + INSERT_SLICER => INSERT_SLICER + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_psel => i_psel, + i_penable => i_penable, + i_paddr => i_paddr, + i_pprot => i_pprot, + i_pwrite => i_pwrite, + i_pstrb => i_pstrb, + i_pwdata => i_pwdata, + o_pready => o_pready, + o_prdata => o_prdata, + o_pslverr => o_pslverr, + o_register_valid => register_valid, + o_register_access => register_access, + o_register_address => register_address, + o_register_write_data => register_write_data, + o_register_strobe => register_strobe, + i_register_active => register_active, + i_register_ready => register_ready, + i_register_status => register_status, + i_register_read_data => register_read_data + ); + g_register_0: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"0001ffff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"00", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(0), + o_register_ready => register_ready(0), + o_register_status => register_status(1 downto 0), + o_register_read_data => register_read_data(31 downto 0), + o_register_value => register_value(31 downto 0), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 0), + i_sw_write_data => bit_field_write_data(3 downto 0), + o_sw_read_data => bit_field_read_data(3 downto 0), + o_sw_value => bit_field_value(3 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_0_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 4), + i_sw_write_data => bit_field_write_data(7 downto 4), + o_sw_read_data => bit_field_read_data(7 downto 4), + o_sw_value => bit_field_value(7 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_0_bit_field_1, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(8 downto 8), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(8 downto 8), + i_sw_write_data => bit_field_write_data(8 downto 8), + o_sw_read_data => bit_field_read_data(8 downto 8), + o_sw_value => bit_field_value(8 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_0_bit_field_2, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ONCE => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(10 downto 9), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(10 downto 9), + i_sw_write_data => bit_field_write_data(10 downto 9), + o_sw_read_data => bit_field_read_data(10 downto 9), + o_sw_value => bit_field_value(10 downto 9), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_0_bit_field_3, + o_value_unmasked => open + ); + end block; + g_bit_field_4: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_CLEAR + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(12 downto 11), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(12 downto 11), + i_sw_write_data => bit_field_write_data(12 downto 11), + o_sw_read_data => bit_field_read_data(12 downto 11), + o_sw_value => bit_field_value(12 downto 11), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_0_bit_field_4, + o_value_unmasked => open + ); + end block; + g_bit_field_5: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_SET + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(14 downto 13), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(14 downto 13), + i_sw_write_data => bit_field_write_data(14 downto 13), + o_sw_read_data => bit_field_read_data(14 downto 13), + o_sw_value => bit_field_value(14 downto 13), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_0_bit_field_5, + o_value_unmasked => open + ); + end block; + g_bit_field_6: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(16 downto 15), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(16 downto 15), + i_sw_write_data => bit_field_write_data(16 downto 15), + o_sw_read_data => bit_field_read_data(16 downto 15), + o_sw_value => bit_field_value(16 downto 15), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_register_0_bit_field_6, + i_mask => (others => '1'), + o_value => o_register_0_bit_field_6, + o_value_unmasked => open + ); + end block; + end block; + g_register_1: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"00000001", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"04", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(1), + o_register_ready => register_ready(1), + o_register_status => register_status(3 downto 2), + o_register_read_data => register_read_data(63 downto 32), + o_register_value => register_value(95 downto 64), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_register_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_1, + o_value_unmasked => open + ); + end block; + end block; + g_register_2: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"00ffff0f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => false, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"08", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(2), + o_register_ready => register_ready(2), + o_register_status => register_status(5 downto 4), + o_register_read_data => register_read_data(95 downto 64), + o_register_value => register_value(159 downto 128), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 0), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(3 downto 0), + i_sw_write_data => bit_field_write_data(3 downto 0), + o_sw_read_data => bit_field_read_data(3 downto 0), + o_sw_value => bit_field_value(3 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_register_2_bit_field_0, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + STORAGE => false, + EXTERNAL_READ_DATA => true + ) + port map ( + i_clk => '0', + i_rst_n => '0', + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(15 downto 8), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(15 downto 8), + i_sw_write_data => bit_field_write_data(15 downto 8), + o_sw_read_data => bit_field_read_data(15 downto 8), + o_sw_value => bit_field_value(15 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => slice(x"ab", 8, 0), + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ACTION => RGGEN_WRITE_NONE + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(19 downto 16), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(19 downto 16), + i_sw_write_data => bit_field_write_data(19 downto 16), + o_sw_read_data => bit_field_read_data(19 downto 16), + o_sw_value => bit_field_value(19 downto 16), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => i_register_2_bit_field_2_latch, + i_hw_write_data => i_register_2_bit_field_2, + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_2_bit_field_2, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ACTION => RGGEN_WRITE_NONE + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(23 downto 20), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(23 downto 20), + i_sw_write_data => bit_field_write_data(23 downto 20), + o_sw_read_data => bit_field_read_data(23 downto 20), + o_sw_value => bit_field_value(23 downto 20), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => register_value(208 downto 208), + i_hw_write_data => i_register_2_bit_field_3, + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_2_bit_field_3, + o_value_unmasked => open + ); + end block; + end block; + g_register_3: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000f0fff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => false, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"08", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(3), + o_register_ready => register_ready(3), + o_register_status => register_status(7 downto 6), + o_register_read_data => register_read_data(127 downto 96), + o_register_value => register_value(223 downto 192), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 0), + i_sw_write_data => bit_field_write_data(3 downto 0), + o_sw_read_data => bit_field_read_data(3 downto 0), + o_sw_value => bit_field_value(3 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_3_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ONCE => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 4), + i_sw_write_data => bit_field_write_data(7 downto 4), + o_sw_read_data => bit_field_read_data(7 downto 4), + o_sw_value => bit_field_value(7 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_3_bit_field_1, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field_w01trg + generic map ( + WRITE_ONE_TRIGGER => false, + WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 8), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(11 downto 8), + i_sw_write_data => bit_field_write_data(11 downto 8), + o_sw_read_data => bit_field_read_data(11 downto 8), + o_sw_value => bit_field_value(11 downto 8), + i_value => (others => '0'), + o_trigger => o_register_3_bit_field_2_trigger + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field_w01trg + generic map ( + WRITE_ONE_TRIGGER => true, + WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(19 downto 16), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(19 downto 16), + i_sw_write_data => bit_field_write_data(19 downto 16), + o_sw_read_data => bit_field_read_data(19 downto 16), + o_sw_value => bit_field_value(19 downto 16), + i_value => (others => '0'), + o_trigger => o_register_3_bit_field_3_trigger + ); + end block; + end block; + g_register_4: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000fff0f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => false, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"0c", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(4), + o_register_ready => register_ready(4), + o_register_status => register_status(9 downto 8), + o_register_read_data => register_read_data(159 downto 128), + o_register_value => register_value(287 downto 256), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_CLEAR, + SW_WRITE_ACTION => RGGEN_WRITE_NONE, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 0), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(3 downto 0), + i_sw_write_data => bit_field_write_data(3 downto 0), + o_sw_read_data => bit_field_read_data(3 downto 0), + o_sw_value => bit_field_value(3 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_4_bit_field_0_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_4_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_CLEAR, + SW_WRITE_ACTION => RGGEN_WRITE_NONE, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 8), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(11 downto 8), + i_sw_write_data => bit_field_write_data(11 downto 8), + o_sw_read_data => bit_field_read_data(11 downto 8), + o_sw_value => bit_field_value(11 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_4_bit_field_1_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => register_value(3 downto 0), + o_value => o_register_4_bit_field_1, + o_value_unmasked => o_register_4_bit_field_1_unmasked + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(15 downto 12), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(15 downto 12), + i_sw_write_data => bit_field_write_data(15 downto 12), + o_sw_read_data => bit_field_read_data(15 downto 12), + o_sw_value => bit_field_value(15 downto 12), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => register_value(267 downto 264), + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_SET, + SW_WRITE_ACTION => RGGEN_WRITE_NONE, + HW_CLEAR_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(19 downto 16), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(19 downto 16), + i_sw_write_data => bit_field_write_data(19 downto 16), + o_sw_read_data => bit_field_read_data(19 downto 16), + o_sw_value => bit_field_value(19 downto 16), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => i_register_4_bit_field_3_clear, + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_4_bit_field_3, + o_value_unmasked => open + ); + end block; + end block; + g_register_5: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"003f3fff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"10", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(5), + o_register_ready => register_ready(5), + o_register_status => register_status(11 downto 10), + o_register_read_data => register_read_data(191 downto 160), + o_register_value => register_value(351 downto 320), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + HW_CLEAR_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(1 downto 0), + i_sw_write_data => bit_field_write_data(1 downto 0), + o_sw_read_data => bit_field_read_data(1 downto 0), + o_sw_value => bit_field_value(1 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => i_register_5_bit_field_0_clear, + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + HW_CLEAR_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 2), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 2), + i_sw_write_data => bit_field_write_data(3 downto 2), + o_sw_read_data => bit_field_read_data(3 downto 2), + o_sw_value => bit_field_value(3 downto 2), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => register_value(200 downto 200), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_1, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0) + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(5 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(5 downto 4), + i_sw_write_data => bit_field_write_data(5 downto 4), + o_sw_read_data => bit_field_read_data(5 downto 4), + o_sw_value => bit_field_value(5 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => i_register_5_bit_field_2_set, + i_hw_write_data => i_register_5_bit_field_2, + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_2, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0) + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 6), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 6), + i_sw_write_data => bit_field_write_data(7 downto 6), + o_sw_read_data => bit_field_read_data(7 downto 6), + o_sw_value => bit_field_value(7 downto 6), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => register_value(208 downto 208), + i_hw_write_data => i_register_5_bit_field_3, + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_3, + o_value_unmasked => open + ); + end block; + g_bit_field_4: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_HIGH + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(9 downto 8), + i_sw_write_enable => i_register_5_bit_field_4_enable, + i_sw_write_mask => bit_field_write_mask(9 downto 8), + i_sw_write_data => bit_field_write_data(9 downto 8), + o_sw_read_data => bit_field_read_data(9 downto 8), + o_sw_value => bit_field_value(9 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_4, + o_value_unmasked => open + ); + end block; + g_bit_field_5: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_HIGH + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 10), + i_sw_write_enable => register_value(8 downto 8), + i_sw_write_mask => bit_field_write_mask(11 downto 10), + i_sw_write_data => bit_field_write_data(11 downto 10), + o_sw_read_data => bit_field_read_data(11 downto 10), + o_sw_value => bit_field_value(11 downto 10), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_5, + o_value_unmasked => open + ); + end block; + g_bit_field_6: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_HIGH + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(13 downto 12), + i_sw_write_enable => register_value(64 downto 64), + i_sw_write_mask => bit_field_write_mask(13 downto 12), + i_sw_write_data => bit_field_write_data(13 downto 12), + o_sw_read_data => bit_field_read_data(13 downto 12), + o_sw_value => bit_field_value(13 downto 12), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_6, + o_value_unmasked => open + ); + end block; + g_bit_field_7: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_LOW + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(17 downto 16), + i_sw_write_enable => i_register_5_bit_field_7_lock, + i_sw_write_mask => bit_field_write_mask(17 downto 16), + i_sw_write_data => bit_field_write_data(17 downto 16), + o_sw_read_data => bit_field_read_data(17 downto 16), + o_sw_value => bit_field_value(17 downto 16), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_7, + o_value_unmasked => open + ); + end block; + g_bit_field_8: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_LOW + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(19 downto 18), + i_sw_write_enable => register_value(8 downto 8), + i_sw_write_mask => bit_field_write_mask(19 downto 18), + i_sw_write_data => bit_field_write_data(19 downto 18), + o_sw_read_data => bit_field_read_data(19 downto 18), + o_sw_value => bit_field_value(19 downto 18), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_8, + o_value_unmasked => open + ); + end block; + g_bit_field_9: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_LOW + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(21 downto 20), + i_sw_write_enable => register_value(64 downto 64), + i_sw_write_mask => bit_field_write_mask(21 downto 20), + i_sw_write_data => bit_field_write_data(21 downto 20), + o_sw_read_data => bit_field_read_data(21 downto 20), + o_sw_value => bit_field_value(21 downto 20), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_5_bit_field_9, + o_value_unmasked => open + ); + end block; + end block; + g_register_6: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(63 downto 0); + signal bit_field_write_mask: std_logic_vector(63 downto 0); + signal bit_field_write_data: std_logic_vector(63 downto 0); + signal bit_field_read_data: std_logic_vector(63 downto 0); + signal bit_field_value: std_logic_vector(63 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 63 generate + g: if (bit_slice(x"000000ffffffffff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"14", + BUS_WIDTH => 32, + DATA_WIDTH => 64 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(6), + o_register_ready => register_ready(6), + o_register_status => register_status(13 downto 12), + o_register_read_data => register_read_data(223 downto 192), + o_register_value => register_value(447 downto 384), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_0_CLEAR, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 0), + i_sw_write_data => bit_field_write_data(3 downto 0), + o_sw_read_data => bit_field_read_data(3 downto 0), + o_sw_value => bit_field_value(3 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_6_bit_field_0_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_6_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_0_CLEAR, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 4), + i_sw_write_data => bit_field_write_data(7 downto 4), + o_sw_read_data => bit_field_read_data(7 downto 4), + o_sw_value => bit_field_value(7 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_6_bit_field_1_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => register_value(3 downto 0), + o_value => o_register_6_bit_field_1, + o_value_unmasked => o_register_6_bit_field_1_unmasked + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 8), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(11 downto 8), + i_sw_write_data => bit_field_write_data(11 downto 8), + o_sw_read_data => bit_field_read_data(11 downto 8), + o_sw_value => bit_field_value(11 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => register_value(391 downto 388), + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_1_CLEAR, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(15 downto 12), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(15 downto 12), + i_sw_write_data => bit_field_write_data(15 downto 12), + o_sw_read_data => bit_field_read_data(15 downto 12), + o_sw_value => bit_field_value(15 downto 12), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_6_bit_field_3_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_6_bit_field_3, + o_value_unmasked => open + ); + end block; + g_bit_field_4: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_1_CLEAR, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(19 downto 16), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(19 downto 16), + i_sw_write_data => bit_field_write_data(19 downto 16), + o_sw_read_data => bit_field_read_data(19 downto 16), + o_sw_value => bit_field_value(19 downto 16), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_6_bit_field_4_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => register_value(3 downto 0), + o_value => o_register_6_bit_field_4, + o_value_unmasked => o_register_6_bit_field_4_unmasked + ); + end block; + g_bit_field_5: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(23 downto 20), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(23 downto 20), + i_sw_write_data => bit_field_write_data(23 downto 20), + o_sw_read_data => bit_field_read_data(23 downto 20), + o_sw_value => bit_field_value(23 downto 20), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => register_value(403 downto 400), + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bit_field_6: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_0_SET, + HW_CLEAR_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(27 downto 24), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(27 downto 24), + i_sw_write_data => bit_field_write_data(27 downto 24), + o_sw_read_data => bit_field_read_data(27 downto 24), + o_sw_value => bit_field_value(27 downto 24), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => i_register_6_bit_field_6_clear, + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_6_bit_field_6, + o_value_unmasked => open + ); + end block; + g_bit_field_7: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_1_SET, + HW_CLEAR_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(31 downto 28), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(31 downto 28), + i_sw_write_data => bit_field_write_data(31 downto 28), + o_sw_read_data => bit_field_read_data(31 downto 28), + o_sw_value => bit_field_value(31 downto 28), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => i_register_6_bit_field_7_clear, + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_6_bit_field_7, + o_value_unmasked => open + ); + end block; + g_bit_field_8: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ACTION => RGGEN_WRITE_0_TOGGLE + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(35 downto 32), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(35 downto 32), + i_sw_write_data => bit_field_write_data(35 downto 32), + o_sw_read_data => bit_field_read_data(35 downto 32), + o_sw_value => bit_field_value(35 downto 32), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_6_bit_field_8, + o_value_unmasked => open + ); + end block; + g_bit_field_9: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ACTION => RGGEN_WRITE_1_TOGGLE + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(39 downto 36), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(39 downto 36), + i_sw_write_data => bit_field_write_data(39 downto 36), + o_sw_read_data => bit_field_read_data(39 downto 36), + o_sw_value => bit_field_value(39 downto 36), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_6_bit_field_9, + o_value_unmasked => open + ); + end block; + end block; + g_register_7: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"0f0f0f0f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"1c", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(7), + o_register_ready => register_ready(7), + o_register_status => register_status(15 downto 14), + o_register_read_data => register_read_data(255 downto 224), + o_register_value => register_value(479 downto 448), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_SET, + SW_WRITE_ACTION => RGGEN_WRITE_0_CLEAR + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 0), + i_sw_write_data => bit_field_write_data(3 downto 0), + o_sw_read_data => bit_field_read_data(3 downto 0), + o_sw_value => bit_field_value(3 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_7_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_SET, + SW_WRITE_ACTION => RGGEN_WRITE_1_CLEAR + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 8), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(11 downto 8), + i_sw_write_data => bit_field_write_data(11 downto 8), + o_sw_read_data => bit_field_read_data(11 downto 8), + o_sw_value => bit_field_value(11 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_7_bit_field_1, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_CLEAR, + SW_WRITE_ACTION => RGGEN_WRITE_0_SET + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(19 downto 16), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(19 downto 16), + i_sw_write_data => bit_field_write_data(19 downto 16), + o_sw_read_data => bit_field_read_data(19 downto 16), + o_sw_value => bit_field_value(19 downto 16), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_7_bit_field_2, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_CLEAR, + SW_WRITE_ACTION => RGGEN_WRITE_1_SET + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(27 downto 24), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(27 downto 24), + i_sw_write_data => bit_field_write_data(27 downto 24), + o_sw_read_data => bit_field_read_data(27 downto 24), + o_sw_value => bit_field_value(27 downto 24), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_7_bit_field_3, + o_value_unmasked => open + ); + end block; + end block; + g_register_8: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(63 downto 0); + signal bit_field_write_mask: std_logic_vector(63 downto 0); + signal bit_field_write_data: std_logic_vector(63 downto 0); + signal bit_field_read_data: std_logic_vector(63 downto 0); + signal bit_field_value: std_logic_vector(63 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 63 generate + g: if (bit_slice(x"00000f0f0f0f0f0f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"20", + BUS_WIDTH => 32, + DATA_WIDTH => 64 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(8), + o_register_ready => register_ready(8), + o_register_status => register_status(17 downto 16), + o_register_read_data => register_read_data(287 downto 256), + o_register_value => register_value(575 downto 512), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_CLEAR, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 0), + i_sw_write_data => bit_field_write_data(3 downto 0), + o_sw_read_data => bit_field_read_data(3 downto 0), + o_sw_value => bit_field_value(3 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_8_bit_field_0_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_8_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_SET, + HW_CLEAR_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 8), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(11 downto 8), + i_sw_write_data => bit_field_write_data(11 downto 8), + o_sw_read_data => bit_field_read_data(11 downto 8), + o_sw_value => bit_field_value(11 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => i_register_8_bit_field_1_clear, + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_8_bit_field_1, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ACTION => RGGEN_WRITE_CLEAR, + HW_SET_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(19 downto 16), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(19 downto 16), + i_sw_write_data => bit_field_write_data(19 downto 16), + o_sw_read_data => bit_field_read_data(19 downto 16), + o_sw_value => bit_field_value(19 downto 16), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_8_bit_field_2_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_8_bit_field_2, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ACTION => RGGEN_WRITE_SET, + HW_CLEAR_WIDTH => 4 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(27 downto 24), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(27 downto 24), + i_sw_write_data => bit_field_write_data(27 downto 24), + o_sw_read_data => bit_field_read_data(27 downto 24), + o_sw_value => bit_field_value(27 downto 24), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => i_register_8_bit_field_3_clear, + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_8_bit_field_3, + o_value_unmasked => open + ); + end block; + g_bit_field_4: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_SET, + SW_WRITE_ACTION => RGGEN_WRITE_CLEAR + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(35 downto 32), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(35 downto 32), + i_sw_write_data => bit_field_write_data(35 downto 32), + o_sw_read_data => bit_field_read_data(35 downto 32), + o_sw_value => bit_field_value(35 downto 32), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_8_bit_field_4, + o_value_unmasked => open + ); + end block; + g_bit_field_5: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_READ_ACTION => RGGEN_READ_CLEAR, + SW_WRITE_ACTION => RGGEN_WRITE_SET + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(43 downto 40), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(43 downto 40), + i_sw_write_data => bit_field_write_data(43 downto 40), + o_sw_read_data => bit_field_read_data(43 downto 40), + o_sw_value => bit_field_value(43 downto 40), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_8_bit_field_5, + o_value_unmasked => open + ); + end block; + end block; + g_register_9: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"00000fff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"28", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(9), + o_register_ready => register_ready(9), + o_register_status => register_status(19 downto 18), + o_register_read_data => register_read_data(319 downto 288), + o_register_value => register_value(607 downto 576), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ONCE => false, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(1 downto 0), + i_sw_write_data => bit_field_write_data(1 downto 0), + o_sw_read_data => bit_field_read_data(1 downto 0), + o_sw_value => bit_field_value(1 downto 0), + o_write_trigger => o_register_9_bit_field_0_write_trigger, + o_read_trigger => o_register_9_bit_field_0_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_9_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 2), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(3 downto 2), + i_sw_write_data => bit_field_write_data(3 downto 2), + o_sw_read_data => bit_field_read_data(3 downto 2), + o_sw_value => bit_field_value(3 downto 2), + o_write_trigger => open, + o_read_trigger => o_register_9_bit_field_1_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_register_9_bit_field_1, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ONCE => false, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(5 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(5 downto 4), + i_sw_write_data => bit_field_write_data(5 downto 4), + o_sw_read_data => bit_field_read_data(5 downto 4), + o_sw_value => bit_field_value(5 downto 4), + o_write_trigger => o_register_9_bit_field_2_write_trigger, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_9_bit_field_2, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 6), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 6), + i_sw_write_data => bit_field_write_data(7 downto 6), + o_sw_read_data => bit_field_read_data(7 downto 6), + o_sw_value => bit_field_value(7 downto 6), + o_write_trigger => o_register_9_bit_field_3_write_trigger, + o_read_trigger => o_register_9_bit_field_3_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_register_9_bit_field_3, + i_mask => (others => '1'), + o_value => o_register_9_bit_field_3, + o_value_unmasked => open + ); + end block; + g_bit_field_4: block + begin + u_bit_field: entity work.rggen_bit_field_w01trg + generic map ( + WRITE_ONE_TRIGGER => false, + WIDTH => 2 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(9 downto 8), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(9 downto 8), + i_sw_write_data => bit_field_write_data(9 downto 8), + o_sw_read_data => bit_field_read_data(9 downto 8), + o_sw_value => bit_field_value(9 downto 8), + i_value => i_register_9_bit_field_4, + o_trigger => o_register_9_bit_field_4_trigger + ); + end block; + g_bit_field_5: block + begin + u_bit_field: entity work.rggen_bit_field_w01trg + generic map ( + WRITE_ONE_TRIGGER => true, + WIDTH => 2 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 10), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(11 downto 10), + i_sw_write_data => bit_field_write_data(11 downto 10), + o_sw_read_data => bit_field_read_data(11 downto 10), + o_sw_value => bit_field_value(11 downto 10), + i_value => i_register_9_bit_field_5, + o_trigger => o_register_9_bit_field_5_trigger + ); + end block; + end block; + g_register_10: block + begin + g: for i in 0 to 3 generate + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"3f3f3f3f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"30"+8*i, + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(10+i), + o_register_ready => register_ready(10+i), + o_register_status => register_status(2*(10+i)+1 downto 2*(10+i)), + o_register_read_data => register_read_data(32*(10+i)+31 downto 32*(10+i)), + o_register_value => register_value(64*(10+i)+0+31 downto 64*(10+i)+0), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + g: for j in 0 to 3 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0+8*j+1 downto 0+8*j), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0+8*j+1 downto 0+8*j), + i_sw_write_data => bit_field_write_data(0+8*j+1 downto 0+8*j), + o_sw_read_data => bit_field_read_data(0+8*j+1 downto 0+8*j), + o_sw_value => bit_field_value(0+8*j+1 downto 0+8*j), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_10_bit_field_0(2*(4*i+j)+1 downto 2*(4*i+j)), + o_value_unmasked => open + ); + end generate; + end block; + g_bit_field_1: block + begin + g: for j in 0 to 3 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(REGISTER_10_BIT_FIELD_1_INITIAL_VALUE, 2, j), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(2+8*j+1 downto 2+8*j), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(2+8*j+1 downto 2+8*j), + i_sw_write_data => bit_field_write_data(2+8*j+1 downto 2+8*j), + o_sw_read_data => bit_field_read_data(2+8*j+1 downto 2+8*j), + o_sw_value => bit_field_value(2+8*j+1 downto 2+8*j), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_10_bit_field_1(2*(4*i+j)+1 downto 2*(4*i+j)), + o_value_unmasked => open + ); + end generate; + end block; + g_bit_field_2: block + begin + g: for j in 0 to 3 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"e4", 2, j), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(4+8*j+1 downto 4+8*j), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(4+8*j+1 downto 4+8*j), + i_sw_write_data => bit_field_write_data(4+8*j+1 downto 4+8*j), + o_sw_read_data => bit_field_read_data(4+8*j+1 downto 4+8*j), + o_sw_value => bit_field_value(4+8*j+1 downto 4+8*j), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_10_bit_field_2(2*(4*i+j)+1 downto 2*(4*i+j)), + o_value_unmasked => open + ); + end generate; + end block; + end generate; + end block; + g_register_11: block + begin + g: for i in 0 to 1 generate + begin + g: for j in 0 to 3 generate + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(63 downto 0); + signal bit_field_write_mask: std_logic_vector(63 downto 0); + signal bit_field_write_data: std_logic_vector(63 downto 0); + signal bit_field_read_data: std_logic_vector(63 downto 0); + signal bit_field_value: std_logic_vector(63 downto 0); + signal indirect_match: std_logic_vector(2 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 63 generate + g: if (bit_slice(x"ffffffffffffffff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(3 downto 0)) = i else '0'; + indirect_match(1) <= '1' when unsigned(register_value(7 downto 4)) = j else '0'; + indirect_match(2) <= '1' when unsigned(register_value(8 downto 8)) = 0 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"50", + BUS_WIDTH => 32, + DATA_WIDTH => 64, + INDIRECT_MATCH_WIDTH => 3 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(14+4*i+j), + o_register_ready => register_ready(14+4*i+j), + o_register_status => register_status(2*(14+4*i+j)+1 downto 2*(14+4*i+j)), + o_register_read_data => register_read_data(32*(14+4*i+j)+31 downto 32*(14+4*i+j)), + o_register_value => register_value(64*(14+4*i+j)+0+63 downto 64*(14+4*i+j)+0), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + g: for k in 0 to 3 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"00", 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0+16*k+7 downto 0+16*k), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0+16*k+7 downto 0+16*k), + i_sw_write_data => bit_field_write_data(0+16*k+7 downto 0+16*k), + o_sw_read_data => bit_field_read_data(0+16*k+7 downto 0+16*k), + o_sw_value => bit_field_value(0+16*k+7 downto 0+16*k), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_11_bit_field_0(8*(16*i+4*j+k)+7 downto 8*(16*i+4*j+k)), + o_value_unmasked => open + ); + end generate; + end block; + g_bit_field_1: block + begin + g: for k in 0 to 3 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"00", 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(8+16*k+7 downto 8+16*k), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(8+16*k+7 downto 8+16*k), + i_sw_write_data => bit_field_write_data(8+16*k+7 downto 8+16*k), + o_sw_read_data => bit_field_read_data(8+16*k+7 downto 8+16*k), + o_sw_value => bit_field_value(8+16*k+7 downto 8+16*k), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_11_bit_field_1(8*(16*i+4*j+k)+7 downto 8*(16*i+4*j+k)), + o_value_unmasked => open + ); + end generate; + end block; + end generate; + end generate; + end block; + g_register_12: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(63 downto 0); + signal bit_field_write_mask: std_logic_vector(63 downto 0); + signal bit_field_write_data: std_logic_vector(63 downto 0); + signal bit_field_read_data: std_logic_vector(63 downto 0); + signal bit_field_value: std_logic_vector(63 downto 0); + signal indirect_match: std_logic_vector(0 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 63 generate + g: if (bit_slice(x"0000000100000001", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(8 downto 8)) = 1 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"50", + BUS_WIDTH => 32, + DATA_WIDTH => 64, + INDIRECT_MATCH_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(22), + o_register_ready => register_ready(22), + o_register_status => register_status(45 downto 44), + o_register_read_data => register_read_data(735 downto 704), + o_register_value => register_value(1471 downto 1408), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_12_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(32 downto 32), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(32 downto 32), + i_sw_write_data => bit_field_write_data(32 downto 32), + o_sw_read_data => bit_field_read_data(32 downto 32), + o_sw_value => bit_field_value(32 downto 32), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_12_bit_field_1, + o_value_unmasked => open + ); + end block; + end block; + g_register_13: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"0003ffff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 8, + OFFSET_ADDRESS => x"60", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(23), + o_register_ready => register_ready(23), + o_register_status => register_status(47 downto 46), + o_register_read_data => register_read_data(767 downto 736), + o_register_value => register_value(1503 downto 1472), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_DEFAULT, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(1 downto 0), + i_sw_write_data => bit_field_write_data(1 downto 0), + o_sw_read_data => bit_field_read_data(1 downto 0), + o_sw_value => bit_field_value(1 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_0, + o_value_unmasked => open + ); + end block; + g_bit_field_1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_NONE, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 2), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 2), + i_sw_write_data => bit_field_write_data(3 downto 2), + o_sw_read_data => bit_field_read_data(3 downto 2), + o_sw_value => bit_field_value(3 downto 2), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_register_13_bit_field_1, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bit_field_2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_DEFAULT, + SW_WRITE_ONCE => true, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(5 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(5 downto 4), + i_sw_write_data => bit_field_write_data(5 downto 4), + o_sw_read_data => bit_field_read_data(5 downto 4), + o_sw_value => bit_field_value(5 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_2, + o_value_unmasked => open + ); + end block; + g_bit_field_3: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_DEFAULT, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 6), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 6), + i_sw_write_data => bit_field_write_data(7 downto 6), + o_sw_read_data => bit_field_read_data(7 downto 6), + o_sw_value => bit_field_value(7 downto 6), + o_write_trigger => o_register_13_bit_field_3_write_trigger, + o_read_trigger => o_register_13_bit_field_3_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_3, + o_value_unmasked => open + ); + end block; + g_bit_field_4: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_CLEAR, + SW_WRITE_ACTION => RGGEN_WRITE_1_SET, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(9 downto 8), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(9 downto 8), + i_sw_write_data => bit_field_write_data(9 downto 8), + o_sw_read_data => bit_field_read_data(9 downto 8), + o_sw_value => bit_field_value(9 downto 8), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_4, + o_value_unmasked => open + ); + end block; + g_bit_field_5: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_SET, + SW_WRITE_ACTION => RGGEN_WRITE_1_CLEAR, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(11 downto 10), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(11 downto 10), + i_sw_write_data => bit_field_write_data(11 downto 10), + o_sw_read_data => bit_field_read_data(11 downto 10), + o_sw_value => bit_field_value(11 downto 10), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_5, + o_value_unmasked => open + ); + end block; + g_bit_field_6: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_1_SET, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(13 downto 12), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(13 downto 12), + i_sw_write_data => bit_field_write_data(13 downto 12), + o_sw_read_data => bit_field_read_data(13 downto 12), + o_sw_value => bit_field_value(13 downto 12), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => i_register_13_bit_field_6_hw_clear, + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_6, + o_value_unmasked => open + ); + end block; + g_bit_field_7: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_1_CLEAR, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(15 downto 14), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(15 downto 14), + i_sw_write_data => bit_field_write_data(15 downto 14), + o_sw_read_data => bit_field_read_data(15 downto 14), + o_sw_value => bit_field_value(15 downto 14), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => i_register_13_bit_field_7_hw_set, + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_7, + o_value_unmasked => open + ); + end block; + g_bit_field_8: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_DEFAULT, + SW_WRITE_ACTION => RGGEN_WRITE_DEFAULT, + SW_WRITE_ONCE => false, + HW_SET_WIDTH => 2, + HW_CLEAR_WIDTH => 2, + STORAGE => true, + EXTERNAL_READ_DATA => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(17 downto 16), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(17 downto 16), + i_sw_write_data => bit_field_write_data(17 downto 16), + o_sw_read_data => bit_field_read_data(17 downto 16), + o_sw_value => bit_field_value(17 downto 16), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => i_register_13_bit_field_8_hw_write_enable, + i_hw_write_data => i_register_13_bit_field_8_hw_write_data, + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_13_bit_field_8, + o_value_unmasked => open + ); + end block; + end block; + g_register_15: block + begin + u_register: entity work.rggen_external_register + generic map ( + ADDRESS_WIDTH => 8, + BUS_WIDTH => 32, + START_ADDRESS => x"80", + BYTE_SIZE => 128 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(24), + o_register_ready => register_ready(24), + o_register_status => register_status(49 downto 48), + o_register_read_data => register_read_data(799 downto 768), + o_register_value => register_value(1567 downto 1536), + o_external_valid => o_register_15_valid, + o_external_access => o_register_15_access, + o_external_address => o_register_15_address, + o_external_data => o_register_15_data, + o_external_strobe => o_register_15_strobe, + i_external_ready => i_register_15_ready, + i_external_status => i_register_15_status, + i_external_data => i_register_15_data + ); + end block; +end rtl; diff --git a/third_party/tests/rggen/rggen-sample/block_0.xlsx b/third_party/tests/rggen/rggen-sample/block_0.xlsx new file mode 100644 index 0000000000000000000000000000000000000000..3bfcc9a2ed411fa902181e3462adaa3565149489 GIT binary patch literal 14656 zcmeHuWpo|6vhFrBGc(1^unn;tGsMggGcz;9%OX3`GQ0i;|=v(>!rvJq~P?j)a-NS?|a+mmk6x*n*zn@d`4m6xU zi5~SDOqy4M4uAO)9{r^w9-ypzLG3S-)0g6Lx>C)GU5=YZN0M{Ffc0EPg=!nP(68Kl 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zurc4pk-PiA^Kg8>#CFGa2MBponVCSsviMo~PVSrk>hVA6z969VZv)+b-Uarn)W4>G z*b^ov_3sM)eRImc3YWY!`(L)I{4V%AVgGN@iMP4>zgVRIL*M^h_}_WTe~SVD7_ff` z|36sEzw7y(y!y8$arpmRiT|Lo{;uWs1%|)191{Ma<@e==-xd5m+4Hx8EQ&uA{5|#a zyXf!VFMo?d(f%p=``66x8h#&_{H?)`@%KLX$5G1f3jaOK|E&%Ha9{!e{v+uBF8=S{ y^Iye(&4vA6@xOfO@6x}U)!*{I?0>Z8|HsJWq#)if2mrvp{V3mH49@ZE?*9NU7YmO7 literal 0 HcmV?d00001 diff --git a/third_party/tests/rggen/rggen-sample/block_0.yml b/third_party/tests/rggen/rggen-sample/block_0.yml new file mode 100644 index 0000000000..be4be1ca8e --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0.yml @@ -0,0 +1,167 @@ +register_blocks: + - name: block_0 + byte_size: 256 + registers: + - name: register_0 + bit_fields: + - { name: bit_field_0, bit_assignment: { width: 4 }, type: rw , initial_value: 0, comment: this is register_0.bit_field_0 } + - { name: bit_field_1, bit_assignment: { width: 4 }, type: rw , initial_value: 0 } + - { name: bit_field_2, bit_assignment: { width: 1 }, type: rw , initial_value: 0 } + - { name: bit_field_3, bit_assignment: { width: 2 }, type: w1 , initial_value: 0 } + - { name: bit_field_4, bit_assignment: { width: 2 }, type: wrc , initial_value: 0 } + - { name: bit_field_5, bit_assignment: { width: 2 }, type: wrs , initial_value: 0 } + - { name: bit_field_6, bit_assignment: { width: 2 }, type: rowo, initial_value: 0 } + + - name: register_1 + bit_fields: + - <<: + - { bit_assignment: { lsb: 0, width: 1 }, type: rw, initial_value: 0 } + - labels: + - { name: foo, value: 0, comment: 'FOO value' } + - { name: bar, value: 1, comment: 'BAR value' } + + - name: register_2 + offset_address: 0x08 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: ro } + - { name: bit_field_1, bit_assignment: { lsb: 8, width: 8 }, type: rof, initial_value: 0xab } + - { name: bit_field_2, bit_assignment: { lsb: 16, width: 4 }, type: rol, initial_value: 0 } + - { name: bit_field_3, bit_assignment: { lsb: 20, width: 4 }, type: rol, initial_value: 0, reference: register_3.bit_field_3 } + - { name: bit_field_4, bit_assignment: { lsb: 24, width: 8 }, type: reserved } + + - name: register_3 + offset_address: 0x08 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: wo , initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 4, width: 4 }, type: wo1, initial_value: 0 } + - { name: bit_field_2, bit_assignment: { lsb: 8, width: 4 }, type: w0trg } + - { name: bit_field_3, bit_assignment: { lsb: 16, width: 4 }, type: w1trg } + + - name: register_4 + offset_address: 0x0C + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: rc, initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 8, width: 4 }, type: rc, initial_value: 0, reference: register_0.bit_field_0 } + - { name: bit_field_2, bit_assignment: { lsb: 12, width: 4 }, type: ro, reference: register_4.bit_field_1 } + - { name: bit_field_3, bit_assignment: { lsb: 16, width: 4 }, type: rs, initial_value: 0 } + + - name: register_5 + offset_address: 0x10 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 2 }, type: rwc, initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 2, width: 2 }, type: rwc, initial_value: 0, reference: register_3.bit_field_2 } + - { name: bit_field_2, bit_assignment: { lsb: 4, width: 2 }, type: rws, initial_value: 0 } + - { name: bit_field_3, bit_assignment: { lsb: 6, width: 2 }, type: rws, initial_value: 0, reference: register_3.bit_field_3 } + - { name: bit_field_4, bit_assignment: { lsb: 8, width: 2 }, type: rwe, initial_value: 0 } + - { name: bit_field_5, bit_assignment: { lsb: 10, width: 2 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 } + - { name: bit_field_6, bit_assignment: { lsb: 12, width: 2 }, type: rwe, initial_value: 0, reference: register_1 } + - { name: bit_field_7, bit_assignment: { lsb: 16, width: 2 }, type: rwl, initial_value: 0 } + - { name: bit_field_8, bit_assignment: { lsb: 18, width: 2 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 } + - { name: bit_field_9, bit_assignment: { lsb: 20, width: 2 }, type: rwl, initial_value: 0, reference: register_1 } + + - name: register_6 + offset_address: 0x14 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: w0c, initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 4, width: 4 }, type: w0c, initial_value: 0, reference: register_0.bit_field_0 } + - { name: bit_field_2, bit_assignment: { lsb: 8, width: 4 }, type: ro , reference: register_6.bit_field_1 } + - { name: bit_field_3, bit_assignment: { lsb: 12, width: 4 }, type: w1c, initial_value: 0 } + - { name: bit_field_4, bit_assignment: { lsb: 16, width: 4 }, type: w1c, initial_value: 0, reference: register_0.bit_field_0 } + - { name: bit_field_5, bit_assignment: { lsb: 20, width: 4 }, type: ro , reference: register_6.bit_field_4 } + - { name: bit_field_6, bit_assignment: { lsb: 24, width: 4 }, type: w0s, initial_value: 0 } + - { name: bit_field_7, bit_assignment: { lsb: 28, width: 4 }, type: w1s, initial_value: 0 } + - { name: bit_field_8, bit_assignment: { lsb: 32, width: 4 }, type: w0t, initial_value: 0 } + - { name: bit_field_9, bit_assignment: { lsb: 36, width: 4 }, type: w1t, initial_value: 0 } + + - name: register_7 + offset_address: 0x1C + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: w0crs, initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 8, width: 4 }, type: w1crs, initial_value: 0 } + - { name: bit_field_2, bit_assignment: { lsb: 16, width: 4 }, type: w0src, initial_value: 0 } + - { name: bit_field_3, bit_assignment: { lsb: 24, width: 4 }, type: w1src, initial_value: 0 } + + - name: register_8 + offset_address: 0x20 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: wc , initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 8, width: 4 }, type: ws , initial_value: 0 } + - { name: bit_field_2, bit_assignment: { lsb: 16, width: 4 }, type: woc , initial_value: 0 } + - { name: bit_field_3, bit_assignment: { lsb: 24, width: 4 }, type: wos , initial_value: 0 } + - { name: bit_field_4, bit_assignment: { lsb: 32, width: 4 }, type: wcrs, initial_value: 0 } + - { name: bit_field_5, bit_assignment: { lsb: 40, width: 4 }, type: wsrc, initial_value: 0 } + + - name: register_9 + offset_address: 0x28 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 2 }, type: rwtrg , initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 2, width: 2 }, type: rotrg } + - { name: bit_field_2, bit_assignment: { lsb: 4, width: 2 }, type: wotrg , initial_value: 0 } + - { name: bit_field_3, bit_assignment: { lsb: 6, width: 2 }, type: rowotrg, initial_value: 0 } + - { name: bit_field_4, bit_assignment: { lsb: 8, width: 2 }, type: row0trg } + - { name: bit_field_5, bit_assignment: { lsb: 10, width: 2 }, type: row1trg } + + - name: register_10 + offset_address: 0x30 + size: [4, step: 8] + bit_fields: + - <<: + # bit assignments: [1:0] [ 9: 8] [17:16] [25:24] + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 2, sequence_size: 4, step: 8 }, type: rw } + - initial_value: 0 + - <<: + # bit assignments: [3:2] [11:10] [19:18] [27:26] + - { name: bit_field_1, bit_assignment: { lsb: 2, width: 2, sequence_size: 4, step: 8 }, type: rw } + - initial_value: { default: 0 } + - <<: + # bit assignments: [5:4] [13:12] [21:20] [29:28] + - { name: bit_field_2, bit_assignment: { lsb: 4, width: 2, sequence_size: 4, step: 8 }, type: rw } + - initial_value: [0, 1, 2, 3] + + - name: register_11 + offset_address: 0x50 + size: [2, 4] + type: [indirect, register_0.bit_field_0, register_0.bit_field_1, [register_0.bit_field_2, 0]] + bit_fields: + - # bit assignments: [ 7:0] [23:16] [39:32] [55:48] + { name: bit_field_0, bit_assignment: { lsb: 0, width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 } + - # bit assignments: [15:8] [31:24] [47:40] [63:56] + { name: bit_field_1, bit_assignment: { lsb: 8, width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 } + + - name: register_12 + offset_address: 0x50 + type: [indirect, [register_0.bit_field_2, 1]] + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 1}, type: rw, initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 32, width: 1}, type: rw, initial_value: 0 } + + - name: register_13 + offset_address: 0x60 + bit_fields: + - # same with RW bit field type + { name: bit_field_0, bit_assignment: { width: 2 }, initial_value: 0, type: [custom ] } + - # same with RO bit filed type + { name: bit_field_1, bit_assignment: { width: 2 }, type: [custom, sw_write: none ] } + - # same with W1 bit field type + { name: bit_field_2, bit_assignment: { width: 2 }, initial_value: 0, type: [custom, sw_write_once: true ] } + - # same with RWTRG bit field type + { name: bit_field_3, bit_assignment: { width: 2 }, initial_value: 0, type: [custom, write_trigger: true, read_trigger: true] } + - # same with W1SRC bit field type + { name: bit_field_4, bit_assignment: { width: 2 }, initial_value: 0, type: [custom, sw_write: set_1 , sw_read: clear ] } + - # same with W1CRS bit field type + { name: bit_field_5, bit_assignment: { width: 2 }, initial_value: 0, type: [custom, sw_write: clear_1, sw_read: set ] } + - # same with W1S bit field type + { name: bit_field_6, bit_assignment: { width: 2 }, initial_value: 0, type: [custom, sw_write: set_1 , hw_clear: true ] } + - # same with W1C bit field type + { name: bit_field_7, bit_assignment: { width: 2 }, initial_value: 0, type: [custom, sw_write: clear_1, hw_set: true ] } + - # RW bit field with HW write + { name: bit_field_8, bit_assignment: { width: 2 }, initial_value: 0, type: [custom, hw_write: true ] } + + - name: register_14 + offset_address: 0x70 + type: reserved + + - name: register_15 + offset_address: 0x80 + size: 32 + type: external diff --git a/third_party/tests/rggen/rggen-sample/block_0_ral_pkg.sv b/third_party/tests/rggen/rggen-sample/block_0_ral_pkg.sv new file mode 100644 index 0000000000..38205ecc85 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0_ral_pkg.sv @@ -0,0 +1,321 @@ +package block_0_ral_pkg; + import uvm_pkg::*; + import rggen_ral_pkg::*; + `include "uvm_macros.svh" + `include "rggen_ral_macros.svh" + class register_0_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_field bit_field_3; + rand rggen_ral_field bit_field_4; + rand rggen_ral_field bit_field_5; + rand rggen_ral_rowo_field bit_field_6; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 4, "RW", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 4, 4, "RW", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_2, 8, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_3, 9, 2, "W1", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_4, 11, 2, "WRC", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_5, 13, 2, "WRS", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_6, 15, 2, "ROWO", 1, 2'h0, 1, -1, "") + endfunction + endclass + class register_1_reg_model extends rggen_ral_reg; + rand rggen_ral_field register_1; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(register_1, 0, 1, "RW", 0, 1'h0, 1, -1, "") + endfunction + endclass + class register_2_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_field bit_field_3; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 4, "RO", 1, 4'h0, 0, -1, "") + `rggen_ral_create_field(bit_field_1, 8, 8, "RO", 0, 8'hab, 1, -1, "") + `rggen_ral_create_field(bit_field_2, 16, 4, "RO", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_3, 20, 4, "RO", 1, 4'h0, 1, -1, "register_3.bit_field_3") + endfunction + endclass + class register_3_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_w0trg_field bit_field_2; + rand rggen_ral_w1trg_field bit_field_3; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 4, "WO", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 4, 4, "WO1", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_2, 8, 4, "W0TRG", 0, 4'h0, 0, -1, "") + `rggen_ral_create_field(bit_field_3, 16, 4, "W1TRG", 0, 4'h0, 0, -1, "") + endfunction + endclass + class register_4_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_field bit_field_3; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 4, "RC", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 8, 4, "RC", 1, 4'h0, 1, -1, "register_0.bit_field_0") + `rggen_ral_create_field(bit_field_2, 12, 4, "RO", 1, 4'h0, 0, -1, "register_4.bit_field_1") + `rggen_ral_create_field(bit_field_3, 16, 4, "RS", 1, 4'h0, 1, -1, "") + endfunction + endclass + class register_5_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_field bit_field_3; + rand rggen_ral_rwe_field bit_field_4; + rand rggen_ral_rwe_field bit_field_5; + rand rggen_ral_rwe_field bit_field_6; + rand rggen_ral_rwl_field bit_field_7; + rand rggen_ral_rwl_field bit_field_8; + rand rggen_ral_rwl_field bit_field_9; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 2, "RW", 1, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 2, 2, "RW", 1, 2'h0, 1, -1, "register_3.bit_field_2") + `rggen_ral_create_field(bit_field_2, 4, 2, "RW", 1, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_3, 6, 2, "RW", 1, 2'h0, 1, -1, "register_3.bit_field_3") + `rggen_ral_create_field(bit_field_4, 8, 2, "RWE", 1, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_5, 10, 2, "RWE", 0, 2'h0, 1, -1, "register_0.bit_field_2") + `rggen_ral_create_field(bit_field_6, 12, 2, "RWE", 0, 2'h0, 1, -1, "register_1.register_1") + `rggen_ral_create_field(bit_field_7, 16, 2, "RWL", 1, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_8, 18, 2, "RWL", 0, 2'h0, 1, -1, "register_0.bit_field_2") + `rggen_ral_create_field(bit_field_9, 20, 2, "RWL", 0, 2'h0, 1, -1, "register_1.register_1") + endfunction + endclass + class register_6_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_field bit_field_3; + rand rggen_ral_field bit_field_4; + rand rggen_ral_field bit_field_5; + rand rggen_ral_field bit_field_6; + rand rggen_ral_field bit_field_7; + rand rggen_ral_field bit_field_8; + rand rggen_ral_field bit_field_9; + function new(string name); + super.new(name, 64, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 4, "W0C", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 4, 4, "W0C", 1, 4'h0, 1, -1, "register_0.bit_field_0") + `rggen_ral_create_field(bit_field_2, 8, 4, "RO", 1, 4'h0, 0, -1, "register_6.bit_field_1") + `rggen_ral_create_field(bit_field_3, 12, 4, "W1C", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_4, 16, 4, "W1C", 1, 4'h0, 1, -1, "register_0.bit_field_0") + `rggen_ral_create_field(bit_field_5, 20, 4, "RO", 1, 4'h0, 0, -1, "register_6.bit_field_4") + `rggen_ral_create_field(bit_field_6, 24, 4, "W0S", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_7, 28, 4, "W1S", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_8, 32, 4, "W0T", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_9, 36, 4, "W1T", 0, 4'h0, 1, -1, "") + endfunction + endclass + class register_7_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_field bit_field_3; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 4, "W0CRS", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 8, 4, "W1CRS", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_2, 16, 4, "W0SRC", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_3, 24, 4, "W1SRC", 0, 4'h0, 1, -1, "") + endfunction + endclass + class register_8_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_field bit_field_3; + rand rggen_ral_field bit_field_4; + rand rggen_ral_field bit_field_5; + function new(string name); + super.new(name, 64, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 4, "WC", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 8, 4, "WS", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_2, 16, 4, "WOC", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_3, 24, 4, "WOS", 1, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_4, 32, 4, "WCRS", 0, 4'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_5, 40, 4, "WSRC", 0, 4'h0, 1, -1, "") + endfunction + endclass + class register_9_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + rand rggen_ral_field bit_field_2; + rand rggen_ral_rowo_field bit_field_3; + rand rggen_ral_row0trg_field bit_field_4; + rand rggen_ral_row1trg_field bit_field_5; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 2, "RW", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 2, 2, "RO", 1, 2'h0, 0, -1, "") + `rggen_ral_create_field(bit_field_2, 4, 2, "WO", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_3, 6, 2, "ROWO", 1, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_4, 8, 2, "ROW0TRG", 1, 2'h0, 0, -1, "") + `rggen_ral_create_field(bit_field_5, 10, 2, "ROW1TRG", 1, 2'h0, 0, -1, "") + endfunction + endclass + class register_10_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0[4]; + rand rggen_ral_field bit_field_1[4]; + rand rggen_ral_field bit_field_2[4]; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0[0], 0, 2, "RW", 0, 2'h0, 1, 0, "") + `rggen_ral_create_field(bit_field_0[1], 8, 2, "RW", 0, 2'h0, 1, 1, "") + `rggen_ral_create_field(bit_field_0[2], 16, 2, "RW", 0, 2'h0, 1, 2, "") + `rggen_ral_create_field(bit_field_0[3], 24, 2, "RW", 0, 2'h0, 1, 3, "") + `rggen_ral_create_field(bit_field_1[0], 2, 2, "RW", 0, 2'h0, 1, 0, "") + `rggen_ral_create_field(bit_field_1[1], 10, 2, "RW", 0, 2'h0, 1, 1, "") + `rggen_ral_create_field(bit_field_1[2], 18, 2, "RW", 0, 2'h0, 1, 2, "") + `rggen_ral_create_field(bit_field_1[3], 26, 2, "RW", 0, 2'h0, 1, 3, "") + `rggen_ral_create_field(bit_field_2[0], 4, 2, "RW", 0, 2'h0, 1, 0, "") + `rggen_ral_create_field(bit_field_2[1], 12, 2, "RW", 0, 2'h1, 1, 1, "") + `rggen_ral_create_field(bit_field_2[2], 20, 2, "RW", 0, 2'h2, 1, 2, "") + `rggen_ral_create_field(bit_field_2[3], 28, 2, "RW", 0, 2'h3, 1, 3, "") + endfunction + endclass + class register_11_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field bit_field_0[4]; + rand rggen_ral_field bit_field_1[4]; + function new(string name); + super.new(name, 64, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0[0], 0, 8, "RW", 0, 8'h00, 1, 0, "") + `rggen_ral_create_field(bit_field_0[1], 16, 8, "RW", 0, 8'h00, 1, 1, "") + `rggen_ral_create_field(bit_field_0[2], 32, 8, "RW", 0, 8'h00, 1, 2, "") + `rggen_ral_create_field(bit_field_0[3], 48, 8, "RW", 0, 8'h00, 1, 3, "") + `rggen_ral_create_field(bit_field_1[0], 8, 8, "RW", 0, 8'h00, 1, 0, "") + `rggen_ral_create_field(bit_field_1[1], 24, 8, "RW", 0, 8'h00, 1, 1, "") + `rggen_ral_create_field(bit_field_1[2], 40, 8, "RW", 0, 8'h00, 1, 2, "") + `rggen_ral_create_field(bit_field_1[3], 56, 8, "RW", 0, 8'h00, 1, 3, "") + endfunction + function void setup_index_fields(); + setup_index_field("register_0.bit_field_0", array_index[0]); + setup_index_field("register_0.bit_field_1", array_index[1]); + setup_index_field("register_0.bit_field_2", 1'h0); + endfunction + endclass + class register_12_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field bit_field_0; + rand rggen_ral_field bit_field_1; + function new(string name); + super.new(name, 64, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 32, 1, "RW", 0, 1'h0, 1, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("register_0.bit_field_2", 1'h1); + endfunction + endclass + class register_13_reg_model extends rggen_ral_reg; + rand rggen_ral_custom_field #("DEFAULT", "DEFAULT", 0, 0) bit_field_0; + rand rggen_ral_custom_field #("DEFAULT", "NONE", 0, 0) bit_field_1; + rand rggen_ral_custom_field #("DEFAULT", "DEFAULT", 1, 0) bit_field_2; + rand rggen_ral_custom_field #("DEFAULT", "DEFAULT", 0, 0) bit_field_3; + rand rggen_ral_custom_field #("CLEAR", "SET_1", 0, 0) bit_field_4; + rand rggen_ral_custom_field #("SET", "CLEAR_1", 0, 0) bit_field_5; + rand rggen_ral_custom_field #("DEFAULT", "SET_1", 0, 1) bit_field_6; + rand rggen_ral_custom_field #("DEFAULT", "CLEAR_1", 0, 1) bit_field_7; + rand rggen_ral_custom_field #("DEFAULT", "DEFAULT", 0, 1) bit_field_8; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 2, "CUSTOM", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_1, 2, 2, "CUSTOM", 1, 2'h0, 0, -1, "") + `rggen_ral_create_field(bit_field_2, 4, 2, "CUSTOM", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_3, 6, 2, "CUSTOM", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_4, 8, 2, "CUSTOM", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_5, 10, 2, "CUSTOM", 0, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_6, 12, 2, "CUSTOM", 1, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_7, 14, 2, "CUSTOM", 1, 2'h0, 1, -1, "") + `rggen_ral_create_field(bit_field_8, 16, 2, "CUSTOM", 1, 2'h0, 1, -1, "") + endfunction + endclass + class block_0_block_model #( + type REGISTER_15 = rggen_ral_block, + bit INTEGRATE_REGISTER_15 = 1 + ) extends rggen_ral_block; + rand register_0_reg_model register_0; + rand register_1_reg_model register_1; + rand register_2_reg_model register_2; + rand register_3_reg_model register_3; + rand register_4_reg_model register_4; + rand register_5_reg_model register_5; + rand register_6_reg_model register_6; + rand register_7_reg_model register_7; + rand register_8_reg_model register_8; + rand register_9_reg_model register_9; + rand register_10_reg_model register_10[4]; + rand register_11_reg_model register_11[2][4]; + rand register_12_reg_model register_12; + rand register_13_reg_model register_13; + rand REGISTER_15 register_15; + function new(string name); + super.new(name, 4, 0); + endfunction + function void build(); + `rggen_ral_create_reg(register_0, '{}, 8'h00, "RW", "g_register_0.u_register") + `rggen_ral_create_reg(register_1, '{}, 8'h04, "RW", "g_register_1.u_register") + `rggen_ral_create_reg(register_2, '{}, 8'h08, "RO", "g_register_2.u_register") + `rggen_ral_create_reg(register_3, '{}, 8'h08, "WO", "g_register_3.u_register") + `rggen_ral_create_reg(register_4, '{}, 8'h0c, "RO", "g_register_4.u_register") + `rggen_ral_create_reg(register_5, '{}, 8'h10, "RW", "g_register_5.u_register") + `rggen_ral_create_reg(register_6, '{}, 8'h14, "RW", "g_register_6.u_register") + `rggen_ral_create_reg(register_7, '{}, 8'h1c, "RW", "g_register_7.u_register") + `rggen_ral_create_reg(register_8, '{}, 8'h20, "RW", "g_register_8.u_register") + `rggen_ral_create_reg(register_9, '{}, 8'h28, "RW", "g_register_9.u_register") + `rggen_ral_create_reg(register_10[0], '{0}, 8'h30, "RW", "g_register_10.g[0].u_register") + `rggen_ral_create_reg(register_10[1], '{1}, 8'h38, "RW", "g_register_10.g[1].u_register") + `rggen_ral_create_reg(register_10[2], '{2}, 8'h40, "RW", "g_register_10.g[2].u_register") + `rggen_ral_create_reg(register_10[3], '{3}, 8'h48, "RW", "g_register_10.g[3].u_register") + `rggen_ral_create_reg(register_11[0][0], '{0, 0}, 8'h50, "RW", "g_register_11.g[0].g[0].u_register") + `rggen_ral_create_reg(register_11[0][1], '{0, 1}, 8'h50, "RW", "g_register_11.g[0].g[1].u_register") + `rggen_ral_create_reg(register_11[0][2], '{0, 2}, 8'h50, "RW", "g_register_11.g[0].g[2].u_register") + `rggen_ral_create_reg(register_11[0][3], '{0, 3}, 8'h50, "RW", "g_register_11.g[0].g[3].u_register") + `rggen_ral_create_reg(register_11[1][0], '{1, 0}, 8'h50, "RW", "g_register_11.g[1].g[0].u_register") + `rggen_ral_create_reg(register_11[1][1], '{1, 1}, 8'h50, "RW", "g_register_11.g[1].g[1].u_register") + `rggen_ral_create_reg(register_11[1][2], '{1, 2}, 8'h50, "RW", "g_register_11.g[1].g[2].u_register") + `rggen_ral_create_reg(register_11[1][3], '{1, 3}, 8'h50, "RW", "g_register_11.g[1].g[3].u_register") + `rggen_ral_create_reg(register_12, '{}, 8'h50, "RW", "g_register_12.u_register") + `rggen_ral_create_reg(register_13, '{}, 8'h60, "RW", "g_register_13.u_register") + `rggen_ral_create_block(register_15, 8'h80, this, INTEGRATE_REGISTER_15) + endfunction + endclass +endpackage diff --git a/third_party/tests/rggen/rggen-sample/block_0_rtl_pkg.sv b/third_party/tests/rggen/rggen-sample/block_0_rtl_pkg.sv new file mode 100644 index 0000000000..e0b8d2fe0d --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_0_rtl_pkg.sv @@ -0,0 +1,267 @@ +package block_0_rtl_pkg; + localparam int REGISTER_0_BYTE_WIDTH = 4; + localparam int REGISTER_0_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_0_BYTE_OFFSET = 8'h00; + localparam int REGISTER_0_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_0_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_0_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_0_BIT_FIELD_1_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_0_BIT_FIELD_1_BIT_MASK = 4'hf; + localparam int REGISTER_0_BIT_FIELD_1_BIT_OFFSET = 4; + localparam int REGISTER_0_BIT_FIELD_2_BIT_WIDTH = 1; + localparam bit REGISTER_0_BIT_FIELD_2_BIT_MASK = 1'h1; + localparam int REGISTER_0_BIT_FIELD_2_BIT_OFFSET = 8; + localparam int REGISTER_0_BIT_FIELD_3_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_0_BIT_FIELD_3_BIT_MASK = 2'h3; + localparam int REGISTER_0_BIT_FIELD_3_BIT_OFFSET = 9; + localparam int REGISTER_0_BIT_FIELD_4_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_0_BIT_FIELD_4_BIT_MASK = 2'h3; + localparam int REGISTER_0_BIT_FIELD_4_BIT_OFFSET = 11; + localparam int REGISTER_0_BIT_FIELD_5_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_0_BIT_FIELD_5_BIT_MASK = 2'h3; + localparam int REGISTER_0_BIT_FIELD_5_BIT_OFFSET = 13; + localparam int REGISTER_0_BIT_FIELD_6_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_0_BIT_FIELD_6_BIT_MASK = 2'h3; + localparam int REGISTER_0_BIT_FIELD_6_BIT_OFFSET = 15; + localparam int REGISTER_1_BYTE_WIDTH = 4; + localparam int REGISTER_1_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_1_BYTE_OFFSET = 8'h04; + localparam int REGISTER_1_BIT_WIDTH = 1; + localparam bit REGISTER_1_BIT_MASK = 1'h1; + localparam int REGISTER_1_BIT_OFFSET = 0; + localparam bit REGISTER_1_FOO = 1'h0; + localparam bit REGISTER_1_BAR = 1'h1; + localparam int REGISTER_2_BYTE_WIDTH = 4; + localparam int REGISTER_2_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_2_BYTE_OFFSET = 8'h08; + localparam int REGISTER_2_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_2_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_2_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_2_BIT_FIELD_1_BIT_WIDTH = 8; + localparam bit [7:0] REGISTER_2_BIT_FIELD_1_BIT_MASK = 8'hff; + localparam int REGISTER_2_BIT_FIELD_1_BIT_OFFSET = 8; + localparam int REGISTER_2_BIT_FIELD_2_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_2_BIT_FIELD_2_BIT_MASK = 4'hf; + localparam int REGISTER_2_BIT_FIELD_2_BIT_OFFSET = 16; + localparam int REGISTER_2_BIT_FIELD_3_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_2_BIT_FIELD_3_BIT_MASK = 4'hf; + localparam int REGISTER_2_BIT_FIELD_3_BIT_OFFSET = 20; + localparam int REGISTER_3_BYTE_WIDTH = 4; + localparam int REGISTER_3_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_3_BYTE_OFFSET = 8'h08; + localparam int REGISTER_3_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_3_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_3_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_3_BIT_FIELD_1_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_3_BIT_FIELD_1_BIT_MASK = 4'hf; + localparam int REGISTER_3_BIT_FIELD_1_BIT_OFFSET = 4; + localparam int REGISTER_3_BIT_FIELD_2_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_3_BIT_FIELD_2_BIT_MASK = 4'hf; + localparam int REGISTER_3_BIT_FIELD_2_BIT_OFFSET = 8; + localparam int REGISTER_3_BIT_FIELD_3_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_3_BIT_FIELD_3_BIT_MASK = 4'hf; + localparam int REGISTER_3_BIT_FIELD_3_BIT_OFFSET = 16; + localparam int REGISTER_4_BYTE_WIDTH = 4; + localparam int REGISTER_4_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_4_BYTE_OFFSET = 8'h0c; + localparam int REGISTER_4_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_4_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_4_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_4_BIT_FIELD_1_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_4_BIT_FIELD_1_BIT_MASK = 4'hf; + localparam int REGISTER_4_BIT_FIELD_1_BIT_OFFSET = 8; + localparam int REGISTER_4_BIT_FIELD_2_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_4_BIT_FIELD_2_BIT_MASK = 4'hf; + localparam int REGISTER_4_BIT_FIELD_2_BIT_OFFSET = 12; + localparam int REGISTER_4_BIT_FIELD_3_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_4_BIT_FIELD_3_BIT_MASK = 4'hf; + localparam int REGISTER_4_BIT_FIELD_3_BIT_OFFSET = 16; + localparam int REGISTER_5_BYTE_WIDTH = 4; + localparam int REGISTER_5_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_5_BYTE_OFFSET = 8'h10; + localparam int REGISTER_5_BIT_FIELD_0_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_0_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_5_BIT_FIELD_1_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_1_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_1_BIT_OFFSET = 2; + localparam int REGISTER_5_BIT_FIELD_2_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_2_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_2_BIT_OFFSET = 4; + localparam int REGISTER_5_BIT_FIELD_3_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_3_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_3_BIT_OFFSET = 6; + localparam int REGISTER_5_BIT_FIELD_4_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_4_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_4_BIT_OFFSET = 8; + localparam int REGISTER_5_BIT_FIELD_5_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_5_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_5_BIT_OFFSET = 10; + localparam int REGISTER_5_BIT_FIELD_6_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_6_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_6_BIT_OFFSET = 12; + localparam int REGISTER_5_BIT_FIELD_7_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_7_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_7_BIT_OFFSET = 16; + localparam int REGISTER_5_BIT_FIELD_8_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_8_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_8_BIT_OFFSET = 18; + localparam int REGISTER_5_BIT_FIELD_9_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_5_BIT_FIELD_9_BIT_MASK = 2'h3; + localparam int REGISTER_5_BIT_FIELD_9_BIT_OFFSET = 20; + localparam int REGISTER_6_BYTE_WIDTH = 8; + localparam int REGISTER_6_BYTE_SIZE = 8; + localparam bit [7:0] REGISTER_6_BYTE_OFFSET = 8'h14; + localparam int REGISTER_6_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_6_BIT_FIELD_1_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_1_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_1_BIT_OFFSET = 4; + localparam int REGISTER_6_BIT_FIELD_2_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_2_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_2_BIT_OFFSET = 8; + localparam int REGISTER_6_BIT_FIELD_3_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_3_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_3_BIT_OFFSET = 12; + localparam int REGISTER_6_BIT_FIELD_4_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_4_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_4_BIT_OFFSET = 16; + localparam int REGISTER_6_BIT_FIELD_5_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_5_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_5_BIT_OFFSET = 20; + localparam int REGISTER_6_BIT_FIELD_6_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_6_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_6_BIT_OFFSET = 24; + localparam int REGISTER_6_BIT_FIELD_7_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_7_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_7_BIT_OFFSET = 28; + localparam int REGISTER_6_BIT_FIELD_8_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_8_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_8_BIT_OFFSET = 32; + localparam int REGISTER_6_BIT_FIELD_9_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_6_BIT_FIELD_9_BIT_MASK = 4'hf; + localparam int REGISTER_6_BIT_FIELD_9_BIT_OFFSET = 36; + localparam int REGISTER_7_BYTE_WIDTH = 4; + localparam int REGISTER_7_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_7_BYTE_OFFSET = 8'h1c; + localparam int REGISTER_7_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_7_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_7_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_7_BIT_FIELD_1_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_7_BIT_FIELD_1_BIT_MASK = 4'hf; + localparam int REGISTER_7_BIT_FIELD_1_BIT_OFFSET = 8; + localparam int REGISTER_7_BIT_FIELD_2_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_7_BIT_FIELD_2_BIT_MASK = 4'hf; + localparam int REGISTER_7_BIT_FIELD_2_BIT_OFFSET = 16; + localparam int REGISTER_7_BIT_FIELD_3_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_7_BIT_FIELD_3_BIT_MASK = 4'hf; + localparam int REGISTER_7_BIT_FIELD_3_BIT_OFFSET = 24; + localparam int REGISTER_8_BYTE_WIDTH = 8; + localparam int REGISTER_8_BYTE_SIZE = 8; + localparam bit [7:0] REGISTER_8_BYTE_OFFSET = 8'h20; + localparam int REGISTER_8_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_8_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_8_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_8_BIT_FIELD_1_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_8_BIT_FIELD_1_BIT_MASK = 4'hf; + localparam int REGISTER_8_BIT_FIELD_1_BIT_OFFSET = 8; + localparam int REGISTER_8_BIT_FIELD_2_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_8_BIT_FIELD_2_BIT_MASK = 4'hf; + localparam int REGISTER_8_BIT_FIELD_2_BIT_OFFSET = 16; + localparam int REGISTER_8_BIT_FIELD_3_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_8_BIT_FIELD_3_BIT_MASK = 4'hf; + localparam int REGISTER_8_BIT_FIELD_3_BIT_OFFSET = 24; + localparam int REGISTER_8_BIT_FIELD_4_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_8_BIT_FIELD_4_BIT_MASK = 4'hf; + localparam int REGISTER_8_BIT_FIELD_4_BIT_OFFSET = 32; + localparam int REGISTER_8_BIT_FIELD_5_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_8_BIT_FIELD_5_BIT_MASK = 4'hf; + localparam int REGISTER_8_BIT_FIELD_5_BIT_OFFSET = 40; + localparam int REGISTER_9_BYTE_WIDTH = 4; + localparam int REGISTER_9_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_9_BYTE_OFFSET = 8'h28; + localparam int REGISTER_9_BIT_FIELD_0_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_9_BIT_FIELD_0_BIT_MASK = 2'h3; + localparam int REGISTER_9_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_9_BIT_FIELD_1_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_9_BIT_FIELD_1_BIT_MASK = 2'h3; + localparam int REGISTER_9_BIT_FIELD_1_BIT_OFFSET = 2; + localparam int REGISTER_9_BIT_FIELD_2_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_9_BIT_FIELD_2_BIT_MASK = 2'h3; + localparam int REGISTER_9_BIT_FIELD_2_BIT_OFFSET = 4; + localparam int REGISTER_9_BIT_FIELD_3_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_9_BIT_FIELD_3_BIT_MASK = 2'h3; + localparam int REGISTER_9_BIT_FIELD_3_BIT_OFFSET = 6; + localparam int REGISTER_9_BIT_FIELD_4_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_9_BIT_FIELD_4_BIT_MASK = 2'h3; + localparam int REGISTER_9_BIT_FIELD_4_BIT_OFFSET = 8; + localparam int REGISTER_9_BIT_FIELD_5_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_9_BIT_FIELD_5_BIT_MASK = 2'h3; + localparam int REGISTER_9_BIT_FIELD_5_BIT_OFFSET = 10; + localparam int REGISTER_10_BYTE_WIDTH = 4; + localparam int REGISTER_10_BYTE_SIZE = 32; + localparam int REGISTER_10_ARRAY_SIZE[1] = '{4}; + localparam bit [7:0] REGISTER_10_BYTE_OFFSET[4] = '{8'h30, 8'h38, 8'h40, 8'h48}; + localparam int REGISTER_10_BIT_FIELD_0_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_10_BIT_FIELD_0_BIT_MASK = 2'h3; + localparam int REGISTER_10_BIT_FIELD_0_BIT_OFFSET[4] = '{0, 8, 16, 24}; + localparam int REGISTER_10_BIT_FIELD_1_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_10_BIT_FIELD_1_BIT_MASK = 2'h3; + localparam int REGISTER_10_BIT_FIELD_1_BIT_OFFSET[4] = '{2, 10, 18, 26}; + localparam int REGISTER_10_BIT_FIELD_2_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_10_BIT_FIELD_2_BIT_MASK = 2'h3; + localparam int REGISTER_10_BIT_FIELD_2_BIT_OFFSET[4] = '{4, 12, 20, 28}; + localparam int REGISTER_11_BYTE_WIDTH = 8; + localparam int REGISTER_11_BYTE_SIZE = 8; + localparam int REGISTER_11_ARRAY_SIZE[2] = '{2, 4}; + localparam bit [7:0] REGISTER_11_BYTE_OFFSET[2][4] = '{'{8'h50, 8'h50, 8'h50, 8'h50}, '{8'h50, 8'h50, 8'h50, 8'h50}}; + localparam int REGISTER_11_BIT_FIELD_0_BIT_WIDTH = 8; + localparam bit [7:0] REGISTER_11_BIT_FIELD_0_BIT_MASK = 8'hff; + localparam int REGISTER_11_BIT_FIELD_0_BIT_OFFSET[4] = '{0, 16, 32, 48}; + localparam int REGISTER_11_BIT_FIELD_1_BIT_WIDTH = 8; + localparam bit [7:0] REGISTER_11_BIT_FIELD_1_BIT_MASK = 8'hff; + localparam int REGISTER_11_BIT_FIELD_1_BIT_OFFSET[4] = '{8, 24, 40, 56}; + localparam int REGISTER_12_BYTE_WIDTH = 8; + localparam int REGISTER_12_BYTE_SIZE = 8; + localparam bit [7:0] REGISTER_12_BYTE_OFFSET = 8'h50; + localparam int REGISTER_12_BIT_FIELD_0_BIT_WIDTH = 1; + localparam bit REGISTER_12_BIT_FIELD_0_BIT_MASK = 1'h1; + localparam int REGISTER_12_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_12_BIT_FIELD_1_BIT_WIDTH = 1; + localparam bit REGISTER_12_BIT_FIELD_1_BIT_MASK = 1'h1; + localparam int REGISTER_12_BIT_FIELD_1_BIT_OFFSET = 32; + localparam int REGISTER_13_BYTE_WIDTH = 4; + localparam int REGISTER_13_BYTE_SIZE = 4; + localparam bit [7:0] REGISTER_13_BYTE_OFFSET = 8'h60; + localparam int REGISTER_13_BIT_FIELD_0_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_0_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_13_BIT_FIELD_1_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_1_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_1_BIT_OFFSET = 2; + localparam int REGISTER_13_BIT_FIELD_2_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_2_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_2_BIT_OFFSET = 4; + localparam int REGISTER_13_BIT_FIELD_3_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_3_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_3_BIT_OFFSET = 6; + localparam int REGISTER_13_BIT_FIELD_4_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_4_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_4_BIT_OFFSET = 8; + localparam int REGISTER_13_BIT_FIELD_5_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_5_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_5_BIT_OFFSET = 10; + localparam int REGISTER_13_BIT_FIELD_6_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_6_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_6_BIT_OFFSET = 12; + localparam int REGISTER_13_BIT_FIELD_7_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_7_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_7_BIT_OFFSET = 14; + localparam int REGISTER_13_BIT_FIELD_8_BIT_WIDTH = 2; + localparam bit [1:0] REGISTER_13_BIT_FIELD_8_BIT_MASK = 2'h3; + localparam int REGISTER_13_BIT_FIELD_8_BIT_OFFSET = 16; + localparam int REGISTER_15_BYTE_WIDTH = 4; + localparam int REGISTER_15_BYTE_SIZE = 128; + localparam bit [7:0] REGISTER_15_BYTE_OFFSET = 8'h80; +endpackage diff --git a/third_party/tests/rggen/rggen-sample/block_1.h b/third_party/tests/rggen/rggen-sample/block_1.h new file mode 100644 index 0000000000..757abf128a --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.h @@ -0,0 +1,111 @@ +#ifndef BLOCK_1_H +#define BLOCK_1_H +#include "stdint.h" +#define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 8 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_MASK 0xff +#define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BYTE_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BYTE_SIZE 4 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET 0x0 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_WIDTH 8 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_MASK 0xff +#define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BYTE_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BYTE_SIZE 4 +#define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET 0x4 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 8 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_MASK 0xff +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_SIZE 4 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_ARRAY_DIMENSION 1 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_ARRAY_SIZE_0 2 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_OFFSET_0 0x10 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_OFFSET_1 0x10 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_WIDTH 8 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_MASK 0xff +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_OFFSET 0 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_SIZE 4 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_ARRAY_DIMENSION 1 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_ARRAY_SIZE_0 2 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_OFFSET_0 0x10 +#define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_OFFSET_1 0x10 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_MASK 0xf +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET_0 0 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET_1 4 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_MASK 0xf +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_OFFSET_0 8 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_OFFSET_1 12 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_MASK 0xf +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_OFFSET_0 16 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_OFFSET_1 20 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_SIZE 48 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_DIMENSION 3 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_SIZE_0 2 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_SIZE_1 2 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_SIZE_2 3 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_0_0 0x20 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_0_1 0x24 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_0_2 0x28 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_1_0 0x2c +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_1_1 0x30 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_1_2 0x34 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_0_0 0x40 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_0_1 0x44 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_0_2 0x48 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_1_0 0x4c +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_1_1 0x50 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_1_2 0x54 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_WIDTH 1 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_MASK 0x1 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET_0 0 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET_1 1 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_WIDTH 4 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_SIZE 8 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_ARRAY_DIMENSION 1 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_ARRAY_SIZE_0 2 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET_0 0x38 +#define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET_1 0x58 +typedef struct { + uint32_t register_0; + uint32_t register_1; +} block_1_register_file_0_t; +typedef union { + uint32_t register_0; + uint32_t register_1; +} block_1_register_file_1_reg_0x00_t; +typedef struct { + block_1_register_file_1_reg_0x00_t reg_0x00; +} block_1_register_file_1_t; +typedef struct { + uint32_t register_0[2][3]; + uint32_t register_1; +} block_1_register_file_2_register_file_0_t; +typedef struct { + block_1_register_file_2_register_file_0_t register_file_0; + uint32_t __reserved_0x1c; +} block_1_register_file_2_t; +typedef struct { + block_1_register_file_0_t register_file_0; + uint32_t __reserved_0x08; + uint32_t __reserved_0x0c; + block_1_register_file_1_t register_file_1; + uint32_t __reserved_0x14; + uint32_t __reserved_0x18; + uint32_t __reserved_0x1c; + block_1_register_file_2_t register_file_2[2]; + uint32_t __reserved_0x60; + uint32_t __reserved_0x64; + uint32_t __reserved_0x68; + uint32_t __reserved_0x6c; + uint32_t __reserved_0x70; + uint32_t __reserved_0x74; + uint32_t __reserved_0x78; + uint32_t __reserved_0x7c; +} block_1_t; +#endif diff --git a/third_party/tests/rggen/rggen-sample/block_1.md b/third_party/tests/rggen/rggen-sample/block_1.md new file mode 100644 index 0000000000..8c684f5066 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.md @@ -0,0 +1,105 @@ +## block_1 + +* byte_size + * 128 +* comment + * this is block_1.
this block includes six registers. + +|name|offset_address| +|:--|:--| +|[register_file_0.register_0](#block_1-register_file_0-register_0)|0x00| +|[register_file_0.register_1](#block_1-register_file_0-register_1)|0x04| +|[register_file_1.register_0[2]](#block_1-register_file_1-register_0)|0x10
0x10| +|[register_file_1.register_1[2]](#block_1-register_file_1-register_1)|0x10
0x10| +|[register_file_2[2].register_file_0.register_0[2][3]](#block_1-register_file_2-register_file_0-register_0)|0x20
0x24
0x28
0x2c
0x30
0x34
0x40
0x44
0x48
0x4c
0x50
0x54| +|[register_file_2[2].register_file_0.register_1](#block_1-register_file_2-register_file_0-register_1)|0x38
0x58| + +###
register_file_0.register_0 + +* offset_address + * 0x00 +* type + * default +* comment + * this is register_0.
bit_field_0 is within this register. + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[7:0]|rw|0x00|||| + +###
register_file_0.register_1 + +* offset_address + * 0x04 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[7:0]|rw|0x00|||| + +###
register_file_1.register_0[2] + +* offset_address + * 0x10 + * 0x10 +* type + * indirect +* index_bit_fields + * register_file_0.register_0.bit_field_0 + * register_file_0.register_1.bit_field_0: 0 + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[7:0]|rw|0x00|||| + +###
register_file_1.register_1[2] + +* offset_address + * 0x10 + * 0x10 +* type + * indirect +* index_bit_fields + * register_file_0.register_0.bit_field_0 + * register_file_0.register_1.bit_field_0: 1 + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0|[7:0]|rw|0x00|||| + +###
register_file_2[2].register_file_0.register_0[2][3] + +* offset_address + * 0x20 + * 0x24 + * 0x28 + * 0x2c + * 0x30 + * 0x34 + * 0x40 + * 0x44 + * 0x48 + * 0x4c + * 0x50 + * 0x54 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0[2]|[3:0]
[7:4]|rw|0x0|||| +|bit_field_1[2]|[11:8]
[15:12]|rwe|0x0|register_file_0.register_0.bit_field_0||| +|bit_field_2[2]|[19:16]
[23:20]|rwl|0x0|register_file_2.register_file_0.register_1.bit_field_0||| + +###
register_file_2[2].register_file_0.register_1 + +* offset_address + * 0x38 + * 0x58 +* type + * default + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|bit_field_0[2]|[0]
[1]|rw|0x0|||| diff --git a/third_party/tests/rggen/rggen-sample/block_1.rb b/third_party/tests/rggen/rggen-sample/block_1.rb new file mode 100644 index 0000000000..4cc7d84d16 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.rb @@ -0,0 +1,76 @@ +# frozen_string_literal: true + +register_block { + name 'block_1' + byte_size 128 + comment <<~COMMENT + this is block_1. + this block includes six registers. + COMMENT + + register_file { + name 'register_file_0' + offset_address 0x00 + register { + name 'register_0' + offset_address 0x00 + comment [ + 'this is register_0.', + 'bit_field_0 is within this register.' + ] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8; type :rw; initial_value 0 } + } + register { + name 'register_1' + offset_address 0x04 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8; type :rw; initial_value 0 } + } + } + + register_file { + name 'register_file_1' + offset_address 0x10 + register { + name 'register_0' + offset_address 0x00 + size [2] + type [ + :indirect, + 'register_file_0.register_0.bit_field_0', ['register_file_0.register_1.bit_field_0', 0] + ] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8; type :rw; initial_value 0 } + } + register { + name 'register_1' + offset_address 0x00 + size [2] + type [ + :indirect, + 'register_file_0.register_0.bit_field_0', ['register_file_0.register_1.bit_field_0', 1] + ] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8; type :rw; initial_value 0 } + } + } + + register_file { + name 'register_file_2' + offset_address 0x20 + size [2, step: 32] + register_file { + name 'register_file_0' + register { + name 'register_0' + offset_address 0x00 + size [2, 3] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4, sequence_size: 2; type :rw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 4, sequence_size: 2; type :rwe; initial_value 0; reference 'register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 4, sequence_size: 2; type :rwl; initial_value 0; reference 'register_file_2.register_file_0.register_1.bit_field_0' } + } + register { + name 'register_1' + offset_address 0x18 + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1, sequence_size: 2; type :rw; initial_value 0 } + } + } + } +} diff --git a/third_party/tests/rggen/rggen-sample/block_1.sv b/third_party/tests/rggen/rggen-sample/block_1.sv new file mode 100644 index 0000000000..1252517e4f --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.sv @@ -0,0 +1,421 @@ +`ifndef rggen_connect_bit_field_if + `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \ + assign FIF.valid = RIF.valid; \ + assign FIF.read_mask = RIF.read_mask[LSB+:WIDTH]; \ + assign FIF.write_mask = RIF.write_mask[LSB+:WIDTH]; \ + assign FIF.write_data = RIF.write_data[LSB+:WIDTH]; \ + assign RIF.read_data[LSB+:WIDTH] = FIF.read_data; \ + assign RIF.value[LSB+:WIDTH] = FIF.value; +`endif +`ifndef rggen_tie_off_unused_signals + `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \ + if (1) begin : __g_tie_off \ + genvar __i; \ + for (__i = 0;__i < WIDTH;++__i) begin : g \ + if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \ + assign RIF.read_data[__i] = 1'b0; \ + assign RIF.value[__i] = 1'b0; \ + end \ + end \ + end +`endif +module block_1 + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 7, + parameter bit PRE_DECODE = 0, + parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, + parameter bit ERROR_STATUS = 0, + parameter bit [31:0] DEFAULT_READ_DATA = '0, + parameter bit INSERT_SLICER = 0 +)( + input logic i_clk, + input logic i_rst_n, + rggen_apb_if.slave apb_if, + output logic [7:0] o_register_file_0_register_0_bit_field_0, + output logic [7:0] o_register_file_0_register_1_bit_field_0, + output logic [1:0][7:0] o_register_file_1_register_0_bit_field_0, + output logic [1:0][7:0] o_register_file_1_register_1_bit_field_0, + output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_0, + output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_1, + output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_2, + output logic [1:0][1:0] o_register_file_2_register_file_0_register_1_bit_field_0 +); + rggen_register_if #(7, 32, 32) register_if[20](); + rggen_apb_adapter #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .LOCAL_ADDRESS_WIDTH (7), + .BUS_WIDTH (32), + .REGISTERS (20), + .PRE_DECODE (PRE_DECODE), + .BASE_ADDRESS (BASE_ADDRESS), + .BYTE_SIZE (128), + .ERROR_STATUS (ERROR_STATUS), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA), + .INSERT_SLICER (INSERT_SLICER) + ) u_adapter ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .apb_if (apb_if), + .register_if (register_if) + ); + generate if (1) begin : g_register_file_0 + if (1) begin : g_register_0 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[0]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [7:0] INITIAL_VALUE = 8'h00; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_0_register_0_bit_field_0), + .o_value_unmasked () + ); + end + end + if (1) begin : g_register_1 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[1]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [7:0] INITIAL_VALUE = 8'h00; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_0_register_1_bit_field_0), + .o_value_unmasked () + ); + end + end + end endgenerate + generate if (1) begin : g_register_file_1 + if (1) begin : g_register_0 + genvar i; + for (i = 0;i < 2;++i) begin : g + rggen_bit_field_if #(32) bit_field_if(); + logic [15:0] indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + assign indirect_index = {register_if[0].value[0+:8], register_if[1].value[0+:8]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32), + .INDIRECT_INDEX_WIDTH (16), + .INDIRECT_INDEX_VALUE ({i[0+:8], 8'h00}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[2+i]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [7:0] INITIAL_VALUE = 8'h00; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_1_register_0_bit_field_0[i]), + .o_value_unmasked () + ); + end + end + end + if (1) begin : g_register_1 + genvar i; + for (i = 0;i < 2;++i) begin : g + rggen_bit_field_if #(32) bit_field_if(); + logic [15:0] indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + assign indirect_index = {register_if[0].value[0+:8], register_if[1].value[0+:8]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32), + .INDIRECT_INDEX_WIDTH (16), + .INDIRECT_INDEX_VALUE ({i[0+:8], 8'h01}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[4+i]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + localparam bit [7:0] INITIAL_VALUE = 8'h00; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_1_register_1_bit_field_0[i]), + .o_value_unmasked () + ); + end + end + end + end endgenerate + generate if (1) begin : g_register_file_2 + genvar i; + for (i = 0;i < 2;++i) begin : g + if (1) begin : g_register_file_0 + if (1) begin : g_register_0 + genvar j; + genvar k; + for (j = 0;j < 2;++j) begin : g + for (k = 0;k < 3;++k) begin : g + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h00ffffff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h20+7'(32*i)+7'(4*(3*j+k))), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[6+7*i+3*j+k]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + genvar l; + for (l = 0;l < 2;++l) begin : g + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+4*l, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_1 + genvar l; + for (l = 0;l < 2;++l) begin : g + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+4*l, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (register_if[0].value[0+:1]), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_2 + genvar l; + for (l = 0;l < 2;++l) begin : g + localparam bit [3:0] INITIAL_VALUE = 4'h0; + rggen_bit_field_if #(4) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16+4*l, 4) + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable (register_if[6+7*i+6].value[0+1*l+:1]), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l]), + .o_value_unmasked () + ); + end + end + end + end + end + if (1) begin : g_register_1 + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h00000003, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h20+7'(32*i)+7'h18), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[6+7*i+6]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_bit_field_0 + genvar j; + for (j = 0;j < 2;++j) begin : g + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+1*j, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_2_register_file_0_register_1_bit_field_0[i][j]), + .o_value_unmasked () + ); + end + end + end + end + end + end endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sample/block_1.toml b/third_party/tests/rggen/rggen-sample/block_1.toml new file mode 100644 index 0000000000..07d5f6764e --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.toml @@ -0,0 +1,100 @@ +[[register_blocks]] +name = 'block_1' +byte_size = 128 +comment = ''' +this is block_1. +this block includes six registers. +''' + +[[register_blocks.register_files]] +name = 'register_file_0' +offset_address = 0x00 + +[[register_blocks.register_files.registers]] +name = 'register_0' +offset_address = 0x00 +comment = ''' +this is register_0. +bit_field_0 is within this register. +''' +[[register_blocks.register_files.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 8 } +type = 'rw' +initial_value = 0 + +[[register_blocks.register_files.registers]] +name = 'register_1' +offset_address = 0x04 +[[register_blocks.register_files.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 8 } +type = 'rw' +initial_value = 0 + +[[register_blocks.register_files]] +name = 'register_file_1' +offset_address = 0x10 + +[[register_blocks.register_files.registers]] +name = 'register_0' +offset_address = 0x00 +size = [2] +type = ['indirect', 'register_file_0.register_0.bit_field_0', ['register_file_0.register_1.bit_field_0', 0]] +[[register_blocks.register_files.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 8 } +type = 'rw' +initial_value = 0 + +[[register_blocks.register_files.registers]] +name = 'register_1' +offset_address = 0x00 +size = [2] +type = ['indirect', 'register_file_0.register_0.bit_field_0', ['register_file_0.register_1.bit_field_0', 1]] +[[register_blocks.register_files.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 8 } +type = 'rw' +initial_value = 0 + +[[register_blocks.register_files]] +name = 'register_file_2' +offset_address = 0x20 +size = [2, { step = 32 }] + +[[register_blocks.register_files.register_files]] +name = 'register_file_0' +offset_address = 0x00 + +[[register_blocks.register_files.register_files.registers]] +name = 'register_0' +offset_address = 0x00 +size = [2, 3] +[[register_blocks.register_files.register_files.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 4, sequence_size = 2 } +type = 'rw' +initial_value = 0 +[[register_blocks.register_files.register_files.registers.bit_fields]] +name = 'bit_field_1' +bit_assignment = { lsb = 8, width = 4, sequence_size = 2 } +type = 'rwe' +initial_value = 0 +reference = 'register_file_0.register_0.bit_field_0' + +[[register_blocks.register_files.register_files.registers.bit_fields]] +name = 'bit_field_2' +bit_assignment = { lsb = 16, width = 4, sequence_size = 2 } +type = 'rwl' +initial_value = 0 +reference = 'register_file_2.register_file_0.register_1.bit_field_0' + +[[register_blocks.register_files.register_files.registers]] +name = 'register_1' +offset_address = 0x18 +[[register_blocks.register_files.register_files.registers.bit_fields]] +name = 'bit_field_0' +bit_assignment = { lsb = 0, width = 1, sequence_size = 2 } +type = 'rw' +initial_value = 0 diff --git a/third_party/tests/rggen/rggen-sample/block_1.v b/third_party/tests/rggen/rggen-sample/block_1.v new file mode 100644 index 0000000000..84752e3af1 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.v @@ -0,0 +1,558 @@ +`include "rggen_rtl_macros.vh" +module block_1 #( + parameter ADDRESS_WIDTH = 7, + parameter PRE_DECODE = 0, + parameter [ADDRESS_WIDTH-1:0] BASE_ADDRESS = 0, + parameter ERROR_STATUS = 0, + parameter [31:0] DEFAULT_READ_DATA = 0, + parameter INSERT_SLICER = 0 +)( + input i_clk, + input i_rst_n, + input i_psel, + input i_penable, + input [ADDRESS_WIDTH-1:0] i_paddr, + input [2:0] i_pprot, + input i_pwrite, + input [3:0] i_pstrb, + input [31:0] i_pwdata, + output o_pready, + output [31:0] o_prdata, + output o_pslverr, + output [7:0] o_register_file_0_register_0_bit_field_0, + output [7:0] o_register_file_0_register_1_bit_field_0, + output [15:0] o_register_file_1_register_0_bit_field_0, + output [15:0] o_register_file_1_register_1_bit_field_0, + output [95:0] o_register_file_2_register_file_0_register_0_bit_field_0, + output [95:0] o_register_file_2_register_file_0_register_0_bit_field_1, + output [95:0] o_register_file_2_register_file_0_register_0_bit_field_2, + output [3:0] o_register_file_2_register_file_0_register_1_bit_field_0 +); + wire w_register_valid; + wire [1:0] w_register_access; + wire [6:0] w_register_address; + wire [31:0] w_register_write_data; + wire [3:0] w_register_strobe; + wire [19:0] w_register_active; + wire [19:0] w_register_ready; + wire [39:0] w_register_status; + wire [639:0] w_register_read_data; + wire [639:0] w_register_value; + rggen_apb_adapter #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .LOCAL_ADDRESS_WIDTH (7), + .BUS_WIDTH (32), + .REGISTERS (20), + .PRE_DECODE (PRE_DECODE), + .BASE_ADDRESS (BASE_ADDRESS), + .BYTE_SIZE (128), + .ERROR_STATUS (ERROR_STATUS), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA), + .INSERT_SLICER (INSERT_SLICER) + ) u_adapter ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_psel (i_psel), + .i_penable (i_penable), + .i_paddr (i_paddr), + .i_pprot (i_pprot), + .i_pwrite (i_pwrite), + .i_pstrb (i_pstrb), + .i_pwdata (i_pwdata), + .o_pready (o_pready), + .o_prdata (o_prdata), + .o_pslverr (o_pslverr), + .o_register_valid (w_register_valid), + .o_register_access (w_register_access), + .o_register_address (w_register_address), + .o_register_write_data (w_register_write_data), + .o_register_strobe (w_register_strobe), + .i_register_active (w_register_active), + .i_register_ready (w_register_ready), + .i_register_status (w_register_status), + .i_register_read_data (w_register_read_data) + ); + generate if (1) begin : g_register_file_0 + if (1) begin : g_register_0 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[0+:1]), + .o_register_ready (w_register_ready[0+:1]), + .o_register_status (w_register_status[0+:2]), + .o_register_read_data (w_register_read_data[0+:32]), + .o_register_value (w_register_value[0+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'h00), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_register_file_0_register_0_bit_field_0), + .o_value_unmasked () + ); + end + end + if (1) begin : g_register_1 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1+:1]), + .o_register_ready (w_register_ready[1+:1]), + .o_register_status (w_register_status[2+:2]), + .o_register_read_data (w_register_read_data[32+:32]), + .o_register_value (w_register_value[32+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'h00), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_register_file_0_register_1_bit_field_0), + .o_value_unmasked () + ); + end + end + end endgenerate + generate if (1) begin : g_register_file_1 + if (1) begin : g_register_0 + genvar i; + for (i = 0;i < 2;i = i + 1) begin : g + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + wire [15:0] w_indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[0+:8], w_register_value[32+:8]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .INDIRECT_INDEX_WIDTH (16), + .INDIRECT_INDEX_VALUE ({i[0+:8], 8'h00}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1*(2+i)+:1]), + .o_register_ready (w_register_ready[1*(2+i)+:1]), + .o_register_status (w_register_status[2*(2+i)+:2]), + .o_register_read_data (w_register_read_data[32*(2+i)+:32]), + .o_register_value (w_register_value[32*(2+i)+0+:32]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'h00), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_register_file_1_register_0_bit_field_0[8*(i)+:8]), + .o_value_unmasked () + ); + end + end + end + if (1) begin : g_register_1 + genvar i; + for (i = 0;i < 2;i = i + 1) begin : g + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + wire [15:0] w_indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[0+:8], w_register_value[32+:8]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .INDIRECT_INDEX_WIDTH (16), + .INDIRECT_INDEX_VALUE ({i[0+:8], 8'h01}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1*(4+i)+:1]), + .o_register_ready (w_register_ready[1*(4+i)+:1]), + .o_register_status (w_register_status[2*(4+i)+:2]), + .o_register_read_data (w_register_read_data[32*(4+i)+:32]), + .o_register_value (w_register_value[32*(4+i)+0+:32]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'h00), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_register_file_1_register_1_bit_field_0[8*(i)+:8]), + .o_value_unmasked () + ); + end + end + end + end endgenerate + generate if (1) begin : g_register_file_2 + genvar i; + for (i = 0;i < 2;i = i + 1) begin : g + if (1) begin : g_register_file_0 + if (1) begin : g_register_0 + genvar j; + genvar k; + for (j = 0;j < 2;j = j + 1) begin : g + for (k = 0;k < 3;k = k + 1) begin : g + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h00ffffff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h20+32*i+4*(3*j+k)), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1*(6+7*i+3*j+k)+:1]), + .o_register_ready (w_register_ready[1*(6+7*i+3*j+k)+:1]), + .o_register_status (w_register_status[2*(6+7*i+3*j+k)+:2]), + .o_register_read_data (w_register_read_data[32*(6+7*i+3*j+k)+:32]), + .o_register_value (w_register_value[32*(6+7*i+3*j+k)+0+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + genvar l; + for (l = 0;l < 2;l = l + 1) begin : g + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+4*l+:4]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+4*l+:4]), + .i_sw_write_data (w_bit_field_write_data[0+4*l+:4]), + .o_sw_read_data (w_bit_field_read_data[0+4*l+:4]), + .o_sw_value (w_bit_field_value[0+4*l+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_file_2_register_file_0_register_0_bit_field_0[4*(12*i+6*j+2*k+l)+:4]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_1 + genvar l; + for (l = 0;l < 2;l = l + 1) begin : g + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_HIGH) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[8+4*l+:4]), + .i_sw_write_enable (w_register_value[0+:1]), + .i_sw_write_mask (w_bit_field_write_mask[8+4*l+:4]), + .i_sw_write_data (w_bit_field_write_data[8+4*l+:4]), + .o_sw_read_data (w_bit_field_read_data[8+4*l+:4]), + .o_sw_value (w_bit_field_value[8+4*l+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_file_2_register_file_0_register_0_bit_field_1[4*(12*i+6*j+2*k+l)+:4]), + .o_value_unmasked () + ); + end + end + if (1) begin : g_bit_field_2 + genvar l; + for (l = 0;l < 2;l = l + 1) begin : g + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (4'h0), + .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_LOW) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[16+4*l+:4]), + .i_sw_write_enable (w_register_value[32*(6+7*i+6)+0+1*l+:1]), + .i_sw_write_mask (w_bit_field_write_mask[16+4*l+:4]), + .i_sw_write_data (w_bit_field_write_data[16+4*l+:4]), + .o_sw_read_data (w_bit_field_read_data[16+4*l+:4]), + .o_sw_value (w_bit_field_value[16+4*l+:4]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({4{1'b0}}), + .i_hw_set ({4{1'b0}}), + .i_hw_clear ({4{1'b0}}), + .i_value ({4{1'b0}}), + .i_mask ({4{1'b1}}), + .o_value (o_register_file_2_register_file_0_register_0_bit_field_2[4*(12*i+6*j+2*k+l)+:4]), + .o_value_unmasked () + ); + end + end + end + end + end + if (1) begin : g_register_1 + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h00000003, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (7), + .OFFSET_ADDRESS (7'h20+32*i+7'h18), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1*(6+7*i+6)+:1]), + .o_register_ready (w_register_ready[1*(6+7*i+6)+:1]), + .o_register_status (w_register_status[2*(6+7*i+6)+:2]), + .o_register_read_data (w_register_read_data[32*(6+7*i+6)+:32]), + .o_register_value (w_register_value[32*(6+7*i+6)+0+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_bit_field_0 + genvar j; + for (j = 0;j < 2;j = j + 1) begin : g + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+1*j+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+1*j+:1]), + .i_sw_write_data (w_bit_field_write_data[0+1*j+:1]), + .o_sw_read_data (w_bit_field_read_data[0+1*j+:1]), + .o_sw_value (w_bit_field_value[0+1*j+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_register_file_2_register_file_0_register_1_bit_field_0[1*(2*i+j)+:1]), + .o_value_unmasked () + ); + end + end + end + end + end + end endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sample/block_1.vh b/third_party/tests/rggen/rggen-sample/block_1.vh new file mode 100644 index 0000000000..927d9fe029 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.vh @@ -0,0 +1,73 @@ +`ifndef BLOCK_1_VH +`define BLOCK_1_VH +`define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 8 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_MASK 8'hff +`define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BYTE_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BYTE_SIZE 4 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET 7'h00 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_WIDTH 8 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_MASK 8'hff +`define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BYTE_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BYTE_SIZE 4 +`define BLOCK_1_REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET 7'h04 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 8 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_MASK 8'hff +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_SIZE 4 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_ARRAY_DIMENSION 1 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_ARRAY_SIZE_0 2 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_OFFSET_0 7'h10 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_0_BYTE_OFFSET_1 7'h10 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_WIDTH 8 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_MASK 8'hff +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_OFFSET 0 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_SIZE 4 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_ARRAY_DIMENSION 1 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_ARRAY_SIZE_0 2 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_OFFSET_0 7'h10 +`define BLOCK_1_REGISTER_FILE_1_REGISTER_1_BYTE_OFFSET_1 7'h10 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_MASK 4'hf +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET_0 0 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET_1 4 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_MASK 4'hf +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_OFFSET_0 8 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_OFFSET_1 12 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_MASK 4'hf +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_OFFSET_0 16 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_OFFSET_1 20 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_SIZE 48 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_DIMENSION 3 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_SIZE_0 2 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_SIZE_1 2 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_SIZE_2 3 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_0_0 7'h20 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_0_1 7'h24 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_0_2 7'h28 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_1_0 7'h2c +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_1_1 7'h30 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_0_1_2 7'h34 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_0_0 7'h40 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_0_1 7'h44 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_0_2 7'h48 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_1_0 7'h4c +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_1_1 7'h50 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET_1_1_2 7'h54 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_WIDTH 1 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_MASK 1'h1 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET_0 0 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET_1 1 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_WIDTH 4 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_SIZE 8 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_ARRAY_DIMENSION 1 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_ARRAY_SIZE_0 2 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET_0 7'h38 +`define BLOCK_1_REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET_1 7'h58 +`endif diff --git a/third_party/tests/rggen/rggen-sample/block_1.vhd b/third_party/tests/rggen/rggen-sample/block_1.vhd new file mode 100644 index 0000000000..a40e8c7e5d --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.vhd @@ -0,0 +1,645 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.rggen_rtl.all; + +entity block_1 is + generic ( + ADDRESS_WIDTH: positive := 7; + PRE_DECODE: boolean := false; + BASE_ADDRESS: unsigned := x"0"; + ERROR_STATUS: boolean := false; + INSERT_SLICER: boolean := false + ); + port ( + i_clk: in std_logic; + i_rst_n: in std_logic; + i_psel: in std_logic; + i_penable: in std_logic; + i_paddr: in std_logic_vector(ADDRESS_WIDTH-1 downto 0); + i_pprot: in std_logic_vector(2 downto 0); + i_pwrite: in std_logic; + i_pstrb: in std_logic_vector(3 downto 0); + i_pwdata: in std_logic_vector(31 downto 0); + o_pready: out std_logic; + o_prdata: out std_logic_vector(31 downto 0); + o_pslverr: out std_logic; + o_register_file_0_register_0_bit_field_0: out std_logic_vector(7 downto 0); + o_register_file_0_register_1_bit_field_0: out std_logic_vector(7 downto 0); + o_register_file_1_register_0_bit_field_0: out std_logic_vector(15 downto 0); + o_register_file_1_register_1_bit_field_0: out std_logic_vector(15 downto 0); + o_register_file_2_register_file_0_register_0_bit_field_0: out std_logic_vector(95 downto 0); + o_register_file_2_register_file_0_register_0_bit_field_1: out std_logic_vector(95 downto 0); + o_register_file_2_register_file_0_register_0_bit_field_2: out std_logic_vector(95 downto 0); + o_register_file_2_register_file_0_register_1_bit_field_0: out std_logic_vector(3 downto 0) + ); +end block_1; + +architecture rtl of block_1 is + signal register_valid: std_logic; + signal register_access: std_logic_vector(1 downto 0); + signal register_address: std_logic_vector(6 downto 0); + signal register_write_data: std_logic_vector(31 downto 0); + signal register_strobe: std_logic_vector(3 downto 0); + signal register_active: std_logic_vector(19 downto 0); + signal register_ready: std_logic_vector(19 downto 0); + signal register_status: std_logic_vector(39 downto 0); + signal register_read_data: std_logic_vector(639 downto 0); + signal register_value: std_logic_vector(639 downto 0); +begin + u_adapter: entity work.rggen_apb_adaper + generic map ( + ADDRESS_WIDTH => ADDRESS_WIDTH, + LOCAL_ADDRESS_WIDTH => 7, + BUS_WIDTH => 32, + REGISTERS => 20, + PRE_DECODE => PRE_DECODE, + BASE_ADDRESS => BASE_ADDRESS, + BYTE_SIZE => 128, + ERROR_STATUS => ERROR_STATUS, + INSERT_SLICER => INSERT_SLICER + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_psel => i_psel, + i_penable => i_penable, + i_paddr => i_paddr, + i_pprot => i_pprot, + i_pwrite => i_pwrite, + i_pstrb => i_pstrb, + i_pwdata => i_pwdata, + o_pready => o_pready, + o_prdata => o_prdata, + o_pslverr => o_pslverr, + o_register_valid => register_valid, + o_register_access => register_access, + o_register_address => register_address, + o_register_write_data => register_write_data, + o_register_strobe => register_strobe, + i_register_active => register_active, + i_register_ready => register_ready, + i_register_status => register_status, + i_register_read_data => register_read_data + ); + g_register_file_0: block + begin + g_register_0: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 7, + OFFSET_ADDRESS => x"00", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(0), + o_register_ready => register_ready(0), + o_register_status => register_status(1 downto 0), + o_register_read_data => register_read_data(31 downto 0), + o_register_value => register_value(31 downto 0), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"00", 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_0_register_0_bit_field_0, + o_value_unmasked => open + ); + end block; + end block; + g_register_1: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 7, + OFFSET_ADDRESS => x"04", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(1), + o_register_ready => register_ready(1), + o_register_status => register_status(3 downto 2), + o_register_read_data => register_read_data(63 downto 32), + o_register_value => register_value(63 downto 32), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"00", 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_0_register_1_bit_field_0, + o_value_unmasked => open + ); + end block; + end block; + end block; + g_register_file_1: block + begin + g_register_0: block + begin + g: for i in 0 to 1 generate + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + signal indirect_match: std_logic_vector(1 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(7 downto 0)) = i else '0'; + indirect_match(1) <= '1' when unsigned(register_value(39 downto 32)) = 0 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 7, + OFFSET_ADDRESS => x"10", + BUS_WIDTH => 32, + DATA_WIDTH => 32, + INDIRECT_MATCH_WIDTH => 2 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(2+i), + o_register_ready => register_ready(2+i), + o_register_status => register_status(2*(2+i)+1 downto 2*(2+i)), + o_register_read_data => register_read_data(32*(2+i)+31 downto 32*(2+i)), + o_register_value => register_value(32*(2+i)+0+31 downto 32*(2+i)+0), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"00", 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_1_register_0_bit_field_0(8*(i)+7 downto 8*(i)), + o_value_unmasked => open + ); + end block; + end generate; + end block; + g_register_1: block + begin + g: for i in 0 to 1 generate + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + signal indirect_match: std_logic_vector(1 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(7 downto 0)) = i else '0'; + indirect_match(1) <= '1' when unsigned(register_value(39 downto 32)) = 1 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 7, + OFFSET_ADDRESS => x"10", + BUS_WIDTH => 32, + DATA_WIDTH => 32, + INDIRECT_MATCH_WIDTH => 2 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(4+i), + o_register_ready => register_ready(4+i), + o_register_status => register_status(2*(4+i)+1 downto 2*(4+i)), + o_register_read_data => register_read_data(32*(4+i)+31 downto 32*(4+i)), + o_register_value => register_value(32*(4+i)+0+31 downto 32*(4+i)+0), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"00", 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_1_register_1_bit_field_0(8*(i)+7 downto 8*(i)), + o_value_unmasked => open + ); + end block; + end generate; + end block; + end block; + g_register_file_2: block + begin + g: for i in 0 to 1 generate + begin + g_register_file_0: block + begin + g_register_0: block + begin + g: for j in 0 to 1 generate + begin + g: for k in 0 to 2 generate + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"00ffffff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 7, + OFFSET_ADDRESS => x"20"+32*i+4*(3*j+k), + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(6+7*i+3*j+k), + o_register_ready => register_ready(6+7*i+3*j+k), + o_register_status => register_status(2*(6+7*i+3*j+k)+1 downto 2*(6+7*i+3*j+k)), + o_register_read_data => register_read_data(32*(6+7*i+3*j+k)+31 downto 32*(6+7*i+3*j+k)), + o_register_value => register_value(32*(6+7*i+3*j+k)+0+31 downto 32*(6+7*i+3*j+k)+0), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + g: for l in 0 to 1 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0+4*l+3 downto 0+4*l), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0+4*l+3 downto 0+4*l), + i_sw_write_data => bit_field_write_data(0+4*l+3 downto 0+4*l), + o_sw_read_data => bit_field_read_data(0+4*l+3 downto 0+4*l), + o_sw_value => bit_field_value(0+4*l+3 downto 0+4*l), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_2_register_file_0_register_0_bit_field_0(4*(12*i+6*j+2*k+l)+3 downto 4*(12*i+6*j+2*k+l)), + o_value_unmasked => open + ); + end generate; + end block; + g_bit_field_1: block + begin + g: for l in 0 to 1 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_HIGH + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(8+4*l+3 downto 8+4*l), + i_sw_write_enable => register_value(0 downto 0), + i_sw_write_mask => bit_field_write_mask(8+4*l+3 downto 8+4*l), + i_sw_write_data => bit_field_write_data(8+4*l+3 downto 8+4*l), + o_sw_read_data => bit_field_read_data(8+4*l+3 downto 8+4*l), + o_sw_value => bit_field_value(8+4*l+3 downto 8+4*l), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_2_register_file_0_register_0_bit_field_1(4*(12*i+6*j+2*k+l)+3 downto 4*(12*i+6*j+2*k+l)), + o_value_unmasked => open + ); + end generate; + end block; + g_bit_field_2: block + begin + g: for l in 0 to 1 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 4, + INITIAL_VALUE => slice(x"0", 4, 0), + SW_WRITE_ENABLE_POLARITY => RGGEN_ACTIVE_LOW + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(16+4*l+3 downto 16+4*l), + i_sw_write_enable => register_value(32*(6+7*i+6)+0+1*l+0 downto 32*(6+7*i+6)+0+1*l), + i_sw_write_mask => bit_field_write_mask(16+4*l+3 downto 16+4*l), + i_sw_write_data => bit_field_write_data(16+4*l+3 downto 16+4*l), + o_sw_read_data => bit_field_read_data(16+4*l+3 downto 16+4*l), + o_sw_value => bit_field_value(16+4*l+3 downto 16+4*l), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_2_register_file_0_register_0_bit_field_2(4*(12*i+6*j+2*k+l)+3 downto 4*(12*i+6*j+2*k+l)), + o_value_unmasked => open + ); + end generate; + end block; + end generate; + end generate; + end block; + g_register_1: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"00000003", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 7, + OFFSET_ADDRESS => x"20"+32*i+x"18", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(6+7*i+6), + o_register_ready => register_ready(6+7*i+6), + o_register_status => register_status(2*(6+7*i+6)+1 downto 2*(6+7*i+6)), + o_register_read_data => register_read_data(32*(6+7*i+6)+31 downto 32*(6+7*i+6)), + o_register_value => register_value(32*(6+7*i+6)+0+31 downto 32*(6+7*i+6)+0), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_bit_field_0: block + begin + g: for j in 0 to 1 generate + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0+1*j+0 downto 0+1*j), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0+1*j+0 downto 0+1*j), + i_sw_write_data => bit_field_write_data(0+1*j+0 downto 0+1*j), + o_sw_read_data => bit_field_read_data(0+1*j+0 downto 0+1*j), + o_sw_value => bit_field_value(0+1*j+0 downto 0+1*j), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_register_file_2_register_file_0_register_1_bit_field_0(1*(2*i+j)+0 downto 1*(2*i+j)), + o_value_unmasked => open + ); + end generate; + end block; + end block; + end block; + end generate; + end block; +end rtl; diff --git a/third_party/tests/rggen/rggen-sample/block_1.yml b/third_party/tests/rggen/rggen-sample/block_1.yml new file mode 100644 index 0000000000..50486c5dff --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1.yml @@ -0,0 +1,65 @@ +- register_block: + - name: block_1 + byte_size: 128 + comment: | + this is block_1. + this block includes six registers. + + - register_file: + - name: register_file_0 + offset_address: 0x00 + - register: + - name: register_0 + offset_address: 0x00 + comment: | + this is register_0. + bit_field_0 is within this register. + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 8 }, type: rw, initial_value: 0 } + + - register: + - name: register_1 + offset_address: 0x04 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 8 }, type: rw, initial_value: 0 } + + - register_file: + - name: register_file_1 + offset_address: 0x10 + - register: + - name: register_0 + offset_address: 0x00 + size: [2] + type: [indirect, register_file_0.register_0.bit_field_0, [register_file_0.register_1.bit_field_0, 0]] + <<: ®ister_file_1_bit_fiels + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 8 }, type: rw, initial_value: 0 } + + - register: + - name: register_1 + offset_address: 0x00 + size: [2] + type: [indirect, register_file_0.register_0.bit_field_0, [register_file_0.register_1.bit_field_0, 1]] + <<: *register_file_1_bit_fiels + + - register_file: + - name: register_file_2 + offset_address: 0x20 + size: [2, step: 32] + - register_file: + - name: register_file_0 + offset_address: 0x00 + - register: + - name: register_0 + offset_address: 0x00 + size: [2, 3] + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 4, sequence_size: 2 }, type: rw , initial_value: 0 } + - { name: bit_field_1, bit_assignment: { lsb: 8, width: 4, sequence_size: 2 }, type: rwe, initial_value: 0, reference: register_file_0.register_0.bit_field_0 } + - { name: bit_field_2, bit_assignment: { lsb: 16, width: 4, sequence_size: 2 }, type: rwl, initial_value: 0, reference: register_file_2.register_file_0.register_1.bit_field_0 } + + - register: + - name: register_1 + offset_address: 0x18 + bit_fields: + - { name: bit_field_0, bit_assignment: { lsb: 0, width: 1, sequence_size: 2 }, type: rw, initial_value: 0 } diff --git a/third_party/tests/rggen/rggen-sample/block_1_ral_pkg.sv b/third_party/tests/rggen/rggen-sample/block_1_ral_pkg.sv new file mode 100644 index 0000000000..0d34707e00 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1_ral_pkg.sv @@ -0,0 +1,139 @@ +package block_1_ral_pkg; + import uvm_pkg::*; + import rggen_ral_pkg::*; + `include "uvm_macros.svh" + `include "rggen_ral_macros.svh" + class register_file_0_register_0_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, 1, -1, "") + endfunction + endclass + class register_file_0_register_1_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, 1, -1, "") + endfunction + endclass + class register_file_0_reg_file_model extends rggen_ral_reg_file; + rand register_file_0_register_0_reg_model register_0; + rand register_file_0_register_1_reg_model register_1; + function new(string name); + super.new(name, 4, 0); + endfunction + function void build(); + `rggen_ral_create_reg(register_0, '{}, 7'h00, "RW", "g_register_0.u_register") + `rggen_ral_create_reg(register_1, '{}, 7'h04, "RW", "g_register_1.u_register") + endfunction + endclass + class register_file_1_register_0_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field bit_field_0; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, 1, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("register_file_0.register_0.bit_field_0", array_index[0]); + setup_index_field("register_file_0.register_1.bit_field_0", 8'h00); + endfunction + endclass + class register_file_1_register_1_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field bit_field_0; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, 1, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("register_file_0.register_0.bit_field_0", array_index[0]); + setup_index_field("register_file_0.register_1.bit_field_0", 8'h01); + endfunction + endclass + class register_file_1_reg_file_model extends rggen_ral_reg_file; + rand register_file_1_register_0_reg_model register_0[2]; + rand register_file_1_register_1_reg_model register_1[2]; + function new(string name); + super.new(name, 4, 0); + endfunction + function void build(); + `rggen_ral_create_reg(register_0[0], '{0}, 7'h00, "RW", "g_register_0.g[0].u_register") + `rggen_ral_create_reg(register_0[1], '{1}, 7'h00, "RW", "g_register_0.g[1].u_register") + `rggen_ral_create_reg(register_1[0], '{0}, 7'h00, "RW", "g_register_1.g[0].u_register") + `rggen_ral_create_reg(register_1[1], '{1}, 7'h00, "RW", "g_register_1.g[1].u_register") + endfunction + endclass + class register_file_2_register_file_0_register_0_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0[2]; + rand rggen_ral_rwe_field bit_field_1[2]; + rand rggen_ral_rwl_field bit_field_2[2]; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0[0], 0, 4, "RW", 0, 4'h0, 1, 0, "") + `rggen_ral_create_field(bit_field_0[1], 4, 4, "RW", 0, 4'h0, 1, 1, "") + `rggen_ral_create_field(bit_field_1[0], 8, 4, "RWE", 0, 4'h0, 1, 0, "register_file_0.register_0.bit_field_0") + `rggen_ral_create_field(bit_field_1[1], 12, 4, "RWE", 0, 4'h0, 1, 1, "register_file_0.register_0.bit_field_0") + `rggen_ral_create_field(bit_field_2[0], 16, 4, "RWL", 0, 4'h0, 1, 0, "register_file_2.register_file_0.register_1.bit_field_0") + `rggen_ral_create_field(bit_field_2[1], 20, 4, "RWL", 0, 4'h0, 1, 1, "register_file_2.register_file_0.register_1.bit_field_0") + endfunction + endclass + class register_file_2_register_file_0_register_1_reg_model extends rggen_ral_reg; + rand rggen_ral_field bit_field_0[2]; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(bit_field_0[0], 0, 1, "RW", 0, 1'h0, 1, 0, "") + `rggen_ral_create_field(bit_field_0[1], 1, 1, "RW", 0, 1'h0, 1, 1, "") + endfunction + endclass + class register_file_2_register_file_0_reg_file_model extends rggen_ral_reg_file; + rand register_file_2_register_file_0_register_0_reg_model register_0[2][3]; + rand register_file_2_register_file_0_register_1_reg_model register_1; + function new(string name); + super.new(name, 4, 0); + endfunction + function void build(); + `rggen_ral_create_reg(register_0[0][0], '{0, 0}, 7'h00, "RW", "g_register_0.g[0].g[0].u_register") + `rggen_ral_create_reg(register_0[0][1], '{0, 1}, 7'h04, "RW", "g_register_0.g[0].g[1].u_register") + `rggen_ral_create_reg(register_0[0][2], '{0, 2}, 7'h08, "RW", "g_register_0.g[0].g[2].u_register") + `rggen_ral_create_reg(register_0[1][0], '{1, 0}, 7'h0c, "RW", "g_register_0.g[1].g[0].u_register") + `rggen_ral_create_reg(register_0[1][1], '{1, 1}, 7'h10, "RW", "g_register_0.g[1].g[1].u_register") + `rggen_ral_create_reg(register_0[1][2], '{1, 2}, 7'h14, "RW", "g_register_0.g[1].g[2].u_register") + `rggen_ral_create_reg(register_1, '{}, 7'h18, "RW", "g_register_1.u_register") + endfunction + endclass + class register_file_2_reg_file_model extends rggen_ral_reg_file; + rand register_file_2_register_file_0_reg_file_model register_file_0; + function new(string name); + super.new(name, 4, 0); + endfunction + function void build(); + `rggen_ral_create_reg_file(register_file_0, '{}, 7'h00, "g_register_file_0") + endfunction + endclass + class block_1_block_model extends rggen_ral_block; + rand register_file_0_reg_file_model register_file_0; + rand register_file_1_reg_file_model register_file_1; + rand register_file_2_reg_file_model register_file_2[2]; + function new(string name); + super.new(name, 4, 0); + endfunction + function void build(); + `rggen_ral_create_reg_file(register_file_0, '{}, 7'h00, "g_register_file_0") + `rggen_ral_create_reg_file(register_file_1, '{}, 7'h10, "g_register_file_1") + `rggen_ral_create_reg_file(register_file_2[0], '{0}, 7'h20, "g_register_file_2.g[0]") + `rggen_ral_create_reg_file(register_file_2[1], '{1}, 7'h40, "g_register_file_2.g[1]") + endfunction + endclass +endpackage diff --git a/third_party/tests/rggen/rggen-sample/block_1_rtl_pkg.sv b/third_party/tests/rggen/rggen-sample/block_1_rtl_pkg.sv new file mode 100644 index 0000000000..2683c6e758 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/block_1_rtl_pkg.sv @@ -0,0 +1,48 @@ +package block_1_rtl_pkg; + localparam int REGISTER_FILE_0_REGISTER_0_BYTE_WIDTH = 4; + localparam int REGISTER_FILE_0_REGISTER_0_BYTE_SIZE = 4; + localparam bit [6:0] REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET = 7'h00; + localparam int REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH = 8; + localparam bit [7:0] REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_MASK = 8'hff; + localparam int REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_FILE_0_REGISTER_1_BYTE_WIDTH = 4; + localparam int REGISTER_FILE_0_REGISTER_1_BYTE_SIZE = 4; + localparam bit [6:0] REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET = 7'h04; + localparam int REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_WIDTH = 8; + localparam bit [7:0] REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_MASK = 8'hff; + localparam int REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_FILE_1_REGISTER_0_BYTE_WIDTH = 4; + localparam int REGISTER_FILE_1_REGISTER_0_BYTE_SIZE = 4; + localparam int REGISTER_FILE_1_REGISTER_0_ARRAY_SIZE[1] = '{2}; + localparam bit [6:0] REGISTER_FILE_1_REGISTER_0_BYTE_OFFSET[2] = '{7'h10, 7'h10}; + localparam int REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_WIDTH = 8; + localparam bit [7:0] REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_MASK = 8'hff; + localparam int REGISTER_FILE_1_REGISTER_0_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_FILE_1_REGISTER_1_BYTE_WIDTH = 4; + localparam int REGISTER_FILE_1_REGISTER_1_BYTE_SIZE = 4; + localparam int REGISTER_FILE_1_REGISTER_1_ARRAY_SIZE[1] = '{2}; + localparam bit [6:0] REGISTER_FILE_1_REGISTER_1_BYTE_OFFSET[2] = '{7'h10, 7'h10}; + localparam int REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_WIDTH = 8; + localparam bit [7:0] REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_MASK = 8'hff; + localparam int REGISTER_FILE_1_REGISTER_1_BIT_FIELD_0_BIT_OFFSET = 0; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_WIDTH = 4; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_SIZE = 48; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_ARRAY_SIZE[3] = '{2, 2, 3}; + localparam bit [6:0] REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BYTE_OFFSET[2][2][3] = '{'{'{7'h20, 7'h24, 7'h28}, '{7'h2c, 7'h30, 7'h34}}, '{'{7'h40, 7'h44, 7'h48}, '{7'h4c, 7'h50, 7'h54}}}; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_MASK = 4'hf; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_0_BIT_OFFSET[2] = '{0, 4}; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_MASK = 4'hf; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_1_BIT_OFFSET[2] = '{8, 12}; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_WIDTH = 4; + localparam bit [3:0] REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_MASK = 4'hf; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_0_BIT_FIELD_2_BIT_OFFSET[2] = '{16, 20}; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_WIDTH = 4; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_SIZE = 8; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_ARRAY_SIZE[1] = '{2}; + localparam bit [6:0] REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BYTE_OFFSET[2] = '{7'h38, 7'h58}; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_WIDTH = 1; + localparam bit REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_MASK = 1'h1; + localparam int REGISTER_FILE_2_REGISTER_FILE_0_REGISTER_1_BIT_FIELD_0_BIT_OFFSET[2] = '{0, 1}; +endpackage diff --git a/third_party/tests/rggen/rggen-sample/config.json b/third_party/tests/rggen/rggen-sample/config.json new file mode 100644 index 0000000000..586b3deb7f --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/config.json @@ -0,0 +1,5 @@ +{ + "bus_width": 32, + "address_width": 16, + "protocol": "apb" +} diff --git a/third_party/tests/rggen/rggen-sample/config.toml b/third_party/tests/rggen/rggen-sample/config.toml new file mode 100644 index 0000000000..61a339b033 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/config.toml @@ -0,0 +1,3 @@ +bus_width = 32 +address_width = 16 +protocol = 'apb' diff --git a/third_party/tests/rggen/rggen-sample/config.yml b/third_party/tests/rggen/rggen-sample/config.yml new file mode 100644 index 0000000000..4ff0220280 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/config.yml @@ -0,0 +1,3 @@ +bus_width: 32 +address_width: 16 +protocol: apb diff --git a/third_party/tests/rggen/rggen-sample/uart_csr.h b/third_party/tests/rggen/rggen-sample/uart_csr.h new file mode 100644 index 0000000000..e3bc9a16a8 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr.h @@ -0,0 +1,195 @@ +#ifndef UART_CSR_H +#define UART_CSR_H +#include "stdint.h" +#define UART_CSR_RBR_BIT_WIDTH 8 +#define UART_CSR_RBR_BIT_MASK 0xff +#define UART_CSR_RBR_BIT_OFFSET 0 +#define UART_CSR_RBR_BYTE_WIDTH 4 +#define UART_CSR_RBR_BYTE_SIZE 4 +#define UART_CSR_RBR_BYTE_OFFSET 0x0 +#define UART_CSR_THR_BIT_WIDTH 8 +#define UART_CSR_THR_BIT_MASK 0xff +#define UART_CSR_THR_BIT_OFFSET 0 +#define UART_CSR_THR_BYTE_WIDTH 4 +#define UART_CSR_THR_BYTE_SIZE 4 +#define UART_CSR_THR_BYTE_OFFSET 0x0 +#define UART_CSR_IER_ERBFI_BIT_WIDTH 1 +#define UART_CSR_IER_ERBFI_BIT_MASK 0x1 +#define UART_CSR_IER_ERBFI_BIT_OFFSET 0 +#define UART_CSR_IER_ETBEI_BIT_WIDTH 1 +#define UART_CSR_IER_ETBEI_BIT_MASK 0x1 +#define UART_CSR_IER_ETBEI_BIT_OFFSET 1 +#define UART_CSR_IER_ELSI_BIT_WIDTH 1 +#define UART_CSR_IER_ELSI_BIT_MASK 0x1 +#define UART_CSR_IER_ELSI_BIT_OFFSET 2 +#define UART_CSR_IER_EDSSI_BIT_WIDTH 1 +#define UART_CSR_IER_EDSSI_BIT_MASK 0x1 +#define UART_CSR_IER_EDSSI_BIT_OFFSET 3 +#define UART_CSR_IER_BYTE_WIDTH 4 +#define UART_CSR_IER_BYTE_SIZE 4 +#define UART_CSR_IER_BYTE_OFFSET 0x4 +#define UART_CSR_IIR_INTPEND_BIT_WIDTH 1 +#define UART_CSR_IIR_INTPEND_BIT_MASK 0x1 +#define UART_CSR_IIR_INTPEND_BIT_OFFSET 0 +#define UART_CSR_IIR_INTID2_BIT_WIDTH 3 +#define UART_CSR_IIR_INTID2_BIT_MASK 0x7 +#define UART_CSR_IIR_INTID2_BIT_OFFSET 1 +#define UART_CSR_IIR_BYTE_WIDTH 4 +#define UART_CSR_IIR_BYTE_SIZE 4 +#define UART_CSR_IIR_BYTE_OFFSET 0x8 +#define UART_CSR_FCR_FIFOEN_BIT_WIDTH 1 +#define UART_CSR_FCR_FIFOEN_BIT_MASK 0x1 +#define UART_CSR_FCR_FIFOEN_BIT_OFFSET 0 +#define UART_CSR_FCR_RCVR_FIFO_RESET_BIT_WIDTH 1 +#define UART_CSR_FCR_RCVR_FIFO_RESET_BIT_MASK 0x1 +#define UART_CSR_FCR_RCVR_FIFO_RESET_BIT_OFFSET 1 +#define UART_CSR_FCR_XMIT_FIFO_RESET_BIT_WIDTH 1 +#define UART_CSR_FCR_XMIT_FIFO_RESET_BIT_MASK 0x1 +#define UART_CSR_FCR_XMIT_FIFO_RESET_BIT_OFFSET 2 +#define UART_CSR_FCR_DMA_MODE_SELECT_BIT_WIDTH 1 +#define UART_CSR_FCR_DMA_MODE_SELECT_BIT_MASK 0x1 +#define UART_CSR_FCR_DMA_MODE_SELECT_BIT_OFFSET 3 +#define UART_CSR_FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_WIDTH 2 +#define UART_CSR_FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_MASK 0x3 +#define UART_CSR_FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_OFFSET 6 +#define UART_CSR_FCR_BYTE_WIDTH 4 +#define UART_CSR_FCR_BYTE_SIZE 4 +#define UART_CSR_FCR_BYTE_OFFSET 0x8 +#define UART_CSR_LCR_WLS_BIT_WIDTH 2 +#define UART_CSR_LCR_WLS_BIT_MASK 0x3 +#define UART_CSR_LCR_WLS_BIT_OFFSET 0 +#define UART_CSR_LCR_STB_BIT_WIDTH 1 +#define UART_CSR_LCR_STB_BIT_MASK 0x1 +#define UART_CSR_LCR_STB_BIT_OFFSET 2 +#define UART_CSR_LCR_PEN_BIT_WIDTH 1 +#define UART_CSR_LCR_PEN_BIT_MASK 0x1 +#define UART_CSR_LCR_PEN_BIT_OFFSET 3 +#define UART_CSR_LCR_EPS_BIT_WIDTH 1 +#define UART_CSR_LCR_EPS_BIT_MASK 0x1 +#define UART_CSR_LCR_EPS_BIT_OFFSET 4 +#define UART_CSR_LCR_STICK_PARITY_BIT_WIDTH 1 +#define UART_CSR_LCR_STICK_PARITY_BIT_MASK 0x1 +#define UART_CSR_LCR_STICK_PARITY_BIT_OFFSET 5 +#define UART_CSR_LCR_SET_BREAK_BIT_WIDTH 1 +#define UART_CSR_LCR_SET_BREAK_BIT_MASK 0x1 +#define UART_CSR_LCR_SET_BREAK_BIT_OFFSET 6 +#define UART_CSR_LCR_DLAB_BIT_WIDTH 1 +#define UART_CSR_LCR_DLAB_BIT_MASK 0x1 +#define UART_CSR_LCR_DLAB_BIT_OFFSET 7 +#define UART_CSR_LCR_BYTE_WIDTH 4 +#define UART_CSR_LCR_BYTE_SIZE 4 +#define UART_CSR_LCR_BYTE_OFFSET 0xc +#define UART_CSR_MRC_DTR_BIT_WIDTH 1 +#define UART_CSR_MRC_DTR_BIT_MASK 0x1 +#define UART_CSR_MRC_DTR_BIT_OFFSET 0 +#define UART_CSR_MRC_RTS_BIT_WIDTH 1 +#define UART_CSR_MRC_RTS_BIT_MASK 0x1 +#define UART_CSR_MRC_RTS_BIT_OFFSET 1 +#define UART_CSR_MRC_OUT1_BIT_WIDTH 1 +#define UART_CSR_MRC_OUT1_BIT_MASK 0x1 +#define UART_CSR_MRC_OUT1_BIT_OFFSET 2 +#define UART_CSR_MRC_OUT2_BIT_WIDTH 1 +#define UART_CSR_MRC_OUT2_BIT_MASK 0x1 +#define UART_CSR_MRC_OUT2_BIT_OFFSET 3 +#define UART_CSR_MRC_LOOP_BIT_WIDTH 1 +#define UART_CSR_MRC_LOOP_BIT_MASK 0x1 +#define UART_CSR_MRC_LOOP_BIT_OFFSET 4 +#define UART_CSR_MRC_BYTE_WIDTH 4 +#define UART_CSR_MRC_BYTE_SIZE 4 +#define UART_CSR_MRC_BYTE_OFFSET 0x10 +#define UART_CSR_LSR_DR_BIT_WIDTH 1 +#define UART_CSR_LSR_DR_BIT_MASK 0x1 +#define UART_CSR_LSR_DR_BIT_OFFSET 0 +#define UART_CSR_LSR_OE_BIT_WIDTH 1 +#define UART_CSR_LSR_OE_BIT_MASK 0x1 +#define UART_CSR_LSR_OE_BIT_OFFSET 1 +#define UART_CSR_LSR_PE_BIT_WIDTH 1 +#define UART_CSR_LSR_PE_BIT_MASK 0x1 +#define UART_CSR_LSR_PE_BIT_OFFSET 2 +#define UART_CSR_LSR_FE_BIT_WIDTH 1 +#define UART_CSR_LSR_FE_BIT_MASK 0x1 +#define UART_CSR_LSR_FE_BIT_OFFSET 3 +#define UART_CSR_LSR_BI_BIT_WIDTH 1 +#define UART_CSR_LSR_BI_BIT_MASK 0x1 +#define UART_CSR_LSR_BI_BIT_OFFSET 4 +#define UART_CSR_LSR_THRE_BIT_WIDTH 1 +#define UART_CSR_LSR_THRE_BIT_MASK 0x1 +#define UART_CSR_LSR_THRE_BIT_OFFSET 5 +#define UART_CSR_LSR_TEMT_BIT_WIDTH 1 +#define UART_CSR_LSR_TEMT_BIT_MASK 0x1 +#define UART_CSR_LSR_TEMT_BIT_OFFSET 6 +#define UART_CSR_LSR_ERROR_IN_RCVR_FIFO_BIT_WIDTH 1 +#define UART_CSR_LSR_ERROR_IN_RCVR_FIFO_BIT_MASK 0x1 +#define UART_CSR_LSR_ERROR_IN_RCVR_FIFO_BIT_OFFSET 7 +#define UART_CSR_LSR_BYTE_WIDTH 4 +#define UART_CSR_LSR_BYTE_SIZE 4 +#define UART_CSR_LSR_BYTE_OFFSET 0x14 +#define UART_CSR_MSR_DCTS_BIT_WIDTH 1 +#define UART_CSR_MSR_DCTS_BIT_MASK 0x1 +#define UART_CSR_MSR_DCTS_BIT_OFFSET 0 +#define UART_CSR_MSR_DDSR_BIT_WIDTH 1 +#define UART_CSR_MSR_DDSR_BIT_MASK 0x1 +#define UART_CSR_MSR_DDSR_BIT_OFFSET 1 +#define UART_CSR_MSR_TERI_BIT_WIDTH 1 +#define UART_CSR_MSR_TERI_BIT_MASK 0x1 +#define UART_CSR_MSR_TERI_BIT_OFFSET 2 +#define UART_CSR_MSR_DDCD_BIT_WIDTH 1 +#define UART_CSR_MSR_DDCD_BIT_MASK 0x1 +#define UART_CSR_MSR_DDCD_BIT_OFFSET 3 +#define UART_CSR_MSR_CTS_BIT_WIDTH 1 +#define UART_CSR_MSR_CTS_BIT_MASK 0x1 +#define UART_CSR_MSR_CTS_BIT_OFFSET 4 +#define UART_CSR_MSR_DSR_BIT_WIDTH 1 +#define UART_CSR_MSR_DSR_BIT_MASK 0x1 +#define UART_CSR_MSR_DSR_BIT_OFFSET 5 +#define UART_CSR_MSR_RI_BIT_WIDTH 1 +#define UART_CSR_MSR_RI_BIT_MASK 0x1 +#define UART_CSR_MSR_RI_BIT_OFFSET 6 +#define UART_CSR_MSR_DCD_BIT_WIDTH 1 +#define UART_CSR_MSR_DCD_BIT_MASK 0x1 +#define UART_CSR_MSR_DCD_BIT_OFFSET 7 +#define UART_CSR_MSR_BYTE_WIDTH 4 +#define UART_CSR_MSR_BYTE_SIZE 4 +#define UART_CSR_MSR_BYTE_OFFSET 0x18 +#define UART_CSR_SCRATCH_BIT_WIDTH 8 +#define UART_CSR_SCRATCH_BIT_MASK 0xff +#define UART_CSR_SCRATCH_BIT_OFFSET 0 +#define UART_CSR_SCRATCH_BYTE_WIDTH 4 +#define UART_CSR_SCRATCH_BYTE_SIZE 4 +#define UART_CSR_SCRATCH_BYTE_OFFSET 0x1c +#define UART_CSR_DLL_BIT_WIDTH 8 +#define UART_CSR_DLL_BIT_MASK 0xff +#define UART_CSR_DLL_BIT_OFFSET 0 +#define UART_CSR_DLL_BYTE_WIDTH 4 +#define UART_CSR_DLL_BYTE_SIZE 4 +#define UART_CSR_DLL_BYTE_OFFSET 0x0 +#define UART_CSR_DLM_BIT_WIDTH 8 +#define UART_CSR_DLM_BIT_MASK 0xff +#define UART_CSR_DLM_BIT_OFFSET 0 +#define UART_CSR_DLM_BYTE_WIDTH 4 +#define UART_CSR_DLM_BYTE_SIZE 4 +#define UART_CSR_DLM_BYTE_OFFSET 0x4 +typedef union { + uint32_t rbr; + uint32_t thr; + uint32_t dll; +} uart_csr_reg_0x00_t; +typedef union { + uint32_t ier; + uint32_t dlm; +} uart_csr_reg_0x04_t; +typedef union { + uint32_t iir; + uint32_t fcr; +} uart_csr_reg_0x08_t; +typedef struct { + uart_csr_reg_0x00_t reg_0x00; + uart_csr_reg_0x04_t reg_0x04; + uart_csr_reg_0x08_t reg_0x08; + uint32_t lcr; + uint32_t mrc; + uint32_t lsr; + uint32_t msr; + uint32_t scratch; +} uart_csr_t; +#endif diff --git a/third_party/tests/rggen/rggen-sample/uart_csr.md b/third_party/tests/rggen/rggen-sample/uart_csr.md new file mode 100644 index 0000000000..c5a6ea08f8 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr.md @@ -0,0 +1,217 @@ +## uart_csr + +* byte_size + * 32 + +|name|offset_address| +|:--|:--| +|[rbr](#uart_csr-rbr)|0x00| +|[thr](#uart_csr-thr)|0x00| +|[ier](#uart_csr-ier)|0x04| +|[iir](#uart_csr-iir)|0x08| +|[fcr](#uart_csr-fcr)|0x08| +|[lcr](#uart_csr-lcr)|0x0c| +|[mrc](#uart_csr-mrc)|0x10| +|[lsr](#uart_csr-lsr)|0x14| +|[msr](#uart_csr-msr)|0x18| +|[scratch](#uart_csr-scratch)|0x1c| +|[dll](#uart_csr-dll)|0x00| +|[dlm](#uart_csr-dlm)|0x04| + +###
rbr + +* offset_address + * 0x00 +* type + * indirect +* index_bit_fields + * lcr.dlab: 0 +* comment + * Receiver Buffer Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|rbr|[7:0]|rotrg||||| + +###
thr + +* offset_address + * 0x00 +* type + * indirect +* index_bit_fields + * lcr.dlab: 0 +* comment + * Transmitter Holding Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|thr|[7:0]|wotrg|0xff|||| + +###
ier + +* offset_address + * 0x04 +* type + * indirect +* index_bit_fields + * lcr.dlab: 0 +* comment + * Interrupt Enable Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|erbfi|[0]|rw|0x0|||Enable Received Data Available Interrupt
0: Disables Received Data Available Interrupts
1: Enables Received Data Available Interrupts| +|etbei|[1]|rw|0x0|||Enable Transmitter Holding Register Empty Interrupt
0: Disables Transmitter Holding Register Empty Interrupts
1: Enables Transmitter Holding Register Interrupts| +|elsi|[2]|rw|0x0|||Enable Receiver Line Status Interrupt
0: Disables Receiver Line Status Interrupts
1: Enables Receiver Line Status Interrupts| +|edssi|[3]|rw|0x0|||Enable Modem Status Interrupt
0: Disables Modem Status Interrupts
1: Enables Modem Status Interrupts| + +###
iir + +* offset_address + * 0x08 +* type + * default +* comment + * Interrupt Identification Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|intpend|[0]|ro|0x1|||0: Interrupt is pending
1: No interrupt is pending| +|intid2|[3:1]|ro|0x0|||Interrupt ID
011: Receiver Line Status (Highest)
010: Received Data Available (Second)
110: Character Timeout (Second)
001: Transmitter Holding Register Empty (Third)
000: Modem Status (Fourth)| + +###
fcr + +* offset_address + * 0x08 +* type + * default +* comment + * FIFO Control Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|fifoen|[0]|wo|0x0|||FIFO Enable
1: Enables FIFOs| +|rcvr_fifo_reset|[1]|w1trg||||Receiver FIFO Reset
1: Resets RCVR FIFO| +|xmit_fifo_reset|[2]|w1trg||||Transmitter FIFO Reset
1: Resets XMIT FIFO| +|dma_mode_select|[3]|wo|0x0|||DMA Mode Select
0: Mode 0
1: Mode 1| +|rcvr_fifo_trigger_level|[7:6]|wo|0x0|||RCVR FIFO Trigger Level
0b00: 1 byte
0b01: 4 bytes
0b10: 8 bytes
0b11: 14 bytes| + +###
lcr + +* offset_address + * 0x0c +* type + * default +* comment + * line control register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|wls|[1:0]|rw|0x3|||Word Length Select
0b00: 5 bits/character
0b01: 6 bits/character
0b10: 7 bits/character
0b11: 8 bits/character| +|stb|[2]|rw|0x0|||Number of Stop Bits
0: 1 Stop bit
1: 2 Stop bits or 1.5, if 5 bits/character selected| +|pen|[3]|rw|0x0|||Parity Enable
1: Enables parity
0: Disables parity| +|eps|[4]|rw|0x0|||Even Parity Select
1: Selects Even parity
0: Selects Odd parity| +|stick_parity|[5]|rw|0x0|||Stick Parity
1: Stick Parity is enabled
0: Stick Parity is disabled| +|set_break|[6]|rw|0x0|||Set Break
1: Enables break condition
0: Disables break condition| +|dlab|[7]|rw|0x0|||Divisor Latch Access Bit.
1: Allows access to the Divisor Latch Registers and reading of the FIFO Control Register
0: Allows access to RBR, THR, IER and IIR registers| + +###
mrc + +* offset_address + * 0x10 +* type + * default +* comment + * Modem Control Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|dtr|[0]|rw|0x0|||Data Terminal Ready
1: Drives DTRN Low
0: Drives DTRN High| +|rts|[1]|rw|0x0|||Request To Send
1: Drives RTSN Low
0: Drives RTSN High| +|out1|[2]|rw|0x0|||User Output 1
1: Drives OUT1N Low
0: Drives OUT1N High| +|out2|[3]|rw|0x0|||User Output 2
1: Drives OUT1N Low
0: Drives OUT1N High| +|loop|[4]|rw|0x0|||Loop Back
1: Enables loop back| + +###
lsr + +* offset_address + * 0x14 +* type + * default +* comment + * Line Status Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|dr|[0]|ro|0x0|||Data Ready
0: All the data in RBR or FIFO is read
1: Complete incoming character has been received and transferred into the RBR of FIFO| +|oe|[1]|rotrg|0x0|||Overrun Error| +|pe|[2]|rotrg|0x0|||Parity Error| +|fe|[3]|rotrg|0x0|||Framing Error| +|bi|[4]|rotrg|0x0|||Break Interrupt| +|thre|[5]|ro|0x0|||Transmitter Holding Register Empty
0: THR or Transmitter FIFO has data to transmit
1: THR and Transmitter FIFO are empty| +|temt|[6]|ro|0x0|||Transmitter Empty:
0: THR or Transmitter shift register contains data
1: THR, Transmitter FIFO and Transmitter shift register are empty| +|error_in_rcvr_fifo|[7]|ro|0x0|||RCVR FIFO contains at least one receiver error (Parity, Framing, Break condition)| + +###
msr + +* offset_address + * 0x18 +* type + * default +* comment + * Modem Status Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|dcts|[0]|rotrg|0x0|||Delta Clear To Send
Change in CTSN after last MSR read| +|ddsr|[1]|rotrg|0x0|||Delta Data Set Ready
Change in DSRN after last MSR read| +|teri|[2]|ro|0x0|||Trailing Edge Ring Indicator
RIN has changed from a Low to a High| +|ddcd|[3]|rotrg|0x0|||Delta Data Carrier Detect
Change in DCDN after last MSR read| +|cts|[4]|ro||||Clear To Send
Complement of CTSN input| +|dsr|[5]|ro||||Data Set Ready
Complement of DSRN input| +|ri|[6]|ro||||Ring Indicator
Complement of RIN input| +|dcd|[7]|ro||||Data Carrier Detect
Complement of DCDN input| + +###
scratch + +* offset_address + * 0x1c +* type + * default +* comment + * Scratch Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|scratch|[7:0]|rw|0x00|||| + +###
dll + +* offset_address + * 0x00 +* type + * indirect +* index_bit_fields + * lcr.dlab: 1 +* comment + * Divisor Latch (Least Significant Byte) Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|dll|[7:0]|rw|default: 0x00|||| + +###
dlm + +* offset_address + * 0x04 +* type + * indirect +* index_bit_fields + * lcr.dlab: 1 +* comment + * Divisor Latch (Most Significant Byte) Register + +|name|bit_assignments|type|initial_value|reference|labels|comment| +|:--|:--|:--|:--|:--|:--|:--| +|dlm|[7:0]|rw|default: 0x00|||| diff --git a/third_party/tests/rggen/rggen-sample/uart_csr.sv b/third_party/tests/rggen/rggen-sample/uart_csr.sv new file mode 100644 index 0000000000..412681e226 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr.sv @@ -0,0 +1,1467 @@ +`ifndef rggen_connect_bit_field_if + `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \ + assign FIF.valid = RIF.valid; \ + assign FIF.read_mask = RIF.read_mask[LSB+:WIDTH]; \ + assign FIF.write_mask = RIF.write_mask[LSB+:WIDTH]; \ + assign FIF.write_data = RIF.write_data[LSB+:WIDTH]; \ + assign RIF.read_data[LSB+:WIDTH] = FIF.read_data; \ + assign RIF.value[LSB+:WIDTH] = FIF.value; +`endif +`ifndef rggen_tie_off_unused_signals + `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \ + if (1) begin : __g_tie_off \ + genvar __i; \ + for (__i = 0;__i < WIDTH;++__i) begin : g \ + if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \ + assign RIF.read_data[__i] = 1'b0; \ + assign RIF.value[__i] = 1'b0; \ + end \ + end \ + end +`endif +module uart_csr + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 5, + parameter bit PRE_DECODE = 0, + parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, + parameter bit ERROR_STATUS = 0, + parameter bit [31:0] DEFAULT_READ_DATA = '0, + parameter bit INSERT_SLICER = 0, + parameter bit [7:0] DLL_INITIAL_VALUE = 8'h00, + parameter bit [7:0] DLM_INITIAL_VALUE = 8'h00 +)( + input logic i_clk, + input logic i_rst_n, + rggen_apb_if.slave apb_if, + input logic [7:0] i_rbr, + output logic o_rbr_read_trigger, + output logic [7:0] o_thr, + output logic o_thr_write_trigger, + output logic o_ier_erbfi, + output logic o_ier_etbei, + output logic o_ier_elsi, + output logic o_ier_edssi, + input logic i_iir_intpend, + input logic [2:0] i_iir_intid2, + output logic o_fcr_fifoen, + output logic o_fcr_rcvr_fifo_reset_trigger, + output logic o_fcr_xmit_fifo_reset_trigger, + output logic o_fcr_dma_mode_select, + output logic [1:0] o_fcr_rcvr_fifo_trigger_level, + output logic [1:0] o_lcr_wls, + output logic o_lcr_stb, + output logic o_lcr_pen, + output logic o_lcr_eps, + output logic o_lcr_stick_parity, + output logic o_lcr_set_break, + output logic o_lcr_dlab, + output logic o_mrc_dtr, + output logic o_mrc_rts, + output logic o_mrc_out1, + output logic o_mrc_out2, + output logic o_mrc_loop, + input logic i_lsr_dr, + input logic i_lsr_oe, + output logic o_lsr_oe_read_trigger, + input logic i_lsr_pe, + output logic o_lsr_pe_read_trigger, + input logic i_lsr_fe, + output logic o_lsr_fe_read_trigger, + input logic i_lsr_bi, + output logic o_lsr_bi_read_trigger, + input logic i_lsr_thre, + input logic i_lsr_temt, + input logic i_lsr_error_in_rcvr_fifo, + input logic i_msr_dcts, + output logic o_msr_dcts_read_trigger, + input logic i_msr_ddsr, + output logic o_msr_ddsr_read_trigger, + input logic i_msr_teri, + input logic i_msr_ddcd, + output logic o_msr_ddcd_read_trigger, + input logic i_msr_cts, + input logic i_msr_dsr, + input logic i_msr_ri, + input logic i_msr_dcd, + output logic [7:0] o_scratch, + output logic [7:0] o_dll, + output logic [7:0] o_dlm +); + rggen_register_if #(5, 32, 32) register_if[12](); + rggen_apb_adapter #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .LOCAL_ADDRESS_WIDTH (5), + .BUS_WIDTH (32), + .REGISTERS (12), + .PRE_DECODE (PRE_DECODE), + .BASE_ADDRESS (BASE_ADDRESS), + .BYTE_SIZE (32), + .ERROR_STATUS (ERROR_STATUS), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA), + .INSERT_SLICER (INSERT_SLICER) + ) u_adapter ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .apb_if (apb_if), + .register_if (register_if) + ); + generate if (1) begin : g_rbr + rggen_bit_field_if #(32) bit_field_if(); + logic indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + assign indirect_index = {register_if[5].value[7+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[0]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_rbr + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_rbr_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_rbr), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_thr + rggen_bit_field_if #(32) bit_field_if(); + logic indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + assign indirect_index = {register_if[5].value[7+:1]}; + rggen_indirect_register #( + .READABLE (0), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[1]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_thr + localparam bit [7:0] INITIAL_VALUE = 8'hff; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (o_thr_write_trigger), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_thr), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_ier + rggen_bit_field_if #(32) bit_field_if(); + logic indirect_index; + `rggen_tie_off_unused_signals(32, 32'h0000000f, bit_field_if) + assign indirect_index = {register_if[5].value[7+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[2]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_erbfi + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_ier_erbfi), + .o_value_unmasked () + ); + end + if (1) begin : g_etbei + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 1, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_ier_etbei), + .o_value_unmasked () + ); + end + if (1) begin : g_elsi + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_ier_elsi), + .o_value_unmasked () + ); + end + if (1) begin : g_edssi + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 3, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_ier_edssi), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_iir + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h0000000f, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[3]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_intpend + localparam bit INITIAL_VALUE = 1'h1; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_iir_intpend), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_intid2 + localparam bit [2:0] INITIAL_VALUE = 3'h0; + rggen_bit_field_if #(3) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 1, 3) + rggen_bit_field #( + .WIDTH (3), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_iir_intid2), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_fcr + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000000cf, bit_field_if) + rggen_default_register #( + .READABLE (0), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[4]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_fifoen + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_fcr_fifoen), + .o_value_unmasked () + ); + end + if (1) begin : g_rcvr_fifo_reset + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 1, 1) + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .i_value ('0), + .o_trigger (o_fcr_rcvr_fifo_reset_trigger) + ); + end + if (1) begin : g_xmit_fifo_reset + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 1) + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .i_value ('0), + .o_trigger (o_fcr_xmit_fifo_reset_trigger) + ); + end + if (1) begin : g_dma_mode_select + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 3, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_fcr_dma_mode_select), + .o_value_unmasked () + ); + end + if (1) begin : g_rcvr_fifo_trigger_level + localparam bit [1:0] INITIAL_VALUE = 2'h0; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_READ_ACTION (RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_fcr_rcvr_fifo_trigger_level), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_lcr + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h0c), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[5]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_wls + localparam bit [1:0] INITIAL_VALUE = 2'h3; + rggen_bit_field_if #(2) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 2) + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_lcr_wls), + .o_value_unmasked () + ); + end + if (1) begin : g_stb + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_lcr_stb), + .o_value_unmasked () + ); + end + if (1) begin : g_pen + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 3, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_lcr_pen), + .o_value_unmasked () + ); + end + if (1) begin : g_eps + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_lcr_eps), + .o_value_unmasked () + ); + end + if (1) begin : g_stick_parity + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 5, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_lcr_stick_parity), + .o_value_unmasked () + ); + end + if (1) begin : g_set_break + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_lcr_set_break), + .o_value_unmasked () + ); + end + if (1) begin : g_dlab + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 7, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_lcr_dlab), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_mrc + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h0000001f, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[6]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_dtr + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_mrc_dtr), + .o_value_unmasked () + ); + end + if (1) begin : g_rts + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 1, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_mrc_rts), + .o_value_unmasked () + ); + end + if (1) begin : g_out1 + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_mrc_out1), + .o_value_unmasked () + ); + end + if (1) begin : g_out2 + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 3, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_mrc_out2), + .o_value_unmasked () + ); + end + if (1) begin : g_loop + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 1) + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_mrc_loop), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_lsr + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h14), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[7]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_dr + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_dr), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_oe + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 1, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_lsr_oe_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_oe), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_pe + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_lsr_pe_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_pe), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_fe + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 3, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_lsr_fe_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_fe), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bi + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_lsr_bi_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_bi), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_thre + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 5, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_thre), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_temt + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_temt), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_error_in_rcvr_fifo + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 7, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_lsr_error_in_rcvr_fifo), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_msr + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h18), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[8]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_dcts + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_msr_dcts_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_dcts), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_ddsr + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 1, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_msr_ddsr_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_ddsr), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_teri + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 2, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_teri), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_ddcd + localparam bit INITIAL_VALUE = 1'h0; + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 3, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (o_msr_ddcd_read_trigger), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_ddcd), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_cts + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_cts), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_dsr + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 5, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_dsr), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_ri + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_ri), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_dcd + rggen_bit_field_if #(1) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 7, 1) + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value (i_msr_dcd), + .i_mask ('1), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_scratch + rggen_bit_field_if #(32) bit_field_if(); + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h1c), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[9]), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_scratch + localparam bit [7:0] INITIAL_VALUE = 8'h00; + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_scratch), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_dll + rggen_bit_field_if #(32) bit_field_if(); + logic indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + assign indirect_index = {register_if[5].value[7+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h1}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[10]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_dll + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (DLL_INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_dll), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_dlm + rggen_bit_field_if #(32) bit_field_if(); + logic indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) + assign indirect_index = {register_if[5].value[7+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .VALUE_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h1}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .register_if (register_if[11]), + .i_indirect_index (indirect_index), + .bit_field_if (bit_field_if) + ); + if (1) begin : g_dlm + rggen_bit_field_if #(8) bit_field_sub_if(); + `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (DLM_INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_dlm), + .o_value_unmasked () + ); + end + end endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sample/uart_csr.v b/third_party/tests/rggen/rggen-sample/uart_csr.v new file mode 100644 index 0000000000..ca4983f976 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr.v @@ -0,0 +1,1795 @@ +`include "rggen_rtl_macros.vh" +module uart_csr #( + parameter ADDRESS_WIDTH = 5, + parameter PRE_DECODE = 0, + parameter [ADDRESS_WIDTH-1:0] BASE_ADDRESS = 0, + parameter ERROR_STATUS = 0, + parameter [31:0] DEFAULT_READ_DATA = 0, + parameter INSERT_SLICER = 0, + parameter [7:0] DLL_INITIAL_VALUE = 8'h00, + parameter [7:0] DLM_INITIAL_VALUE = 8'h00 +)( + input i_clk, + input i_rst_n, + input i_psel, + input i_penable, + input [ADDRESS_WIDTH-1:0] i_paddr, + input [2:0] i_pprot, + input i_pwrite, + input [3:0] i_pstrb, + input [31:0] i_pwdata, + output o_pready, + output [31:0] o_prdata, + output o_pslverr, + input [7:0] i_rbr, + output o_rbr_read_trigger, + output [7:0] o_thr, + output o_thr_write_trigger, + output o_ier_erbfi, + output o_ier_etbei, + output o_ier_elsi, + output o_ier_edssi, + input i_iir_intpend, + input [2:0] i_iir_intid2, + output o_fcr_fifoen, + output o_fcr_rcvr_fifo_reset_trigger, + output o_fcr_xmit_fifo_reset_trigger, + output o_fcr_dma_mode_select, + output [1:0] o_fcr_rcvr_fifo_trigger_level, + output [1:0] o_lcr_wls, + output o_lcr_stb, + output o_lcr_pen, + output o_lcr_eps, + output o_lcr_stick_parity, + output o_lcr_set_break, + output o_lcr_dlab, + output o_mrc_dtr, + output o_mrc_rts, + output o_mrc_out1, + output o_mrc_out2, + output o_mrc_loop, + input i_lsr_dr, + input i_lsr_oe, + output o_lsr_oe_read_trigger, + input i_lsr_pe, + output o_lsr_pe_read_trigger, + input i_lsr_fe, + output o_lsr_fe_read_trigger, + input i_lsr_bi, + output o_lsr_bi_read_trigger, + input i_lsr_thre, + input i_lsr_temt, + input i_lsr_error_in_rcvr_fifo, + input i_msr_dcts, + output o_msr_dcts_read_trigger, + input i_msr_ddsr, + output o_msr_ddsr_read_trigger, + input i_msr_teri, + input i_msr_ddcd, + output o_msr_ddcd_read_trigger, + input i_msr_cts, + input i_msr_dsr, + input i_msr_ri, + input i_msr_dcd, + output [7:0] o_scratch, + output [7:0] o_dll, + output [7:0] o_dlm +); + wire w_register_valid; + wire [1:0] w_register_access; + wire [4:0] w_register_address; + wire [31:0] w_register_write_data; + wire [3:0] w_register_strobe; + wire [11:0] w_register_active; + wire [11:0] w_register_ready; + wire [23:0] w_register_status; + wire [383:0] w_register_read_data; + wire [383:0] w_register_value; + rggen_apb_adapter #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .LOCAL_ADDRESS_WIDTH (5), + .BUS_WIDTH (32), + .REGISTERS (12), + .PRE_DECODE (PRE_DECODE), + .BASE_ADDRESS (BASE_ADDRESS), + .BYTE_SIZE (32), + .ERROR_STATUS (ERROR_STATUS), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA), + .INSERT_SLICER (INSERT_SLICER) + ) u_adapter ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_psel (i_psel), + .i_penable (i_penable), + .i_paddr (i_paddr), + .i_pprot (i_pprot), + .i_pwrite (i_pwrite), + .i_pstrb (i_pstrb), + .i_pwdata (i_pwdata), + .o_pready (o_pready), + .o_prdata (o_prdata), + .o_pslverr (o_pslverr), + .o_register_valid (w_register_valid), + .o_register_access (w_register_access), + .o_register_address (w_register_address), + .o_register_write_data (w_register_write_data), + .o_register_strobe (w_register_strobe), + .i_register_active (w_register_active), + .i_register_ready (w_register_ready), + .i_register_status (w_register_status), + .i_register_read_data (w_register_read_data) + ); + generate if (1) begin : g_rbr + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + wire w_indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[167+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[0+:1]), + .o_register_ready (w_register_ready[0+:1]), + .o_register_status (w_register_status[0+:2]), + .o_register_read_data (w_register_read_data[0+:32]), + .o_register_value (w_register_value[0+:32]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_rbr + rggen_bit_field #( + .WIDTH (8), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (o_rbr_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value (i_rbr), + .i_mask ({8{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_thr + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + wire w_indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[167+:1]}; + rggen_indirect_register #( + .READABLE (0), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[1+:1]), + .o_register_ready (w_register_ready[1+:1]), + .o_register_status (w_register_status[2+:2]), + .o_register_read_data (w_register_read_data[32+:32]), + .o_register_value (w_register_value[32+:32]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_thr + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'hff), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (o_thr_write_trigger), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_thr), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_ier + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + wire w_indirect_index; + `rggen_tie_off_unused_signals(32, 32'h0000000f, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[167+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h0}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[2+:1]), + .o_register_ready (w_register_ready[2+:1]), + .o_register_status (w_register_status[4+:2]), + .o_register_read_data (w_register_read_data[64+:32]), + .o_register_value (w_register_value[64+:32]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_erbfi + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_ier_erbfi), + .o_value_unmasked () + ); + end + if (1) begin : g_etbei + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[1+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[1+:1]), + .i_sw_write_data (w_bit_field_write_data[1+:1]), + .o_sw_read_data (w_bit_field_read_data[1+:1]), + .o_sw_value (w_bit_field_value[1+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_ier_etbei), + .o_value_unmasked () + ); + end + if (1) begin : g_elsi + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[2+:1]), + .i_sw_write_data (w_bit_field_write_data[2+:1]), + .o_sw_read_data (w_bit_field_read_data[2+:1]), + .o_sw_value (w_bit_field_value[2+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_ier_elsi), + .o_value_unmasked () + ); + end + if (1) begin : g_edssi + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[3+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[3+:1]), + .i_sw_write_data (w_bit_field_write_data[3+:1]), + .o_sw_read_data (w_bit_field_read_data[3+:1]), + .o_sw_value (w_bit_field_value[3+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_ier_edssi), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_iir + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h0000000f, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[3+:1]), + .o_register_ready (w_register_ready[3+:1]), + .o_register_status (w_register_status[6+:2]), + .o_register_read_data (w_register_read_data[96+:32]), + .o_register_value (w_register_value[96+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_intpend + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_iir_intpend), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_intid2 + rggen_bit_field #( + .WIDTH (3), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[1+:3]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[1+:3]), + .i_sw_write_data (w_bit_field_write_data[1+:3]), + .o_sw_read_data (w_bit_field_read_data[1+:3]), + .o_sw_value (w_bit_field_value[1+:3]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({3{1'b0}}), + .i_hw_set ({3{1'b0}}), + .i_hw_clear ({3{1'b0}}), + .i_value (i_iir_intid2), + .i_mask ({3{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_fcr + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000000cf, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (0), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h08), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[4+:1]), + .o_register_ready (w_register_ready[4+:1]), + .o_register_status (w_register_status[8+:2]), + .o_register_read_data (w_register_read_data[128+:32]), + .o_register_value (w_register_value[128+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_fifoen + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_fcr_fifoen), + .o_value_unmasked () + ); + end + if (1) begin : g_rcvr_fifo_reset + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[1+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[1+:1]), + .i_sw_write_data (w_bit_field_write_data[1+:1]), + .o_sw_read_data (w_bit_field_read_data[1+:1]), + .o_sw_value (w_bit_field_value[1+:1]), + .i_value ({1{1'b0}}), + .o_trigger (o_fcr_rcvr_fifo_reset_trigger) + ); + end + if (1) begin : g_xmit_fifo_reset + rggen_bit_field_w01trg #( + .TRIGGER_VALUE (1'b1), + .WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[2+:1]), + .i_sw_write_data (w_bit_field_write_data[2+:1]), + .o_sw_read_data (w_bit_field_read_data[2+:1]), + .o_sw_value (w_bit_field_value[2+:1]), + .i_value ({1{1'b0}}), + .o_trigger (o_fcr_xmit_fifo_reset_trigger) + ); + end + if (1) begin : g_dma_mode_select + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[3+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[3+:1]), + .i_sw_write_data (w_bit_field_write_data[3+:1]), + .o_sw_read_data (w_bit_field_read_data[3+:1]), + .o_sw_value (w_bit_field_value[3+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_fcr_dma_mode_select), + .o_value_unmasked () + ); + end + if (1) begin : g_rcvr_fifo_trigger_level + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h0), + .SW_READ_ACTION (`RGGEN_READ_NONE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[6+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[6+:2]), + .i_sw_write_data (w_bit_field_write_data[6+:2]), + .o_sw_read_data (w_bit_field_read_data[6+:2]), + .o_sw_value (w_bit_field_value[6+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_fcr_rcvr_fifo_trigger_level), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_lcr + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h0c), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[5+:1]), + .o_register_ready (w_register_ready[5+:1]), + .o_register_status (w_register_status[10+:2]), + .o_register_read_data (w_register_read_data[160+:32]), + .o_register_value (w_register_value[160+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_wls + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (2'h3), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:2]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:2]), + .i_sw_write_data (w_bit_field_write_data[0+:2]), + .o_sw_read_data (w_bit_field_read_data[0+:2]), + .o_sw_value (w_bit_field_value[0+:2]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({2{1'b0}}), + .i_hw_set ({2{1'b0}}), + .i_hw_clear ({2{1'b0}}), + .i_value ({2{1'b0}}), + .i_mask ({2{1'b1}}), + .o_value (o_lcr_wls), + .o_value_unmasked () + ); + end + if (1) begin : g_stb + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[2+:1]), + .i_sw_write_data (w_bit_field_write_data[2+:1]), + .o_sw_read_data (w_bit_field_read_data[2+:1]), + .o_sw_value (w_bit_field_value[2+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_lcr_stb), + .o_value_unmasked () + ); + end + if (1) begin : g_pen + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[3+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[3+:1]), + .i_sw_write_data (w_bit_field_write_data[3+:1]), + .o_sw_read_data (w_bit_field_read_data[3+:1]), + .o_sw_value (w_bit_field_value[3+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_lcr_pen), + .o_value_unmasked () + ); + end + if (1) begin : g_eps + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:1]), + .i_sw_write_data (w_bit_field_write_data[4+:1]), + .o_sw_read_data (w_bit_field_read_data[4+:1]), + .o_sw_value (w_bit_field_value[4+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_lcr_eps), + .o_value_unmasked () + ); + end + if (1) begin : g_stick_parity + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[5+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[5+:1]), + .i_sw_write_data (w_bit_field_write_data[5+:1]), + .o_sw_read_data (w_bit_field_read_data[5+:1]), + .o_sw_value (w_bit_field_value[5+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_lcr_stick_parity), + .o_value_unmasked () + ); + end + if (1) begin : g_set_break + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[6+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[6+:1]), + .i_sw_write_data (w_bit_field_write_data[6+:1]), + .o_sw_read_data (w_bit_field_read_data[6+:1]), + .o_sw_value (w_bit_field_value[6+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_lcr_set_break), + .o_value_unmasked () + ); + end + if (1) begin : g_dlab + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[7+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[7+:1]), + .i_sw_write_data (w_bit_field_write_data[7+:1]), + .o_sw_read_data (w_bit_field_read_data[7+:1]), + .o_sw_value (w_bit_field_value[7+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_lcr_dlab), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_mrc + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h0000001f, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h10), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[6+:1]), + .o_register_ready (w_register_ready[6+:1]), + .o_register_status (w_register_status[12+:2]), + .o_register_read_data (w_register_read_data[192+:32]), + .o_register_value (w_register_value[192+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_dtr + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_mrc_dtr), + .o_value_unmasked () + ); + end + if (1) begin : g_rts + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[1+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[1+:1]), + .i_sw_write_data (w_bit_field_write_data[1+:1]), + .o_sw_read_data (w_bit_field_read_data[1+:1]), + .o_sw_value (w_bit_field_value[1+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_mrc_rts), + .o_value_unmasked () + ); + end + if (1) begin : g_out1 + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[2+:1]), + .i_sw_write_data (w_bit_field_write_data[2+:1]), + .o_sw_read_data (w_bit_field_read_data[2+:1]), + .o_sw_value (w_bit_field_value[2+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_mrc_out1), + .o_value_unmasked () + ); + end + if (1) begin : g_out2 + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[3+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[3+:1]), + .i_sw_write_data (w_bit_field_write_data[3+:1]), + .o_sw_read_data (w_bit_field_read_data[3+:1]), + .o_sw_value (w_bit_field_value[3+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_mrc_out2), + .o_value_unmasked () + ); + end + if (1) begin : g_loop + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (1'h0), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:1]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[4+:1]), + .i_sw_write_data (w_bit_field_write_data[4+:1]), + .o_sw_read_data (w_bit_field_read_data[4+:1]), + .o_sw_value (w_bit_field_value[4+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value ({1{1'b0}}), + .i_mask ({1{1'b1}}), + .o_value (o_mrc_loop), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_lsr + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h14), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[7+:1]), + .o_register_ready (w_register_ready[7+:1]), + .o_register_status (w_register_status[14+:2]), + .o_register_read_data (w_register_read_data[224+:32]), + .o_register_value (w_register_value[224+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_dr + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_dr), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_oe + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[1+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[1+:1]), + .i_sw_write_data (w_bit_field_write_data[1+:1]), + .o_sw_read_data (w_bit_field_read_data[1+:1]), + .o_sw_value (w_bit_field_value[1+:1]), + .o_write_trigger (), + .o_read_trigger (o_lsr_oe_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_oe), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_pe + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[2+:1]), + .i_sw_write_data (w_bit_field_write_data[2+:1]), + .o_sw_read_data (w_bit_field_read_data[2+:1]), + .o_sw_value (w_bit_field_value[2+:1]), + .o_write_trigger (), + .o_read_trigger (o_lsr_pe_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_pe), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_fe + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[3+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[3+:1]), + .i_sw_write_data (w_bit_field_write_data[3+:1]), + .o_sw_read_data (w_bit_field_read_data[3+:1]), + .o_sw_value (w_bit_field_value[3+:1]), + .o_write_trigger (), + .o_read_trigger (o_lsr_fe_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_fe), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_bi + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[4+:1]), + .i_sw_write_data (w_bit_field_write_data[4+:1]), + .o_sw_read_data (w_bit_field_read_data[4+:1]), + .o_sw_value (w_bit_field_value[4+:1]), + .o_write_trigger (), + .o_read_trigger (o_lsr_bi_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_bi), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_thre + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[5+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[5+:1]), + .i_sw_write_data (w_bit_field_write_data[5+:1]), + .o_sw_read_data (w_bit_field_read_data[5+:1]), + .o_sw_value (w_bit_field_value[5+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_thre), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_temt + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[6+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[6+:1]), + .i_sw_write_data (w_bit_field_write_data[6+:1]), + .o_sw_read_data (w_bit_field_read_data[6+:1]), + .o_sw_value (w_bit_field_value[6+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_temt), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_error_in_rcvr_fifo + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[7+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[7+:1]), + .i_sw_write_data (w_bit_field_write_data[7+:1]), + .o_sw_read_data (w_bit_field_read_data[7+:1]), + .o_sw_value (w_bit_field_value[7+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_lsr_error_in_rcvr_fifo), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_msr + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (0), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h18), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[8+:1]), + .o_register_ready (w_register_ready[8+:1]), + .o_register_status (w_register_status[16+:2]), + .o_register_read_data (w_register_read_data[256+:32]), + .o_register_value (w_register_value[256+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_dcts + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[0+:1]), + .i_sw_write_data (w_bit_field_write_data[0+:1]), + .o_sw_read_data (w_bit_field_read_data[0+:1]), + .o_sw_value (w_bit_field_value[0+:1]), + .o_write_trigger (), + .o_read_trigger (o_msr_dcts_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_dcts), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_ddsr + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[1+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[1+:1]), + .i_sw_write_data (w_bit_field_write_data[1+:1]), + .o_sw_read_data (w_bit_field_read_data[1+:1]), + .o_sw_value (w_bit_field_value[1+:1]), + .o_write_trigger (), + .o_read_trigger (o_msr_ddsr_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_ddsr), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_teri + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[2+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[2+:1]), + .i_sw_write_data (w_bit_field_write_data[2+:1]), + .o_sw_read_data (w_bit_field_read_data[2+:1]), + .o_sw_value (w_bit_field_value[2+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_teri), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_ddcd + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[3+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[3+:1]), + .i_sw_write_data (w_bit_field_write_data[3+:1]), + .o_sw_read_data (w_bit_field_read_data[3+:1]), + .o_sw_value (w_bit_field_value[3+:1]), + .o_write_trigger (), + .o_read_trigger (o_msr_ddcd_read_trigger), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_ddcd), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_cts + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[4+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[4+:1]), + .i_sw_write_data (w_bit_field_write_data[4+:1]), + .o_sw_read_data (w_bit_field_read_data[4+:1]), + .o_sw_value (w_bit_field_value[4+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_cts), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_dsr + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[5+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[5+:1]), + .i_sw_write_data (w_bit_field_write_data[5+:1]), + .o_sw_read_data (w_bit_field_read_data[5+:1]), + .o_sw_value (w_bit_field_value[5+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_dsr), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_ri + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[6+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[6+:1]), + .i_sw_write_data (w_bit_field_write_data[6+:1]), + .o_sw_read_data (w_bit_field_read_data[6+:1]), + .o_sw_value (w_bit_field_value[6+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_ri), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + if (1) begin : g_dcd + rggen_bit_field #( + .WIDTH (1), + .STORAGE (0), + .EXTERNAL_READ_DATA (1), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[7+:1]), + .i_sw_write_enable (1'b0), + .i_sw_write_mask (w_bit_field_write_mask[7+:1]), + .i_sw_write_data (w_bit_field_write_data[7+:1]), + .o_sw_read_data (w_bit_field_read_data[7+:1]), + .o_sw_value (w_bit_field_value[7+:1]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({1{1'b0}}), + .i_hw_set ({1{1'b0}}), + .i_hw_clear ({1{1'b0}}), + .i_value (i_msr_dcd), + .i_mask ({1{1'b1}}), + .o_value (), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_scratch + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + rggen_default_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h1c), + .BUS_WIDTH (32), + .DATA_WIDTH (32) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[9+:1]), + .o_register_ready (w_register_ready[9+:1]), + .o_register_status (w_register_status[18+:2]), + .o_register_read_data (w_register_read_data[288+:32]), + .o_register_value (w_register_value[288+:32]), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_scratch + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (8'h00), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_scratch), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_dll + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + wire w_indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[167+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h00), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h1}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[10+:1]), + .o_register_ready (w_register_ready[10+:1]), + .o_register_status (w_register_status[20+:2]), + .o_register_read_data (w_register_read_data[320+:32]), + .o_register_value (w_register_value[320+:32]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_dll + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (DLL_INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_dll), + .o_value_unmasked () + ); + end + end endgenerate + generate if (1) begin : g_dlm + wire w_bit_field_valid; + wire [31:0] w_bit_field_read_mask; + wire [31:0] w_bit_field_write_mask; + wire [31:0] w_bit_field_write_data; + wire [31:0] w_bit_field_read_data; + wire [31:0] w_bit_field_value; + wire w_indirect_index; + `rggen_tie_off_unused_signals(32, 32'h000000ff, w_bit_field_read_data, w_bit_field_value) + assign w_indirect_index = {w_register_value[167+:1]}; + rggen_indirect_register #( + .READABLE (1), + .WRITABLE (1), + .ADDRESS_WIDTH (5), + .OFFSET_ADDRESS (5'h04), + .BUS_WIDTH (32), + .DATA_WIDTH (32), + .INDIRECT_INDEX_WIDTH (1), + .INDIRECT_INDEX_VALUE ({1'h1}) + ) u_register ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_register_valid (w_register_valid), + .i_register_access (w_register_access), + .i_register_address (w_register_address), + .i_register_write_data (w_register_write_data), + .i_register_strobe (w_register_strobe), + .o_register_active (w_register_active[11+:1]), + .o_register_ready (w_register_ready[11+:1]), + .o_register_status (w_register_status[22+:2]), + .o_register_read_data (w_register_read_data[352+:32]), + .o_register_value (w_register_value[352+:32]), + .i_indirect_index (w_indirect_index), + .o_bit_field_valid (w_bit_field_valid), + .o_bit_field_read_mask (w_bit_field_read_mask), + .o_bit_field_write_mask (w_bit_field_write_mask), + .o_bit_field_write_data (w_bit_field_write_data), + .i_bit_field_read_data (w_bit_field_read_data), + .i_bit_field_value (w_bit_field_value) + ); + if (1) begin : g_dlm + rggen_bit_field #( + .WIDTH (8), + .INITIAL_VALUE (DLM_INITIAL_VALUE), + .SW_WRITE_ONCE (0), + .TRIGGER (0) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .i_sw_valid (w_bit_field_valid), + .i_sw_read_mask (w_bit_field_read_mask[0+:8]), + .i_sw_write_enable (1'b1), + .i_sw_write_mask (w_bit_field_write_mask[0+:8]), + .i_sw_write_data (w_bit_field_write_data[0+:8]), + .o_sw_read_data (w_bit_field_read_data[0+:8]), + .o_sw_value (w_bit_field_value[0+:8]), + .o_write_trigger (), + .o_read_trigger (), + .i_hw_write_enable (1'b0), + .i_hw_write_data ({8{1'b0}}), + .i_hw_set ({8{1'b0}}), + .i_hw_clear ({8{1'b0}}), + .i_value ({8{1'b0}}), + .i_mask ({8{1'b1}}), + .o_value (o_dlm), + .o_value_unmasked () + ); + end + end endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sample/uart_csr.vh b/third_party/tests/rggen/rggen-sample/uart_csr.vh new file mode 100644 index 0000000000..6e8feca158 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr.vh @@ -0,0 +1,171 @@ +`ifndef UART_CSR_VH +`define UART_CSR_VH +`define UART_CSR_RBR_BIT_WIDTH 8 +`define UART_CSR_RBR_BIT_MASK 8'hff +`define UART_CSR_RBR_BIT_OFFSET 0 +`define UART_CSR_RBR_BYTE_WIDTH 4 +`define UART_CSR_RBR_BYTE_SIZE 4 +`define UART_CSR_RBR_BYTE_OFFSET 5'h00 +`define UART_CSR_THR_BIT_WIDTH 8 +`define UART_CSR_THR_BIT_MASK 8'hff +`define UART_CSR_THR_BIT_OFFSET 0 +`define UART_CSR_THR_BYTE_WIDTH 4 +`define UART_CSR_THR_BYTE_SIZE 4 +`define UART_CSR_THR_BYTE_OFFSET 5'h00 +`define UART_CSR_IER_ERBFI_BIT_WIDTH 1 +`define UART_CSR_IER_ERBFI_BIT_MASK 1'h1 +`define UART_CSR_IER_ERBFI_BIT_OFFSET 0 +`define UART_CSR_IER_ETBEI_BIT_WIDTH 1 +`define UART_CSR_IER_ETBEI_BIT_MASK 1'h1 +`define UART_CSR_IER_ETBEI_BIT_OFFSET 1 +`define UART_CSR_IER_ELSI_BIT_WIDTH 1 +`define UART_CSR_IER_ELSI_BIT_MASK 1'h1 +`define UART_CSR_IER_ELSI_BIT_OFFSET 2 +`define UART_CSR_IER_EDSSI_BIT_WIDTH 1 +`define UART_CSR_IER_EDSSI_BIT_MASK 1'h1 +`define UART_CSR_IER_EDSSI_BIT_OFFSET 3 +`define UART_CSR_IER_BYTE_WIDTH 4 +`define UART_CSR_IER_BYTE_SIZE 4 +`define UART_CSR_IER_BYTE_OFFSET 5'h04 +`define UART_CSR_IIR_INTPEND_BIT_WIDTH 1 +`define UART_CSR_IIR_INTPEND_BIT_MASK 1'h1 +`define UART_CSR_IIR_INTPEND_BIT_OFFSET 0 +`define UART_CSR_IIR_INTID2_BIT_WIDTH 3 +`define UART_CSR_IIR_INTID2_BIT_MASK 3'h7 +`define UART_CSR_IIR_INTID2_BIT_OFFSET 1 +`define UART_CSR_IIR_BYTE_WIDTH 4 +`define UART_CSR_IIR_BYTE_SIZE 4 +`define UART_CSR_IIR_BYTE_OFFSET 5'h08 +`define UART_CSR_FCR_FIFOEN_BIT_WIDTH 1 +`define UART_CSR_FCR_FIFOEN_BIT_MASK 1'h1 +`define UART_CSR_FCR_FIFOEN_BIT_OFFSET 0 +`define UART_CSR_FCR_RCVR_FIFO_RESET_BIT_WIDTH 1 +`define UART_CSR_FCR_RCVR_FIFO_RESET_BIT_MASK 1'h1 +`define UART_CSR_FCR_RCVR_FIFO_RESET_BIT_OFFSET 1 +`define UART_CSR_FCR_XMIT_FIFO_RESET_BIT_WIDTH 1 +`define UART_CSR_FCR_XMIT_FIFO_RESET_BIT_MASK 1'h1 +`define UART_CSR_FCR_XMIT_FIFO_RESET_BIT_OFFSET 2 +`define UART_CSR_FCR_DMA_MODE_SELECT_BIT_WIDTH 1 +`define UART_CSR_FCR_DMA_MODE_SELECT_BIT_MASK 1'h1 +`define UART_CSR_FCR_DMA_MODE_SELECT_BIT_OFFSET 3 +`define UART_CSR_FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_WIDTH 2 +`define UART_CSR_FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_MASK 2'h3 +`define UART_CSR_FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_OFFSET 6 +`define UART_CSR_FCR_BYTE_WIDTH 4 +`define UART_CSR_FCR_BYTE_SIZE 4 +`define UART_CSR_FCR_BYTE_OFFSET 5'h08 +`define UART_CSR_LCR_WLS_BIT_WIDTH 2 +`define UART_CSR_LCR_WLS_BIT_MASK 2'h3 +`define UART_CSR_LCR_WLS_BIT_OFFSET 0 +`define UART_CSR_LCR_STB_BIT_WIDTH 1 +`define UART_CSR_LCR_STB_BIT_MASK 1'h1 +`define UART_CSR_LCR_STB_BIT_OFFSET 2 +`define UART_CSR_LCR_PEN_BIT_WIDTH 1 +`define UART_CSR_LCR_PEN_BIT_MASK 1'h1 +`define UART_CSR_LCR_PEN_BIT_OFFSET 3 +`define UART_CSR_LCR_EPS_BIT_WIDTH 1 +`define UART_CSR_LCR_EPS_BIT_MASK 1'h1 +`define UART_CSR_LCR_EPS_BIT_OFFSET 4 +`define UART_CSR_LCR_STICK_PARITY_BIT_WIDTH 1 +`define UART_CSR_LCR_STICK_PARITY_BIT_MASK 1'h1 +`define UART_CSR_LCR_STICK_PARITY_BIT_OFFSET 5 +`define UART_CSR_LCR_SET_BREAK_BIT_WIDTH 1 +`define UART_CSR_LCR_SET_BREAK_BIT_MASK 1'h1 +`define UART_CSR_LCR_SET_BREAK_BIT_OFFSET 6 +`define UART_CSR_LCR_DLAB_BIT_WIDTH 1 +`define UART_CSR_LCR_DLAB_BIT_MASK 1'h1 +`define UART_CSR_LCR_DLAB_BIT_OFFSET 7 +`define UART_CSR_LCR_BYTE_WIDTH 4 +`define UART_CSR_LCR_BYTE_SIZE 4 +`define UART_CSR_LCR_BYTE_OFFSET 5'h0c +`define UART_CSR_MRC_DTR_BIT_WIDTH 1 +`define UART_CSR_MRC_DTR_BIT_MASK 1'h1 +`define UART_CSR_MRC_DTR_BIT_OFFSET 0 +`define UART_CSR_MRC_RTS_BIT_WIDTH 1 +`define UART_CSR_MRC_RTS_BIT_MASK 1'h1 +`define UART_CSR_MRC_RTS_BIT_OFFSET 1 +`define UART_CSR_MRC_OUT1_BIT_WIDTH 1 +`define UART_CSR_MRC_OUT1_BIT_MASK 1'h1 +`define UART_CSR_MRC_OUT1_BIT_OFFSET 2 +`define UART_CSR_MRC_OUT2_BIT_WIDTH 1 +`define UART_CSR_MRC_OUT2_BIT_MASK 1'h1 +`define UART_CSR_MRC_OUT2_BIT_OFFSET 3 +`define UART_CSR_MRC_LOOP_BIT_WIDTH 1 +`define UART_CSR_MRC_LOOP_BIT_MASK 1'h1 +`define UART_CSR_MRC_LOOP_BIT_OFFSET 4 +`define UART_CSR_MRC_BYTE_WIDTH 4 +`define UART_CSR_MRC_BYTE_SIZE 4 +`define UART_CSR_MRC_BYTE_OFFSET 5'h10 +`define UART_CSR_LSR_DR_BIT_WIDTH 1 +`define UART_CSR_LSR_DR_BIT_MASK 1'h1 +`define UART_CSR_LSR_DR_BIT_OFFSET 0 +`define UART_CSR_LSR_OE_BIT_WIDTH 1 +`define UART_CSR_LSR_OE_BIT_MASK 1'h1 +`define UART_CSR_LSR_OE_BIT_OFFSET 1 +`define UART_CSR_LSR_PE_BIT_WIDTH 1 +`define UART_CSR_LSR_PE_BIT_MASK 1'h1 +`define UART_CSR_LSR_PE_BIT_OFFSET 2 +`define UART_CSR_LSR_FE_BIT_WIDTH 1 +`define UART_CSR_LSR_FE_BIT_MASK 1'h1 +`define UART_CSR_LSR_FE_BIT_OFFSET 3 +`define UART_CSR_LSR_BI_BIT_WIDTH 1 +`define UART_CSR_LSR_BI_BIT_MASK 1'h1 +`define UART_CSR_LSR_BI_BIT_OFFSET 4 +`define UART_CSR_LSR_THRE_BIT_WIDTH 1 +`define UART_CSR_LSR_THRE_BIT_MASK 1'h1 +`define UART_CSR_LSR_THRE_BIT_OFFSET 5 +`define UART_CSR_LSR_TEMT_BIT_WIDTH 1 +`define UART_CSR_LSR_TEMT_BIT_MASK 1'h1 +`define UART_CSR_LSR_TEMT_BIT_OFFSET 6 +`define UART_CSR_LSR_ERROR_IN_RCVR_FIFO_BIT_WIDTH 1 +`define UART_CSR_LSR_ERROR_IN_RCVR_FIFO_BIT_MASK 1'h1 +`define UART_CSR_LSR_ERROR_IN_RCVR_FIFO_BIT_OFFSET 7 +`define UART_CSR_LSR_BYTE_WIDTH 4 +`define UART_CSR_LSR_BYTE_SIZE 4 +`define UART_CSR_LSR_BYTE_OFFSET 5'h14 +`define UART_CSR_MSR_DCTS_BIT_WIDTH 1 +`define UART_CSR_MSR_DCTS_BIT_MASK 1'h1 +`define UART_CSR_MSR_DCTS_BIT_OFFSET 0 +`define UART_CSR_MSR_DDSR_BIT_WIDTH 1 +`define UART_CSR_MSR_DDSR_BIT_MASK 1'h1 +`define UART_CSR_MSR_DDSR_BIT_OFFSET 1 +`define UART_CSR_MSR_TERI_BIT_WIDTH 1 +`define UART_CSR_MSR_TERI_BIT_MASK 1'h1 +`define UART_CSR_MSR_TERI_BIT_OFFSET 2 +`define UART_CSR_MSR_DDCD_BIT_WIDTH 1 +`define UART_CSR_MSR_DDCD_BIT_MASK 1'h1 +`define UART_CSR_MSR_DDCD_BIT_OFFSET 3 +`define UART_CSR_MSR_CTS_BIT_WIDTH 1 +`define UART_CSR_MSR_CTS_BIT_MASK 1'h1 +`define UART_CSR_MSR_CTS_BIT_OFFSET 4 +`define UART_CSR_MSR_DSR_BIT_WIDTH 1 +`define UART_CSR_MSR_DSR_BIT_MASK 1'h1 +`define UART_CSR_MSR_DSR_BIT_OFFSET 5 +`define UART_CSR_MSR_RI_BIT_WIDTH 1 +`define UART_CSR_MSR_RI_BIT_MASK 1'h1 +`define UART_CSR_MSR_RI_BIT_OFFSET 6 +`define UART_CSR_MSR_DCD_BIT_WIDTH 1 +`define UART_CSR_MSR_DCD_BIT_MASK 1'h1 +`define UART_CSR_MSR_DCD_BIT_OFFSET 7 +`define UART_CSR_MSR_BYTE_WIDTH 4 +`define UART_CSR_MSR_BYTE_SIZE 4 +`define UART_CSR_MSR_BYTE_OFFSET 5'h18 +`define UART_CSR_SCRATCH_BIT_WIDTH 8 +`define UART_CSR_SCRATCH_BIT_MASK 8'hff +`define UART_CSR_SCRATCH_BIT_OFFSET 0 +`define UART_CSR_SCRATCH_BYTE_WIDTH 4 +`define UART_CSR_SCRATCH_BYTE_SIZE 4 +`define UART_CSR_SCRATCH_BYTE_OFFSET 5'h1c +`define UART_CSR_DLL_BIT_WIDTH 8 +`define UART_CSR_DLL_BIT_MASK 8'hff +`define UART_CSR_DLL_BIT_OFFSET 0 +`define UART_CSR_DLL_BYTE_WIDTH 4 +`define UART_CSR_DLL_BYTE_SIZE 4 +`define UART_CSR_DLL_BYTE_OFFSET 5'h00 +`define UART_CSR_DLM_BIT_WIDTH 8 +`define UART_CSR_DLM_BIT_MASK 8'hff +`define UART_CSR_DLM_BIT_OFFSET 0 +`define UART_CSR_DLM_BYTE_WIDTH 4 +`define UART_CSR_DLM_BYTE_SIZE 4 +`define UART_CSR_DLM_BYTE_OFFSET 5'h04 +`endif diff --git a/third_party/tests/rggen/rggen-sample/uart_csr.vhd b/third_party/tests/rggen/rggen-sample/uart_csr.vhd new file mode 100644 index 0000000000..2f5357ed00 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr.vhd @@ -0,0 +1,2029 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.rggen_rtl.all; + +entity uart_csr is + generic ( + ADDRESS_WIDTH: positive := 5; + PRE_DECODE: boolean := false; + BASE_ADDRESS: unsigned := x"0"; + ERROR_STATUS: boolean := false; + INSERT_SLICER: boolean := false; + DLL_INITIAL_VALUE: unsigned(7 downto 0) := repeat(x"00", 8, 1); + DLM_INITIAL_VALUE: unsigned(7 downto 0) := repeat(x"00", 8, 1) + ); + port ( + i_clk: in std_logic; + i_rst_n: in std_logic; + i_psel: in std_logic; + i_penable: in std_logic; + i_paddr: in std_logic_vector(ADDRESS_WIDTH-1 downto 0); + i_pprot: in std_logic_vector(2 downto 0); + i_pwrite: in std_logic; + i_pstrb: in std_logic_vector(3 downto 0); + i_pwdata: in std_logic_vector(31 downto 0); + o_pready: out std_logic; + o_prdata: out std_logic_vector(31 downto 0); + o_pslverr: out std_logic; + i_rbr: in std_logic_vector(7 downto 0); + o_rbr_read_trigger: out std_logic_vector(0 downto 0); + o_thr: out std_logic_vector(7 downto 0); + o_thr_write_trigger: out std_logic_vector(0 downto 0); + o_ier_erbfi: out std_logic_vector(0 downto 0); + o_ier_etbei: out std_logic_vector(0 downto 0); + o_ier_elsi: out std_logic_vector(0 downto 0); + o_ier_edssi: out std_logic_vector(0 downto 0); + i_iir_intpend: in std_logic_vector(0 downto 0); + i_iir_intid2: in std_logic_vector(2 downto 0); + o_fcr_fifoen: out std_logic_vector(0 downto 0); + o_fcr_rcvr_fifo_reset_trigger: out std_logic_vector(0 downto 0); + o_fcr_xmit_fifo_reset_trigger: out std_logic_vector(0 downto 0); + o_fcr_dma_mode_select: out std_logic_vector(0 downto 0); + o_fcr_rcvr_fifo_trigger_level: out std_logic_vector(1 downto 0); + o_lcr_wls: out std_logic_vector(1 downto 0); + o_lcr_stb: out std_logic_vector(0 downto 0); + o_lcr_pen: out std_logic_vector(0 downto 0); + o_lcr_eps: out std_logic_vector(0 downto 0); + o_lcr_stick_parity: out std_logic_vector(0 downto 0); + o_lcr_set_break: out std_logic_vector(0 downto 0); + o_lcr_dlab: out std_logic_vector(0 downto 0); + o_mrc_dtr: out std_logic_vector(0 downto 0); + o_mrc_rts: out std_logic_vector(0 downto 0); + o_mrc_out1: out std_logic_vector(0 downto 0); + o_mrc_out2: out std_logic_vector(0 downto 0); + o_mrc_loop: out std_logic_vector(0 downto 0); + i_lsr_dr: in std_logic_vector(0 downto 0); + i_lsr_oe: in std_logic_vector(0 downto 0); + o_lsr_oe_read_trigger: out std_logic_vector(0 downto 0); + i_lsr_pe: in std_logic_vector(0 downto 0); + o_lsr_pe_read_trigger: out std_logic_vector(0 downto 0); + i_lsr_fe: in std_logic_vector(0 downto 0); + o_lsr_fe_read_trigger: out std_logic_vector(0 downto 0); + i_lsr_bi: in std_logic_vector(0 downto 0); + o_lsr_bi_read_trigger: out std_logic_vector(0 downto 0); + i_lsr_thre: in std_logic_vector(0 downto 0); + i_lsr_temt: in std_logic_vector(0 downto 0); + i_lsr_error_in_rcvr_fifo: in std_logic_vector(0 downto 0); + i_msr_dcts: in std_logic_vector(0 downto 0); + o_msr_dcts_read_trigger: out std_logic_vector(0 downto 0); + i_msr_ddsr: in std_logic_vector(0 downto 0); + o_msr_ddsr_read_trigger: out std_logic_vector(0 downto 0); + i_msr_teri: in std_logic_vector(0 downto 0); + i_msr_ddcd: in std_logic_vector(0 downto 0); + o_msr_ddcd_read_trigger: out std_logic_vector(0 downto 0); + i_msr_cts: in std_logic_vector(0 downto 0); + i_msr_dsr: in std_logic_vector(0 downto 0); + i_msr_ri: in std_logic_vector(0 downto 0); + i_msr_dcd: in std_logic_vector(0 downto 0); + o_scratch: out std_logic_vector(7 downto 0); + o_dll: out std_logic_vector(7 downto 0); + o_dlm: out std_logic_vector(7 downto 0) + ); +end uart_csr; + +architecture rtl of uart_csr is + signal register_valid: std_logic; + signal register_access: std_logic_vector(1 downto 0); + signal register_address: std_logic_vector(4 downto 0); + signal register_write_data: std_logic_vector(31 downto 0); + signal register_strobe: std_logic_vector(3 downto 0); + signal register_active: std_logic_vector(11 downto 0); + signal register_ready: std_logic_vector(11 downto 0); + signal register_status: std_logic_vector(23 downto 0); + signal register_read_data: std_logic_vector(383 downto 0); + signal register_value: std_logic_vector(383 downto 0); +begin + u_adapter: entity work.rggen_apb_adaper + generic map ( + ADDRESS_WIDTH => ADDRESS_WIDTH, + LOCAL_ADDRESS_WIDTH => 5, + BUS_WIDTH => 32, + REGISTERS => 12, + PRE_DECODE => PRE_DECODE, + BASE_ADDRESS => BASE_ADDRESS, + BYTE_SIZE => 32, + ERROR_STATUS => ERROR_STATUS, + INSERT_SLICER => INSERT_SLICER + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_psel => i_psel, + i_penable => i_penable, + i_paddr => i_paddr, + i_pprot => i_pprot, + i_pwrite => i_pwrite, + i_pstrb => i_pstrb, + i_pwdata => i_pwdata, + o_pready => o_pready, + o_prdata => o_prdata, + o_pslverr => o_pslverr, + o_register_valid => register_valid, + o_register_access => register_access, + o_register_address => register_address, + o_register_write_data => register_write_data, + o_register_strobe => register_strobe, + i_register_active => register_active, + i_register_ready => register_ready, + i_register_status => register_status, + i_register_read_data => register_read_data + ); + g_rbr: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + signal indirect_match: std_logic_vector(0 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(167 downto 167)) = 0 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => false, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"00", + BUS_WIDTH => 32, + DATA_WIDTH => 32, + INDIRECT_MATCH_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(0), + o_register_ready => register_ready(0), + o_register_status => register_status(1 downto 0), + o_register_read_data => register_read_data(31 downto 0), + o_register_value => register_value(31 downto 0), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_rbr: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => o_rbr_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_rbr, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + end block; + g_thr: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + signal indirect_match: std_logic_vector(0 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(167 downto 167)) = 0 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => false, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"00", + BUS_WIDTH => 32, + DATA_WIDTH => 32, + INDIRECT_MATCH_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(1), + o_register_ready => register_ready(1), + o_register_status => register_status(3 downto 2), + o_register_read_data => register_read_data(63 downto 32), + o_register_value => register_value(63 downto 32), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_thr: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"ff", 8, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ONCE => false, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => o_thr_write_trigger, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_thr, + o_value_unmasked => open + ); + end block; + end block; + g_ier: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + signal indirect_match: std_logic_vector(0 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"0000000f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(167 downto 167)) = 0 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"04", + BUS_WIDTH => 32, + DATA_WIDTH => 32, + INDIRECT_MATCH_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(2), + o_register_ready => register_ready(2), + o_register_status => register_status(5 downto 4), + o_register_read_data => register_read_data(95 downto 64), + o_register_value => register_value(95 downto 64), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_erbfi: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_ier_erbfi, + o_value_unmasked => open + ); + end block; + g_etbei: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 1), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(1 downto 1), + i_sw_write_data => bit_field_write_data(1 downto 1), + o_sw_read_data => bit_field_read_data(1 downto 1), + o_sw_value => bit_field_value(1 downto 1), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_ier_etbei, + o_value_unmasked => open + ); + end block; + g_elsi: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(2 downto 2), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(2 downto 2), + i_sw_write_data => bit_field_write_data(2 downto 2), + o_sw_read_data => bit_field_read_data(2 downto 2), + o_sw_value => bit_field_value(2 downto 2), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_ier_elsi, + o_value_unmasked => open + ); + end block; + g_edssi: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 3), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 3), + i_sw_write_data => bit_field_write_data(3 downto 3), + o_sw_read_data => bit_field_read_data(3 downto 3), + o_sw_value => bit_field_value(3 downto 3), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_ier_edssi, + o_value_unmasked => open + ); + end block; + end block; + g_iir: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"0000000f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => false, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"08", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(3), + o_register_ready => register_ready(3), + o_register_status => register_status(7 downto 6), + o_register_read_data => register_read_data(127 downto 96), + o_register_value => register_value(127 downto 96), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_intpend: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_iir_intpend, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_intid2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 3, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 1), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(3 downto 1), + i_sw_write_data => bit_field_write_data(3 downto 1), + o_sw_read_data => bit_field_read_data(3 downto 1), + o_sw_value => bit_field_value(3 downto 1), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_iir_intid2, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + end block; + g_fcr: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000cf", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => false, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"08", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(4), + o_register_ready => register_ready(4), + o_register_status => register_status(9 downto 8), + o_register_read_data => register_read_data(159 downto 128), + o_register_value => register_value(159 downto 128), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_fifoen: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_fcr_fifoen, + o_value_unmasked => open + ); + end block; + g_rcvr_fifo_reset: block + begin + u_bit_field: entity work.rggen_bit_field_w01trg + generic map ( + WRITE_ONE_TRIGGER => true, + WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 1), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(1 downto 1), + i_sw_write_data => bit_field_write_data(1 downto 1), + o_sw_read_data => bit_field_read_data(1 downto 1), + o_sw_value => bit_field_value(1 downto 1), + i_value => (others => '0'), + o_trigger => o_fcr_rcvr_fifo_reset_trigger + ); + end block; + g_xmit_fifo_reset: block + begin + u_bit_field: entity work.rggen_bit_field_w01trg + generic map ( + WRITE_ONE_TRIGGER => true, + WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(2 downto 2), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(2 downto 2), + i_sw_write_data => bit_field_write_data(2 downto 2), + o_sw_read_data => bit_field_read_data(2 downto 2), + o_sw_value => bit_field_value(2 downto 2), + i_value => (others => '0'), + o_trigger => o_fcr_xmit_fifo_reset_trigger + ); + end block; + g_dma_mode_select: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 3), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 3), + i_sw_write_data => bit_field_write_data(3 downto 3), + o_sw_read_data => bit_field_read_data(3 downto 3), + o_sw_value => bit_field_value(3 downto 3), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_fcr_dma_mode_select, + o_value_unmasked => open + ); + end block; + g_rcvr_fifo_trigger_level: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"0", 2, 0), + SW_READ_ACTION => RGGEN_READ_NONE, + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 6), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 6), + i_sw_write_data => bit_field_write_data(7 downto 6), + o_sw_read_data => bit_field_read_data(7 downto 6), + o_sw_value => bit_field_value(7 downto 6), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_fcr_rcvr_fifo_trigger_level, + o_value_unmasked => open + ); + end block; + end block; + g_lcr: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"0c", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(5), + o_register_ready => register_ready(5), + o_register_status => register_status(11 downto 10), + o_register_read_data => register_read_data(191 downto 160), + o_register_value => register_value(191 downto 160), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_wls: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 2, + INITIAL_VALUE => slice(x"3", 2, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(1 downto 0), + i_sw_write_data => bit_field_write_data(1 downto 0), + o_sw_read_data => bit_field_read_data(1 downto 0), + o_sw_value => bit_field_value(1 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_lcr_wls, + o_value_unmasked => open + ); + end block; + g_stb: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(2 downto 2), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(2 downto 2), + i_sw_write_data => bit_field_write_data(2 downto 2), + o_sw_read_data => bit_field_read_data(2 downto 2), + o_sw_value => bit_field_value(2 downto 2), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_lcr_stb, + o_value_unmasked => open + ); + end block; + g_pen: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 3), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 3), + i_sw_write_data => bit_field_write_data(3 downto 3), + o_sw_read_data => bit_field_read_data(3 downto 3), + o_sw_value => bit_field_value(3 downto 3), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_lcr_pen, + o_value_unmasked => open + ); + end block; + g_eps: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(4 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(4 downto 4), + i_sw_write_data => bit_field_write_data(4 downto 4), + o_sw_read_data => bit_field_read_data(4 downto 4), + o_sw_value => bit_field_value(4 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_lcr_eps, + o_value_unmasked => open + ); + end block; + g_stick_parity: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(5 downto 5), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(5 downto 5), + i_sw_write_data => bit_field_write_data(5 downto 5), + o_sw_read_data => bit_field_read_data(5 downto 5), + o_sw_value => bit_field_value(5 downto 5), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_lcr_stick_parity, + o_value_unmasked => open + ); + end block; + g_set_break: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(6 downto 6), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(6 downto 6), + i_sw_write_data => bit_field_write_data(6 downto 6), + o_sw_read_data => bit_field_read_data(6 downto 6), + o_sw_value => bit_field_value(6 downto 6), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_lcr_set_break, + o_value_unmasked => open + ); + end block; + g_dlab: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 7), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 7), + i_sw_write_data => bit_field_write_data(7 downto 7), + o_sw_read_data => bit_field_read_data(7 downto 7), + o_sw_value => bit_field_value(7 downto 7), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_lcr_dlab, + o_value_unmasked => open + ); + end block; + end block; + g_mrc: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"0000001f", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"10", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(6), + o_register_ready => register_ready(6), + o_register_status => register_status(13 downto 12), + o_register_read_data => register_read_data(223 downto 192), + o_register_value => register_value(223 downto 192), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_dtr: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_mrc_dtr, + o_value_unmasked => open + ); + end block; + g_rts: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 1), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(1 downto 1), + i_sw_write_data => bit_field_write_data(1 downto 1), + o_sw_read_data => bit_field_read_data(1 downto 1), + o_sw_value => bit_field_value(1 downto 1), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_mrc_rts, + o_value_unmasked => open + ); + end block; + g_out1: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(2 downto 2), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(2 downto 2), + i_sw_write_data => bit_field_write_data(2 downto 2), + o_sw_read_data => bit_field_read_data(2 downto 2), + o_sw_value => bit_field_value(2 downto 2), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_mrc_out1, + o_value_unmasked => open + ); + end block; + g_out2: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 3), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(3 downto 3), + i_sw_write_data => bit_field_write_data(3 downto 3), + o_sw_read_data => bit_field_read_data(3 downto 3), + o_sw_value => bit_field_value(3 downto 3), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_mrc_out2, + o_value_unmasked => open + ); + end block; + g_loop: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + INITIAL_VALUE => slice(x"0", 1, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(4 downto 4), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(4 downto 4), + i_sw_write_data => bit_field_write_data(4 downto 4), + o_sw_read_data => bit_field_read_data(4 downto 4), + o_sw_value => bit_field_value(4 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_mrc_loop, + o_value_unmasked => open + ); + end block; + end block; + g_lsr: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => false, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"14", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(7), + o_register_ready => register_ready(7), + o_register_status => register_status(15 downto 14), + o_register_read_data => register_read_data(255 downto 224), + o_register_value => register_value(255 downto 224), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_dr: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_dr, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_oe: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 1), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(1 downto 1), + i_sw_write_data => bit_field_write_data(1 downto 1), + o_sw_read_data => bit_field_read_data(1 downto 1), + o_sw_value => bit_field_value(1 downto 1), + o_write_trigger => open, + o_read_trigger => o_lsr_oe_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_oe, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_pe: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(2 downto 2), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(2 downto 2), + i_sw_write_data => bit_field_write_data(2 downto 2), + o_sw_read_data => bit_field_read_data(2 downto 2), + o_sw_value => bit_field_value(2 downto 2), + o_write_trigger => open, + o_read_trigger => o_lsr_pe_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_pe, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_fe: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 3), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(3 downto 3), + i_sw_write_data => bit_field_write_data(3 downto 3), + o_sw_read_data => bit_field_read_data(3 downto 3), + o_sw_value => bit_field_value(3 downto 3), + o_write_trigger => open, + o_read_trigger => o_lsr_fe_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_fe, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_bi: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(4 downto 4), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(4 downto 4), + i_sw_write_data => bit_field_write_data(4 downto 4), + o_sw_read_data => bit_field_read_data(4 downto 4), + o_sw_value => bit_field_value(4 downto 4), + o_write_trigger => open, + o_read_trigger => o_lsr_bi_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_bi, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_thre: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(5 downto 5), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(5 downto 5), + i_sw_write_data => bit_field_write_data(5 downto 5), + o_sw_read_data => bit_field_read_data(5 downto 5), + o_sw_value => bit_field_value(5 downto 5), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_thre, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_temt: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(6 downto 6), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(6 downto 6), + i_sw_write_data => bit_field_write_data(6 downto 6), + o_sw_read_data => bit_field_read_data(6 downto 6), + o_sw_value => bit_field_value(6 downto 6), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_temt, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_error_in_rcvr_fifo: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 7), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(7 downto 7), + i_sw_write_data => bit_field_write_data(7 downto 7), + o_sw_read_data => bit_field_read_data(7 downto 7), + o_sw_value => bit_field_value(7 downto 7), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_lsr_error_in_rcvr_fifo, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + end block; + g_msr: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => false, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"18", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(8), + o_register_ready => register_ready(8), + o_register_status => register_status(17 downto 16), + o_register_read_data => register_read_data(287 downto 256), + o_register_value => register_value(287 downto 256), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_dcts: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(0 downto 0), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(0 downto 0), + i_sw_write_data => bit_field_write_data(0 downto 0), + o_sw_read_data => bit_field_read_data(0 downto 0), + o_sw_value => bit_field_value(0 downto 0), + o_write_trigger => open, + o_read_trigger => o_msr_dcts_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_dcts, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_ddsr: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(1 downto 1), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(1 downto 1), + i_sw_write_data => bit_field_write_data(1 downto 1), + o_sw_read_data => bit_field_read_data(1 downto 1), + o_sw_value => bit_field_value(1 downto 1), + o_write_trigger => open, + o_read_trigger => o_msr_ddsr_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_ddsr, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_teri: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(2 downto 2), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(2 downto 2), + i_sw_write_data => bit_field_write_data(2 downto 2), + o_sw_read_data => bit_field_read_data(2 downto 2), + o_sw_value => bit_field_value(2 downto 2), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_teri, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_ddcd: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => true + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(3 downto 3), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(3 downto 3), + i_sw_write_data => bit_field_write_data(3 downto 3), + o_sw_read_data => bit_field_read_data(3 downto 3), + o_sw_value => bit_field_value(3 downto 3), + o_write_trigger => open, + o_read_trigger => o_msr_ddcd_read_trigger, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_ddcd, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_cts: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(4 downto 4), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(4 downto 4), + i_sw_write_data => bit_field_write_data(4 downto 4), + o_sw_read_data => bit_field_read_data(4 downto 4), + o_sw_value => bit_field_value(4 downto 4), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_cts, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_dsr: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(5 downto 5), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(5 downto 5), + i_sw_write_data => bit_field_write_data(5 downto 5), + o_sw_read_data => bit_field_read_data(5 downto 5), + o_sw_value => bit_field_value(5 downto 5), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_dsr, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_ri: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(6 downto 6), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(6 downto 6), + i_sw_write_data => bit_field_write_data(6 downto 6), + o_sw_read_data => bit_field_read_data(6 downto 6), + o_sw_value => bit_field_value(6 downto 6), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_ri, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + g_dcd: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 1, + STORAGE => false, + EXTERNAL_READ_DATA => true, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 7), + i_sw_write_enable => "0", + i_sw_write_mask => bit_field_write_mask(7 downto 7), + i_sw_write_data => bit_field_write_data(7 downto 7), + o_sw_read_data => bit_field_read_data(7 downto 7), + o_sw_value => bit_field_value(7 downto 7), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => i_msr_dcd, + i_mask => (others => '1'), + o_value => open, + o_value_unmasked => open + ); + end block; + end block; + g_scratch: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + u_register: entity work.rggen_default_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"1c", + BUS_WIDTH => 32, + DATA_WIDTH => 32 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(9), + o_register_ready => register_ready(9), + o_register_status => register_status(19 downto 18), + o_register_read_data => register_read_data(319 downto 288), + o_register_value => register_value(319 downto 288), + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_scratch: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(x"00", 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_scratch, + o_value_unmasked => open + ); + end block; + end block; + g_dll: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + signal indirect_match: std_logic_vector(0 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(167 downto 167)) = 1 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"00", + BUS_WIDTH => 32, + DATA_WIDTH => 32, + INDIRECT_MATCH_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(10), + o_register_ready => register_ready(10), + o_register_status => register_status(21 downto 20), + o_register_read_data => register_read_data(351 downto 320), + o_register_value => register_value(351 downto 320), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_dll: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(DLL_INITIAL_VALUE, 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_dll, + o_value_unmasked => open + ); + end block; + end block; + g_dlm: block + signal bit_field_valid: std_logic; + signal bit_field_read_mask: std_logic_vector(31 downto 0); + signal bit_field_write_mask: std_logic_vector(31 downto 0); + signal bit_field_write_data: std_logic_vector(31 downto 0); + signal bit_field_read_data: std_logic_vector(31 downto 0); + signal bit_field_value: std_logic_vector(31 downto 0); + signal indirect_match: std_logic_vector(0 downto 0); + begin + \g_tie_off\: for \__i\ in 0 to 31 generate + g: if (bit_slice(x"000000ff", \__i\) = '0') generate + bit_field_read_data(\__i\) <= '0'; + bit_field_value(\__i\) <= '0'; + end generate; + end generate; + indirect_match(0) <= '1' when unsigned(register_value(167 downto 167)) = 1 else '0'; + u_register: entity work.rggen_indirect_register + generic map ( + READABLE => true, + WRITABLE => true, + ADDRESS_WIDTH => 5, + OFFSET_ADDRESS => x"04", + BUS_WIDTH => 32, + DATA_WIDTH => 32, + INDIRECT_MATCH_WIDTH => 1 + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_register_valid => register_valid, + i_register_access => register_access, + i_register_address => register_address, + i_register_write_data => register_write_data, + i_register_strobe => register_strobe, + o_register_active => register_active(11), + o_register_ready => register_ready(11), + o_register_status => register_status(23 downto 22), + o_register_read_data => register_read_data(383 downto 352), + o_register_value => register_value(383 downto 352), + i_indirect_match => indirect_match, + o_bit_field_valid => bit_field_valid, + o_bit_field_read_mask => bit_field_read_mask, + o_bit_field_write_mask => bit_field_write_mask, + o_bit_field_write_data => bit_field_write_data, + i_bit_field_read_data => bit_field_read_data, + i_bit_field_value => bit_field_value + ); + g_dlm: block + begin + u_bit_field: entity work.rggen_bit_field + generic map ( + WIDTH => 8, + INITIAL_VALUE => slice(DLM_INITIAL_VALUE, 8, 0), + SW_WRITE_ONCE => false, + TRIGGER => false + ) + port map ( + i_clk => i_clk, + i_rst_n => i_rst_n, + i_sw_valid => bit_field_valid, + i_sw_read_mask => bit_field_read_mask(7 downto 0), + i_sw_write_enable => "1", + i_sw_write_mask => bit_field_write_mask(7 downto 0), + i_sw_write_data => bit_field_write_data(7 downto 0), + o_sw_read_data => bit_field_read_data(7 downto 0), + o_sw_value => bit_field_value(7 downto 0), + o_write_trigger => open, + o_read_trigger => open, + i_hw_write_enable => "0", + i_hw_write_data => (others => '0'), + i_hw_set => (others => '0'), + i_hw_clear => (others => '0'), + i_value => (others => '0'), + i_mask => (others => '1'), + o_value => o_dlm, + o_value_unmasked => open + ); + end block; + end block; +end rtl; diff --git a/third_party/tests/rggen/rggen-sample/uart_csr.yml b/third_party/tests/rggen/rggen-sample/uart_csr.yml new file mode 100644 index 0000000000..d8df588485 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr.yml @@ -0,0 +1,326 @@ +- register_block: + - name: uart_csr + byte_size: 32 + +################################################################ + - register: + - name: rbr + offset_address: 0x00 + type: [indirect, [lcr.dlab, 0]] + comment: | + Receiver Buffer Register + bit_fields: + - { bit_assignment: { lsb: 0, width: 8 }, type: rotrg } + +################################################################ + - register: + - name: thr + offset_address: 0x00 + type: [indirect, [lcr.dlab, 0]] + comment: | + Transmitter Holding Register + bit_fields: + - { bit_assignment: { lsb: 0, width: 8 }, type: wotrg, initial_value: 0xFF } + +################################################################ + - register: + - name: ier + offset_address: 0x04 + type: [indirect, [lcr.dlab, 0]] + comment: | + Interrupt Enable Register + bit_fields: + - <<: + - { name: erbfi, bit_assignment: { lsb: 0, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Enable Received Data Available Interrupt + 0: Disables Received Data Available Interrupts + 1: Enables Received Data Available Interrupts + - <<: + - { name: etbei, bit_assignment: { lsb: 1, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Enable Transmitter Holding Register Empty Interrupt + 0: Disables Transmitter Holding Register Empty Interrupts + 1: Enables Transmitter Holding Register Interrupts + - <<: + - { name: elsi, bit_assignment: { lsb: 2, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Enable Receiver Line Status Interrupt + 0: Disables Receiver Line Status Interrupts + 1: Enables Receiver Line Status Interrupts + - <<: + - { name: edssi, bit_assignment: { lsb: 3, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Enable Modem Status Interrupt + 0: Disables Modem Status Interrupts + 1: Enables Modem Status Interrupts + +################################################################ + - register: + - name: iir + offset_address: 0x08 + comment: | + Interrupt Identification Register + bit_fields: + - <<: + - { name: intpend, bit_assignment: { lsb: 0, width: 1 }, type: ro, initial_value: 1 } + - comment: | + 0: Interrupt is pending + 1: No interrupt is pending + - <<: + - { name: intid2, bit_assignment: { lsb: 1, width: 3 }, type: ro, initial_value: 0b000 } + - comment: | + Interrupt ID + 011: Receiver Line Status (Highest) + 010: Received Data Available (Second) + 110: Character Timeout (Second) + 001: Transmitter Holding Register Empty (Third) + 000: Modem Status (Fourth) + +################################################################ + - register: + - name: fcr + offset_address: 0x08 + comment: | + FIFO Control Register + bit_fields: + - <<: + - { name: fifoen, bit_assignment: { lsb: 0, width: 1 }, type: wo, initial_value: 0 } + - comment: | + FIFO Enable + 1: Enables FIFOs + - <<: + - { name: rcvr_fifo_reset, bit_assignment: { lsb: 1, width: 1 }, type: w1trg } + - comment: | + Receiver FIFO Reset + 1: Resets RCVR FIFO + - <<: + - { name: xmit_fifo_reset, bit_assignment: { lsb: 2, width: 1 }, type: w1trg } + - comment: | + Transmitter FIFO Reset + 1: Resets XMIT FIFO + - <<: + - { name: dma_mode_select, bit_assignment: { lsb: 3, width: 1 }, type: wo, initial_value: 0 } + - comment: | + DMA Mode Select + 0: Mode 0 + 1: Mode 1 + - <<: + - { name: rcvr_fifo_trigger_level, bit_assignment: { lsb: 6, width: 2 }, type: wo, initial_value: 0b00 } + - comment: | + RCVR FIFO Trigger Level + 0b00: 1 byte + 0b01: 4 bytes + 0b10: 8 bytes + 0b11: 14 bytes + +################################################################ + - register: + - name: lcr + offset_address: 0x0C + comment: | + line control register + bit_fields: + - <<: + - { name: wls, bit_assignment: { lsb: 0, width: 2 }, type: rw, initial_value: 0b11 } + - comment: | + Word Length Select + 0b00: 5 bits/character + 0b01: 6 bits/character + 0b10: 7 bits/character + 0b11: 8 bits/character + - <<: + - { name: stb, bit_assignment: { lsb: 2, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Number of Stop Bits + 0: 1 Stop bit + 1: 2 Stop bits or 1.5, if 5 bits/character selected + - <<: + - { name: pen, bit_assignment: { lsb: 3, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Parity Enable + 1: Enables parity + 0: Disables parity + - <<: + - { name: eps, bit_assignment: { lsb: 4, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Even Parity Select + 1: Selects Even parity + 0: Selects Odd parity + - <<: + - { name: stick_parity, bit_assignment: { lsb: 5, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Stick Parity + 1: Stick Parity is enabled + 0: Stick Parity is disabled + - <<: + - { name: set_break, bit_assignment: { lsb: 6, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Set Break + 1: Enables break condition + 0: Disables break condition + - <<: + - { name: dlab, bit_assignment: { lsb: 7, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Divisor Latch Access Bit. + 1: Allows access to the Divisor Latch Registers and reading of the FIFO Control Register + 0: Allows access to RBR, THR, IER and IIR registers + +################################################################ + - register: + - name: mrc + offset_address: 0x10 + comment: | + Modem Control Register + bit_fields: + - <<: + - { name: dtr, bit_assignment: { lsb: 0, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Data Terminal Ready + 1: Drives DTRN Low + 0: Drives DTRN High + - <<: + - { name: rts, bit_assignment: { lsb: 1, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Request To Send + 1: Drives RTSN Low + 0: Drives RTSN High + - <<: + - { name: out1, bit_assignment: { lsb: 2, width: 1 }, type: rw, initial_value: 0 } + - comment: | + User Output 1 + 1: Drives OUT1N Low + 0: Drives OUT1N High + - <<: + - { name: out2, bit_assignment: { lsb: 3, width: 1 }, type: rw, initial_value: 0 } + - comment: | + User Output 2 + 1: Drives OUT1N Low + 0: Drives OUT1N High + - <<: + - { name: loop, bit_assignment: { lsb: 4, width: 1 }, type: rw, initial_value: 0 } + - comment: | + Loop Back + 1: Enables loop back + +################################################################ + - register: + - name: lsr + offset_address: 0x14 + comment: | + Line Status Register + bit_fields: + - <<: + - { name: dr, bit_assignment: { lsb: 0, width: 1 }, type: ro, initial_value: 0 } + - comment: | + Data Ready + 0: All the data in RBR or FIFO is read + 1: Complete incoming character has been received and transferred into the RBR of FIFO + - <<: + - { name: oe, bit_assignment: { lsb: 1, width: 1 }, type: rotrg, initial_value: 0 } + - comment: | + Overrun Error + - <<: + - { name: pe, bit_assignment: { lsb: 2, width: 1 }, type: rotrg, initial_value: 0 } + - comment: | + Parity Error + - <<: + - { name: fe, bit_assignment: { lsb: 3, width: 1 }, type: rotrg, initial_value: 0 } + - comment: | + Framing Error + - <<: + - { name: bi, bit_assignment: { lsb: 4, width: 1 }, type: rotrg, initial_value: 0 } + - comment: | + Break Interrupt + - <<: + - { name: thre, bit_assignment: { lsb: 5, width: 1 }, type: ro, initial_value: 0 } + - comment: | + Transmitter Holding Register Empty + 0: THR or Transmitter FIFO has data to transmit + 1: THR and Transmitter FIFO are empty + - <<: + - { name: temt, bit_assignment: { lsb: 6, width: 1 }, type: ro, initial_value: 0 } + - comment: | + Transmitter Empty: + 0: THR or Transmitter shift register contains data + 1: THR, Transmitter FIFO and Transmitter shift register are empty + - <<: + - { name: error_in_rcvr_fifo, bit_assignment: { lsb: 7, width: 1 }, type: ro, initial_value: 0 } + - comment: | + RCVR FIFO contains at least one receiver error (Parity, Framing, Break condition) + +################################################################ + - register: + - name: msr + offset_address: 0x18 + comment: | + Modem Status Register + bit_fields: + - <<: + - { name: dcts, bit_assignment: { lsb: 0, width: 1 }, type: rotrg, initial_value: 0 } + - comment: | + Delta Clear To Send + Change in CTSN after last MSR read + - <<: + - { name: ddsr, bit_assignment: { lsb: 1, width: 1 }, type: rotrg, initial_value: 0 } + - comment: | + Delta Data Set Ready + Change in DSRN after last MSR read + - <<: + - { name: teri, bit_assignment: { lsb: 2, width: 1 }, type: ro, initial_value: 0 } + - comment: | + Trailing Edge Ring Indicator + RIN has changed from a Low to a High + - <<: + - { name: ddcd, bit_assignment: { lsb: 3, width: 1 }, type: rotrg, initial_value: 0 } + - comment: | + Delta Data Carrier Detect + Change in DCDN after last MSR read + - <<: + - { name: cts, bit_assignment: { lsb: 4, width: 1 }, type: ro } + - comment: | + Clear To Send + Complement of CTSN input + - <<: + - { name: dsr, bit_assignment: { lsb: 5, width: 1 }, type: ro } + - comment: | + Data Set Ready + Complement of DSRN input + - <<: + - { name: ri, bit_assignment: { lsb: 6, width: 1 }, type: ro } + - comment: | + Ring Indicator + Complement of RIN input + - <<: + - { name: dcd, bit_assignment: { lsb: 7, width: 1 }, type: ro } + - comment: | + Data Carrier Detect + Complement of DCDN input + +################################################################ + - register: + - name: scratch + offset_address: 0x1c + comment: | + Scratch Register + bit_fields: + - { bit_assignment: { lsb: 0, width: 8 }, type: rw, initial_value: 0 } + +################################################################ + - register: + - name: dll + offset_address: 0x00 + type: [indirect, [lcr.dlab, 1]] + comment: | + Divisor Latch (Least Significant Byte) Register + bit_fields: + - { bit_assignment: { lsb: 0, width: 8 }, type: rw, initial_value: { default: 0 }} + + - register: + - name: dlm + offset_address: 0x04 + type: [indirect, [lcr.dlab, 1]] + comment: | + Divisor Latch (Most Significant Byte) Register + bit_fields: + - { bit_assignment: { lsb: 0, width: 8 }, type: rw, initial_value: { default: 0 }} diff --git a/third_party/tests/rggen/rggen-sample/uart_csr_ral_pkg.sv b/third_party/tests/rggen/rggen-sample/uart_csr_ral_pkg.sv new file mode 100644 index 0000000000..eeda355dc8 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr_ral_pkg.sv @@ -0,0 +1,224 @@ +package uart_csr_ral_pkg; + import uvm_pkg::*; + import rggen_ral_pkg::*; + `include "uvm_macros.svh" + `include "rggen_ral_macros.svh" + class rbr_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field rbr; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(rbr, 0, 8, "RO", 1, 8'h00, 0, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("lcr.dlab", 1'h0); + endfunction + endclass + class thr_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field thr; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(thr, 0, 8, "WO", 0, 8'hff, 1, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("lcr.dlab", 1'h0); + endfunction + endclass + class ier_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field erbfi; + rand rggen_ral_field etbei; + rand rggen_ral_field elsi; + rand rggen_ral_field edssi; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(erbfi, 0, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(etbei, 1, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(elsi, 2, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(edssi, 3, 1, "RW", 0, 1'h0, 1, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("lcr.dlab", 1'h0); + endfunction + endclass + class iir_reg_model extends rggen_ral_reg; + rand rggen_ral_field intpend; + rand rggen_ral_field intid2; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(intpend, 0, 1, "RO", 1, 1'h1, 1, -1, "") + `rggen_ral_create_field(intid2, 1, 3, "RO", 1, 3'h0, 1, -1, "") + endfunction + endclass + class fcr_reg_model extends rggen_ral_reg; + rand rggen_ral_field fifoen; + rand rggen_ral_w1trg_field rcvr_fifo_reset; + rand rggen_ral_w1trg_field xmit_fifo_reset; + rand rggen_ral_field dma_mode_select; + rand rggen_ral_field rcvr_fifo_trigger_level; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(fifoen, 0, 1, "WO", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(rcvr_fifo_reset, 1, 1, "W1TRG", 0, 1'h0, 0, -1, "") + `rggen_ral_create_field(xmit_fifo_reset, 2, 1, "W1TRG", 0, 1'h0, 0, -1, "") + `rggen_ral_create_field(dma_mode_select, 3, 1, "WO", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(rcvr_fifo_trigger_level, 6, 2, "WO", 0, 2'h0, 1, -1, "") + endfunction + endclass + class lcr_reg_model extends rggen_ral_reg; + rand rggen_ral_field wls; + rand rggen_ral_field stb; + rand rggen_ral_field pen; + rand rggen_ral_field eps; + rand rggen_ral_field stick_parity; + rand rggen_ral_field set_break; + rand rggen_ral_field dlab; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(wls, 0, 2, "RW", 0, 2'h3, 1, -1, "") + `rggen_ral_create_field(stb, 2, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(pen, 3, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(eps, 4, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(stick_parity, 5, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(set_break, 6, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(dlab, 7, 1, "RW", 0, 1'h0, 1, -1, "") + endfunction + endclass + class mrc_reg_model extends rggen_ral_reg; + rand rggen_ral_field dtr; + rand rggen_ral_field rts; + rand rggen_ral_field out1; + rand rggen_ral_field out2; + rand rggen_ral_field loop; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(dtr, 0, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(rts, 1, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(out1, 2, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(out2, 3, 1, "RW", 0, 1'h0, 1, -1, "") + `rggen_ral_create_field(loop, 4, 1, "RW", 0, 1'h0, 1, -1, "") + endfunction + endclass + class lsr_reg_model extends rggen_ral_reg; + rand rggen_ral_field dr; + rand rggen_ral_field oe; + rand rggen_ral_field pe; + rand rggen_ral_field fe; + rand rggen_ral_field bi; + rand rggen_ral_field thre; + rand rggen_ral_field temt; + rand rggen_ral_field error_in_rcvr_fifo; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(dr, 0, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(oe, 1, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(pe, 2, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(fe, 3, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(bi, 4, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(thre, 5, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(temt, 6, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(error_in_rcvr_fifo, 7, 1, "RO", 1, 1'h0, 1, -1, "") + endfunction + endclass + class msr_reg_model extends rggen_ral_reg; + rand rggen_ral_field dcts; + rand rggen_ral_field ddsr; + rand rggen_ral_field teri; + rand rggen_ral_field ddcd; + rand rggen_ral_field cts; + rand rggen_ral_field dsr; + rand rggen_ral_field ri; + rand rggen_ral_field dcd; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(dcts, 0, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(ddsr, 1, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(teri, 2, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(ddcd, 3, 1, "RO", 1, 1'h0, 1, -1, "") + `rggen_ral_create_field(cts, 4, 1, "RO", 1, 1'h0, 0, -1, "") + `rggen_ral_create_field(dsr, 5, 1, "RO", 1, 1'h0, 0, -1, "") + `rggen_ral_create_field(ri, 6, 1, "RO", 1, 1'h0, 0, -1, "") + `rggen_ral_create_field(dcd, 7, 1, "RO", 1, 1'h0, 0, -1, "") + endfunction + endclass + class scratch_reg_model extends rggen_ral_reg; + rand rggen_ral_field scratch; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(scratch, 0, 8, "RW", 0, 8'h00, 1, -1, "") + endfunction + endclass + class dll_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field dll; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(dll, 0, 8, "RW", 0, 8'h00, 1, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("lcr.dlab", 1'h1); + endfunction + endclass + class dlm_reg_model extends rggen_ral_indirect_reg; + rand rggen_ral_field dlm; + function new(string name); + super.new(name, 32, 0); + endfunction + function void build(); + `rggen_ral_create_field(dlm, 0, 8, "RW", 0, 8'h00, 1, -1, "") + endfunction + function void setup_index_fields(); + setup_index_field("lcr.dlab", 1'h1); + endfunction + endclass + class uart_csr_block_model extends rggen_ral_block; + rand rbr_reg_model rbr; + rand thr_reg_model thr; + rand ier_reg_model ier; + rand iir_reg_model iir; + rand fcr_reg_model fcr; + rand lcr_reg_model lcr; + rand mrc_reg_model mrc; + rand lsr_reg_model lsr; + rand msr_reg_model msr; + rand scratch_reg_model scratch; + rand dll_reg_model dll; + rand dlm_reg_model dlm; + function new(string name); + super.new(name, 4, 0); + endfunction + function void build(); + `rggen_ral_create_reg(rbr, '{}, 5'h00, "RO", "g_rbr.u_register") + `rggen_ral_create_reg(thr, '{}, 5'h00, "WO", "g_thr.u_register") + `rggen_ral_create_reg(ier, '{}, 5'h04, "RW", "g_ier.u_register") + `rggen_ral_create_reg(iir, '{}, 5'h08, "RO", "g_iir.u_register") + `rggen_ral_create_reg(fcr, '{}, 5'h08, "WO", "g_fcr.u_register") + `rggen_ral_create_reg(lcr, '{}, 5'h0c, "RW", "g_lcr.u_register") + `rggen_ral_create_reg(mrc, '{}, 5'h10, "RW", "g_mrc.u_register") + `rggen_ral_create_reg(lsr, '{}, 5'h14, "RO", "g_lsr.u_register") + `rggen_ral_create_reg(msr, '{}, 5'h18, "RO", "g_msr.u_register") + `rggen_ral_create_reg(scratch, '{}, 5'h1c, "RW", "g_scratch.u_register") + `rggen_ral_create_reg(dll, '{}, 5'h00, "RW", "g_dll.u_register") + `rggen_ral_create_reg(dlm, '{}, 5'h04, "RW", "g_dlm.u_register") + endfunction + endclass +endpackage diff --git a/third_party/tests/rggen/rggen-sample/uart_csr_rtl_pkg.sv b/third_party/tests/rggen/rggen-sample/uart_csr_rtl_pkg.sv new file mode 100644 index 0000000000..9f97c0f557 --- /dev/null +++ b/third_party/tests/rggen/rggen-sample/uart_csr_rtl_pkg.sv @@ -0,0 +1,170 @@ +package uart_csr_rtl_pkg; + localparam int RBR_BYTE_WIDTH = 4; + localparam int RBR_BYTE_SIZE = 4; + localparam bit [4:0] RBR_BYTE_OFFSET = 5'h00; + localparam int RBR_BIT_WIDTH = 8; + localparam bit [7:0] RBR_BIT_MASK = 8'hff; + localparam int RBR_BIT_OFFSET = 0; + localparam int THR_BYTE_WIDTH = 4; + localparam int THR_BYTE_SIZE = 4; + localparam bit [4:0] THR_BYTE_OFFSET = 5'h00; + localparam int THR_BIT_WIDTH = 8; + localparam bit [7:0] THR_BIT_MASK = 8'hff; + localparam int THR_BIT_OFFSET = 0; + localparam int IER_BYTE_WIDTH = 4; + localparam int IER_BYTE_SIZE = 4; + localparam bit [4:0] IER_BYTE_OFFSET = 5'h04; + localparam int IER_ERBFI_BIT_WIDTH = 1; + localparam bit IER_ERBFI_BIT_MASK = 1'h1; + localparam int IER_ERBFI_BIT_OFFSET = 0; + localparam int IER_ETBEI_BIT_WIDTH = 1; + localparam bit IER_ETBEI_BIT_MASK = 1'h1; + localparam int IER_ETBEI_BIT_OFFSET = 1; + localparam int IER_ELSI_BIT_WIDTH = 1; + localparam bit IER_ELSI_BIT_MASK = 1'h1; + localparam int IER_ELSI_BIT_OFFSET = 2; + localparam int IER_EDSSI_BIT_WIDTH = 1; + localparam bit IER_EDSSI_BIT_MASK = 1'h1; + localparam int IER_EDSSI_BIT_OFFSET = 3; + localparam int IIR_BYTE_WIDTH = 4; + localparam int IIR_BYTE_SIZE = 4; + localparam bit [4:0] IIR_BYTE_OFFSET = 5'h08; + localparam int IIR_INTPEND_BIT_WIDTH = 1; + localparam bit IIR_INTPEND_BIT_MASK = 1'h1; + localparam int IIR_INTPEND_BIT_OFFSET = 0; + localparam int IIR_INTID2_BIT_WIDTH = 3; + localparam bit [2:0] IIR_INTID2_BIT_MASK = 3'h7; + localparam int IIR_INTID2_BIT_OFFSET = 1; + localparam int FCR_BYTE_WIDTH = 4; + localparam int FCR_BYTE_SIZE = 4; + localparam bit [4:0] FCR_BYTE_OFFSET = 5'h08; + localparam int FCR_FIFOEN_BIT_WIDTH = 1; + localparam bit FCR_FIFOEN_BIT_MASK = 1'h1; + localparam int FCR_FIFOEN_BIT_OFFSET = 0; + localparam int FCR_RCVR_FIFO_RESET_BIT_WIDTH = 1; + localparam bit FCR_RCVR_FIFO_RESET_BIT_MASK = 1'h1; + localparam int FCR_RCVR_FIFO_RESET_BIT_OFFSET = 1; + localparam int FCR_XMIT_FIFO_RESET_BIT_WIDTH = 1; + localparam bit FCR_XMIT_FIFO_RESET_BIT_MASK = 1'h1; + localparam int FCR_XMIT_FIFO_RESET_BIT_OFFSET = 2; + localparam int FCR_DMA_MODE_SELECT_BIT_WIDTH = 1; + localparam bit FCR_DMA_MODE_SELECT_BIT_MASK = 1'h1; + localparam int FCR_DMA_MODE_SELECT_BIT_OFFSET = 3; + localparam int FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_WIDTH = 2; + localparam bit [1:0] FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_MASK = 2'h3; + localparam int FCR_RCVR_FIFO_TRIGGER_LEVEL_BIT_OFFSET = 6; + localparam int LCR_BYTE_WIDTH = 4; + localparam int LCR_BYTE_SIZE = 4; + localparam bit [4:0] LCR_BYTE_OFFSET = 5'h0c; + localparam int LCR_WLS_BIT_WIDTH = 2; + localparam bit [1:0] LCR_WLS_BIT_MASK = 2'h3; + localparam int LCR_WLS_BIT_OFFSET = 0; + localparam int LCR_STB_BIT_WIDTH = 1; + localparam bit LCR_STB_BIT_MASK = 1'h1; + localparam int LCR_STB_BIT_OFFSET = 2; + localparam int LCR_PEN_BIT_WIDTH = 1; + localparam bit LCR_PEN_BIT_MASK = 1'h1; + localparam int LCR_PEN_BIT_OFFSET = 3; + localparam int LCR_EPS_BIT_WIDTH = 1; + localparam bit LCR_EPS_BIT_MASK = 1'h1; + localparam int LCR_EPS_BIT_OFFSET = 4; + localparam int LCR_STICK_PARITY_BIT_WIDTH = 1; + localparam bit LCR_STICK_PARITY_BIT_MASK = 1'h1; + localparam int LCR_STICK_PARITY_BIT_OFFSET = 5; + localparam int LCR_SET_BREAK_BIT_WIDTH = 1; + localparam bit LCR_SET_BREAK_BIT_MASK = 1'h1; + localparam int LCR_SET_BREAK_BIT_OFFSET = 6; + localparam int LCR_DLAB_BIT_WIDTH = 1; + localparam bit LCR_DLAB_BIT_MASK = 1'h1; + localparam int LCR_DLAB_BIT_OFFSET = 7; + localparam int MRC_BYTE_WIDTH = 4; + localparam int MRC_BYTE_SIZE = 4; + localparam bit [4:0] MRC_BYTE_OFFSET = 5'h10; + localparam int MRC_DTR_BIT_WIDTH = 1; + localparam bit MRC_DTR_BIT_MASK = 1'h1; + localparam int MRC_DTR_BIT_OFFSET = 0; + localparam int MRC_RTS_BIT_WIDTH = 1; + localparam bit MRC_RTS_BIT_MASK = 1'h1; + localparam int MRC_RTS_BIT_OFFSET = 1; + localparam int MRC_OUT1_BIT_WIDTH = 1; + localparam bit MRC_OUT1_BIT_MASK = 1'h1; + localparam int MRC_OUT1_BIT_OFFSET = 2; + localparam int MRC_OUT2_BIT_WIDTH = 1; + localparam bit MRC_OUT2_BIT_MASK = 1'h1; + localparam int MRC_OUT2_BIT_OFFSET = 3; + localparam int MRC_LOOP_BIT_WIDTH = 1; + localparam bit MRC_LOOP_BIT_MASK = 1'h1; + localparam int MRC_LOOP_BIT_OFFSET = 4; + localparam int LSR_BYTE_WIDTH = 4; + localparam int LSR_BYTE_SIZE = 4; + localparam bit [4:0] LSR_BYTE_OFFSET = 5'h14; + localparam int LSR_DR_BIT_WIDTH = 1; + localparam bit LSR_DR_BIT_MASK = 1'h1; + localparam int LSR_DR_BIT_OFFSET = 0; + localparam int LSR_OE_BIT_WIDTH = 1; + localparam bit LSR_OE_BIT_MASK = 1'h1; + localparam int LSR_OE_BIT_OFFSET = 1; + localparam int LSR_PE_BIT_WIDTH = 1; + localparam bit LSR_PE_BIT_MASK = 1'h1; + localparam int LSR_PE_BIT_OFFSET = 2; + localparam int LSR_FE_BIT_WIDTH = 1; + localparam bit LSR_FE_BIT_MASK = 1'h1; + localparam int LSR_FE_BIT_OFFSET = 3; + localparam int LSR_BI_BIT_WIDTH = 1; + localparam bit LSR_BI_BIT_MASK = 1'h1; + localparam int LSR_BI_BIT_OFFSET = 4; + localparam int LSR_THRE_BIT_WIDTH = 1; + localparam bit LSR_THRE_BIT_MASK = 1'h1; + localparam int LSR_THRE_BIT_OFFSET = 5; + localparam int LSR_TEMT_BIT_WIDTH = 1; + localparam bit LSR_TEMT_BIT_MASK = 1'h1; + localparam int LSR_TEMT_BIT_OFFSET = 6; + localparam int LSR_ERROR_IN_RCVR_FIFO_BIT_WIDTH = 1; + localparam bit LSR_ERROR_IN_RCVR_FIFO_BIT_MASK = 1'h1; + localparam int LSR_ERROR_IN_RCVR_FIFO_BIT_OFFSET = 7; + localparam int MSR_BYTE_WIDTH = 4; + localparam int MSR_BYTE_SIZE = 4; + localparam bit [4:0] MSR_BYTE_OFFSET = 5'h18; + localparam int MSR_DCTS_BIT_WIDTH = 1; + localparam bit MSR_DCTS_BIT_MASK = 1'h1; + localparam int MSR_DCTS_BIT_OFFSET = 0; + localparam int MSR_DDSR_BIT_WIDTH = 1; + localparam bit MSR_DDSR_BIT_MASK = 1'h1; + localparam int MSR_DDSR_BIT_OFFSET = 1; + localparam int MSR_TERI_BIT_WIDTH = 1; + localparam bit MSR_TERI_BIT_MASK = 1'h1; + localparam int MSR_TERI_BIT_OFFSET = 2; + localparam int MSR_DDCD_BIT_WIDTH = 1; + localparam bit MSR_DDCD_BIT_MASK = 1'h1; + localparam int MSR_DDCD_BIT_OFFSET = 3; + localparam int MSR_CTS_BIT_WIDTH = 1; + localparam bit MSR_CTS_BIT_MASK = 1'h1; + localparam int MSR_CTS_BIT_OFFSET = 4; + localparam int MSR_DSR_BIT_WIDTH = 1; + localparam bit MSR_DSR_BIT_MASK = 1'h1; + localparam int MSR_DSR_BIT_OFFSET = 5; + localparam int MSR_RI_BIT_WIDTH = 1; + localparam bit MSR_RI_BIT_MASK = 1'h1; + localparam int MSR_RI_BIT_OFFSET = 6; + localparam int MSR_DCD_BIT_WIDTH = 1; + localparam bit MSR_DCD_BIT_MASK = 1'h1; + localparam int MSR_DCD_BIT_OFFSET = 7; + localparam int SCRATCH_BYTE_WIDTH = 4; + localparam int SCRATCH_BYTE_SIZE = 4; + localparam bit [4:0] SCRATCH_BYTE_OFFSET = 5'h1c; + localparam int SCRATCH_BIT_WIDTH = 8; + localparam bit [7:0] SCRATCH_BIT_MASK = 8'hff; + localparam int SCRATCH_BIT_OFFSET = 0; + localparam int DLL_BYTE_WIDTH = 4; + localparam int DLL_BYTE_SIZE = 4; + localparam bit [4:0] DLL_BYTE_OFFSET = 5'h00; + localparam int DLL_BIT_WIDTH = 8; + localparam bit [7:0] DLL_BIT_MASK = 8'hff; + localparam int DLL_BIT_OFFSET = 0; + localparam int DLM_BYTE_WIDTH = 4; + localparam int DLM_BYTE_SIZE = 4; + localparam bit [4:0] DLM_BYTE_OFFSET = 5'h04; + localparam int DLM_BIT_WIDTH = 8; + localparam bit [7:0] DLM_BIT_MASK = 8'hff; + localparam int DLM_BIT_OFFSET = 0; +endpackage diff --git a/third_party/tests/rggen/rggen-sv-rtl/.github/workflows/svlint.yml b/third_party/tests/rggen/rggen-sv-rtl/.github/workflows/svlint.yml new file mode 100644 index 0000000000..74356d1a0f --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/.github/workflows/svlint.yml @@ -0,0 +1,18 @@ +name: svlint + +on: [push, pull_request] + +jobs: + svlint: + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + + - name: Run svlint + uses: dalance/svlint-action@v1 + with: + filelists: | + compile.f + env: + RGGEN_SV_RTL_ROOT: ${{ github.workspace }} diff --git a/third_party/tests/rggen/rggen-sv-rtl/.svlint.toml b/third_party/tests/rggen/rggen-sv-rtl/.svlint.toml new file mode 100644 index 0000000000..b4683872fd --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/.svlint.toml @@ -0,0 +1,30 @@ +[option] +exclude_paths = [] + +[rules] +case_default = false +enum_with_type = true +for_with_begin = true +function_same_as_system_function = true +function_with_automatic = true +generate_for_with_label = true +generate_if_with_label = true +generate_keyword_forbidden = false +generate_keyword_required = true +genvar_declaration_in_loop = false +genvar_declaration_out_loop = true +if_with_begin = true +inout_with_tri = false +input_with_var = false +interface_port_with_modport = true +legacy_always = true +level_sensitive_always = true +loop_variable_declaration = true +non_ansi_module = true +output_with_var = false +parameter_in_package = true +priority_keyword = false +tab_character = true +unique0_keyword = false +unique_keyword = false +wire_reg = false diff --git a/third_party/tests/rggen/rggen-sv-rtl/LICENSE b/third_party/tests/rggen/rggen-sv-rtl/LICENSE new file mode 100644 index 0000000000..83e0fdf4fe --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2019-2023 Taichi Ishitani + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/third_party/tests/rggen/rggen-sv-rtl/compile.f b/third_party/tests/rggen/rggen-sv-rtl/compile.f new file mode 100644 index 0000000000..04e2fb65fd --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/compile.f @@ -0,0 +1,25 @@ +-f ${RGGEN_SV_RTL_ROOT}/compile_backdoor.f +${RGGEN_SV_RTL_ROOT}/rggen_rtl_pkg.sv +${RGGEN_SV_RTL_ROOT}/rggen_or_reducer.sv +${RGGEN_SV_RTL_ROOT}/rggen_mux.sv +${RGGEN_SV_RTL_ROOT}/rggen_bit_field_if.sv +${RGGEN_SV_RTL_ROOT}/rggen_bit_field.sv +${RGGEN_SV_RTL_ROOT}/rggen_bit_field_w01trg.sv +${RGGEN_SV_RTL_ROOT}/rggen_register_if.sv +${RGGEN_SV_RTL_ROOT}/rggen_address_decoder.sv +${RGGEN_SV_RTL_ROOT}/rggen_register_common.sv +${RGGEN_SV_RTL_ROOT}/rggen_default_register.sv +${RGGEN_SV_RTL_ROOT}/rggen_external_register.sv +${RGGEN_SV_RTL_ROOT}/rggen_indirect_register.sv +${RGGEN_SV_RTL_ROOT}/rggen_bus_if.sv +${RGGEN_SV_RTL_ROOT}/rggen_adapter_common.sv +${RGGEN_SV_RTL_ROOT}/rggen_apb_if.sv +${RGGEN_SV_RTL_ROOT}/rggen_apb_adapter.sv +${RGGEN_SV_RTL_ROOT}/rggen_apb_bridge.sv +${RGGEN_SV_RTL_ROOT}/rggen_axi4lite_if.sv +${RGGEN_SV_RTL_ROOT}/rggen_axi4lite_skid_buffer.sv +${RGGEN_SV_RTL_ROOT}/rggen_axi4lite_adapter.sv +${RGGEN_SV_RTL_ROOT}/rggen_axi4lite_bridge.sv +${RGGEN_SV_RTL_ROOT}/rggen_wishbone_if.sv +${RGGEN_SV_RTL_ROOT}/rggen_wishbone_adapter.sv +${RGGEN_SV_RTL_ROOT}/rggen_wishbone_bridge.sv diff --git a/third_party/tests/rggen/rggen-sv-rtl/compile.rb b/third_party/tests/rggen/rggen-sv-rtl/compile.rb new file mode 100644 index 0000000000..e6dfad3478 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/compile.rb @@ -0,0 +1,30 @@ +if macro_defined? :RGGEN_ENABLE_BACKDOOR + file_list 'compile_backdoor.rb', from: :current +end + +[ + 'rggen_rtl_pkg.sv', + 'rggen_or_reducer.sv', + 'rggen_mux.sv', + 'rggen_bit_field_if.sv', + 'rggen_bit_field.sv', + 'rggen_bit_field_w01trg.sv', + 'rggen_register_if.sv', + 'rggen_address_decoder.sv', + 'rggen_register_common.sv', + 'rggen_default_register.sv', + 'rggen_external_register.sv', + 'rggen_indirect_register.sv', + 'rggen_bus_if.sv', + 'rggen_adapter_common.sv', + 'rggen_apb_if.sv', + 'rggen_apb_adapter.sv', + 'rggen_apb_bridge.sv', + 'rggen_axi4lite_if.sv', + 'rggen_axi4lite_skid_buffer.sv', + 'rggen_axi4lite_adapter.sv', + 'rggen_axi4lite_bridge.sv', + 'rggen_wishbone_if.sv', + 'rggen_wishbone_adapter.sv', + 'rggen_wishbone_bridge.sv' +].each { |file| source_file file } diff --git a/third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.f b/third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.f new file mode 100644 index 0000000000..befb30aaba --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.f @@ -0,0 +1,3 @@ +${RGGEN_SV_RTL_ROOT}/rggen_backdoor_if.sv +${RGGEN_SV_RTL_ROOT}/rggen_backdoor_pkg.sv +${RGGEN_SV_RTL_ROOT}/rggen_backdoor.sv diff --git a/third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.rb b/third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.rb new file mode 100644 index 0000000000..28f18b7bc2 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/compile_backdoor.rb @@ -0,0 +1,5 @@ +[ + 'rggen_backdoor_if.sv', + 'rggen_backdoor_pkg.sv', + 'rggen_backdoor.sv' +].each { |file| source_file file } diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv new file mode 100644 index 0000000000..ba09e11383 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_adapter_common.sv @@ -0,0 +1,192 @@ +module rggen_adapter_common + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 8, + parameter int LOCAL_ADDRESS_WIDTH = 8, + parameter int BUS_WIDTH = 32, + parameter int REGISTERS = 1, + parameter bit PRE_DECODE = 0, + parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, + parameter int BYTE_SIZE = 256, + parameter bit ERROR_STATUS = 0, + parameter bit [BUS_WIDTH-1:0] DEFAULT_READ_DATA = '0, + parameter bit INSERT_SLICER = 0 +)( + input logic i_clk, + input logic i_rst_n, + rggen_bus_if.slave bus_if, + rggen_register_if.host register_if[REGISTERS] +); + genvar i; + + // State + logic busy; + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + busy <= '0; + end + else if (bus_if.ready) begin + busy <= '0; + end + else if (bus_if.valid) begin + busy <= '1; + end + end + + // Pre-decode + logic inside_range; + + assign inside_range = pre_decode(bus_if.address); + + function automatic logic pre_decode( + logic [ADDRESS_WIDTH-1:0] address + ); + if (PRE_DECODE) begin + logic [ADDRESS_WIDTH-1:0] begin_addrss; + logic [ADDRESS_WIDTH-1:0] end_address; + + begin_addrss = BASE_ADDRESS; + end_address = BASE_ADDRESS + ADDRESS_WIDTH'(BYTE_SIZE - 1); + + return (address >= begin_addrss) && (address <= end_address); + end + else begin + return '1; + end + endfunction + + // Request + logic bus_valid; + rggen_access bus_access; + logic [LOCAL_ADDRESS_WIDTH-1:0] bus_address; + logic [BUS_WIDTH-1:0] bus_write_data; + logic [BUS_WIDTH/8-1:0] bus_strobe; + + generate + if (INSERT_SLICER) begin : g_request_slicer + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + bus_valid <= '0; + end + else if (!busy) begin + bus_valid <= bus_if.valid && inside_range; + end + else begin + bus_valid <= '0; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + bus_access <= rggen_access'(0); + bus_address <= '0; + bus_write_data <= '0; + bus_strobe <= '0; + end + else if (bus_if.valid && (!busy)) begin + bus_access <= bus_if.access; + bus_address <= get_local_address(bus_if.address); + bus_write_data <= bus_if.write_data; + bus_strobe <= bus_if.strobe; + end + end + end + else begin : g_no_request_slicer + assign bus_valid = bus_if.valid && inside_range && (!busy); + assign bus_access = bus_if.access; + assign bus_address = get_local_address(bus_if.address); + assign bus_write_data = bus_if.write_data; + assign bus_strobe = bus_if.strobe; + end + + for (i = 0;i < REGISTERS;++i) begin : g_request + assign register_if[i].valid = bus_valid; + assign register_if[i].access = bus_access; + assign register_if[i].address = bus_address; + assign register_if[i].write_data = bus_write_data; + assign register_if[i].strobe = bus_strobe; + end + endgenerate + + function automatic logic [LOCAL_ADDRESS_WIDTH-1:0] get_local_address( + logic [ADDRESS_WIDTH-1:0] address + ); + logic [ADDRESS_WIDTH-1:0] local_address; + + if (BASE_ADDRESS[0+:LOCAL_ADDRESS_WIDTH] == '0) begin + local_address = address; + end + else begin + local_address = address - BASE_ADDRESS; + end + + return local_address[0+:LOCAL_ADDRESS_WIDTH]; + endfunction + + // Response + localparam rggen_status DEFAULT_STATUS = (ERROR_STATUS) ? RGGEN_SLAVE_ERROR : RGGEN_OKAY; + localparam int STATUS_WIDTH = $bits(rggen_status); + localparam int RESPONSE_WIDTH = BUS_WIDTH + STATUS_WIDTH; + + logic [REGISTERS-1:0] ready; + logic [REGISTERS-1:0] active; + logic [REGISTERS-1:0][RESPONSE_WIDTH-1:0] response; + logic [RESPONSE_WIDTH-1:0] selected_response; + logic register_inactive; + rggen_status register_status; + logic [BUS_WIDTH-1:0] register_read_data; + + generate + for (i = 0;i < REGISTERS;++i) begin : g_response + assign active[i] = register_if[i].active; + assign ready[i] = register_if[i].ready; + assign response[i] = {register_if[i].status, register_if[i].read_data}; + end + endgenerate + + rggen_mux #( + .WIDTH (RESPONSE_WIDTH ), + .ENTRIES (REGISTERS ) + ) u_mux ( + .i_select (active ), + .i_data (response ), + .o_data (selected_response ) + ); + + assign register_inactive = (!inside_range) || (active == '0); + assign register_status = rggen_status'(selected_response[BUS_WIDTH+:STATUS_WIDTH]); + assign register_read_data = selected_response[0+:BUS_WIDTH]; + + assign bus_if.ready = ((!INSERT_SLICER) || busy) && ((ready != '0) || register_inactive); + assign bus_if.status = (register_inactive) ? DEFAULT_STATUS : register_status; + assign bus_if.read_data = (register_inactive) ? DEFAULT_READ_DATA : register_read_data; + +`ifdef RGGEN_ENABLE_SVA + ast_hold_request_command_until_ready_is_high: + assert property ( + @(posedge i_clk) + (bus_if.valid && (!bus_if.ready)) |=> + ($stable(bus_if.valid) && $stable(bus_if.access) && $stable(bus_if.address)) + ); + + ast_hold_request_data_until_ready_is_high: + assert property ( + @(posedge i_clk) + (bus_if.valid && (!bus_if.ready) && (bus_if.access != RGGEN_READ)) |=> + ($stable(bus_if.write_data) && $stable(bus_if.strobe)) + ); + + ast_only_one_register_is_active: + assert property ( + @(posedge i_clk) + (bus_if.valid && (active != '0)) |-> $onehot(active) + ); + + ast_assert_ready_of_active_register_only: + assert property ( + @(posedge i_clk) + (bus_if.valid && (ready != '0)) |-> (active == ready) + ); +`endif +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv new file mode 100644 index 0000000000..e81f560a9e --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_address_decoder.sv @@ -0,0 +1,63 @@ +module rggen_address_decoder + import rggen_rtl_pkg::*; +#( + parameter bit READABLE = 1, + parameter bit WRITABLE = 1, + parameter int WIDTH = 8, + parameter int BUS_WIDTH = 32, + parameter bit [WIDTH-1:0] START_ADDRESS = '0, + parameter int BYTE_SIZE = 0 +)( + input logic [WIDTH-1:0] i_address, + input rggen_access i_access, + input logic i_additional_match, + output logic o_match +); + localparam int LSB = $clog2(BUS_WIDTH) - 3; + localparam bit [WIDTH-LSB-1:0] BEGIN_ADDRESS = START_ADDRESS[WIDTH-1:LSB]; + localparam bit [WIDTH-LSB-1:0] END_ADDRESS = calc_end_address(START_ADDRESS, BYTE_SIZE); + + function automatic bit [WIDTH-LSB-1:0] calc_end_address( + bit [WIDTH-1:0] start_address, + int byte_size + ); + bit [WIDTH-1:0] end_address; + end_address = start_address + WIDTH'(byte_size - 1); + return end_address[WIDTH-1:LSB]; + endfunction + + logic address_match; + logic access_match; + + generate + if (BEGIN_ADDRESS == END_ADDRESS) begin : g_address_matcher + assign address_match = i_address[WIDTH-1:LSB] == BEGIN_ADDRESS; + end + else if ((BEGIN_ADDRESS != '0) && (END_ADDRESS != '1)) begin : g_address_matcher + assign address_match = + (i_address[WIDTH-1:LSB] >= BEGIN_ADDRESS) && + (i_address[WIDTH-1:LSB] <= END_ADDRESS ); + end + else if ((BEGIN_ADDRESS == '0) && (END_ADDRESS != '1)) begin : g_address_matcher + assign address_match = i_address[WIDTH-1:LSB] <= END_ADDRESS; + end + else if ((BEGIN_ADDRESS != '0) && (END_ADDRESS == '1)) begin : g_address_matcher + assign address_match = i_address[WIDTH-1:LSB] >= BEGIN_ADDRESS; + end + else begin : g_address_matcher + assign address_match = '1; + end + + if (READABLE && WRITABLE) begin : g_access_matcher + assign access_match = '1; + end + else if (READABLE) begin : g_access_matcher + assign access_match = (!i_access[RGGEN_ACCESS_DATA_BIT]); + end + else begin : g_access_matcher + assign access_match = i_access[RGGEN_ACCESS_DATA_BIT]; + end + endgenerate + + assign o_match = address_match && access_match && i_additional_match; +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv new file mode 100644 index 0000000000..38e9d1e226 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_adapter.sv @@ -0,0 +1,64 @@ +module rggen_apb_adapter + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 8, + parameter int LOCAL_ADDRESS_WIDTH = 8, + parameter int BUS_WIDTH = 32, + parameter int REGISTERS = 1, + parameter bit PRE_DECODE = 0, + parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, + parameter int BYTE_SIZE = 256, + parameter bit ERROR_STATUS = 0, + parameter bit [BUS_WIDTH-1:0] DEFAULT_READ_DATA = '0, + parameter bit INSERT_SLICER = 0 +)( + input logic i_clk, + input logic i_rst_n, + rggen_apb_if.slave apb_if, + rggen_register_if.host register_if[REGISTERS] +); + rggen_bus_if #(ADDRESS_WIDTH, BUS_WIDTH) bus_if(); + + assign bus_if.valid = (apb_if.psel && (!apb_if.pready)) ? '1 : '0; + assign bus_if.access = (apb_if.pwrite) ? RGGEN_WRITE : RGGEN_READ; + assign bus_if.address = apb_if.paddr[ADDRESS_WIDTH-1:0]; + assign bus_if.write_data = apb_if.pwdata; + assign bus_if.strobe = apb_if.pstrb; + + always_ff @(posedge i_clk , negedge i_rst_n) begin + if (!i_rst_n) begin + apb_if.pready <= '0; + end + else if (bus_if.valid && bus_if.ready) begin + apb_if.pready <= '1; + end + else begin + apb_if.pready <= '0; + end + end + + always_ff @(posedge i_clk) begin + if (bus_if.valid && bus_if.ready) begin + apb_if.prdata <= bus_if.read_data; + apb_if.pslverr <= bus_if.status[1]; + end + end + + rggen_adapter_common #( + .ADDRESS_WIDTH (ADDRESS_WIDTH ), + .LOCAL_ADDRESS_WIDTH (LOCAL_ADDRESS_WIDTH ), + .BUS_WIDTH (BUS_WIDTH ), + .REGISTERS (REGISTERS ), + .PRE_DECODE (PRE_DECODE ), + .BASE_ADDRESS (BASE_ADDRESS ), + .BYTE_SIZE (BYTE_SIZE ), + .ERROR_STATUS (ERROR_STATUS ), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA ), + .INSERT_SLICER (INSERT_SLICER ) + ) u_adapter_common ( + .i_clk (i_clk ), + .i_rst_n (i_rst_n ), + .bus_if (bus_if ), + .register_if (register_if ) + ); +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv new file mode 100644 index 0000000000..444106a986 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_bridge.sv @@ -0,0 +1,44 @@ +module rggen_apb_bridge + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 16 +)( + input logic i_clk, + input logic i_rst_n, + rggen_bus_if.slave bus_if, + rggen_apb_if.master apb_if +); +`ifndef SYNTHESIS + initial begin + assume (ADDRESS_WIDTH == apb_if.ADDRESS_WIDTH); + end +`endif + + logic busy; + + // Request + assign apb_if.psel = bus_if.valid; + assign apb_if.penable = (busy) ? bus_if.valid : '0; + assign apb_if.paddr = ADDRESS_WIDTH'(bus_if.address); + assign apb_if.pprot = '0; + assign apb_if.pwrite = bus_if.access[RGGEN_ACCESS_DATA_BIT]; + assign apb_if.pstrb = bus_if.strobe; + assign apb_if.pwdata = bus_if.write_data; + + // Response + assign bus_if.ready = (busy) ? apb_if.pready : '0; + assign bus_if.status = (apb_if.pslverr) ? RGGEN_SLAVE_ERROR : RGGEN_OKAY; + assign bus_if.read_data = apb_if.prdata; + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + busy <= '0; + end + else if (apb_if.penable && apb_if.pready) begin + busy <= '0; + end + else if (apb_if.psel) begin + busy <= '1; + end + end +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv new file mode 100644 index 0000000000..d079ab6336 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_apb_if.sv @@ -0,0 +1,54 @@ +interface rggen_apb_if #( + parameter int ADDRESS_WIDTH = 16, + parameter int BUS_WIDTH = 32 +); + logic psel; + logic penable; + logic [ADDRESS_WIDTH-1:0] paddr; + logic [2:0] pprot; + logic pwrite; + logic [BUS_WIDTH/8-1:0] pstrb; + logic [BUS_WIDTH-1:0] pwdata; + logic pready; + logic [BUS_WIDTH-1:0] prdata; + logic pslverr; + + modport master ( + output psel, + output penable, + output paddr, + output pprot, + output pwrite, + output pstrb, + output pwdata, + input pready, + input prdata, + input pslverr + ); + + modport slave ( + input psel, + input penable, + input paddr, + input pprot, + input pwrite, + input pstrb, + input pwdata, + output pready, + output prdata, + output pslverr + ); + + modport monitor ( + input psel, + input penable, + input paddr, + input pprot, + input pwrite, + input pstrb, + input pwdata, + input pready, + input prdata, + input pslverr + ); +endinterface diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_adapter.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_adapter.sv new file mode 100644 index 0000000000..2abafc8c7b --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_adapter.sv @@ -0,0 +1,189 @@ +module rggen_axi4lite_adapter + import rggen_rtl_pkg::*; +#( + parameter int ID_WIDTH = 0, + parameter int ADDRESS_WIDTH = 8, + parameter int LOCAL_ADDRESS_WIDTH = 8, + parameter int BUS_WIDTH = 32, + parameter int REGISTERS = 1, + parameter bit PRE_DECODE = 0, + parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, + parameter int BYTE_SIZE = 256, + parameter bit ERROR_STATUS = 0, + parameter bit [BUS_WIDTH-1:0] DEFAULT_READ_DATA = '0, + parameter bit INSERT_SLICER = 0, + parameter bit WRITE_FIRST = 1 +)( + input logic i_clk, + input logic i_rst_n, + rggen_axi4lite_if.slave axi4lite_if, + rggen_register_if.host register_if[REGISTERS] +); + rggen_axi4lite_if #(ID_WIDTH, ADDRESS_WIDTH, BUS_WIDTH) buffer_if(); + rggen_bus_if #(ADDRESS_WIDTH, BUS_WIDTH) bus_if(); + + // Input buffer + rggen_axi4lite_skid_buffer #( + .ID_WIDTH (ID_WIDTH ), + .ADDRESS_WIDTH (ADDRESS_WIDTH ), + .BUS_WIDTH (BUS_WIDTH ) + ) u_buffer ( + .i_clk (i_clk ), + .i_rst_n (i_rst_n ), + .slave_if (axi4lite_if ), + .master_if (buffer_if ) + ); + + logic [1:0] request_valid; + logic [1:0] request_valid_latched; + logic [1:0] response_valid; + logic response_ack; + logic [rggen_clip_width(ID_WIDTH)-1:0] id; + logic [BUS_WIDTH-1:0] read_data; + logic [1:0] status; + + // Request + always_comb begin + buffer_if.awready = bus_if.ready && request_valid[0] && (response_valid == '0); + buffer_if.wready = bus_if.ready && request_valid[0] && (response_valid == '0); + buffer_if.arready = bus_if.ready && request_valid[1] && (response_valid == '0); + end + + always_comb begin + bus_if.valid = (request_valid != '0) && (response_valid == '0); + if (request_valid[0]) begin + bus_if.access = RGGEN_WRITE; + bus_if.address = buffer_if.awaddr; + bus_if.write_data = buffer_if.wdata; + bus_if.strobe = buffer_if.wstrb; + end + else begin + bus_if.access = RGGEN_READ; + bus_if.address = buffer_if.araddr; + bus_if.write_data = buffer_if.wdata; + bus_if.strobe = buffer_if.wstrb; + end + end + + always_comb begin + if (request_valid_latched != '0) begin + request_valid = request_valid_latched; + end + else begin + request_valid = get_request_valid(buffer_if.awvalid, buffer_if.wvalid, buffer_if.arvalid); + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + request_valid_latched <= '0; + end + else if (bus_if.ready) begin + request_valid_latched <= '0; + end + else if (bus_if.valid) begin + request_valid_latched <= request_valid; + end + end + + function automatic logic [1:0] get_request_valid( + logic awvalid, + logic wvalid, + logic arvalid + ); + logic [1:0] valid; + + if (WRITE_FIRST) begin + valid[0] = awvalid && wvalid; + valid[1] = arvalid && (!valid[0]); + end + else begin + valid[0] = awvalid && wvalid && (!arvalid); + valid[1] = arvalid; + end + + return valid; + endfunction + + // Response + always_comb begin + buffer_if.bvalid = response_valid[0]; + buffer_if.bid = id; + buffer_if.bresp = status; + end + + always_comb begin + buffer_if.rvalid = response_valid[1]; + buffer_if.rid = id; + buffer_if.rresp = status; + buffer_if.rdata = read_data; + end + + always_comb begin + response_ack = + (buffer_if.bvalid && buffer_if.bready) || + (buffer_if.rvalid && buffer_if.rready); + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + response_valid <= 2'b00; + end + else if (response_ack) begin + response_valid <= 2'b00; + end + else if (bus_if.valid && bus_if.ready) begin + if (bus_if.access[RGGEN_ACCESS_DATA_BIT]) begin + response_valid <= 2'b01; + end + else begin + response_valid <= 2'b10; + end + end + end + + generate if (ID_WIDTH > 0) begin : g_id + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + id <= '0; + end + else if (buffer_if.awvalid && buffer_if.awready) begin + id <= buffer_if.awid; + end + else if (buffer_if.arvalid && buffer_if.arready) begin + id <= buffer_if.arid; + end + end + end + else begin : g_no_id + always_comb begin + id = '0; + end + end endgenerate + + always_ff @(posedge i_clk) begin + if (bus_if.valid && bus_if.ready) begin + status <= bus_if.status; + read_data <= bus_if.read_data; + end + end + + // Adapter common + rggen_adapter_common #( + .ADDRESS_WIDTH (ADDRESS_WIDTH ), + .LOCAL_ADDRESS_WIDTH (LOCAL_ADDRESS_WIDTH ), + .BUS_WIDTH (BUS_WIDTH ), + .REGISTERS (REGISTERS ), + .PRE_DECODE (PRE_DECODE ), + .BASE_ADDRESS (BASE_ADDRESS ), + .BYTE_SIZE (BYTE_SIZE ), + .ERROR_STATUS (ERROR_STATUS ), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA ), + .INSERT_SLICER (INSERT_SLICER ) + ) u_adapter_common ( + .i_clk (i_clk ), + .i_rst_n (i_rst_n ), + .bus_if (bus_if ), + .register_if (register_if ) + ); +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_bridge.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_bridge.sv new file mode 100644 index 0000000000..9de6fc8ef8 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_bridge.sv @@ -0,0 +1,65 @@ +module rggen_axi4lite_bridge + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 16 +)( + input logic i_clk, + input logic i_rst_n, + rggen_bus_if.slave bus_if, + rggen_axi4lite_if.master axi4lite_if +); +`ifndef SYNTHESIS + initial begin + assume (ADDRESS_WIDTH == axi4lite_if.ADDRESS_WIDTH); + end +`endif + + logic write_access; + logic [2:0] request_done; + + // Request + assign write_access = bus_if.access[RGGEN_ACCESS_DATA_BIT]; + assign axi4lite_if.awvalid = ((!request_done[0]) && write_access) ? bus_if.valid : '0; + assign axi4lite_if.awid = '0; + assign axi4lite_if.awaddr = ADDRESS_WIDTH'(bus_if.address); + assign axi4lite_if.awprot = '0; + assign axi4lite_if.wvalid = ((!request_done[1]) && write_access) ? bus_if.valid : '0; + assign axi4lite_if.wdata = bus_if.write_data; + assign axi4lite_if.wstrb = bus_if.strobe; + assign axi4lite_if.arvalid = (!(request_done[2] || write_access)) ? bus_if.valid : '0; + assign axi4lite_if.arid = '0; + assign axi4lite_if.araddr = ADDRESS_WIDTH'(bus_if.address); + assign axi4lite_if.arprot = '0; + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + request_done <= '0; + end + else if (bus_if.ready) begin + request_done <= '0; + end + else begin + if (axi4lite_if.awvalid && axi4lite_if.awready) begin + request_done[0] <= '1; + end + if (axi4lite_if.wvalid && axi4lite_if.wready) begin + request_done[1] <= '1; + end + if (axi4lite_if.arvalid && axi4lite_if.arready) begin + request_done[2] <= '1; + end + end + end + + // Response + assign axi4lite_if.bready = request_done[0] & request_done[1]; + assign axi4lite_if.rready = request_done[2]; + + assign bus_if.ready + = (request_done[0] && request_done[1]) ? axi4lite_if.bvalid + : (request_done[2] ) ? axi4lite_if.rvalid : '0; + assign bus_if.status + = (request_done[0] && request_done[1]) ? rggen_status'(axi4lite_if.bresp) + : (request_done[2] ) ? rggen_status'(axi4lite_if.rresp) : RGGEN_OKAY; + assign bus_if.read_data = axi4lite_if.rdata; +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_if.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_if.sv new file mode 100644 index 0000000000..9f6f08e3fb --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_if.sv @@ -0,0 +1,111 @@ +interface rggen_axi4lite_if + import rggen_rtl_pkg::*; +#( + parameter int ID_WIDTH = 0, + parameter int ADDRESS_WIDTH = 16, + parameter int BUS_WIDTH = 32 +); + localparam int ACTUAL_ID_WIDTH = rggen_clip_width(ID_WIDTH); + + logic awvalid; + logic awready; + logic [ACTUAL_ID_WIDTH-1:0] awid; + logic [ADDRESS_WIDTH-1:0] awaddr; + logic [2:0] awprot; + logic wvalid; + logic wready; + logic [BUS_WIDTH-1:0] wdata; + logic [BUS_WIDTH/8-1:0] wstrb; + logic bvalid; + logic bready; + logic [ACTUAL_ID_WIDTH-1:0] bid; + logic [1:0] bresp; + logic arvalid; + logic arready; + logic [ADDRESS_WIDTH-1:0] araddr; + logic [ACTUAL_ID_WIDTH-1:0] arid; + logic [2:0] arprot; + logic rvalid; + logic rready; + logic [ACTUAL_ID_WIDTH-1:0] rid; + logic [1:0] rresp; + logic [BUS_WIDTH-1:0] rdata; + + modport master ( + output awvalid, + input awready, + output awid, + output awaddr, + output awprot, + output wvalid, + input wready, + output wdata, + output wstrb, + input bvalid, + output bready, + input bid, + input bresp, + output arvalid, + input arready, + output arid, + output araddr, + output arprot, + input rvalid, + output rready, + input rid, + input rresp, + input rdata + ); + + modport slave ( + input awvalid, + output awready, + input awid, + input awaddr, + input awprot, + input wvalid, + output wready, + input wdata, + input wstrb, + output bvalid, + input bready, + output bid, + output bresp, + input arvalid, + output arready, + input arid, + input araddr, + input arprot, + output rvalid, + input rready, + output rid, + output rresp, + output rdata + ); + + modport monitor ( + input awvalid, + input awready, + input awid, + input awaddr, + input awprot, + input wvalid, + input wready, + input wdata, + input wstrb, + input bvalid, + input bready, + input bid, + input bresp, + input arvalid, + input arready, + input arid, + input araddr, + input arprot, + input rvalid, + input rready, + input rid, + input rresp, + input rdata + ); +endinterface diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_skid_buffer.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_skid_buffer.sv new file mode 100644 index 0000000000..c922156d58 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_axi4lite_skid_buffer.sv @@ -0,0 +1,175 @@ +module rggen_axi4lite_skid_buffer + import rggen_rtl_pkg::*; +#( + parameter int ID_WIDTH = 0, + parameter int ADDRESS_WIDTH = 8, + parameter int BUS_WIDTH = 32 +)( + input logic i_clk, + input logic i_rst_n, + rggen_axi4lite_if.slave slave_if, + rggen_axi4lite_if.master master_if +); + logic awvalid; + logic [rggen_clip_width(ID_WIDTH)-1:0] awid; + logic [ADDRESS_WIDTH-1:0] awaddr; + logic [2:0] awprot; + logic wvalid; + logic [BUS_WIDTH-1:0] wdata; + logic [BUS_WIDTH/8-1:0] wstrb; + logic arvalid; + logic arready; + logic [ADDRESS_WIDTH-1:0] araddr; + logic [rggen_clip_width(ID_WIDTH)-1:0] arid; + logic [2:0] arprot; + + // Write address channel + always_comb begin + slave_if.awready = !awvalid; + end + + always_comb begin + master_if.awvalid = slave_if.awvalid || awvalid; + end + + always_comb begin + if (awvalid) begin + master_if.awid = awid; + master_if.awaddr = awaddr; + master_if.awprot = awprot; + end + else begin + master_if.awid = slave_if.awid; + master_if.awaddr = ADDRESS_WIDTH'(slave_if.awaddr); + master_if.awprot = slave_if.awprot; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + awvalid <= '0; + end + else if (master_if.awvalid && master_if.awready) begin + awvalid <= '0; + end + else if (slave_if.awvalid && slave_if.awready) begin + awvalid <= '1; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + awid <= '0; + awaddr <= '0; + awprot <= '0; + end + else if (slave_if.awvalid && slave_if.awready) begin + awid <= slave_if.awid; + awaddr <= slave_if.awaddr; + awprot <= slave_if.awprot; + end + end + + // Write data channel + always_comb begin + slave_if.wready = !wvalid; + end + + always_comb begin + master_if.wvalid = slave_if.wvalid || wvalid; + end + + always_comb begin + if (wvalid) begin + master_if.wdata = wdata; + master_if.wstrb = wstrb; + end + else begin + master_if.wdata = slave_if.wdata; + master_if.wstrb = slave_if.wstrb; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + wvalid <= '0; + end + else if (master_if.wvalid && master_if.wready) begin + wvalid <= '0; + end + else if (slave_if.wvalid && slave_if.wready) begin + wvalid <= '1; + end + end + + always_ff @(posedge i_clk) begin + if (slave_if.wvalid && slave_if.wready) begin + wdata <= slave_if.wdata; + wstrb <= slave_if.wstrb; + end + end + + // Write response channel + always_comb begin + master_if.bready = slave_if.bready; + slave_if.bvalid = master_if.bvalid; + slave_if.bid = master_if.bid; + slave_if.bresp = master_if.bresp; + end + + // Read address channel + always_comb begin + slave_if.arready = !arvalid; + end + + always_comb begin + master_if.arvalid = slave_if.arvalid || arvalid; + end + + always_comb begin + if (arvalid) begin + master_if.arid = arid; + master_if.araddr = ADDRESS_WIDTH'(araddr); + master_if.arprot = arprot; + end + else begin + master_if.arid = slave_if.arid; + master_if.araddr = slave_if.araddr; + master_if.arprot = slave_if.arprot; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + arvalid <= '0; + end + else if (master_if.arvalid && master_if.arready) begin + arvalid <= '0; + end + else if (slave_if.arvalid && slave_if.arready) begin + arvalid <= '1; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + arid <= '0; + araddr <= '0; + arprot <= '0; + end + else if (slave_if.arvalid && slave_if.arready) begin + arid <= slave_if.arid; + araddr <= slave_if.araddr; + arprot <= slave_if.arprot; + end + end + + // Read response channel + always_comb begin + master_if.rready = slave_if.rready; + slave_if.rvalid = master_if.rvalid; + slave_if.rid = master_if.rid; + slave_if.rresp = master_if.rresp; + slave_if.rdata = master_if.rdata; + end +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor.sv new file mode 100644 index 0000000000..cae70c1adf --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor.sv @@ -0,0 +1,44 @@ +`ifdef RGGEN_ENABLE_BACKDOOR +module rggen_backdoor #( + parameter int DATA_WIDTH = 32 +)( + input logic i_clk, + input logic i_rst_n, + input logic i_frontdoor_valid, + input logic i_frontdoor_ready, + output logic o_backdoor_valid, + output logic o_pending_valid, + output logic [DATA_WIDTH-1:0] o_read_mask, + output logic [DATA_WIDTH-1:0] o_write_mask, + output logic [DATA_WIDTH-1:0] o_write_data, + input logic [DATA_WIDTH-1:0] i_read_data, + input logic [DATA_WIDTH-1:0] i_value +); + rggen_backdoor_if backdoor_if(i_clk, i_rst_n); + logic pending_valid; + + assign o_backdoor_valid = backdoor_if.valid; + assign o_pending_valid = pending_valid; + assign o_read_mask = backdoor_if.read_mask; + assign o_write_mask = backdoor_if.write_mask; + assign o_write_data = backdoor_if.write_data; + assign backdoor_if.read_data = i_read_data; + assign backdoor_if.value = i_value; + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + pending_valid <= '0; + end + else if (i_frontdoor_ready) begin + pending_valid <= '0; + end + else if (backdoor_if.valid && i_frontdoor_valid) begin + pending_valid <= '1; + end + end + + initial begin + rggen_backdoor_pkg::set_backdoor_vif($sformatf("%m"), backdoor_if); + end +endmodule +`endif diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_if.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_if.sv new file mode 100644 index 0000000000..566012aefd --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_if.sv @@ -0,0 +1,103 @@ +`ifndef RGGEN_BACKDOOR_IF_SV +`define RGGEN_BACKDOOR_IF_SV + +`ifdef RGGEN_ENABLE_BACKDOOR + +`ifndef RGGEN_BACKDOOR_DATA_WIDTH + `ifdef UVM_REG_DATA_WIDTH + `define RGGEN_BACKDOOR_DATA_WIDTH `UVM_REG_DATA_WIDTH + `else + `define RGGEN_BACKDOOR_DATA_WIDTH 64 + `endif +`endif + +interface rggen_backdoor_if( + input logic i_clk, + input logic i_rst_n +); + typedef bit [`RGGEN_BACKDOOR_DATA_WIDTH-1:0] rggen_backdoor_data; + + bit valid; + rggen_backdoor_data read_mask; + rggen_backdoor_data write_mask; + rggen_backdoor_data write_data; + rggen_backdoor_data read_data; + rggen_backdoor_data value; + + clocking backdoor_cb @(posedge i_clk); + output valid; + output read_mask; + output write_mask; + output write_data; + input read_data; + input value; + endclocking + + event at_clock_edge; + always @(backdoor_cb) begin + ->at_clock_edge; + end + + semaphore backdoor_access_lock; + initial begin + backdoor_access_lock = new(1); + end + + task automatic backdoor_read( + input rggen_backdoor_data mask, + ref rggen_backdoor_data data + ); + backdoor_access(0, mask, data); + endtask + + task automatic backdoor_write( + rggen_backdoor_data mask, + rggen_backdoor_data data + ); + backdoor_access(1, mask, data); + endtask + + task automatic backdoor_access( + input bit write, + input rggen_backdoor_data mask, + ref rggen_backdoor_data data + ); + backdoor_access_lock.get(1); + + if (!at_clock_edge.triggered) begin + @(backdoor_cb); + end + + backdoor_cb.valid <= '1; + if (write) begin + backdoor_cb.read_mask <= '0; + backdoor_cb.write_mask <= mask; + backdoor_cb.write_data <= data; + end + else begin + data = get_read_data(); + backdoor_cb.read_mask <= mask; + backdoor_cb.write_mask <= '0; + end + + @(backdoor_cb); + backdoor_cb.valid <= '0; + + backdoor_access_lock.put(1); + endtask + + function automatic rggen_backdoor_data get_read_data(); + return backdoor_cb.read_data; + endfunction + + function automatic rggen_backdoor_data get_value(); + return backdoor_cb.value; + endfunction + + task automatic wait_for_change(); + @(backdoor_cb.read_data); + endtask +endinterface +`endif + +`endif diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_pkg.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_pkg.sv new file mode 100644 index 0000000000..dce0576330 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_backdoor_pkg.sv @@ -0,0 +1,78 @@ +`ifndef RGGEN_BACKDOOR_PKG_SV +`define RGGEN_BACKDOOR_PKG_SV + +`ifdef RGGEN_ENABLE_BACKDOOR +package rggen_backdoor_pkg; + typedef virtual rggen_backdoor_if rggen_backdoor_vif; + + class rggen_backdoor_if_store; +`ifndef XILINX_SIMULATOR + protected rggen_backdoor_vif vif[string]; + + function void set(string hdl_path, rggen_backdoor_vif vif); + string path; + path = normalize_hdl_path(hdl_path); + this.vif[path] = vif; + endfunction + + function rggen_backdoor_vif get(string hdl_path); + return vif[hdl_path]; + endfunction +`else + class rggen_backdoor_if_wrapper; + rggen_backdoor_vif vif; + function new(rggen_backdoor_vif vif); + this.vif = vif; + endfunction + endclass + + protected rggen_backdoor_if_wrapper vif_wrapper[string]; + + function void set(string hdl_path, rggen_backdoor_vif vif); + string path; + path = normalize_hdl_path(hdl_path); + this.vif_wrapper[path] = new(vif); + endfunction + + function rggen_backdoor_vif get(string hdl_path); + return vif_wrapper[hdl_path].vif; + endfunction +`endif + protected function string normalize_hdl_path(string path); + string normalized_path; + for (int i = 0;i < path.len();++i) begin + if ((path[i] != "\\") && (path[i] != " ")) begin + normalized_path = {normalized_path, path[i]}; + end + end + return normalized_path.tolower(); + endfunction + + static protected rggen_backdoor_if_store store; + + static function rggen_backdoor_if_store get_store(); + if (store == null) begin + store = new; + end + return store; + endfunction + endclass + + function automatic void set_backdoor_vif( + string hdl_path, + rggen_backdoor_vif vif + ); + rggen_backdoor_if_store store; + store = rggen_backdoor_if_store::get_store(); + store.set(hdl_path, vif); + endfunction + + function automatic rggen_backdoor_vif get_backdoor_vif(string hdl_path); + rggen_backdoor_if_store store; + store = rggen_backdoor_if_store::get_store(); + return store.get(hdl_path); + endfunction +endpackage +`endif + +`endif diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv new file mode 100644 index 0000000000..e537291245 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field.sv @@ -0,0 +1,279 @@ +module rggen_bit_field + import rggen_rtl_pkg::*; +#( + parameter int WIDTH = 8, + parameter bit [WIDTH-1:0] INITIAL_VALUE = '0, + parameter rggen_sw_hw_access PRECEDENCE_ACCESS = RGGEN_HW_ACCESS, + parameter rggen_sw_action SW_READ_ACTION = RGGEN_READ_DEFAULT, + parameter rggen_sw_action SW_WRITE_ACTION = RGGEN_WRITE_DEFAULT, + parameter bit SW_WRITE_ONCE = '0, + parameter rggen_polarity SW_WRITE_ENABLE_POLARITY = RGGEN_ACTIVE_HIGH, + parameter rggen_polarity HW_WRITE_ENABLE_POLARITY = RGGEN_ACTIVE_HIGH, + parameter int HW_SET_WIDTH = WIDTH, + parameter int HW_CLEAR_WIDTH = WIDTH, + parameter bit STORAGE = '1, + parameter bit EXTERNAL_READ_DATA = '0, + parameter bit TRIGGER = '0 +)( + input logic i_clk, + input logic i_rst_n, + rggen_bit_field_if.bit_field bit_field_if, + output logic o_write_trigger, + output logic o_read_trigger, + input logic i_sw_write_enable, + input logic i_hw_write_enable, + input logic [WIDTH-1:0] i_hw_write_data, + input logic [HW_SET_WIDTH-1:0] i_hw_set, + input logic [HW_CLEAR_WIDTH-1:0] i_hw_clear, + input logic [WIDTH-1:0] i_value, + input logic [WIDTH-1:0] i_mask, + output logic [WIDTH-1:0] o_value, + output logic [WIDTH-1:0] o_value_unmasked +); +//-------------------------------------------------------------- +// Utility functions +//-------------------------------------------------------------- + function automatic logic [1:0] get_sw_update( + logic valid, + logic [WIDTH-1:0] read_mask, + logic write_enable, + logic [WIDTH-1:0] write_mask, + logic write_done + ); + logic [1:0] action; + logic [1:0] access; + logic [1:0] update; + + action[0] = (SW_READ_ACTION == RGGEN_READ_CLEAR) || + (SW_READ_ACTION == RGGEN_READ_SET ); + action[1] = (SW_WRITE_ACTION != RGGEN_WRITE_NONE); + + access[0] = (read_mask != '0); + access[1] = (write_mask != '0) && (write_enable == SW_WRITE_ENABLE_POLARITY) && (!write_done); + + update[0] = valid && action[0] && access[0]; + update[1] = valid && action[1] && access[1]; + return update; + endfunction + + function automatic logic get_hw_update( + logic write_enable, + logic [HW_SET_WIDTH-1:0] set, + logic [HW_CLEAR_WIDTH-1:0] clear + ); + logic update; + update = (write_enable == HW_WRITE_ENABLE_POLARITY) || (set != '0) || (clear != '0); + return update; + endfunction + + function automatic logic [WIDTH-1:0] get_next_value( + logic [WIDTH-1:0] current_value, + logic [1:0] sw_update, + logic [WIDTH-1:0] sw_write_mask, + logic [WIDTH-1:0] sw_write_data, + logic hw_write_enable, + logic [WIDTH-1:0] hw_write_data, + logic [HW_SET_WIDTH-1:0] hw_set, + logic [HW_CLEAR_WIDTH-1:0] hw_clear + ); + logic [WIDTH-1:0] value; + + if (PRECEDENCE_ACCESS == RGGEN_SW_ACCESS) begin + value = + get_hw_next_value( + current_value, hw_write_enable, hw_write_data, + hw_set, hw_clear + ); + value = + get_sw_next_value( + value, sw_update, sw_write_mask, sw_write_data + ); + end + else begin + value = + get_sw_next_value( + current_value, sw_update, sw_write_mask, sw_write_data + ); + value = + get_hw_next_value( + value, hw_write_enable, hw_write_data, + hw_set, hw_clear + ); + end + + return value; + endfunction + + function automatic logic [WIDTH-1:0] get_sw_next_value( + logic [WIDTH-1:0] current_value, + logic [1:0] update, + logic [WIDTH-1:0] write_mask, + logic [WIDTH-1:0] write_data + ); + logic [WIDTH-1:0] value[2]; + logic [WIDTH-1:0] masked_data[2]; + + case (SW_READ_ACTION) + RGGEN_READ_CLEAR: value[0] = '0; + RGGEN_READ_SET: value[0] = '1; + default: value[0] = current_value; + endcase + + masked_data[0] = write_mask & (~write_data); + masked_data[1] = write_mask & ( write_data); + case (SW_WRITE_ACTION) + RGGEN_WRITE_DEFAULT: value[1] = (current_value & (~write_mask)) | masked_data[1]; + RGGEN_WRITE_0_CLEAR: value[1] = current_value & (~masked_data[0]); + RGGEN_WRITE_1_CLEAR: value[1] = current_value & (~masked_data[1]); + RGGEN_WRITE_CLEAR: value[1] = '0; + RGGEN_WRITE_0_SET: value[1] = current_value | masked_data[0]; + RGGEN_WRITE_1_SET: value[1] = current_value | masked_data[1]; + RGGEN_WRITE_SET: value[1] = '1; + RGGEN_WRITE_0_TOGGLE: value[1] = current_value ^ masked_data[0]; + RGGEN_WRITE_1_TOGGLE: value[1] = current_value ^ masked_data[1]; + default: value[1] = current_value; + endcase + + case (update) + 2'b01: return value[0]; + 2'b10: return value[1]; + default: return current_value; + endcase + endfunction + + function automatic logic [WIDTH-1:0] get_hw_next_value( + logic [WIDTH-1:0] current_value, + logic write_enable, + logic [WIDTH-1:0] write_data, + logic [HW_SET_WIDTH-1:0] set, + logic [HW_CLEAR_WIDTH-1:0] clear + ); + logic [WIDTH-1:0] set_clear[2]; + logic [WIDTH-1:0] value; + + if (HW_SET_WIDTH == WIDTH) begin + set_clear[0][HW_SET_WIDTH-1:0] = set; + end + else begin + set_clear[0] = {WIDTH{set[0]}}; + end + + if (HW_CLEAR_WIDTH == WIDTH) begin + set_clear[1][HW_CLEAR_WIDTH-1:0] = clear; + end + else begin + set_clear[1] = {WIDTH{clear[0]}}; + end + + if (write_enable == HW_WRITE_ENABLE_POLARITY) begin + value = write_data; + end + else begin + value = current_value; + end + + return (value & (~set_clear[1])) | set_clear[0];; + endfunction + +//-------------------------------------------------------------- +// Body +//-------------------------------------------------------------- + localparam bit SW_READABLE = SW_READ_ACTION != RGGEN_READ_NONE; + + logic [1:0] sw_update; + logic sw_write_done; + logic hw_update; + logic [1:0] trigger; + logic [WIDTH-1:0] value; + logic [WIDTH-1:0] read_data; + + assign bit_field_if.read_data = read_data & i_mask; + assign bit_field_if.value = value; + assign o_write_trigger = trigger[0]; + assign o_read_trigger = trigger[1]; + assign o_value = value & i_mask; + assign o_value_unmasked = value; + + assign sw_update = + get_sw_update( + bit_field_if.valid, bit_field_if.read_mask, + i_sw_write_enable, bit_field_if.write_mask, sw_write_done + ); + assign hw_update = + get_hw_update( + i_hw_write_enable, i_hw_set, i_hw_clear + ); + + generate if (STORAGE && SW_WRITE_ONCE) begin : g_sw_write_done + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + sw_write_done <= '0; + end + else if (sw_update[1]) begin + sw_write_done <= '1; + end + end + end + else begin : g_sw_write_done + assign sw_write_done = '0; + end endgenerate + + generate if (TRIGGER && (SW_WRITE_ACTION != RGGEN_WRITE_NONE)) begin : g_write_trigger + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + trigger[0] <= '0; + end + else begin + trigger[0] <= sw_update[1]; + end + end + end + else begin : g_write_trigger + assign trigger[0] = '0; + end endgenerate + + generate if (TRIGGER && (SW_READ_ACTION != RGGEN_READ_NONE)) begin : g_read_trigger + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + trigger[1] <= '0; + end + else begin + trigger[1] <= bit_field_if.valid && (bit_field_if.read_mask != '0); + end + end + end + else begin : g_read_trigger + assign trigger[1] = '0; + end endgenerate + + generate if (STORAGE) begin : g_value + logic [WIDTH-1:0] value_next; + + assign value_next = + get_next_value( + value, sw_update, bit_field_if.write_mask, bit_field_if.write_data, + i_hw_write_enable, i_hw_write_data, i_hw_set, i_hw_clear + ); + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + value <= INITIAL_VALUE; + end + else if (sw_update[0] || sw_update[1] || hw_update) begin + value <= value_next; + end + end + end + else begin : g_value + assign value = i_value; + end endgenerate + + generate if (!SW_READABLE) begin : g_read_data + assign read_data = '0; + end + else if (EXTERNAL_READ_DATA) begin : g_read_data + assign read_data = i_value; + end + else begin : g_read_data + assign read_data = value; + end endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv new file mode 100644 index 0000000000..705b53a428 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_if.sv @@ -0,0 +1,37 @@ +interface rggen_bit_field_if #( + parameter int WIDTH = 32 +); + logic valid; + logic [WIDTH-1:0] read_mask; + logic [WIDTH-1:0] write_mask; + logic [WIDTH-1:0] write_data; + logic [WIDTH-1:0] read_data; + logic [WIDTH-1:0] value; + + modport register ( + output valid, + output read_mask, + output write_mask, + output write_data, + input read_data, + input value + ); + + modport bit_field ( + input valid, + input read_mask, + input write_mask, + input write_data, + output read_data, + output value + ); + + modport monitor ( + input valid, + input read_mask, + input write_mask, + input write_data, + input read_data, + input value + ); +endinterface diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv new file mode 100644 index 0000000000..1df24dd002 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_bit_field_w01trg.sv @@ -0,0 +1,42 @@ +module rggen_bit_field_w01trg #( + parameter bit TRIGGER_VALUE = '0, + parameter int WIDTH = 1 +)( + input logic i_clk, + input logic i_rst_n, + rggen_bit_field_if.bit_field bit_field_if, + input logic [WIDTH-1:0] i_value, + output logic [WIDTH-1:0] o_trigger +); + logic [WIDTH-1:0] trigger; + + assign bit_field_if.read_data = i_value; + assign bit_field_if.value = trigger; + assign o_trigger = trigger; + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + trigger <= '0; + end + else if (bit_field_if.valid) begin + trigger <= get_trigger( + bit_field_if.write_mask, bit_field_if.write_data + ); + end + else if (trigger != '0) begin + trigger <= '0; + end + end + + function automatic logic [WIDTH-1:0] get_trigger( + logic [WIDTH-1:0] mask, + logic [WIDTH-1:0] write_data + ); + if (TRIGGER_VALUE) begin + return mask & write_data; + end + else begin + return mask & (~write_data); + end + endfunction +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv new file mode 100644 index 0000000000..1e4a4c0dd8 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_bus_if.sv @@ -0,0 +1,48 @@ +interface rggen_bus_if #( + parameter int ADDRESS_WIDTH = 16, + parameter int BUS_WIDTH = 32 +); + import rggen_rtl_pkg::*; + + logic valid; + rggen_access access; + logic [ADDRESS_WIDTH-1:0] address; + logic [BUS_WIDTH-1:0] write_data; + logic [BUS_WIDTH/8-1:0] strobe; + logic ready; + rggen_status status; + logic [BUS_WIDTH-1:0] read_data; + + modport master ( + output valid, + output access, + output address, + output write_data, + output strobe, + input ready, + input status, + input read_data + ); + + modport slave ( + input valid, + input access, + input address, + input write_data, + input strobe, + output ready, + output status, + output read_data + ); + + modport monitor ( + input valid, + input access, + input address, + input write_data, + input strobe, + input ready, + input status, + input read_data + ); +endinterface diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv new file mode 100644 index 0000000000..8e383a4f88 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_default_register.sv @@ -0,0 +1,30 @@ +module rggen_default_register #( + parameter bit READABLE = 1, + parameter bit WRITABLE = 1, + parameter int ADDRESS_WIDTH = 8, + parameter bit [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = '0, + parameter int BUS_WIDTH = 32, + parameter int DATA_WIDTH = BUS_WIDTH, + parameter int VALUE_WIDTH = BUS_WIDTH +)( + input logic i_clk, + input logic i_rst_n, + rggen_register_if.register register_if, + rggen_bit_field_if.register bit_field_if +); + rggen_register_common #( + .READABLE (READABLE ), + .WRITABLE (WRITABLE ), + .ADDRESS_WIDTH (ADDRESS_WIDTH ), + .OFFSET_ADDRESS (OFFSET_ADDRESS ), + .BUS_WIDTH (BUS_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ), + .VALUE_WIDTH (VALUE_WIDTH ) + ) u_register_common ( + .i_clk (i_clk ), + .i_rst_n (i_rst_n ), + .register_if (register_if ), + .i_additional_match (1'b1 ), + .bit_field_if (bit_field_if ) + ); +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv new file mode 100644 index 0000000000..8eec5e03b2 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_external_register.sv @@ -0,0 +1,74 @@ +module rggen_external_register + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 8, + parameter int BUS_WIDTH = 32, + parameter int VALUE_WIDTH = BUS_WIDTH, + parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0, + parameter int BYTE_SIZE = 0 +)( + input logic i_clk, + input logic i_rst_n, + rggen_register_if.register register_if, + rggen_bus_if.master bus_if +); + // Decode address + logic match; + rggen_address_decoder #( + .READABLE (1'b1 ), + .WRITABLE (1'b1 ), + .WIDTH (ADDRESS_WIDTH ), + .BUS_WIDTH (BUS_WIDTH ), + .START_ADDRESS (START_ADDRESS ), + .BYTE_SIZE (BYTE_SIZE ) + ) u_decoder ( + .i_address (register_if.address ), + .i_access (register_if.access ), + .i_additional_match (1'b1 ), + .o_match (match ) + ); + + // Request + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + bus_if.valid <= '0; + end + else if (bus_if.valid && bus_if.ready) begin + bus_if.valid <= '0; + end + else if (register_if.valid && match) begin + bus_if.valid <= '1; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + bus_if.address <= '0; + bus_if.access <= RGGEN_READ; + end + else if (register_if.valid && match) begin + bus_if.address <= get_bus_address(register_if.address); + bus_if.access <= register_if.access; + end + end + + function automatic logic [ADDRESS_WIDTH-1:0] get_bus_address( + logic [ADDRESS_WIDTH-1:0] address + ); + return address - START_ADDRESS; + endfunction + + always_ff @(posedge i_clk) begin + if (register_if.valid && match) begin + bus_if.write_data <= register_if.write_data; + bus_if.strobe <= register_if.strobe; + end + end + + // Response + assign register_if.active = match; + assign register_if.ready = (bus_if.valid) ? bus_if.ready : '0; + assign register_if.status = bus_if.status; + assign register_if.read_data = bus_if.read_data; + assign register_if.value = VALUE_WIDTH'(bus_if.read_data); +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv new file mode 100644 index 0000000000..afa36687a6 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_indirect_register.sv @@ -0,0 +1,36 @@ +module rggen_indirect_register #( + parameter bit READABLE = 1, + parameter bit WRITABLE = 1, + parameter int ADDRESS_WIDTH = 8, + parameter bit [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = '0, + parameter int BUS_WIDTH = 32, + parameter int DATA_WIDTH = BUS_WIDTH, + parameter int VALUE_WIDTH = BUS_WIDTH, + parameter int INDIRECT_INDEX_WIDTH = 1, + parameter bit [INDIRECT_INDEX_WIDTH-1:0] INDIRECT_INDEX_VALUE = '0 +)( + input logic i_clk, + input logic i_rst_n, + rggen_register_if.register register_if, + input logic [INDIRECT_INDEX_WIDTH-1:0] i_indirect_index, + rggen_bit_field_if.register bit_field_if +); + logic index_matched; + + assign index_matched = (i_indirect_index == INDIRECT_INDEX_VALUE) ? '1 : '0; + rggen_register_common #( + .READABLE (READABLE ), + .WRITABLE (WRITABLE ), + .ADDRESS_WIDTH (ADDRESS_WIDTH ), + .OFFSET_ADDRESS (OFFSET_ADDRESS ), + .BUS_WIDTH (BUS_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ), + .VALUE_WIDTH (VALUE_WIDTH ) + ) u_register_common ( + .i_clk (i_clk ), + .i_rst_n (i_rst_n ), + .register_if (register_if ), + .i_additional_match (index_matched ), + .bit_field_if (bit_field_if ) + ); +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv new file mode 100644 index 0000000000..0c4fe64898 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_mux.sv @@ -0,0 +1,33 @@ +module rggen_mux #( + parameter int WIDTH = 2, + parameter int ENTRIES = 2 +)( + input logic [ENTRIES-1:0] i_select, + input logic [ENTRIES-1:0][WIDTH-1:0] i_data, + output logic [WIDTH-1:0] o_data +); + generate + if (ENTRIES >= 2) begin : g + logic [ENTRIES-1:0][WIDTH-1:0] masked_data; + + always_comb begin + for (int i = 0;i < ENTRIES;++i) begin + masked_data[i] = i_data[i] & {WIDTH{i_select[i]}}; + end + end + + rggen_or_reducer #( + .WIDTH (WIDTH ), + .N (ENTRIES ) + ) u_reducer ( + .i_data (masked_data ), + .o_result (o_data ) + ); + end + else begin : g + always_comb begin + o_data = i_data[0]; + end + end + endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv new file mode 100644 index 0000000000..4ba2a708c4 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_or_reducer.sv @@ -0,0 +1,103 @@ +module rggen_or_reducer #( + parameter int WIDTH = 2, + parameter int N = 1 +)( + input logic [N-1:0][WIDTH-1:0] i_data, + output logic [WIDTH-1:0] o_result +); + function automatic bit [N-1:0][15:0] get_sub_n_list(int n); + bit [N-1:0][15:0] list; + int list_index; + bit [15:0] current_n; + bit [15:0] half_n; + + list = '0; + list_index = 0; + current_n = 16'(n); + while (current_n > 0) begin + half_n = current_n / 2; + if ((current_n > 4) && (half_n <= 4)) begin + list[list_index] = half_n; + end + else if (current_n >= 4) begin + list[list_index] = 4; + end + else begin + list[list_index] = current_n; + end + + current_n -= list[list_index]; + list_index += 1; + end + + return list; + endfunction + + function automatic bit [N-1:0][15:0] get_offset_list(bit [N-1:0][15:0] sub_n_list); + bit [N-1:0][15:0] list; + + for (int i = 0;i < N;++i) begin + if (i == 0) begin + list[i] = 0; + end + else begin + list[i] = sub_n_list[i-1] + list[i-1]; + end + end + + return list; + endfunction + + function automatic int get_next_n(bit [N-1:0][15:0] sub_n_list); + int next_n; + + next_n = 0; + for (int i = 0;i < N;++i) begin + next_n += ((sub_n_list[i] != 0) ? 1 : 0); + end + + return next_n; + endfunction + + localparam bit [N-1:0][15:0] SUB_N_LIST = get_sub_n_list(N); + localparam bit [N-1:0][15:0] OFFSET_LIST = get_offset_list(SUB_N_LIST); + localparam int NEXT_N = get_next_n(SUB_N_LIST); + + logic [NEXT_N-1:0][WIDTH-1:0] next_data; + + always_comb begin + for (int i = 0;i < NEXT_N;++i) begin + if (SUB_N_LIST[i] == 4) begin + next_data[i] = (i_data[OFFSET_LIST[i]+0] | i_data[OFFSET_LIST[i]+1]) | + (i_data[OFFSET_LIST[i]+2] | i_data[OFFSET_LIST[i]+3]); + end + else if (SUB_N_LIST[i] == 3) begin + next_data[i] = i_data[OFFSET_LIST[i]+0] | i_data[OFFSET_LIST[i]+1] | + i_data[OFFSET_LIST[i]+2]; + end + else if (SUB_N_LIST[i] == 2) begin + next_data[i] = i_data[OFFSET_LIST[i]+0] | i_data[OFFSET_LIST[i]+1]; + end + else begin + next_data[i] = i_data[OFFSET_LIST[i]+0]; + end + end + end + + generate + if (NEXT_N > 1) begin : g_reduce + rggen_or_reducer #( + .WIDTH (WIDTH ), + .N (NEXT_N ) + ) u_reducer ( + .i_data (next_data ), + .o_result (o_result ) + ); + end + else begin : g_reduce + always_comb begin + o_result = next_data[0]; + end + end + endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv new file mode 100644 index 0000000000..f7c27a2e05 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_register_common.sv @@ -0,0 +1,140 @@ +module rggen_register_common + import rggen_rtl_pkg::*; +#( + parameter bit READABLE = 1, + parameter bit WRITABLE = 1, + parameter int ADDRESS_WIDTH = 8, + parameter bit [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = '0, + parameter int BUS_WIDTH = 32, + parameter int DATA_WIDTH = BUS_WIDTH, + parameter int VALUE_WIDTH = BUS_WIDTH +)( + input logic i_clk, + input logic i_rst_n, + rggen_register_if.register register_if, + input logic i_additional_match, + rggen_bit_field_if.register bit_field_if +); + localparam int WORDS = DATA_WIDTH / BUS_WIDTH; + localparam int BUS_BYTE_WIDTH = BUS_WIDTH / 8; + localparam int DATA_BYTE_WIDTH = DATA_WIDTH / 8; + localparam int WORD_INDEX_WIDTH = (WORDS >= 2) ? $clog2(WORDS) : 1; + + genvar g; + + // Decode address + logic [WORDS-1:0] match; + logic active; + + assign active = match != '0; + + generate + for (g = 0;g < WORDS;++g) begin : g_decoder + localparam bit [ADDRESS_WIDTH-1:0] START_ADDRESS = OFFSET_ADDRESS + + ADDRESS_WIDTH'(BUS_BYTE_WIDTH * g); + + rggen_address_decoder #( + .READABLE (READABLE ), + .WRITABLE (WRITABLE ), + .WIDTH (ADDRESS_WIDTH ), + .BUS_WIDTH (BUS_WIDTH ), + .START_ADDRESS (START_ADDRESS ), + .BYTE_SIZE (BUS_BYTE_WIDTH ) + ) u_decoder ( + .i_address (register_if.address ), + .i_access (register_if.access ), + .i_additional_match (i_additional_match ), + .o_match (match[g] ) + ); + end + endgenerate + + // Request + logic frontdoor_valid; + logic backdoor_valid; + logic pending_valid; + logic [DATA_WIDTH-1:0] read_mask[2]; + logic [DATA_WIDTH-1:0] write_mask[2]; + logic [DATA_WIDTH-1:0] write_data[2]; + + assign bit_field_if.valid = frontdoor_valid || backdoor_valid || pending_valid; + assign bit_field_if.read_mask = (backdoor_valid) ? read_mask[1] : read_mask[0]; + assign bit_field_if.write_mask = (backdoor_valid) ? write_mask[1] : write_mask[0]; + assign bit_field_if.write_data = (backdoor_valid) ? write_data[1] : write_data[0]; + + assign frontdoor_valid = (active) ? register_if.valid : '0; + assign read_mask[0] = get_mask(1'b0, READABLE, match, register_if.access, {BUS_BYTE_WIDTH{1'b1}}); + assign write_mask[0] = get_mask(1'b1, WRITABLE, match, register_if.access, register_if.strobe ); + assign write_data[0] = (WRITABLE) ? {WORDS{register_if.write_data}} : '0; + + function automatic logic [DATA_WIDTH-1:0] get_mask( + logic write_access, + logic accessible, + logic [WORDS-1:0] match, + rggen_access access, + logic [BUS_BYTE_WIDTH-1:0] strobe + ); + logic [DATA_WIDTH-1:0] mask; + + for (int i = 0;i < WORDS;++i) begin + for (int j = 0;j < BUS_BYTE_WIDTH;++j) begin + mask[i*BUS_WIDTH+8*j+:8] = ( + accessible && (access[RGGEN_ACCESS_DATA_BIT] == write_access) && match[i] + ) ? {8{strobe[j]}} : '0; + end + end + + return mask; + endfunction + + // Response + logic [BUS_WIDTH-1:0] read_data; + + rggen_mux #( + .WIDTH (BUS_WIDTH ), + .ENTRIES (WORDS ) + ) u_read_data_mux ( + .i_select (match ), + .i_data (bit_field_if.read_data ), + .o_data (read_data ) + ); + + assign register_if.active = active; + assign register_if.ready = (!backdoor_valid) && active; + assign register_if.status = RGGEN_OKAY; + assign register_if.read_data = read_data; + assign register_if.value = VALUE_WIDTH'(bit_field_if.value); + +`ifdef RGGEN_ENABLE_BACKDOOR + // Backdoor access + rggen_backdoor #( + .DATA_WIDTH (DATA_WIDTH ) + ) u_backdoor ( + .i_clk (i_clk ), + .i_rst_n (i_rst_n ), + .i_frontdoor_valid (frontdoor_valid ), + .i_frontdoor_ready (register_if.ready ), + .o_backdoor_valid (backdoor_valid ), + .o_pending_valid (pending_valid ), + .o_read_mask (read_mask[1] ), + .o_write_mask (write_mask[1] ), + .o_write_data (write_data[1] ), + .i_read_data (bit_field_if.read_data ), + .i_value (bit_field_if.value ) + ); +`else + assign backdoor_valid = '0; + assign pending_valid = '0; + assign read_mask[1] = '0; + assign write_mask[1] = '0; + assign write_data[1] = '0; +`endif + +`ifdef RGGEN_ENABLE_SVA + ast_only_one_word_is_selected: + assert property ( + @(posedge i_clk) + (register_if.valid && (match != '0)) |-> $onehot(match) + ); +`endif +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv new file mode 100644 index 0000000000..0f8b154082 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_register_if.sv @@ -0,0 +1,56 @@ +interface rggen_register_if #( + parameter int ADDRESS_WIDTH = 16, + parameter int BUS_WIDTH = 32, + parameter int VALUE_WIDTH = BUS_WIDTH +); + import rggen_rtl_pkg::*; + + logic valid; + rggen_access access; + logic [ADDRESS_WIDTH-1:0] address; + logic [BUS_WIDTH-1:0] write_data; + logic [BUS_WIDTH/8-1:0] strobe; + logic ready; + rggen_status status; + logic [BUS_WIDTH-1:0] read_data; + logic active; + logic [VALUE_WIDTH-1:0] value; + + modport host ( + output valid, + output access, + output address, + output write_data, + output strobe, + input ready, + input status, + input read_data, + input active + ); + + modport register ( + input valid, + input access, + input address, + input write_data, + input strobe, + output ready, + output status, + output read_data, + output active, + output value + ); + + modport monitor ( + input valid, + input access, + input address, + input write_data, + input strobe, + input ready, + input status, + input read_data, + input active, + input value + ); +endinterface diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv new file mode 100644 index 0000000000..b04477f532 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_rtl_pkg.sv @@ -0,0 +1,48 @@ +package rggen_rtl_pkg; + typedef enum logic [1:0] { + RGGEN_READ = 2'b10, + RGGEN_POSTED_WRITE = 2'b01, + RGGEN_WRITE = 2'b11 + } rggen_access; + + localparam int RGGEN_ACCESS_DATA_BIT = 0; + localparam int RGGEN_ACCESS_NON_POSTED_BIT = 1; + + typedef enum logic [1:0] { + RGGEN_OKAY = 2'b00, + RGGEN_EXOKAY = 2'b01, + RGGEN_SLAVE_ERROR = 2'b10, + RGGEN_DECODE_ERROR = 2'b11 + } rggen_status; + + typedef enum logic { + RGGEN_SW_ACCESS, + RGGEN_HW_ACCESS + } rggen_sw_hw_access; + + typedef enum logic { + RGGEN_ACTIVE_LOW = 1'b0, + RGGEN_ACTIVE_HIGH = 1'b1 + } rggen_polarity; + + typedef enum logic [3:0] { + RGGEN_READ_NONE, + RGGEN_READ_DEFAULT, + RGGEN_READ_CLEAR, + RGGEN_READ_SET, + RGGEN_WRITE_NONE, + RGGEN_WRITE_DEFAULT, + RGGEN_WRITE_0_CLEAR, + RGGEN_WRITE_1_CLEAR, + RGGEN_WRITE_CLEAR, + RGGEN_WRITE_0_SET, + RGGEN_WRITE_1_SET, + RGGEN_WRITE_SET, + RGGEN_WRITE_0_TOGGLE, + RGGEN_WRITE_1_TOGGLE + } rggen_sw_action; + + function automatic int rggen_clip_width(int width); + return (width > 0) ? width : 1; + endfunction +endpackage diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_adapter.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_adapter.sv new file mode 100644 index 0000000000..4abaf3034b --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_adapter.sv @@ -0,0 +1,138 @@ +module rggen_wishbone_adapter + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 8, + parameter int LOCAL_ADDRESS_WIDTH = 8, + parameter int BUS_WIDTH = 32, + parameter int REGISTERS = 1, + parameter bit PRE_DECODE = 0, + parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, + parameter int BYTE_SIZE = 256, + parameter bit ERROR_STATUS = 0, + parameter bit [BUS_WIDTH-1:0] DEFAULT_READ_DATA = '0, + parameter bit INSERT_SLICER = 0, + parameter bit USE_STALL = '1 +)( + input logic i_clk, + input logic i_rst_n, + rggen_wishbone_if.slave wishbone_if, + rggen_register_if.host register_if[REGISTERS] +); + rggen_bus_if #(ADDRESS_WIDTH, BUS_WIDTH) bus_if(); + logic [1:0] request_valid; + logic [ADDRESS_WIDTH-1:0] wb_adr; + logic wb_we; + logic [BUS_WIDTH-1:0] wb_dat_w; + logic [BUS_WIDTH/8-1:0] wb_sel; + logic [1:0] response_valid; + logic [BUS_WIDTH-1:0] response_data; + + always_comb begin + wishbone_if.stall = request_valid[1]; + wishbone_if.ack = response_valid[0]; + wishbone_if.err = response_valid[1]; + wishbone_if.rty = '0; + wishbone_if.dat_r = response_data; + end + + always_comb begin + bus_if.valid = (request_valid != '0) && (response_valid == '0); + if (request_valid[1]) begin + bus_if.access = (wb_we) ? RGGEN_WRITE : RGGEN_READ; + bus_if.address = wb_adr; + bus_if.write_data = wb_dat_w; + bus_if.strobe = wb_sel; + end + else begin + bus_if.access = (wishbone_if.we) ? RGGEN_WRITE : RGGEN_READ; + bus_if.address = ADDRESS_WIDTH'(wishbone_if.adr); + bus_if.write_data = wishbone_if.dat_w; + bus_if.strobe = wishbone_if.sel; + end + end + + always_comb begin + request_valid[0] = wishbone_if.cyc && wishbone_if.stb; + end + + generate + if (USE_STALL) begin : g_stall + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + request_valid[1] <= '0; + end + else if (response_valid != '0) begin + request_valid[1] <= '0; + end + else if (request_valid == 2'b01) begin + request_valid[1] <= '1; + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + wb_adr <= '0; + wb_we <= '0; + wb_dat_w <= '0; + end + else if (request_valid == 2'b01) begin + wb_adr <= ADDRESS_WIDTH'(wishbone_if.adr); + wb_we <= wishbone_if.we; + wb_dat_w <= wishbone_if.dat_w; + end + end + end + else begin : g_no_stall + always_comb begin + request_valid[1] = '0; + wb_adr = '0; + wb_we = '0; + wb_dat_w = '0; + end + end + endgenerate + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + response_valid <= '0; + end + else if (response_valid != '0) begin + response_valid <= '0; + end + else if (bus_if.valid && bus_if.ready) begin + if (bus_if.status[1]) begin + response_valid <= 2'b10; + end + else begin + response_valid <= 2'b01; + end + end + end + + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + response_data <= '0; + end + else if (bus_if.valid && bus_if.ready) begin + response_data <= bus_if.read_data; + end + end + + rggen_adapter_common #( + .ADDRESS_WIDTH (ADDRESS_WIDTH ), + .LOCAL_ADDRESS_WIDTH (LOCAL_ADDRESS_WIDTH ), + .BUS_WIDTH (BUS_WIDTH ), + .REGISTERS (REGISTERS ), + .PRE_DECODE (PRE_DECODE ), + .BASE_ADDRESS (BASE_ADDRESS ), + .BYTE_SIZE (BYTE_SIZE ), + .ERROR_STATUS (ERROR_STATUS ), + .DEFAULT_READ_DATA (DEFAULT_READ_DATA ), + .INSERT_SLICER (INSERT_SLICER ) + ) u_adapter_common ( + .i_clk (i_clk ), + .i_rst_n (i_rst_n ), + .bus_if (bus_if ), + .register_if (register_if ) + ); +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_bridge.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_bridge.sv new file mode 100644 index 0000000000..2b0dbc53a9 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_bridge.sv @@ -0,0 +1,55 @@ +module rggen_wishbone_bridge + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 16, + parameter bit USE_STALL = '1 +)( + input var i_clk, + input var i_rst_n, + rggen_bus_if.slave bus_if, + rggen_wishbone_if.master wishbone_if +); +`ifndef SYNTHESIS + initial begin + assume (ADDRESS_WIDTH == wishbone_if.ADDRESS_WIDTH); + end +`endif + + logic request_done; + + always_comb begin + wishbone_if.cyc = bus_if.valid; + wishbone_if.stb = bus_if.valid && (!request_done); + wishbone_if.adr = ADDRESS_WIDTH'(bus_if.address); + wishbone_if.we = bus_if.access != RGGEN_READ; + wishbone_if.dat_w = bus_if.write_data; + wishbone_if.sel = bus_if.strobe; + end + + always_comb begin + bus_if.ready = wishbone_if.ack || wishbone_if.err || wishbone_if.rty; + bus_if.status = (wishbone_if.ack) ? RGGEN_OKAY : RGGEN_SLAVE_ERROR; + bus_if.read_data = wishbone_if.dat_r; + end + + generate + if (USE_STALL) begin : g_stall + always_ff @(posedge i_clk, negedge i_rst_n) begin + if (!i_rst_n) begin + request_done <= '0; + end + else if (bus_if.valid && bus_if.ready) begin + request_done <= '0; + end + else if (wishbone_if.stb && (!wishbone_if.stall)) begin + request_done <= '1; + end + end + end + else begin : g_no_stall + always_comb begin + request_done = '0; + end + end + endgenerate +endmodule diff --git a/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_if.sv b/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_if.sv new file mode 100644 index 0000000000..4f7a196779 --- /dev/null +++ b/third_party/tests/rggen/rggen-sv-rtl/rggen_wishbone_if.sv @@ -0,0 +1,46 @@ +interface rggen_wishbone_if + import rggen_rtl_pkg::*; +#( + parameter int ADDRESS_WIDTH = 16, + parameter int DATA_WIDTH = 32 +); + logic cyc; + logic stb; + logic stall; + logic [ADDRESS_WIDTH-1:0] adr; + logic we; + logic [DATA_WIDTH/8-1:0] sel; + logic ack; + logic err; + logic rty; + logic [DATA_WIDTH-1:0] dat_w; + logic [DATA_WIDTH-1:0] dat_r; + + modport master ( + output cyc, + output stb, + input stall, + output adr, + output we, + output dat_w, + output sel, + input ack, + input err, + input rty, + input dat_r + ); + + modport slave ( + input cyc, + input stb, + output stall, + input adr, + input we, + input dat_w, + input sel, + output ack, + output err, + output rty, + output dat_r + ); +endinterface diff --git a/third_party/tests/rggen/tests/generated/rggen/rggen.sv b/third_party/tests/rggen/tests/generated/rggen/rggen.sv new file mode 100644 index 0000000000..d184192ded --- /dev/null +++ b/third_party/tests/rggen/tests/generated/rggen/rggen.sv @@ -0,0 +1,292 @@ +/* +:name: RgGen +:description: Full RgGen test +:files: /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_rtl_pkg.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_or_reducer.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_mux.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_bit_field_if.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_bit_field.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_bit_field_w01trg.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_register_if.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_address_decoder.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_register_common.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_default_register.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_external_register.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_indirect_register.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_bus_if.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_adapter_common.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_apb_if.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_apb_adapter.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sv-rtl/rggen_apb_bridge.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sample/block_0.sv /home/alain/alain-marcel/sv-tests/third_party/cores/rggen-sample/block_1.sv /home/alain/alain-marcel/sv-tests/tests/generated/rggen/rggen.sv +:tags: RgGen +:top_module: rggen +:results_group: cores +:timeout: 100 +*/ + +module rggen; + import rggen_rtl_pkg::*; + + logic clk; + logic rst_n; + rggen_apb_if #(16, 32) apb_if[2](); + logic [3:0] register_0_bit_field_0; + logic [3:0] register_0_bit_field_1; + logic register_0_bit_field_2; + logic [1:0] register_0_bit_field_3; + logic [1:0] register_0_bit_field_4; + logic [1:0] register_0_bit_field_5; + logic [1:0] register_0_bit_field_6; + logic register_1; + logic [3:0] register_2_bit_field_0; + logic register_2_bit_field_2_latch; + logic [1:0][3:0] register_2_bit_field_2; + logic [1:0][3:0] register_2_bit_field_3; + logic [3:0] register_3_bit_field_0; + logic [3:0] register_3_bit_field_1; + logic [3:0] register_3_bit_field_2_trigger; + logic [3:0] register_3_bit_field_3_trigger; + logic [3:0] register_4_bit_field_0_set; + logic [3:0] register_4_bit_field_0; + logic [3:0] register_4_bit_field_1_set; + logic [3:0] register_4_bit_field_1; + logic [3:0] register_4_bit_field_1_unmasked; + logic [3:0] register_4_bit_field_3_clear; + logic [3:0] register_4_bit_field_3; + logic register_5_bit_field_0_clear; + logic [1:0] register_5_bit_field_0; + logic [1:0] register_5_bit_field_1; + logic register_5_bit_field_2_set; + logic [1:0] register_5_bit_field_2[2]; + logic [1:0] register_5_bit_field_3[2]; + logic register_5_bit_field_4_enable; + logic [1:0] register_5_bit_field_4; + logic [1:0] register_5_bit_field_5; + logic [1:0] register_5_bit_field_6; + logic register_5_bit_field_7_lock; + logic [1:0] register_5_bit_field_7; + logic [1:0] register_5_bit_field_8; + logic [1:0] register_5_bit_field_9; + logic [3:0] register_6_bit_field_0_set; + logic [3:0] register_6_bit_field_0; + logic [3:0] register_6_bit_field_1_set; + logic [3:0] register_6_bit_field_1; + logic [3:0] register_6_bit_field_1_unmasked; + logic [3:0] register_6_bit_field_3_set; + logic [3:0] register_6_bit_field_3; + logic [3:0] register_6_bit_field_4_set; + logic [3:0] register_6_bit_field_4; + logic [3:0] register_6_bit_field_4_unmasked; + logic [3:0] register_6_bit_field_6_clear; + logic [3:0] register_6_bit_field_6; + logic [3:0] register_6_bit_field_7_clear; + logic [3:0] register_6_bit_field_7; + logic [3:0] register_6_bit_field_8; + logic [3:0] register_6_bit_field_9; + logic [3:0] register_7_bit_field_0; + logic [3:0] register_7_bit_field_1; + logic [3:0] register_7_bit_field_2; + logic [3:0] register_7_bit_field_3; + logic [3:0] register_8_bit_field_0_set; + logic [3:0] register_8_bit_field_0; + logic [3:0] register_8_bit_field_1_clear; + logic [3:0] register_8_bit_field_1; + logic [3:0] register_8_bit_field_2_set; + logic [3:0] register_8_bit_field_2; + logic [3:0] register_8_bit_field_3_clear; + logic [3:0] register_8_bit_field_3; + logic [3:0] register_8_bit_field_4; + logic [3:0] register_8_bit_field_5; + logic [1:0] register_9_bit_field_0; + logic [1:0] register_9_bit_field_1; + logic [1:0] register_9_bit_field_2; + logic [1:0][1:0] register_9_bit_field_3; + logic [1:0] register_9_bit_field_4; + logic [1:0] register_9_bit_field_5; + logic [3:0][3:0][1:0] register_10_bit_field_0; + logic [3:0][3:0][1:0] register_10_bit_field_1; + logic [3:0][3:0][1:0] register_10_bit_field_2; + logic [1:0][3:0][3:0][7:0] register_11_bit_field_0; + logic [1:0][3:0][3:0][7:0] register_11_bit_field_1; + logic register_12_bit_field_0; + logic register_12_bit_field_1; + logic [1:0] register_13_bit_field_0; + logic [1:0] register_13_bit_field_1; + logic [1:0] register_13_bit_field_2; + logic [1:0] register_13_bit_field_3; + logic register_13_bit_field_3_write_trigger; + logic register_13_bit_field_3_read_trigger; + logic [1:0] register_13_bit_field_4; + logic [1:0] register_13_bit_field_5; + logic [1:0] register_13_bit_field_6; + logic [1:0] register_13_bit_field_6_hw_clear; + logic [1:0] register_13_bit_field_7; + logic [1:0] register_13_bit_field_7_hw_set; + logic [1:0] register_13_bit_field_8; + logic register_13_bit_field_8_hw_write_enable; + logic [1:0] register_13_bit_field_8_hw_write_data; + rggen_bus_if #(8, 32) register_15_bus_if(); + + always_comb begin + register_2_bit_field_0 = register_0_bit_field_0; + register_2_bit_field_2_latch = register_3_bit_field_3_trigger[0]; + register_2_bit_field_2[0] = register_0_bit_field_0; + register_2_bit_field_3[0] = register_0_bit_field_0; + register_4_bit_field_0_set = register_3_bit_field_3_trigger; + register_4_bit_field_1_set = register_3_bit_field_3_trigger; + register_4_bit_field_3_clear = register_3_bit_field_2_trigger; + register_5_bit_field_0_clear = register_3_bit_field_2_trigger[0]; + register_5_bit_field_2_set = register_3_bit_field_3_trigger[0]; + register_5_bit_field_2[0] = register_0_bit_field_0[1:0]; + register_5_bit_field_3[0] = register_0_bit_field_0[1:0]; + register_5_bit_field_4_enable = register_0_bit_field_2; + register_5_bit_field_7_lock = register_0_bit_field_2; + register_6_bit_field_0_set = register_3_bit_field_3_trigger; + register_6_bit_field_1_set = register_3_bit_field_3_trigger; + register_6_bit_field_3_set = register_3_bit_field_3_trigger; + register_6_bit_field_4_set = register_3_bit_field_3_trigger; + register_6_bit_field_6_clear = register_3_bit_field_2_trigger; + register_6_bit_field_7_clear = register_3_bit_field_2_trigger; + register_8_bit_field_0_set = register_3_bit_field_3_trigger; + register_8_bit_field_1_clear = register_3_bit_field_2_trigger; + register_8_bit_field_2_set = register_3_bit_field_3_trigger; + register_8_bit_field_3_clear = register_3_bit_field_2_trigger; + register_9_bit_field_1 = register_0_bit_field_0[1:0]; + register_9_bit_field_3[1] = register_0_bit_field_0[1:0]; + register_9_bit_field_4 = register_0_bit_field_0[1:0]; + register_9_bit_field_5 = register_0_bit_field_0[1:0]; + register_13_bit_field_1 = register_13_bit_field_0; + register_13_bit_field_6_hw_clear = register_13_bit_field_3_read_trigger; + register_13_bit_field_7_hw_set = register_13_bit_field_3_read_trigger; + register_13_bit_field_8_hw_write_enable = register_13_bit_field_3_write_trigger; + register_13_bit_field_8_hw_write_data = register_13_bit_field_3; + end + + block_0 #( + .ADDRESS_WIDTH (16 ), + .PRE_DECODE (1 ), + .INSERT_SLICER (1 ), + .BASE_ADDRESS (16'h1000 ), + .DEFAULT_READ_DATA (32'hDEAD_BEAF ), + .REGISTER_10_BIT_FIELD_1_INITIAL_VALUE ({2'h3, 2'h2, 2'h1, 2'h0} ) + ) u_block_0 ( + .i_clk (clk ), + .i_rst_n (rst_n ), + .apb_if (apb_if[0] ), + .o_register_0_bit_field_0 (register_0_bit_field_0 ), + .o_register_0_bit_field_1 (register_0_bit_field_1 ), + .o_register_0_bit_field_2 (register_0_bit_field_2 ), + .o_register_0_bit_field_3 (register_0_bit_field_3 ), + .o_register_0_bit_field_4 (register_0_bit_field_4 ), + .o_register_0_bit_field_5 (register_0_bit_field_5 ), + .o_register_0_bit_field_6 (register_0_bit_field_6 ), + .i_register_0_bit_field_6 (register_0_bit_field_6 ), + .o_register_1 (register_1 ), + .i_register_2_bit_field_0 (register_2_bit_field_0 ), + .i_register_2_bit_field_2_latch (register_2_bit_field_2_latch ), + .i_register_2_bit_field_2 (register_2_bit_field_2[0] ), + .o_register_2_bit_field_2 (register_2_bit_field_2[1] ), + .i_register_2_bit_field_3 (register_2_bit_field_3[0] ), + .o_register_2_bit_field_3 (register_2_bit_field_3[1] ), + .o_register_3_bit_field_0 (register_3_bit_field_0 ), + .o_register_3_bit_field_1 (register_3_bit_field_1 ), + .o_register_3_bit_field_2_trigger (register_3_bit_field_2_trigger ), + .o_register_3_bit_field_3_trigger (register_3_bit_field_3_trigger ), + .i_register_4_bit_field_0_set (register_4_bit_field_0_set ), + .o_register_4_bit_field_0 (register_4_bit_field_0 ), + .i_register_4_bit_field_1_set (register_4_bit_field_1_set ), + .o_register_4_bit_field_1 (register_4_bit_field_1 ), + .o_register_4_bit_field_1_unmasked (register_4_bit_field_1_unmasked ), + .i_register_4_bit_field_3_clear (register_4_bit_field_3_clear ), + .o_register_4_bit_field_3 (register_4_bit_field_3 ), + .i_register_5_bit_field_0_clear (register_5_bit_field_0_clear ), + .o_register_5_bit_field_0 (register_5_bit_field_0 ), + .o_register_5_bit_field_1 (register_5_bit_field_1 ), + .i_register_5_bit_field_2_set (register_5_bit_field_2_set ), + .i_register_5_bit_field_2 (register_5_bit_field_2[0] ), + .o_register_5_bit_field_2 (register_5_bit_field_2[1] ), + .i_register_5_bit_field_3 (register_5_bit_field_3[0] ), + .o_register_5_bit_field_3 (register_5_bit_field_3[1] ), + .i_register_5_bit_field_4_enable (register_5_bit_field_4_enable ), + .o_register_5_bit_field_4 (register_5_bit_field_4 ), + .o_register_5_bit_field_5 (register_5_bit_field_5 ), + .o_register_5_bit_field_6 (register_5_bit_field_6 ), + .i_register_5_bit_field_7_lock (register_5_bit_field_7_lock ), + .o_register_5_bit_field_7 (register_5_bit_field_7 ), + .o_register_5_bit_field_8 (register_5_bit_field_8 ), + .o_register_5_bit_field_9 (register_5_bit_field_9 ), + .i_register_6_bit_field_0_set (register_6_bit_field_0_set ), + .o_register_6_bit_field_0 (register_6_bit_field_0 ), + .i_register_6_bit_field_1_set (register_6_bit_field_1_set ), + .o_register_6_bit_field_1 (register_6_bit_field_1 ), + .o_register_6_bit_field_1_unmasked (register_6_bit_field_1_unmasked ), + .i_register_6_bit_field_3_set (register_6_bit_field_3_set ), + .o_register_6_bit_field_3 (register_6_bit_field_3 ), + .i_register_6_bit_field_4_set (register_6_bit_field_4_set ), + .o_register_6_bit_field_4 (register_6_bit_field_4 ), + .o_register_6_bit_field_4_unmasked (register_6_bit_field_4_unmasked ), + .i_register_6_bit_field_6_clear (register_6_bit_field_6_clear ), + .o_register_6_bit_field_6 (register_6_bit_field_6 ), + .i_register_6_bit_field_7_clear (register_6_bit_field_7_clear ), + .o_register_6_bit_field_7 (register_6_bit_field_7 ), + .o_register_6_bit_field_8 (register_6_bit_field_8 ), + .o_register_6_bit_field_9 (register_6_bit_field_9 ), + .o_register_7_bit_field_0 (register_7_bit_field_0 ), + .o_register_7_bit_field_1 (register_7_bit_field_1 ), + .o_register_7_bit_field_2 (register_7_bit_field_2 ), + .o_register_7_bit_field_3 (register_7_bit_field_3 ), + .i_register_8_bit_field_0_set (register_8_bit_field_0_set ), + .o_register_8_bit_field_0 (register_8_bit_field_0 ), + .i_register_8_bit_field_1_clear (register_8_bit_field_1_clear ), + .o_register_8_bit_field_1 (register_8_bit_field_1 ), + .i_register_8_bit_field_2_set (register_8_bit_field_2_set ), + .o_register_8_bit_field_2 (register_8_bit_field_2 ), + .i_register_8_bit_field_3_clear (register_8_bit_field_3_clear ), + .o_register_8_bit_field_3 (register_8_bit_field_3 ), + .o_register_8_bit_field_4 (register_8_bit_field_4 ), + .o_register_8_bit_field_5 (register_8_bit_field_5 ), + .o_register_9_bit_field_0 (register_9_bit_field_0 ), + .o_register_9_bit_field_0_write_trigger (), + .o_register_9_bit_field_0_read_trigger (), + .i_register_9_bit_field_1 (register_9_bit_field_1 ), + .o_register_9_bit_field_1_read_trigger (), + .o_register_9_bit_field_2 (register_9_bit_field_2 ), + .o_register_9_bit_field_2_write_trigger (), + .o_register_9_bit_field_3 (register_9_bit_field_3[0] ), + .i_register_9_bit_field_3 (register_9_bit_field_3[1] ), + .o_register_9_bit_field_3_write_trigger (), + .o_register_9_bit_field_3_read_trigger (), + .i_register_9_bit_field_4 (register_9_bit_field_4 ), + .o_register_9_bit_field_4_trigger (), + .i_register_9_bit_field_5 (register_9_bit_field_5 ), + .o_register_9_bit_field_5_trigger (), + .o_register_10_bit_field_0 (register_10_bit_field_0 ), + .o_register_10_bit_field_1 (register_10_bit_field_1 ), + .o_register_10_bit_field_2 (register_10_bit_field_2 ), + .o_register_11_bit_field_0 (register_11_bit_field_0 ), + .o_register_11_bit_field_1 (register_11_bit_field_1 ), + .o_register_12_bit_field_0 (register_12_bit_field_0 ), + .o_register_12_bit_field_1 (register_12_bit_field_1 ), + .o_register_13_bit_field_0 (register_13_bit_field_0 ), + .i_register_13_bit_field_1 (register_13_bit_field_1 ), + .o_register_13_bit_field_2 (register_13_bit_field_2 ), + .o_register_13_bit_field_3 (register_13_bit_field_3 ), + .o_register_13_bit_field_3_write_trigger (register_13_bit_field_3_write_trigger ), + .o_register_13_bit_field_3_read_trigger (register_13_bit_field_3_read_trigger ), + .o_register_13_bit_field_4 (register_13_bit_field_4 ), + .o_register_13_bit_field_5 (register_13_bit_field_5 ), + .o_register_13_bit_field_6 (register_13_bit_field_6 ), + .i_register_13_bit_field_6_hw_clear (register_13_bit_field_6_hw_clear ), + .o_register_13_bit_field_7 (register_13_bit_field_7 ), + .i_register_13_bit_field_7_hw_set (register_13_bit_field_7_hw_set ), + .o_register_13_bit_field_8 (register_13_bit_field_8 ), + .i_register_13_bit_field_8_hw_write_enable (register_13_bit_field_8_hw_write_enable ), + .i_register_13_bit_field_8_hw_write_data (register_13_bit_field_8_hw_write_data ), + .register_15_bus_if (register_15_bus_if ) + ); + + rggen_apb_bridge u_bridge ( + .i_clk (clk ), + .i_rst_n (rst_n ), + .bus_if (register_15_bus_if ), + .apb_if (apb_if[1] ) + ); + + block_1 u_block_1 ( + .i_clk (clk ), + .i_rst_n (rst_n ), + .apb_if (apb_if[1] ), + .o_register_file_0_register_0_bit_field_0 (), + .o_register_file_0_register_1_bit_field_0 (), + .o_register_file_1_register_0_bit_field_0 (), + .o_register_file_1_register_1_bit_field_0 (), + .o_register_file_2_register_file_0_register_0_bit_field_0 (), + .o_register_file_2_register_file_0_register_0_bit_field_1 (), + .o_register_file_2_register_file_0_register_0_bit_field_2 (), + .o_register_file_2_register_file_0_register_1_bit_field_0 () + ); +endmodule