From 71da5db81d469c3a25298d9db15b9ddff8d2efa1 Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Sun, 22 Sep 2024 11:42:12 -0700 Subject: [PATCH] Optional pp location in syntax error messages --- .../Surelog/CommandLine/CommandLineParser.h | 3 + .../SourceCompile/AntlrParserErrorListener.h | 6 +- src/CommandLine/CommandLineParser.cpp | 4 + .../AntlrParserErrorListener.cpp | 7 +- src/SourceCompile/ParseFile.cpp | 4 +- .../DiffSimpleIncludeAndMacros.log | 2 +- tests/ParamFile/ParamFileMacro.log | 2 +- tests/PreProcMacro/PreProcMacro.log | 24 +- tests/PreprocLine/PreprocLine.log | 2 +- .../SimpleIncludeAndMacros.log | 15 +- .../UnitSimpleIncludeAndMacros.log | 15 +- tests/TestMacros/TestMacros.log | 2 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 4 +- third_party/tests/Google/Google.log | 126 ++--- third_party/tests/Icarus/Icarus.log | 18 +- third_party/tests/UtdSV/UtdSV.log | 6 +- third_party/tests/Verilator/Verilator.log | 282 ++++++----- third_party/tests/Yosys/Yosys.log | 28 +- .../tests/YosysTestSuite/YosysTestSuite.log | 200 ++++---- third_party/tests/YosysTests/YosysTests.log | 440 +++++++++--------- third_party/tests/Zachjs/Zachjs.log | 78 ++-- 21 files changed, 622 insertions(+), 646 deletions(-) diff --git a/include/Surelog/CommandLine/CommandLineParser.h b/include/Surelog/CommandLine/CommandLineParser.h index 70b4c50ac3..52eb63d3e9 100644 --- a/include/Surelog/CommandLine/CommandLineParser.h +++ b/include/Surelog/CommandLine/CommandLineParser.h @@ -97,6 +97,8 @@ class CommandLineParser final { PathId getCacheDirId() const { return m_cacheDirId; } PathId getPrecompiledDirId() const { return m_precompiledDirId; } bool usePPOutputFileLocation() const { return m_ppOutputFileLocation; } + void printExtraPpLineInfo(bool on) { m_ppPrintLineInfo = on; } + bool printExtraPpLineInfo() { return m_ppPrintLineInfo; } /* PP Output content generation options */ bool filterFileLine() const { return m_filterFileLine; } void setFilterFileLine(bool val) { m_filterFileLine = val; } @@ -345,6 +347,7 @@ class CommandLineParser final { bool m_profile; bool m_parseBuiltIn; bool m_ppOutputFileLocation; + bool m_ppPrintLineInfo; PathId m_programId; std::string m_exeCommand; std::set> m_topLevelModules; diff --git a/include/Surelog/SourceCompile/AntlrParserErrorListener.h b/include/Surelog/SourceCompile/AntlrParserErrorListener.h index a482e31a0e..58fc447e8b 100644 --- a/include/Surelog/SourceCompile/AntlrParserErrorListener.h +++ b/include/Surelog/SourceCompile/AntlrParserErrorListener.h @@ -38,13 +38,14 @@ class ParseFile; class AntlrParserErrorListener : public antlr4::ANTLRErrorListener { public: AntlrParserErrorListener(ParseFile *parser, bool watchDogOn, - uint32_t lineOffset, PathId fileId) + uint32_t lineOffset, PathId fileId, bool printExtraPpLineInfo) : m_parser(parser), m_reportedSyntaxError(0), m_watchDogOn(watchDogOn), m_barked(false), m_lineOffset(lineOffset), - m_fileId(fileId) {} + m_fileId(fileId), + m_printExtraPpLineInfo(printExtraPpLineInfo) {} ~AntlrParserErrorListener() override{}; @@ -76,6 +77,7 @@ class AntlrParserErrorListener : public antlr4::ANTLRErrorListener { uint32_t m_lineOffset; PathId m_fileId; std::vector m_fileContent; + bool m_printExtraPpLineInfo; }; }; // namespace SURELOG diff --git a/src/CommandLine/CommandLineParser.cpp b/src/CommandLine/CommandLineParser.cpp index 383ed810b4..f8a1f2eb5d 100644 --- a/src/CommandLine/CommandLineParser.cpp +++ b/src/CommandLine/CommandLineParser.cpp @@ -226,6 +226,7 @@ static const std::initializer_list helpText = { " output", " -pploc Output message location in terms of post", " preprocessor location", + " -ppextra_loc Adds pre-processor location to syntax errors" " -noinfo Filters out INFO messages", " -nonote Filters out NOTE messages", " -nowarning Filters out WARNING messages", @@ -393,6 +394,7 @@ CommandLineParser::CommandLineParser(ErrorContainer* errors, m_profile(false), m_parseBuiltIn(true), m_ppOutputFileLocation(false), + m_ppPrintLineInfo(false), m_sverilog(false), m_dumpUhdm(false), m_elabUhdm(false), @@ -1311,6 +1313,8 @@ bool CommandLineParser::parseCommandLine(int32_t argc, const char** argv) { m_elabUhdm = true; } else if (all_arguments[i] == "-pploc") { m_ppOutputFileLocation = true; + } else if (all_arguments[i] == "-ppextra_loc") { + m_ppPrintLineInfo = true; } else if (all_arguments[i] == "-pythonlistener") { m_writePpOutput = true; m_parse = true; diff --git a/src/SourceCompile/AntlrParserErrorListener.cpp b/src/SourceCompile/AntlrParserErrorListener.cpp index dff41c316a..9df51329d5 100644 --- a/src/SourceCompile/AntlrParserErrorListener.cpp +++ b/src/SourceCompile/AntlrParserErrorListener.cpp @@ -47,8 +47,11 @@ void AntlrParserErrorListener::syntaxError( if (!lineText.empty()) { lineText.push_back('\n'); lineText.append(charPositionInLine, ' '); - StrAppend(&lineText, "^-- ", fileSystem->toPath(m_fileId), ":", line, ":", - charPositionInLine, ":"); + if (m_printExtraPpLineInfo) + StrAppend(&lineText, "^-- ", fileSystem->toPath(m_fileId), ":", line, + ":", charPositionInLine, ":"); + else + StrAppend(&lineText, "^--"); } } if (m_reportedSyntaxError < 10) { diff --git a/src/SourceCompile/ParseFile.cpp b/src/SourceCompile/ParseFile.cpp index 462b01c526..a57305ffcb 100644 --- a/src/SourceCompile/ParseFile.cpp +++ b/src/SourceCompile/ParseFile.cpp @@ -287,8 +287,8 @@ bool ParseFile::parseOneFile_(PathId fileId, uint32_t lineOffset) { new antlr4::ANTLRInputStream(m_sourceText); } - m_antlrParserHandler->m_errorListener = - new AntlrParserErrorListener(this, false, lineOffset, fileId); + m_antlrParserHandler->m_errorListener = new AntlrParserErrorListener( + this, false, lineOffset, fileId, clp->printExtraPpLineInfo()); m_antlrParserHandler->m_lexer = new SV3_1aLexer(m_antlrParserHandler->m_inputStream); VerilogVersion version = VerilogVersion::SystemVerilog; diff --git a/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log b/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log index f3fe3ba0e3..8d19a5b532 100644 --- a/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log +++ b/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log @@ -2,7 +2,7 @@ | | FILE UNIT COMP | ALL COMPILATION | |-------|------------------|-------------------| | FATAL | 0 | 0 | -|SYNTAX | 6 | 6 | +|SYNTAX | 3 | 3 | | ERROR | 23 | 23 | |WARNING| 12 | 12 | | INFO | | | diff --git a/tests/ParamFile/ParamFileMacro.log b/tests/ParamFile/ParamFileMacro.log index f97922b9a7..238e547a14 100644 --- a/tests/ParamFile/ParamFileMacro.log +++ b/tests/ParamFile/ParamFileMacro.log @@ -213,7 +213,7 @@ n<> u<206> t c<1> l<3:1> el<32:1> AST_DEBUG_END [SNT:PA0207] ${SURELOG_DIR}/tests/ParamFile/dut.sv:4:28: Syntax error: extraneous input '/' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'virtual', 'type', 'const', 'local', 'super', '{', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, parameter SRAMInitFile = /toto/blah; - ^-- ${SURELOG_DIR}/build/regression/ParamFileMacro/slpp_unit/lib/work/dut.sv:4:28:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 diff --git a/tests/PreProcMacro/PreProcMacro.log b/tests/PreProcMacro/PreProcMacro.log index 8ebcea3ed4..f651b5f20a 100644 --- a/tests/PreProcMacro/PreProcMacro.log +++ b/tests/PreProcMacro/PreProcMacro.log @@ -218,38 +218,32 @@ n<> u<210> t c<1> l<14:1> el<24:1> AST_DEBUG_END [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', SURELOG_MACRO_NOT_DEFINED:check1!!! A - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', SURELOG_MACRO_NOT_DEFINED:check1!!! A - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'A \n "A is ifdef'd"', "A is ifdef'd" - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:18:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"A is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, "A is not ifdef'd" - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:20:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', SURELOG_MACRO_NOT_DEFINED:check1!!! B - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', SURELOG_MACRO_NOT_DEFINED:check1!!! B - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'B \n "B is ifdef'd"', "B is ifdef'd" - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:27:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"B is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, "B is not ifdef'd" - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:29:4:. -[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', - SURELOG_MACRO_NOT_DEFINED:check1!!! A - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:. -[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!', - SURELOG_MACRO_NOT_DEFINED:check1!!! A - ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5: Unknown macro "check1". [ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:7: Unknown macro "check2". [ FATAL] : 0 -[ SYNTAX] : 10 +[ SYNTAX] : 8 [ ERROR] : 4 [WARNING] : 0 [ NOTE] : 0 diff --git a/tests/PreprocLine/PreprocLine.log b/tests/PreprocLine/PreprocLine.log index 17fa3ba69a..860f4d72da 100644 --- a/tests/PreprocLine/PreprocLine.log +++ b/tests/PreprocLine/PreprocLine.log @@ -79,7 +79,7 @@ n<> u<69> t c<1> l<1:1> el<13:1> AST_DEBUG_END [SNT:PA0207] ${SURELOG_DIR}/tests/PreprocLine/fake.v:7: Syntax error: extraneous input '"line.vh"' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, "line.vh" -^-- ${SURELOG_DIR}/build/regression/PreprocLine/slpp_all/lib/work/dut.sv:7:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 diff --git a/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log b/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log index 292084dad8..b7d74d6ba0 100644 --- a/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log +++ b/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log @@ -92,21 +92,12 @@ ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:21:9: macro definition takes ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_4.v:34: macro instance. [SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top.v:69:0:. -[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , -initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_1.v:69:0:. -[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , -initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_2.v:69:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_3.v:5: Syntax error: mismatched input '1' expecting , 1 + 1 + 42 + 100 + c -^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_3.v:5:0:. -[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , -initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_4.v:69:0:. +^--. [ FATAL] : 0 -[ SYNTAX] : 6 +[ SYNTAX] : 3 [ ERROR] : 23 [WARNING] : 12 [ NOTE] : 16 diff --git a/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log b/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log index 95918c56b5..378b52d4e3 100644 --- a/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log +++ b/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log @@ -85,26 +85,17 @@ ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:21:9: macro definition takes [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top.v". [SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top.v:69:0:. +^--. [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_1.v". -[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , -initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_1.v:69:0:. [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_2.v". -[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , -initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_2.v:69:0:. [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_3.v". [SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_3.v:5: Syntax error: mismatched input '1' expecting , 1 + 1 + 42 + 100 + c -^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_3.v:5:0:. +^--. [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_4.v". -[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting , -initial $display("start", "msg1" , "msg2", "end"); -^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_4.v:69:0:. [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/lib.v". [ FATAL] : 0 -[ SYNTAX] : 6 +[ SYNTAX] : 3 [ ERROR] : 23 [WARNING] : 12 [ NOTE] : 6 diff --git a/tests/TestMacros/TestMacros.log b/tests/TestMacros/TestMacros.log index e6a51ee7f8..ca9b8c2a1d 100644 --- a/tests/TestMacros/TestMacros.log +++ b/tests/TestMacros/TestMacros.log @@ -5,7 +5,7 @@ [ERR:PP0111] ${SURELOG_DIR}/tests/TestMacros/TestMacros.v:12: Illegally redefining compiler directive "`define" as a macro name. [SNT:PA0207] ${SURELOG_DIR}/tests/TestMacros/macros.inc:11:3: Syntax error: mismatched input 'begin' expecting , begin - ^-- ${SURELOG_DIR}/build/regression/TestMacros/slpp_all/lib/work/TestMacros/TestMacros.v:3:3:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 6f0faecb48..324c64fb23 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -66,8 +66,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess [ 6%] Generating 10_lsu_bus_intf.sv [ 12%] Generating 11_ifu_bp_ctl.sv -[ 18%] Generating 13_ifu_mem_ctl.sv -[ 25%] Generating 12_beh_lib.sv +[ 18%] Generating 12_beh_lib.sv +[ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv [ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv diff --git a/third_party/tests/Google/Google.log b/third_party/tests/Google/Google.log index ba9573d417..8e071b29d2 100644 --- a/third_party/tests/Google/Google.log +++ b/third_party/tests/Google/Google.log @@ -1,7 +1,7 @@ Processing: -cd . -I../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns sanity.sv -l sanity.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/sanity.sv:14:1: Syntax error: no viable alternative at input 'syntaxerror\n\twire', wire clk; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/sanity.sv:14:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -10,10 +10,10 @@ Processing: -cd . -I../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouh Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 5.7.2-real-constants-illegal.sv -l 5.7.2-real-constants-illegal.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:20:8: Syntax error: no viable alternative at input 'module top();\n logic [31:0] a;\n\n initial begin;\n a = .', a = .12; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:20:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:19:2: Syntax error: mismatched input 'initial' expecting , initial begin; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.2-real-constants-illegal.sv:19:2:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -112,7 +112,7 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 5.6.4--compiler-directives-preprocessor-macro_0.sv -l 5.6.4--compiler-directives-preprocessor-macro_0.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_0.sv:20:16: Syntax error: no viable alternative at input 'TEST_VAR parsed not', TEST_VAR parsed not correctly from template - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_0.sv:20:16:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -218,16 +218,16 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 5.6--wrong-identifiers.sv -l 5.6--wrong-identifiers.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6: Syntax error: no viable alternative at input 'module identifiers();\n reg $', reg $dollar; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6: Syntax error: extraneous input '$' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, reg $dollar; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:17:6:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:18:6: Syntax error: extraneous input '0' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, reg 0number; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:18:6:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6--wrong-identifiers.sv:19: Syntax error: extraneous input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6--wrong-identifiers.sv:19:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 4 [ ERROR] : 0 @@ -279,10 +279,10 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 5.7.1--integers-signed-illegal.sv -l 5.7.1--integers-signed-illegal.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:20:10: Syntax error: no viable alternative at input 'module top();\n logic [7:0] a;\n\n initial begin\n a = 8'd', a = 8'd-6; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:20:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:19:2: Syntax error: mismatched input 'initial' expecting , initial begin - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.7.1--integers-signed-illegal.sv:19:2:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -312,13 +312,13 @@ Processing: -cd chapter-5 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:18: Unknown macro "VAR_2". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8: Syntax error: no viable alternative at input 'module top();\nint a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!!', int a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!! + SURELOG_MACRO_NOT_DEFINED:VAR_2!!! ; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8: Syntax error: no viable alternative at input '= SURELOG_MACRO_NOT_DEFINED:VAR_1!!!', int a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!! + SURELOG_MACRO_NOT_DEFINED:VAR_2!!! ; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:44: Syntax error: mismatched input '+' expecting , int a = SURELOG_MACRO_NOT_DEFINED:VAR_1!!! + SURELOG_MACRO_NOT_DEFINED:VAR_2!!! ; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18:44:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Google/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv:18: Unknown macro "VAR_1". [ FATAL] : 0 [ SYNTAX] : 3 @@ -573,10 +573,10 @@ Processing: -cd chapter-15 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - Processing: -cd chapter-15 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 15.4--mailbox-blocking.sv -l 15.4--mailbox-blocking.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-blocking.sv:21:1: Syntax error: no viable alternative at input 'module top();\n\nmailbox m;\n\ninitial begin\n\tm = new();\n\tstring', string msg = "abc"; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-blocking.sv:21:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-blocking.sv:19: Syntax error: mismatched input 'initial' expecting , initial begin -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-blocking.sv:19:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -585,10 +585,10 @@ initial begin Processing: -cd chapter-15 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 15.4--mailbox-non-blocking.sv -l 15.4--mailbox-non-blocking.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:21:1: Syntax error: no viable alternative at input 'module top();\n\nmailbox m;\n\ninitial begin\n\tm = new();\n\tstring', string msg = "abc"; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:21:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:19: Syntax error: mismatched input 'initial' expecting , initial begin -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-15/15.4--mailbox-non-blocking.sv:19:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -771,10 +771,10 @@ Processing: -cd chapter-11 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - Processing: -cd chapter-11 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.3.6--assign_in_expr_inv.sv -l 11.3.6--assign_in_expr_inv.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:23:7: Syntax error: no viable alternative at input 'module top();\n\nint a;\nint b;\nint c;\n\ninitial begin\n\ta = b =', a = b = c = 5; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:23:7:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:22: Syntax error: mismatched input 'initial' expecting , initial begin -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-11/11.3.6--assign_in_expr_inv.sv:22:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1996,7 +1996,7 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_8.sv:17:9: macro definition takes 2. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_8.sv:18: Syntax error: mismatched input 'initial' expecting , initial $display("start", , , "end"); -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_8.sv:18:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 1 @@ -2032,10 +2032,10 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:17:9: No default value for argument 3 (c) in macro definition. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:19: Syntax error: no viable alternative at input 'module top ();\n`', `MACRO1 // ILLEGAL: b and c omitted, no default for c -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:19:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:20: Syntax error: extraneous input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_12.sv:20:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 @@ -2104,7 +2104,7 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - ^-- ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.12--line-illegal-2.sv:17:8:. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.12--line-illegal-2.sv:17:9: Syntax error: no viable alternative at input 'somefile 2', somefile 2 - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.12--line-illegal-2.sv:17:9:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2128,7 +2128,7 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - ^-- ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.9--unconnected_drive-invalid-3.sv:18:21:. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.9--unconnected_drive-invalid-3.sv:18:21: Syntax error: extraneous input 'pull0' expecting , `nounconnected_drive pull0 - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.9--unconnected_drive-invalid-3.sv:18:21:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2163,10 +2163,10 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:17:9: No default value for argument 2 (y) in macro definition. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:19: Syntax error: no viable alternative at input 'module top ();\n`', `D -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:19:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:20: Syntax error: extraneous input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_6.sv:20:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 @@ -2332,7 +2332,7 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - ^-- ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.9--unconnected_drive-invalid-1.sv:17:18:. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.9--unconnected_drive-invalid-1.sv:18: Syntax error: missing {'pull0', 'pull1', Simple_identifier} at '`nounconnected_drive', `nounconnected_drive -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.9--unconnected_drive-invalid-1.sv:18:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2354,10 +2354,10 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [ERR:PP0120] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.3--resetall_illegal.sv:19: Illegal directive in design element "`resetall". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.3--resetall_illegal.sv:19: Syntax error: no viable alternative at input 'module top ();\n`', `resetall -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.3--resetall_illegal.sv:19:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.3--resetall_illegal.sv:20: Syntax error: extraneous input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.3--resetall_illegal.sv:20:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 @@ -2420,7 +2420,7 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - [ERR:PP0119] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.4--include_two_in_one_line.sv:8:29: Invalid include filename. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.4--include_two_in_one_line.sv:8: Syntax error: mismatched input '.' expecting , .sv> .sv> -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.4--include_two_in_one_line.sv:8:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 2 @@ -2474,7 +2474,7 @@ Processing: -cd chapter-22 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote - <<. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-22/22.5.1--define-expansion_21.sv:19: Syntax error: mismatched input '"' expecting , "start of string -^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-22/22.5.1--define-expansion_21.sv:19:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 2 @@ -4502,13 +4502,13 @@ Processing: -cd chapter-6 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n Processing: -cd chapter-6 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 6.23--type_op_compare.sv -l 6.23--type_op_compare.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.23--type_op_compare.sv:18:19: Syntax error: no viable alternative at input 'module top #( parameter type T = type(logic[11:0]) )\n ();\n initial begin\n case (type(T))', case (type(T)) - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.23--type_op_compare.sv:18:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.23--type_op_compare.sv:15:51: Syntax error: mismatched input ')' expecting ';', module top #( parameter type T = type(logic[11:0]) ) - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.23--type_op_compare.sv:15:51:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.23--type_op_compare.sv:17:3: Syntax error: mismatched input 'initial' expecting , initial begin - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.23--type_op_compare.sv:17:3:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -4829,16 +4829,16 @@ Processing: -cd chapter-6 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -n Processing: -cd chapter-6 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 6.9.2--vector_vectored_inv.sv -l 6.9.2--vector_vectored_inv.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7: Syntax error: no viable alternative at input 'module top();\n\tlogic vectored', logic vectored [15:0] a = 0; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7: Syntax error: mismatched input 'vectored' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, logic vectored [15:0] a = 0; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:7:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:23: Syntax error: missing ';' at 'a', logic vectored [15:0] a = 0; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:17:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:19:1: Syntax error: mismatched input 'assign' expecting , assign a[1] = 1; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-6/6.9.2--vector_vectored_inv.sv:19:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 4 [ ERROR] : 0 @@ -4993,7 +4993,7 @@ Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse - Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns preproc_test_10.sv -l preproc_test_10.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/generic/preproc/preproc_test_10.sv:8:1: Syntax error: no viable alternative at input 'a,', a, - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/generic/preproc/preproc_test_10.sv:8:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -5014,7 +5014,7 @@ Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse - Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns preproc_test_11.sv -l preproc_test_11.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/generic/preproc/preproc_test_11.sv:8:1: Syntax error: no viable alternative at input 'a,', a, - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/generic/preproc/preproc_test_11.sv:8:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -5035,7 +5035,7 @@ Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse - Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns preproc_test_12.sv -l preproc_test_12.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/generic/preproc/preproc_test_12.sv:8:1: Syntax error: no viable alternative at input 'a,', a, b=2, c=42) \ - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/generic/preproc/preproc_test_12.sv:8:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -5059,7 +5059,7 @@ Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse - Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns preproc_test_13.sv -l preproc_test_13.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/generic/preproc/preproc_test_13.sv:8:1: Syntax error: no viable alternative at input 'a,', a, b="(3,2)", c=(3,2)) \ - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/generic/preproc/preproc_test_13.sv:8:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -5068,7 +5068,7 @@ a, b="(3,2)", c=(3,2)) \ Processing: -cd generic/preproc -I../../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns preproc_test_9.sv -l preproc_test_9.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/generic/preproc/preproc_test_9.sv:8:1: Syntax error: no viable alternative at input 'a,', a, b, c) - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/generic/preproc/preproc_test_9.sv:8:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -8270,34 +8270,34 @@ Processing: -cd chapter-18 -I../../../UVM/1800.2-2017-1.0/src/ ../../../UVM/1800 [WRN:PP0113] ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/macros/uvm_callback_defines.svh:302:9: Unused macro argument "OPER". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:32:20: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, 0 : zero; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7368:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:33:21: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, 1 : first; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7369:21:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:34:12: Syntax error: mismatched input '2' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'void', DOLLAR_UNIT, 'endsequence', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, 2 : second; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7370:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:35:12: Syntax error: extraneous input 'default' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, default : third; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7371:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:36:8: Syntax error: extraneous input 'endcase' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, endcase; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7372:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:37:19: Syntax error: no viable alternative at input '{ x =', zero : { x = 0; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7373:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:37:24: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, zero : { x = 0; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7373:24:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:38:20: Syntax error: no viable alternative at input '{ x =', first : { x = 10; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7374:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:38:26: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, first : { x = 10; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7374:26:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:39:21: Syntax error: no viable alternative at input '{ x =', second : { x = 2; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_1.sv:7375:21:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -8515,34 +8515,34 @@ Processing: -cd chapter-18 -I../../../UVM/1800.2-2017-1.0/src/ ../../../UVM/1800 Processing: -cd chapter-18 -I../../../UVM/1800.2-2017-1.0/src/ -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 18.17.3--case-production-statements_0.sv -l 18.17.3--case-production-statements_0.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:20:18: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, 0 : zero; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:20:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:21:19: Syntax error: extraneous input ';' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'endcase', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, 1 : first; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:21:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:22:10: Syntax error: mismatched input '2' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'void', DOLLAR_UNIT, 'endsequence', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, 2 : second; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:22:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:23:10: Syntax error: extraneous input 'default' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, default : third; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:23:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:24:6: Syntax error: extraneous input 'endcase' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, endcase; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:24:6:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:18: Syntax error: no viable alternative at input '{ x =', zero2 : { x = 0; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:23: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, zero2 : { x = 0; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:25:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:18: Syntax error: no viable alternative at input '{ x =', first : { x = 10; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:24: Syntax error: extraneous input '}' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', 'endfunction', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, first : { x = 10; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:26:24:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:27:19: Syntax error: no viable alternative at input '{ x =', second : { x = 2; }; - ^-- ${SURELOG_DIR}/build/regression/Google/slpp_all/lib/work/tests/Google/chapter-18/18.17.3--case-production-statements_0.sv:27:19:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 diff --git a/third_party/tests/Icarus/Icarus.log b/third_party/tests/Icarus/Icarus.log index 1336db7fb6..6a0cf0d105 100644 --- a/third_party/tests/Icarus/Icarus.log +++ b/third_party/tests/Icarus/Icarus.log @@ -561,19 +561,19 @@ Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -t Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns specify_01.v -l specify_01.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:9: Syntax error: no viable alternative at input '(clk,d =>', (clk,d => q) = (tR_clk_q,tF_clk_q); - ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:17: Syntax error: extraneous input '(' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (clk,d => q) = (tR_clk_q,tF_clk_q); - ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:17:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:26: Syntax error: mismatched input ',' expecting '=', (clk,d => q) = (tR_clk_q,tF_clk_q); - ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:26:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:13:35: Syntax error: mismatched input ')' expecting '=', (clk,d => q) = (tR_clk_q,tF_clk_q); - ^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:13:35:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/specify_01.v:14: Syntax error: extraneous input 'endspecify' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, endspecify -^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/specify_01.v:14:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 5 [ ERROR] : 0 @@ -1879,10 +1879,10 @@ Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -t Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns escape2a.v -l escape2a.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2a.v:14: Syntax error: no viable alternative at input 'module part1 (\n#~@6A_A#~@,\n#~@6Y_A#~@,\nVCC ,\nGND ,\n#~@6A_B#~@,\n#~@6Y_B#~@,\n#~@6A_C#~@,\n#~@6Y_C#~@,\n#~@6A_D#~@,\n#~@6Y_D#~@,\n#~@6A_E#~@,\n// note: there is not a space character before the nl below\n\', \6Y_E -^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2a.v:14:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2a.v:17: Syntax error: mismatched input 'input' expecting , input #~@6A_A#~@; -^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2a.v:17:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2268,10 +2268,10 @@ Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -t Processing: -cd ivltests +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns escape2b.v -l escape2b.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2b.v:15: Syntax error: no viable alternative at input 'module part2 (\n#~@6A_A#~@,\n#~@6Y_A#~@,\nVCC ,\nGND ,\n#~@6A_B#~@,\n#~@6Y_B#~@,\n#~@6A_C#~@,\n#~@6Y_C#~@,\n#~@6A_D#~@,\n#~@6Y_D#~@,\n#~@6A_E#~@,\n// note: there is not a space character before the nl below\n// no space character after nl also\n\', \6Y_E -^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2b.v:15:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Icarus/ivltests/escape2b.v:18: Syntax error: mismatched input 'input' expecting , input #~@6A_A#~@; -^-- ${SURELOG_DIR}/build/regression/Icarus/slpp_all/lib/work/ivltests/escape2b.v:18:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 diff --git a/third_party/tests/UtdSV/UtdSV.log b/third_party/tests/UtdSV/UtdSV.log index a81052464e..fd182937ec 100644 --- a/third_party/tests/UtdSV/UtdSV.log +++ b/third_party/tests/UtdSV/UtdSV.log @@ -3364,13 +3364,13 @@ Processing: -cd . +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescal <<. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/UtdSV/ifdef-2.v:17: Syntax error: extraneous input '"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, "first_block, second_block not defined, -^-- ${SURELOG_DIR}/build/regression/UtdSV/slpp_all/lib/work/ifdef-2.v:17:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/UtdSV/ifdef-2.v:17:38: Syntax error: mismatched input ',' expecting '(', "first_block, second_block not defined, - ^-- ${SURELOG_DIR}/build/regression/UtdSV/slpp_all/lib/work/ifdef-2.v:17:38:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/UtdSV/ifdef-2.v:18: Syntax error: mismatched input '"' expecting {'(', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, "); -^-- ${SURELOG_DIR}/build/regression/UtdSV/slpp_all/lib/work/ifdef-2.v:18:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 2 diff --git a/third_party/tests/Verilator/Verilator.log b/third_party/tests/Verilator/Verilator.log index 995e101611..94fe5821db 100644 --- a/third_party/tests/Verilator/Verilator.log +++ b/third_party/tests/Verilator/Verilator.log @@ -109,7 +109,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_lint_pkg_colon_bad.v -l t_lint_pkg_colon_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pkg_colon_bad.v:7:14: Syntax error: mismatched input '::' expecting ';', reg mispkgb::bar_t b; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pkg_colon_bad.v:7:14:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -118,7 +118,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_case_wild.v -l t_case_wild.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_case_wild.v:64:6: Syntax error: mismatched input 'endcase' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, 'default', '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'matches', 'tagged', ''', 'inside', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, endcase - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_case_wild.v:64:6:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -235,10 +235,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_var_dup_bad.v -l t_var_dup_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_dup_bad.v:65:3: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, output bad_reout_port; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_dup_bad.v:65:3:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_dup_bad.v:65:24: Syntax error: no viable alternative at input 'bad_reout_port;', output bad_reout_port; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_dup_bad.v:65:24:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -348,31 +348,31 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_lint_pindup_bad.v -l t_lint_pindup_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:14:7: Syntax error: no viable alternative at input 'sub\n #(,', #(, // Not found - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:14:7:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:15:15: Syntax error: no viable alternative at input '(1', .NEXIST(1), // Not found - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:15:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:16:10: Syntax error: no viable alternative at input '(2', .P(2), - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:16:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:17:10: Syntax error: no viable alternative at input '(3', .P(3)) // Dup - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:17:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:18:8: Syntax error: no viable alternative at input '(.', sub (.o(o), - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:18:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:18:12: Syntax error: extraneous input ')' expecting ',', sub (.o(o), - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:18:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:19:8: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .i(i), - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:19:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:20:8: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .i(i2), // Dup - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:20:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_pindup_bad.v:21:8: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .nexist(i2) // Not found - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_pindup_bad.v:21:8:. + ^--. [ FATAL] : 0 [ SYNTAX] : 9 [ ERROR] : 0 @@ -436,10 +436,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_display.v:11:4: Unknown macro "error". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_display.v:11:39: Syntax error: no viable alternative at input 'module t ();\n\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion."', SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion." - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_display.v:11:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_display.v:11:39: Syntax error: mismatched input '"Only Verilator supports PLI-ish DPI calls and sformat conversion."' expecting , SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion." - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_display.v:11:39:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_display.v:11: Unknown macro "error". [ FATAL] : 0 [ SYNTAX] : 2 @@ -639,13 +639,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_flag_language.v -l t_flag_language.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_flag_language.v:10:11: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n // See also t_preproc_kwd.v\n\n integer bit', integer bit; initial bit = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_flag_language.v:10:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_flag_language.v:10:11: Syntax error: mismatched input 'bit' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, integer bit; initial bit = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_flag_language.v:10:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_flag_language.v:10:16: Syntax error: mismatched input 'initial' expecting , integer bit; initial bit = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_flag_language.v:10:16:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -1023,36 +1023,24 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_pipe_filter.v -l t_pipe_filter.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter.v:10:13: Syntax error: no viable alternative at input 'example line 10', example line 10; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:10:13:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter.v:11:13: Syntax error: no viable alternative at input 'example line 11', example line 11; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:11:13:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:6:9: Syntax error: no viable alternative at input 'inc line 6', inc line 6; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:18:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:7:9: Syntax error: no viable alternative at input 'inc line 7', inc line 7; // example_lint_off_line FOO - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:19:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:8:9: Syntax error: no viable alternative at input 'inc line 8', inc line 8; // example_lint_off_line BAR - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:20:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:9:9: Syntax error: no viable alternative at input 'inc line 9', inc line 9; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:21:9:. -[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:6:9: Syntax error: no viable alternative at input 'inc line 6', -inc line 6; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:29:9:. -[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:7:9: Syntax error: no viable alternative at input 'inc line 7', -inc line 7; // example_lint_off_line FOO - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:30:9:. -[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:8:9: Syntax error: no viable alternative at input 'inc line 8', -inc line 8; // example_lint_off_line BAR - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:31:9:. -[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pipe_filter_inc.vh:9:9: Syntax error: no viable alternative at input 'inc line 9', -inc line 9; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pipe_filter.v:32:9:. + ^--. [ FATAL] : 0 -[ SYNTAX] : 10 +[ SYNTAX] : 6 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 @@ -1168,7 +1156,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_lint_bsspace_bad.v -l t_lint_bsspace_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_bsspace_bad.v:12: Syntax error: no viable alternative at input 'blak\n\nmodule', module t; -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_bsspace_bad.v:12:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -1250,13 +1238,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_interface_modportlist.v -l t_interface_modportlist.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_modportlist.v:10:26: Syntax error: no viable alternative at input 'my_module m(.clk(clk), iface', my_module m(.clk(clk), iface); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_modportlist.v:10:26:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_modportlist.v:10:15: Syntax error: no viable alternative at input '(.', my_module m(.clk(clk), iface); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_modportlist.v:10:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_modportlist.v:10:23: Syntax error: extraneous input ')' expecting ',', my_module m(.clk(clk), iface); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_modportlist.v:10:23:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -1321,7 +1309,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_preproc_persist_inc.v -l t_preproc_persist_inc.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist_inc.v:8:7: Syntax error: no viable alternative at input 'Inside "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist_inc.v"', Inside "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist_inc.v". - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_persist_inc.v:8:7:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -1366,13 +1354,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_const_dec_mixed_bad.v -l t_const_dec_mixed_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_const_dec_mixed_bad.v:8:35: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n parameter [200:0] MIXED = 32'dx_1', parameter [200:0] MIXED = 32'dx_1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_const_dec_mixed_bad.v:8:35:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_const_dec_mixed_bad.v:8:35: Syntax error: extraneous input '1' expecting ';', parameter [200:0] MIXED = 32'dx_1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_const_dec_mixed_bad.v:8:35:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_const_dec_mixed_bad.v:10: Syntax error: extraneous input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_const_dec_mixed_bad.v:10:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -1393,10 +1381,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_trace_primitive.v -l t_trace_primitive.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_trace_primitive.v:34: Syntax error: extraneous input 'assign' expecting {'input', 'output', 'reg', '(*', 'table', 'initial'}, assign b = ~a; -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_trace_primitive.v:34:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_trace_primitive.v:35: Syntax error: mismatched input 'endprimitive' expecting , endprimitive -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_trace_primitive.v:35:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1411,19 +1399,19 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_enum.v -l t_enum.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:16: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n localparam FIVE = 5;\n\n enum { e0,\n\t e1,\n\t e3=3,\n\t e5=FIVE,\n\t e10_[2] = 10,\n\t e12,\n\t e20_[5:7] = 25,\n\t e20_z,\n\t e30_[7:5] = 30,\n\t e30_z\n\t } EN;\n\n enum {\n\t z5 = e5\n\t } ZN;\n\n typedef enum [', typedef enum [2:0] { ONES=~0 } three_t; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:16: Syntax error: no viable alternative at input 'enum [', typedef enum [2:0] { ONES=~0 } three_t; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:16: Syntax error: mismatched input '[' expecting {'{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, typedef enum [2:0] { ONES=~0 } three_t; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:33:22: Syntax error: mismatched input '{' expecting ';', typedef enum [2:0] { ONES=~0 } three_t; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:33:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum.v:41:3: Syntax error: mismatched input 'initial' expecting , initial begin - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum.v:41:3:. + ^--. [ FATAL] : 0 [ SYNTAX] : 5 [ ERROR] : 0 @@ -1482,7 +1470,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_threads.v:19:4: Unknown macro "error". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_threads.v:19:39: Syntax error: extraneous input '"Only Verilator supports PLI-ish DPI calls."' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_threads.v:19:39:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_threads.v:19: Unknown macro "error". [ FATAL] : 0 [ SYNTAX] : 1 @@ -1602,13 +1590,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_inst_missing.v -l t_inst_missing.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing.v:10:21: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n // verilator lint_off PINNOCONNECT\n // verilator lint_off PINCONNECTEMPTY\n sub sub (.ok(ok), ,', sub sub (.ok(ok), , .nc()); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing.v:10:21:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing.v:10:11: Syntax error: no viable alternative at input 'sub sub (', sub sub (.ok(ok), , .nc()); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing.v:10:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing.v:13: Syntax error: mismatched input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing.v:13:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -1634,34 +1622,34 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PA0209] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:73: Unsupported keyword set: "VAMS-2.3". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:16: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', integer signed; initial signed = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:26: Syntax error: mismatched input 'signed' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, integer signed; initial signed = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:26:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:33: Syntax error: mismatched input '=' expecting {'[', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, integer signed; initial signed = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:33:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:29:35: Syntax error: mismatched input '1' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, integer signed; initial signed = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:29:35:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:35:10: Syntax error: mismatched input 'bit' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, integer bit; initial bit = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:35:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:35:23: Syntax error: mismatched input 'bit' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, integer bit; initial bit = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:35:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:35:27: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', integer bit; initial bit = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:35:27:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:41:10: Syntax error: mismatched input 'final' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, integer final; initial final = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:41:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:41:25: Syntax error: mismatched input 'final' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, integer final; initial final = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:41:25:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_kwd.v:41:31: Syntax error: mismatched input '=' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, integer final; initial final = 1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_kwd.v:41:31:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 1 @@ -1722,10 +1710,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0120] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_implicit_def_bad.v:21: Illegal directive in design element "`resetall". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_implicit_def_bad.v:14: Syntax error: extraneous input '`default_nettype' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, `default_nettype none -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_implicit_def_bad.v:14:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_implicit_def_bad.v:15:3: Syntax error: mismatched input 'assign' expecting , assign imp_err = 1'b1; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_implicit_def_bad.v:15:3:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 @@ -1772,13 +1760,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_inst_missing_bad.v -l t_inst_missing_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing_bad.v:8:21: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n sub sub (.ok(ok), ,', sub sub (.ok(ok), , .nc()); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing_bad.v:8:21:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing_bad.v:8:11: Syntax error: no viable alternative at input 'sub sub (', sub sub (.ok(ok), , .nc()); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing_bad.v:8:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_inst_missing_bad.v:9: Syntax error: mismatched input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_inst_missing_bad.v:9:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -1838,25 +1826,25 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:17:9: No default value for argument 1 (x) in macro definition. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:21:3: Syntax error: no viable alternative at input '$display("left side: \"right side\"" // The 'left' as the variable name shouldn't match the "left" in the `" string\n initial', initial begin - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:33:3:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:20:15: Syntax error: no viable alternative at input '("left side: \"right side\""', $display("left side: \"right side\"" // The 'left' as the variable name shouldn't match the "left" in the `" string - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:32:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:31: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', ':', 'virtual', 'type', 'bind', 'const', 'static', 'local', 'super', '{', '->', 'if', 'foreach', 'automatic', 'localparam', 'parameter', 'import', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', 'var', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', 'let', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, ); -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:35:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:39:15: Syntax error: no viable alternative at input '$display(`', $display(`"standalone`"); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:43:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:39:14: Syntax error: mismatched input '(' expecting ';', $display(`"standalone`"); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:43:14:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:39:16: Syntax error: mismatched input '"standalone`"' expecting Simple_identifier, $display(`"standalone`"); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:43:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v:49:6: Syntax error: mismatched input '$' expecting , $display("Line %0d File \"%s\"",49,"${SURELOG_DIR}/third_party/tests/Verilator/t_pp_display.v"); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_display.v:53:6:. + ^--. [ FATAL] : 0 [ SYNTAX] : 7 [ ERROR] : 1 @@ -1969,16 +1957,16 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_mem_slice_bad.v -l t_mem_slice_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:30: Syntax error: mismatched input '[' expecting '=', assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:30:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:41: Syntax error: extraneous input '=' expecting {'[', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:53: Syntax error: mismatched input '?' expecting ';', assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:53:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_slice_bad.v:38:82: Syntax error: extraneous input ':' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_slice_bad.v:38:82:. + ^--. [ FATAL] : 0 [ SYNTAX] : 4 [ ERROR] : 0 @@ -2041,10 +2029,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_mem_multi_ref_bad.v -l t_mem_multi_ref_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_multi_ref_bad.v:18:18: Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n reg dimn;\n reg [1:0] dim0;\n reg [1:0] dim1 [1:0];\n reg [1:0] dim2 [1:0][1:0];\n reg dim0nv[1:0];\n\n initial begin\n dimn[1:0] = 0; // Bad: Not ranged\n dim0[1][1] = 0; // Bad: Not arrayed\n dim1[1][1][1] = 0; // Bad: Not arrayed to right depth\n dim2[1][1][1] = 0; // OK\n dim2[0 +: 1][', dim2[0 +: 1][1] = 0; // Bad: Range on non-bits - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_multi_ref_bad.v:18:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_mem_multi_ref_bad.v:13:3: Syntax error: mismatched input 'initial' expecting , initial begin - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_mem_multi_ref_bad.v:13:3:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2077,7 +2065,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_preproc_persist.v -l t_preproc_persist.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist.v:6:7: Syntax error: no viable alternative at input 'Inside "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist.v"', Inside "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist.v". - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_persist.v:6:7:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -2165,13 +2153,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_langext_order.v -l t_langext_order.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_langext_order.v:10:15: Syntax error: no viable alternative at input 'input do', module t(input do); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_langext_order.v:10:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_langext_order.v:11:29: Syntax error: no viable alternative at input 't_langext_order_sub sub (.do', t_langext_order_sub sub (.do(do)); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_langext_order.v:11:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_langext_order.v:11:28: Syntax error: no viable alternative at input '(.', t_langext_order_sub sub (.do(do)); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_langext_order.v:11:28:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -2286,10 +2274,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_sys.v:15:4: Unknown macro "error". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_sys.v:15:39: Syntax error: no viable alternative at input 'module t ();\n\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls."', SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_sys.v:15:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_sys.v:15:39: Syntax error: mismatched input '"Only Verilator supports PLI-ish DPI calls."' expecting , SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_sys.v:15:39:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_sys.v:15: Unknown macro "error". [ FATAL] : 0 [ SYNTAX] : 2 @@ -2397,7 +2385,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_lint_mod_paren_bad.v -l t_lint_mod_paren_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_mod_paren_bad.v:12:5: Syntax error: mismatched input '(' expecting ';', ) ( - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_mod_paren_bad.v:12:5:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -2430,10 +2418,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_clk_concat2.v -l t_clk_concat2.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat2.v:85:3: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input clk; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat2.v:85:3:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat2.v:85:18: Syntax error: no viable alternative at input 'clk;', input clk; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat2.v:85:18:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2720,10 +2708,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_hierarchy_identifier.v -l t_hierarchy_identifier.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_hierarchy_identifier.v:30:26: Syntax error: mismatched input '\' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, if (cnt==SIZE) begin : \0escaped___name - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_hierarchy_identifier.v:30:26:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_hierarchy_identifier.v:33:3: Syntax error: extraneous input 'end' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, end : \0escaped___name - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_hierarchy_identifier.v:33:3:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2801,7 +2789,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_def09.v:55:9: No default value for argument 1 (a) in macro definition. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_def09.v:11: Syntax error: mismatched input ''' expecting , 'initial $display("start", "msg1" , "msg2", "end");' -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_def09.v:11:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 1 @@ -2949,7 +2937,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_preproc_noline.v -l t_preproc_noline.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_noline.v:9:9: Syntax error: no viable alternative at input 'Hello in t_preproc_psl', Hello in t_preproc_psl.v - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_noline.v:9:9:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -3007,7 +2995,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_preproc_persist2.v -l t_preproc_persist2.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist2.v:6:7: Syntax error: no viable alternative at input 'Inside "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist2.v"', Inside "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_persist2.v". - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_persist2.v:6:7:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -3166,10 +3154,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_attr_parenstar.v -l t_attr_parenstar.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_attr_parenstar.v:32:12: Syntax error: no viable alternative at input '@ (*', always @ (* - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_attr_parenstar.v:32:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_attr_parenstar.v:35:3: Syntax error: extraneous input 'end' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, end - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_attr_parenstar.v:35:3:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -3316,13 +3304,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_var_bad_sv.v -l t_var_bad_sv.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_bad_sv.v:7:7: Syntax error: mismatched input 'do' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, reg do; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_bad_sv.v:7:7:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_bad_sv.v:8:13: Syntax error: no viable alternative at input 'mod mod (.do', mod mod (.do(bar)); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_bad_sv.v:8:13:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_bad_sv.v:8:12: Syntax error: no viable alternative at input '(.', mod mod (.do(bar)); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_bad_sv.v:8:12:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -3614,10 +3602,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_lib_library.v:7:11: Unknown macro "WIDTH". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_lib_library.v:7:10: Syntax error: no viable alternative at input '[SURELOG_MACRO_NOT_DEFINED:WIDTH!!!', input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!! -1:0] a; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_lib_library.v:7:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_lib_library.v:7:45: Syntax error: extraneous input '-' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!! -1:0] a; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_lib_library.v:7:45:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_lib_library.v:7: Unknown macro "WIDTH". [ FATAL] : 0 [ SYNTAX] : 2 @@ -3806,7 +3794,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_tri_gate.v:36:2: Unknown macro "error". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_tri_gate.v:36:37: Syntax error: extraneous input '"Unknown test name"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, SURELOG_MACRO_NOT_DEFINED:error!!! "Unknown test name" - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_tri_gate.v:36:37:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_tri_gate.v:36: Unknown macro "error". [ FATAL] : 0 [ SYNTAX] : 1 @@ -3841,7 +3829,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_gen_missing.v:13:2: Unknown macro "error". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_gen_missing.v:13:37: Syntax error: extraneous input '"Bad Test"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, SURELOG_MACRO_NOT_DEFINED:error!!! "Bad Test" - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_gen_missing.v:13:37:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_gen_missing.v:13: Unknown macro "error". [ FATAL] : 0 [ SYNTAX] : 1 @@ -4116,13 +4104,13 @@ ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc.v:97:9: No default value fo [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc.v:651:8: Unknown macro "SV_COV_PARTIAL". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_inc2.vh:4:8: Syntax error: no viable alternative at input 'At file "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_inc2.vh"', At file "${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_inc2.vh" line 4 - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc.v:10:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc.v:29:4: Syntax error: no viable alternative at input 'text.', text. - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc.v:35:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc.v:84:1: Syntax error: mismatched input '$' expecting , $c("Zap(\"","bug2","\");"); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc.v:100:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 6 [ ERROR] : 28 @@ -4210,10 +4198,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_clk_concat6.v -l t_clk_concat6.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat6.v:97:3: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input clk; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat6.v:97:3:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat6.v:97:18: Syntax error: no viable alternative at input 'clk;', input clk; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat6.v:97:18:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -4588,10 +4576,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_circdef_bad.v:9:25: Unknown macro "SEL_NUM_BITS". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_circdef_bad.v:13:18: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '(*', '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, typedef logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! +: SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! -1:0] d_t; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_circdef_bad.v:13:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_circdef_bad.v:13:61: Syntax error: mismatched input '+:' expecting , typedef logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! +: SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! -1:0] d_t; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_pp_circdef_bad.v:13:61:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_pp_circdef_bad.v:13: Unknown macro "SEL_NUM_BITS". [ FATAL] : 0 [ SYNTAX] : 2 @@ -4800,10 +4788,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_clk_concat5.v -l t_clk_concat5.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat5.v:84:3: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input clk; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat5.v:84:3:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_clk_concat5.v:84:18: Syntax error: no viable alternative at input 'clk;', input clk; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_clk_concat5.v:84:18:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -4832,10 +4820,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:14:29: Unknown macro "error". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:9:37: Syntax error: extraneous input '"Test setup error, PREDEF_COMMAND_LINE pre-missing"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, SURELOG_MACRO_NOT_DEFINED:error!!! "Test setup error, PREDEF_COMMAND_LINE pre-missing" - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_undefineall.v:9:37:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:14:37: Syntax error: extraneous input '"Deleted too much, no PREDEF_COMMAND_LINE"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, SURELOG_MACRO_NOT_DEFINED:error!!! "Deleted too much, no PREDEF_COMMAND_LINE" - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_undefineall.v:14:37:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:9: Unknown macro "error". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_undefineall.v:14: Unknown macro "error". [ FATAL] : 0 @@ -4853,16 +4841,16 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:75:1: Unknown macro "error". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:75:52: Syntax error: missing '(' at 'choke', SURELOG_MACRO_NOT_DEFINED:error!!! Commercial sims choke on cross ref here - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:75:52:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:75:61: Syntax error: mismatched input 'cross' expecting '(', SURELOG_MACRO_NOT_DEFINED:error!!! Commercial sims choke on cross ref here - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:75:61:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:76:10: Syntax error: missing '(' at '.', isub.g.value = i_value; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:76:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:76:12: Syntax error: mismatched input '.' expecting ')', isub.g.value = i_value; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_interface_down_gen.v:76:12:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_interface_down_gen.v:75: Unknown macro "error". [ FATAL] : 0 [ SYNTAX] : 4 @@ -4890,7 +4878,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_preproc_inc_bad.v -l t_preproc_inc_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_preproc_inc_inc_bad.vh:10: Syntax error: no viable alternative at input 'xx // intentional error\n\nendmodule', endmodule -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_preproc_inc_bad.v:17:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -4930,7 +4918,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_var_rsvd.v -l t_var_rsvd.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_var_rsvd.v:24:8: Syntax error: mismatched input 'global' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, reg global; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_var_rsvd.v:24:8:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -5017,7 +5005,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_lint_rsvd_bad.v -l t_lint_rsvd_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_rsvd_bad.v:7: Syntax error: mismatched input 'endconfig' expecting {'design', 'localparam'}, endconfig -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_rsvd_bad.v:7:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -5123,22 +5111,22 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_enum_type_methods.v -l t_enum_type_methods.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:15:16: Syntax error: no viable alternative at input 'enum [', typedef enum [3:0] { - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:15:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:15:16: Syntax error: mismatched input '[' expecting {'{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, typedef enum [3:0] { - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:15:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:15:22: Syntax error: mismatched input '{' expecting ';', typedef enum [3:0] { - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:15:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:16:15: Syntax error: mismatched input '1' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, E01 = 1, - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:16:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:17:15: Syntax error: mismatched input '3' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, E03 = 3, - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:17:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_enum_type_methods.v:18:15: Syntax error: mismatched input '4' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, E04 = 4 - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_enum_type_methods.v:18:15:. + ^--. [ FATAL] : 0 [ SYNTAX] : 6 [ ERROR] : 0 @@ -5147,13 +5135,13 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_lint_in_inc_bad.v -l t_lint_in_inc_bad.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_in_inc_bad_2.vh:8:6: Syntax error: mismatched input 'if' expecting '(', if if if; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_in_inc_bad.v:18:6:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_in_inc_bad_2.vh:8:9: Syntax error: mismatched input 'if' expecting '(', if if if; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_in_inc_bad.v:18:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_lint_in_inc_bad_2.vh:8:11: Syntax error: mismatched input ';' expecting '(', if if if; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_lint_in_inc_bad.v:18:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -5205,7 +5193,7 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns t_langext_order_sub.v -l t_langext_order_sub.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_langext_order_sub.v:10:33: Syntax error: no viable alternative at input 'input do', module t_langext_order_sub(input do); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_langext_order_sub.v:10:33:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -5401,19 +5389,19 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:56:2: Unknown macro "verilog". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:49: Syntax error: extraneous input '#' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, #include "t_extend_class_c.h" // Header for contained object -^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:49:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:51:19: Syntax error: no viable alternative at input 't_extend_class_c*', t_extend_class_c* m_myobjp; // Pointer to object we are embedding - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:51:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:53:12: Syntax error: no viable alternative at input 'm_myobjp =', m_myobjp = new t_extend_class_c(); // Construct contained object - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:53:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:53:14: Syntax error: extraneous input 'new' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, m_myobjp = new t_extend_class_c(); // Construct contained object - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:53:14:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:53:34: Syntax error: missing '=' at '(', m_myobjp = new t_extend_class_c(); // Construct contained object - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_extend_class.v:53:34:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:48: Unknown macro "systemc_header". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:50: Unknown macro "systemc_interface". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_extend_class.v:52: Unknown macro "systemc_ctor". @@ -5435,10 +5423,10 @@ Processing: -cd . +incdir+. -parse -noelab -nocache -nobuiltin -nonote -noinfo - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_var.v:69:1: Unknown macro "verilog". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_var.v:67:2: Syntax error: no viable alternative at input 'module sub (/*AUTOARG*/\n // Outputs\n fr_a, fr_b, fr_chk,\n // Inputs\n in\n );\n\nSURELOG_MACRO_NOT_DEFINED:systemc_imp_header!!! \n void', void mon_class_name(const char* namep); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_var.v:67:2:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_var.v:67:2: Syntax error: mismatched input 'void' expecting , void mon_class_name(const char* namep); - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_dpi_var.v:67:2:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_dpi_var.v:66: Unknown macro "systemc_imp_header". [ FATAL] : 0 [ SYNTAX] : 2 @@ -5540,10 +5528,10 @@ Processing: -cd t_sv_cpu_code +incdir+. -parse -noelab -nocache -nobuiltin -nono [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/ports.sv:49:12: Unknown macro "PACKED". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/ports.sv:44:9: Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'}, struct SURELOG_MACRO_NOT_DEFINED:PACKED!!! - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/ports.sv:44:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/ports.sv:49:11: Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'}, struct SURELOG_MACRO_NOT_DEFINED:PACKED!!! - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/ports.sv:49:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 2 @@ -5572,10 +5560,10 @@ Processing: -cd t_sv_cpu_code +incdir+. -parse -noelab -nocache -nobuiltin -nono [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:35:7: Unknown macro "EOP". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:18:6: Syntax error: no viable alternative at input ''{\n SURELOG_MACRO_NOT_DEFINED:LDI!!!', SURELOG_MACRO_NOT_DEFINED:LDI!!! - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/rom.sv:18:6:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:36:6: Syntax error: mismatched input '}' expecting , }; - ^-- ${SURELOG_DIR}/build/regression/Verilator/slpp_all/lib/work/t_sv_cpu_code/rom.sv:36:6:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:18: Unknown macro "LDI". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:19: Unknown macro "LDI". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Verilator/t_sv_cpu_code/rom.sv:20: Unknown macro "LDI". @@ -5650,7 +5638,7 @@ Processing: -cd t_sv_bus_mux_demux +incdir+. -parse -noelab -nocache -nobuiltin [ NOTE] : 0 Processed 837 tests. [ FATAL] : 0 -[ SYNTAX] : 140 +[ SYNTAX] : 136 [ ERROR] : 154 [WARNING] : 43 [ NOTE] : 0 diff --git a/third_party/tests/Yosys/Yosys.log b/third_party/tests/Yosys/Yosys.log index 75da9257b6..a0d13254a2 100644 --- a/third_party/tests/Yosys/Yosys.log +++ b/third_party/tests/Yosys/Yosys.log @@ -819,7 +819,7 @@ Processing: -cd hana +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -times Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err11.v -l syntax_err11.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err11.v:2:18: Syntax error: extraneous input 'real' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, parameter integer real x=0; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err11.v:2:18:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -828,7 +828,7 @@ parameter integer real x=0; Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err07.v -l syntax_err07.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err07.v:4:14: Syntax error: extraneous input '55' expecting ';', assign y = (4)55; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err07.v:4:14:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -843,10 +843,10 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err02.v -l syntax_err02.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err02.v:3:16: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', input integer [3:0]x - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err02.v:3:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err02.v:3:21: Syntax error: extraneous input 'x' expecting ')', input integer [3:0]x - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err02.v:3:21:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -855,13 +855,13 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err10.v -l syntax_err10.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err10.v:2:18: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', parameter integer [2:0]x=0; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err10.v:2:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err10.v:2:23: Syntax error: missing ';' at 'x', parameter integer [2:0]x=0; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err10.v:2:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err10.v:2:25: Syntax error: mismatched input '0' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, parameter integer [2:0]x=0; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err10.v:2:25:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -870,10 +870,10 @@ parameter integer [2:0]x=0; Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err05.v -l syntax_err05.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err05.v:2: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input x[2:0]; -^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err05.v:2:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err05.v:2:12: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', input x[2:0]; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err05.v:2:12:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -890,10 +890,10 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err01.v -l syntax_err01.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err01.v:2:8: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', integer [31:0]w; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err01.v:2:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err01.v:2:14: Syntax error: extraneous input 'w' expecting ';', integer [31:0]w; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err01.v:2:14:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -908,7 +908,7 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err08.v -l syntax_err08.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err08.v:4:13: Syntax error: no viable alternative at input 'x 55', assign y = x 55; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err08.v:4:13:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -917,7 +917,7 @@ assign y = x 55; Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err04.v -l syntax_err04.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err04.v:2:7: Syntax error: mismatched input ']' expecting ':', wire [3]x; - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err04.v:2:7:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -932,7 +932,7 @@ Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim Processing: -cd errors +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns syntax_err03.v -l syntax_err03.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/errors/syntax_err03.v:3:10: Syntax error: mismatched input ']' expecting ':', input [3]x - ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/errors/syntax_err03.v:3:10:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 diff --git a/third_party/tests/YosysTestSuite/YosysTestSuite.log b/third_party/tests/YosysTestSuite/YosysTestSuite.log index 9dcf35c91c..aba3708fca 100644 --- a/third_party/tests/YosysTestSuite/YosysTestSuite.log +++ b/third_party/tests/YosysTestSuite/YosysTestSuite.log @@ -152,10 +152,10 @@ Processing: -cd asicworld code_verilog_tutorial_first_counter_tb.v -writepp -par [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_first_counter_tb.v:9:17: Unknown macro "outfile". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_first_counter_tb.v:9:16: Syntax error: no viable alternative at input 'module testbench();\n// Declare inputs as regs and outputs as wires\nreg clock = 1, reset = 0, enable = 0;\nwire [3:0] counter_out;\ninteger file;\n\n// Initialize all variables\ninitial begin \n file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_first_counter_tb.v:9:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_first_counter_tb.v:8: Syntax error: mismatched input 'initial' expecting , initial begin -^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_first_counter_tb.v:8:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 @@ -219,10 +219,10 @@ Processing: -cd asicworld code_verilog_tutorial_fsm_full_tb.v -writepp -parse -n [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_fsm_full_tb.v:10:17: Unknown macro "outfile". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_fsm_full_tb.v:10:16: Syntax error: no viable alternative at input 'module testbench();\nreg clock = 0 , reset ;\nreg req_0 , req_1 , req_2 , req_3; \nwire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;\ninteger file;\n\ninitial begin\n // $dumpfile("testbench.vcd");\n // $dumpvars(0, testbench);\n file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_fsm_full_tb.v:10:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_fsm_full_tb.v:7: Syntax error: mismatched input 'initial' expecting , initial begin -^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_fsm_full_tb.v:7:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 @@ -358,10 +358,10 @@ Processing: -cd asicworld code_verilog_tutorial_counter_tb.v -writepp -parse -no [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_counter_tb.v:34:16: Unknown macro "outfile". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_counter_tb.v:34:14: Syntax error: mismatched input '(' expecting ';', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_counter_tb.v:34:14:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_counter_tb.v:34:52: Syntax error: extraneous input ')' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_verilog_tutorial_counter_tb.v:34:52:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_verilog_tutorial_counter_tb.v:34: Unknown macro "outfile". [ FATAL] : 0 [ SYNTAX] : 2 @@ -534,10 +534,10 @@ Processing: -cd asicworld code_hdl_models_arbiter_tb.v -writepp -parse -nocache [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_hdl_models_arbiter_tb.v:22:17: Unknown macro "outfile". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_hdl_models_arbiter_tb.v:22:16: Syntax error: no viable alternative at input 'module testbench ();\n\nreg clk = 0;\nreg rst = 1;\nreg req3 = 0;\nreg req2 = 0;\nreg req1 = 0;\nreg req0 = 0;\nwire gnt3; \nwire gnt2; \nwire gnt1; \nwire gnt0; \n\n// Clock generator\nalways #1 clk = ~clk;\ninteger file;\n\nalways @(posedge clk)\n $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});\n\ninitial begin\n file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!', file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_hdl_models_arbiter_tb.v:22:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/asicworld/code_hdl_models_arbiter_tb.v:15: Syntax error: mismatched input 'always' expecting , always #1 clk = ~clk; -^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/asicworld/code_hdl_models_arbiter_tb.v:15:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 1 @@ -576,7 +576,7 @@ Processing: -cd opt opt_share_extend.v -writepp -parse -nocache -nobuiltin -nono Processing: -cd opt opt_share_cat_multiuser.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_cat_multiuser.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/opt/opt_share_cat_multiuser.v:8:2: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/opt/opt_share_cat_multiuser.v:8:2:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -585,10 +585,10 @@ Processing: -cd opt opt_share_cat_multiuser.v -writepp -parse -nocache -nobuilti Processing: -cd opt opt_expr_cmp.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_expr_cmp.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/opt/opt_expr_cmp.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/opt/opt_expr_cmp.v:1:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/opt/opt_expr_cmp.v:2:2: Syntax error: mismatched input 'input' expecting , input [3:0] a; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/opt/opt_expr_cmp.v:2:2:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -603,7 +603,7 @@ Processing: -cd opt opt_share_large_pmux_part.v -writepp -parse -nocache -nobuil Processing: -cd opt opt_share_add_sub.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_add_sub.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/opt/opt_share_add_sub.v:6:2: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/opt/opt_share_add_sub.v:6:2:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -618,7 +618,7 @@ Processing: -cd opt opt_share_diff_port_widths.v -writepp -parse -nocache -nobui Processing: -cd opt opt_share_cat.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_cat.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/opt/opt_share_cat.v:8:2: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/opt/opt_share_cat.v:8:2:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -851,7 +851,7 @@ Processing: -cd hana test_simulation_decoder.v -writepp -parse -nocache -nobuilt Processing: -cd errors syntax_err11.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err11.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err11.v:2:18: Syntax error: extraneous input 'real' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, parameter integer real x=0; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err11.v:2:18:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -860,7 +860,7 @@ parameter integer real x=0; Processing: -cd errors syntax_err07.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err07.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err07.v:4:14: Syntax error: extraneous input '55' expecting ';', assign y = (4)55; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err07.v:4:14:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -875,10 +875,10 @@ Processing: -cd errors syntax_err13.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd errors syntax_err02.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err02.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err02.v:3:16: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', input integer [3:0]x - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err02.v:3:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err02.v:3:21: Syntax error: extraneous input 'x' expecting ')', input integer [3:0]x - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err02.v:3:21:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -887,13 +887,13 @@ Processing: -cd errors syntax_err02.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd errors syntax_err10.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err10.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err10.v:2:18: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', parameter integer [2:0]x=0; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err10.v:2:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err10.v:2:23: Syntax error: missing ';' at 'x', parameter integer [2:0]x=0; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err10.v:2:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err10.v:2:25: Syntax error: mismatched input '0' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, parameter integer [2:0]x=0; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err10.v:2:25:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -902,10 +902,10 @@ parameter integer [2:0]x=0; Processing: -cd errors syntax_err05.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err05.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err05.v:2: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input x[2:0]; -^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err05.v:2:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err05.v:2:12: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', input x[2:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err05.v:2:12:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -922,10 +922,10 @@ Processing: -cd errors syntax_err06.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd errors syntax_err01.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err01.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err01.v:2:8: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '[', integer [31:0]w; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err01.v:2:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err01.v:2:14: Syntax error: extraneous input 'w' expecting ';', integer [31:0]w; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err01.v:2:14:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -940,7 +940,7 @@ Processing: -cd errors syntax_err09.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd errors syntax_err08.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err08.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err08.v:4:13: Syntax error: no viable alternative at input 'x 55', assign y = x 55; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err08.v:4:13:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -949,7 +949,7 @@ assign y = x 55; Processing: -cd errors syntax_err04.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err04.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err04.v:2:7: Syntax error: mismatched input ']' expecting ':', wire [3]x; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err04.v:2:7:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -964,7 +964,7 @@ Processing: -cd errors syntax_err12.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd errors syntax_err03.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err03.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/errors/syntax_err03.v:3:10: Syntax error: mismatched input ']' expecting ':', input [3]x - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/errors/syntax_err03.v:3:10:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -1012,34 +1012,34 @@ Processing: -cd svinterfaces svinterface_at_top_tb_wrapper.v -writepp -parse -no Processing: -cd svinterfaces svinterface_at_top_wrapper.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface_at_top_wrapper.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:16:2: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:16:2:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:26:5: Syntax error: no viable alternative at input 'TopModule u_dut (\n .clk(clk),\n .rst(rst),\n .outOther(outOther),\n .sig(sig),\n .flip(flip),\n .passThrough(passThrough),\n .\', .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:26:5:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:20:4: Syntax error: no viable alternative at input '(\n .', .clk(clk), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:20:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:20:12: Syntax error: extraneous input ')' expecting ',', .clk(clk), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:20:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:21:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .rst(rst), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:21:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:22:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .outOther(outOther), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:22:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:23:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .sig(sig), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:23:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:24:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .flip(flip), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:24:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:25:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .passThrough(passThrough), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:25:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svinterfaces/svinterface_at_top_wrapper.v:26:4: Syntax error: mismatched input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svinterfaces/svinterface_at_top_wrapper.v:26:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -1054,10 +1054,10 @@ Processing: -cd various attrib05_port_conn.v -writepp -parse -nocache -nobuiltin Processing: -cd various shregmap.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l shregmap.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/shregmap.v:15:7: Syntax error: no viable alternative at input 'module $', module $__SHREG_DFF_P_(input C, D, output Q); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/shregmap.v:15:7:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/shregmap.v:19: Syntax error: mismatched input 'always' expecting , always @(posedge C) -^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/shregmap.v:19:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1114,10 +1114,10 @@ Processing: -cd various attrib07_func_call.v -elabuhdm -writepp -parse -nocache Processing: -cd various constmsk_testmap.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l constmsk_testmap.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/constmsk_testmap.v:2:25: Syntax error: no viable alternative at input '(* techmap_celltype = "$reduce_or" *)\nmodule my_opt_reduce_or(..', module my_opt_reduce_or(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/constmsk_testmap.v:2:25:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/various/constmsk_testmap.v:7:4: Syntax error: mismatched input 'input' expecting , input [A_WIDTH-1:0] A; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/various/constmsk_testmap.v:7:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1150,7 +1150,7 @@ Processing: -cd arch/common add_sub.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd arch/common mul.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mul.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/common/mul.v:7: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); -^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/common/mul.v:7:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -1225,10 +1225,10 @@ Processing: -cd arch/xilinx macc.v -writepp -parse -nocache -nobuiltin -nonote - Processing: -cd arch/xilinx macc_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l macc_tb.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/macc_tb.v:8:1: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, output signed [SIZEOUT-1:0] REF_accum_out, accum_out; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/macc_tb.v:8:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/macc_tb.v:9:1: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, output REF_overflow, overflow; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/macc_tb.v:9:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1237,16 +1237,16 @@ Processing: -cd arch/xilinx macc_tb.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd arch/xilinx xilinx_srl.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l xilinx_srl.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:29:7: Syntax error: no viable alternative at input 'module $', module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:29:7:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:29:54: Syntax error: extraneous input 'output' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:29:54:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:29:62: Syntax error: extraneous input ')' expecting ';', module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:29:62:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/arch/xilinx/xilinx_srl.v:36: Syntax error: mismatched input 'always' expecting , always @(posedge C) -^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/arch/xilinx/xilinx_srl.v:36:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 4 [ ERROR] : 0 @@ -1453,22 +1453,22 @@ Processing: -cd techmap mem_simple_4x1_uut.v -writepp -parse -nocache -nobuiltin Processing: -cd rpc design.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l design.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:7:1: Syntax error: no viable alternative at input 'python_inv #(\n\t .width(4)\n\t) inv (\n\t\t.i(i),\n\t\t.o(o),\n\t)', ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:7:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:3:10: Syntax error: no viable alternative at input '(4', .width(4) - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:3:10:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:5:2: Syntax error: no viable alternative at input '(\n\t\t.', .i(i), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:5:2:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:5:6: Syntax error: extraneous input ')' expecting ',', .i(i), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:5:6:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:6:2: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .o(o), - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:6:2:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/rpc/design.v:7:1: Syntax error: mismatched input ')' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, ); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/rpc/design.v:7:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 6 [ ERROR] : 0 @@ -1477,10 +1477,10 @@ Processing: -cd rpc design.v -writepp -parse -nocache -nobuiltin -nonote -noinfo Processing: -cd lut map_not.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_not.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_not.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_not.v:1:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_not.v:2:4: Syntax error: mismatched input 'input' expecting , input a; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_not.v:2:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1489,10 +1489,10 @@ module top(...); Processing: -cd lut map_xor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_xor.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_xor.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_xor.v:1:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_xor.v:2:4: Syntax error: mismatched input 'input' expecting , input a, b; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_xor.v:2:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1501,10 +1501,10 @@ module top(...); Processing: -cd lut map_cmp.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_cmp.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_cmp.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_cmp.v:1:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_cmp.v:3:1: Syntax error: mismatched input 'input' expecting , input [LUT_WIDTH-1:0] a; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_cmp.v:3:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1513,10 +1513,10 @@ module top(...); Processing: -cd lut map_mux.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_mux.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_mux.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_mux.v:1:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_mux.v:2:4: Syntax error: mismatched input 'input' expecting , input a, b, s; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_mux.v:2:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1525,10 +1525,10 @@ module top(...); Processing: -cd lut map_and.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_and.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_and.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_and.v:1:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_and.v:2:4: Syntax error: mismatched input 'input' expecting , input a, b; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_and.v:2:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1537,10 +1537,10 @@ module top(...); Processing: -cd lut map_or.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_or.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_or.v:1:12: Syntax error: no viable alternative at input 'module top(..', module top(...); - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_or.v:1:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/lut/map_or.v:2:4: Syntax error: mismatched input 'input' expecting , input a, b; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/lut/map_or.v:2:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2030,10 +2030,10 @@ Processing: -cd sva basic03.sv -writepp -parse -nocache -nobuiltin -nonote -noin Processing: -cd svtypes typedef_memory_2.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_memory_2.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_memory_2.sv:4:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, (nibble) mem[0:15]; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_memory_2.sv:4:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_memory_2.sv:4:19: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', (nibble) mem[0:15]; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_memory_2.sv:4:19:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2042,34 +2042,34 @@ Processing: -cd svtypes typedef_memory_2.sv -writepp -parse -nocache -nobuiltin Processing: -cd svtypes typedef_param.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_param.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:9:9: Syntax error: extraneous input '(' expecting {'interface', 'virtual', 'class', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, typedef (int8_t) char_t; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:9:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:9:16: Syntax error: no viable alternative at input 'int8_t)', typedef (int8_t) char_t; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:9:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:11:11: Syntax error: extraneous input '(' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, parameter (uint2_t) int2 = 2'b10; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:11:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:11:19: Syntax error: mismatched input ')' expecting ';', parameter (uint2_t) int2 = 2'b10; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:11:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:11:28: Syntax error: mismatched input '2'b10' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, parameter (uint2_t) int2 = 2'b10; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:11:28:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:12:12: Syntax error: extraneous input '(' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, localparam (int4_t) int4 = -1; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:12:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:12:19: Syntax error: mismatched input ')' expecting ';', localparam (int4_t) int4 = -1; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:12:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:12:28: Syntax error: mismatched input '-' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, localparam (int4_t) int4 = -1; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:12:28:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:13:12: Syntax error: extraneous input '(' expecting {'virtual', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, localparam (int8_t) int8 = int4; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:13:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_param.sv:13:19: Syntax error: mismatched input ')' expecting ';', localparam (int8_t) int8 = int4; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_param.sv:13:19:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -2078,31 +2078,31 @@ Processing: -cd svtypes typedef_param.sv -writepp -parse -nocache -nobuiltin -no Processing: -cd svtypes typedef_scopes.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_scopes.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:6:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, (outer_uint4_t) u4_i = 8'hA5; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:6:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:6:15: Syntax error: no viable alternative at input 'outer_uint4_t)', (outer_uint4_t) u4_i = 8'hA5; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:6:15:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:6:24: Syntax error: mismatched input '8'hA5' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (outer_uint4_t) u4_i = 8'hA5; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:6:24:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:10:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, (inner_type) inner_i1 = 8'h5A; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:10:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:10:25: Syntax error: mismatched input '8'h5A' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (inner_type) inner_i1 = 8'h5A; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:10:25:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:15:2: Syntax error: extraneous input '(' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, (inner_type) inner_gb_i = 8'hA5; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:15:2:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:15:28: Syntax error: mismatched input '8'hA5' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (inner_type) inner_gb_i = 8'hA5; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:15:28:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:19:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, (inner_type) inner_i2 = 8'h42; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:19:1:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_scopes.sv:19:25: Syntax error: mismatched input '8'h42' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (inner_type) inner_i2 = 8'h42; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_scopes.sv:19:25:. + ^--. [ FATAL] : 0 [ SYNTAX] : 9 [ ERROR] : 0 @@ -2111,34 +2111,34 @@ Processing: -cd svtypes typedef_scopes.sv -writepp -parse -nocache -nobuiltin -n Processing: -cd svtypes typedef_simple.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_simple.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:6:9: Syntax error: extraneous input '(' expecting {'interface', 'virtual', 'class', 'type', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', DOLLAR_UNIT, 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, typedef (int8_t) char_t; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:6:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:6:16: Syntax error: no viable alternative at input 'int8_t)', typedef (int8_t) char_t; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:6:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:8:12: Syntax error: no viable alternative at input '(* keep *) (', (* keep *) (uint2_t) int2 = 2'b10; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:8:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:8:29: Syntax error: mismatched input '2'b10' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (* keep *) (uint2_t) int2 = 2'b10; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:8:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:9:12: Syntax error: no viable alternative at input '(* keep *) (', (* keep *) (int4_t) int4 = -1; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:9:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:9:28: Syntax error: mismatched input '-' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (* keep *) (int4_t) int4 = -1; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:9:28:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:10:12: Syntax error: no viable alternative at input '(* keep *) (', (* keep *) (int8_t) int8 = int4; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:10:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:10:32: Syntax error: mismatched input ';' expecting '=', (* keep *) (int8_t) int8 = int4; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:10:32:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:11:12: Syntax error: no viable alternative at input '(* keep *) (', (* keep *) (char_t) ch = int8; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:11:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_simple.sv:11:30: Syntax error: mismatched input ';' expecting '=', (* keep *) (char_t) ch = int8; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_simple.sv:11:30:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -2147,7 +2147,7 @@ Processing: -cd svtypes typedef_simple.sv -writepp -parse -nocache -nobuiltin -n Processing: -cd svtypes typedef_memory.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_memory.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_memory.sv:4:1: Syntax error: extraneous input '(' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, (ram16x4_t) mem; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_memory.sv:4:1:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -2156,10 +2156,10 @@ Processing: -cd svtypes typedef_memory.sv -writepp -parse -nocache -nobuiltin -n Processing: -cd svtypes typedef_package.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_package.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_package.sv:7:12: Syntax error: no viable alternative at input '(* keep *) (', (* keep *) (pkg::uint8_t) a = 8'hAA; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_package.sv:7:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTestSuite/svtypes/typedef_package.sv:7:31: Syntax error: mismatched input '8'hAA' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, (* keep *) (pkg::uint8_t) a = 8'hAA; - ^-- ${SURELOG_DIR}/build/regression/YosysTestSuite/slpp_all/lib/work/svtypes/typedef_package.sv:7:31:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 diff --git a/third_party/tests/YosysTests/YosysTests.log b/third_party/tests/YosysTests/YosysTests.log index d35a49f616..6b83fa372e 100644 --- a/third_party/tests/YosysTests/YosysTests.log +++ b/third_party/tests/YosysTests/YosysTests.log @@ -746,10 +746,10 @@ Processing: -cd misc/stat_error top.v -writepp -parse -nocache -nobuiltin -nonot Processing: -cd misc/miter_assert_assume top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/miter_assert_assume/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/miter_assert_assume/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/miter_assert_assume/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/miter_assert_assume/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1017,10 +1017,10 @@ Processing: -cd misc/plugin_error top.v -writepp -parse -nocache -nobuiltin -non Processing: -cd misc/splitnets_logic top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/splitnets_logic/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/splitnets_logic/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/splitnets_logic/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/splitnets_logic/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1086,10 +1086,10 @@ Processing: -cd misc/insbuf testbench.v -writepp -parse -nocache -nobuiltin -non Processing: -cd misc/fmcombine_assert_assume top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/fmcombine_assert_assume/top.v:58:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/fmcombine_assert_assume/top.v:58:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/fmcombine_assert_assume/top.v:65:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/fmcombine_assert_assume/top.v:65:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1230,10 +1230,10 @@ Processing: -cd misc/rmports top.v -writepp -parse -nocache -nobuiltin -nonote - Processing: -cd misc/chformal top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1332,10 +1332,10 @@ Processing: -cd misc/history top.v -writepp -parse -nocache -nobuiltin -nonote - Processing: -cd misc/chformal_error top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal_error/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal_error/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/misc/chformal_error/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/misc/chformal_error/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1564,10 +1564,10 @@ Processing: -cd frontends/read_aiger top2.v -writepp -parse -nocache -nobuiltin [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_aiger/aig.map". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_aiger/top2.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_aiger/top2.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_aiger/top2.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_aiger/top2.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -1869,7 +1869,7 @@ Processing: -cd frontends/verilog_defaults_error testbench.v -writepp -parse -no Processing: -cd frontends/verilog_lexer_enum_typedef top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_enum_typedef/top.v:117: Syntax error: extraneous input 'endmodule' expecting , endmodule -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_enum_typedef/top.v:117:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -1910,10 +1910,10 @@ Processing: -cd frontends/read_ilang_mux testbench.v -writepp -parse -nocache -n Processing: -cd frontends/read_verilog_assert top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_verilog_assert/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_verilog_assert/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/read_verilog_assert/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/read_verilog_assert/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2130,10 +2130,10 @@ Processing: -cd frontends/read_verilog_mem testbench.v -writepp -parse -nocache Processing: -cd frontends/verilog_lexer_supply top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_supply/top.v:90:12: Syntax error: mismatched input ')' expecting ',', buf (supply1) g1 (y, a); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_supply/top.v:90:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_supply/top.v:91:12: Syntax error: mismatched input ')' expecting ',', buf (supply0) g2 (y, b); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_supply/top.v:91:12:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2480,10 +2480,10 @@ Processing: -cd frontends/verilog_lexer_assert_assume_restrict top.v -writepp -p Processing: -cd frontends/verilog_lexer_assert_assume_restrict top2.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top2.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_assert_assume_restrict/top2.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_assert_assume_restrict/top2.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_assert_assume_restrict/top2.v:37:11: Syntax error: extraneous input 'eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_assert_assume_restrict/top2.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -2579,7 +2579,7 @@ Processing: -cd frontends/read_liberty_ff_pn testbench.v -writepp -parse -nocach Processing: -cd frontends/verilog_lexer_package top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/frontends/verilog_lexer_package/top.v:18: Syntax error: mismatched input '{' expecting , {* AAA *} -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/frontends/verilog_lexer_package/top.v:18:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -2895,16 +2895,16 @@ Processing: -cd backends/write_simplec_mux testbench.v -writepp -parse -nocache Processing: -cd backends/write_xaiger_error top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:37:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:74:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:74:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top.v:81:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top.v:81:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 4 [ ERROR] : 0 @@ -2913,10 +2913,10 @@ Processing: -cd backends/write_xaiger_error top.v -writepp -parse -nocache -nobu Processing: -cd backends/write_xaiger_error top2.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top2.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top2.v:31:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top2.v:31:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger_error/top2.v:38:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger_error/top2.v:38:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -3167,10 +3167,10 @@ Processing: -cd backends/write_firrtl_reduce testbench.v -writepp -parse -nocach Processing: -cd backends/write_btor top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor/top.v:32:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor/top.v:32:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor/top.v:39:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor/top.v:39:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -3656,10 +3656,10 @@ Processing: -cd backends/write_firrtl_fsm testbench.v -writepp -parse -nocache - Processing: -cd backends/write_smt2_init_assert top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_smt2_init_assert/top.v:32:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_smt2_init_assert/top.v:32:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_smt2_init_assert/top.v:39:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_smt2_init_assert/top.v:39:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -3971,10 +3971,10 @@ Processing: -cd backends/write_intersynth_error top.v -writepp -parse -nocache - Processing: -cd backends/write_intersynth_error top2.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top2.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_intersynth_error/top2.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_intersynth_error/top2.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_intersynth_error/top2.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_intersynth_error/top2.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -4017,10 +4017,10 @@ Processing: -cd backends/write_smt2_logic testbench.v -writepp -parse -nocache - Processing: -cd backends/write_aiger top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -4046,16 +4046,16 @@ Processing: -cd backends/write_aiger top_clean.v -writepp -parse -nocache -nobui Processing: -cd backends/write_aiger_error top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:37:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:74:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:74:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top.v:81:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top.v:81:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 4 [ ERROR] : 0 @@ -4064,10 +4064,10 @@ Processing: -cd backends/write_aiger_error top.v -writepp -parse -nocache -nobui Processing: -cd backends/write_aiger_error top2.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top2.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top2.v:31:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top2.v:31:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_aiger_error/top2.v:38:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_aiger_error/top2.v:38:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -4093,10 +4093,10 @@ Processing: -cd backends/write_aiger_error top_clean.v -writepp -parse -nocache Processing: -cd backends/write_btor_init_assert top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor_init_assert/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor_init_assert/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_btor_init_assert/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_btor_init_assert/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -4227,10 +4227,10 @@ Processing: -cd backends/write_btor_and_or testbench.v -writepp -parse -nocache Processing: -cd backends/write_xaiger top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger/top.v:30:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assume(s_eventually too); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger/top.v:30:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/backends/write_xaiger/top.v:37:11: Syntax error: extraneous input 's_eventually' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, assert(s_eventually ASSERT); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/backends/write_xaiger/top.v:37:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -5139,34 +5139,34 @@ Processing: -cd architecture/synth_xilinx_srl ug901a.v -writepp -parse -nocache Processing: -cd architecture/synth_xilinx_srl sr_fixed_length_other_users_port.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sr_fixed_length_other_users_port.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:7:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:7:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:18: Syntax error: mismatched input '[' expecting ''', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:31: Syntax error: mismatched input ';' expecting '=', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:10:31:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:45:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:30: Syntax error: no viable alternative at input '(.', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:30:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:36: Syntax error: extraneous input ')' expecting ',', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:36:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:41: Syntax error: mismatched input '(' expecting {',', ')'}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:57: Syntax error: no viable alternative at input '(1'b1', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:70: Syntax error: mismatched input '[' expecting ''', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v:12:70:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5187,34 +5187,34 @@ Processing: -cd architecture/synth_xilinx_srl rotate_3.v -writepp -parse -nocach Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:6:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:6:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:18: Syntax error: mismatched input '[' expecting ''', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:31: Syntax error: mismatched input ';' expecting '=', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:9:31:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:45: Syntax error: no viable alternative at input '#~@$_DFF_PP0_#~@r(.C(clk), .D(int[', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:45:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:30: Syntax error: no viable alternative at input '(.', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:30:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:36: Syntax error: extraneous input ')' expecting ',', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:36:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:41: Syntax error: mismatched input '(' expecting {',', ')'}, #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:58: Syntax error: extraneous input ')' expecting ',', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:58:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:61: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v:11:61:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5223,25 +5223,25 @@ Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_infe Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_inferred_N_width.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l neg_clk_no_enable_with_init_with_inferred_N_width.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:6:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:6:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:11:23: Syntax error: no viable alternative at input 'int[', initial int[w][d] <= ~((d+w) % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:11:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:14:37: Syntax error: no viable alternative at input 'int[', always @(negedge clk) int[w] <= i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:14:37:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:15:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:15:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:17:8: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, else begin - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:17:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:18:37: Syntax error: no viable alternative at input 'int[', always @(negedge clk) int[w] <= { int[w][depth-2:0], i[w] }; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:18:37:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:19:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w][depth-1]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v:19:29:. + ^--. [ FATAL] : 0 [ SYNTAX] : 7 [ ERROR] : 0 @@ -5250,34 +5250,34 @@ Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_i Processing: -cd architecture/synth_xilinx_srl test21b.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test21b.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:3:20: Syntax error: mismatched input 'int' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, reg [depth-1:0] int; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:3:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:7:19: Syntax error: no viable alternative at input 'int[', initial int[d] <= ~(d % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:7:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:7:19: Syntax error: extraneous input '[' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, initial int[d] <= ~(d % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:7:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:7:21: Syntax error: mismatched input ']' expecting ';', initial int[d] <= ~(d % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:7:21:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:10:41: Syntax error: no viable alternative at input 'int <=', always @(negedge clk) if (e) int <= ~^i[width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:10:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:11:22: Syntax error: no viable alternative at input 'int;', assign q = int; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:11:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:13:4: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, else begin - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:13:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:14:41: Syntax error: no viable alternative at input 'int <=', always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] }; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:14:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:14:41: Syntax error: mismatched input '<=' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] }; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:14:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21b.v:14:49: Syntax error: extraneous input '[' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] }; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21b.v:14:49:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5286,34 +5286,34 @@ Processing: -cd architecture/synth_xilinx_srl test21b.v -writepp -parse -nocache Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_inferred_with_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l pos_clk_no_enable_no_init_not_inferred_with_reset.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:6:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:6:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:18: Syntax error: mismatched input '[' expecting ''', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:31: Syntax error: mismatched input ';' expecting '=', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:9:31:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:45: Syntax error: no viable alternative at input '#~@$_DFF_PP0_#~@r(.C(clk), .D(int[', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:45:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:30: Syntax error: no viable alternative at input '(.', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:30:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:36: Syntax error: extraneous input ')' expecting ',', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:36:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:41: Syntax error: mismatched input '(' expecting {',', ')'}, #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:58: Syntax error: extraneous input ')' expecting ',', #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:58:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:61: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFF_PP0_#~@r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v:11:61:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5334,28 +5334,28 @@ Processing: -cd architecture/synth_xilinx_srl multien.v -writepp -parse -nocache Processing: -cd architecture/synth_xilinx_srl sr_var_length_other_users_port.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sr_var_length_other_users_port.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:7:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:7:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:12:23: Syntax error: no viable alternative at input 'int[', initial int[w][d] <= ~((d+w) % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:12:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:15:44: Syntax error: no viable alternative at input 'int[', always @(negedge clk) if (e) int[w] <= i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:15:44:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:16:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:16:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:18:8: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, else begin - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:18:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:19:44: Syntax error: no viable alternative at input 'int[', always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }}; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:19:44:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:20:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w][l]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:20:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:23:22: Syntax error: no viable alternative at input 'int[', assign state = int[0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v:23:22:. + ^--. [ FATAL] : 0 [ SYNTAX] : 8 [ ERROR] : 0 @@ -5364,34 +5364,34 @@ Processing: -cd architecture/synth_xilinx_srl sr_var_length_other_users_port.v - Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:6:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:6:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:11:23: Syntax error: no viable alternative at input 'int[', initial int[w][d] <= ~((d+w) % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:11:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:57: Syntax error: no viable alternative at input 'int[', always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:70: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:14:70:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:15:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:15:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:17:8: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, else begin - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:17:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:57: Syntax error: no viable alternative at input 'int[', always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }}; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:79: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }}; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:18:79:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:19:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w][l]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:19:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:21:4: Syntax error: extraneous input 'end' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, end - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v:21:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5400,34 +5400,34 @@ Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_i Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_inferred_N_width.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l pos_clk_no_enable_no_init_not_inferred_N_width.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:6:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:6:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:18: Syntax error: mismatched input '[' expecting ''', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:31: Syntax error: mismatched input ';' expecting '=', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:9:31:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:45:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:30: Syntax error: no viable alternative at input '(.', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:30:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:36: Syntax error: extraneous input ')' expecting ',', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:36:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:41: Syntax error: mismatched input '(' expecting {',', ')'}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:57: Syntax error: no viable alternative at input '(1'b0', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:70: Syntax error: mismatched input '[' expecting ''', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v:11:70:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5436,28 +5436,28 @@ Processing: -cd architecture/synth_xilinx_srl pos_clk_no_enable_no_init_not_infe Processing: -cd architecture/synth_xilinx_srl sr_var_length_other_users_xor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sr_var_length_other_users_xor.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:7:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:7:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:12:23: Syntax error: no viable alternative at input 'int[', initial int[w][d] <= ~((d+w) % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:12:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:15:44: Syntax error: no viable alternative at input 'int[', always @(negedge clk) if (e) int[w] <= i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:15:44:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:16:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:16:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:18:8: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, else begin - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:18:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:19:44: Syntax error: no viable alternative at input 'int[', always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }}; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:19:44:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:20:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w][l]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:20:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:23:30: Syntax error: no viable alternative at input '{^int[', assign state = {depth{^int[0]}}; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v:23:30:. + ^--. [ FATAL] : 0 [ SYNTAX] : 8 [ ERROR] : 0 @@ -5504,34 +5504,34 @@ Processing: -cd architecture/synth_xilinx_srl test17b.v -writepp -parse -nocache Processing: -cd architecture/synth_xilinx_srl neg_clk_no_enable_with_init_with_inferred_with_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l neg_clk_no_enable_with_init_with_inferred_with_reset.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:6:20: Syntax error: no viable alternative at input 'reg [depth-1:0] int', reg [depth-1:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:6:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:11:23: Syntax error: no viable alternative at input 'int[', initial int[w][d] <= ~((d+w) % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:11:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:57: Syntax error: no viable alternative at input 'int[', always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:70: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:14:70:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:15:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:15:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:17:8: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, else begin - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:17:8:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:57: Syntax error: no viable alternative at input 'int[', always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] }; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:79: Syntax error: extraneous input 'else' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'end', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] }; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:18:79:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:19:29: Syntax error: no viable alternative at input 'int[', assign q[w] = int[w][depth-1]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:19:29:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:21:4: Syntax error: extraneous input 'end' expecting {';', 'default', 'extern', 'interface', 'virtual', 'class', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'rand', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'modport', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'begin', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'endgenerate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, end - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v:21:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5573,34 +5573,34 @@ Processing: -cd architecture/synth_xilinx_srl multiclock_var_len.v -writepp -par Processing: -cd architecture/synth_xilinx_srl sr_fixed_length_other_users_xor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sr_fixed_length_other_users_xor.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:7:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int [width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:7:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:18: Syntax error: mismatched input '[' expecting ''', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:31: Syntax error: mismatched input ';' expecting '=', assign int[w][0] = i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:10:31:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:45:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:30: Syntax error: no viable alternative at input '(.', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:30:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:36: Syntax error: extraneous input ')' expecting ',', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:36:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:41: Syntax error: mismatched input '(' expecting {',', ')'}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:41:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:57: Syntax error: no viable alternative at input '(1'b1', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:70: Syntax error: mismatched input '[' expecting ''', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v:12:70:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5615,34 +5615,34 @@ Processing: -cd architecture/synth_xilinx_srl multiclock.v -writepp -parse -noca Processing: -cd architecture/synth_xilinx_srl test21a.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test21a.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:4:19: Syntax error: mismatched input 'int' expecting {Pound_Pound_delay, Pound_delay, '#', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, wire [depth:0] int; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:4:19:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:4:22: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at ';', wire [depth:0] int; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:4:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:5:14: Syntax error: mismatched input '[' expecting ''', assign int[0] = ^i[width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:5:14:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:5:16: Syntax error: mismatched input ']' expecting ':', assign int[0] = ^i[width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:5:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:5:18: Syntax error: extraneous input '=' expecting {'[', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, assign int[0] = ^i[width-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:5:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:45: Syntax error: no viable alternative at input '#~@$_DFFE_PP_#~@r(.C(clk), .D(int[', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:45:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:30: Syntax error: no viable alternative at input '(.', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:30:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:36: Syntax error: extraneous input ')' expecting ',', #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:36:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:39: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:39:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test21a.v:8:41: Syntax error: mismatched input '(' expecting {',', ')'}, #~@$_DFFE_PP_#~@r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1])); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test21a.v:8:41:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -5651,22 +5651,22 @@ Processing: -cd architecture/synth_xilinx_srl test21a.v -writepp -parse -nocache Processing: -cd architecture/synth_xilinx_srl test20.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test20.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:4:20: Syntax error: no viable alternative at input 'reg [width-1:0] int', reg [width-1:0] int [depth-1:0]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:4:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:9:23: Syntax error: no viable alternative at input 'int[', initial int[d][w] <= ~((d+w) % 2); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:9:23:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:12:48: Syntax error: no viable alternative at input 'int[', always @(negedge clk) if (e) int[d][w] <= i[w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:12:48:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:14:12: Syntax error: rule if_generate_construct failed predicate: _input->LA(1) != ELSE?, else begin - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:14:12:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:15:48: Syntax error: no viable alternative at input 'int[', always @(negedge clk) if (e) int[d][w] <= int[d-1][w]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:15:48:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/architecture/synth_xilinx_srl/test20.v:19:18: Syntax error: no viable alternative at input 'int[', assign z = int[depth-1]; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/architecture/synth_xilinx_srl/test20.v:19:18:. + ^--. [ FATAL] : 0 [ SYNTAX] : 6 [ ERROR] : 0 @@ -6127,34 +6127,34 @@ Processing: -cd bigsim/picorv32/rtl picorv32.v -writepp -parse -nocache -nobuilt Processing: -cd bigsim/navre/sim sieve.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sieve.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:1:9: Syntax error: mismatched input ']' expecting ':', pmem[ 0] = 16'hc00c; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:1:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:1:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', pmem[ 0] = 16'hc00c; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:1:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:2:9: Syntax error: mismatched input ']' expecting ':', pmem[ 1] = 16'hc01b; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:2:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:2:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', pmem[ 1] = 16'hc01b; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:2:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:3:9: Syntax error: mismatched input ']' expecting ':', pmem[ 2] = 16'hc01a; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:3:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:3:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', pmem[ 2] = 16'hc01a; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:3:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:4:9: Syntax error: mismatched input ']' expecting ':', pmem[ 3] = 16'hc019; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:4:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:4:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', pmem[ 3] = 16'hc019; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:4:11:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:5:9: Syntax error: mismatched input ']' expecting ':', pmem[ 4] = 16'hc018; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:5:9:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/bigsim/navre/sim/sieve.v:5:11: Syntax error: missing {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier} at '=', pmem[ 4] = 16'hc018; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/bigsim/navre/sim/sieve.v:5:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -6217,7 +6217,7 @@ Processing: -cd regression/issue_00085 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00085 top_fault.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top_fault.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00085/top_fault.v:1:21: Syntax error: extraneous input ''sh0' expecting ';', module a;assign a = 0'sh0; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00085/top_fault.v:1:21:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -6433,7 +6433,7 @@ Processing: -cd regression/issue_00086 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00086 top_fault.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top_fault.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00086/top_fault.v:3:11: Syntax error: extraneous input ''H0' expecting ';', reg N=0.0/0'H0; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00086/top_fault.v:3:11:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -6575,7 +6575,7 @@ Processing: -cd regression/issue_01273 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00524 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00524/top.v:5: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00524/top.v:5:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -6644,10 +6644,10 @@ Processing: -cd regression/issue_01033 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00093 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00093/top.v:1:34: Syntax error: mismatched input '+' expecting {Pound_Pound_delay, Pound_delay, '(', 'type', 'local', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, module top(b);inout b;reg c;assign+0-c=b;endmodule - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00093/top.v:1:34:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00093/top.v:1:40: Syntax error: mismatched input ';' expecting '=', module top(b);inout b;reg c;assign+0-c=b;endmodule - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00093/top.v:1:40:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -6910,7 +6910,7 @@ Processing: -cd regression/issue_00391 top_clean.v -writepp -parse -nocache -nob Processing: -cd regression/issue_00089 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00089/top.v:6:13: Syntax error: extraneous input ''' expecting ';', A <= '0'; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00089/top.v:6:13:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -7033,7 +7033,7 @@ Processing: -cd regression/issue_00081 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00081 top_fault.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top_fault.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00081/top_fault.v:18:17: Syntax error: mismatched input ''' expecting ';', assign y0 = 1'b_ >= (-1 * -1.17); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00081/top_fault.v:18:17:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -7228,13 +7228,13 @@ Processing: -cd regression/issue_00655/verilog/submodule/test tb_lm32_system.v - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:296:23: Unknown macro "TRUE". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:291:22: Syntax error: no viable alternative at input 'module soc();\n\ninteger i;\n\nreg sys_rst;\nreg sys_clk;\nreg [31:0] interrupt;\n\nreg i_ack;\nwire [31:0] i_adr;\nwire i_cyc;\nwire [31:0] i_dat;\nwire i_stb;\n\nreg d_ack;\nwire [31:0] d_adr;\nwire d_cyc;\nwire [31:0] d_dat_i;\nwire [31:0] d_dat_o;\nwire [3:0] d_sel;\nwire d_stb;\n\nlm32_top lm32(\n\t.clk_i(sys_clk),\n\t.rst_i(sys_rst),\n\n\t.interrupt(interrupt),\n\n\t.I_ACK_I(i_ack),\n\t.I_ADR_O(i_adr),\n\t.I_BTE_O(),\n\t.I_CTI_O(),\n\t.I_CYC_O(i_cyc),\n\t.I_DAT_I(i_dat),\n\t.I_DAT_O(),\n\t.I_ERR_I(1'b0),\n\t.I_LOCK_O(),\n\t.I_RTY_I(1'b0),\n\t.I_SEL_O(),\n\t.I_STB_O(i_stb),\n\t.I_WE_O(),\n\n\t.D_ACK_I(d_ack),\n\t.D_ADR_O(d_adr),\n\t.D_BTE_O(),\n\t.D_CTI_O(),\n\t.D_CYC_O(d_cyc),\n\t.D_DAT_I(d_dat_i),\n\t.D_DAT_O(d_dat_o),\n\t.D_ERR_I(1'b0),\n\t.D_LOCK_O(),\n\t.D_RTY_I(1'b0),\n\t.D_SEL_O(d_sel),\n\t.D_STB_O(d_stb),\n\t.D_WE_O(d_we)\n);\n\n// clock\ninitial sys_clk = 1'b0;\nalways #5 sys_clk = ~sys_clk;\n\n// reset\ninitial begin\n\tsys_rst = 1'b1;\n\t#20\n\tsys_rst = 1'b0;\nend\n\n// memory\nreg [7:0] mem[0:65536];\ninitial begin\n\tfor(i=0;i<65536;i=i+1)\n\t\tmem[i] = 8'b0;\nend\n\nwire [31:0] dmem_dat_i;\nreg [31:0] dmem_dat_o;\nwire [13:0] dmem_adr;\nwire [3:0] dmem_we;\nalways @(posedge sys_clk) begin\n\tif(dmem_we[0]) mem[{dmem_adr, 2'b11}] <= dmem_dat_i[7:0];\n\tif(dmem_we[1]) mem[{dmem_adr, 2'b10}] <= dmem_dat_i[15:8];\n\tif(dmem_we[2]) mem[{dmem_adr, 2'b01}] <= dmem_dat_i[23:16];\n\tif(dmem_we[3]) mem[{dmem_adr, 2'b00}] <= dmem_dat_i[31:24];\n\tdmem_dat_o[7:0] <= mem[{dmem_adr, 2'b11}];\n\tdmem_dat_o[15:8] <= mem[{dmem_adr, 2'b10}];\n\tdmem_dat_o[23:16] <= mem[{dmem_adr, 2'b01}];\n\tdmem_dat_o[31:24] <= mem[{dmem_adr, 2'b00}];\nend\nreg [31:0] pmem_dat_o;\nwire [13:0] pmem_adr;\nalways @(posedge sys_clk) begin\n\tpmem_dat_o[7:0] <= mem[{pmem_adr, 2'b11}];\n\tpmem_dat_o[15:8] <= mem[{pmem_adr, 2'b10}];\n\tpmem_dat_o[23:16] <= mem[{pmem_adr, 2'b01}];\n\tpmem_dat_o[31:24] <= mem[{pmem_adr, 2'b00}];\nend\n\n// uart\nalways @(posedge sys_clk) begin\n\tif(d_cyc & d_stb & d_we & d_ack)\n\t\tif(d_adr == 32'hff000000)\n\t\t\t$write("%c", d_dat_o[7:0]);\nend\n\n// wishbone interface for instruction bus\nalways @(posedge sys_clk) begin\n\tif(sys_rst)\n\t\ti_ack <= 1'b0;\n\telse begin\n\t\ti_ack <= 1'b0;\n\t\tif(i_cyc & i_stb & ~i_ack)\n\t\t\ti_ack <= 1'b1;\n\tend\nend\n\nassign i_dat = pmem_dat_o;\nassign pmem_adr = i_adr[15:2];\n\ntask dump_processor_state;\nbegin\n\t$display("Processor state:");\n\t$display(" PSW=%08x", lm32.cpu.psw);\n\t$display(" IE=%08x IP=%08x IM=%08x",\n\t\tlm32.cpu.interrupt_unit.ie,\n\t\tlm32.cpu.interrupt_unit.ip,\n\t\tlm32.cpu.interrupt_unit.im\n\t);\n\tfor(i=0; i<32; i=i+1) begin\n\t\tif(i%4 == 0)\n\t\t\t$write(" ");\n\t\t$write("r%02d=%08x ", i, lm32.cpu.reg_0.mem[i]);\n\t\tif((i+1)%4 == 0)\n\t\t\t$write("\n");\n\tend\nend\nendtask\n\n// QEMU test core\nreg [15:0] testname_adr;\nreg [8*32:0] testname;\nreg testname_end;\nalways @(posedge sys_clk) begin\n\tif(d_cyc & d_stb & d_we & d_ack)\n\tbegin\n\t\tif(d_adr == 32'hffff0000)\n\t\t\t$finish;\n\t\telse if(d_adr == 32'hffff0004) begin\n\t\t\t// is there any better way to do this?\n\t\t\ttestname_end = 1'b0;\n\t\t\tfor(i=0; i<32; i=i+1) begin\n\t\t\t\ttestname = testname << 8;\n\t\t\t\tif(testname_end == 1'b0) begin\n\t\t\t\t\ttestname[7:0] = mem[testname_adr+i];\n\t\t\t\t\tif(mem[testname_adr+i] == 8'b0)\n\t\t\t\t\t\ttestname_end = 1'b1;\n\t\t\t\tend else\n\t\t\t\t\ttestname[7:0] = 8'b0;\n\t\t\tend\n\t\t\t$display("TC %-32s %s", testname, (|d_dat_o) ? "FAILED" : "OK");\n\t\t\tif(|d_dat_o)\n\t\t\t\tdump_processor_state();\n\t\tend\n\t\telse if(d_adr == 32'hffff0008)\n\t\t\ttestname_adr <= d_dat_o[15:0];\n\tend\nend\n\n// wishbone interface for data bus\nalways @(posedge sys_clk) begin\n\tif(sys_rst)\n\t\td_ack <= 1'b0;\n\telse begin\n\t\td_ack <= 1'b0;\n\t\tif(d_cyc & d_stb & ~d_ack)\n\t\t\td_ack <= 1'b1;\n\tend\nend\n\nassign d_dat_i = dmem_dat_o;\nassign dmem_dat_i = d_dat_o;\nassign dmem_adr = d_adr[15:2];\nassign dmem_we = {4{d_cyc & d_stb & d_we & ~|d_adr[31:16]}} & d_sel;\n\n// interrupts\ninitial interrupt <= 32'b0;\n\n// simulation end request\nalways @(posedge sys_clk) begin\n\tif(d_cyc & d_stb & d_we & d_ack)\n\t\tif(d_adr == 32'hdead0000 && d_dat_o == 32'hbeef)\n\t\t\t$finish;\nend\n\n// traces\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n// dump signals\nreg [256*8:0] vcdfile;\ninitial begin\n\tif($value$plusargs("dump=%s", vcdfile)) begin\n\t\t$dumpfile(vcdfile);\n\t\t$dumpvars(0, soc);\n\tend\nend\n\n// init memory\nreg [256*8:0] prog;\ninitial begin\n\tif(! $value$plusargs("prog=%s", prog)) begin\n\t\t$display("ERROR: please specify +prog=.vh to start.");\n\t\t$finish;\n\tend\nend\n\ninitial $readmemh(prog, mem);\n\n// trace pipeline\nreg [256*8:0] tracefile;\ninteger trace_started;\ninteger trace_enabled;\ninteger cycle;\ninteger tracefd;\ninitial begin\n\tif($value$plusargs("trace=%s", tracefile)) begin\n\t\ttrace_enabled = 1;\n\t\tcycle = 0;\n\t\ttracefd = $fopen(tracefile);\n\t\ttrace_started = 0;\n\tend else\n\t\ttrace_enabled = 0;\nend\n\n\n\nassign icache_ready = SURELOG_MACRO_NOT_DEFINED:TRUE!!!', assign icache_ready = SURELOG_MACRO_NOT_DEFINED:TRUE!!! ; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:291:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:55:13: Syntax error: no viable alternative at input 'lm32_top lm32(', lm32_top lm32( - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:55:13:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:91: Syntax error: mismatched input 'initial' expecting , initial sys_clk = 1'b0; -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/test/tb_lm32_system.v:91:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 3 @@ -7274,16 +7274,16 @@ Processing: -cd regression/issue_00655/verilog/submodule/rtl lm32_instruction_un [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:196:58: Unknown macro "CLOG2". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:188:22: Syntax error: no viable alternative at input 'module lm32_instruction_unit (\n // ----- Inputs -------\n clk_i,\n rst_i,\n\n\n\n\n\n // From pipeline\n stall_a,\n stall_f,\n stall_d,\n stall_x,\n stall_m,\n valid_f,\n valid_d,\n kill_f,\n branch_predict_taken_d,\n branch_predict_address_d,\n\n\n\n\n exception_m,\n branch_taken_m,\n branch_mispredict_taken_m,\n branch_target_m,\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // From Wishbone\n i_dat_i,\n i_ack_i,\n i_err_i,\n\n\n\n\n\n\n\n // ----- Outputs -------\n // To pipeline\n pc_f,\n pc_d,\n pc_x,\n pc_m,\n pc_w,\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // To Wishbone\n i_dat_o,\n i_adr_o,\n i_cyc_o,\n i_sel_o,\n i_stb_o,\n i_we_o,\n i_cti_o,\n i_lock_o,\n i_bte_o,\n\n\n\n\n\n\n bus_error_d,\n\n\n\n\n instruction_d\n );\n\n/////////////////////////////////////////////////////\n// Parameters\n/////////////////////////////////////////////////////\n\nparameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!', parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:555:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:188:22: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'virtual', 'type', 'const', 'local', 'super', '{', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:555:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:196:51: Syntax error: mismatched input '?' expecting ';', localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:563:51:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:196:92: Syntax error: mismatched input '-' expecting , localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:563:92:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_instruction_unit.v:196: Unknown macro "CLOG2". [ FATAL] : 0 [ SYNTAX] : 4 @@ -7371,13 +7371,13 @@ Processing: -cd regression/issue_00655/verilog/submodule/rtl lm32_cpu.v -writepp [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:191:23: Unknown macro "CFG_EBA_RESET". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:191:22: Syntax error: no viable alternative at input 'module lm32_cpu (\n // ----- Inputs -------\n clk_i,\n\n\n\n rst_i,\n\n\n\n\n\n // From external devices\n\n interrupt,\n\n // From user logic\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // Instruction Wishbone master\n I_DAT_I,\n I_ACK_I,\n I_ERR_I,\n I_RTY_I,\n\n // Data Wishbone master\n D_DAT_I,\n D_ACK_I,\n D_ERR_I,\n D_RTY_I,\n // ----- Outputs -------\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // Instruction Wishbone master\n I_DAT_O,\n I_ADR_O,\n I_CYC_O,\n I_SEL_O,\n I_STB_O,\n I_WE_O,\n I_CTI_O,\n I_LOCK_O,\n I_BTE_O,\n\n // Data Wishbone master\n D_DAT_O,\n D_ADR_O,\n D_CYC_O,\n D_SEL_O,\n D_STB_O,\n D_WE_O,\n D_CTI_O,\n D_LOCK_O,\n D_BTE_O\n );\n\n/////////////////////////////////////////////////////\n// Parameters\n/////////////////////////////////////////////////////\n\nparameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!', parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; // Reset value for EBA CSR - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:558:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:191:22: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'virtual', 'type', 'const', 'local', 'super', '{', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, parameter eba_reset = SURELOG_MACRO_NOT_DEFINED:CFG_EBA_RESET!!! ; // Reset value for EBA CSR - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:558:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:245: Syntax error: mismatched input 'input' expecting , input clk_i; // Clock -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_cpu.v:612:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 2 @@ -7388,13 +7388,13 @@ Processing: -cd regression/issue_00655/verilog/submodule/rtl lm32_load_store_uni [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159:58: Unknown macro "CLOG2". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159:57: Syntax error: no viable alternative at input 'module lm32_load_store_unit (\n // ----- Inputs -------\n clk_i,\n rst_i,\n // From pipeline\n stall_a,\n stall_x,\n stall_m,\n kill_m,\n exception_m,\n store_operand_x,\n load_store_address_x,\n load_store_address_m,\n load_store_address_w,\n\n\n\n\n load_x,\n store_x,\n load_q_x,\n store_q_x,\n load_q_m,\n store_q_m,\n sign_extend_x,\n size_x,\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n // From Wishbone\n d_dat_i,\n d_ack_i,\n d_err_i,\n d_rty_i,\n // ----- Outputs -------\n // To pipeline\n\n\n\n\n\n\n\n\n\n\n\n\n load_data_w,\n stall_wb_load,\n\n\n\n\n\n\n // To Wishbone\n d_dat_o,\n d_adr_o,\n d_cyc_o,\n d_sel_o,\n d_stb_o,\n d_we_o,\n d_cti_o,\n d_lock_o,\n d_bte_o\n );\n\n/////////////////////////////////////////////////////\n// Parameters\n/////////////////////////////////////////////////////\n\nparameter associativity = 1; // Associativity of the cache (Number of ways)\nparameter sets = 512; // Number of sets\nparameter bytes_per_line = 16; // Number of bytes per cache line\nparameter base_address = 0; // Base address of cachable memory\nparameter limit = 0; // Limit (highest address) of cachable memory\n\n// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used\nlocalparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!!', localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:526:57:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159:51: Syntax error: mismatched input '?' expecting ';', localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:526:51:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159:92: Syntax error: mismatched input '-' expecting , localparam addr_offset_width = bytes_per_line == 4 ? 1 : SURELOG_MACRO_NOT_DEFINED:CLOG2!!! -2; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:526:92:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00655/verilog/submodule/rtl/lm32_load_store_unit.v:159: Unknown macro "CLOG2". [ FATAL] : 0 [ SYNTAX] : 3 @@ -7748,28 +7748,28 @@ Processing: -cd regression/issue_00126 testbench.v -writepp -parse -nocache -nob Processing: -cd regression/issue_00589 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:568:14: Syntax error: no viable alternative at input 'corebit_and join', corebit_and join( - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:568:14:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:569:18: Syntax error: extraneous input ')' expecting ',', .in0(join__in0), - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:569:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:570:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .in1(join__in1), - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:570:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:571:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .out(join__out) - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:571:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:589:14: Syntax error: no viable alternative at input 'corebit_and join', corebit_and join( - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:589:14:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:590:18: Syntax error: extraneous input ')' expecting ',', .in0(join__in0), - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:590:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:591:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .in1(join__in1), - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:591:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00589/top.v:592:4: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, .out(join__out) - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00589/top.v:592:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 8 [ ERROR] : 0 @@ -8061,34 +8061,34 @@ Processing: -cd regression/issue_00938 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00502 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:38: Syntax error: no viable alternative at input 'MY_AND2 inst_a1 (.A(A), .B(B), .Y( \', MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:38:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:20: Syntax error: no viable alternative at input '(.', MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:24: Syntax error: extraneous input ')' expecting ',', MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:24:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:27: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:27:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:34: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:34:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:14:36: Syntax error: extraneous input '(' expecting {',', ')'}, MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:14:36:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:31: Syntax error: no viable alternative at input 'MY_AND2 inst_a2 (.A(C), .B( \', MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:31:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:20: Syntax error: no viable alternative at input '(.', MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:20:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:24: Syntax error: extraneous input ')' expecting ',', MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:24:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00502/top.v:15:27: Syntax error: extraneous input '.' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '++', '+', '--', '-', DOLLAR_UNIT, '!', 'tagged', ''', 'null', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier}, MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) ); - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00502/top.v:15:27:. + ^--. [ FATAL] : 0 [ SYNTAX] : 10 [ ERROR] : 0 @@ -8174,13 +8174,13 @@ Processing: -cd regression/issue_00896 testbench.v -writepp -parse -nocache -nob Processing: -cd regression/issue_00095 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00095/top.v:1:21: Syntax error: missing ';' at '=', module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00095/top.v:1:21:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00095/top.v:1:22: Syntax error: mismatched input '0' expecting {Pound_Pound_delay, Pound_delay, 'type', 'local', 'super', '{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', DOLLAR_UNIT, '#', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00095/top.v:1:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00095/top.v:1:61: Syntax error: extraneous input '#0' expecting ';', module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00095/top.v:1:61:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -8274,13 +8274,13 @@ Processing: -cd regression/issue_00956 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00096 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00096/top.v:2: Syntax error: no viable alternative at input 'module top(b);integer\ninout', inout b;reg c;assign&0=0;assign 0=0;always -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00096/top.v:2:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00096/top.v:2: Syntax error: extraneous input 'inout' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, inout b;reg c;assign&0=0;assign 0=0;always -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00096/top.v:2:0:. +^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00096/top.v:2:14: Syntax error: mismatched input 'assign' expecting , inout b;reg c;assign&0=0;assign 0=0;always - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00096/top.v:2:14:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -8431,7 +8431,7 @@ Processing: -cd regression/issue_00082 top.v -writepp -parse -nocache -nobuiltin Processing: -cd regression/issue_00082 top_fault.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top_fault.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00082/top_fault.v:6: Syntax error: mismatched input 'endmodule' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'virtual', 'type', 'bind', 'const', 'static', 'local', 'super', '{', '->', 'if', 'foreach', 'automatic', 'localparam', 'parameter', 'import', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', 'var', 'void', '$', 'endtask', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', 'let', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', 'nettype', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, endmodule -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00082/top_fault.v:6:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -8539,7 +8539,7 @@ Processing: -cd regression/issue_00372 testbench.v -writepp -parse -nocache -nob Processing: -cd regression/issue_00807 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00807/top.v:4: Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'this', DOLLAR_ROOT, 'randomize', 'sample', Escaped_identifier, Simple_identifier}, ); -^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_00807/top.v:4:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 @@ -8712,7 +8712,7 @@ Processing: -cd regression/issue_00809 testbench.v -writepp -parse -nocache -nob Processing: -cd regression/issue_01131 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_01131/top.v:4:6: Syntax error: no viable alternative at input ''81', q <= '81; - ^-- ${SURELOG_DIR}/build/regression/YosysTests/slpp_all/lib/work/regression/issue_01131/top.v:4:6:. + ^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 0 diff --git a/third_party/tests/Zachjs/Zachjs.log b/third_party/tests/Zachjs/Zachjs.log index 29abea454a..db69401836 100644 --- a/third_party/tests/Zachjs/Zachjs.log +++ b/third_party/tests/Zachjs/Zachjs.log @@ -1,10 +1,10 @@ Processing: -cd resolve +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ -parse -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns reference.v -l reference.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/reference.v:4:4: Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, input [width-1:0] i; - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/reference.v:4:4:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/reference.v:5:4: Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, output [width-1:0] o; - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/reference.v:5:4:. + ^--. [ FATAL] : 0 [ SYNTAX] : 2 [ ERROR] : 0 @@ -103,28 +103,28 @@ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ -parse -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns flatten.v -l flatten.v.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:24: Syntax error: no viable alternative at input '$display($time, `', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:24:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:16: Syntax error: mismatched input '(' expecting ';', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:22: Syntax error: mismatched input ',' expecting ';', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:25: Syntax error: mismatched input '" A1 @+ "' expecting Simple_identifier, $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:25:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:43: Syntax error: no viable alternative at input 'a]', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:43:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:48: Syntax error: no viable alternative at input 'b+:', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:48:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:52: Syntax error: mismatched input ')' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:50:52:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:11: Syntax error: mismatched input '111' expecting , 111 $display($time, `" A1 @+ ", out[2+a][1+b+:1]); -^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.v:51:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 8 [ ERROR] : 0 @@ -293,13 +293,13 @@ ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:1:9: No default ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:1:9: No default value for argument 2 (b) in macro definition. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:17: Syntax error: no viable alternative at input '$display(`', $display(`FOO - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.v:5:17:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:16: Syntax error: mismatched input '(' expecting ';', $display(`FOO - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.v:5:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:6:8: Syntax error: mismatched input '(' expecting , ( - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.v:6:8:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 3 @@ -325,7 +325,7 @@ Processing: -cd lex +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ - <<. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_iv.sv:122: Syntax error: mismatched input '"' expecting , "); -^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_iv.v:123:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 1 @@ -336,22 +336,22 @@ Processing: -cd lib +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ - [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4:22: Unknown macro "TEST_TOP". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3:18: Syntax error: no viable alternative at input '$dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!!', $dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:3:18:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3:17: Syntax error: mismatched input '(' expecting ';', $dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:3:17:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3:56: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, $dumpfile(SURELOG_MACRO_NOT_DEFINED:TEST_VCD!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:3:56:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4:21: Syntax error: no viable alternative at input '$dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!!', $dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:4:21:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4:17: Syntax error: mismatched input '(' expecting ';', $dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:4:17:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4:59: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, $dumpvars(1, SURELOG_MACRO_NOT_DEFINED:TEST_TOP!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lib/tb_dumper.v:4:59:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:3: Unknown macro "TEST_VCD". [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Zachjs/lib/tb_dumper.v:4: Unknown macro "TEST_TOP". [ FATAL] : 0 @@ -640,13 +640,13 @@ Processing: -cd resolve +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolv [ERR:PP0102] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8:18: Unknown macro "FANCY_SEEING_YOU". [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8:17: Syntax error: no viable alternative at input '$display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!!', $display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/module.sv:8:17:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8:16: Syntax error: mismatched input '(' expecting ';', $display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/module.sv:8:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8:63: Syntax error: extraneous input ')' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED}, $display(SURELOG_MACRO_NOT_DEFINED:FANCY_SEEING_YOU!!! ); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/resolve/module.sv:8:63:. + ^--. [ERR:PA0203] ${SURELOG_DIR}/third_party/tests/Zachjs/resolve/module.sv:8: Unknown macro "FANCY_SEEING_YOU". [ FATAL] : 0 [ SYNTAX] : 3 @@ -668,28 +668,28 @@ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ -parse -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns flatten.sv -l flatten.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:24: Syntax error: no viable alternative at input '$display($time, `', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:24:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:16: Syntax error: mismatched input '(' expecting ';', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:22: Syntax error: mismatched input ',' expecting ';', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:22:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:25: Syntax error: mismatched input '" A1 @+ "' expecting Simple_identifier, $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:25:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:43: Syntax error: no viable alternative at input 'a]', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:43:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:48: Syntax error: no viable alternative at input 'b+:', $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:48:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:10:52: Syntax error: mismatched input ')' expecting {'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, $display($time, `" A1 @+ ", out[1+a][1+b+:1]); - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:49:52:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/flatten.sv:11: Syntax error: mismatched input '111' expecting , 111 $display($time, `" A1 @+ ", out[2+a][1+b+:1]); -^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/flatten.sv:50:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 8 [ ERROR] : 0 @@ -710,13 +710,13 @@ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ Processing: -cd basic +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ -parse -nocache -nobuiltin -nonote -noinfo -sverilog -timescale=1ns/1ns enum.sv -l enum.sv.log [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/enum.sv:25:13: Syntax error: no viable alternative at input 'enum [', typedef enum [0:0] { - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/enum.sv:25:13:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/enum.sv:25:13: Syntax error: mismatched input '[' expecting {'{', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'this', 'randomize', 'sample', Escaped_identifier, Simple_identifier}, typedef enum [0:0] { - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/enum.sv:25:13:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/basic/enum.sv:25:19: Syntax error: mismatched input '{' expecting ';', typedef enum [0:0] { - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/basic/enum.sv:25:19:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 @@ -846,13 +846,13 @@ ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:1:9: No default ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:1:9: No default value for argument 2 (b) in macro definition. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:17: Syntax error: no viable alternative at input '$display(`', $display(`FOO - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.sv:5:17:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:5:16: Syntax error: mismatched input '(' expecting ';', $display(`FOO - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.sv:5:16:. + ^--. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_whitespace.sv:6:8: Syntax error: mismatched input '(' expecting , ( - ^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_whitespace.sv:6:8:. + ^--. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 3 @@ -865,7 +865,7 @@ Processing: -cd lex +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ - <<. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro_iv.sv:122: Syntax error: mismatched input '"' expecting , "); -^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro_iv.sv:122:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 1 @@ -884,7 +884,7 @@ Processing: -cd lex +incdir+.+../basic/+../lex/+../lib/+../relong/+../resolve/ - <<. [SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Zachjs/lex/macro.sv:43: Syntax error: mismatched input '=' expecting , = "bar" ) str, str -^-- ${SURELOG_DIR}/build/regression/Zachjs/slpp_all/lib/work/lex/macro.sv:43:0:. +^--. [ FATAL] : 0 [ SYNTAX] : 1 [ ERROR] : 2