diff --git a/src/DesignCompile/CompileFileContent.cpp b/src/DesignCompile/CompileFileContent.cpp
index d9210f3be6..9c0110c942 100644
--- a/src/DesignCompile/CompileFileContent.cpp
+++ b/src/DesignCompile/CompileFileContent.cpp
@@ -99,6 +99,11 @@ bool CompileFileContent::collectObjects_() {
         }
         break;
       }
+      case VObjectType::paBind_directive: {
+        m_helper.compileBindStmt(m_fileContent, fC, id, m_compileDesign,
+                                 nullptr);
+        break;
+      }
       case VObjectType::paParameter_declaration: {
         if (m_declOnly) {
           NodeId list_of_type_assignments = fC->Child(id);
diff --git a/tests/AssertDelayError/AssertDelayError.log b/tests/AssertDelayError/AssertDelayError.log
new file mode 100644
index 0000000000..a4ade7fcbc
--- /dev/null
+++ b/tests/AssertDelayError/AssertDelayError.log
@@ -0,0 +1,4684 @@
+[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/AssertDelayError/slpp_all/surelog.log".
+AST_DEBUG_BEGIN
+LIB:  work
+FILE: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<393> s<392> l<1:1> el<1:0>
+n<module> u<2> t<Module_keyword> p<65> s<3> l<1:1> el<1:7>
+n<left_rotate_assertions> u<3> t<StringConst> p<65> s<64> l<1:8> el<1:30>
+n<> u<4> t<PortDir_Inp> p<7> s<6> l<2:5> el<2:10>
+n<> u<5> t<Data_type_or_implicit> p<6> l<2:11> el<2:11>
+n<> u<6> t<Net_port_type> p<7> c<5> l<2:11> el<2:11>
+n<> u<7> t<Net_port_header> p<9> c<4> s<8> l<2:5> el<2:10>
+n<clk> u<8> t<StringConst> p<9> l<2:11> el<2:14>
+n<> u<9> t<Ansi_port_declaration> p<64> c<7> s<15> l<2:5> el<2:14>
+n<> u<10> t<PortDir_Inp> p<13> s<12> l<3:5> el<3:10>
+n<> u<11> t<Data_type_or_implicit> p<12> l<3:11> el<3:11>
+n<> u<12> t<Net_port_type> p<13> c<11> l<3:11> el<3:11>
+n<> u<13> t<Net_port_header> p<15> c<10> s<14> l<3:5> el<3:10>
+n<rst_n> u<14> t<StringConst> p<15> l<3:11> el<3:16>
+n<> u<15> t<Ansi_port_declaration> p<64> c<13> s<31> l<3:5> el<3:16>
+n<> u<16> t<PortDir_Inp> p<29> s<28> l<4:5> el<4:10>
+n<31> u<17> t<IntConst> p<18> l<4:12> el<4:14>
+n<> u<18> t<Primary_literal> p<19> c<17> l<4:12> el<4:14>
+n<> u<19> t<Constant_primary> p<20> c<18> l<4:12> el<4:14>
+n<> u<20> t<Constant_expression> p<25> c<19> s<24> l<4:12> el<4:14>
+n<0> u<21> t<IntConst> p<22> l<4:15> el<4:16>
+n<> u<22> t<Primary_literal> p<23> c<21> l<4:15> el<4:16>
+n<> u<23> t<Constant_primary> p<24> c<22> l<4:15> el<4:16>
+n<> u<24> t<Constant_expression> p<25> c<23> l<4:15> el<4:16>
+n<> u<25> t<Constant_range> p<26> c<20> l<4:12> el<4:16>
+n<> u<26> t<Packed_dimension> p<27> c<25> l<4:11> el<4:17>
+n<> u<27> t<Data_type_or_implicit> p<28> c<26> l<4:11> el<4:17>
+n<> u<28> t<Net_port_type> p<29> c<27> l<4:11> el<4:17>
+n<> u<29> t<Net_port_header> p<31> c<16> s<30> l<4:5> el<4:17>
+n<word_in> u<30> t<StringConst> p<31> l<4:18> el<4:25>
+n<> u<31> t<Ansi_port_declaration> p<64> c<29> s<47> l<4:5> el<4:25>
+n<> u<32> t<PortDir_Inp> p<45> s<44> l<5:5> el<5:10>
+n<4> u<33> t<IntConst> p<34> l<5:12> el<5:13>
+n<> u<34> t<Primary_literal> p<35> c<33> l<5:12> el<5:13>
+n<> u<35> t<Constant_primary> p<36> c<34> l<5:12> el<5:13>
+n<> u<36> t<Constant_expression> p<41> c<35> s<40> l<5:12> el<5:13>
+n<0> u<37> t<IntConst> p<38> l<5:14> el<5:15>
+n<> u<38> t<Primary_literal> p<39> c<37> l<5:14> el<5:15>
+n<> u<39> t<Constant_primary> p<40> c<38> l<5:14> el<5:15>
+n<> u<40> t<Constant_expression> p<41> c<39> l<5:14> el<5:15>
+n<> u<41> t<Constant_range> p<42> c<36> l<5:12> el<5:15>
+n<> u<42> t<Packed_dimension> p<43> c<41> l<5:11> el<5:16>
+n<> u<43> t<Data_type_or_implicit> p<44> c<42> l<5:11> el<5:16>
+n<> u<44> t<Net_port_type> p<45> c<43> l<5:11> el<5:16>
+n<> u<45> t<Net_port_header> p<47> c<32> s<46> l<5:5> el<5:16>
+n<rotate_by> u<46> t<StringConst> p<47> l<5:17> el<5:26>
+n<> u<47> t<Ansi_port_declaration> p<64> c<45> s<63> l<5:5> el<5:26>
+n<> u<48> t<PortDir_Inp> p<61> s<60> l<6:5> el<6:10>
+n<31> u<49> t<IntConst> p<50> l<6:12> el<6:14>
+n<> u<50> t<Primary_literal> p<51> c<49> l<6:12> el<6:14>
+n<> u<51> t<Constant_primary> p<52> c<50> l<6:12> el<6:14>
+n<> u<52> t<Constant_expression> p<57> c<51> s<56> l<6:12> el<6:14>
+n<0> u<53> t<IntConst> p<54> l<6:15> el<6:16>
+n<> u<54> t<Primary_literal> p<55> c<53> l<6:15> el<6:16>
+n<> u<55> t<Constant_primary> p<56> c<54> l<6:15> el<6:16>
+n<> u<56> t<Constant_expression> p<57> c<55> l<6:15> el<6:16>
+n<> u<57> t<Constant_range> p<58> c<52> l<6:12> el<6:16>
+n<> u<58> t<Packed_dimension> p<59> c<57> l<6:11> el<6:17>
+n<> u<59> t<Data_type_or_implicit> p<60> c<58> l<6:11> el<6:17>
+n<> u<60> t<Net_port_type> p<61> c<59> l<6:11> el<6:17>
+n<> u<61> t<Net_port_header> p<63> c<48> s<62> l<6:5> el<6:17>
+n<rotated> u<62> t<StringConst> p<63> l<6:18> el<6:25>
+n<> u<63> t<Ansi_port_declaration> p<64> c<61> l<6:5> el<6:25>
+n<> u<64> t<List_of_port_declarations> p<65> c<9> l<1:31> el<7:2>
+n<> u<65> t<Module_ansi_header> p<344> c<2> s<123> l<1:1> el<7:3>
+n<> u<66> t<Edge_Posedge> p<71> s<70> l<11:7> el<11:14>
+n<clk> u<67> t<StringConst> p<68> l<11:15> el<11:18>
+n<> u<68> t<Primary_literal> p<69> c<67> l<11:15> el<11:18>
+n<> u<69> t<Primary> p<70> c<68> l<11:15> el<11:18>
+n<> u<70> t<Expression> p<71> c<69> l<11:15> el<11:18>
+n<> u<71> t<Event_expression> p<72> c<66> l<11:7> el<11:18>
+n<> u<72> t<Event_control> p<73> c<71> l<11:5> el<11:19>
+n<> u<73> t<Procedural_timing_control> p<75> c<72> s<74> l<11:5> el<11:19>
+n<> u<74> t<Statement_or_null> p<75> l<11:19> el<11:20>
+n<> u<75> t<Procedural_timing_control_statement> p<76> c<73> l<11:5> el<11:20>
+n<> u<76> t<Statement_item> p<77> c<75> l<11:5> el<11:20>
+n<> u<77> t<Statement> p<78> c<76> l<11:5> el<11:20>
+n<> u<78> t<Statement_or_null> p<116> c<77> s<114> l<11:5> el<11:20>
+n<rst_n> u<79> t<StringConst> p<80> l<12:10> el<12:15>
+n<> u<80> t<Primary_literal> p<81> c<79> l<12:10> el<12:15>
+n<> u<81> t<Primary> p<82> c<80> l<12:10> el<12:15>
+n<> u<82> t<Expression> p<84> c<81> l<12:10> el<12:15>
+n<> u<83> t<Unary_Not> p<84> s<82> l<12:9> el<12:10>
+n<> u<84> t<Expression> p<85> c<83> l<12:9> el<12:15>
+n<> u<85> t<Expression_or_cond_pattern> p<86> c<84> l<12:9> el<12:15>
+n<> u<86> t<Cond_predicate> p<111> c<85> s<110> l<12:9> el<12:15>
+n<rotated> u<87> t<StringConst> p<88> l<13:14> el<13:21>
+n<> u<88> t<Primary_literal> p<89> c<87> l<13:14> el<13:21>
+n<> u<89> t<Primary> p<90> c<88> l<13:14> el<13:21>
+n<> u<90> t<Expression> p<96> c<89> s<95> l<13:14> el<13:21>
+n<0> u<91> t<IntConst> p<92> l<13:25> el<13:26>
+n<> u<92> t<Primary_literal> p<93> c<91> l<13:25> el<13:26>
+n<> u<93> t<Primary> p<94> c<92> l<13:25> el<13:26>
+n<> u<94> t<Expression> p<96> c<93> l<13:25> el<13:26>
+n<> u<95> t<BinOp_Equiv> p<96> s<94> l<13:22> el<13:24>
+n<> u<96> t<Expression> p<99> c<90> s<98> l<13:14> el<13:26>
+n<> u<97> t<Statement_or_null> p<98> l<13:27> el<13:28>
+n<> u<98> t<Action_block> p<99> c<97> l<13:27> el<13:28>
+n<> u<99> t<Simple_immediate_assert_statement> p<100> c<96> l<13:7> el<13:28>
+n<> u<100> t<Simple_immediate_assertion_statement> p<101> c<99> l<13:7> el<13:28>
+n<> u<101> t<Immediate_assertion_statement> p<102> c<100> l<13:7> el<13:28>
+n<> u<102> t<Procedural_assertion_statement> p<103> c<101> l<13:7> el<13:28>
+n<> u<103> t<Statement_item> p<104> c<102> l<13:7> el<13:28>
+n<> u<104> t<Statement> p<105> c<103> l<13:7> el<13:28>
+n<> u<105> t<Statement_or_null> p<107> c<104> s<106> l<13:7> el<13:28>
+n<> u<106> t<END> p<107> l<14:5> el<14:8>
+n<> u<107> t<Seq_block> p<108> c<105> l<12:17> el<14:8>
+n<> u<108> t<Statement_item> p<109> c<107> l<12:17> el<14:8>
+n<> u<109> t<Statement> p<110> c<108> l<12:17> el<14:8>
+n<> u<110> t<Statement_or_null> p<111> c<109> l<12:17> el<14:8>
+n<> u<111> t<Conditional_statement> p<112> c<86> l<12:5> el<14:8>
+n<> u<112> t<Statement_item> p<113> c<111> l<12:5> el<14:8>
+n<> u<113> t<Statement> p<114> c<112> l<12:5> el<14:8>
+n<> u<114> t<Statement_or_null> p<116> c<113> s<115> l<12:5> el<14:8>
+n<> u<115> t<END> p<116> l<15:3> el<15:6>
+n<> u<116> t<Seq_block> p<117> c<78> l<10:11> el<15:6>
+n<> u<117> t<Statement_item> p<118> c<116> l<10:11> el<15:6>
+n<> u<118> t<Statement> p<119> c<117> l<10:11> el<15:6>
+n<> u<119> t<Statement_or_null> p<120> c<118> l<10:11> el<15:6>
+n<> u<120> t<Initial_construct> p<121> c<119> l<10:3> el<15:6>
+n<> u<121> t<Module_common_item> p<122> c<120> l<10:3> el<15:6>
+n<> u<122> t<Module_or_generate_item> p<123> c<121> l<10:3> el<15:6>
+n<> u<123> t<Non_port_module_item> p<344> c<122> s<192> l<10:3> el<15:6>
+n<p_valid_rotation> u<124> t<StringConst> p<186> s<184> l<18:12> el<18:28>
+n<> u<125> t<Edge_Posedge> p<130> s<129> l<19:7> el<19:14>
+n<clk> u<126> t<StringConst> p<127> l<19:15> el<19:18>
+n<> u<127> t<Primary_literal> p<128> c<126> l<19:15> el<19:18>
+n<> u<128> t<Primary> p<129> c<127> l<19:15> el<19:18>
+n<> u<129> t<Expression> p<130> c<128> l<19:15> el<19:18>
+n<> u<130> t<Event_expression> p<131> c<125> l<19:7> el<19:18>
+n<> u<131> t<Clocking_event> p<184> c<130> s<183> l<19:5> el<19:19>
+n<rst_n> u<132> t<StringConst> p<133> l<19:22> el<19:27>
+n<> u<133> t<Primary_literal> p<134> c<132> l<19:22> el<19:27>
+n<> u<134> t<Primary> p<135> c<133> l<19:22> el<19:27>
+n<> u<135> t<Expression> p<137> c<134> l<19:22> el<19:27>
+n<> u<136> t<Unary_Not> p<137> s<135> l<19:21> el<19:22>
+n<> u<137> t<Expression> p<138> c<136> l<19:21> el<19:27>
+n<> u<138> t<Expression> p<139> c<137> l<19:20> el<19:28>
+n<> u<139> t<Expression_or_dist> p<140> c<138> l<19:20> el<19:28>
+n<> u<140> t<Sequence_expr> p<183> c<139> s<182> l<19:20> el<19:28>
+n<rotated> u<141> t<StringConst> p<142> l<19:34> el<19:41>
+n<> u<142> t<Primary_literal> p<143> c<141> l<19:34> el<19:41>
+n<> u<143> t<Primary> p<144> c<142> l<19:34> el<19:41>
+n<> u<144> t<Expression> p<157> c<143> s<156> l<19:34> el<19:41>
+n<word_in> u<145> t<StringConst> p<146> l<19:46> el<19:53>
+n<> u<146> t<Primary_literal> p<147> c<145> l<19:46> el<19:53>
+n<> u<147> t<Primary> p<148> c<146> l<19:46> el<19:53>
+n<> u<148> t<Expression> p<154> c<147> s<153> l<19:46> el<19:53>
+n<rotate_by> u<149> t<StringConst> p<150> l<19:57> el<19:66>
+n<> u<150> t<Primary_literal> p<151> c<149> l<19:57> el<19:66>
+n<> u<151> t<Primary> p<152> c<150> l<19:57> el<19:66>
+n<> u<152> t<Expression> p<154> c<151> l<19:57> el<19:66>
+n<> u<153> t<BinOp_ShiftLeft> p<154> s<152> l<19:54> el<19:56>
+n<> u<154> t<Expression> p<155> c<148> l<19:46> el<19:66>
+n<> u<155> t<Expression> p<157> c<154> l<19:45> el<19:67>
+n<> u<156> t<BinOp_Equiv> p<157> s<155> l<19:42> el<19:44>
+n<> u<157> t<Expression> p<177> c<144> s<176> l<19:34> el<19:67>
+n<word_in> u<158> t<StringConst> p<159> l<19:71> el<19:78>
+n<> u<159> t<Primary_literal> p<160> c<158> l<19:71> el<19:78>
+n<> u<160> t<Primary> p<161> c<159> l<19:71> el<19:78>
+n<> u<161> t<Expression> p<174> c<160> s<173> l<19:71> el<19:78>
+n<32> u<162> t<IntConst> p<163> l<19:83> el<19:85>
+n<> u<163> t<Primary_literal> p<164> c<162> l<19:83> el<19:85>
+n<> u<164> t<Primary> p<165> c<163> l<19:83> el<19:85>
+n<> u<165> t<Expression> p<171> c<164> s<170> l<19:83> el<19:85>
+n<rotate_by> u<166> t<StringConst> p<167> l<19:86> el<19:95>
+n<> u<167> t<Primary_literal> p<168> c<166> l<19:86> el<19:95>
+n<> u<168> t<Primary> p<169> c<167> l<19:86> el<19:95>
+n<> u<169> t<Expression> p<171> c<168> l<19:86> el<19:95>
+n<> u<170> t<BinOp_Minus> p<171> s<169> l<19:85> el<19:86>
+n<> u<171> t<Expression> p<172> c<165> l<19:83> el<19:95>
+n<> u<172> t<Expression> p<174> c<171> l<19:82> el<19:96>
+n<> u<173> t<BinOp_ShiftRight> p<174> s<172> l<19:79> el<19:81>
+n<> u<174> t<Expression> p<175> c<161> l<19:71> el<19:96>
+n<> u<175> t<Expression> p<177> c<174> l<19:70> el<19:97>
+n<> u<176> t<BinOp_BitwOr> p<177> s<175> l<19:68> el<19:69>
+n<> u<177> t<Expression> p<178> c<157> l<19:34> el<19:97>
+n<> u<178> t<Expression> p<179> c<177> l<19:33> el<19:98>
+n<> u<179> t<Expression_or_dist> p<180> c<178> l<19:33> el<19:98>
+n<> u<180> t<Sequence_expr> p<181> c<179> l<19:33> el<19:98>
+n<> u<181> t<Property_expr> p<183> c<180> l<19:33> el<19:98>
+n<> u<182> t<OVERLAP_IMPLY> p<183> s<181> l<19:29> el<19:32>
+n<> u<183> t<Property_expr> p<184> c<140> l<19:20> el<19:98>
+n<> u<184> t<Property_spec> p<186> c<131> s<185> l<19:5> el<19:98>
+n<> u<185> t<ENDPROPERTY> p<186> l<20:3> el<20:14>
+n<> u<186> t<Property_declaration> p<187> c<124> l<18:3> el<20:14>
+n<> u<187> t<Assertion_item_declaration> p<188> c<186> l<18:3> el<20:14>
+n<> u<188> t<Package_or_generate_item_declaration> p<189> c<187> l<18:3> el<20:14>
+n<> u<189> t<Module_or_generate_item_declaration> p<190> c<188> l<18:3> el<20:14>
+n<> u<190> t<Module_common_item> p<191> c<189> l<18:3> el<20:14>
+n<> u<191> t<Module_or_generate_item> p<192> c<190> l<18:3> el<20:14>
+n<> u<192> t<Non_port_module_item> p<344> c<191> s<210> l<18:3> el<20:14>
+n<a_valid_rotation> u<193> t<StringConst> p<206> s<205> l<21:3> el<21:19>
+n<p_valid_rotation> u<194> t<StringConst> p<195> l<21:37> el<21:53>
+n<> u<195> t<Primary_literal> p<196> c<194> l<21:37> el<21:53>
+n<> u<196> t<Primary> p<197> c<195> l<21:37> el<21:53>
+n<> u<197> t<Expression> p<198> c<196> l<21:37> el<21:53>
+n<> u<198> t<Expression_or_dist> p<199> c<197> l<21:37> el<21:53>
+n<> u<199> t<Sequence_expr> p<200> c<198> l<21:37> el<21:53>
+n<> u<200> t<Property_expr> p<201> c<199> l<21:37> el<21:53>
+n<> u<201> t<Property_spec> p<204> c<200> s<203> l<21:37> el<21:53>
+n<> u<202> t<Statement_or_null> p<203> l<21:54> el<21:55>
+n<> u<203> t<Action_block> p<204> c<202> l<21:54> el<21:55>
+n<> u<204> t<Assert_property_statement> p<205> c<201> l<21:21> el<21:55>
+n<> u<205> t<Concurrent_assertion_statement> p<206> c<204> l<21:21> el<21:55>
+n<> u<206> t<Concurrent_assertion_item> p<207> c<193> l<21:3> el<21:55>
+n<> u<207> t<Assertion_item> p<208> c<206> l<21:3> el<21:55>
+n<> u<208> t<Module_common_item> p<209> c<207> l<21:3> el<21:55>
+n<> u<209> t<Module_or_generate_item> p<210> c<208> l<21:3> el<21:55>
+n<> u<210> t<Non_port_module_item> p<344> c<209> s<252> l<21:3> el<21:55>
+n<p_rotation_range> u<211> t<StringConst> p<246> s<244> l<24:12> el<24:28>
+n<> u<212> t<Edge_Posedge> p<217> s<216> l<25:7> el<25:14>
+n<clk> u<213> t<StringConst> p<214> l<25:15> el<25:18>
+n<> u<214> t<Primary_literal> p<215> c<213> l<25:15> el<25:18>
+n<> u<215> t<Primary> p<216> c<214> l<25:15> el<25:18>
+n<> u<216> t<Expression> p<217> c<215> l<25:15> el<25:18>
+n<> u<217> t<Event_expression> p<218> c<212> l<25:7> el<25:18>
+n<> u<218> t<Clocking_event> p<244> c<217> s<243> l<25:5> el<25:19>
+n<rst_n> u<219> t<StringConst> p<220> l<25:22> el<25:27>
+n<> u<220> t<Primary_literal> p<221> c<219> l<25:22> el<25:27>
+n<> u<221> t<Primary> p<222> c<220> l<25:22> el<25:27>
+n<> u<222> t<Expression> p<224> c<221> l<25:22> el<25:27>
+n<> u<223> t<Unary_Not> p<224> s<222> l<25:21> el<25:22>
+n<> u<224> t<Expression> p<225> c<223> l<25:21> el<25:27>
+n<> u<225> t<Expression> p<226> c<224> l<25:20> el<25:28>
+n<> u<226> t<Expression_or_dist> p<227> c<225> l<25:20> el<25:28>
+n<> u<227> t<Sequence_expr> p<243> c<226> s<242> l<25:20> el<25:28>
+n<rotate_by> u<228> t<StringConst> p<229> l<25:34> el<25:43>
+n<> u<229> t<Primary_literal> p<230> c<228> l<25:34> el<25:43>
+n<> u<230> t<Primary> p<231> c<229> l<25:34> el<25:43>
+n<> u<231> t<Expression> p<237> c<230> s<236> l<25:34> el<25:43>
+n<5'd31> u<232> t<IntConst> p<233> l<25:47> el<25:52>
+n<> u<233> t<Primary_literal> p<234> c<232> l<25:47> el<25:52>
+n<> u<234> t<Primary> p<235> c<233> l<25:47> el<25:52>
+n<> u<235> t<Expression> p<237> c<234> l<25:47> el<25:52>
+n<> u<236> t<BinOp_LessEqual> p<237> s<235> l<25:44> el<25:46>
+n<> u<237> t<Expression> p<238> c<231> l<25:34> el<25:52>
+n<> u<238> t<Expression> p<239> c<237> l<25:33> el<25:53>
+n<> u<239> t<Expression_or_dist> p<240> c<238> l<25:33> el<25:53>
+n<> u<240> t<Sequence_expr> p<241> c<239> l<25:33> el<25:53>
+n<> u<241> t<Property_expr> p<243> c<240> l<25:33> el<25:53>
+n<> u<242> t<OVERLAP_IMPLY> p<243> s<241> l<25:29> el<25:32>
+n<> u<243> t<Property_expr> p<244> c<227> l<25:20> el<25:53>
+n<> u<244> t<Property_spec> p<246> c<218> s<245> l<25:5> el<25:53>
+n<> u<245> t<ENDPROPERTY> p<246> l<26:3> el<26:14>
+n<> u<246> t<Property_declaration> p<247> c<211> l<24:3> el<26:14>
+n<> u<247> t<Assertion_item_declaration> p<248> c<246> l<24:3> el<26:14>
+n<> u<248> t<Package_or_generate_item_declaration> p<249> c<247> l<24:3> el<26:14>
+n<> u<249> t<Module_or_generate_item_declaration> p<250> c<248> l<24:3> el<26:14>
+n<> u<250> t<Module_common_item> p<251> c<249> l<24:3> el<26:14>
+n<> u<251> t<Module_or_generate_item> p<252> c<250> l<24:3> el<26:14>
+n<> u<252> t<Non_port_module_item> p<344> c<251> s<270> l<24:3> el<26:14>
+n<a_rotation_range> u<253> t<StringConst> p<266> s<265> l<27:3> el<27:19>
+n<p_rotation_range> u<254> t<StringConst> p<255> l<27:37> el<27:53>
+n<> u<255> t<Primary_literal> p<256> c<254> l<27:37> el<27:53>
+n<> u<256> t<Primary> p<257> c<255> l<27:37> el<27:53>
+n<> u<257> t<Expression> p<258> c<256> l<27:37> el<27:53>
+n<> u<258> t<Expression_or_dist> p<259> c<257> l<27:37> el<27:53>
+n<> u<259> t<Sequence_expr> p<260> c<258> l<27:37> el<27:53>
+n<> u<260> t<Property_expr> p<261> c<259> l<27:37> el<27:53>
+n<> u<261> t<Property_spec> p<264> c<260> s<263> l<27:37> el<27:53>
+n<> u<262> t<Statement_or_null> p<263> l<27:54> el<27:55>
+n<> u<263> t<Action_block> p<264> c<262> l<27:54> el<27:55>
+n<> u<264> t<Assert_property_statement> p<265> c<261> l<27:21> el<27:55>
+n<> u<265> t<Concurrent_assertion_statement> p<266> c<264> l<27:21> el<27:55>
+n<> u<266> t<Concurrent_assertion_item> p<267> c<253> l<27:3> el<27:55>
+n<> u<267> t<Assertion_item> p<268> c<266> l<27:3> el<27:55>
+n<> u<268> t<Module_common_item> p<269> c<267> l<27:3> el<27:55>
+n<> u<269> t<Module_or_generate_item> p<270> c<268> l<27:3> el<27:55>
+n<> u<270> t<Non_port_module_item> p<344> c<269> s<324> l<27:3> el<27:55>
+n<p_no_rotation> u<271> t<StringConst> p<318> s<316> l<30:12> el<30:25>
+n<> u<272> t<Edge_Posedge> p<277> s<276> l<31:7> el<31:14>
+n<clk> u<273> t<StringConst> p<274> l<31:15> el<31:18>
+n<> u<274> t<Primary_literal> p<275> c<273> l<31:15> el<31:18>
+n<> u<275> t<Primary> p<276> c<274> l<31:15> el<31:18>
+n<> u<276> t<Expression> p<277> c<275> l<31:15> el<31:18>
+n<> u<277> t<Event_expression> p<278> c<272> l<31:7> el<31:18>
+n<> u<278> t<Clocking_event> p<316> c<277> s<315> l<31:5> el<31:19>
+n<rst_n> u<279> t<StringConst> p<280> l<31:22> el<31:27>
+n<> u<280> t<Primary_literal> p<281> c<279> l<31:22> el<31:27>
+n<> u<281> t<Primary> p<282> c<280> l<31:22> el<31:27>
+n<> u<282> t<Expression> p<284> c<281> l<31:22> el<31:27>
+n<> u<283> t<Unary_Not> p<284> s<282> l<31:21> el<31:22>
+n<> u<284> t<Expression> p<296> c<283> s<295> l<31:21> el<31:27>
+n<rotate_by> u<285> t<StringConst> p<286> l<31:31> el<31:40>
+n<> u<286> t<Primary_literal> p<287> c<285> l<31:31> el<31:40>
+n<> u<287> t<Primary> p<288> c<286> l<31:31> el<31:40>
+n<> u<288> t<Expression> p<294> c<287> s<293> l<31:31> el<31:40>
+n<0> u<289> t<IntConst> p<290> l<31:44> el<31:45>
+n<> u<290> t<Primary_literal> p<291> c<289> l<31:44> el<31:45>
+n<> u<291> t<Primary> p<292> c<290> l<31:44> el<31:45>
+n<> u<292> t<Expression> p<294> c<291> l<31:44> el<31:45>
+n<> u<293> t<BinOp_Equiv> p<294> s<292> l<31:41> el<31:43>
+n<> u<294> t<Expression> p<296> c<288> l<31:31> el<31:45>
+n<> u<295> t<BinOp_LogicAnd> p<296> s<294> l<31:28> el<31:30>
+n<> u<296> t<Expression> p<297> c<284> l<31:21> el<31:45>
+n<> u<297> t<Expression> p<298> c<296> l<31:20> el<31:46>
+n<> u<298> t<Expression_or_dist> p<299> c<297> l<31:20> el<31:46>
+n<> u<299> t<Sequence_expr> p<315> c<298> s<314> l<31:20> el<31:46>
+n<rotated> u<300> t<StringConst> p<301> l<31:52> el<31:59>
+n<> u<301> t<Primary_literal> p<302> c<300> l<31:52> el<31:59>
+n<> u<302> t<Primary> p<303> c<301> l<31:52> el<31:59>
+n<> u<303> t<Expression> p<309> c<302> s<308> l<31:52> el<31:59>
+n<word_in> u<304> t<StringConst> p<305> l<31:63> el<31:70>
+n<> u<305> t<Primary_literal> p<306> c<304> l<31:63> el<31:70>
+n<> u<306> t<Primary> p<307> c<305> l<31:63> el<31:70>
+n<> u<307> t<Expression> p<309> c<306> l<31:63> el<31:70>
+n<> u<308> t<BinOp_Equiv> p<309> s<307> l<31:60> el<31:62>
+n<> u<309> t<Expression> p<310> c<303> l<31:52> el<31:70>
+n<> u<310> t<Expression> p<311> c<309> l<31:51> el<31:71>
+n<> u<311> t<Expression_or_dist> p<312> c<310> l<31:51> el<31:71>
+n<> u<312> t<Sequence_expr> p<313> c<311> l<31:51> el<31:71>
+n<> u<313> t<Property_expr> p<315> c<312> l<31:51> el<31:71>
+n<> u<314> t<OVERLAP_IMPLY> p<315> s<313> l<31:47> el<31:50>
+n<> u<315> t<Property_expr> p<316> c<299> l<31:20> el<31:71>
+n<> u<316> t<Property_spec> p<318> c<278> s<317> l<31:5> el<31:71>
+n<> u<317> t<ENDPROPERTY> p<318> l<32:3> el<32:14>
+n<> u<318> t<Property_declaration> p<319> c<271> l<30:3> el<32:14>
+n<> u<319> t<Assertion_item_declaration> p<320> c<318> l<30:3> el<32:14>
+n<> u<320> t<Package_or_generate_item_declaration> p<321> c<319> l<30:3> el<32:14>
+n<> u<321> t<Module_or_generate_item_declaration> p<322> c<320> l<30:3> el<32:14>
+n<> u<322> t<Module_common_item> p<323> c<321> l<30:3> el<32:14>
+n<> u<323> t<Module_or_generate_item> p<324> c<322> l<30:3> el<32:14>
+n<> u<324> t<Non_port_module_item> p<344> c<323> s<342> l<30:3> el<32:14>
+n<a_no_rotation> u<325> t<StringConst> p<338> s<337> l<33:3> el<33:16>
+n<p_no_rotation> u<326> t<StringConst> p<327> l<33:34> el<33:47>
+n<> u<327> t<Primary_literal> p<328> c<326> l<33:34> el<33:47>
+n<> u<328> t<Primary> p<329> c<327> l<33:34> el<33:47>
+n<> u<329> t<Expression> p<330> c<328> l<33:34> el<33:47>
+n<> u<330> t<Expression_or_dist> p<331> c<329> l<33:34> el<33:47>
+n<> u<331> t<Sequence_expr> p<332> c<330> l<33:34> el<33:47>
+n<> u<332> t<Property_expr> p<333> c<331> l<33:34> el<33:47>
+n<> u<333> t<Property_spec> p<336> c<332> s<335> l<33:34> el<33:47>
+n<> u<334> t<Statement_or_null> p<335> l<33:48> el<33:49>
+n<> u<335> t<Action_block> p<336> c<334> l<33:48> el<33:49>
+n<> u<336> t<Assert_property_statement> p<337> c<333> l<33:18> el<33:49>
+n<> u<337> t<Concurrent_assertion_statement> p<338> c<336> l<33:18> el<33:49>
+n<> u<338> t<Concurrent_assertion_item> p<339> c<325> l<33:3> el<33:49>
+n<> u<339> t<Assertion_item> p<340> c<338> l<33:3> el<33:49>
+n<> u<340> t<Module_common_item> p<341> c<339> l<33:3> el<33:49>
+n<> u<341> t<Module_or_generate_item> p<342> c<340> l<33:3> el<33:49>
+n<> u<342> t<Non_port_module_item> p<344> c<341> s<343> l<33:3> el<33:49>
+n<> u<343> t<ENDMODULE> p<344> l<35:1> el<35:10>
+n<> u<344> t<Module_declaration> p<345> c<65> l<1:1> el<35:10>
+n<> u<345> t<Description> p<392> c<344> s<391> l<1:1> el<35:10>
+n<left_rotation> u<346> t<StringConst> p<390> s<389> l<37:6> el<37:19>
+n<left_rotate_assertions> u<347> t<StringConst> p<388> s<387> l<37:20> el<37:42>
+n<u_left_rotate_assertions> u<348> t<StringConst> p<349> l<37:43> el<37:67>
+n<> u<349> t<Name_of_instance> p<387> c<348> s<386> l<37:43> el<37:67>
+n<clk> u<350> t<StringConst> p<357> s<355> l<38:6> el<38:9>
+n<clk> u<351> t<StringConst> p<352> l<38:10> el<38:13>
+n<> u<352> t<Primary_literal> p<353> c<351> l<38:10> el<38:13>
+n<> u<353> t<Primary> p<354> c<352> l<38:10> el<38:13>
+n<> u<354> t<Expression> p<357> c<353> s<356> l<38:10> el<38:13>
+n<> u<355> t<OPEN_PARENS> p<357> s<354> l<38:9> el<38:10>
+n<> u<356> t<CLOSE_PARENS> p<357> l<38:13> el<38:14>
+n<> u<357> t<Named_port_connection> p<386> c<350> s<365> l<38:5> el<38:14>
+n<rst_n> u<358> t<StringConst> p<365> s<363> l<39:4> el<39:9>
+n<reset> u<359> t<StringConst> p<360> l<39:10> el<39:15>
+n<> u<360> t<Primary_literal> p<361> c<359> l<39:10> el<39:15>
+n<> u<361> t<Primary> p<362> c<360> l<39:10> el<39:15>
+n<> u<362> t<Expression> p<365> c<361> s<364> l<39:10> el<39:15>
+n<> u<363> t<OPEN_PARENS> p<365> s<362> l<39:9> el<39:10>
+n<> u<364> t<CLOSE_PARENS> p<365> l<39:15> el<39:16>
+n<> u<365> t<Named_port_connection> p<386> c<358> s<373> l<39:3> el<39:16>
+n<word_in> u<366> t<StringConst> p<373> s<371> l<40:4> el<40:11>
+n<in_data> u<367> t<StringConst> p<368> l<40:12> el<40:19>
+n<> u<368> t<Primary_literal> p<369> c<367> l<40:12> el<40:19>
+n<> u<369> t<Primary> p<370> c<368> l<40:12> el<40:19>
+n<> u<370> t<Expression> p<373> c<369> s<372> l<40:12> el<40:19>
+n<> u<371> t<OPEN_PARENS> p<373> s<370> l<40:11> el<40:12>
+n<> u<372> t<CLOSE_PARENS> p<373> l<40:19> el<40:20>
+n<> u<373> t<Named_port_connection> p<386> c<366> s<377> l<40:3> el<40:20>
+n<rotate_by> u<374> t<StringConst> p<377> s<375> l<41:6> el<41:15>
+n<> u<375> t<OPEN_PARENS> p<377> s<376> l<41:15> el<41:16>
+n<> u<376> t<CLOSE_PARENS> p<377> l<41:16> el<41:17>
+n<> u<377> t<Named_port_connection> p<386> c<374> s<385> l<41:5> el<41:17>
+n<rotated> u<378> t<StringConst> p<385> s<383> l<42:4> el<42:11>
+n<out_data> u<379> t<StringConst> p<380> l<42:12> el<42:20>
+n<> u<380> t<Primary_literal> p<381> c<379> l<42:12> el<42:20>
+n<> u<381> t<Primary> p<382> c<380> l<42:12> el<42:20>
+n<> u<382> t<Expression> p<385> c<381> s<384> l<42:12> el<42:20>
+n<> u<383> t<OPEN_PARENS> p<385> s<382> l<42:11> el<42:12>
+n<> u<384> t<CLOSE_PARENS> p<385> l<42:20> el<42:21>
+n<> u<385> t<Named_port_connection> p<386> c<378> l<42:3> el<42:21>
+n<> u<386> t<List_of_port_connections> p<387> c<357> l<38:5> el<42:21>
+n<> u<387> t<Hierarchical_instance> p<388> c<349> l<37:43> el<43:2>
+n<> u<388> t<Module_instantiation> p<389> c<347> l<37:20> el<43:3>
+n<> u<389> t<Bind_instantiation> p<390> c<388> l<37:20> el<43:3>
+n<> u<390> t<Bind_directive> p<391> c<346> l<37:1> el<43:3>
+n<> u<391> t<Description> p<392> c<390> l<37:1> el<43:3>
+n<> u<392> t<Source_text> p<393> c<345> l<1:1> el<43:3>
+n<> u<393> t<Top_level_rule> c<1> l<1:1> el<44:1>
+AST_DEBUG_END
+AST_DEBUG_BEGIN
+LIB:  work
+FILE: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<183> s<182> l<1:1> el<1:0>
+n<module> u<2> t<Module_keyword> p<54> s<3> l<1:1> el<1:7>
+n<left_rotation> u<3> t<StringConst> p<54> s<53> l<1:8> el<1:21>
+n<> u<4> t<PortDir_Inp> p<8> s<7> l<2:5> el<2:10>
+n<> u<5> t<NetType_Wire> p<7> s<6> l<2:11> el<2:15>
+n<> u<6> t<Data_type_or_implicit> p<7> l<2:16> el<2:16>
+n<> u<7> t<Net_port_type> p<8> c<5> l<2:11> el<2:15>
+n<> u<8> t<Net_port_header> p<10> c<4> s<9> l<2:5> el<2:15>
+n<clk> u<9> t<StringConst> p<10> l<2:16> el<2:19>
+n<> u<10> t<Ansi_port_declaration> p<53> c<8> s<17> l<2:5> el<2:19>
+n<> u<11> t<PortDir_Inp> p<15> s<14> l<3:5> el<3:10>
+n<> u<12> t<NetType_Wire> p<14> s<13> l<3:11> el<3:15>
+n<> u<13> t<Data_type_or_implicit> p<14> l<3:16> el<3:16>
+n<> u<14> t<Net_port_type> p<15> c<12> l<3:11> el<3:15>
+n<> u<15> t<Net_port_header> p<17> c<11> s<16> l<3:5> el<3:15>
+n<reset> u<16> t<StringConst> p<17> l<3:16> el<3:21>
+n<> u<17> t<Ansi_port_declaration> p<53> c<15> s<34> l<3:5> el<3:21>
+n<> u<18> t<PortDir_Inp> p<32> s<31> l<4:5> el<4:10>
+n<> u<19> t<NetType_Wire> p<31> s<30> l<4:11> el<4:15>
+n<7> u<20> t<IntConst> p<21> l<4:17> el<4:18>
+n<> u<21> t<Primary_literal> p<22> c<20> l<4:17> el<4:18>
+n<> u<22> t<Constant_primary> p<23> c<21> l<4:17> el<4:18>
+n<> u<23> t<Constant_expression> p<28> c<22> s<27> l<4:17> el<4:18>
+n<0> u<24> t<IntConst> p<25> l<4:19> el<4:20>
+n<> u<25> t<Primary_literal> p<26> c<24> l<4:19> el<4:20>
+n<> u<26> t<Constant_primary> p<27> c<25> l<4:19> el<4:20>
+n<> u<27> t<Constant_expression> p<28> c<26> l<4:19> el<4:20>
+n<> u<28> t<Constant_range> p<29> c<23> l<4:17> el<4:20>
+n<> u<29> t<Packed_dimension> p<30> c<28> l<4:16> el<4:21>
+n<> u<30> t<Data_type_or_implicit> p<31> c<29> l<4:16> el<4:21>
+n<> u<31> t<Net_port_type> p<32> c<19> l<4:11> el<4:21>
+n<> u<32> t<Net_port_header> p<34> c<18> s<33> l<4:5> el<4:21>
+n<in_data> u<33> t<StringConst> p<34> l<4:22> el<4:29>
+n<> u<34> t<Ansi_port_declaration> p<53> c<32> s<52> l<4:5> el<4:29>
+n<> u<35> t<PortDir_Out> p<50> s<49> l<5:5> el<5:11>
+n<> u<36> t<IntVec_TypeReg> p<47> s<46> l<5:12> el<5:15>
+n<7> u<37> t<IntConst> p<38> l<5:17> el<5:18>
+n<> u<38> t<Primary_literal> p<39> c<37> l<5:17> el<5:18>
+n<> u<39> t<Constant_primary> p<40> c<38> l<5:17> el<5:18>
+n<> u<40> t<Constant_expression> p<45> c<39> s<44> l<5:17> el<5:18>
+n<0> u<41> t<IntConst> p<42> l<5:19> el<5:20>
+n<> u<42> t<Primary_literal> p<43> c<41> l<5:19> el<5:20>
+n<> u<43> t<Constant_primary> p<44> c<42> l<5:19> el<5:20>
+n<> u<44> t<Constant_expression> p<45> c<43> l<5:19> el<5:20>
+n<> u<45> t<Constant_range> p<46> c<40> l<5:17> el<5:20>
+n<> u<46> t<Packed_dimension> p<47> c<45> l<5:16> el<5:21>
+n<> u<47> t<Data_type> p<48> c<36> l<5:12> el<5:21>
+n<> u<48> t<Data_type_or_implicit> p<49> c<47> l<5:12> el<5:21>
+n<> u<49> t<Net_port_type> p<50> c<48> l<5:12> el<5:21>
+n<> u<50> t<Net_port_header> p<52> c<35> s<51> l<5:5> el<5:21>
+n<out_data> u<51> t<StringConst> p<52> l<5:22> el<5:30>
+n<> u<52> t<Ansi_port_declaration> p<53> c<50> l<5:5> el<5:30>
+n<> u<53> t<List_of_port_declarations> p<54> c<10> l<1:22> el<6:2>
+n<> u<54> t<Module_ansi_header> p<180> c<2> s<154> l<1:1> el<6:3>
+n<> u<55> t<ALWAYS> p<151> s<150> l<8:1> el<8:7>
+n<> u<56> t<Edge_Posedge> p<61> s<60> l<8:10> el<8:17>
+n<clk> u<57> t<StringConst> p<58> l<8:18> el<8:21>
+n<> u<58> t<Primary_literal> p<59> c<57> l<8:18> el<8:21>
+n<> u<59> t<Primary> p<60> c<58> l<8:18> el<8:21>
+n<> u<60> t<Expression> p<61> c<59> l<8:18> el<8:21>
+n<> u<61> t<Event_expression> p<69> c<56> s<62> l<8:10> el<8:21>
+n<> u<62> t<Or_operator> p<69> s<68> l<8:22> el<8:24>
+n<> u<63> t<Edge_Posedge> p<68> s<67> l<8:25> el<8:32>
+n<reset> u<64> t<StringConst> p<65> l<8:33> el<8:38>
+n<> u<65> t<Primary_literal> p<66> c<64> l<8:33> el<8:38>
+n<> u<66> t<Primary> p<67> c<65> l<8:33> el<8:38>
+n<> u<67> t<Expression> p<68> c<66> l<8:33> el<8:38>
+n<> u<68> t<Event_expression> p<69> c<63> l<8:25> el<8:38>
+n<> u<69> t<Event_expression> p<70> c<61> l<8:10> el<8:38>
+n<> u<70> t<Event_control> p<71> c<69> l<8:8> el<8:39>
+n<> u<71> t<Procedural_timing_control> p<148> c<70> s<147> l<8:8> el<8:39>
+n<reset> u<72> t<StringConst> p<73> l<9:9> el<9:14>
+n<> u<73> t<Primary_literal> p<74> c<72> l<9:9> el<9:14>
+n<> u<74> t<Primary> p<75> c<73> l<9:9> el<9:14>
+n<> u<75> t<Expression> p<76> c<74> l<9:9> el<9:14>
+n<> u<76> t<Expression_or_cond_pattern> p<77> c<75> l<9:9> el<9:14>
+n<> u<77> t<Cond_predicate> p<139> c<76> s<95> l<9:9> el<9:14>
+n<out_data> u<78> t<StringConst> p<79> l<10:9> el<10:17>
+n<> u<79> t<Ps_or_hierarchical_identifier> p<82> c<78> s<81> l<10:9> el<10:17>
+n<> u<80> t<Bit_select> p<81> l<10:18> el<10:18>
+n<> u<81> t<Select> p<82> c<80> l<10:18> el<10:18>
+n<> u<82> t<Variable_lvalue> p<87> c<79> s<86> l<10:9> el<10:17>
+n<8'b0000_0000> u<83> t<IntConst> p<84> l<10:21> el<10:33>
+n<> u<84> t<Primary_literal> p<85> c<83> l<10:21> el<10:33>
+n<> u<85> t<Primary> p<86> c<84> l<10:21> el<10:33>
+n<> u<86> t<Expression> p<87> c<85> l<10:21> el<10:33>
+n<> u<87> t<Nonblocking_assignment> p<88> c<82> l<10:9> el<10:33>
+n<> u<88> t<Statement_item> p<89> c<87> l<10:9> el<10:34>
+n<> u<89> t<Statement> p<90> c<88> l<10:9> el<10:34>
+n<> u<90> t<Statement_or_null> p<92> c<89> s<91> l<10:9> el<10:34>
+n<> u<91> t<END> p<92> l<11:5> el<11:8>
+n<> u<92> t<Seq_block> p<93> c<90> l<9:16> el<11:8>
+n<> u<93> t<Statement_item> p<94> c<92> l<9:16> el<11:8>
+n<> u<94> t<Statement> p<95> c<93> l<9:16> el<11:8>
+n<> u<95> t<Statement_or_null> p<139> c<94> s<138> l<9:16> el<11:8>
+n<out_data> u<96> t<StringConst> p<97> l<13:9> el<13:17>
+n<> u<97> t<Ps_or_hierarchical_identifier> p<100> c<96> s<99> l<13:9> el<13:17>
+n<> u<98> t<Bit_select> p<99> l<13:18> el<13:18>
+n<> u<99> t<Select> p<100> c<98> l<13:18> el<13:18>
+n<> u<100> t<Variable_lvalue> p<130> c<97> s<129> l<13:9> el<13:17>
+n<out_data> u<101> t<StringConst> p<114> s<113> l<13:22> el<13:30>
+n<> u<102> t<Bit_select> p<113> s<112> l<13:30> el<13:30>
+n<6> u<103> t<IntConst> p<104> l<13:31> el<13:32>
+n<> u<104> t<Primary_literal> p<105> c<103> l<13:31> el<13:32>
+n<> u<105> t<Constant_primary> p<106> c<104> l<13:31> el<13:32>
+n<> u<106> t<Constant_expression> p<111> c<105> s<110> l<13:31> el<13:32>
+n<0> u<107> t<IntConst> p<108> l<13:33> el<13:34>
+n<> u<108> t<Primary_literal> p<109> c<107> l<13:33> el<13:34>
+n<> u<109> t<Constant_primary> p<110> c<108> l<13:33> el<13:34>
+n<> u<110> t<Constant_expression> p<111> c<109> l<13:33> el<13:34>
+n<> u<111> t<Constant_range> p<112> c<106> l<13:31> el<13:34>
+n<> u<112> t<Part_select_range> p<113> c<111> l<13:31> el<13:34>
+n<> u<113> t<Select> p<114> c<102> l<13:30> el<13:35>
+n<> u<114> t<Complex_func_call> p<115> c<101> l<13:22> el<13:35>
+n<> u<115> t<Primary> p<116> c<114> l<13:22> el<13:35>
+n<> u<116> t<Expression> p<127> c<115> s<126> l<13:22> el<13:35>
+n<out_data> u<117> t<StringConst> p<124> s<123> l<13:37> el<13:45>
+n<7> u<118> t<IntConst> p<119> l<13:46> el<13:47>
+n<> u<119> t<Primary_literal> p<120> c<118> l<13:46> el<13:47>
+n<> u<120> t<Primary> p<121> c<119> l<13:46> el<13:47>
+n<> u<121> t<Expression> p<122> c<120> l<13:46> el<13:47>
+n<> u<122> t<Bit_select> p<123> c<121> l<13:45> el<13:48>
+n<> u<123> t<Select> p<124> c<122> l<13:45> el<13:48>
+n<> u<124> t<Complex_func_call> p<125> c<117> l<13:37> el<13:48>
+n<> u<125> t<Primary> p<126> c<124> l<13:37> el<13:48>
+n<> u<126> t<Expression> p<127> c<125> l<13:37> el<13:48>
+n<> u<127> t<Concatenation> p<128> c<116> l<13:21> el<13:49>
+n<> u<128> t<Primary> p<129> c<127> l<13:21> el<13:49>
+n<> u<129> t<Expression> p<130> c<128> l<13:21> el<13:49>
+n<> u<130> t<Nonblocking_assignment> p<131> c<100> l<13:9> el<13:49>
+n<> u<131> t<Statement_item> p<132> c<130> l<13:9> el<13:50>
+n<> u<132> t<Statement> p<133> c<131> l<13:9> el<13:50>
+n<> u<133> t<Statement_or_null> p<135> c<132> s<134> l<13:9> el<13:50>
+n<> u<134> t<END> p<135> l<14:5> el<14:8>
+n<> u<135> t<Seq_block> p<136> c<133> l<11:14> el<14:8>
+n<> u<136> t<Statement_item> p<137> c<135> l<11:14> el<14:8>
+n<> u<137> t<Statement> p<138> c<136> l<11:14> el<14:8>
+n<> u<138> t<Statement_or_null> p<139> c<137> l<11:14> el<14:8>
+n<> u<139> t<Conditional_statement> p<140> c<77> l<9:5> el<14:8>
+n<> u<140> t<Statement_item> p<141> c<139> l<9:5> el<14:8>
+n<> u<141> t<Statement> p<142> c<140> l<9:5> el<14:8>
+n<> u<142> t<Statement_or_null> p<144> c<141> s<143> l<9:5> el<14:8>
+n<> u<143> t<END> p<144> l<15:1> el<15:4>
+n<> u<144> t<Seq_block> p<145> c<142> l<8:40> el<15:4>
+n<> u<145> t<Statement_item> p<146> c<144> l<8:40> el<15:4>
+n<> u<146> t<Statement> p<147> c<145> l<8:40> el<15:4>
+n<> u<147> t<Statement_or_null> p<148> c<146> l<8:40> el<15:4>
+n<> u<148> t<Procedural_timing_control_statement> p<149> c<71> l<8:8> el<15:4>
+n<> u<149> t<Statement_item> p<150> c<148> l<8:8> el<15:4>
+n<> u<150> t<Statement> p<151> c<149> l<8:8> el<15:4>
+n<> u<151> t<Always_construct> p<152> c<55> l<8:1> el<15:4>
+n<> u<152> t<Module_common_item> p<153> c<151> l<8:1> el<15:4>
+n<> u<153> t<Module_or_generate_item> p<154> c<152> l<8:1> el<15:4>
+n<> u<154> t<Non_port_module_item> p<180> c<153> s<178> l<8:1> el<15:4>
+n<out_data> u<155> t<StringConst> p<156> l<18:5> el<18:13>
+n<> u<156> t<Ps_or_hierarchical_identifier> p<159> c<155> s<158> l<18:5> el<18:13>
+n<> u<157> t<Bit_select> p<158> l<18:14> el<18:14>
+n<> u<158> t<Select> p<159> c<157> l<18:14> el<18:14>
+n<> u<159> t<Variable_lvalue> p<165> c<156> s<160> l<18:5> el<18:13>
+n<> u<160> t<AssignOp_Assign> p<165> s<164> l<18:14> el<18:15>
+n<8'b0000_0000> u<161> t<IntConst> p<162> l<18:16> el<18:28>
+n<> u<162> t<Primary_literal> p<163> c<161> l<18:16> el<18:28>
+n<> u<163> t<Primary> p<164> c<162> l<18:16> el<18:28>
+n<> u<164> t<Expression> p<165> c<163> l<18:16> el<18:28>
+n<> u<165> t<Operator_assignment> p<166> c<159> l<18:5> el<18:28>
+n<> u<166> t<Blocking_assignment> p<167> c<165> l<18:5> el<18:28>
+n<> u<167> t<Statement_item> p<168> c<166> l<18:5> el<18:29>
+n<> u<168> t<Statement> p<169> c<167> l<18:5> el<18:29>
+n<> u<169> t<Statement_or_null> p<171> c<168> s<170> l<18:5> el<18:29>
+n<> u<170> t<END> p<171> l<19:1> el<19:4>
+n<> u<171> t<Seq_block> p<172> c<169> l<17:9> el<19:4>
+n<> u<172> t<Statement_item> p<173> c<171> l<17:9> el<19:4>
+n<> u<173> t<Statement> p<174> c<172> l<17:9> el<19:4>
+n<> u<174> t<Statement_or_null> p<175> c<173> l<17:9> el<19:4>
+n<> u<175> t<Initial_construct> p<176> c<174> l<17:1> el<19:4>
+n<> u<176> t<Module_common_item> p<177> c<175> l<17:1> el<19:4>
+n<> u<177> t<Module_or_generate_item> p<178> c<176> l<17:1> el<19:4>
+n<> u<178> t<Non_port_module_item> p<180> c<177> s<179> l<17:1> el<19:4>
+n<> u<179> t<ENDMODULE> p<180> l<21:1> el<21:10>
+n<> u<180> t<Module_declaration> p<181> c<54> l<1:1> el<21:10>
+n<> u<181> t<Description> p<182> c<180> l<1:1> el<21:10>
+n<> u<182> t<Source_text> p<183> c<181> l<1:1> el<21:10>
+n<> u<183> t<Top_level_rule> c<1> l<1:1> el<23:1>
+AST_DEBUG_END
+AST_DEBUG_BEGIN
+LIB:  work
+FILE: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<351> s<350> l<2:1> el<1:2>
+n<module> u<2> t<Module_keyword> p<4> s<3> l<2:1> el<2:7>
+n<tb_left_rotation> u<3> t<StringConst> p<4> l<2:8> el<2:24>
+n<> u<4> t<Module_ansi_header> p<348> c<2> s<18> l<2:1> el<2:25>
+n<> u<5> t<IntVec_TypeReg> p<6> l<3:5> el<3:8>
+n<> u<6> t<Data_type> p<12> c<5> s<11> l<3:5> el<3:8>
+n<clk> u<7> t<StringConst> p<8> l<3:9> el<3:12>
+n<> u<8> t<Variable_decl_assignment> p<11> c<7> s<10> l<3:9> el<3:12>
+n<reset> u<9> t<StringConst> p<10> l<3:14> el<3:19>
+n<> u<10> t<Variable_decl_assignment> p<11> c<9> l<3:14> el<3:19>
+n<> u<11> t<List_of_variable_decl_assignments> p<12> c<8> l<3:9> el<3:19>
+n<> u<12> t<Variable_declaration> p<13> c<6> l<3:5> el<3:20>
+n<> u<13> t<Data_declaration> p<14> c<12> l<3:5> el<3:20>
+n<> u<14> t<Package_or_generate_item_declaration> p<15> c<13> l<3:5> el<3:20>
+n<> u<15> t<Module_or_generate_item_declaration> p<16> c<14> l<3:5> el<3:20>
+n<> u<16> t<Module_common_item> p<17> c<15> l<3:5> el<3:20>
+n<> u<17> t<Module_or_generate_item> p<18> c<16> l<3:5> el<3:20>
+n<> u<18> t<Non_port_module_item> p<348> c<17> s<40> l<3:5> el<3:20>
+n<> u<19> t<IntVec_TypeReg> p<30> s<29> l<4:5> el<4:8>
+n<7> u<20> t<IntConst> p<21> l<4:10> el<4:11>
+n<> u<21> t<Primary_literal> p<22> c<20> l<4:10> el<4:11>
+n<> u<22> t<Constant_primary> p<23> c<21> l<4:10> el<4:11>
+n<> u<23> t<Constant_expression> p<28> c<22> s<27> l<4:10> el<4:11>
+n<0> u<24> t<IntConst> p<25> l<4:12> el<4:13>
+n<> u<25> t<Primary_literal> p<26> c<24> l<4:12> el<4:13>
+n<> u<26> t<Constant_primary> p<27> c<25> l<4:12> el<4:13>
+n<> u<27> t<Constant_expression> p<28> c<26> l<4:12> el<4:13>
+n<> u<28> t<Constant_range> p<29> c<23> l<4:10> el<4:13>
+n<> u<29> t<Packed_dimension> p<30> c<28> l<4:9> el<4:14>
+n<> u<30> t<Data_type> p<34> c<19> s<33> l<4:5> el<4:14>
+n<in_data> u<31> t<StringConst> p<32> l<4:15> el<4:22>
+n<> u<32> t<Variable_decl_assignment> p<33> c<31> l<4:15> el<4:22>
+n<> u<33> t<List_of_variable_decl_assignments> p<34> c<32> l<4:15> el<4:22>
+n<> u<34> t<Variable_declaration> p<35> c<30> l<4:5> el<4:23>
+n<> u<35> t<Data_declaration> p<36> c<34> l<4:5> el<4:23>
+n<> u<36> t<Package_or_generate_item_declaration> p<37> c<35> l<4:5> el<4:23>
+n<> u<37> t<Module_or_generate_item_declaration> p<38> c<36> l<4:5> el<4:23>
+n<> u<38> t<Module_common_item> p<39> c<37> l<4:5> el<4:23>
+n<> u<39> t<Module_or_generate_item> p<40> c<38> l<4:5> el<4:23>
+n<> u<40> t<Non_port_module_item> p<348> c<39> s<61> l<4:5> el<4:23>
+n<> u<41> t<NetType_Wire> p<56> s<52> l<5:5> el<5:9>
+n<7> u<42> t<IntConst> p<43> l<5:11> el<5:12>
+n<> u<43> t<Primary_literal> p<44> c<42> l<5:11> el<5:12>
+n<> u<44> t<Constant_primary> p<45> c<43> l<5:11> el<5:12>
+n<> u<45> t<Constant_expression> p<50> c<44> s<49> l<5:11> el<5:12>
+n<0> u<46> t<IntConst> p<47> l<5:13> el<5:14>
+n<> u<47> t<Primary_literal> p<48> c<46> l<5:13> el<5:14>
+n<> u<48> t<Constant_primary> p<49> c<47> l<5:13> el<5:14>
+n<> u<49> t<Constant_expression> p<50> c<48> l<5:13> el<5:14>
+n<> u<50> t<Constant_range> p<51> c<45> l<5:11> el<5:14>
+n<> u<51> t<Packed_dimension> p<52> c<50> l<5:10> el<5:15>
+n<> u<52> t<Data_type_or_implicit> p<56> c<51> s<55> l<5:10> el<5:15>
+n<out_data> u<53> t<StringConst> p<54> l<5:16> el<5:24>
+n<> u<54> t<Net_decl_assignment> p<55> c<53> l<5:16> el<5:24>
+n<> u<55> t<List_of_net_decl_assignments> p<56> c<54> l<5:16> el<5:24>
+n<> u<56> t<Net_declaration> p<57> c<41> l<5:5> el<5:25>
+n<> u<57> t<Package_or_generate_item_declaration> p<58> c<56> l<5:5> el<5:25>
+n<> u<58> t<Module_or_generate_item_declaration> p<59> c<57> l<5:5> el<5:25>
+n<> u<59> t<Module_common_item> p<60> c<58> l<5:5> el<5:25>
+n<> u<60> t<Module_or_generate_item> p<61> c<59> l<5:5> el<5:25>
+n<> u<61> t<Non_port_module_item> p<348> c<60> s<101> l<5:5> el<5:25>
+n<left_rotation> u<62> t<StringConst> p<99> s<98> l<8:5> el<8:18>
+n<left_rotation_inst> u<63> t<StringConst> p<64> l<8:19> el<8:37>
+n<> u<64> t<Name_of_instance> p<98> c<63> s<97> l<8:19> el<8:37>
+n<clk> u<65> t<StringConst> p<72> s<70> l<9:10> el<9:13>
+n<clk> u<66> t<StringConst> p<67> l<9:14> el<9:17>
+n<> u<67> t<Primary_literal> p<68> c<66> l<9:14> el<9:17>
+n<> u<68> t<Primary> p<69> c<67> l<9:14> el<9:17>
+n<> u<69> t<Expression> p<72> c<68> s<71> l<9:14> el<9:17>
+n<> u<70> t<OPEN_PARENS> p<72> s<69> l<9:13> el<9:14>
+n<> u<71> t<CLOSE_PARENS> p<72> l<9:17> el<9:18>
+n<> u<72> t<Named_port_connection> p<97> c<65> s<80> l<9:9> el<9:18>
+n<reset> u<73> t<StringConst> p<80> s<78> l<10:10> el<10:15>
+n<reset> u<74> t<StringConst> p<75> l<10:16> el<10:21>
+n<> u<75> t<Primary_literal> p<76> c<74> l<10:16> el<10:21>
+n<> u<76> t<Primary> p<77> c<75> l<10:16> el<10:21>
+n<> u<77> t<Expression> p<80> c<76> s<79> l<10:16> el<10:21>
+n<> u<78> t<OPEN_PARENS> p<80> s<77> l<10:15> el<10:16>
+n<> u<79> t<CLOSE_PARENS> p<80> l<10:21> el<10:22>
+n<> u<80> t<Named_port_connection> p<97> c<73> s<88> l<10:9> el<10:22>
+n<in_data> u<81> t<StringConst> p<88> s<86> l<11:10> el<11:17>
+n<in_data> u<82> t<StringConst> p<83> l<11:18> el<11:25>
+n<> u<83> t<Primary_literal> p<84> c<82> l<11:18> el<11:25>
+n<> u<84> t<Primary> p<85> c<83> l<11:18> el<11:25>
+n<> u<85> t<Expression> p<88> c<84> s<87> l<11:18> el<11:25>
+n<> u<86> t<OPEN_PARENS> p<88> s<85> l<11:17> el<11:18>
+n<> u<87> t<CLOSE_PARENS> p<88> l<11:25> el<11:26>
+n<> u<88> t<Named_port_connection> p<97> c<81> s<96> l<11:9> el<11:26>
+n<out_data> u<89> t<StringConst> p<96> s<94> l<12:10> el<12:18>
+n<out_data> u<90> t<StringConst> p<91> l<12:19> el<12:27>
+n<> u<91> t<Primary_literal> p<92> c<90> l<12:19> el<12:27>
+n<> u<92> t<Primary> p<93> c<91> l<12:19> el<12:27>
+n<> u<93> t<Expression> p<96> c<92> s<95> l<12:19> el<12:27>
+n<> u<94> t<OPEN_PARENS> p<96> s<93> l<12:18> el<12:19>
+n<> u<95> t<CLOSE_PARENS> p<96> l<12:27> el<12:28>
+n<> u<96> t<Named_port_connection> p<97> c<89> l<12:9> el<12:28>
+n<> u<97> t<List_of_port_connections> p<98> c<72> l<9:9> el<12:28>
+n<> u<98> t<Hierarchical_instance> p<99> c<64> l<8:19> el<13:6>
+n<> u<99> t<Module_instantiation> p<100> c<62> l<8:5> el<13:7>
+n<> u<100> t<Module_or_generate_item> p<101> c<99> l<8:5> el<13:7>
+n<> u<101> t<Non_port_module_item> p<348> c<100> s<134> l<8:5> el<13:7>
+n<> u<102> t<ALWAYS> p<131> s<130> l<16:5> el<16:11>
+n<#5> u<103> t<IntConst> p<104> l<17:9> el<17:11>
+n<> u<104> t<Delay_control> p<105> c<103> l<17:9> el<17:11>
+n<> u<105> t<Procedural_timing_control> p<123> c<104> s<122> l<17:9> el<17:11>
+n<clk> u<106> t<StringConst> p<107> l<17:12> el<17:15>
+n<> u<107> t<Ps_or_hierarchical_identifier> p<110> c<106> s<109> l<17:12> el<17:15>
+n<> u<108> t<Bit_select> p<109> l<17:16> el<17:16>
+n<> u<109> t<Select> p<110> c<108> l<17:16> el<17:16>
+n<> u<110> t<Variable_lvalue> p<118> c<107> s<111> l<17:12> el<17:15>
+n<> u<111> t<AssignOp_Assign> p<118> s<117> l<17:16> el<17:17>
+n<clk> u<112> t<StringConst> p<113> l<17:19> el<17:22>
+n<> u<113> t<Primary_literal> p<114> c<112> l<17:19> el<17:22>
+n<> u<114> t<Primary> p<115> c<113> l<17:19> el<17:22>
+n<> u<115> t<Expression> p<117> c<114> l<17:19> el<17:22>
+n<> u<116> t<Unary_Tilda> p<117> s<115> l<17:18> el<17:19>
+n<> u<117> t<Expression> p<118> c<116> l<17:18> el<17:22>
+n<> u<118> t<Operator_assignment> p<119> c<110> l<17:12> el<17:22>
+n<> u<119> t<Blocking_assignment> p<120> c<118> l<17:12> el<17:22>
+n<> u<120> t<Statement_item> p<121> c<119> l<17:12> el<17:23>
+n<> u<121> t<Statement> p<122> c<120> l<17:12> el<17:23>
+n<> u<122> t<Statement_or_null> p<123> c<121> l<17:12> el<17:23>
+n<> u<123> t<Procedural_timing_control_statement> p<124> c<105> l<17:9> el<17:23>
+n<> u<124> t<Statement_item> p<125> c<123> l<17:9> el<17:23>
+n<> u<125> t<Statement> p<126> c<124> l<17:9> el<17:23>
+n<> u<126> t<Statement_or_null> p<128> c<125> s<127> l<17:9> el<17:23>
+n<> u<127> t<END> p<128> l<18:5> el<18:8>
+n<> u<128> t<Seq_block> p<129> c<126> l<16:12> el<18:8>
+n<> u<129> t<Statement_item> p<130> c<128> l<16:12> el<18:8>
+n<> u<130> t<Statement> p<131> c<129> l<16:12> el<18:8>
+n<> u<131> t<Always_construct> p<132> c<102> l<16:5> el<18:8>
+n<> u<132> t<Module_common_item> p<133> c<131> l<16:5> el<18:8>
+n<> u<133> t<Module_or_generate_item> p<134> c<132> l<16:5> el<18:8>
+n<> u<134> t<Non_port_module_item> p<348> c<133> s<346> l<16:5> el<18:8>
+n<clk> u<135> t<StringConst> p<136> l<23:9> el<23:12>
+n<> u<136> t<Ps_or_hierarchical_identifier> p<139> c<135> s<138> l<23:9> el<23:12>
+n<> u<137> t<Bit_select> p<138> l<23:13> el<23:13>
+n<> u<138> t<Select> p<139> c<137> l<23:13> el<23:13>
+n<> u<139> t<Variable_lvalue> p<145> c<136> s<140> l<23:9> el<23:12>
+n<> u<140> t<AssignOp_Assign> p<145> s<144> l<23:13> el<23:14>
+n<0> u<141> t<IntConst> p<142> l<23:15> el<23:16>
+n<> u<142> t<Primary_literal> p<143> c<141> l<23:15> el<23:16>
+n<> u<143> t<Primary> p<144> c<142> l<23:15> el<23:16>
+n<> u<144> t<Expression> p<145> c<143> l<23:15> el<23:16>
+n<> u<145> t<Operator_assignment> p<146> c<139> l<23:9> el<23:16>
+n<> u<146> t<Blocking_assignment> p<147> c<145> l<23:9> el<23:16>
+n<> u<147> t<Statement_item> p<148> c<146> l<23:9> el<23:17>
+n<> u<148> t<Statement> p<149> c<147> l<23:9> el<23:17>
+n<> u<149> t<Statement_or_null> p<339> c<148> s<164> l<23:9> el<23:17>
+n<reset> u<150> t<StringConst> p<151> l<24:9> el<24:14>
+n<> u<151> t<Ps_or_hierarchical_identifier> p<154> c<150> s<153> l<24:9> el<24:14>
+n<> u<152> t<Bit_select> p<153> l<24:15> el<24:15>
+n<> u<153> t<Select> p<154> c<152> l<24:15> el<24:15>
+n<> u<154> t<Variable_lvalue> p<160> c<151> s<155> l<24:9> el<24:14>
+n<> u<155> t<AssignOp_Assign> p<160> s<159> l<24:15> el<24:16>
+n<1> u<156> t<IntConst> p<157> l<24:17> el<24:18>
+n<> u<157> t<Primary_literal> p<158> c<156> l<24:17> el<24:18>
+n<> u<158> t<Primary> p<159> c<157> l<24:17> el<24:18>
+n<> u<159> t<Expression> p<160> c<158> l<24:17> el<24:18>
+n<> u<160> t<Operator_assignment> p<161> c<154> l<24:9> el<24:18>
+n<> u<161> t<Blocking_assignment> p<162> c<160> l<24:9> el<24:18>
+n<> u<162> t<Statement_item> p<163> c<161> l<24:9> el<24:19>
+n<> u<163> t<Statement> p<164> c<162> l<24:9> el<24:19>
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+n<> u<166> t<Ps_or_hierarchical_identifier> p<169> c<165> s<168> l<25:9> el<25:16>
+n<> u<167> t<Bit_select> p<168> l<25:17> el<25:17>
+n<> u<168> t<Select> p<169> c<167> l<25:17> el<25:17>
+n<> u<169> t<Variable_lvalue> p<175> c<166> s<170> l<25:9> el<25:16>
+n<> u<170> t<AssignOp_Assign> p<175> s<174> l<25:17> el<25:18>
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+n<> u<172> t<Primary_literal> p<173> c<171> l<25:19> el<25:23>
+n<> u<173> t<Primary> p<174> c<172> l<25:19> el<25:23>
+n<> u<174> t<Expression> p<175> c<173> l<25:19> el<25:23>
+n<> u<175> t<Operator_assignment> p<176> c<169> l<25:9> el<25:23>
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+n<> u<177> t<Statement_item> p<178> c<176> l<25:9> el<25:24>
+n<> u<178> t<Statement> p<179> c<177> l<25:9> el<25:24>
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+n<> u<181> t<Delay_control> p<182> c<180> l<26:9> el<26:12>
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+n<> u<184> t<Ps_or_hierarchical_identifier> p<187> c<183> s<186> l<26:13> el<26:18>
+n<> u<185> t<Bit_select> p<186> l<26:19> el<26:19>
+n<> u<186> t<Select> p<187> c<185> l<26:19> el<26:19>
+n<> u<187> t<Variable_lvalue> p<193> c<184> s<188> l<26:13> el<26:18>
+n<> u<188> t<AssignOp_Assign> p<193> s<192> l<26:19> el<26:20>
+n<0> u<189> t<IntConst> p<190> l<26:21> el<26:22>
+n<> u<190> t<Primary_literal> p<191> c<189> l<26:21> el<26:22>
+n<> u<191> t<Primary> p<192> c<190> l<26:21> el<26:22>
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+n<> u<193> t<Operator_assignment> p<194> c<187> l<26:13> el<26:22>
+n<> u<194> t<Blocking_assignment> p<195> c<193> l<26:13> el<26:22>
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+n<> u<214> t<Primary> p<215> c<213> l<30:19> el<30:38>
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+n<> u<222> t<Dollar_keyword> p<234> s<223> l<31:9> el<31:10>
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+n<> u<230> t<Primary> p<231> c<229> l<31:22> el<31:38>
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+n<> u<251> t<Bit_select> p<252> l<35:31> el<35:31>
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+n<> u<253> t<Complex_func_call> p<254> c<249> l<35:23> el<35:30>
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+n<> u<311> t<Ps_or_hierarchical_identifier> p<314> c<310> s<313> l<41:13> el<41:18>
+n<> u<312> t<Bit_select> p<313> l<41:19> el<41:19>
+n<> u<313> t<Select> p<314> c<312> l<41:19> el<41:19>
+n<> u<314> t<Variable_lvalue> p<320> c<311> s<315> l<41:13> el<41:18>
+n<> u<315> t<AssignOp_Assign> p<320> s<319> l<41:19> el<41:20>
+n<0> u<316> t<IntConst> p<317> l<41:21> el<41:22>
+n<> u<317> t<Primary_literal> p<318> c<316> l<41:21> el<41:22>
+n<> u<318> t<Primary> p<319> c<317> l<41:21> el<41:22>
+n<> u<319> t<Expression> p<320> c<318> l<41:21> el<41:22>
+n<> u<320> t<Operator_assignment> p<321> c<314> l<41:13> el<41:22>
+n<> u<321> t<Blocking_assignment> p<322> c<320> l<41:13> el<41:22>
+n<> u<322> t<Statement_item> p<323> c<321> l<41:13> el<41:23>
+n<> u<323> t<Statement> p<324> c<322> l<41:13> el<41:23>
+n<> u<324> t<Statement_or_null> p<325> c<323> l<41:13> el<41:23>
+n<> u<325> t<Procedural_timing_control_statement> p<326> c<309> l<41:9> el<41:23>
+n<> u<326> t<Statement_item> p<327> c<325> l<41:9> el<41:23>
+n<> u<327> t<Statement> p<328> c<326> l<41:9> el<41:23>
+n<> u<328> t<Statement_or_null> p<339> c<327> s<337> l<41:9> el<41:23>
+n<> u<329> t<Dollar_keyword> p<333> s<330> l<44:9> el<44:10>
+n<finish> u<330> t<StringConst> p<333> s<332> l<44:10> el<44:16>
+n<> u<331> t<Bit_select> p<332> l<44:16> el<44:16>
+n<> u<332> t<Select> p<333> c<331> l<44:16> el<44:16>
+n<> u<333> t<Subroutine_call> p<334> c<329> l<44:9> el<44:16>
+n<> u<334> t<Subroutine_call_statement> p<335> c<333> l<44:9> el<44:17>
+n<> u<335> t<Statement_item> p<336> c<334> l<44:9> el<44:17>
+n<> u<336> t<Statement> p<337> c<335> l<44:9> el<44:17>
+n<> u<337> t<Statement_or_null> p<339> c<336> s<338> l<44:9> el<44:17>
+n<> u<338> t<END> p<339> l<45:5> el<45:8>
+n<> u<339> t<Seq_block> p<340> c<149> l<21:13> el<45:8>
+n<> u<340> t<Statement_item> p<341> c<339> l<21:13> el<45:8>
+n<> u<341> t<Statement> p<342> c<340> l<21:13> el<45:8>
+n<> u<342> t<Statement_or_null> p<343> c<341> l<21:13> el<45:8>
+n<> u<343> t<Initial_construct> p<344> c<342> l<21:5> el<45:8>
+n<> u<344> t<Module_common_item> p<345> c<343> l<21:5> el<45:8>
+n<> u<345> t<Module_or_generate_item> p<346> c<344> l<21:5> el<45:8>
+n<> u<346> t<Non_port_module_item> p<348> c<345> s<347> l<21:5> el<45:8>
+n<> u<347> t<ENDMODULE> p<348> l<46:1> el<46:10>
+n<> u<348> t<Module_declaration> p<349> c<4> l<2:1> el<46:10>
+n<> u<349> t<Description> p<350> c<348> l<2:1> el<46:10>
+n<> u<350> t<Source_text> p<351> c<349> l<2:1> el<46:10>
+n<> u<351> t<Top_level_rule> c<1> l<2:1> el<48:1>
+AST_DEBUG_END
+[WRN:PA0205] ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:1:1: No timescale set for "left_rotate_assertions".
+[WRN:PA0205] ${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv:1:1: No timescale set for "left_rotation".
+[WRN:PA0205] ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:2:1: No timescale set for "tb_left_rotation".
+[INF:CP0300] Compilation...
+[INF:CP0303] ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:1:1: Compile module "work@left_rotate_assertions".
+[INF:CP0303] ${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv:1:1: Compile module "work@left_rotation".
+[INF:CP0303] ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:2:1: Compile module "work@tb_left_rotation".
+[INF:EL0526] Design Elaboration...
+[NTE:EL0503] ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:2:1: Top level module "work@tb_left_rotation".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 2.
+[NTE:EL0510] Nb instances: 4.
+[NTE:EL0511] Nb leaf instances: 0.
+[INF:UH0706] Creating UHDM Model...
+=== UHDM Object Stats Begin (Non-Elaborated Model) ===
+always                                                 2
+assert_stmt                                            3
+assignment                                            11
+begin                                                  9
+bit_select                                             1
+constant                                              89
+delay_control                                          6
+design                                                 1
+event_control                                          2
+if_else                                                1
+if_stmt                                                1
+immediate_assert                                       1
+initial                                                3
+logic_net                                             32
+logic_typespec                                        44
+module_inst                                           11
+operation                                             29
+part_select                                            1
+port                                                  27
+property_decl                                          3
+property_spec                                          6
+range                                                 35
+ref_module                                             1
+ref_obj                                               76
+ref_typespec                                          45
+repeat                                                 1
+sys_func_call                                          4
+=== UHDM Object Stats End ===
+[INF:UH0707] Elaborating UHDM...
+=== UHDM Object Stats Begin (Elaborated Model) ===
+always                                                 5
+assert_stmt                                            9
+assignment                                            30
+begin                                                 23
+bit_select                                             2
+constant                                              89
+delay_control                                         18
+design                                                 1
+event_control                                          5
+if_else                                                2
+if_stmt                                                3
+immediate_assert                                       3
+initial                                                8
+logic_net                                             32
+logic_typespec                                        44
+module_inst                                           11
+operation                                             81
+part_select                                            2
+port                                                  41
+property_decl                                          9
+property_spec                                         18
+range                                                 35
+ref_module                                             1
+ref_obj                                              170
+ref_typespec                                          59
+repeat                                                 3
+sys_func_call                                         12
+=== UHDM Object Stats End ===
+[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/AssertDelayError/slpp_all/surelog.uhdm ...
+[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/AssertDelayError/slpp_all/checker/surelog.chk.html ...
+[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/AssertDelayError/slpp_all/surelog.uhdm ...
+[INF:UH0711] Decompiling UHDM...
+====== UHDM =======
+design: (work@tb_left_rotation)
+|vpiElaborated:1
+|vpiName:work@tb_left_rotation
+|uhdmallModules:
+\_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+  |vpiParent:
+  \_design: (work@tb_left_rotation)
+  |vpiFullName:work@left_rotate_assertions
+  |vpiPropertyDecl:
+  \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+    |vpiName:p_valid_rotation
+    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation
+    |vpiPropertySpec:
+    \_property_spec: , line:19:5, endln:19:98
+      |vpiParent:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+      |vpiClockingEvent:
+      \_operation: , line:19:7, endln:19:18
+        |vpiParent:
+        \_property_spec: , line:19:5, endln:19:98
+        |vpiOpType:39
+        |vpiOperand:
+        \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk), line:19:15, endln:19:18
+          |vpiParent:
+          \_operation: , line:19:7, endln:19:18
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+      |vpiPropertyExpr:
+      \_operation: , line:19:20, endln:19:98
+        |vpiParent:
+        \_property_spec: , line:19:5, endln:19:98
+        |vpiOpType:52
+        |vpiOperand:
+        \_operation: , line:19:21, endln:19:27
+          |vpiParent:
+          \_operation: , line:19:20, endln:19:98
+          |vpiOpType:3
+          |vpiOperand:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n), line:19:22, endln:19:27
+            |vpiParent:
+            \_operation: , line:19:21, endln:19:27
+            |vpiName:rst_n
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+        |vpiOperand:
+        \_operation: , line:19:34, endln:19:97
+          |vpiParent:
+          \_operation: , line:19:20, endln:19:98
+          |vpiOpType:29
+          |vpiOperand:
+          \_operation: , line:19:34, endln:19:67
+            |vpiParent:
+            \_operation: , line:19:34, endln:19:97
+            |vpiOpType:14
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated), line:19:34, endln:19:41
+              |vpiParent:
+              \_operation: , line:19:34, endln:19:67
+              |vpiName:rotated
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+            |vpiOperand:
+            \_operation: , line:19:46, endln:19:66
+              |vpiParent:
+              \_operation: , line:19:34, endln:19:67
+              |vpiOpType:22
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:46, endln:19:53
+                |vpiParent:
+                \_operation: , line:19:46, endln:19:66
+                |vpiName:word_in
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:57, endln:19:66
+                |vpiParent:
+                \_operation: , line:19:46, endln:19:66
+                |vpiName:rotate_by
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+          |vpiOperand:
+          \_operation: , line:19:71, endln:19:96
+            |vpiParent:
+            \_operation: , line:19:34, endln:19:97
+            |vpiOpType:23
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:71, endln:19:78
+              |vpiParent:
+              \_operation: , line:19:71, endln:19:96
+              |vpiName:word_in
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+            |vpiOperand:
+            \_operation: , line:19:83, endln:19:95
+              |vpiParent:
+              \_operation: , line:19:71, endln:19:96
+              |vpiOpType:11
+              |vpiOperand:
+              \_constant: , line:19:83, endln:19:85
+                |vpiParent:
+                \_operation: , line:19:83, endln:19:95
+                |vpiDecompile:32
+                |vpiSize:64
+                |UINT:32
+                |vpiConstType:9
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:86, endln:19:95
+                |vpiParent:
+                \_operation: , line:19:83, endln:19:95
+                |vpiName:rotate_by
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+  |vpiPropertyDecl:
+  \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+    |vpiName:p_rotation_range
+    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range
+    |vpiPropertySpec:
+    \_property_spec: , line:25:5, endln:25:53
+      |vpiParent:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+      |vpiClockingEvent:
+      \_operation: , line:25:7, endln:25:18
+        |vpiParent:
+        \_property_spec: , line:25:5, endln:25:53
+        |vpiOpType:39
+        |vpiOperand:
+        \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk), line:25:15, endln:25:18
+          |vpiParent:
+          \_operation: , line:25:7, endln:25:18
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+      |vpiPropertyExpr:
+      \_operation: , line:25:20, endln:25:53
+        |vpiParent:
+        \_property_spec: , line:25:5, endln:25:53
+        |vpiOpType:52
+        |vpiOperand:
+        \_operation: , line:25:21, endln:25:27
+          |vpiParent:
+          \_operation: , line:25:20, endln:25:53
+          |vpiOpType:3
+          |vpiOperand:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n), line:25:22, endln:25:27
+            |vpiParent:
+            \_operation: , line:25:21, endln:25:27
+            |vpiName:rst_n
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+        |vpiOperand:
+        \_operation: , line:25:34, endln:25:52
+          |vpiParent:
+          \_operation: , line:25:20, endln:25:53
+          |vpiOpType:21
+          |vpiOperand:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by), line:25:34, endln:25:43
+            |vpiParent:
+            \_operation: , line:25:34, endln:25:52
+            |vpiName:rotate_by
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+          |vpiOperand:
+          \_constant: , line:25:47, endln:25:52
+            |vpiParent:
+            \_operation: , line:25:34, endln:25:52
+            |vpiDecompile:5'd31
+            |vpiSize:5
+            |DEC:31
+            |vpiConstType:1
+  |vpiPropertyDecl:
+  \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+    |vpiName:p_no_rotation
+    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation
+    |vpiPropertySpec:
+    \_property_spec: , line:31:5, endln:31:71
+      |vpiParent:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+      |vpiClockingEvent:
+      \_operation: , line:31:7, endln:31:18
+        |vpiParent:
+        \_property_spec: , line:31:5, endln:31:71
+        |vpiOpType:39
+        |vpiOperand:
+        \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk), line:31:15, endln:31:18
+          |vpiParent:
+          \_operation: , line:31:7, endln:31:18
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+      |vpiPropertyExpr:
+      \_operation: , line:31:20, endln:31:71
+        |vpiParent:
+        \_property_spec: , line:31:5, endln:31:71
+        |vpiOpType:52
+        |vpiOperand:
+        \_operation: , line:31:21, endln:31:45
+          |vpiParent:
+          \_operation: , line:31:20, endln:31:71
+          |vpiOpType:26
+          |vpiOperand:
+          \_operation: , line:31:21, endln:31:27
+            |vpiParent:
+            \_operation: , line:31:21, endln:31:45
+            |vpiOpType:3
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n), line:31:22, endln:31:27
+              |vpiParent:
+              \_operation: , line:31:21, endln:31:27
+              |vpiName:rst_n
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+          |vpiOperand:
+          \_operation: , line:31:31, endln:31:45
+            |vpiParent:
+            \_operation: , line:31:21, endln:31:45
+            |vpiOpType:14
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by), line:31:31, endln:31:40
+              |vpiParent:
+              \_operation: , line:31:31, endln:31:45
+              |vpiName:rotate_by
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+            |vpiOperand:
+            \_constant: , line:31:44, endln:31:45
+              |vpiParent:
+              \_operation: , line:31:31, endln:31:45
+              |vpiDecompile:0
+              |vpiSize:64
+              |UINT:0
+              |vpiConstType:9
+        |vpiOperand:
+        \_operation: , line:31:52, endln:31:70
+          |vpiParent:
+          \_operation: , line:31:20, endln:31:71
+          |vpiOpType:14
+          |vpiOperand:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated), line:31:52, endln:31:59
+            |vpiParent:
+            \_operation: , line:31:52, endln:31:70
+            |vpiName:rotated
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+          |vpiOperand:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in), line:31:63, endln:31:70
+            |vpiParent:
+            \_operation: , line:31:52, endln:31:70
+            |vpiName:word_in
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+  |vpiDefName:work@left_rotate_assertions
+  |vpiNet:
+  \_logic_net: (work@left_rotate_assertions.clk), line:2:11, endln:2:14
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:clk
+    |vpiFullName:work@left_rotate_assertions.clk
+  |vpiNet:
+  \_logic_net: (work@left_rotate_assertions.rst_n), line:3:11, endln:3:16
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:rst_n
+    |vpiFullName:work@left_rotate_assertions.rst_n
+  |vpiNet:
+  \_logic_net: (work@left_rotate_assertions.word_in), line:4:18, endln:4:25
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:word_in
+    |vpiFullName:work@left_rotate_assertions.word_in
+  |vpiNet:
+  \_logic_net: (work@left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:rotate_by
+    |vpiFullName:work@left_rotate_assertions.rotate_by
+  |vpiNet:
+  \_logic_net: (work@left_rotate_assertions.rotated), line:6:18, endln:6:25
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:rotated
+    |vpiFullName:work@left_rotate_assertions.rotated
+  |vpiAssertion:
+  \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+    |vpiName:a_valid_rotation
+    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation
+    |vpiProperty:
+    \_property_spec: , line:21:37, endln:21:53
+      |vpiParent:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55
+      |vpiPropertyExpr:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation), line:21:37, endln:21:53
+        |vpiParent:
+        \_property_spec: , line:21:37, endln:21:53
+        |vpiName:p_valid_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation
+        |vpiActual:
+        \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+  |vpiAssertion:
+  \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+    |vpiName:a_rotation_range
+    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range
+    |vpiProperty:
+    \_property_spec: , line:27:37, endln:27:53
+      |vpiParent:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55
+      |vpiPropertyExpr:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range), line:27:37, endln:27:53
+        |vpiParent:
+        \_property_spec: , line:27:37, endln:27:53
+        |vpiName:p_rotation_range
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range
+        |vpiActual:
+        \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+  |vpiAssertion:
+  \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+    |vpiName:a_no_rotation
+    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation
+    |vpiProperty:
+    \_property_spec: , line:33:34, endln:33:47
+      |vpiParent:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49
+      |vpiPropertyExpr:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation), line:33:34, endln:33:47
+        |vpiParent:
+        \_property_spec: , line:33:34, endln:33:47
+        |vpiName:p_no_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation
+        |vpiActual:
+        \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+  |vpiPort:
+  \_port: (clk), line:2:11, endln:2:14
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:clk
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotate_assertions.clk.clk), line:2:11, endln:2:14
+      |vpiParent:
+      \_port: (clk), line:2:11, endln:2:14
+      |vpiName:clk
+      |vpiFullName:work@left_rotate_assertions.clk.clk
+      |vpiActual:
+      \_logic_net: (work@left_rotate_assertions.clk), line:2:11, endln:2:14
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotate_assertions.clk)
+      |vpiParent:
+      \_port: (clk), line:2:11, endln:2:14
+      |vpiFullName:work@left_rotate_assertions.clk
+      |vpiActual:
+      \_logic_typespec: , line:2:11, endln:2:11
+  |vpiPort:
+  \_port: (rst_n), line:3:11, endln:3:16
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:rst_n
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotate_assertions.rst_n.rst_n), line:3:11, endln:3:16
+      |vpiParent:
+      \_port: (rst_n), line:3:11, endln:3:16
+      |vpiName:rst_n
+      |vpiFullName:work@left_rotate_assertions.rst_n.rst_n
+      |vpiActual:
+      \_logic_net: (work@left_rotate_assertions.rst_n), line:3:11, endln:3:16
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotate_assertions.rst_n)
+      |vpiParent:
+      \_port: (rst_n), line:3:11, endln:3:16
+      |vpiFullName:work@left_rotate_assertions.rst_n
+      |vpiActual:
+      \_logic_typespec: , line:3:11, endln:3:11
+  |vpiPort:
+  \_port: (word_in), line:4:18, endln:4:25
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:word_in
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotate_assertions.word_in.word_in), line:4:18, endln:4:25
+      |vpiParent:
+      \_port: (word_in), line:4:18, endln:4:25
+      |vpiName:word_in
+      |vpiFullName:work@left_rotate_assertions.word_in.word_in
+      |vpiActual:
+      \_logic_net: (work@left_rotate_assertions.word_in), line:4:18, endln:4:25
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotate_assertions.word_in)
+      |vpiParent:
+      \_port: (word_in), line:4:18, endln:4:25
+      |vpiFullName:work@left_rotate_assertions.word_in
+      |vpiActual:
+      \_logic_typespec: , line:4:11, endln:4:17
+  |vpiPort:
+  \_port: (rotate_by), line:5:17, endln:5:26
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:rotate_by
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotate_assertions.rotate_by.rotate_by), line:5:17, endln:5:26
+      |vpiParent:
+      \_port: (rotate_by), line:5:17, endln:5:26
+      |vpiName:rotate_by
+      |vpiFullName:work@left_rotate_assertions.rotate_by.rotate_by
+      |vpiActual:
+      \_logic_net: (work@left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotate_assertions.rotate_by)
+      |vpiParent:
+      \_port: (rotate_by), line:5:17, endln:5:26
+      |vpiFullName:work@left_rotate_assertions.rotate_by
+      |vpiActual:
+      \_logic_typespec: , line:5:11, endln:5:16
+  |vpiPort:
+  \_port: (rotated), line:6:18, endln:6:25
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiName:rotated
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotate_assertions.rotated.rotated), line:6:18, endln:6:25
+      |vpiParent:
+      \_port: (rotated), line:6:18, endln:6:25
+      |vpiName:rotated
+      |vpiFullName:work@left_rotate_assertions.rotated.rotated
+      |vpiActual:
+      \_logic_net: (work@left_rotate_assertions.rotated), line:6:18, endln:6:25
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotate_assertions.rotated)
+      |vpiParent:
+      \_port: (rotated), line:6:18, endln:6:25
+      |vpiFullName:work@left_rotate_assertions.rotated
+      |vpiActual:
+      \_logic_typespec: , line:6:11, endln:6:17
+  |vpiProcess:
+  \_initial: , line:10:3, endln:15:6
+    |vpiParent:
+    \_module_inst: work@left_rotate_assertions (work@left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:1:1, endln:35:10
+    |vpiStmt:
+    \_begin: (work@left_rotate_assertions), line:10:11, endln:15:6
+      |vpiParent:
+      \_initial: , line:10:3, endln:15:6
+      |vpiFullName:work@left_rotate_assertions
+      |vpiStmt:
+      \_event_control: , line:11:5, endln:11:19
+        |vpiParent:
+        \_begin: (work@left_rotate_assertions), line:10:11, endln:15:6
+        |vpiCondition:
+        \_operation: , line:11:7, endln:11:18
+          |vpiParent:
+          \_event_control: , line:11:5, endln:11:19
+          |vpiOpType:39
+          |vpiOperand:
+          \_ref_obj: (work@left_rotate_assertions.clk), line:11:15, endln:11:18
+            |vpiParent:
+            \_operation: , line:11:7, endln:11:18
+            |vpiName:clk
+            |vpiFullName:work@left_rotate_assertions.clk
+            |vpiActual:
+            \_logic_net: (work@left_rotate_assertions.clk), line:2:11, endln:2:14
+      |vpiStmt:
+      \_if_stmt: , line:12:5, endln:14:8
+        |vpiParent:
+        \_begin: (work@left_rotate_assertions), line:10:11, endln:15:6
+        |vpiCondition:
+        \_operation: , line:12:9, endln:12:15
+          |vpiParent:
+          \_begin: (work@left_rotate_assertions), line:10:11, endln:15:6
+          |vpiOpType:3
+          |vpiOperand:
+          \_ref_obj: (work@left_rotate_assertions.rst_n), line:12:10, endln:12:15
+            |vpiParent:
+            \_operation: , line:12:9, endln:12:15
+            |vpiName:rst_n
+            |vpiFullName:work@left_rotate_assertions.rst_n
+            |vpiActual:
+            \_logic_net: (work@left_rotate_assertions.rst_n), line:3:11, endln:3:16
+        |vpiStmt:
+        \_begin: (work@left_rotate_assertions), line:12:17, endln:14:8
+          |vpiParent:
+          \_if_stmt: , line:12:5, endln:14:8
+          |vpiFullName:work@left_rotate_assertions
+          |vpiStmt:
+          \_immediate_assert: , line:13:7, endln:13:28
+            |vpiParent:
+            \_begin: (work@left_rotate_assertions), line:12:17, endln:14:8
+            |vpiExpr:
+            \_operation: , line:13:14, endln:13:26
+              |vpiParent:
+              \_immediate_assert: , line:13:7, endln:13:28
+              |vpiOpType:14
+              |vpiOperand:
+              \_ref_obj: (work@left_rotate_assertions.rotated), line:13:14, endln:13:21
+                |vpiParent:
+                \_operation: , line:13:14, endln:13:26
+                |vpiName:rotated
+                |vpiFullName:work@left_rotate_assertions.rotated
+                |vpiActual:
+                \_logic_net: (work@left_rotate_assertions.rotated), line:6:18, endln:6:25
+              |vpiOperand:
+              \_constant: , line:13:25, endln:13:26
+                |vpiParent:
+                \_operation: , line:13:14, endln:13:26
+                |vpiDecompile:0
+                |vpiSize:64
+                |UINT:0
+                |vpiConstType:9
+|uhdmallModules:
+\_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+  |vpiParent:
+  \_design: (work@tb_left_rotation)
+  |vpiFullName:work@left_rotation
+  |vpiDefName:work@left_rotation
+  |vpiNet:
+  \_logic_net: (work@left_rotation.clk), line:2:16, endln:2:19
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:clk
+    |vpiFullName:work@left_rotation.clk
+    |vpiNetType:1
+  |vpiNet:
+  \_logic_net: (work@left_rotation.reset), line:3:16, endln:3:21
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:reset
+    |vpiFullName:work@left_rotation.reset
+    |vpiNetType:1
+  |vpiNet:
+  \_logic_net: (work@left_rotation.in_data), line:4:22, endln:4:29
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:in_data
+    |vpiFullName:work@left_rotation.in_data
+    |vpiNetType:1
+  |vpiNet:
+  \_logic_net: (work@left_rotation.out_data), line:5:22, endln:5:30
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:out_data
+    |vpiFullName:work@left_rotation.out_data
+    |vpiNetType:48
+  |vpiPort:
+  \_port: (clk), line:2:16, endln:2:19
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:clk
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotation.clk.clk), line:2:16, endln:2:19
+      |vpiParent:
+      \_port: (clk), line:2:16, endln:2:19
+      |vpiName:clk
+      |vpiFullName:work@left_rotation.clk.clk
+      |vpiActual:
+      \_logic_net: (work@left_rotation.clk), line:2:16, endln:2:19
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotation.clk)
+      |vpiParent:
+      \_port: (clk), line:2:16, endln:2:19
+      |vpiFullName:work@left_rotation.clk
+      |vpiActual:
+      \_logic_typespec: , line:2:11, endln:2:15
+  |vpiPort:
+  \_port: (reset), line:3:16, endln:3:21
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:reset
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotation.reset.reset), line:3:16, endln:3:21
+      |vpiParent:
+      \_port: (reset), line:3:16, endln:3:21
+      |vpiName:reset
+      |vpiFullName:work@left_rotation.reset.reset
+      |vpiActual:
+      \_logic_net: (work@left_rotation.reset), line:3:16, endln:3:21
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotation.reset)
+      |vpiParent:
+      \_port: (reset), line:3:16, endln:3:21
+      |vpiFullName:work@left_rotation.reset
+      |vpiActual:
+      \_logic_typespec: , line:3:11, endln:3:15
+  |vpiPort:
+  \_port: (in_data), line:4:22, endln:4:29
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:in_data
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotation.in_data.in_data), line:4:22, endln:4:29
+      |vpiParent:
+      \_port: (in_data), line:4:22, endln:4:29
+      |vpiName:in_data
+      |vpiFullName:work@left_rotation.in_data.in_data
+      |vpiActual:
+      \_logic_net: (work@left_rotation.in_data), line:4:22, endln:4:29
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotation.in_data)
+      |vpiParent:
+      \_port: (in_data), line:4:22, endln:4:29
+      |vpiFullName:work@left_rotation.in_data
+      |vpiActual:
+      \_logic_typespec: , line:4:11, endln:4:21
+  |vpiPort:
+  \_port: (out_data), line:5:22, endln:5:30
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiName:out_data
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@left_rotation.out_data.out_data), line:5:22, endln:5:30
+      |vpiParent:
+      \_port: (out_data), line:5:22, endln:5:30
+      |vpiName:out_data
+      |vpiFullName:work@left_rotation.out_data.out_data
+      |vpiActual:
+      \_logic_net: (work@left_rotation.out_data), line:5:22, endln:5:30
+    |vpiTypedef:
+    \_ref_typespec: (work@left_rotation.out_data)
+      |vpiParent:
+      \_port: (out_data), line:5:22, endln:5:30
+      |vpiFullName:work@left_rotation.out_data
+      |vpiActual:
+      \_logic_typespec: , line:5:12, endln:5:21
+  |vpiProcess:
+  \_always: , line:8:1, endln:15:4
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiStmt:
+    \_event_control: , line:8:8, endln:8:39
+      |vpiParent:
+      \_always: , line:8:1, endln:15:4
+      |vpiCondition:
+      \_operation: , line:8:10, endln:8:38
+        |vpiParent:
+        \_event_control: , line:8:8, endln:8:39
+        |vpiOpType:35
+        |vpiOperand:
+        \_operation: , line:8:10, endln:8:21
+          |vpiParent:
+          \_operation: , line:8:10, endln:8:38
+          |vpiOpType:39
+          |vpiOperand:
+          \_ref_obj: (work@left_rotation.clk), line:8:18, endln:8:21
+            |vpiParent:
+            \_operation: , line:8:10, endln:8:21
+            |vpiName:clk
+            |vpiFullName:work@left_rotation.clk
+            |vpiActual:
+            \_logic_net: (work@left_rotation.clk), line:2:16, endln:2:19
+        |vpiOperand:
+        \_operation: , line:8:25, endln:8:38
+          |vpiParent:
+          \_operation: , line:8:10, endln:8:38
+          |vpiOpType:39
+          |vpiOperand:
+          \_ref_obj: (work@left_rotation.reset), line:8:33, endln:8:38
+            |vpiParent:
+            \_operation: , line:8:25, endln:8:38
+            |vpiName:reset
+            |vpiFullName:work@left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@left_rotation.reset), line:3:16, endln:3:21
+      |vpiStmt:
+      \_begin: (work@left_rotation), line:8:40, endln:15:4
+        |vpiParent:
+        \_event_control: , line:8:8, endln:8:39
+        |vpiFullName:work@left_rotation
+        |vpiStmt:
+        \_if_else: , line:9:5, endln:14:8
+          |vpiParent:
+          \_begin: (work@left_rotation), line:8:40, endln:15:4
+          |vpiCondition:
+          \_ref_obj: (work@left_rotation.reset), line:9:9, endln:9:14
+            |vpiParent:
+            \_begin: (work@left_rotation), line:8:40, endln:15:4
+            |vpiName:reset
+            |vpiFullName:work@left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@left_rotation.reset), line:3:16, endln:3:21
+          |vpiStmt:
+          \_begin: (work@left_rotation), line:9:16, endln:11:8
+            |vpiParent:
+            \_if_else: , line:9:5, endln:14:8
+            |vpiFullName:work@left_rotation
+            |vpiStmt:
+            \_assignment: , line:10:9, endln:10:33
+              |vpiParent:
+              \_begin: (work@left_rotation), line:9:16, endln:11:8
+              |vpiOpType:82
+              |vpiRhs:
+              \_constant: , line:10:21, endln:10:33
+                |vpiDecompile:8'b0000_0000
+                |vpiSize:8
+                |BIN:00000000
+                |vpiConstType:3
+              |vpiLhs:
+              \_ref_obj: (work@left_rotation.out_data), line:10:9, endln:10:17
+                |vpiParent:
+                \_assignment: , line:10:9, endln:10:33
+                |vpiName:out_data
+                |vpiFullName:work@left_rotation.out_data
+                |vpiActual:
+                \_logic_net: (work@left_rotation.out_data), line:5:22, endln:5:30
+          |vpiElseStmt:
+          \_begin: (work@left_rotation), line:11:14, endln:14:8
+            |vpiParent:
+            \_if_else: , line:9:5, endln:14:8
+            |vpiFullName:work@left_rotation
+            |vpiStmt:
+            \_assignment: , line:13:9, endln:13:49
+              |vpiParent:
+              \_begin: (work@left_rotation), line:11:14, endln:14:8
+              |vpiOpType:82
+              |vpiRhs:
+              \_operation: , line:13:21, endln:13:49
+                |vpiParent:
+                \_assignment: , line:13:9, endln:13:49
+                |vpiOpType:33
+                |vpiOperand:
+                \_part_select: out_data (work@left_rotation.out_data), line:13:22, endln:13:35
+                  |vpiParent:
+                  \_operation: , line:13:21, endln:13:49
+                  |vpiName:out_data
+                  |vpiFullName:work@left_rotation.out_data
+                  |vpiDefName:out_data
+                  |vpiConstantSelect:1
+                  |vpiLeftRange:
+                  \_constant: , line:13:31, endln:13:32
+                    |vpiDecompile:6
+                    |vpiSize:64
+                    |UINT:6
+                    |vpiConstType:9
+                  |vpiRightRange:
+                  \_constant: , line:13:33, endln:13:34
+                    |vpiDecompile:0
+                    |vpiSize:64
+                    |UINT:0
+                    |vpiConstType:9
+                |vpiOperand:
+                \_bit_select: (work@left_rotation.out_data), line:13:46, endln:13:47
+                  |vpiParent:
+                  \_operation: , line:13:21, endln:13:49
+                  |vpiName:out_data
+                  |vpiFullName:work@left_rotation.out_data
+                  |vpiIndex:
+                  \_constant: , line:13:46, endln:13:47
+                    |vpiParent:
+                    \_bit_select: (work@left_rotation.out_data), line:13:46, endln:13:47
+                    |vpiDecompile:7
+                    |vpiSize:64
+                    |UINT:7
+                    |vpiConstType:9
+              |vpiLhs:
+              \_ref_obj: (work@left_rotation.out_data), line:13:9, endln:13:17
+                |vpiParent:
+                \_assignment: , line:13:9, endln:13:49
+                |vpiName:out_data
+                |vpiFullName:work@left_rotation.out_data
+                |vpiActual:
+                \_logic_net: (work@left_rotation.out_data), line:5:22, endln:5:30
+    |vpiAlwaysType:1
+  |vpiProcess:
+  \_initial: , line:17:1, endln:19:4
+    |vpiParent:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiStmt:
+    \_begin: (work@left_rotation), line:17:9, endln:19:4
+      |vpiParent:
+      \_initial: , line:17:1, endln:19:4
+      |vpiFullName:work@left_rotation
+      |vpiStmt:
+      \_assignment: , line:18:5, endln:18:28
+        |vpiParent:
+        \_begin: (work@left_rotation), line:17:9, endln:19:4
+        |vpiOpType:82
+        |vpiBlocking:1
+        |vpiRhs:
+        \_constant: , line:18:16, endln:18:28
+          |vpiDecompile:8'b0000_0000
+          |vpiSize:8
+          |BIN:00000000
+          |vpiConstType:3
+        |vpiLhs:
+        \_ref_obj: (work@left_rotation.out_data), line:18:5, endln:18:13
+          |vpiParent:
+          \_assignment: , line:18:5, endln:18:28
+          |vpiName:out_data
+          |vpiFullName:work@left_rotation.out_data
+          |vpiActual:
+          \_logic_net: (work@left_rotation.out_data), line:5:22, endln:5:30
+|uhdmallModules:
+\_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+  |vpiParent:
+  \_design: (work@tb_left_rotation)
+  |vpiFullName:work@tb_left_rotation
+  |vpiDefName:work@tb_left_rotation
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.clk)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+      |vpiFullName:work@tb_left_rotation.clk
+      |vpiActual:
+      \_logic_typespec: , line:3:5, endln:3:8
+    |vpiName:clk
+    |vpiFullName:work@tb_left_rotation.clk
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.reset)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiFullName:work@tb_left_rotation.reset
+      |vpiActual:
+      \_logic_typespec: , line:3:5, endln:3:8
+    |vpiName:reset
+    |vpiFullName:work@tb_left_rotation.reset
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.in_data)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+      |vpiFullName:work@tb_left_rotation.in_data
+      |vpiActual:
+      \_logic_typespec: , line:4:5, endln:4:14
+    |vpiName:in_data
+    |vpiFullName:work@tb_left_rotation.in_data
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.out_data), line:5:16, endln:5:24
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.out_data)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.out_data), line:5:16, endln:5:24
+      |vpiFullName:work@tb_left_rotation.out_data
+      |vpiActual:
+      \_logic_typespec: , line:5:5, endln:5:15
+    |vpiName:out_data
+    |vpiFullName:work@tb_left_rotation.out_data
+    |vpiNetType:1
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.tb_left_rotation), line:31:22, endln:31:38
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiName:tb_left_rotation
+    |vpiFullName:work@tb_left_rotation.tb_left_rotation
+    |vpiNetType:1
+  |vpiProcess:
+  \_always: , line:16:5, endln:18:8
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiStmt:
+    \_begin: (work@tb_left_rotation), line:16:12, endln:18:8
+      |vpiParent:
+      \_always: , line:16:5, endln:18:8
+      |vpiFullName:work@tb_left_rotation
+      |vpiStmt:
+      \_delay_control: , line:17:9, endln:17:11
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:16:12, endln:18:8
+        |#5
+        |vpiStmt:
+        \_assignment: , line:17:12, endln:17:22
+          |vpiParent:
+          \_delay_control: , line:17:9, endln:17:11
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_operation: , line:17:18, endln:17:22
+            |vpiParent:
+            \_assignment: , line:17:12, endln:17:22
+            |vpiOpType:4
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.clk), line:17:19, endln:17:22
+              |vpiParent:
+              \_operation: , line:17:18, endln:17:22
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.clk), line:17:12, endln:17:15
+            |vpiParent:
+            \_assignment: , line:17:12, endln:17:22
+            |vpiName:clk
+            |vpiFullName:work@tb_left_rotation.clk
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+    |vpiAlwaysType:1
+  |vpiProcess:
+  \_initial: , line:21:5, endln:45:8
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiStmt:
+    \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+      |vpiParent:
+      \_initial: , line:21:5, endln:45:8
+      |vpiFullName:work@tb_left_rotation
+      |vpiStmt:
+      \_assignment: , line:23:9, endln:23:16
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiOpType:82
+        |vpiBlocking:1
+        |vpiRhs:
+        \_constant: , line:23:15, endln:23:16
+          |vpiDecompile:0
+          |vpiSize:64
+          |UINT:0
+          |vpiConstType:9
+        |vpiLhs:
+        \_ref_obj: (work@tb_left_rotation.clk), line:23:9, endln:23:12
+          |vpiParent:
+          \_assignment: , line:23:9, endln:23:16
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+      |vpiStmt:
+      \_assignment: , line:24:9, endln:24:18
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiOpType:82
+        |vpiBlocking:1
+        |vpiRhs:
+        \_constant: , line:24:17, endln:24:18
+          |vpiDecompile:1
+          |vpiSize:64
+          |UINT:1
+          |vpiConstType:9
+        |vpiLhs:
+        \_ref_obj: (work@tb_left_rotation.reset), line:24:9, endln:24:14
+          |vpiParent:
+          \_assignment: , line:24:9, endln:24:18
+          |vpiName:reset
+          |vpiFullName:work@tb_left_rotation.reset
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_assignment: , line:25:9, endln:25:23
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiOpType:82
+        |vpiBlocking:1
+        |vpiRhs:
+        \_constant: , line:25:19, endln:25:23
+          |vpiDecompile:8'b0
+          |vpiSize:8
+          |BIN:0
+          |vpiConstType:3
+        |vpiLhs:
+        \_ref_obj: (work@tb_left_rotation.in_data), line:25:9, endln:25:16
+          |vpiParent:
+          \_assignment: , line:25:9, endln:25:23
+          |vpiName:in_data
+          |vpiFullName:work@tb_left_rotation.in_data
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+      |vpiStmt:
+      \_delay_control: , line:26:9, endln:26:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+        |vpiStmt:
+        \_assignment: , line:26:13, endln:26:22
+          |vpiParent:
+          \_delay_control: , line:26:9, endln:26:12
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_constant: , line:26:21, endln:26:22
+            |vpiDecompile:0
+            |vpiSize:64
+            |UINT:0
+            |vpiConstType:9
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.reset), line:26:13, endln:26:18
+            |vpiParent:
+            \_assignment: , line:26:13, endln:26:22
+            |vpiName:reset
+            |vpiFullName:work@tb_left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_delay_control: , line:27:9, endln:27:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+      |vpiStmt:
+      \_sys_func_call: ($dumpfile), line:30:9, endln:30:39
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiArgument:
+        \_constant: , line:30:19, endln:30:38
+          |vpiParent:
+          \_sys_func_call: ($dumpfile), line:30:9, endln:30:39
+          |vpiDecompile:"left_rotation.vcd"
+          |vpiSize:136
+          |STRING:left_rotation.vcd
+          |vpiConstType:6
+        |vpiName:$dumpfile
+      |vpiStmt:
+      \_sys_func_call: ($dumpvars), line:31:9, endln:31:39
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiArgument:
+        \_constant: , line:31:19, endln:31:20
+          |vpiParent:
+          \_sys_func_call: ($dumpvars), line:31:9, endln:31:39
+          |vpiDecompile:0
+          |vpiSize:64
+          |UINT:0
+          |vpiConstType:9
+        |vpiArgument:
+        \_ref_obj: (work@tb_left_rotation.tb_left_rotation), line:31:22, endln:31:38
+          |vpiParent:
+          \_sys_func_call: ($dumpvars), line:31:9, endln:31:39
+          |vpiName:tb_left_rotation
+          |vpiFullName:work@tb_left_rotation.tb_left_rotation
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.tb_left_rotation), line:31:22, endln:31:38
+        |vpiName:$dumpvars
+      |vpiStmt:
+      \_repeat: , line:34:9, endln:34:15
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiCondition:
+        \_constant: , line:34:16, endln:34:18
+          |vpiDecompile:20
+          |vpiSize:64
+          |UINT:20
+          |vpiConstType:9
+        |vpiStmt:
+        \_begin: (work@tb_left_rotation), line:34:20, endln:37:12
+          |vpiParent:
+          \_repeat: , line:34:9, endln:34:15
+          |vpiFullName:work@tb_left_rotation
+          |vpiStmt:
+          \_assignment: , line:35:13, endln:35:44
+            |vpiParent:
+            \_begin: (work@tb_left_rotation), line:34:20, endln:37:12
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_operation: , line:35:23, endln:35:44
+              |vpiParent:
+              \_assignment: , line:35:13, endln:35:44
+              |vpiOpType:28
+              |vpiOperand:
+              \_sys_func_call: ($random), line:35:23, endln:35:30
+                |vpiParent:
+                \_operation: , line:35:23, endln:35:44
+                |vpiName:$random
+              |vpiOperand:
+              \_constant: , line:35:33, endln:35:44
+                |vpiParent:
+                \_operation: , line:35:23, endln:35:44
+                |vpiDecompile:8'b11111111
+                |vpiSize:8
+                |BIN:11111111
+                |vpiConstType:3
+            |vpiLhs:
+            \_ref_obj: (work@tb_left_rotation.in_data), line:35:13, endln:35:20
+              |vpiParent:
+              \_assignment: , line:35:13, endln:35:44
+              |vpiName:in_data
+              |vpiFullName:work@tb_left_rotation.in_data
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+          |vpiStmt:
+          \_delay_control: , line:36:13, endln:36:16
+            |vpiParent:
+            \_begin: (work@tb_left_rotation), line:34:20, endln:37:12
+            |#10
+      |vpiStmt:
+      \_delay_control: , line:40:9, endln:40:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+        |vpiStmt:
+        \_assignment: , line:40:13, endln:40:22
+          |vpiParent:
+          \_delay_control: , line:40:9, endln:40:12
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_constant: , line:40:21, endln:40:22
+            |vpiDecompile:1
+            |vpiSize:64
+            |UINT:1
+            |vpiConstType:9
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.reset), line:40:13, endln:40:18
+            |vpiParent:
+            \_assignment: , line:40:13, endln:40:22
+            |vpiName:reset
+            |vpiFullName:work@tb_left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_delay_control: , line:41:9, endln:41:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+        |vpiStmt:
+        \_assignment: , line:41:13, endln:41:22
+          |vpiParent:
+          \_delay_control: , line:41:9, endln:41:12
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_constant: , line:41:21, endln:41:22
+            |vpiDecompile:0
+            |vpiSize:64
+            |UINT:0
+            |vpiConstType:9
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.reset), line:41:13, endln:41:18
+            |vpiParent:
+            \_assignment: , line:41:13, endln:41:22
+            |vpiName:reset
+            |vpiFullName:work@tb_left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_sys_func_call: ($finish), line:44:9, endln:44:16
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiName:$finish
+  |vpiRefModule:
+  \_ref_module: work@left_rotation (left_rotation_inst), line:8:19, endln:8:37
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiName:left_rotation_inst
+    |vpiDefName:work@left_rotation
+    |vpiActual:
+    \_module_inst: work@left_rotation (work@left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv, line:1:1, endln:21:10
+    |vpiPort:
+    \_port: (clk), line:9:9, endln:9:18
+      |vpiParent:
+      \_ref_module: work@left_rotation (left_rotation_inst), line:8:19, endln:8:37
+      |vpiName:clk
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.clk.clk), line:9:14, endln:9:17
+        |vpiParent:
+        \_port: (clk), line:9:9, endln:9:18
+        |vpiName:clk
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.clk.clk
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+    |vpiPort:
+    \_port: (reset), line:10:9, endln:10:22
+      |vpiParent:
+      \_ref_module: work@left_rotation (left_rotation_inst), line:8:19, endln:8:37
+      |vpiName:reset
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.reset.reset), line:10:16, endln:10:21
+        |vpiParent:
+        \_port: (reset), line:10:9, endln:10:22
+        |vpiName:reset
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.reset.reset
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+    |vpiPort:
+    \_port: (in_data), line:11:9, endln:11:26
+      |vpiParent:
+      \_ref_module: work@left_rotation (left_rotation_inst), line:8:19, endln:8:37
+      |vpiName:in_data
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.in_data.in_data), line:11:18, endln:11:25
+        |vpiParent:
+        \_port: (in_data), line:11:9, endln:11:26
+        |vpiName:in_data
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.in_data.in_data
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+    |vpiPort:
+    \_port: (out_data), line:12:9, endln:12:28
+      |vpiParent:
+      \_ref_module: work@left_rotation (left_rotation_inst), line:8:19, endln:8:37
+      |vpiName:out_data
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.out_data.out_data), line:12:19, endln:12:27
+        |vpiParent:
+        \_port: (out_data), line:12:9, endln:12:28
+        |vpiName:out_data
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data.out_data
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.out_data), line:5:16, endln:5:24
+|uhdmtopModules:
+\_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+  |vpiName:work@tb_left_rotation
+  |vpiDefName:work@tb_left_rotation
+  |vpiTop:1
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.clk)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+      |vpiFullName:work@tb_left_rotation.clk
+      |vpiActual:
+      \_logic_typespec: , line:3:5, endln:3:8
+    |vpiName:clk
+    |vpiFullName:work@tb_left_rotation.clk
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.reset)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiFullName:work@tb_left_rotation.reset
+      |vpiActual:
+      \_logic_typespec: , line:3:5, endln:3:8
+    |vpiName:reset
+    |vpiFullName:work@tb_left_rotation.reset
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.in_data)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+      |vpiFullName:work@tb_left_rotation.in_data
+      |vpiActual:
+      \_logic_typespec: , line:4:5, endln:4:14
+    |vpiName:in_data
+    |vpiFullName:work@tb_left_rotation.in_data
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@tb_left_rotation.out_data), line:5:16, endln:5:24
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiTypespec:
+    \_ref_typespec: (work@tb_left_rotation.out_data)
+      |vpiParent:
+      \_logic_net: (work@tb_left_rotation.out_data), line:5:16, endln:5:24
+      |vpiFullName:work@tb_left_rotation.out_data
+      |vpiActual:
+      \_logic_typespec: , line:5:5, endln:5:15
+    |vpiName:out_data
+    |vpiFullName:work@tb_left_rotation.out_data
+    |vpiNetType:1
+  |vpiTopModule:1
+  |vpiProcess:
+  \_always: , line:16:5, endln:18:8
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiStmt:
+    \_begin: (work@tb_left_rotation), line:16:12, endln:18:8
+      |vpiParent:
+      \_always: , line:16:5, endln:18:8
+      |vpiFullName:work@tb_left_rotation
+      |vpiStmt:
+      \_delay_control: , line:17:9, endln:17:11
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:16:12, endln:18:8
+        |#5
+        |vpiStmt:
+        \_assignment: , line:17:12, endln:17:22
+          |vpiParent:
+          \_delay_control: , line:17:9, endln:17:11
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_operation: , line:17:18, endln:17:22
+            |vpiParent:
+            \_assignment: , line:17:12, endln:17:22
+            |vpiOpType:4
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.clk), line:17:19, endln:17:22
+              |vpiParent:
+              \_operation: , line:17:18, endln:17:22
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.clk), line:17:12, endln:17:15
+            |vpiParent:
+            \_assignment: , line:17:12, endln:17:22
+            |vpiName:clk
+            |vpiFullName:work@tb_left_rotation.clk
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+    |vpiAlwaysType:1
+  |vpiProcess:
+  \_initial: , line:21:5, endln:45:8
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiStmt:
+    \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+      |vpiParent:
+      \_initial: , line:21:5, endln:45:8
+      |vpiFullName:work@tb_left_rotation
+      |vpiStmt:
+      \_assignment: , line:23:9, endln:23:16
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiOpType:82
+        |vpiBlocking:1
+        |vpiRhs:
+        \_constant: , line:23:15, endln:23:16
+        |vpiLhs:
+        \_ref_obj: (work@tb_left_rotation.clk), line:23:9, endln:23:12
+          |vpiParent:
+          \_assignment: , line:23:9, endln:23:16
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
+      |vpiStmt:
+      \_assignment: , line:24:9, endln:24:18
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiOpType:82
+        |vpiBlocking:1
+        |vpiRhs:
+        \_constant: , line:24:17, endln:24:18
+        |vpiLhs:
+        \_ref_obj: (work@tb_left_rotation.reset), line:24:9, endln:24:14
+          |vpiParent:
+          \_assignment: , line:24:9, endln:24:18
+          |vpiName:reset
+          |vpiFullName:work@tb_left_rotation.reset
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_assignment: , line:25:9, endln:25:23
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiOpType:82
+        |vpiBlocking:1
+        |vpiRhs:
+        \_constant: , line:25:19, endln:25:23
+        |vpiLhs:
+        \_ref_obj: (work@tb_left_rotation.in_data), line:25:9, endln:25:16
+          |vpiParent:
+          \_assignment: , line:25:9, endln:25:23
+          |vpiName:in_data
+          |vpiFullName:work@tb_left_rotation.in_data
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+      |vpiStmt:
+      \_delay_control: , line:26:9, endln:26:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+        |vpiStmt:
+        \_assignment: , line:26:13, endln:26:22
+          |vpiParent:
+          \_delay_control: , line:26:9, endln:26:12
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_constant: , line:26:21, endln:26:22
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.reset), line:26:13, endln:26:18
+            |vpiParent:
+            \_assignment: , line:26:13, endln:26:22
+            |vpiName:reset
+            |vpiFullName:work@tb_left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_delay_control: , line:27:9, endln:27:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+      |vpiStmt:
+      \_sys_func_call: ($dumpfile), line:30:9, endln:30:39
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiArgument:
+        \_constant: , line:30:19, endln:30:38
+        |vpiName:$dumpfile
+      |vpiStmt:
+      \_sys_func_call: ($dumpvars), line:31:9, endln:31:39
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiArgument:
+        \_constant: , line:31:19, endln:31:20
+        |vpiArgument:
+        \_ref_obj: (work@tb_left_rotation.tb_left_rotation), line:31:22, endln:31:38
+          |vpiParent:
+          \_sys_func_call: ($dumpvars), line:31:9, endln:31:39
+          |vpiName:tb_left_rotation
+          |vpiFullName:work@tb_left_rotation.tb_left_rotation
+          |vpiActual:
+          \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+        |vpiName:$dumpvars
+      |vpiStmt:
+      \_repeat: , line:34:9, endln:34:15
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiCondition:
+        \_constant: , line:34:16, endln:34:18
+        |vpiStmt:
+        \_begin: (work@tb_left_rotation), line:34:20, endln:37:12
+          |vpiParent:
+          \_repeat: , line:34:9, endln:34:15
+          |vpiFullName:work@tb_left_rotation
+          |vpiStmt:
+          \_assignment: , line:35:13, endln:35:44
+            |vpiParent:
+            \_begin: (work@tb_left_rotation), line:34:20, endln:37:12
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_operation: , line:35:23, endln:35:44
+              |vpiParent:
+              \_assignment: , line:35:13, endln:35:44
+              |vpiOpType:28
+              |vpiOperand:
+              \_sys_func_call: ($random), line:35:23, endln:35:30
+                |vpiParent:
+                \_operation: , line:35:23, endln:35:44
+                |vpiName:$random
+              |vpiOperand:
+              \_constant: , line:35:33, endln:35:44
+            |vpiLhs:
+            \_ref_obj: (work@tb_left_rotation.in_data), line:35:13, endln:35:20
+              |vpiParent:
+              \_assignment: , line:35:13, endln:35:44
+              |vpiName:in_data
+              |vpiFullName:work@tb_left_rotation.in_data
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+          |vpiStmt:
+          \_delay_control: , line:36:13, endln:36:16
+            |vpiParent:
+            \_begin: (work@tb_left_rotation), line:34:20, endln:37:12
+            |#10
+      |vpiStmt:
+      \_delay_control: , line:40:9, endln:40:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+        |vpiStmt:
+        \_assignment: , line:40:13, endln:40:22
+          |vpiParent:
+          \_delay_control: , line:40:9, endln:40:12
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_constant: , line:40:21, endln:40:22
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.reset), line:40:13, endln:40:18
+            |vpiParent:
+            \_assignment: , line:40:13, endln:40:22
+            |vpiName:reset
+            |vpiFullName:work@tb_left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_delay_control: , line:41:9, endln:41:12
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |#10
+        |vpiStmt:
+        \_assignment: , line:41:13, endln:41:22
+          |vpiParent:
+          \_delay_control: , line:41:9, endln:41:12
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_constant: , line:41:21, endln:41:22
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.reset), line:41:13, endln:41:18
+            |vpiParent:
+            \_assignment: , line:41:13, endln:41:22
+            |vpiName:reset
+            |vpiFullName:work@tb_left_rotation.reset
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+      |vpiStmt:
+      \_sys_func_call: ($finish), line:44:9, endln:44:16
+        |vpiParent:
+        \_begin: (work@tb_left_rotation), line:21:13, endln:45:8
+        |vpiName:$finish
+  |vpiModule:
+  \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+    |vpiParent:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiName:left_rotation_inst
+    |vpiFullName:work@tb_left_rotation.left_rotation_inst
+    |vpiDefName:work@left_rotation
+    |vpiDefFile:${SURELOG_DIR}/tests/AssertDelayError/left_rotate.sv
+    |vpiDefLineNo:1
+    |vpiNet:
+    \_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiTypespec:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.clk)
+        |vpiParent:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.clk
+        |vpiActual:
+        \_logic_typespec: , line:2:11, endln:2:15
+      |vpiName:clk
+      |vpiFullName:work@tb_left_rotation.left_rotation_inst.clk
+      |vpiNetType:1
+    |vpiNet:
+    \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiTypespec:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.reset)
+        |vpiParent:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.reset
+        |vpiActual:
+        \_logic_typespec: , line:3:11, endln:3:15
+      |vpiName:reset
+      |vpiFullName:work@tb_left_rotation.left_rotation_inst.reset
+      |vpiNetType:1
+    |vpiNet:
+    \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiTypespec:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.in_data)
+        |vpiParent:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.in_data
+        |vpiActual:
+        \_logic_typespec: , line:4:11, endln:4:21
+      |vpiName:in_data
+      |vpiFullName:work@tb_left_rotation.left_rotation_inst.in_data
+      |vpiNetType:1
+    |vpiNet:
+    \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiTypespec:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.out_data)
+        |vpiParent:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+        |vpiActual:
+        \_logic_typespec: , line:5:12, endln:5:21
+      |vpiName:out_data
+      |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+      |vpiNetType:48
+    |vpiInstance:
+    \_module_inst: work@tb_left_rotation (work@tb_left_rotation), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:2:1, endln:46:10
+    |vpiPort:
+    \_port: (clk), line:2:16, endln:2:19
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiName:clk
+      |vpiDirection:1
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.clk), line:9:14, endln:9:17
+        |vpiParent:
+        \_port: (clk), line:2:16, endln:2:19
+        |vpiName:clk
+        |vpiFullName:work@tb_left_rotation.clk
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
+      |vpiLowConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.clk), line:9:10, endln:9:13
+        |vpiParent:
+        \_port: (clk), line:2:16, endln:2:19
+        |vpiName:clk
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.clk
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
+      |vpiTypedef:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.clk)
+        |vpiParent:
+        \_port: (clk), line:2:16, endln:2:19
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.clk
+        |vpiActual:
+        \_logic_typespec: , line:2:11, endln:2:15
+      |vpiInstance:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+    |vpiPort:
+    \_port: (reset), line:3:16, endln:3:21
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiName:reset
+      |vpiDirection:1
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.reset), line:10:16, endln:10:21
+        |vpiParent:
+        \_port: (reset), line:3:16, endln:3:21
+        |vpiName:reset
+        |vpiFullName:work@tb_left_rotation.reset
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+      |vpiLowConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.reset), line:10:10, endln:10:15
+        |vpiParent:
+        \_port: (reset), line:3:16, endln:3:21
+        |vpiName:reset
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.reset
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+      |vpiTypedef:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.reset)
+        |vpiParent:
+        \_port: (reset), line:3:16, endln:3:21
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.reset
+        |vpiActual:
+        \_logic_typespec: , line:3:11, endln:3:15
+      |vpiInstance:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+    |vpiPort:
+    \_port: (in_data), line:4:22, endln:4:29
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiName:in_data
+      |vpiDirection:1
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.in_data), line:11:18, endln:11:25
+        |vpiParent:
+        \_port: (in_data), line:4:22, endln:4:29
+        |vpiName:in_data
+        |vpiFullName:work@tb_left_rotation.in_data
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
+      |vpiLowConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.in_data), line:11:10, endln:11:17
+        |vpiParent:
+        \_port: (in_data), line:4:22, endln:4:29
+        |vpiName:in_data
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.in_data
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
+      |vpiTypedef:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.in_data)
+        |vpiParent:
+        \_port: (in_data), line:4:22, endln:4:29
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.in_data
+        |vpiActual:
+        \_logic_typespec: , line:4:11, endln:4:21
+      |vpiInstance:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+    |vpiPort:
+    \_port: (out_data), line:5:22, endln:5:30
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiName:out_data
+      |vpiDirection:2
+      |vpiHighConn:
+      \_ref_obj: (work@tb_left_rotation.out_data), line:12:19, endln:12:27
+        |vpiParent:
+        \_port: (out_data), line:5:22, endln:5:30
+        |vpiName:out_data
+        |vpiFullName:work@tb_left_rotation.out_data
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+      |vpiLowConn:
+      \_ref_obj: (work@tb_left_rotation.left_rotation_inst.out_data), line:12:10, endln:12:18
+        |vpiParent:
+        \_port: (out_data), line:5:22, endln:5:30
+        |vpiName:out_data
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+        |vpiActual:
+        \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+      |vpiTypedef:
+      \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.out_data)
+        |vpiParent:
+        \_port: (out_data), line:5:22, endln:5:30
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+        |vpiActual:
+        \_logic_typespec: , line:5:12, endln:5:21
+      |vpiInstance:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+    |vpiProcess:
+    \_always: , line:8:1, endln:15:4
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiStmt:
+      \_event_control: , line:8:8, endln:8:39
+        |vpiParent:
+        \_always: , line:8:1, endln:15:4
+        |vpiCondition:
+        \_operation: , line:8:10, endln:8:38
+          |vpiParent:
+          \_event_control: , line:8:8, endln:8:39
+          |vpiOpType:35
+          |vpiOperand:
+          \_operation: , line:8:10, endln:8:21
+            |vpiParent:
+            \_operation: , line:8:10, endln:8:38
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.clk), line:8:18, endln:8:21
+              |vpiParent:
+              \_operation: , line:8:10, endln:8:21
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
+          |vpiOperand:
+          \_operation: , line:8:25, endln:8:38
+            |vpiParent:
+            \_operation: , line:8:10, endln:8:38
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.reset), line:8:33, endln:8:38
+              |vpiParent:
+              \_operation: , line:8:25, endln:8:38
+              |vpiName:reset
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.reset
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+        |vpiStmt:
+        \_begin: (work@tb_left_rotation.left_rotation_inst), line:8:40, endln:15:4
+          |vpiParent:
+          \_event_control: , line:8:8, endln:8:39
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst
+          |vpiStmt:
+          \_if_else: , line:9:5, endln:14:8
+            |vpiParent:
+            \_begin: (work@tb_left_rotation.left_rotation_inst), line:8:40, endln:15:4
+            |vpiCondition:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.reset), line:9:9, endln:9:14
+              |vpiParent:
+              \_if_else: , line:9:5, endln:14:8
+              |vpiName:reset
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.reset
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+            |vpiStmt:
+            \_begin: (work@tb_left_rotation.left_rotation_inst), line:9:16, endln:11:8
+              |vpiParent:
+              \_if_else: , line:9:5, endln:14:8
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst
+              |vpiStmt:
+              \_assignment: , line:10:9, endln:10:33
+                |vpiParent:
+                \_begin: (work@tb_left_rotation.left_rotation_inst), line:9:16, endln:11:8
+                |vpiOpType:82
+                |vpiRhs:
+                \_constant: , line:10:21, endln:10:33
+                |vpiLhs:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.out_data), line:10:9, endln:10:17
+                  |vpiParent:
+                  \_assignment: , line:10:9, endln:10:33
+                  |vpiName:out_data
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+            |vpiElseStmt:
+            \_begin: (work@tb_left_rotation.left_rotation_inst), line:11:14, endln:14:8
+              |vpiParent:
+              \_if_else: , line:9:5, endln:14:8
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst
+              |vpiStmt:
+              \_assignment: , line:13:9, endln:13:49
+                |vpiParent:
+                \_begin: (work@tb_left_rotation.left_rotation_inst), line:11:14, endln:14:8
+                |vpiOpType:82
+                |vpiRhs:
+                \_operation: , line:13:21, endln:13:49
+                  |vpiParent:
+                  \_assignment: , line:13:9, endln:13:49
+                  |vpiOpType:33
+                  |vpiOperand:
+                  \_part_select: out_data (work@tb_left_rotation.left_rotation_inst.out_data), line:13:22, endln:13:35
+                    |vpiParent:
+                    \_operation: , line:13:21, endln:13:49
+                    |vpiName:out_data
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+                    |vpiDefName:out_data
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+                    |vpiConstantSelect:1
+                    |vpiLeftRange:
+                    \_constant: , line:13:31, endln:13:32
+                    |vpiRightRange:
+                    \_constant: , line:13:33, endln:13:34
+                  |vpiOperand:
+                  \_bit_select: (work@tb_left_rotation.left_rotation_inst.out_data), line:13:46, endln:13:47
+                    |vpiParent:
+                    \_operation: , line:13:21, endln:13:49
+                    |vpiName:out_data
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+                    |vpiIndex:
+                    \_constant: , line:13:46, endln:13:47
+                |vpiLhs:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.out_data), line:13:9, endln:13:17
+                  |vpiParent:
+                  \_assignment: , line:13:9, endln:13:49
+                  |vpiName:out_data
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+      |vpiAlwaysType:1
+    |vpiProcess:
+    \_initial: , line:17:1, endln:19:4
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiStmt:
+      \_begin: (work@tb_left_rotation.left_rotation_inst), line:17:9, endln:19:4
+        |vpiParent:
+        \_initial: , line:17:1, endln:19:4
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst
+        |vpiStmt:
+        \_assignment: , line:18:5, endln:18:28
+          |vpiParent:
+          \_begin: (work@tb_left_rotation.left_rotation_inst), line:17:9, endln:19:4
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_constant: , line:18:16, endln:18:28
+          |vpiLhs:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.out_data), line:18:5, endln:18:13
+            |vpiParent:
+            \_assignment: , line:18:5, endln:18:28
+            |vpiName:out_data
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.out_data
+            |vpiActual:
+            \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+    |vpiModule:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiName:u_left_rotate_assertions
+      |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions
+      |vpiPropertyDecl:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:p_valid_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation
+        |vpiPropertySpec:
+        \_property_spec: , line:19:5, endln:19:98
+          |vpiParent:
+          \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+          |vpiClockingEvent:
+          \_operation: , line:19:7, endln:19:18
+            |vpiParent:
+            \_property_spec: , line:19:5, endln:19:98
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk), line:19:15, endln:19:18
+              |vpiParent:
+              \_operation: , line:19:7, endln:19:18
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiPropertyExpr:
+          \_operation: , line:19:20, endln:19:98
+            |vpiParent:
+            \_property_spec: , line:19:5, endln:19:98
+            |vpiOpType:52
+            |vpiOperand:
+            \_operation: , line:19:21, endln:19:27
+              |vpiParent:
+              \_operation: , line:19:20, endln:19:98
+              |vpiOpType:3
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n), line:19:22, endln:19:27
+                |vpiParent:
+                \_operation: , line:19:21, endln:19:27
+                |vpiName:rst_n
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+            |vpiOperand:
+            \_operation: , line:19:34, endln:19:97
+              |vpiParent:
+              \_operation: , line:19:20, endln:19:98
+              |vpiOpType:29
+              |vpiOperand:
+              \_operation: , line:19:34, endln:19:67
+                |vpiParent:
+                \_operation: , line:19:34, endln:19:97
+                |vpiOpType:14
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated), line:19:34, endln:19:41
+                  |vpiParent:
+                  \_operation: , line:19:34, endln:19:67
+                  |vpiName:rotated
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+                |vpiOperand:
+                \_operation: , line:19:46, endln:19:66
+                  |vpiParent:
+                  \_operation: , line:19:34, endln:19:67
+                  |vpiOpType:22
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:46, endln:19:53
+                    |vpiParent:
+                    \_operation: , line:19:46, endln:19:66
+                    |vpiName:word_in
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:57, endln:19:66
+                    |vpiParent:
+                    \_operation: , line:19:46, endln:19:66
+                    |vpiName:rotate_by
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+              |vpiOperand:
+              \_operation: , line:19:71, endln:19:96
+                |vpiParent:
+                \_operation: , line:19:34, endln:19:97
+                |vpiOpType:23
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:71, endln:19:78
+                  |vpiParent:
+                  \_operation: , line:19:71, endln:19:96
+                  |vpiName:word_in
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+                |vpiOperand:
+                \_operation: , line:19:83, endln:19:95
+                  |vpiParent:
+                  \_operation: , line:19:71, endln:19:96
+                  |vpiOpType:11
+                  |vpiOperand:
+                  \_constant: , line:19:83, endln:19:85
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:86, endln:19:95
+                    |vpiParent:
+                    \_operation: , line:19:83, endln:19:95
+                    |vpiName:rotate_by
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+      |vpiPropertyDecl:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:p_rotation_range
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range
+        |vpiPropertySpec:
+        \_property_spec: , line:25:5, endln:25:53
+          |vpiParent:
+          \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+          |vpiClockingEvent:
+          \_operation: , line:25:7, endln:25:18
+            |vpiParent:
+            \_property_spec: , line:25:5, endln:25:53
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk), line:25:15, endln:25:18
+              |vpiParent:
+              \_operation: , line:25:7, endln:25:18
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiPropertyExpr:
+          \_operation: , line:25:20, endln:25:53
+            |vpiParent:
+            \_property_spec: , line:25:5, endln:25:53
+            |vpiOpType:52
+            |vpiOperand:
+            \_operation: , line:25:21, endln:25:27
+              |vpiParent:
+              \_operation: , line:25:20, endln:25:53
+              |vpiOpType:3
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n), line:25:22, endln:25:27
+                |vpiParent:
+                \_operation: , line:25:21, endln:25:27
+                |vpiName:rst_n
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+            |vpiOperand:
+            \_operation: , line:25:34, endln:25:52
+              |vpiParent:
+              \_operation: , line:25:20, endln:25:53
+              |vpiOpType:21
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by), line:25:34, endln:25:43
+                |vpiParent:
+                \_operation: , line:25:34, endln:25:52
+                |vpiName:rotate_by
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+              |vpiOperand:
+              \_constant: , line:25:47, endln:25:52
+      |vpiPropertyDecl:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:p_no_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation
+        |vpiPropertySpec:
+        \_property_spec: , line:31:5, endln:31:71
+          |vpiParent:
+          \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+          |vpiClockingEvent:
+          \_operation: , line:31:7, endln:31:18
+            |vpiParent:
+            \_property_spec: , line:31:5, endln:31:71
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk), line:31:15, endln:31:18
+              |vpiParent:
+              \_operation: , line:31:7, endln:31:18
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiPropertyExpr:
+          \_operation: , line:31:20, endln:31:71
+            |vpiParent:
+            \_property_spec: , line:31:5, endln:31:71
+            |vpiOpType:52
+            |vpiOperand:
+            \_operation: , line:31:21, endln:31:45
+              |vpiParent:
+              \_operation: , line:31:20, endln:31:71
+              |vpiOpType:26
+              |vpiOperand:
+              \_operation: , line:31:21, endln:31:27
+                |vpiParent:
+                \_operation: , line:31:21, endln:31:45
+                |vpiOpType:3
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n), line:31:22, endln:31:27
+                  |vpiParent:
+                  \_operation: , line:31:21, endln:31:27
+                  |vpiName:rst_n
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+              |vpiOperand:
+              \_operation: , line:31:31, endln:31:45
+                |vpiParent:
+                \_operation: , line:31:21, endln:31:45
+                |vpiOpType:14
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by), line:31:31, endln:31:40
+                  |vpiParent:
+                  \_operation: , line:31:31, endln:31:45
+                  |vpiName:rotate_by
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+                |vpiOperand:
+                \_constant: , line:31:44, endln:31:45
+            |vpiOperand:
+            \_operation: , line:31:52, endln:31:70
+              |vpiParent:
+              \_operation: , line:31:20, endln:31:71
+              |vpiOpType:14
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated), line:31:52, endln:31:59
+                |vpiParent:
+                \_operation: , line:31:52, endln:31:70
+                |vpiName:rotated
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in), line:31:63, endln:31:70
+                |vpiParent:
+                \_operation: , line:31:52, endln:31:70
+                |vpiName:word_in
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+      |vpiDefName:work@left_rotate_assertions
+      |vpiDefFile:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv
+      |vpiDefLineNo:1
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+          |vpiActual:
+          \_logic_typespec: , line:2:11, endln:2:11
+        |vpiName:clk
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+          |vpiActual:
+          \_logic_typespec: , line:3:11, endln:3:11
+        |vpiName:rst_n
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in
+          |vpiActual:
+          \_logic_typespec: , line:4:11, endln:4:17
+        |vpiName:word_in
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by
+          |vpiActual:
+          \_logic_typespec: , line:5:11, endln:5:16
+        |vpiName:rotate_by
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+          |vpiActual:
+          \_logic_typespec: , line:6:11, endln:6:17
+        |vpiName:rotated
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+      |vpiAssertion:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:a_valid_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation
+        |vpiProperty:
+        \_property_spec: , line:21:37, endln:21:53
+          |vpiParent:
+          \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55
+          |vpiPropertyExpr:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation), line:21:37, endln:21:53
+            |vpiParent:
+            \_property_spec: , line:21:37, endln:21:53
+            |vpiName:p_valid_rotation
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation
+            |vpiActual:
+            \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+      |vpiAssertion:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:a_rotation_range
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range
+        |vpiProperty:
+        \_property_spec: , line:27:37, endln:27:53
+          |vpiParent:
+          \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55
+          |vpiPropertyExpr:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range), line:27:37, endln:27:53
+            |vpiParent:
+            \_property_spec: , line:27:37, endln:27:53
+            |vpiName:p_rotation_range
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range
+            |vpiActual:
+            \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+      |vpiAssertion:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:a_no_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation
+        |vpiProperty:
+        \_property_spec: , line:33:34, endln:33:47
+          |vpiParent:
+          \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49
+          |vpiPropertyExpr:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation), line:33:34, endln:33:47
+            |vpiParent:
+            \_property_spec: , line:33:34, endln:33:47
+            |vpiName:p_no_rotation
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation
+            |vpiActual:
+            \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+      |vpiInstance:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiPort:
+      \_port: (clk), line:2:11, endln:2:14
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:clk
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.clk), line:38:10, endln:38:13
+          |vpiParent:
+          \_port: (clk), line:2:11, endln:2:14
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.clk), line:38:6, endln:38:9
+          |vpiParent:
+          \_port: (clk), line:2:11, endln:2:14
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk)
+          |vpiParent:
+          \_port: (clk), line:2:11, endln:2:14
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+          |vpiActual:
+          \_logic_typespec: , line:2:11, endln:2:11
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (rst_n), line:3:11, endln:3:16
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:rst_n
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.reset), line:39:10, endln:39:15
+          |vpiParent:
+          \_port: (rst_n), line:3:11, endln:3:16
+          |vpiName:reset
+          |vpiFullName:work@tb_left_rotation.reset
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rst_n), line:39:4, endln:39:9
+          |vpiParent:
+          \_port: (rst_n), line:3:11, endln:3:16
+          |vpiName:rst_n
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rst_n
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n)
+          |vpiParent:
+          \_port: (rst_n), line:3:11, endln:3:16
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+          |vpiActual:
+          \_logic_typespec: , line:3:11, endln:3:11
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (word_in), line:4:18, endln:4:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:word_in
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.in_data), line:40:12, endln:40:19
+          |vpiParent:
+          \_port: (word_in), line:4:18, endln:4:25
+          |vpiName:in_data
+          |vpiFullName:work@tb_left_rotation.in_data
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.word_in), line:40:4, endln:40:11
+          |vpiParent:
+          \_port: (word_in), line:4:18, endln:4:25
+          |vpiName:word_in
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.word_in
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in)
+          |vpiParent:
+          \_port: (word_in), line:4:18, endln:4:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in
+          |vpiActual:
+          \_logic_typespec: , line:4:11, endln:4:17
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (rotate_by), line:5:17, endln:5:26
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:rotate_by
+        |vpiDirection:1
+        |vpiHighConn:
+        \_operation: , line:41:16, endln:41:17
+          |vpiParent:
+          \_port: (rotate_by), line:5:17, endln:5:26
+          |vpiOpType:36
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+          |vpiParent:
+          \_port: (rotate_by), line:5:17, endln:5:26
+          |vpiName:rotate_by
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rotate_by
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by)
+          |vpiParent:
+          \_port: (rotate_by), line:5:17, endln:5:26
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by
+          |vpiActual:
+          \_logic_typespec: , line:5:11, endln:5:16
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (rotated), line:6:18, endln:6:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:rotated
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.out_data), line:42:12, endln:42:20
+          |vpiParent:
+          \_port: (rotated), line:6:18, endln:6:25
+          |vpiName:out_data
+          |vpiFullName:work@tb_left_rotation.out_data
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rotated), line:42:4, endln:42:11
+          |vpiParent:
+          \_port: (rotated), line:6:18, endln:6:25
+          |vpiName:rotated
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rotated
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated)
+          |vpiParent:
+          \_port: (rotated), line:6:18, endln:6:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+          |vpiActual:
+          \_logic_typespec: , line:6:11, endln:6:17
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiProcess:
+      \_initial: , line:10:3, endln:15:6
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiStmt:
+        \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6
+          |vpiParent:
+          \_initial: , line:10:3, endln:15:6
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions
+          |vpiStmt:
+          \_event_control: , line:11:5, endln:11:19
+            |vpiParent:
+            \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6
+            |vpiCondition:
+            \_operation: , line:11:7, endln:11:18
+              |vpiParent:
+              \_event_control: , line:11:5, endln:11:19
+              |vpiOpType:39
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:11:15, endln:11:18
+                |vpiParent:
+                \_operation: , line:11:7, endln:11:18
+                |vpiName:clk
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiStmt:
+          \_if_stmt: , line:12:5, endln:14:8
+            |vpiParent:
+            \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6
+            |vpiCondition:
+            \_operation: , line:12:9, endln:12:15
+              |vpiParent:
+              \_if_stmt: , line:12:5, endln:14:8
+              |vpiOpType:3
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:12:10, endln:12:15
+                |vpiParent:
+                \_operation: , line:12:9, endln:12:15
+                |vpiName:rst_n
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+            |vpiStmt:
+            \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:12:17, endln:14:8
+              |vpiParent:
+              \_if_stmt: , line:12:5, endln:14:8
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions
+              |vpiStmt:
+              \_immediate_assert: , line:13:7, endln:13:28
+                |vpiParent:
+                \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:12:17, endln:14:8
+                |vpiExpr:
+                \_operation: , line:13:14, endln:13:26
+                  |vpiParent:
+                  \_immediate_assert: , line:13:7, endln:13:28
+                  |vpiOpType:14
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:13:14, endln:13:21
+                    |vpiParent:
+                    \_operation: , line:13:14, endln:13:26
+                    |vpiName:rotated
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+                  |vpiOperand:
+                  \_constant: , line:13:25, endln:13:26
+    |vpiModule:
+    \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiParent:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiName:u_left_rotate_assertions
+      |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions
+      |vpiPropertyDecl:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:p_valid_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation
+        |vpiPropertySpec:
+        \_property_spec: , line:19:5, endln:19:98
+          |vpiParent:
+          \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+          |vpiClockingEvent:
+          \_operation: , line:19:7, endln:19:18
+            |vpiParent:
+            \_property_spec: , line:19:5, endln:19:98
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk), line:19:15, endln:19:18
+              |vpiParent:
+              \_operation: , line:19:7, endln:19:18
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiPropertyExpr:
+          \_operation: , line:19:20, endln:19:98
+            |vpiParent:
+            \_property_spec: , line:19:5, endln:19:98
+            |vpiOpType:52
+            |vpiOperand:
+            \_operation: , line:19:21, endln:19:27
+              |vpiParent:
+              \_operation: , line:19:20, endln:19:98
+              |vpiOpType:3
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n), line:19:22, endln:19:27
+                |vpiParent:
+                \_operation: , line:19:21, endln:19:27
+                |vpiName:rst_n
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rst_n
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+            |vpiOperand:
+            \_operation: , line:19:34, endln:19:97
+              |vpiParent:
+              \_operation: , line:19:20, endln:19:98
+              |vpiOpType:29
+              |vpiOperand:
+              \_operation: , line:19:34, endln:19:67
+                |vpiParent:
+                \_operation: , line:19:34, endln:19:97
+                |vpiOpType:14
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated), line:19:34, endln:19:41
+                  |vpiParent:
+                  \_operation: , line:19:34, endln:19:67
+                  |vpiName:rotated
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotated
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+                |vpiOperand:
+                \_operation: , line:19:46, endln:19:66
+                  |vpiParent:
+                  \_operation: , line:19:34, endln:19:67
+                  |vpiOpType:22
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:46, endln:19:53
+                    |vpiParent:
+                    \_operation: , line:19:46, endln:19:66
+                    |vpiName:word_in
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:57, endln:19:66
+                    |vpiParent:
+                    \_operation: , line:19:46, endln:19:66
+                    |vpiName:rotate_by
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+              |vpiOperand:
+              \_operation: , line:19:71, endln:19:96
+                |vpiParent:
+                \_operation: , line:19:34, endln:19:97
+                |vpiOpType:23
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in), line:19:71, endln:19:78
+                  |vpiParent:
+                  \_operation: , line:19:71, endln:19:96
+                  |vpiName:word_in
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.word_in
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+                |vpiOperand:
+                \_operation: , line:19:83, endln:19:95
+                  |vpiParent:
+                  \_operation: , line:19:71, endln:19:96
+                  |vpiOpType:11
+                  |vpiOperand:
+                  \_constant: , line:19:83, endln:19:85
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by), line:19:86, endln:19:95
+                    |vpiParent:
+                    \_operation: , line:19:83, endln:19:95
+                    |vpiName:rotate_by
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation.rotate_by
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+      |vpiPropertyDecl:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:p_rotation_range
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range
+        |vpiPropertySpec:
+        \_property_spec: , line:25:5, endln:25:53
+          |vpiParent:
+          \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+          |vpiClockingEvent:
+          \_operation: , line:25:7, endln:25:18
+            |vpiParent:
+            \_property_spec: , line:25:5, endln:25:53
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk), line:25:15, endln:25:18
+              |vpiParent:
+              \_operation: , line:25:7, endln:25:18
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiPropertyExpr:
+          \_operation: , line:25:20, endln:25:53
+            |vpiParent:
+            \_property_spec: , line:25:5, endln:25:53
+            |vpiOpType:52
+            |vpiOperand:
+            \_operation: , line:25:21, endln:25:27
+              |vpiParent:
+              \_operation: , line:25:20, endln:25:53
+              |vpiOpType:3
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n), line:25:22, endln:25:27
+                |vpiParent:
+                \_operation: , line:25:21, endln:25:27
+                |vpiName:rst_n
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rst_n
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+            |vpiOperand:
+            \_operation: , line:25:34, endln:25:52
+              |vpiParent:
+              \_operation: , line:25:20, endln:25:53
+              |vpiOpType:21
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by), line:25:34, endln:25:43
+                |vpiParent:
+                \_operation: , line:25:34, endln:25:52
+                |vpiName:rotate_by
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range.rotate_by
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+              |vpiOperand:
+              \_constant: , line:25:47, endln:25:52
+      |vpiPropertyDecl:
+      \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:p_no_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation
+        |vpiPropertySpec:
+        \_property_spec: , line:31:5, endln:31:71
+          |vpiParent:
+          \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+          |vpiClockingEvent:
+          \_operation: , line:31:7, endln:31:18
+            |vpiParent:
+            \_property_spec: , line:31:5, endln:31:71
+            |vpiOpType:39
+            |vpiOperand:
+            \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk), line:31:15, endln:31:18
+              |vpiParent:
+              \_operation: , line:31:7, endln:31:18
+              |vpiName:clk
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.clk
+              |vpiActual:
+              \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiPropertyExpr:
+          \_operation: , line:31:20, endln:31:71
+            |vpiParent:
+            \_property_spec: , line:31:5, endln:31:71
+            |vpiOpType:52
+            |vpiOperand:
+            \_operation: , line:31:21, endln:31:45
+              |vpiParent:
+              \_operation: , line:31:20, endln:31:71
+              |vpiOpType:26
+              |vpiOperand:
+              \_operation: , line:31:21, endln:31:27
+                |vpiParent:
+                \_operation: , line:31:21, endln:31:45
+                |vpiOpType:3
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n), line:31:22, endln:31:27
+                  |vpiParent:
+                  \_operation: , line:31:21, endln:31:27
+                  |vpiName:rst_n
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rst_n
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+              |vpiOperand:
+              \_operation: , line:31:31, endln:31:45
+                |vpiParent:
+                \_operation: , line:31:21, endln:31:45
+                |vpiOpType:14
+                |vpiOperand:
+                \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by), line:31:31, endln:31:40
+                  |vpiParent:
+                  \_operation: , line:31:31, endln:31:45
+                  |vpiName:rotate_by
+                  |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotate_by
+                  |vpiActual:
+                  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+                |vpiOperand:
+                \_constant: , line:31:44, endln:31:45
+            |vpiOperand:
+            \_operation: , line:31:52, endln:31:70
+              |vpiParent:
+              \_operation: , line:31:20, endln:31:71
+              |vpiOpType:14
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated), line:31:52, endln:31:59
+                |vpiParent:
+                \_operation: , line:31:52, endln:31:70
+                |vpiName:rotated
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.rotated
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in), line:31:63, endln:31:70
+                |vpiParent:
+                \_operation: , line:31:52, endln:31:70
+                |vpiName:word_in
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation.word_in
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+      |vpiDefName:work@left_rotate_assertions
+      |vpiDefFile:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv
+      |vpiDefLineNo:1
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+          |vpiActual:
+          \_logic_typespec: , line:2:11, endln:2:11
+        |vpiName:clk
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+          |vpiActual:
+          \_logic_typespec: , line:3:11, endln:3:11
+        |vpiName:rst_n
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in
+          |vpiActual:
+          \_logic_typespec: , line:4:11, endln:4:17
+        |vpiName:word_in
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by
+          |vpiActual:
+          \_logic_typespec: , line:5:11, endln:5:16
+        |vpiName:rotate_by
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by
+      |vpiNet:
+      \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiTypespec:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated)
+          |vpiParent:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+          |vpiActual:
+          \_logic_typespec: , line:6:11, endln:6:17
+        |vpiName:rotated
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+      |vpiAssertion:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:a_valid_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation
+        |vpiProperty:
+        \_property_spec: , line:21:37, endln:21:53
+          |vpiParent:
+          \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation), line:21:3, endln:21:55
+          |vpiPropertyExpr:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation), line:21:37, endln:21:53
+            |vpiParent:
+            \_property_spec: , line:21:37, endln:21:53
+            |vpiName:p_valid_rotation
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_valid_rotation.p_valid_rotation
+            |vpiActual:
+            \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_valid_rotation)
+      |vpiAssertion:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:a_rotation_range
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range
+        |vpiProperty:
+        \_property_spec: , line:27:37, endln:27:53
+          |vpiParent:
+          \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range), line:27:3, endln:27:55
+          |vpiPropertyExpr:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range), line:27:37, endln:27:53
+            |vpiParent:
+            \_property_spec: , line:27:37, endln:27:53
+            |vpiName:p_rotation_range
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_rotation_range.p_rotation_range
+            |vpiActual:
+            \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_rotation_range)
+      |vpiAssertion:
+      \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:a_no_rotation
+        |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation
+        |vpiProperty:
+        \_property_spec: , line:33:34, endln:33:47
+          |vpiParent:
+          \_assert_stmt: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation), line:33:3, endln:33:49
+          |vpiPropertyExpr:
+          \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation), line:33:34, endln:33:47
+            |vpiParent:
+            \_property_spec: , line:33:34, endln:33:47
+            |vpiName:p_no_rotation
+            |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.a_no_rotation.p_no_rotation
+            |vpiActual:
+            \_property_decl: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.p_no_rotation)
+      |vpiInstance:
+      \_module_inst: work@left_rotation (work@tb_left_rotation.left_rotation_inst), file:${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv, line:8:5, endln:13:7
+      |vpiPort:
+      \_port: (clk), line:2:11, endln:2:14
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:clk
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.clk), line:38:10, endln:38:13
+          |vpiParent:
+          \_port: (clk), line:2:11, endln:2:14
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.clk), line:38:6, endln:38:9
+          |vpiParent:
+          \_port: (clk), line:2:11, endln:2:14
+          |vpiName:clk
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.clk
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk)
+          |vpiParent:
+          \_port: (clk), line:2:11, endln:2:14
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+          |vpiActual:
+          \_logic_typespec: , line:2:11, endln:2:11
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (rst_n), line:3:11, endln:3:16
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:rst_n
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.reset), line:39:10, endln:39:15
+          |vpiParent:
+          \_port: (rst_n), line:3:11, endln:3:16
+          |vpiName:reset
+          |vpiFullName:work@tb_left_rotation.reset
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rst_n), line:39:4, endln:39:9
+          |vpiParent:
+          \_port: (rst_n), line:3:11, endln:3:16
+          |vpiName:rst_n
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rst_n
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n)
+          |vpiParent:
+          \_port: (rst_n), line:3:11, endln:3:16
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+          |vpiActual:
+          \_logic_typespec: , line:3:11, endln:3:11
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (word_in), line:4:18, endln:4:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:word_in
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.in_data), line:40:12, endln:40:19
+          |vpiParent:
+          \_port: (word_in), line:4:18, endln:4:25
+          |vpiName:in_data
+          |vpiFullName:work@tb_left_rotation.in_data
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.word_in), line:40:4, endln:40:11
+          |vpiParent:
+          \_port: (word_in), line:4:18, endln:4:25
+          |vpiName:word_in
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.word_in
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in)
+          |vpiParent:
+          \_port: (word_in), line:4:18, endln:4:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in
+          |vpiActual:
+          \_logic_typespec: , line:4:11, endln:4:17
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (rotate_by), line:5:17, endln:5:26
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:rotate_by
+        |vpiDirection:1
+        |vpiHighConn:
+        \_operation: , line:41:16, endln:41:17
+          |vpiParent:
+          \_port: (rotate_by), line:5:17, endln:5:26
+          |vpiOpType:36
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+          |vpiParent:
+          \_port: (rotate_by), line:5:17, endln:5:26
+          |vpiName:rotate_by
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rotate_by
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by)
+          |vpiParent:
+          \_port: (rotate_by), line:5:17, endln:5:26
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by
+          |vpiActual:
+          \_logic_typespec: , line:5:11, endln:5:16
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiPort:
+      \_port: (rotated), line:6:18, endln:6:25
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiName:rotated
+        |vpiDirection:1
+        |vpiHighConn:
+        \_ref_obj: (work@tb_left_rotation.out_data), line:42:12, endln:42:20
+          |vpiParent:
+          \_port: (rotated), line:6:18, endln:6:25
+          |vpiName:out_data
+          |vpiFullName:work@tb_left_rotation.out_data
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+        |vpiLowConn:
+        \_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.rotated), line:42:4, endln:42:11
+          |vpiParent:
+          \_port: (rotated), line:6:18, endln:6:25
+          |vpiName:rotated
+          |vpiFullName:work@tb_left_rotation.u_left_rotate_assertions.rotated
+          |vpiActual:
+          \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+        |vpiTypedef:
+        \_ref_typespec: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated)
+          |vpiParent:
+          \_port: (rotated), line:6:18, endln:6:25
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+          |vpiActual:
+          \_logic_typespec: , line:6:11, endln:6:17
+        |vpiInstance:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+      |vpiProcess:
+      \_initial: , line:10:3, endln:15:6
+        |vpiParent:
+        \_module_inst: work@left_rotate_assertions (work@tb_left_rotation.u_left_rotate_assertions), file:${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv, line:37:20, endln:43:3
+        |vpiStmt:
+        \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6
+          |vpiParent:
+          \_initial: , line:10:3, endln:15:6
+          |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions
+          |vpiStmt:
+          \_event_control: , line:11:5, endln:11:19
+            |vpiParent:
+            \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6
+            |vpiCondition:
+            \_operation: , line:11:7, endln:11:18
+              |vpiParent:
+              \_event_control: , line:11:5, endln:11:19
+              |vpiOpType:39
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:11:15, endln:11:18
+                |vpiParent:
+                \_operation: , line:11:7, endln:11:18
+                |vpiName:clk
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+          |vpiStmt:
+          \_if_stmt: , line:12:5, endln:14:8
+            |vpiParent:
+            \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:10:11, endln:15:6
+            |vpiCondition:
+            \_operation: , line:12:9, endln:12:15
+              |vpiParent:
+              \_if_stmt: , line:12:5, endln:14:8
+              |vpiOpType:3
+              |vpiOperand:
+              \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:12:10, endln:12:15
+                |vpiParent:
+                \_operation: , line:12:9, endln:12:15
+                |vpiName:rst_n
+                |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n
+                |vpiActual:
+                \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+            |vpiStmt:
+            \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:12:17, endln:14:8
+              |vpiParent:
+              \_if_stmt: , line:12:5, endln:14:8
+              |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions
+              |vpiStmt:
+              \_immediate_assert: , line:13:7, endln:13:28
+                |vpiParent:
+                \_begin: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions), line:12:17, endln:14:8
+                |vpiExpr:
+                \_operation: , line:13:14, endln:13:26
+                  |vpiParent:
+                  \_immediate_assert: , line:13:7, endln:13:28
+                  |vpiOpType:14
+                  |vpiOperand:
+                  \_ref_obj: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:13:14, endln:13:21
+                    |vpiParent:
+                    \_operation: , line:13:14, endln:13:26
+                    |vpiName:rotated
+                    |vpiFullName:work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated
+                    |vpiActual:
+                    \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+                  |vpiOperand:
+                  \_constant: , line:13:25, endln:13:26
+\_weaklyReferenced:
+\_logic_typespec: , line:3:5, endln:3:8
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
+\_logic_typespec: , line:4:5, endln:4:14
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
+  |vpiRange:
+  \_range: , line:4:9, endln:4:14
+    |vpiParent:
+    \_logic_typespec: , line:4:5, endln:4:14
+    |vpiLeftRange:
+    \_constant: , line:4:10, endln:4:11
+      |vpiParent:
+      \_range: , line:4:9, endln:4:14
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:12, endln:4:13
+      |vpiParent:
+      \_range: , line:4:9, endln:4:14
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:5, endln:5:15
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.out_data), line:5:16, endln:5:24
+  |vpiRange:
+  \_range: , line:5:10, endln:5:15
+    |vpiParent:
+    \_logic_typespec: , line:5:5, endln:5:15
+    |vpiLeftRange:
+    \_constant: , line:5:11, endln:5:12
+      |vpiParent:
+      \_range: , line:5:10, endln:5:15
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:13, endln:5:14
+      |vpiParent:
+      \_range: , line:5:10, endln:5:15
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:15
+\_logic_typespec: , line:3:11, endln:3:15
+\_logic_typespec: , line:4:11, endln:4:21
+  |vpiRange:
+  \_range: , line:4:16, endln:4:21
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:21
+    |vpiLeftRange:
+    \_constant: , line:4:17, endln:4:18
+      |vpiParent:
+      \_range: , line:4:16, endln:4:21
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:19, endln:4:20
+      |vpiParent:
+      \_range: , line:4:16, endln:4:21
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:12, endln:5:21
+  |vpiRange:
+  \_range: , line:5:16, endln:5:21
+    |vpiParent:
+    \_logic_typespec: , line:5:12, endln:5:21
+    |vpiLeftRange:
+    \_constant: , line:5:17, endln:5:18
+      |vpiParent:
+      \_range: , line:5:16, endln:5:21
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:19, endln:5:20
+      |vpiParent:
+      \_range: , line:5:16, endln:5:21
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:15
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
+\_logic_typespec: , line:3:11, endln:3:15
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
+\_logic_typespec: , line:4:11, endln:4:21
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
+  |vpiRange:
+  \_range: , line:4:16, endln:4:21
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:21
+    |vpiLeftRange:
+    \_constant: , line:4:17, endln:4:18
+      |vpiParent:
+      \_range: , line:4:16, endln:4:21
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:19, endln:4:20
+      |vpiParent:
+      \_range: , line:4:16, endln:4:21
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:12, endln:5:21
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
+  |vpiRange:
+  \_range: , line:5:16, endln:5:21
+    |vpiParent:
+    \_logic_typespec: , line:5:12, endln:5:21
+    |vpiLeftRange:
+    \_constant: , line:5:17, endln:5:18
+      |vpiParent:
+      \_range: , line:5:16, endln:5:21
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:19, endln:5:20
+      |vpiParent:
+      \_range: , line:5:16, endln:5:21
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:11
+\_logic_typespec: , line:3:11, endln:3:11
+\_logic_typespec: , line:4:11, endln:4:17
+  |vpiRange:
+  \_range: , line:4:11, endln:4:17
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:17
+    |vpiLeftRange:
+    \_constant: , line:4:12, endln:4:14
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:15, endln:4:16
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:11, endln:5:16
+  |vpiRange:
+  \_range: , line:5:11, endln:5:16
+    |vpiParent:
+    \_logic_typespec: , line:5:11, endln:5:16
+    |vpiLeftRange:
+    \_constant: , line:5:12, endln:5:13
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:4
+      |vpiSize:64
+      |UINT:4
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:14, endln:5:15
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:6:11, endln:6:17
+  |vpiRange:
+  \_range: , line:6:11, endln:6:17
+    |vpiParent:
+    \_logic_typespec: , line:6:11, endln:6:17
+    |vpiLeftRange:
+    \_constant: , line:6:12, endln:6:14
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:6:15, endln:6:16
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:11
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+\_logic_typespec: , line:3:11, endln:3:11
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+\_logic_typespec: , line:4:11, endln:4:17
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+  |vpiRange:
+  \_range: , line:4:11, endln:4:17
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:17
+    |vpiLeftRange:
+    \_constant: , line:4:12, endln:4:14
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:15, endln:4:16
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:11, endln:5:16
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+  |vpiRange:
+  \_range: , line:5:11, endln:5:16
+    |vpiParent:
+    \_logic_typespec: , line:5:11, endln:5:16
+    |vpiLeftRange:
+    \_constant: , line:5:12, endln:5:13
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:4
+      |vpiSize:64
+      |UINT:4
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:14, endln:5:15
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:6:11, endln:6:17
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+  |vpiRange:
+  \_range: , line:6:11, endln:6:17
+    |vpiParent:
+    \_logic_typespec: , line:6:11, endln:6:17
+    |vpiLeftRange:
+    \_constant: , line:6:12, endln:6:14
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:6:15, endln:6:16
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:11
+\_logic_typespec: , line:3:11, endln:3:11
+\_logic_typespec: , line:4:11, endln:4:17
+  |vpiRange:
+  \_range: , line:4:11, endln:4:17
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:17
+    |vpiLeftRange:
+    \_constant: , line:4:12, endln:4:14
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:15, endln:4:16
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:11, endln:5:16
+  |vpiRange:
+  \_range: , line:5:11, endln:5:16
+    |vpiParent:
+    \_logic_typespec: , line:5:11, endln:5:16
+    |vpiLeftRange:
+    \_constant: , line:5:12, endln:5:13
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:4
+      |vpiSize:64
+      |UINT:4
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:14, endln:5:15
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:6:11, endln:6:17
+  |vpiRange:
+  \_range: , line:6:11, endln:6:17
+    |vpiParent:
+    \_logic_typespec: , line:6:11, endln:6:17
+    |vpiLeftRange:
+    \_constant: , line:6:12, endln:6:14
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:6:15, endln:6:16
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:11
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
+\_logic_typespec: , line:3:11, endln:3:11
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rst_n), line:3:11, endln:3:16
+\_logic_typespec: , line:4:11, endln:4:17
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.word_in), line:4:18, endln:4:25
+  |vpiRange:
+  \_range: , line:4:11, endln:4:17
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:17
+    |vpiLeftRange:
+    \_constant: , line:4:12, endln:4:14
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:15, endln:4:16
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:11, endln:5:16
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotate_by), line:5:17, endln:5:26
+  |vpiRange:
+  \_range: , line:5:11, endln:5:16
+    |vpiParent:
+    \_logic_typespec: , line:5:11, endln:5:16
+    |vpiLeftRange:
+    \_constant: , line:5:12, endln:5:13
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:4
+      |vpiSize:64
+      |UINT:4
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:14, endln:5:15
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:6:11, endln:6:17
+  |vpiParent:
+  \_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.rotated), line:6:18, endln:6:25
+  |vpiRange:
+  \_range: , line:6:11, endln:6:17
+    |vpiParent:
+    \_logic_typespec: , line:6:11, endln:6:17
+    |vpiLeftRange:
+    \_constant: , line:6:12, endln:6:14
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:6:15, endln:6:16
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:11
+\_logic_typespec: , line:3:11, endln:3:11
+\_logic_typespec: , line:4:11, endln:4:17
+  |vpiRange:
+  \_range: , line:4:11, endln:4:17
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:17
+    |vpiLeftRange:
+    \_constant: , line:4:12, endln:4:14
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:15, endln:4:16
+      |vpiParent:
+      \_range: , line:4:11, endln:4:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:11, endln:5:16
+  |vpiRange:
+  \_range: , line:5:11, endln:5:16
+    |vpiParent:
+    \_logic_typespec: , line:5:11, endln:5:16
+    |vpiLeftRange:
+    \_constant: , line:5:12, endln:5:13
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:4
+      |vpiSize:64
+      |UINT:4
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:14, endln:5:15
+      |vpiParent:
+      \_range: , line:5:11, endln:5:16
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:6:11, endln:6:17
+  |vpiRange:
+  \_range: , line:6:11, endln:6:17
+    |vpiParent:
+    \_logic_typespec: , line:6:11, endln:6:17
+    |vpiLeftRange:
+    \_constant: , line:6:12, endln:6:14
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:6:15, endln:6:16
+      |vpiParent:
+      \_range: , line:6:11, endln:6:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:2:11, endln:2:15
+\_logic_typespec: , line:3:11, endln:3:15
+\_logic_typespec: , line:4:11, endln:4:21
+  |vpiRange:
+  \_range: , line:4:16, endln:4:21
+    |vpiParent:
+    \_logic_typespec: , line:4:11, endln:4:21
+    |vpiLeftRange:
+    \_constant: , line:4:17, endln:4:18
+      |vpiParent:
+      \_range: , line:4:16, endln:4:21
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:19, endln:4:20
+      |vpiParent:
+      \_range: , line:4:16, endln:4:21
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:12, endln:5:21
+  |vpiRange:
+  \_range: , line:5:16, endln:5:21
+    |vpiParent:
+    \_logic_typespec: , line:5:12, endln:5:21
+    |vpiLeftRange:
+    \_constant: , line:5:17, endln:5:18
+      |vpiParent:
+      \_range: , line:5:16, endln:5:21
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:19, endln:5:20
+      |vpiParent:
+      \_range: , line:5:16, endln:5:21
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:3:5, endln:3:8
+\_logic_typespec: , line:3:5, endln:3:8
+\_logic_typespec: , line:4:5, endln:4:14
+  |vpiRange:
+  \_range: , line:4:9, endln:4:14
+    |vpiParent:
+    \_logic_typespec: , line:4:5, endln:4:14
+    |vpiLeftRange:
+    \_constant: , line:4:10, endln:4:11
+      |vpiParent:
+      \_range: , line:4:9, endln:4:14
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:4:12, endln:4:13
+      |vpiParent:
+      \_range: , line:4:9, endln:4:14
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:5:5, endln:5:15
+  |vpiRange:
+  \_range: , line:5:10, endln:5:15
+    |vpiParent:
+    \_logic_typespec: , line:5:5, endln:5:15
+    |vpiLeftRange:
+    \_constant: , line:5:11, endln:5:12
+      |vpiParent:
+      \_range: , line:5:10, endln:5:15
+      |vpiDecompile:7
+      |vpiSize:64
+      |UINT:7
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:5:13, endln:5:14
+      |vpiParent:
+      \_range: , line:5:10, endln:5:15
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+===================
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 3
+[   NOTE] : 5
+
+============================== Begin Linting Results ==============================
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:19:5: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:37:20: Non synthesizable construct, u_left_rotate_assertions
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:17:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:26:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:27:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:36:13: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:40:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:41:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:17:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:26:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:27:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:36:13: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:40:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/tb_left_rotate.sv:41:9: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:19:5: Non synthesizable construct,
+[LINT]: ${SURELOG_DIR}/tests/AssertDelayError/left_rotate_assertions.sv:37:20: Non synthesizable construct, u_left_rotate_assertions
+============================== End Linting Results ==============================
diff --git a/tests/AssertDelayError/AssertDelayError.sl b/tests/AssertDelayError/AssertDelayError.sl
new file mode 100644
index 0000000000..7773c64972
--- /dev/null
+++ b/tests/AssertDelayError/AssertDelayError.sl
@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -d ast left_rotate_assertions.sv  left_rotate.sv  tb_left_rotate.sv -nobuiltin
diff --git a/tests/AssertDelayError/left_rotate.sv b/tests/AssertDelayError/left_rotate.sv
new file mode 100644
index 0000000000..ec5f72b371
--- /dev/null
+++ b/tests/AssertDelayError/left_rotate.sv
@@ -0,0 +1,22 @@
+module left_rotation (
+    input wire clk,     // Clock input
+    input wire reset,   // Active-high synchronous reset
+    input wire [7:0] in_data, // 8-bit input data
+    output reg [7:0] out_data  // 8-bit output data after rotation
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        out_data <= 8'b0000_0000;  // Reset value
+    end else begin
+        // Perform left rotation
+        out_data <= {out_data[6:0], out_data[7]};
+    end
+end
+
+initial begin
+    out_data = 8'b0000_0000;  // Initial value
+end
+
+endmodule
+
diff --git a/tests/AssertDelayError/left_rotate_assertions.sv b/tests/AssertDelayError/left_rotate_assertions.sv
new file mode 100644
index 0000000000..fe492124de
--- /dev/null
+++ b/tests/AssertDelayError/left_rotate_assertions.sv
@@ -0,0 +1,43 @@
+module left_rotate_assertions (
+    input clk,
+    input rst_n,
+    input [31:0] word_in,
+    input [4:0] rotate_by, // 5 bits can represent values from 0 to 31
+    input [31:0] rotated
+);
+
+  // Initialization check
+  initial begin
+    @(posedge clk);
+    if (!rst_n) begin
+      assert(rotated == 0);
+    end
+  end
+
+  // Valid Rotation
+  property p_valid_rotation;
+    @(posedge clk) (!rst_n) |-> (rotated == (word_in << rotate_by) | (word_in >> (32-rotate_by)));
+  endproperty
+  a_valid_rotation: assert property(p_valid_rotation);
+
+  // Rotation Range
+  property p_rotation_range;
+    @(posedge clk) (!rst_n) |-> (rotate_by <= 5'd31);
+  endproperty
+  a_rotation_range: assert property(p_rotation_range);
+
+  // No Rotation
+  property p_no_rotation;
+    @(posedge clk) (!rst_n && rotate_by == 0) |-> (rotated == word_in);
+  endproperty
+  a_no_rotation: assert property(p_no_rotation);
+
+endmodule
+
+bind left_rotation left_rotate_assertions u_left_rotate_assertions (
+    .clk(clk),
+  .rst_n(reset),
+  .word_in(in_data),
+    .rotate_by(),
+  .rotated(out_data)
+);
diff --git a/tests/AssertDelayError/tb_left_rotate.sv b/tests/AssertDelayError/tb_left_rotate.sv
new file mode 100644
index 0000000000..fa73eb0f0f
--- /dev/null
+++ b/tests/AssertDelayError/tb_left_rotate.sv
@@ -0,0 +1,47 @@
+
+module tb_left_rotation;
+    reg clk, reset;
+    reg [7:0] in_data;
+    wire [7:0] out_data;
+
+    // Instantiate the left_rotation module
+    left_rotation left_rotation_inst(
+        .clk(clk),
+        .reset(reset),
+        .in_data(in_data),
+        .out_data(out_data)
+    );
+
+    // Clock generator
+    always begin
+        #5 clk = ~clk;
+    end
+
+    // Test procedure
+    initial begin
+        // Initial conditions
+        clk = 0;
+        reset = 1;
+        in_data = 8'b0;
+        #10 reset = 0;
+        #10;
+
+        // Start VCD dumping
+        $dumpfile("left_rotation.vcd");
+        $dumpvars(0, tb_left_rotation);
+
+        // Apply random inputs and observe the output
+        repeat(20) begin
+            in_data = $random & 8'b11111111;
+            #10;
+        end
+
+        // Assert reset to observe reset behavior
+        #10 reset = 1;
+        #10 reset = 0;
+
+        // Finish the simulation
+        $finish;
+    end
+endmodule
+
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index 6bbe19ed38..658e9b601f 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -77,7 +77,7 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
   CMake that the project does not need compatibility with older versions.
 
 
--- Configuring done (0.1s)
+-- Configuring done (0.0s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
 [  6%] Generating 10_lsu_bus_intf.sv
diff --git a/third_party/tests/SimpleUVM/SimpleUVM.log b/third_party/tests/SimpleUVM/SimpleUVM.log
index 7fb067dc96..12b0017c7a 100644
--- a/third_party/tests/SimpleUVM/SimpleUVM.log
+++ b/third_party/tests/SimpleUVM/SimpleUVM.log
@@ -386,8 +386,8 @@ assign_stmt                                         3547
 assignment                                          6293
 begin                                               6779
 bit_select                                          2126
-bit_typespec                                        3074
-bit_var                                             1194
+bit_typespec                                        3078
+bit_var                                             1196
 break_stmt                                            53
 byte_typespec                                        120
 byte_var                                              38
@@ -398,9 +398,9 @@ chandle_var                                            2
 class_defn                                           615
 class_typespec                                      8549
 class_var                                           3294
-clocking_block                                         1
-clocking_io_decl                                       4
-constant                                           28556
+clocking_block                                         3
+clocking_io_decl                                      12
+constant                                           28592
 constraint                                             4
 continue_stmt                                         52
 delay_control                                         54
@@ -410,7 +410,7 @@ do_while                                              51
 enum_const                                           551
 enum_typespec                                         93
 enum_var                                             186
-event_control                                         17
+event_control                                         19
 event_stmt                                            10
 event_typespec                                        10
 extends                                              279
@@ -430,32 +430,32 @@ indexed_part_select                                   41
 initial                                                3
 int_typespec                                        2767
 int_var                                             1363
-interface_inst                                         1
+interface_inst                                         5
 interface_typespec                                     1
 io_decl                                             6908
-logic_net                                            238
-logic_typespec                                        93
+logic_net                                            246
+logic_typespec                                       109
 logic_var                                             49
 long_int_typespec                                     99
 long_int_var                                          20
 method_func_call                                    8000
-module_inst                                           32
+module_inst                                           34
 named_begin                                            6
 named_event                                            8
 named_fork                                             3
-operation                                          10002
+operation                                          10004
 package                                                4
 packed_array_typespec                                  8
 param_assign                                         468
 parameter                                            673
 part_select                                           43
-port                                                  16
-range                                               2896
+port                                                  26
+range                                               2914
 real_typespec                                         33
 real_var                                               8
 ref_module                                             1
-ref_obj                                            41208
-ref_typespec                                       20760
+ref_obj                                            41230
+ref_typespec                                       20780
 ref_var                                             1788
 repeat                                                27
 return_stmt                                         3272
@@ -3907,6 +3907,16 @@ while_stmt                                           108
 [LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/testbench.sv:61:7: Non synthesizable construct,
 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_misc.svh:74:39: Non synthesizable construct, $urandom
 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_misc.svh:74:39: Non synthesizable construct, $urandom
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:33:15: Non synthesizable construct, a
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:34:15: Non synthesizable construct, b
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:35:15: Non synthesizable construct, doAdd
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:36:15: Non synthesizable construct, result
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:32:3: Non synthesizable construct, cb
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:33:15: Non synthesizable construct, a
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:34:15: Non synthesizable construct, b
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:35:15: Non synthesizable construct, doAdd
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:36:15: Non synthesizable construct, result
+[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:32:3: Non synthesizable construct, cb
 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_agent.svh:67:6: Unsupported typespec, uvm_resource_types::rsrc_q_t
 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/macros/uvm_resource_defines.svh:123:6: Unsupported typespec, __tmp_int_t__
 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_traversal.svh:168:13: Unsupported typespec, c