diff --git a/tests/BlockingAssignRewrite/BlockingAssignRewrite.log b/tests/BlockingAssignRewrite/BlockingAssignRewrite.log
new file mode 100644
index 0000000000..698428a979
--- /dev/null
+++ b/tests/BlockingAssignRewrite/BlockingAssignRewrite.log
@@ -0,0 +1,4069 @@
+[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/surelog.log".
+AST_DEBUG_BEGIN
+LIB:  work
+FILE: ${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<943> s<942> l<1:1> el<1:0>
+n<module> u<2> t<Module_keyword> p<77> s<3> l<1:1> el<1:7>
+n<asym_ram_tdp_write_first_dc> u<3> t<StringConst> p<77> s<76> l<1:8> el<1:35>
+n<clkA> u<4> t<StringConst> p<7> s<6> l<1:37> el<1:41>
+n<> u<5> t<Constant_bit_select> p<6> l<1:41> el<1:41>
+n<> u<6> t<Constant_select> p<7> c<5> l<1:41> el<1:41>
+n<> u<7> t<Port_reference> p<8> c<4> l<1:37> el<1:41>
+n<> u<8> t<Port_expression> p<9> c<7> l<1:37> el<1:41>
+n<> u<9> t<Port> p<76> c<8> s<15> l<1:37> el<1:41>
+n<clkB> u<10> t<StringConst> p<13> s<12> l<1:43> el<1:47>
+n<> u<11> t<Constant_bit_select> p<12> l<1:47> el<1:47>
+n<> u<12> t<Constant_select> p<13> c<11> l<1:47> el<1:47>
+n<> u<13> t<Port_reference> p<14> c<10> l<1:43> el<1:47>
+n<> u<14> t<Port_expression> p<15> c<13> l<1:43> el<1:47>
+n<> u<15> t<Port> p<76> c<14> s<21> l<1:43> el<1:47>
+n<enaA> u<16> t<StringConst> p<19> s<18> l<1:49> el<1:53>
+n<> u<17> t<Constant_bit_select> p<18> l<1:53> el<1:53>
+n<> u<18> t<Constant_select> p<19> c<17> l<1:53> el<1:53>
+n<> u<19> t<Port_reference> p<20> c<16> l<1:49> el<1:53>
+n<> u<20> t<Port_expression> p<21> c<19> l<1:49> el<1:53>
+n<> u<21> t<Port> p<76> c<20> s<27> l<1:49> el<1:53>
+n<weA> u<22> t<StringConst> p<25> s<24> l<1:55> el<1:58>
+n<> u<23> t<Constant_bit_select> p<24> l<1:58> el<1:58>
+n<> u<24> t<Constant_select> p<25> c<23> l<1:58> el<1:58>
+n<> u<25> t<Port_reference> p<26> c<22> l<1:55> el<1:58>
+n<> u<26> t<Port_expression> p<27> c<25> l<1:55> el<1:58>
+n<> u<27> t<Port> p<76> c<26> s<33> l<1:55> el<1:58>
+n<enaB> u<28> t<StringConst> p<31> s<30> l<1:60> el<1:64>
+n<> u<29> t<Constant_bit_select> p<30> l<1:64> el<1:64>
+n<> u<30> t<Constant_select> p<31> c<29> l<1:64> el<1:64>
+n<> u<31> t<Port_reference> p<32> c<28> l<1:60> el<1:64>
+n<> u<32> t<Port_expression> p<33> c<31> l<1:60> el<1:64>
+n<> u<33> t<Port> p<76> c<32> s<39> l<1:60> el<1:64>
+n<weB> u<34> t<StringConst> p<37> s<36> l<1:66> el<1:69>
+n<> u<35> t<Constant_bit_select> p<36> l<1:69> el<1:69>
+n<> u<36> t<Constant_select> p<37> c<35> l<1:69> el<1:69>
+n<> u<37> t<Port_reference> p<38> c<34> l<1:66> el<1:69>
+n<> u<38> t<Port_expression> p<39> c<37> l<1:66> el<1:69>
+n<> u<39> t<Port> p<76> c<38> s<45> l<1:66> el<1:69>
+n<addrA> u<40> t<StringConst> p<43> s<42> l<1:71> el<1:76>
+n<> u<41> t<Constant_bit_select> p<42> l<1:76> el<1:76>
+n<> u<42> t<Constant_select> p<43> c<41> l<1:76> el<1:76>
+n<> u<43> t<Port_reference> p<44> c<40> l<1:71> el<1:76>
+n<> u<44> t<Port_expression> p<45> c<43> l<1:71> el<1:76>
+n<> u<45> t<Port> p<76> c<44> s<51> l<1:71> el<1:76>
+n<addrB> u<46> t<StringConst> p<49> s<48> l<1:78> el<1:83>
+n<> u<47> t<Constant_bit_select> p<48> l<1:83> el<1:83>
+n<> u<48> t<Constant_select> p<49> c<47> l<1:83> el<1:83>
+n<> u<49> t<Port_reference> p<50> c<46> l<1:78> el<1:83>
+n<> u<50> t<Port_expression> p<51> c<49> l<1:78> el<1:83>
+n<> u<51> t<Port> p<76> c<50> s<57> l<1:78> el<1:83>
+n<diA> u<52> t<StringConst> p<55> s<54> l<1:85> el<1:88>
+n<> u<53> t<Constant_bit_select> p<54> l<1:88> el<1:88>
+n<> u<54> t<Constant_select> p<55> c<53> l<1:88> el<1:88>
+n<> u<55> t<Port_reference> p<56> c<52> l<1:85> el<1:88>
+n<> u<56> t<Port_expression> p<57> c<55> l<1:85> el<1:88>
+n<> u<57> t<Port> p<76> c<56> s<63> l<1:85> el<1:88>
+n<doA> u<58> t<StringConst> p<61> s<60> l<1:90> el<1:93>
+n<> u<59> t<Constant_bit_select> p<60> l<1:93> el<1:93>
+n<> u<60> t<Constant_select> p<61> c<59> l<1:93> el<1:93>
+n<> u<61> t<Port_reference> p<62> c<58> l<1:90> el<1:93>
+n<> u<62> t<Port_expression> p<63> c<61> l<1:90> el<1:93>
+n<> u<63> t<Port> p<76> c<62> s<69> l<1:90> el<1:93>
+n<diB> u<64> t<StringConst> p<67> s<66> l<1:95> el<1:98>
+n<> u<65> t<Constant_bit_select> p<66> l<1:98> el<1:98>
+n<> u<66> t<Constant_select> p<67> c<65> l<1:98> el<1:98>
+n<> u<67> t<Port_reference> p<68> c<64> l<1:95> el<1:98>
+n<> u<68> t<Port_expression> p<69> c<67> l<1:95> el<1:98>
+n<> u<69> t<Port> p<76> c<68> s<75> l<1:95> el<1:98>
+n<doB> u<70> t<StringConst> p<73> s<72> l<1:100> el<1:103>
+n<> u<71> t<Constant_bit_select> p<72> l<1:103> el<1:103>
+n<> u<72> t<Constant_select> p<73> c<71> l<1:103> el<1:103>
+n<> u<73> t<Port_reference> p<74> c<70> l<1:100> el<1:103>
+n<> u<74> t<Port_expression> p<75> c<73> l<1:100> el<1:103>
+n<> u<75> t<Port> p<76> c<74> l<1:100> el<1:103>
+n<> u<76> t<List_of_ports> p<77> c<9> l<1:36> el<1:104>
+n<> u<77> t<Module_nonansi_header> p<940> c<2> s<94> l<1:1> el<1:105>
+n<> u<78> t<Data_type_or_implicit> p<88> s<87> l<3:11> el<3:11>
+n<WIDTHB> u<79> t<StringConst> p<86> s<85> l<3:11> el<3:17>
+n<4> u<80> t<IntConst> p<81> l<3:20> el<3:21>
+n<> u<81> t<Primary_literal> p<82> c<80> l<3:20> el<3:21>
+n<> u<82> t<Constant_primary> p<83> c<81> l<3:20> el<3:21>
+n<> u<83> t<Constant_expression> p<84> c<82> l<3:20> el<3:21>
+n<> u<84> t<Constant_mintypmax_expression> p<85> c<83> l<3:20> el<3:21>
+n<> u<85> t<Constant_param_expression> p<86> c<84> l<3:20> el<3:21>
+n<> u<86> t<Param_assignment> p<87> c<79> l<3:11> el<3:21>
+n<> u<87> t<List_of_param_assignments> p<88> c<86> l<3:11> el<3:21>
+n<> u<88> t<Parameter_declaration> p<89> c<78> l<3:1> el<3:21>
+n<> u<89> t<Package_or_generate_item_declaration> p<90> c<88> l<3:1> el<3:22>
+n<> u<90> t<Module_or_generate_item_declaration> p<91> c<89> l<3:1> el<3:22>
+n<> u<91> t<Module_common_item> p<92> c<90> l<3:1> el<3:22>
+n<> u<92> t<Module_or_generate_item> p<93> c<91> l<3:1> el<3:22>
+n<> u<93> t<Non_port_module_item> p<94> c<92> l<3:1> el<3:22>
+n<> u<94> t<Module_item> p<940> c<93> s<111> l<3:1> el<3:22>
+n<> u<95> t<Data_type_or_implicit> p<105> s<104> l<4:11> el<4:11>
+n<SIZEB> u<96> t<StringConst> p<103> s<102> l<4:11> el<4:16>
+n<1024> u<97> t<IntConst> p<98> l<4:19> el<4:23>
+n<> u<98> t<Primary_literal> p<99> c<97> l<4:19> el<4:23>
+n<> u<99> t<Constant_primary> p<100> c<98> l<4:19> el<4:23>
+n<> u<100> t<Constant_expression> p<101> c<99> l<4:19> el<4:23>
+n<> u<101> t<Constant_mintypmax_expression> p<102> c<100> l<4:19> el<4:23>
+n<> u<102> t<Constant_param_expression> p<103> c<101> l<4:19> el<4:23>
+n<> u<103> t<Param_assignment> p<104> c<96> l<4:11> el<4:23>
+n<> u<104> t<List_of_param_assignments> p<105> c<103> l<4:11> el<4:23>
+n<> u<105> t<Parameter_declaration> p<106> c<95> l<4:1> el<4:23>
+n<> u<106> t<Package_or_generate_item_declaration> p<107> c<105> l<4:1> el<4:24>
+n<> u<107> t<Module_or_generate_item_declaration> p<108> c<106> l<4:1> el<4:24>
+n<> u<108> t<Module_common_item> p<109> c<107> l<4:1> el<4:24>
+n<> u<109> t<Module_or_generate_item> p<110> c<108> l<4:1> el<4:24>
+n<> u<110> t<Non_port_module_item> p<111> c<109> l<4:1> el<4:24>
+n<> u<111> t<Module_item> p<940> c<110> s<128> l<4:1> el<4:24>
+n<> u<112> t<Data_type_or_implicit> p<122> s<121> l<5:11> el<5:11>
+n<ADDRWIDTHB> u<113> t<StringConst> p<120> s<119> l<5:11> el<5:21>
+n<10> u<114> t<IntConst> p<115> l<5:24> el<5:26>
+n<> u<115> t<Primary_literal> p<116> c<114> l<5:24> el<5:26>
+n<> u<116> t<Constant_primary> p<117> c<115> l<5:24> el<5:26>
+n<> u<117> t<Constant_expression> p<118> c<116> l<5:24> el<5:26>
+n<> u<118> t<Constant_mintypmax_expression> p<119> c<117> l<5:24> el<5:26>
+n<> u<119> t<Constant_param_expression> p<120> c<118> l<5:24> el<5:26>
+n<> u<120> t<Param_assignment> p<121> c<113> l<5:11> el<5:26>
+n<> u<121> t<List_of_param_assignments> p<122> c<120> l<5:11> el<5:26>
+n<> u<122> t<Parameter_declaration> p<123> c<112> l<5:1> el<5:26>
+n<> u<123> t<Package_or_generate_item_declaration> p<124> c<122> l<5:1> el<5:27>
+n<> u<124> t<Module_or_generate_item_declaration> p<125> c<123> l<5:1> el<5:27>
+n<> u<125> t<Module_common_item> p<126> c<124> l<5:1> el<5:27>
+n<> u<126> t<Module_or_generate_item> p<127> c<125> l<5:1> el<5:27>
+n<> u<127> t<Non_port_module_item> p<128> c<126> l<5:1> el<5:27>
+n<> u<128> t<Module_item> p<940> c<127> s<145> l<5:1> el<5:27>
+n<> u<129> t<Data_type_or_implicit> p<139> s<138> l<6:11> el<6:11>
+n<WIDTHA> u<130> t<StringConst> p<137> s<136> l<6:11> el<6:17>
+n<16> u<131> t<IntConst> p<132> l<6:20> el<6:22>
+n<> u<132> t<Primary_literal> p<133> c<131> l<6:20> el<6:22>
+n<> u<133> t<Constant_primary> p<134> c<132> l<6:20> el<6:22>
+n<> u<134> t<Constant_expression> p<135> c<133> l<6:20> el<6:22>
+n<> u<135> t<Constant_mintypmax_expression> p<136> c<134> l<6:20> el<6:22>
+n<> u<136> t<Constant_param_expression> p<137> c<135> l<6:20> el<6:22>
+n<> u<137> t<Param_assignment> p<138> c<130> l<6:11> el<6:22>
+n<> u<138> t<List_of_param_assignments> p<139> c<137> l<6:11> el<6:22>
+n<> u<139> t<Parameter_declaration> p<140> c<129> l<6:1> el<6:22>
+n<> u<140> t<Package_or_generate_item_declaration> p<141> c<139> l<6:1> el<6:23>
+n<> u<141> t<Module_or_generate_item_declaration> p<142> c<140> l<6:1> el<6:23>
+n<> u<142> t<Module_common_item> p<143> c<141> l<6:1> el<6:23>
+n<> u<143> t<Module_or_generate_item> p<144> c<142> l<6:1> el<6:23>
+n<> u<144> t<Non_port_module_item> p<145> c<143> l<6:1> el<6:23>
+n<> u<145> t<Module_item> p<940> c<144> s<162> l<6:1> el<6:23>
+n<> u<146> t<Data_type_or_implicit> p<156> s<155> l<7:11> el<7:11>
+n<SIZEA> u<147> t<StringConst> p<154> s<153> l<7:11> el<7:16>
+n<256> u<148> t<IntConst> p<149> l<7:19> el<7:22>
+n<> u<149> t<Primary_literal> p<150> c<148> l<7:19> el<7:22>
+n<> u<150> t<Constant_primary> p<151> c<149> l<7:19> el<7:22>
+n<> u<151> t<Constant_expression> p<152> c<150> l<7:19> el<7:22>
+n<> u<152> t<Constant_mintypmax_expression> p<153> c<151> l<7:19> el<7:22>
+n<> u<153> t<Constant_param_expression> p<154> c<152> l<7:19> el<7:22>
+n<> u<154> t<Param_assignment> p<155> c<147> l<7:11> el<7:22>
+n<> u<155> t<List_of_param_assignments> p<156> c<154> l<7:11> el<7:22>
+n<> u<156> t<Parameter_declaration> p<157> c<146> l<7:1> el<7:22>
+n<> u<157> t<Package_or_generate_item_declaration> p<158> c<156> l<7:1> el<7:23>
+n<> u<158> t<Module_or_generate_item_declaration> p<159> c<157> l<7:1> el<7:23>
+n<> u<159> t<Module_common_item> p<160> c<158> l<7:1> el<7:23>
+n<> u<160> t<Module_or_generate_item> p<161> c<159> l<7:1> el<7:23>
+n<> u<161> t<Non_port_module_item> p<162> c<160> l<7:1> el<7:23>
+n<> u<162> t<Module_item> p<940> c<161> s<179> l<7:1> el<7:23>
+n<> u<163> t<Data_type_or_implicit> p<173> s<172> l<8:11> el<8:11>
+n<ADDRWIDTHA> u<164> t<StringConst> p<171> s<170> l<8:11> el<8:21>
+n<8> u<165> t<IntConst> p<166> l<8:24> el<8:25>
+n<> u<166> t<Primary_literal> p<167> c<165> l<8:24> el<8:25>
+n<> u<167> t<Constant_primary> p<168> c<166> l<8:24> el<8:25>
+n<> u<168> t<Constant_expression> p<169> c<167> l<8:24> el<8:25>
+n<> u<169> t<Constant_mintypmax_expression> p<170> c<168> l<8:24> el<8:25>
+n<> u<170> t<Constant_param_expression> p<171> c<169> l<8:24> el<8:25>
+n<> u<171> t<Param_assignment> p<172> c<164> l<8:11> el<8:25>
+n<> u<172> t<List_of_param_assignments> p<173> c<171> l<8:11> el<8:25>
+n<> u<173> t<Parameter_declaration> p<174> c<163> l<8:1> el<8:25>
+n<> u<174> t<Package_or_generate_item_declaration> p<175> c<173> l<8:1> el<8:26>
+n<> u<175> t<Module_or_generate_item_declaration> p<176> c<174> l<8:1> el<8:26>
+n<> u<176> t<Module_common_item> p<177> c<175> l<8:1> el<8:26>
+n<> u<177> t<Module_or_generate_item> p<178> c<176> l<8:1> el<8:26>
+n<> u<178> t<Non_port_module_item> p<179> c<177> l<8:1> el<8:26>
+n<> u<179> t<Module_item> p<940> c<178> s<186> l<8:1> el<8:26>
+n<> u<180> t<Data_type_or_implicit> p<181> l<10:7> el<10:7>
+n<> u<181> t<Net_port_type> p<184> c<180> s<183> l<10:7> el<10:7>
+n<clkA> u<182> t<StringConst> p<183> l<10:7> el<10:11>
+n<> u<183> t<List_of_port_identifiers> p<184> c<182> l<10:7> el<10:11>
+n<> u<184> t<Input_declaration> p<185> c<181> l<10:1> el<10:11>
+n<> u<185> t<Port_declaration> p<186> c<184> l<10:1> el<10:11>
+n<> u<186> t<Module_item> p<940> c<185> s<193> l<10:1> el<10:12>
+n<> u<187> t<Data_type_or_implicit> p<188> l<11:7> el<11:7>
+n<> u<188> t<Net_port_type> p<191> c<187> s<190> l<11:7> el<11:7>
+n<clkB> u<189> t<StringConst> p<190> l<11:7> el<11:11>
+n<> u<190> t<List_of_port_identifiers> p<191> c<189> l<11:7> el<11:11>
+n<> u<191> t<Input_declaration> p<192> c<188> l<11:1> el<11:11>
+n<> u<192> t<Port_declaration> p<193> c<191> l<11:1> el<11:11>
+n<> u<193> t<Module_item> p<940> c<192> s<201> l<11:1> el<11:12>
+n<> u<194> t<Data_type_or_implicit> p<195> l<12:7> el<12:7>
+n<> u<195> t<Net_port_type> p<199> c<194> s<198> l<12:7> el<12:7>
+n<weA> u<196> t<StringConst> p<198> s<197> l<12:7> el<12:10>
+n<weB> u<197> t<StringConst> p<198> l<12:12> el<12:15>
+n<> u<198> t<List_of_port_identifiers> p<199> c<196> l<12:7> el<12:15>
+n<> u<199> t<Input_declaration> p<200> c<195> l<12:1> el<12:15>
+n<> u<200> t<Port_declaration> p<201> c<199> l<12:1> el<12:15>
+n<> u<201> t<Module_item> p<940> c<200> s<209> l<12:1> el<12:16>
+n<> u<202> t<Data_type_or_implicit> p<203> l<13:7> el<13:7>
+n<> u<203> t<Net_port_type> p<207> c<202> s<206> l<13:7> el<13:7>
+n<enaA> u<204> t<StringConst> p<206> s<205> l<13:7> el<13:11>
+n<enaB> u<205> t<StringConst> p<206> l<13:13> el<13:17>
+n<> u<206> t<List_of_port_identifiers> p<207> c<204> l<13:7> el<13:17>
+n<> u<207> t<Input_declaration> p<208> c<203> l<13:1> el<13:17>
+n<> u<208> t<Port_declaration> p<209> c<207> l<13:1> el<13:17>
+n<> u<209> t<Module_item> p<940> c<208> s<232> l<13:1> el<13:18>
+n<ADDRWIDTHA> u<210> t<StringConst> p<211> l<14:8> el<14:18>
+n<> u<211> t<Primary_literal> p<212> c<210> l<14:8> el<14:18>
+n<> u<212> t<Constant_primary> p<213> c<211> l<14:8> el<14:18>
+n<> u<213> t<Constant_expression> p<219> c<212> s<218> l<14:8> el<14:18>
+n<1> u<214> t<IntConst> p<215> l<14:19> el<14:20>
+n<> u<215> t<Primary_literal> p<216> c<214> l<14:19> el<14:20>
+n<> u<216> t<Constant_primary> p<217> c<215> l<14:19> el<14:20>
+n<> u<217> t<Constant_expression> p<219> c<216> l<14:19> el<14:20>
+n<> u<218> t<BinOp_Minus> p<219> s<217> l<14:18> el<14:19>
+n<> u<219> t<Constant_expression> p<224> c<213> s<223> l<14:8> el<14:20>
+n<0> u<220> t<IntConst> p<221> l<14:21> el<14:22>
+n<> u<221> t<Primary_literal> p<222> c<220> l<14:21> el<14:22>
+n<> u<222> t<Constant_primary> p<223> c<221> l<14:21> el<14:22>
+n<> u<223> t<Constant_expression> p<224> c<222> l<14:21> el<14:22>
+n<> u<224> t<Constant_range> p<225> c<219> l<14:8> el<14:22>
+n<> u<225> t<Packed_dimension> p<226> c<224> l<14:7> el<14:23>
+n<> u<226> t<Data_type_or_implicit> p<227> c<225> l<14:7> el<14:23>
+n<> u<227> t<Net_port_type> p<230> c<226> s<229> l<14:7> el<14:23>
+n<addrA> u<228> t<StringConst> p<229> l<14:24> el<14:29>
+n<> u<229> t<List_of_port_identifiers> p<230> c<228> l<14:24> el<14:29>
+n<> u<230> t<Input_declaration> p<231> c<227> l<14:1> el<14:29>
+n<> u<231> t<Port_declaration> p<232> c<230> l<14:1> el<14:29>
+n<> u<232> t<Module_item> p<940> c<231> s<255> l<14:1> el<14:30>
+n<ADDRWIDTHB> u<233> t<StringConst> p<234> l<15:8> el<15:18>
+n<> u<234> t<Primary_literal> p<235> c<233> l<15:8> el<15:18>
+n<> u<235> t<Constant_primary> p<236> c<234> l<15:8> el<15:18>
+n<> u<236> t<Constant_expression> p<242> c<235> s<241> l<15:8> el<15:18>
+n<1> u<237> t<IntConst> p<238> l<15:19> el<15:20>
+n<> u<238> t<Primary_literal> p<239> c<237> l<15:19> el<15:20>
+n<> u<239> t<Constant_primary> p<240> c<238> l<15:19> el<15:20>
+n<> u<240> t<Constant_expression> p<242> c<239> l<15:19> el<15:20>
+n<> u<241> t<BinOp_Minus> p<242> s<240> l<15:18> el<15:19>
+n<> u<242> t<Constant_expression> p<247> c<236> s<246> l<15:8> el<15:20>
+n<0> u<243> t<IntConst> p<244> l<15:21> el<15:22>
+n<> u<244> t<Primary_literal> p<245> c<243> l<15:21> el<15:22>
+n<> u<245> t<Constant_primary> p<246> c<244> l<15:21> el<15:22>
+n<> u<246> t<Constant_expression> p<247> c<245> l<15:21> el<15:22>
+n<> u<247> t<Constant_range> p<248> c<242> l<15:8> el<15:22>
+n<> u<248> t<Packed_dimension> p<249> c<247> l<15:7> el<15:23>
+n<> u<249> t<Data_type_or_implicit> p<250> c<248> l<15:7> el<15:23>
+n<> u<250> t<Net_port_type> p<253> c<249> s<252> l<15:7> el<15:23>
+n<addrB> u<251> t<StringConst> p<252> l<15:24> el<15:29>
+n<> u<252> t<List_of_port_identifiers> p<253> c<251> l<15:24> el<15:29>
+n<> u<253> t<Input_declaration> p<254> c<250> l<15:1> el<15:29>
+n<> u<254> t<Port_declaration> p<255> c<253> l<15:1> el<15:29>
+n<> u<255> t<Module_item> p<940> c<254> s<278> l<15:1> el<15:30>
+n<WIDTHA> u<256> t<StringConst> p<257> l<16:8> el<16:14>
+n<> u<257> t<Primary_literal> p<258> c<256> l<16:8> el<16:14>
+n<> u<258> t<Constant_primary> p<259> c<257> l<16:8> el<16:14>
+n<> u<259> t<Constant_expression> p<265> c<258> s<264> l<16:8> el<16:14>
+n<1> u<260> t<IntConst> p<261> l<16:15> el<16:16>
+n<> u<261> t<Primary_literal> p<262> c<260> l<16:15> el<16:16>
+n<> u<262> t<Constant_primary> p<263> c<261> l<16:15> el<16:16>
+n<> u<263> t<Constant_expression> p<265> c<262> l<16:15> el<16:16>
+n<> u<264> t<BinOp_Minus> p<265> s<263> l<16:14> el<16:15>
+n<> u<265> t<Constant_expression> p<270> c<259> s<269> l<16:8> el<16:16>
+n<0> u<266> t<IntConst> p<267> l<16:17> el<16:18>
+n<> u<267> t<Primary_literal> p<268> c<266> l<16:17> el<16:18>
+n<> u<268> t<Constant_primary> p<269> c<267> l<16:17> el<16:18>
+n<> u<269> t<Constant_expression> p<270> c<268> l<16:17> el<16:18>
+n<> u<270> t<Constant_range> p<271> c<265> l<16:8> el<16:18>
+n<> u<271> t<Packed_dimension> p<272> c<270> l<16:7> el<16:19>
+n<> u<272> t<Data_type_or_implicit> p<273> c<271> l<16:7> el<16:19>
+n<> u<273> t<Net_port_type> p<276> c<272> s<275> l<16:7> el<16:19>
+n<diA> u<274> t<StringConst> p<275> l<16:20> el<16:23>
+n<> u<275> t<List_of_port_identifiers> p<276> c<274> l<16:20> el<16:23>
+n<> u<276> t<Input_declaration> p<277> c<273> l<16:1> el<16:23>
+n<> u<277> t<Port_declaration> p<278> c<276> l<16:1> el<16:23>
+n<> u<278> t<Module_item> p<940> c<277> s<301> l<16:1> el<16:24>
+n<WIDTHB> u<279> t<StringConst> p<280> l<17:8> el<17:14>
+n<> u<280> t<Primary_literal> p<281> c<279> l<17:8> el<17:14>
+n<> u<281> t<Constant_primary> p<282> c<280> l<17:8> el<17:14>
+n<> u<282> t<Constant_expression> p<288> c<281> s<287> l<17:8> el<17:14>
+n<1> u<283> t<IntConst> p<284> l<17:15> el<17:16>
+n<> u<284> t<Primary_literal> p<285> c<283> l<17:15> el<17:16>
+n<> u<285> t<Constant_primary> p<286> c<284> l<17:15> el<17:16>
+n<> u<286> t<Constant_expression> p<288> c<285> l<17:15> el<17:16>
+n<> u<287> t<BinOp_Minus> p<288> s<286> l<17:14> el<17:15>
+n<> u<288> t<Constant_expression> p<293> c<282> s<292> l<17:8> el<17:16>
+n<0> u<289> t<IntConst> p<290> l<17:17> el<17:18>
+n<> u<290> t<Primary_literal> p<291> c<289> l<17:17> el<17:18>
+n<> u<291> t<Constant_primary> p<292> c<290> l<17:17> el<17:18>
+n<> u<292> t<Constant_expression> p<293> c<291> l<17:17> el<17:18>
+n<> u<293> t<Constant_range> p<294> c<288> l<17:8> el<17:18>
+n<> u<294> t<Packed_dimension> p<295> c<293> l<17:7> el<17:19>
+n<> u<295> t<Data_type_or_implicit> p<296> c<294> l<17:7> el<17:19>
+n<> u<296> t<Net_port_type> p<299> c<295> s<298> l<17:7> el<17:19>
+n<diB> u<297> t<StringConst> p<298> l<17:20> el<17:23>
+n<> u<298> t<List_of_port_identifiers> p<299> c<297> l<17:20> el<17:23>
+n<> u<299> t<Input_declaration> p<300> c<296> l<17:1> el<17:23>
+n<> u<300> t<Port_declaration> p<301> c<299> l<17:1> el<17:23>
+n<> u<301> t<Module_item> p<940> c<300> s<324> l<17:1> el<17:24>
+n<WIDTHA> u<302> t<StringConst> p<303> l<18:9> el<18:15>
+n<> u<303> t<Primary_literal> p<304> c<302> l<18:9> el<18:15>
+n<> u<304> t<Constant_primary> p<305> c<303> l<18:9> el<18:15>
+n<> u<305> t<Constant_expression> p<311> c<304> s<310> l<18:9> el<18:15>
+n<1> u<306> t<IntConst> p<307> l<18:16> el<18:17>
+n<> u<307> t<Primary_literal> p<308> c<306> l<18:16> el<18:17>
+n<> u<308> t<Constant_primary> p<309> c<307> l<18:16> el<18:17>
+n<> u<309> t<Constant_expression> p<311> c<308> l<18:16> el<18:17>
+n<> u<310> t<BinOp_Minus> p<311> s<309> l<18:15> el<18:16>
+n<> u<311> t<Constant_expression> p<316> c<305> s<315> l<18:9> el<18:17>
+n<0> u<312> t<IntConst> p<313> l<18:18> el<18:19>
+n<> u<313> t<Primary_literal> p<314> c<312> l<18:18> el<18:19>
+n<> u<314> t<Constant_primary> p<315> c<313> l<18:18> el<18:19>
+n<> u<315> t<Constant_expression> p<316> c<314> l<18:18> el<18:19>
+n<> u<316> t<Constant_range> p<317> c<311> l<18:9> el<18:19>
+n<> u<317> t<Packed_dimension> p<318> c<316> l<18:8> el<18:20>
+n<> u<318> t<Data_type_or_implicit> p<319> c<317> l<18:8> el<18:20>
+n<> u<319> t<Net_port_type> p<322> c<318> s<321> l<18:8> el<18:20>
+n<doA> u<320> t<StringConst> p<321> l<18:21> el<18:24>
+n<> u<321> t<List_of_port_identifiers> p<322> c<320> l<18:21> el<18:24>
+n<> u<322> t<Output_declaration> p<323> c<319> l<18:1> el<18:24>
+n<> u<323> t<Port_declaration> p<324> c<322> l<18:1> el<18:24>
+n<> u<324> t<Module_item> p<940> c<323> s<347> l<18:1> el<18:25>
+n<WIDTHB> u<325> t<StringConst> p<326> l<19:9> el<19:15>
+n<> u<326> t<Primary_literal> p<327> c<325> l<19:9> el<19:15>
+n<> u<327> t<Constant_primary> p<328> c<326> l<19:9> el<19:15>
+n<> u<328> t<Constant_expression> p<334> c<327> s<333> l<19:9> el<19:15>
+n<1> u<329> t<IntConst> p<330> l<19:16> el<19:17>
+n<> u<330> t<Primary_literal> p<331> c<329> l<19:16> el<19:17>
+n<> u<331> t<Constant_primary> p<332> c<330> l<19:16> el<19:17>
+n<> u<332> t<Constant_expression> p<334> c<331> l<19:16> el<19:17>
+n<> u<333> t<BinOp_Minus> p<334> s<332> l<19:15> el<19:16>
+n<> u<334> t<Constant_expression> p<339> c<328> s<338> l<19:9> el<19:17>
+n<0> u<335> t<IntConst> p<336> l<19:18> el<19:19>
+n<> u<336> t<Primary_literal> p<337> c<335> l<19:18> el<19:19>
+n<> u<337> t<Constant_primary> p<338> c<336> l<19:18> el<19:19>
+n<> u<338> t<Constant_expression> p<339> c<337> l<19:18> el<19:19>
+n<> u<339> t<Constant_range> p<340> c<334> l<19:9> el<19:19>
+n<> u<340> t<Packed_dimension> p<341> c<339> l<19:8> el<19:20>
+n<> u<341> t<Data_type_or_implicit> p<342> c<340> l<19:8> el<19:20>
+n<> u<342> t<Net_port_type> p<345> c<341> s<344> l<19:8> el<19:20>
+n<doB> u<343> t<StringConst> p<344> l<19:21> el<19:24>
+n<> u<344> t<List_of_port_identifiers> p<345> c<343> l<19:21> el<19:24>
+n<> u<345> t<Output_declaration> p<346> c<342> l<19:1> el<19:24>
+n<> u<346> t<Port_declaration> p<347> c<345> l<19:1> el<19:24>
+n<> u<347> t<Module_item> p<940> c<346> s<541> l<19:1> el<19:25>
+n<> u<348> t<IntegerAtomType_Integer> p<349> l<24:10> el<24:17>
+n<> u<349> t<Data_type> p<350> c<348> l<24:10> el<24:17>
+n<> u<350> t<Function_data_type> p<351> c<349> l<24:10> el<24:17>
+n<> u<351> t<Function_data_type_or_implicit> p<534> c<350> s<352> l<24:10> el<24:17>
+n<log2> u<352> t<StringConst> p<534> s<360> l<24:18> el<24:22>
+n<> u<353> t<TfPortDir_Inp> p<359> s<356> l<25:1> el<25:6>
+n<> u<354> t<IntegerAtomType_Integer> p<355> l<25:7> el<25:14>
+n<> u<355> t<Data_type> p<356> c<354> l<25:7> el<25:14>
+n<> u<356> t<Data_type_or_implicit> p<359> c<355> s<358> l<25:7> el<25:14>
+n<value> u<357> t<StringConst> p<358> l<25:15> el<25:20>
+n<> u<358> t<List_of_tf_variable_identifiers> p<359> c<357> l<25:15> el<25:20>
+n<> u<359> t<Tf_port_declaration> p<360> c<353> l<25:1> el<25:21>
+n<> u<360> t<Tf_item_declaration> p<534> c<359> s<379> l<25:1> el<25:21>
+n<> u<361> t<IntVec_TypeReg> p<372> s<371> l<26:1> el<26:4>
+n<31> u<362> t<IntConst> p<363> l<26:6> el<26:8>
+n<> u<363> t<Primary_literal> p<364> c<362> l<26:6> el<26:8>
+n<> u<364> t<Constant_primary> p<365> c<363> l<26:6> el<26:8>
+n<> u<365> t<Constant_expression> p<370> c<364> s<369> l<26:6> el<26:8>
+n<0> u<366> t<IntConst> p<367> l<26:9> el<26:10>
+n<> u<367> t<Primary_literal> p<368> c<366> l<26:9> el<26:10>
+n<> u<368> t<Constant_primary> p<369> c<367> l<26:9> el<26:10>
+n<> u<369> t<Constant_expression> p<370> c<368> l<26:9> el<26:10>
+n<> u<370> t<Constant_range> p<371> c<365> l<26:6> el<26:10>
+n<> u<371> t<Packed_dimension> p<372> c<370> l<26:5> el<26:11>
+n<> u<372> t<Data_type> p<376> c<361> s<375> l<26:1> el<26:11>
+n<shifted> u<373> t<StringConst> p<374> l<26:12> el<26:19>
+n<> u<374> t<Variable_decl_assignment> p<375> c<373> l<26:12> el<26:19>
+n<> u<375> t<List_of_variable_decl_assignments> p<376> c<374> l<26:12> el<26:19>
+n<> u<376> t<Variable_declaration> p<377> c<372> l<26:1> el<26:20>
+n<> u<377> t<Data_declaration> p<378> c<376> l<26:1> el<26:20>
+n<> u<378> t<Block_item_declaration> p<379> c<377> l<26:1> el<26:20>
+n<> u<379> t<Tf_item_declaration> p<534> c<378> s<388> l<26:1> el<26:20>
+n<> u<380> t<IntegerAtomType_Integer> p<381> l<27:1> el<27:8>
+n<> u<381> t<Data_type> p<385> c<380> s<384> l<27:1> el<27:8>
+n<res> u<382> t<StringConst> p<383> l<27:9> el<27:12>
+n<> u<383> t<Variable_decl_assignment> p<384> c<382> l<27:9> el<27:12>
+n<> u<384> t<List_of_variable_decl_assignments> p<385> c<383> l<27:9> el<27:12>
+n<> u<385> t<Variable_declaration> p<386> c<381> l<27:1> el<27:13>
+n<> u<386> t<Data_declaration> p<387> c<385> l<27:1> el<27:13>
+n<> u<387> t<Block_item_declaration> p<388> c<386> l<27:1> el<27:13>
+n<> u<388> t<Tf_item_declaration> p<534> c<387> s<532> l<27:1> el<27:13>
+n<value> u<389> t<StringConst> p<390> l<29:9> el<29:14>
+n<> u<390> t<Primary_literal> p<391> c<389> l<29:9> el<29:14>
+n<> u<391> t<Primary> p<392> c<390> l<29:9> el<29:14>
+n<> u<392> t<Expression> p<398> c<391> s<397> l<29:9> el<29:14>
+n<2> u<393> t<IntConst> p<394> l<29:17> el<29:18>
+n<> u<394> t<Primary_literal> p<395> c<393> l<29:17> el<29:18>
+n<> u<395> t<Primary> p<396> c<394> l<29:17> el<29:18>
+n<> u<396> t<Expression> p<398> c<395> l<29:17> el<29:18>
+n<> u<397> t<BinOp_Less> p<398> s<396> l<29:15> el<29:16>
+n<> u<398> t<Expression> p<399> c<392> l<29:9> el<29:18>
+n<> u<399> t<Expression_or_cond_pattern> p<400> c<398> l<29:9> el<29:18>
+n<> u<400> t<Cond_predicate> p<524> c<399> s<415> l<29:9> el<29:18>
+n<log2> u<401> t<StringConst> p<402> l<30:9> el<30:13>
+n<> u<402> t<Ps_or_hierarchical_identifier> p<405> c<401> s<404> l<30:9> el<30:13>
+n<> u<403> t<Bit_select> p<404> l<30:14> el<30:14>
+n<> u<404> t<Select> p<405> c<403> l<30:14> el<30:14>
+n<> u<405> t<Variable_lvalue> p<411> c<402> s<406> l<30:9> el<30:13>
+n<> u<406> t<AssignOp_Assign> p<411> s<410> l<30:14> el<30:15>
+n<value> u<407> t<StringConst> p<408> l<30:16> el<30:21>
+n<> u<408> t<Primary_literal> p<409> c<407> l<30:16> el<30:21>
+n<> u<409> t<Primary> p<410> c<408> l<30:16> el<30:21>
+n<> u<410> t<Expression> p<411> c<409> l<30:16> el<30:21>
+n<> u<411> t<Operator_assignment> p<412> c<405> l<30:9> el<30:21>
+n<> u<412> t<Blocking_assignment> p<413> c<411> l<30:9> el<30:21>
+n<> u<413> t<Statement_item> p<414> c<412> l<30:9> el<30:22>
+n<> u<414> t<Statement> p<415> c<413> l<30:9> el<30:22>
+n<> u<415> t<Statement_or_null> p<524> c<414> s<523> l<30:9> el<30:22>
+n<shifted> u<416> t<StringConst> p<417> l<33:9> el<33:16>
+n<> u<417> t<Ps_or_hierarchical_identifier> p<420> c<416> s<419> l<33:9> el<33:16>
+n<> u<418> t<Bit_select> p<419> l<33:17> el<33:17>
+n<> u<419> t<Select> p<420> c<418> l<33:17> el<33:17>
+n<> u<420> t<Variable_lvalue> p<432> c<417> s<421> l<33:9> el<33:16>
+n<> u<421> t<AssignOp_Assign> p<432> s<431> l<33:17> el<33:18>
+n<value> u<422> t<StringConst> p<423> l<33:19> el<33:24>
+n<> u<423> t<Primary_literal> p<424> c<422> l<33:19> el<33:24>
+n<> u<424> t<Primary> p<425> c<423> l<33:19> el<33:24>
+n<> u<425> t<Expression> p<431> c<424> s<430> l<33:19> el<33:24>
+n<1> u<426> t<IntConst> p<427> l<33:25> el<33:26>
+n<> u<427> t<Primary_literal> p<428> c<426> l<33:25> el<33:26>
+n<> u<428> t<Primary> p<429> c<427> l<33:25> el<33:26>
+n<> u<429> t<Expression> p<431> c<428> l<33:25> el<33:26>
+n<> u<430> t<BinOp_Minus> p<431> s<429> l<33:24> el<33:25>
+n<> u<431> t<Expression> p<432> c<425> l<33:19> el<33:26>
+n<> u<432> t<Operator_assignment> p<433> c<420> l<33:9> el<33:26>
+n<> u<433> t<Blocking_assignment> p<434> c<432> l<33:9> el<33:26>
+n<> u<434> t<Statement_item> p<435> c<433> l<33:9> el<33:27>
+n<> u<435> t<Statement> p<436> c<434> l<33:9> el<33:27>
+n<> u<436> t<Statement_or_null> p<520> c<435> s<503> l<33:9> el<33:27>
+n<res> u<437> t<StringConst> p<438> l<34:18> el<34:21>
+n<> u<438> t<Ps_or_hierarchical_identifier> p<441> c<437> s<440> l<34:18> el<34:21>
+n<> u<439> t<Bit_select> p<440> l<34:21> el<34:21>
+n<> u<440> t<Select> p<441> c<439> l<34:21> el<34:21>
+n<> u<441> t<Variable_lvalue> p<446> c<438> s<445> l<34:18> el<34:21>
+n<0> u<442> t<IntConst> p<443> l<34:22> el<34:23>
+n<> u<443> t<Primary_literal> p<444> c<442> l<34:22> el<34:23>
+n<> u<444> t<Primary> p<445> c<443> l<34:22> el<34:23>
+n<> u<445> t<Expression> p<446> c<444> l<34:22> el<34:23>
+n<> u<446> t<Variable_assignment> p<447> c<441> l<34:18> el<34:23>
+n<> u<447> t<List_of_variable_assignments> p<448> c<446> l<34:18> el<34:23>
+n<> u<448> t<For_initialization> p<500> c<447> s<458> l<34:18> el<34:23>
+n<shifted> u<449> t<StringConst> p<450> l<34:25> el<34:32>
+n<> u<450> t<Primary_literal> p<451> c<449> l<34:25> el<34:32>
+n<> u<451> t<Primary> p<452> c<450> l<34:25> el<34:32>
+n<> u<452> t<Expression> p<458> c<451> s<457> l<34:25> el<34:32>
+n<0> u<453> t<IntConst> p<454> l<34:33> el<34:34>
+n<> u<454> t<Primary_literal> p<455> c<453> l<34:33> el<34:34>
+n<> u<455> t<Primary> p<456> c<454> l<34:33> el<34:34>
+n<> u<456> t<Expression> p<458> c<455> l<34:33> el<34:34>
+n<> u<457> t<BinOp_Great> p<458> s<456> l<34:32> el<34:33>
+n<> u<458> t<Expression> p<500> c<452> s<477> l<34:25> el<34:34>
+n<res> u<459> t<StringConst> p<460> l<34:36> el<34:39>
+n<> u<460> t<Ps_or_hierarchical_identifier> p<463> c<459> s<462> l<34:36> el<34:39>
+n<> u<461> t<Bit_select> p<462> l<34:39> el<34:39>
+n<> u<462> t<Select> p<463> c<461> l<34:39> el<34:39>
+n<> u<463> t<Variable_lvalue> p<475> c<460> s<464> l<34:36> el<34:39>
+n<> u<464> t<AssignOp_Assign> p<475> s<474> l<34:39> el<34:40>
+n<res> u<465> t<StringConst> p<466> l<34:40> el<34:43>
+n<> u<466> t<Primary_literal> p<467> c<465> l<34:40> el<34:43>
+n<> u<467> t<Primary> p<468> c<466> l<34:40> el<34:43>
+n<> u<468> t<Expression> p<474> c<467> s<473> l<34:40> el<34:43>
+n<1> u<469> t<IntConst> p<470> l<34:44> el<34:45>
+n<> u<470> t<Primary_literal> p<471> c<469> l<34:44> el<34:45>
+n<> u<471> t<Primary> p<472> c<470> l<34:44> el<34:45>
+n<> u<472> t<Expression> p<474> c<471> l<34:44> el<34:45>
+n<> u<473> t<BinOp_Plus> p<474> s<472> l<34:43> el<34:44>
+n<> u<474> t<Expression> p<475> c<468> l<34:40> el<34:45>
+n<> u<475> t<Operator_assignment> p<476> c<463> l<34:36> el<34:45>
+n<> u<476> t<For_step_assignment> p<477> c<475> l<34:36> el<34:45>
+n<> u<477> t<For_step> p<500> c<476> s<498> l<34:36> el<34:45>
+n<shifted> u<478> t<StringConst> p<479> l<35:17> el<35:24>
+n<> u<479> t<Ps_or_hierarchical_identifier> p<482> c<478> s<481> l<35:17> el<35:24>
+n<> u<480> t<Bit_select> p<481> l<35:25> el<35:25>
+n<> u<481> t<Select> p<482> c<480> l<35:25> el<35:25>
+n<> u<482> t<Variable_lvalue> p<494> c<479> s<483> l<35:17> el<35:24>
+n<> u<483> t<AssignOp_Assign> p<494> s<493> l<35:25> el<35:26>
+n<shifted> u<484> t<StringConst> p<485> l<35:27> el<35:34>
+n<> u<485> t<Primary_literal> p<486> c<484> l<35:27> el<35:34>
+n<> u<486> t<Primary> p<487> c<485> l<35:27> el<35:34>
+n<> u<487> t<Expression> p<493> c<486> s<492> l<35:27> el<35:34>
+n<1> u<488> t<IntConst> p<489> l<35:36> el<35:37>
+n<> u<489> t<Primary_literal> p<490> c<488> l<35:36> el<35:37>
+n<> u<490> t<Primary> p<491> c<489> l<35:36> el<35:37>
+n<> u<491> t<Expression> p<493> c<490> l<35:36> el<35:37>
+n<> u<492> t<BinOp_ShiftRight> p<493> s<491> l<35:34> el<35:36>
+n<> u<493> t<Expression> p<494> c<487> l<35:27> el<35:37>
+n<> u<494> t<Operator_assignment> p<495> c<482> l<35:17> el<35:37>
+n<> u<495> t<Blocking_assignment> p<496> c<494> l<35:17> el<35:37>
+n<> u<496> t<Statement_item> p<497> c<495> l<35:17> el<35:38>
+n<> u<497> t<Statement> p<498> c<496> l<35:17> el<35:38>
+n<> u<498> t<Statement_or_null> p<500> c<497> l<35:17> el<35:38>
+n<> u<499> t<FOR> p<500> s<448> l<34:13> el<34:16>
+n<> u<500> t<Loop_statement> p<501> c<499> l<34:13> el<35:38>
+n<> u<501> t<Statement_item> p<502> c<500> l<34:13> el<35:38>
+n<> u<502> t<Statement> p<503> c<501> l<34:13> el<35:38>
+n<> u<503> t<Statement_or_null> p<520> c<502> s<518> l<34:13> el<35:38>
+n<log2> u<504> t<StringConst> p<505> l<36:17> el<36:21>
+n<> u<505> t<Ps_or_hierarchical_identifier> p<508> c<504> s<507> l<36:17> el<36:21>
+n<> u<506> t<Bit_select> p<507> l<36:22> el<36:22>
+n<> u<507> t<Select> p<508> c<506> l<36:22> el<36:22>
+n<> u<508> t<Variable_lvalue> p<514> c<505> s<509> l<36:17> el<36:21>
+n<> u<509> t<AssignOp_Assign> p<514> s<513> l<36:22> el<36:23>
+n<res> u<510> t<StringConst> p<511> l<36:24> el<36:27>
+n<> u<511> t<Primary_literal> p<512> c<510> l<36:24> el<36:27>
+n<> u<512> t<Primary> p<513> c<511> l<36:24> el<36:27>
+n<> u<513> t<Expression> p<514> c<512> l<36:24> el<36:27>
+n<> u<514> t<Operator_assignment> p<515> c<508> l<36:17> el<36:27>
+n<> u<515> t<Blocking_assignment> p<516> c<514> l<36:17> el<36:27>
+n<> u<516> t<Statement_item> p<517> c<515> l<36:17> el<36:28>
+n<> u<517> t<Statement> p<518> c<516> l<36:17> el<36:28>
+n<> u<518> t<Statement_or_null> p<520> c<517> s<519> l<36:17> el<36:28>
+n<> u<519> t<END> p<520> l<37:5> el<37:8>
+n<> u<520> t<Seq_block> p<521> c<436> l<32:5> el<37:8>
+n<> u<521> t<Statement_item> p<522> c<520> l<32:5> el<37:8>
+n<> u<522> t<Statement> p<523> c<521> l<32:5> el<37:8>
+n<> u<523> t<Statement_or_null> p<524> c<522> l<32:5> el<37:8>
+n<> u<524> t<Conditional_statement> p<525> c<400> l<29:5> el<37:8>
+n<> u<525> t<Statement_item> p<526> c<524> l<29:5> el<37:8>
+n<> u<526> t<Statement> p<527> c<525> l<29:5> el<37:8>
+n<> u<527> t<Statement_or_null> p<529> c<526> s<528> l<29:5> el<37:8>
+n<> u<528> t<END> p<529> l<38:1> el<38:4>
+n<> u<529> t<Seq_block> p<530> c<527> l<28:1> el<38:4>
+n<> u<530> t<Statement_item> p<531> c<529> l<28:1> el<38:4>
+n<> u<531> t<Statement> p<532> c<530> l<28:1> el<38:4>
+n<> u<532> t<Function_statement_or_null> p<534> c<531> s<533> l<28:1> el<38:4>
+n<> u<533> t<ENDFUNCTION> p<534> l<39:1> el<39:12>
+n<> u<534> t<Function_body_declaration> p<535> c<351> l<24:10> el<39:12>
+n<> u<535> t<Function_declaration> p<536> c<534> l<24:1> el<39:12>
+n<> u<536> t<Package_or_generate_item_declaration> p<537> c<535> l<24:1> el<39:12>
+n<> u<537> t<Module_or_generate_item_declaration> p<538> c<536> l<24:1> el<39:12>
+n<> u<538> t<Module_common_item> p<539> c<537> l<24:1> el<39:12>
+n<> u<539> t<Module_or_generate_item> p<540> c<538> l<24:1> el<39:12>
+n<> u<540> t<Non_port_module_item> p<541> c<539> l<24:1> el<39:12>
+n<> u<541> t<Module_item> p<940> c<540> s<584> l<24:1> el<39:12>
+n<> u<542> t<Data_type_or_implicit> p<578> s<577> l<41:12> el<41:12>
+n<maxSIZE> u<543> t<StringConst> p<576> s<575> l<41:12> el<41:19>
+n<SIZEA> u<544> t<StringConst> p<545> l<41:24> el<41:29>
+n<> u<545> t<Primary_literal> p<546> c<544> l<41:24> el<41:29>
+n<> u<546> t<Constant_primary> p<547> c<545> l<41:24> el<41:29>
+n<> u<547> t<Constant_expression> p<548> c<546> l<41:24> el<41:29>
+n<> u<548> t<Constant_primary> p<549> c<547> l<41:23> el<41:30>
+n<> u<549> t<Constant_expression> p<557> c<548> s<556> l<41:23> el<41:30>
+n<SIZEB> u<550> t<StringConst> p<551> l<41:34> el<41:39>
+n<> u<551> t<Primary_literal> p<552> c<550> l<41:34> el<41:39>
+n<> u<552> t<Constant_primary> p<553> c<551> l<41:34> el<41:39>
+n<> u<553> t<Constant_expression> p<554> c<552> l<41:34> el<41:39>
+n<> u<554> t<Constant_primary> p<555> c<553> l<41:33> el<41:40>
+n<> u<555> t<Constant_expression> p<557> c<554> l<41:33> el<41:40>
+n<> u<556> t<BinOp_Great> p<557> s<555> l<41:31> el<41:32>
+n<> u<557> t<Constant_expression> p<570> c<549> s<558> l<41:23> el<41:40>
+n<> u<558> t<Conditional_operator> p<570> s<563> l<41:41> el<41:42>
+n<SIZEA> u<559> t<StringConst> p<560> l<41:44> el<41:49>
+n<> u<560> t<Primary_literal> p<561> c<559> l<41:44> el<41:49>
+n<> u<561> t<Primary> p<562> c<560> l<41:44> el<41:49>
+n<> u<562> t<Expression> p<563> c<561> l<41:44> el<41:49>
+n<> u<563> t<Expression> p<570> c<562> s<569> l<41:43> el<41:50>
+n<SIZEB> u<564> t<StringConst> p<565> l<41:54> el<41:59>
+n<> u<565> t<Primary_literal> p<566> c<564> l<41:54> el<41:59>
+n<> u<566> t<Constant_primary> p<567> c<565> l<41:54> el<41:59>
+n<> u<567> t<Constant_expression> p<568> c<566> l<41:54> el<41:59>
+n<> u<568> t<Constant_primary> p<569> c<567> l<41:53> el<41:60>
+n<> u<569> t<Constant_expression> p<570> c<568> l<41:53> el<41:60>
+n<> u<570> t<Constant_expression> p<571> c<557> l<41:23> el<41:60>
+n<> u<571> t<Constant_concatenation> p<572> c<570> l<41:22> el<41:61>
+n<> u<572> t<Constant_primary> p<573> c<571> l<41:22> el<41:61>
+n<> u<573> t<Constant_expression> p<574> c<572> l<41:22> el<41:61>
+n<> u<574> t<Constant_mintypmax_expression> p<575> c<573> l<41:22> el<41:61>
+n<> u<575> t<Constant_param_expression> p<576> c<574> l<41:22> el<41:61>
+n<> u<576> t<Param_assignment> p<577> c<543> l<41:12> el<41:61>
+n<> u<577> t<List_of_param_assignments> p<578> c<576> l<41:12> el<41:61>
+n<> u<578> t<Local_parameter_declaration> p<579> c<542> l<41:1> el<41:61>
+n<> u<579> t<Package_or_generate_item_declaration> p<580> c<578> l<41:1> el<41:62>
+n<> u<580> t<Module_or_generate_item_declaration> p<581> c<579> l<41:1> el<41:62>
+n<> u<581> t<Module_common_item> p<582> c<580> l<41:1> el<41:62>
+n<> u<582> t<Module_or_generate_item> p<583> c<581> l<41:1> el<41:62>
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+n<> u<584> t<Module_item> p<940> c<583> s<627> l<41:1> el<41:62>
+n<> u<585> t<Data_type_or_implicit> p<621> s<620> l<42:12> el<42:12>
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+n<WIDTHA> u<587> t<StringConst> p<588> l<42:25> el<42:31>
+n<> u<588> t<Primary_literal> p<589> c<587> l<42:25> el<42:31>
+n<> u<589> t<Constant_primary> p<590> c<588> l<42:25> el<42:31>
+n<> u<590> t<Constant_expression> p<591> c<589> l<42:25> el<42:31>
+n<> u<591> t<Constant_primary> p<592> c<590> l<42:24> el<42:32>
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+n<> u<594> t<Primary_literal> p<595> c<593> l<42:36> el<42:42>
+n<> u<595> t<Constant_primary> p<596> c<594> l<42:36> el<42:42>
+n<> u<596> t<Constant_expression> p<597> c<595> l<42:36> el<42:42>
+n<> u<597> t<Constant_primary> p<598> c<596> l<42:35> el<42:43>
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+n<> u<599> t<BinOp_Great> p<600> s<598> l<42:33> el<42:34>
+n<> u<600> t<Constant_expression> p<613> c<592> s<601> l<42:24> el<42:43>
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+n<> u<603> t<Primary_literal> p<604> c<602> l<42:47> el<42:53>
+n<> u<604> t<Primary> p<605> c<603> l<42:47> el<42:53>
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+n<> u<608> t<Primary_literal> p<609> c<607> l<42:58> el<42:64>
+n<> u<609> t<Constant_primary> p<610> c<608> l<42:58> el<42:64>
+n<> u<610> t<Constant_expression> p<611> c<609> l<42:58> el<42:64>
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+n<> u<614> t<Constant_concatenation> p<615> c<613> l<42:23> el<42:66>
+n<> u<615> t<Constant_primary> p<616> c<614> l<42:23> el<42:66>
+n<> u<616> t<Constant_expression> p<617> c<615> l<42:23> el<42:66>
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+n<> u<621> t<Local_parameter_declaration> p<622> c<585> l<42:1> el<42:66>
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+n<> u<633> t<Constant_expression> p<634> c<632> l<43:25> el<43:31>
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+n<> u<644> t<Conditional_operator> p<656> s<649> l<43:44> el<43:45>
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+n<> u<651> t<Primary_literal> p<652> c<650> l<43:58> el<43:64>
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+n<> u<653> t<Constant_expression> p<654> c<652> l<43:58> el<43:64>
+n<> u<654> t<Constant_primary> p<655> c<653> l<43:57> el<43:65>
+n<> u<655> t<Constant_expression> p<656> c<654> l<43:57> el<43:65>
+n<> u<656> t<Constant_expression> p<657> c<643> l<43:24> el<43:65>
+n<> u<657> t<Constant_concatenation> p<658> c<656> l<43:23> el<43:66>
+n<> u<658> t<Constant_primary> p<659> c<657> l<43:23> el<43:66>
+n<> u<659> t<Constant_expression> p<660> c<658> l<43:23> el<43:66>
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+n<> u<661> t<Constant_param_expression> p<662> c<660> l<43:23> el<43:66>
+n<> u<662> t<Param_assignment> p<663> c<629> l<43:12> el<43:66>
+n<> u<663> t<List_of_param_assignments> p<664> c<662> l<43:12> el<43:66>
+n<> u<664> t<Local_parameter_declaration> p<665> c<628> l<43:1> el<43:66>
+n<> u<665> t<Package_or_generate_item_declaration> p<666> c<664> l<43:1> el<43:67>
+n<> u<666> t<Module_or_generate_item_declaration> p<667> c<665> l<43:1> el<43:67>
+n<> u<667> t<Module_common_item> p<668> c<666> l<43:1> el<43:67>
+n<> u<668> t<Module_or_generate_item> p<669> c<667> l<43:1> el<43:67>
+n<> u<669> t<Non_port_module_item> p<670> c<668> l<43:1> el<43:67>
+n<> u<670> t<Module_item> p<940> c<669> s<693> l<43:1> el<43:67>
+n<> u<671> t<Data_type_or_implicit> p<687> s<686> l<44:12> el<44:12>
+n<RATIO> u<672> t<StringConst> p<685> s<684> l<44:12> el<44:17>
+n<maxWIDTH> u<673> t<StringConst> p<674> l<44:20> el<44:28>
+n<> u<674> t<Primary_literal> p<675> c<673> l<44:20> el<44:28>
+n<> u<675> t<Constant_primary> p<676> c<674> l<44:20> el<44:28>
+n<> u<676> t<Constant_expression> p<682> c<675> s<681> l<44:20> el<44:28>
+n<minWIDTH> u<677> t<StringConst> p<678> l<44:31> el<44:39>
+n<> u<678> t<Primary_literal> p<679> c<677> l<44:31> el<44:39>
+n<> u<679> t<Constant_primary> p<680> c<678> l<44:31> el<44:39>
+n<> u<680> t<Constant_expression> p<682> c<679> l<44:31> el<44:39>
+n<> u<681> t<BinOp_Div> p<682> s<680> l<44:29> el<44:30>
+n<> u<682> t<Constant_expression> p<683> c<676> l<44:20> el<44:39>
+n<> u<683> t<Constant_mintypmax_expression> p<684> c<682> l<44:20> el<44:39>
+n<> u<684> t<Constant_param_expression> p<685> c<683> l<44:20> el<44:39>
+n<> u<685> t<Param_assignment> p<686> c<672> l<44:12> el<44:39>
+n<> u<686> t<List_of_param_assignments> p<687> c<685> l<44:12> el<44:39>
+n<> u<687> t<Local_parameter_declaration> p<688> c<671> l<44:1> el<44:39>
+n<> u<688> t<Package_or_generate_item_declaration> p<689> c<687> l<44:1> el<44:40>
+n<> u<689> t<Module_or_generate_item_declaration> p<690> c<688> l<44:1> el<44:40>
+n<> u<690> t<Module_common_item> p<691> c<689> l<44:1> el<44:40>
+n<> u<691> t<Module_or_generate_item> p<692> c<690> l<44:1> el<44:40>
+n<> u<692> t<Non_port_module_item> p<693> c<691> l<44:1> el<44:40>
+n<> u<693> t<Module_item> p<940> c<692> s<715> l<44:1> el<44:40>
+n<> u<694> t<Data_type_or_implicit> p<709> s<708> l<45:12> el<45:12>
+n<log2RATIO> u<695> t<StringConst> p<707> s<706> l<45:12> el<45:21>
+n<log2> u<696> t<StringConst> p<702> s<701> l<45:24> el<45:28>
+n<RATIO> u<697> t<StringConst> p<698> l<45:29> el<45:34>
+n<> u<698> t<Primary_literal> p<699> c<697> l<45:29> el<45:34>
+n<> u<699> t<Primary> p<700> c<698> l<45:29> el<45:34>
+n<> u<700> t<Expression> p<701> c<699> l<45:29> el<45:34>
+n<> u<701> t<List_of_arguments> p<702> c<700> l<45:29> el<45:34>
+n<> u<702> t<Subroutine_call> p<703> c<696> l<45:24> el<45:35>
+n<> u<703> t<Constant_primary> p<704> c<702> l<45:24> el<45:35>
+n<> u<704> t<Constant_expression> p<705> c<703> l<45:24> el<45:35>
+n<> u<705> t<Constant_mintypmax_expression> p<706> c<704> l<45:24> el<45:35>
+n<> u<706> t<Constant_param_expression> p<707> c<705> l<45:24> el<45:35>
+n<> u<707> t<Param_assignment> p<708> c<695> l<45:12> el<45:35>
+n<> u<708> t<List_of_param_assignments> p<709> c<707> l<45:12> el<45:35>
+n<> u<709> t<Local_parameter_declaration> p<710> c<694> l<45:1> el<45:35>
+n<> u<710> t<Package_or_generate_item_declaration> p<711> c<709> l<45:1> el<45:36>
+n<> u<711> t<Module_or_generate_item_declaration> p<712> c<710> l<45:1> el<45:36>
+n<> u<712> t<Module_common_item> p<713> c<711> l<45:1> el<45:36>
+n<> u<713> t<Module_or_generate_item> p<714> c<712> l<45:1> el<45:36>
+n<> u<714> t<Non_port_module_item> p<715> c<713> l<45:1> el<45:36>
+n<> u<715> t<Module_item> p<940> c<714> s<761> l<45:1> el<45:36>
+n<> u<716> t<IntVec_TypeReg> p<733> s<732> l<47:1> el<47:4>
+n<minWIDTH> u<717> t<StringConst> p<718> l<47:6> el<47:14>
+n<> u<718> t<Primary_literal> p<719> c<717> l<47:6> el<47:14>
+n<> u<719> t<Constant_primary> p<720> c<718> l<47:6> el<47:14>
+n<> u<720> t<Constant_expression> p<726> c<719> s<725> l<47:6> el<47:14>
+n<1> u<721> t<IntConst> p<722> l<47:15> el<47:16>
+n<> u<722> t<Primary_literal> p<723> c<721> l<47:15> el<47:16>
+n<> u<723> t<Constant_primary> p<724> c<722> l<47:15> el<47:16>
+n<> u<724> t<Constant_expression> p<726> c<723> l<47:15> el<47:16>
+n<> u<725> t<BinOp_Minus> p<726> s<724> l<47:14> el<47:15>
+n<> u<726> t<Constant_expression> p<731> c<720> s<730> l<47:6> el<47:16>
+n<0> u<727> t<IntConst> p<728> l<47:17> el<47:18>
+n<> u<728> t<Primary_literal> p<729> c<727> l<47:17> el<47:18>
+n<> u<729> t<Constant_primary> p<730> c<728> l<47:17> el<47:18>
+n<> u<730> t<Constant_expression> p<731> c<729> l<47:17> el<47:18>
+n<> u<731> t<Constant_range> p<732> c<726> l<47:6> el<47:18>
+n<> u<732> t<Packed_dimension> p<733> c<731> l<47:5> el<47:19>
+n<> u<733> t<Data_type> p<754> c<716> s<753> l<47:1> el<47:19>
+n<RAM> u<734> t<StringConst> p<752> s<751> l<47:20> el<47:23>
+n<0> u<735> t<IntConst> p<736> l<47:25> el<47:26>
+n<> u<736> t<Primary_literal> p<737> c<735> l<47:25> el<47:26>
+n<> u<737> t<Constant_primary> p<738> c<736> l<47:25> el<47:26>
+n<> u<738> t<Constant_expression> p<749> c<737> s<748> l<47:25> el<47:26>
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+n<> u<740> t<Primary_literal> p<741> c<739> l<47:27> el<47:34>
+n<> u<741> t<Constant_primary> p<742> c<740> l<47:27> el<47:34>
+n<> u<742> t<Constant_expression> p<748> c<741> s<747> l<47:27> el<47:34>
+n<1> u<743> t<IntConst> p<744> l<47:35> el<47:36>
+n<> u<744> t<Primary_literal> p<745> c<743> l<47:35> el<47:36>
+n<> u<745> t<Constant_primary> p<746> c<744> l<47:35> el<47:36>
+n<> u<746> t<Constant_expression> p<748> c<745> l<47:35> el<47:36>
+n<> u<747> t<BinOp_Minus> p<748> s<746> l<47:34> el<47:35>
+n<> u<748> t<Constant_expression> p<749> c<742> l<47:27> el<47:36>
+n<> u<749> t<Constant_range> p<750> c<738> l<47:25> el<47:36>
+n<> u<750> t<Unpacked_dimension> p<751> c<749> l<47:24> el<47:37>
+n<> u<751> t<Variable_dimension> p<752> c<750> l<47:24> el<47:37>
+n<> u<752> t<Variable_decl_assignment> p<753> c<734> l<47:20> el<47:37>
+n<> u<753> t<List_of_variable_decl_assignments> p<754> c<752> l<47:20> el<47:37>
+n<> u<754> t<Variable_declaration> p<755> c<733> l<47:1> el<47:38>
+n<> u<755> t<Data_declaration> p<756> c<754> l<47:1> el<47:38>
+n<> u<756> t<Package_or_generate_item_declaration> p<757> c<755> l<47:1> el<47:38>
+n<> u<757> t<Module_or_generate_item_declaration> p<758> c<756> l<47:1> el<47:38>
+n<> u<758> t<Module_common_item> p<759> c<757> l<47:1> el<47:38>
+n<> u<759> t<Module_or_generate_item> p<760> c<758> l<47:1> el<47:38>
+n<> u<760> t<Non_port_module_item> p<761> c<759> l<47:1> el<47:38>
+n<> u<761> t<Module_item> p<940> c<760> s<790> l<47:1> el<47:38>
+n<> u<762> t<IntVec_TypeReg> p<779> s<778> l<48:1> el<48:4>
+n<WIDTHA> u<763> t<StringConst> p<764> l<48:6> el<48:12>
+n<> u<764> t<Primary_literal> p<765> c<763> l<48:6> el<48:12>
+n<> u<765> t<Constant_primary> p<766> c<764> l<48:6> el<48:12>
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+n<> u<768> t<Primary_literal> p<769> c<767> l<48:13> el<48:14>
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+n<> u<770> t<Constant_expression> p<772> c<769> l<48:13> el<48:14>
+n<> u<771> t<BinOp_Minus> p<772> s<770> l<48:12> el<48:13>
+n<> u<772> t<Constant_expression> p<777> c<766> s<776> l<48:6> el<48:14>
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+n<> u<774> t<Primary_literal> p<775> c<773> l<48:15> el<48:16>
+n<> u<775> t<Constant_primary> p<776> c<774> l<48:15> el<48:16>
+n<> u<776> t<Constant_expression> p<777> c<775> l<48:15> el<48:16>
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+n<> u<778> t<Packed_dimension> p<779> c<777> l<48:5> el<48:17>
+n<> u<779> t<Data_type> p<783> c<762> s<782> l<48:1> el<48:17>
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+n<> u<782> t<List_of_variable_decl_assignments> p<783> c<781> l<48:18> el<48:23>
+n<> u<783> t<Variable_declaration> p<784> c<779> l<48:1> el<48:24>
+n<> u<784> t<Data_declaration> p<785> c<783> l<48:1> el<48:24>
+n<> u<785> t<Package_or_generate_item_declaration> p<786> c<784> l<48:1> el<48:24>
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+n<> u<793> t<Primary_literal> p<794> c<792> l<49:6> el<49:12>
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+n<> u<883> t<Statement> p<884> c<882> l<56:9> el<56:29>
+n<> u<884> t<Statement_or_null> p<886> c<883> s<885> l<56:9> el<56:29>
+n<> u<885> t<END> p<886> l<57:5> el<57:8>
+n<> u<886> t<Seq_block> p<887> c<863> l<53:5> el<57:8>
+n<> u<887> t<Statement_item> p<888> c<886> l<53:5> el<57:8>
+n<> u<888> t<Statement> p<889> c<887> l<53:5> el<57:8>
+n<> u<889> t<Statement_or_null> p<890> c<888> l<53:5> el<57:8>
+n<> u<890> t<Conditional_statement> p<891> c<834> l<52:5> el<57:8>
+n<> u<891> t<Statement_item> p<892> c<890> l<52:5> el<57:8>
+n<> u<892> t<Statement> p<893> c<891> l<52:5> el<57:8>
+n<> u<893> t<Statement_or_null> p<895> c<892> s<894> l<52:5> el<57:8>
+n<> u<894> t<END> p<895> l<58:1> el<58:4>
+n<> u<895> t<Seq_block> p<896> c<893> l<51:1> el<58:4>
+n<> u<896> t<Statement_item> p<897> c<895> l<51:1> el<58:4>
+n<> u<897> t<Statement> p<898> c<896> l<51:1> el<58:4>
+n<> u<898> t<Statement_or_null> p<899> c<897> l<51:1> el<58:4>
+n<> u<899> t<Procedural_timing_control_statement> p<900> c<828> l<50:8> el<58:4>
+n<> u<900> t<Statement_item> p<901> c<899> l<50:8> el<58:4>
+n<> u<901> t<Statement> p<902> c<900> l<50:8> el<58:4>
+n<> u<902> t<Always_construct> p<903> c<820> l<50:1> el<58:4>
+n<> u<903> t<Module_common_item> p<904> c<902> l<50:1> el<58:4>
+n<> u<904> t<Module_or_generate_item> p<905> c<903> l<50:1> el<58:4>
+n<> u<905> t<Non_port_module_item> p<906> c<904> l<50:1> el<58:4>
+n<> u<906> t<Module_item> p<940> c<905> s<922> l<50:1> el<58:4>
+n<doA> u<907> t<StringConst> p<908> l<76:8> el<76:11>
+n<> u<908> t<Ps_or_hierarchical_identifier> p<911> c<907> s<910> l<76:8> el<76:11>
+n<> u<909> t<Constant_bit_select> p<910> l<76:12> el<76:12>
+n<> u<910> t<Constant_select> p<911> c<909> l<76:12> el<76:12>
+n<> u<911> t<Net_lvalue> p<916> c<908> s<915> l<76:8> el<76:11>
+n<readA> u<912> t<StringConst> p<913> l<76:14> el<76:19>
+n<> u<913> t<Primary_literal> p<914> c<912> l<76:14> el<76:19>
+n<> u<914> t<Primary> p<915> c<913> l<76:14> el<76:19>
+n<> u<915> t<Expression> p<916> c<914> l<76:14> el<76:19>
+n<> u<916> t<Net_assignment> p<917> c<911> l<76:8> el<76:19>
+n<> u<917> t<List_of_net_assignments> p<918> c<916> l<76:8> el<76:19>
+n<> u<918> t<Continuous_assign> p<919> c<917> l<76:1> el<76:20>
+n<> u<919> t<Module_common_item> p<920> c<918> l<76:1> el<76:20>
+n<> u<920> t<Module_or_generate_item> p<921> c<919> l<76:1> el<76:20>
+n<> u<921> t<Non_port_module_item> p<922> c<920> l<76:1> el<76:20>
+n<> u<922> t<Module_item> p<940> c<921> s<938> l<76:1> el<76:20>
+n<doB> u<923> t<StringConst> p<924> l<77:8> el<77:11>
+n<> u<924> t<Ps_or_hierarchical_identifier> p<927> c<923> s<926> l<77:8> el<77:11>
+n<> u<925> t<Constant_bit_select> p<926> l<77:12> el<77:12>
+n<> u<926> t<Constant_select> p<927> c<925> l<77:12> el<77:12>
+n<> u<927> t<Net_lvalue> p<932> c<924> s<931> l<77:8> el<77:11>
+n<readB> u<928> t<StringConst> p<929> l<77:14> el<77:19>
+n<> u<929> t<Primary_literal> p<930> c<928> l<77:14> el<77:19>
+n<> u<930> t<Primary> p<931> c<929> l<77:14> el<77:19>
+n<> u<931> t<Expression> p<932> c<930> l<77:14> el<77:19>
+n<> u<932> t<Net_assignment> p<933> c<927> l<77:8> el<77:19>
+n<> u<933> t<List_of_net_assignments> p<934> c<932> l<77:8> el<77:19>
+n<> u<934> t<Continuous_assign> p<935> c<933> l<77:1> el<77:20>
+n<> u<935> t<Module_common_item> p<936> c<934> l<77:1> el<77:20>
+n<> u<936> t<Module_or_generate_item> p<937> c<935> l<77:1> el<77:20>
+n<> u<937> t<Non_port_module_item> p<938> c<936> l<77:1> el<77:20>
+n<> u<938> t<Module_item> p<940> c<937> s<939> l<77:1> el<77:20>
+n<> u<939> t<ENDMODULE> p<940> l<79:1> el<79:10>
+n<> u<940> t<Module_declaration> p<941> c<77> l<1:1> el<79:10>
+n<> u<941> t<Description> p<942> c<940> l<1:1> el<79:10>
+n<> u<942> t<Source_text> p<943> c<941> l<1:1> el<79:10>
+n<> u<943> t<Top_level_rule> c<1> l<1:1> el<80:1>
+AST_DEBUG_END
+[INF:CP0300] Compilation...
+[INF:CP0303] ${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv:1:1: Compile module "work@asym_ram_tdp_write_first_dc".
+[NTE:CP0309] ${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv:1:90: Implicit port type (wire) for "doA",
+there are 1 more instances of this message.
+[INF:EL0526] Design Elaboration...
+[NTE:EL0503] ${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv:1:1: Top level module "work@asym_ram_tdp_write_first_dc".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 1.
+[NTE:EL0510] Nb instances: 1.
+[NTE:EL0511] Nb leaf instances: 0.
+[INF:UH0706] Creating UHDM Model...
+=== UHDM Object Stats Begin (Non-Elaborated Model) ===
+always                                                 1
+array_net                                              1
+assignment                                             8
+begin                                                  4
+bit_select                                             2
+constant                                             181
+cont_assign                                            2
+design                                                 1
+event_control                                          1
+for_stmt                                               1
+func_call                                              2
+function                                               1
+if_else                                                1
+if_stmt                                                2
+int_typespec                                          12
+integer_typespec                                       6
+integer_var                                            4
+io_decl                                                1
+logic_net                                             30
+logic_typespec                                        40
+logic_var                                              2
+module_inst                                            6
+operation                                             57
+param_assign                                          30
+parameter                                             30
+port                                                  24
+range                                                 37
+ref_obj                                               71
+ref_typespec                                          80
+ref_var                                                1
+=== UHDM Object Stats End ===
+[INF:UH0707] Elaborating UHDM...
+=== UHDM Object Stats Begin (Elaborated Model) ===
+always                                                 2
+array_net                                              1
+assignment                                            16
+begin                                                  8
+bit_select                                             4
+constant                                             181
+cont_assign                                            4
+design                                                 1
+event_control                                          2
+for_stmt                                               2
+func_call                                              2
+function                                               2
+if_else                                                2
+if_stmt                                                4
+int_typespec                                          12
+integer_typespec                                       6
+integer_var                                            5
+io_decl                                                2
+logic_net                                             30
+logic_typespec                                        40
+logic_var                                              3
+module_inst                                            6
+operation                                             63
+param_assign                                          30
+parameter                                             30
+port                                                  36
+range                                                 37
+ref_obj                                              106
+ref_typespec                                          95
+ref_var                                                2
+=== UHDM Object Stats End ===
+Converting blocking to non-blocking assignment to enable RAM inference for RAM
+Converting blocking to non-blocking assignment to enable RAM inference for RAM
+[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/surelog.uhdm ...
+[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/checker/surelog.chk.html ...
+[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/surelog.uhdm ...
+[INF:UH0711] Decompiling UHDM...
+====== UHDM =======
+design: (work@asym_ram_tdp_write_first_dc)
+|vpiElaborated:1
+|vpiName:work@asym_ram_tdp_write_first_dc
+|uhdmallModules:
+\_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiParent:
+  \_design: (work@asym_ram_tdp_write_first_dc)
+  |vpiFullName:work@asym_ram_tdp_write_first_dc
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:3:11, endln:3:17
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:4
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.WIDTHB)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:3:11, endln:3:17
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+      |vpiActual:
+      \_int_typespec: , line:3:1, endln:3:21
+    |vpiName:WIDTHB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEB), line:4:11, endln:4:16
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:1024
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.SIZEB)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEB), line:4:11, endln:4:16
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEB
+      |vpiActual:
+      \_int_typespec: , line:4:1, endln:4:23
+    |vpiName:SIZEB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEB
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB), line:5:11, endln:5:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB), line:5:11, endln:5:21
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHB
+      |vpiActual:
+      \_int_typespec: , line:5:1, endln:5:26
+    |vpiName:ADDRWIDTHB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHB
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:6:11, endln:6:17
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:16
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.WIDTHA)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:6:11, endln:6:17
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+      |vpiActual:
+      \_int_typespec: , line:6:1, endln:6:22
+    |vpiName:WIDTHA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEA), line:7:11, endln:7:16
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:256
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.SIZEA)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEA), line:7:11, endln:7:16
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEA
+      |vpiActual:
+      \_int_typespec: , line:7:1, endln:7:22
+    |vpiName:SIZEA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEA
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA), line:8:11, endln:8:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:8
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA), line:8:11, endln:8:21
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHA
+      |vpiActual:
+      \_int_typespec: , line:8:1, endln:8:25
+    |vpiName:ADDRWIDTHA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHA
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.maxSIZE), line:41:12, endln:41:19
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:maxSIZE
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.maxSIZE
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.maxWIDTH), line:42:12, endln:42:20
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:maxWIDTH
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.maxWIDTH
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.minWIDTH), line:43:12, endln:43:20
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:minWIDTH
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.minWIDTH
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.RATIO), line:44:12, endln:44:17
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:RATIO
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.RATIO
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.log2RATIO), line:45:12, endln:45:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:log2RATIO
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.log2RATIO
+  |vpiParamAssign:
+  \_param_assign: , line:3:11, endln:3:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:3:20, endln:3:21
+      |vpiParent:
+      \_param_assign: , line:3:11, endln:3:21
+      |vpiDecompile:4
+      |vpiSize:64
+      |UINT:4
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:3:20, endln:3:21
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:3:1, endln:3:21
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:3:11, endln:3:17
+  |vpiParamAssign:
+  \_param_assign: , line:4:11, endln:4:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:4:19, endln:4:23
+      |vpiParent:
+      \_param_assign: , line:4:11, endln:4:23
+      |vpiDecompile:1024
+      |vpiSize:64
+      |UINT:1024
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:4:19, endln:4:23
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:4:1, endln:4:23
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEB), line:4:11, endln:4:16
+  |vpiParamAssign:
+  \_param_assign: , line:5:11, endln:5:26
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:5:24, endln:5:26
+      |vpiParent:
+      \_param_assign: , line:5:11, endln:5:26
+      |vpiDecompile:10
+      |vpiSize:64
+      |UINT:10
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:5:24, endln:5:26
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:5:1, endln:5:26
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB), line:5:11, endln:5:21
+  |vpiParamAssign:
+  \_param_assign: , line:6:11, endln:6:22
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:6:20, endln:6:22
+      |vpiParent:
+      \_param_assign: , line:6:11, endln:6:22
+      |vpiDecompile:16
+      |vpiSize:64
+      |UINT:16
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:6:20, endln:6:22
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:6:1, endln:6:22
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:6:11, endln:6:17
+  |vpiParamAssign:
+  \_param_assign: , line:7:11, endln:7:22
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:7:19, endln:7:22
+      |vpiParent:
+      \_param_assign: , line:7:11, endln:7:22
+      |vpiDecompile:256
+      |vpiSize:64
+      |UINT:256
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:7:19, endln:7:22
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:7:1, endln:7:22
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEA), line:7:11, endln:7:16
+  |vpiParamAssign:
+  \_param_assign: , line:8:11, endln:8:25
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:8:24, endln:8:25
+      |vpiParent:
+      \_param_assign: , line:8:11, endln:8:25
+      |vpiDecompile:8
+      |vpiSize:64
+      |UINT:8
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:8:24, endln:8:25
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:8:1, endln:8:25
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA), line:8:11, endln:8:21
+  |vpiParamAssign:
+  \_param_assign: , line:41:12, endln:41:61
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_operation: , line:41:22, endln:41:61
+      |vpiParent:
+      \_param_assign: , line:41:12, endln:41:61
+      |vpiOpType:33
+      |vpiOperand:
+      \_operation: , line:41:23, endln:41:60
+        |vpiParent:
+        \_operation: , line:41:22, endln:41:61
+        |vpiOpType:32
+        |vpiOperand:
+        \_operation: , line:41:23, endln:41:40
+          |vpiParent:
+          \_operation: , line:41:23, endln:41:60
+          |vpiOpType:18
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.SIZEA), line:41:24, endln:41:29
+            |vpiParent:
+            \_operation: , line:41:23, endln:41:40
+            |vpiName:SIZEA
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEA
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.SIZEB), line:41:34, endln:41:39
+            |vpiParent:
+            \_operation: , line:41:23, endln:41:40
+            |vpiName:SIZEB
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEB
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.SIZEA), line:41:44, endln:41:49
+          |vpiParent:
+          \_operation: , line:41:23, endln:41:60
+          |vpiName:SIZEA
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEA
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.SIZEB), line:41:54, endln:41:59
+          |vpiParent:
+          \_operation: , line:41:23, endln:41:60
+          |vpiName:SIZEB
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEB
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.maxSIZE), line:41:12, endln:41:19
+  |vpiParamAssign:
+  \_param_assign: , line:42:12, endln:42:66
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_operation: , line:42:23, endln:42:66
+      |vpiParent:
+      \_param_assign: , line:42:12, endln:42:66
+      |vpiOpType:33
+      |vpiOperand:
+      \_operation: , line:42:24, endln:42:65
+        |vpiParent:
+        \_operation: , line:42:23, endln:42:66
+        |vpiOpType:32
+        |vpiOperand:
+        \_operation: , line:42:24, endln:42:43
+          |vpiParent:
+          \_operation: , line:42:24, endln:42:65
+          |vpiOpType:18
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:42:25, endln:42:31
+            |vpiParent:
+            \_operation: , line:42:24, endln:42:43
+            |vpiName:WIDTHA
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:42:36, endln:42:42
+            |vpiParent:
+            \_operation: , line:42:24, endln:42:43
+            |vpiName:WIDTHB
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:42:47, endln:42:53
+          |vpiParent:
+          \_operation: , line:42:24, endln:42:65
+          |vpiName:WIDTHA
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:42:58, endln:42:64
+          |vpiParent:
+          \_operation: , line:42:24, endln:42:65
+          |vpiName:WIDTHB
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.maxWIDTH), line:42:12, endln:42:20
+  |vpiParamAssign:
+  \_param_assign: , line:43:12, endln:43:66
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_operation: , line:43:23, endln:43:66
+      |vpiParent:
+      \_param_assign: , line:43:12, endln:43:66
+      |vpiOpType:33
+      |vpiOperand:
+      \_operation: , line:43:24, endln:43:65
+        |vpiParent:
+        \_operation: , line:43:23, endln:43:66
+        |vpiOpType:32
+        |vpiOperand:
+        \_operation: , line:43:24, endln:43:43
+          |vpiParent:
+          \_operation: , line:43:24, endln:43:65
+          |vpiOpType:20
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:43:25, endln:43:31
+            |vpiParent:
+            \_operation: , line:43:24, endln:43:43
+            |vpiName:WIDTHA
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:43:36, endln:43:42
+            |vpiParent:
+            \_operation: , line:43:24, endln:43:43
+            |vpiName:WIDTHB
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:43:47, endln:43:53
+          |vpiParent:
+          \_operation: , line:43:24, endln:43:65
+          |vpiName:WIDTHA
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:43:58, endln:43:64
+          |vpiParent:
+          \_operation: , line:43:24, endln:43:65
+          |vpiName:WIDTHB
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.minWIDTH), line:43:12, endln:43:20
+  |vpiParamAssign:
+  \_param_assign: , line:44:12, endln:44:39
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_operation: , line:44:20, endln:44:39
+      |vpiParent:
+      \_param_assign: , line:44:12, endln:44:39
+      |vpiOpType:12
+      |vpiOperand:
+      \_ref_obj: (work@asym_ram_tdp_write_first_dc.maxWIDTH), line:44:20, endln:44:28
+        |vpiParent:
+        \_operation: , line:44:20, endln:44:39
+        |vpiName:maxWIDTH
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.maxWIDTH
+      |vpiOperand:
+      \_ref_obj: (work@asym_ram_tdp_write_first_dc.minWIDTH), line:44:31, endln:44:39
+        |vpiParent:
+        \_operation: , line:44:20, endln:44:39
+        |vpiName:minWIDTH
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.minWIDTH
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.RATIO), line:44:12, endln:44:17
+  |vpiParamAssign:
+  \_param_assign: , line:45:12, endln:45:35
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_func_call: (log2), line:45:24, endln:45:28
+      |vpiParent:
+      \_param_assign: , line:45:12, endln:45:35
+      |vpiArgument:
+      \_ref_obj: (work@asym_ram_tdp_write_first_dc.RATIO), line:45:29, endln:45:34
+        |vpiParent:
+        \_func_call: (log2), line:45:24, endln:45:28
+        |vpiName:RATIO
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.RATIO
+      |vpiName:log2
+      |vpiFunction:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.log2RATIO), line:45:12, endln:45:21
+  |vpiDefName:work@asym_ram_tdp_write_first_dc
+  |vpiTaskFunc:
+  \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:log2
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+    |vpiVariables:
+    \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.log2.shifted)
+        |vpiParent:
+        \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+        |vpiActual:
+        \_logic_typespec: , line:26:1, endln:26:11
+      |vpiName:shifted
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+      |vpiAutomatic:1
+    |vpiVariables:
+    \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.log2.res)
+        |vpiParent:
+        \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+        |vpiActual:
+        \_integer_typespec: , line:27:1, endln:27:8
+      |vpiName:res
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+      |vpiSigned:1
+      |vpiAutomatic:1
+    |vpiVisibility:1
+    |vpiReturn:
+    \_integer_var: (work@asym_ram_tdp_write_first_dc.log2), line:24:10, endln:24:17
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.log2)
+        |vpiParent:
+        \_integer_var: (work@asym_ram_tdp_write_first_dc.log2), line:24:10, endln:24:17
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+        |vpiActual:
+        \_integer_typespec: , line:24:10, endln:24:17
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+      |vpiSigned:1
+    |vpiIODecl:
+    \_io_decl: (value), line:25:15, endln:25:20
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiDirection:1
+      |vpiName:value
+      |vpiTypedef:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.log2.value)
+        |vpiParent:
+        \_io_decl: (value), line:25:15, endln:25:20
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+        |vpiActual:
+        \_integer_typespec: , line:25:7, endln:25:14
+    |vpiStmt:
+    \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:28:1, endln:38:4
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+      |vpiStmt:
+      \_if_else: , line:29:5, endln:37:8
+        |vpiParent:
+        \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:28:1, endln:38:4
+        |vpiCondition:
+        \_operation: , line:29:9, endln:29:18
+          |vpiParent:
+          \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:28:1, endln:38:4
+          |vpiOpType:20
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.value), line:29:9, endln:29:14
+            |vpiParent:
+            \_operation: , line:29:9, endln:29:18
+            |vpiName:value
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+            |vpiActual:
+            \_io_decl: (value), line:25:15, endln:25:20
+          |vpiOperand:
+          \_constant: , line:29:17, endln:29:18
+            |vpiParent:
+            \_operation: , line:29:9, endln:29:18
+            |vpiDecompile:2
+            |vpiSize:64
+            |UINT:2
+            |vpiConstType:9
+        |vpiStmt:
+        \_assignment: , line:30:9, endln:30:21
+          |vpiParent:
+          \_if_else: , line:29:5, endln:37:8
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.value), line:30:16, endln:30:21
+            |vpiParent:
+            \_assignment: , line:30:9, endln:30:21
+            |vpiName:value
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+            |vpiActual:
+            \_io_decl: (value), line:25:15, endln:25:20
+          |vpiLhs:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.log2), line:30:9, endln:30:13
+            |vpiParent:
+            \_assignment: , line:30:9, endln:30:21
+            |vpiName:log2
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.log2
+            |vpiActual:
+            \_integer_var: (work@asym_ram_tdp_write_first_dc.log2), line:24:10, endln:24:17
+        |vpiElseStmt:
+        \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+          |vpiParent:
+          \_if_else: , line:29:5, endln:37:8
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+          |vpiStmt:
+          \_assignment: , line:33:9, endln:33:26
+            |vpiParent:
+            \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_operation: , line:33:19, endln:33:26
+              |vpiParent:
+              \_assignment: , line:33:9, endln:33:26
+              |vpiOpType:11
+              |vpiOperand:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.value), line:33:19, endln:33:24
+                |vpiParent:
+                \_operation: , line:33:19, endln:33:26
+                |vpiName:value
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+                |vpiActual:
+                \_io_decl: (value), line:25:15, endln:25:20
+              |vpiOperand:
+              \_constant: , line:33:25, endln:33:26
+                |vpiParent:
+                \_operation: , line:33:19, endln:33:26
+                |vpiDecompile:1
+                |vpiSize:64
+                |UINT:1
+                |vpiConstType:9
+            |vpiLhs:
+            \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:33:9, endln:33:16
+              |vpiParent:
+              \_assignment: , line:33:9, endln:33:26
+              |vpiName:shifted
+              |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+              |vpiActual:
+              \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+          |vpiStmt:
+          \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+            |vpiParent:
+            \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+            |vpiForInitStmt:
+            \_assignment: , line:34:18, endln:34:23
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiRhs:
+              \_constant: , line:34:22, endln:34:23
+                |vpiParent:
+                \_assignment: , line:34:18, endln:34:23
+                |vpiDecompile:0
+                |vpiSize:64
+                |UINT:0
+                |vpiConstType:9
+              |vpiLhs:
+              \_ref_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:34:18, endln:34:21
+                |vpiParent:
+                \_assignment: , line:34:18, endln:34:23
+                |vpiName:res
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+            |vpiForIncStmt:
+            \_assignment: , line:34:36, endln:34:45
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiOpType:82
+              |vpiBlocking:1
+              |vpiRhs:
+              \_operation: , line:34:40, endln:34:45
+                |vpiParent:
+                \_assignment: , line:34:36, endln:34:45
+                |vpiOpType:24
+                |vpiOperand:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.res), line:34:40, endln:34:43
+                  |vpiParent:
+                  \_operation: , line:34:40, endln:34:45
+                  |vpiName:res
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+                  |vpiActual:
+                  \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+                |vpiOperand:
+                \_constant: , line:34:44, endln:34:45
+                  |vpiParent:
+                  \_operation: , line:34:40, endln:34:45
+                  |vpiDecompile:1
+                  |vpiSize:64
+                  |UINT:1
+                  |vpiConstType:9
+              |vpiLhs:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.res), line:34:36, endln:34:39
+                |vpiParent:
+                \_assignment: , line:34:36, endln:34:45
+                |vpiName:res
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+                |vpiActual:
+                \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+            |vpiCondition:
+            \_operation: , line:34:25, endln:34:34
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiOpType:18
+              |vpiOperand:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:34:25, endln:34:32
+                |vpiParent:
+                \_operation: , line:34:25, endln:34:34
+                |vpiName:shifted
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+                |vpiActual:
+                \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+              |vpiOperand:
+              \_constant: , line:34:33, endln:34:34
+                |vpiParent:
+                \_operation: , line:34:25, endln:34:34
+                |vpiDecompile:0
+                |vpiSize:64
+                |UINT:0
+                |vpiConstType:9
+            |vpiStmt:
+            \_assignment: , line:35:17, endln:35:37
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiOpType:82
+              |vpiBlocking:1
+              |vpiRhs:
+              \_operation: , line:35:27, endln:35:37
+                |vpiParent:
+                \_assignment: , line:35:17, endln:35:37
+                |vpiOpType:23
+                |vpiOperand:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:35:27, endln:35:34
+                  |vpiParent:
+                  \_operation: , line:35:27, endln:35:37
+                  |vpiName:shifted
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+                  |vpiActual:
+                  \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+                |vpiOperand:
+                \_constant: , line:35:36, endln:35:37
+                  |vpiParent:
+                  \_operation: , line:35:27, endln:35:37
+                  |vpiDecompile:1
+                  |vpiSize:64
+                  |UINT:1
+                  |vpiConstType:9
+              |vpiLhs:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:35:17, endln:35:24
+                |vpiParent:
+                \_assignment: , line:35:17, endln:35:37
+                |vpiName:shifted
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+                |vpiActual:
+                \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+          |vpiStmt:
+          \_assignment: , line:36:17, endln:36:27
+            |vpiParent:
+            \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.res), line:36:24, endln:36:27
+              |vpiParent:
+              \_assignment: , line:36:17, endln:36:27
+              |vpiName:res
+              |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+              |vpiActual:
+              \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+            |vpiLhs:
+            \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.log2), line:36:17, endln:36:21
+              |vpiParent:
+              \_assignment: , line:36:17, endln:36:27
+              |vpiName:log2
+              |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.log2
+              |vpiActual:
+              \_integer_var: (work@asym_ram_tdp_write_first_dc.log2), line:24:10, endln:24:17
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:RAM
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.readA), line:48:18, endln:48:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:readA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.readA
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:readB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.readB
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.clkA), line:1:37, endln:1:41
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:clkA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.clkA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:clkB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.enaA), line:1:49, endln:1:53
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:enaA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.enaA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.weA), line:1:55, endln:1:58
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:weA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.weA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:enaB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:weB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrA), line:1:71, endln:1:76
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:addrA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.addrA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:addrB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.diA), line:1:85, endln:1:88
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:diA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.diA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:doA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:diB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:doB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+  |vpiPort:
+  \_port: (clkA), line:1:37, endln:1:41
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:clkA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.clkA.clkA), line:1:37, endln:1:41
+      |vpiParent:
+      \_port: (clkA), line:1:37, endln:1:41
+      |vpiName:clkA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkA.clkA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.clkA), line:1:37, endln:1:41
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.clkA)
+      |vpiParent:
+      \_port: (clkA), line:1:37, endln:1:41
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkA
+      |vpiActual:
+      \_logic_typespec: , line:10:7, endln:10:7
+  |vpiPort:
+  \_port: (clkB), line:1:43, endln:1:47
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:clkB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.clkB.clkB), line:1:43, endln:1:47
+      |vpiParent:
+      \_port: (clkB), line:1:43, endln:1:47
+      |vpiName:clkB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB.clkB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.clkB)
+      |vpiParent:
+      \_port: (clkB), line:1:43, endln:1:47
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+      |vpiActual:
+      \_logic_typespec: , line:11:7, endln:11:7
+  |vpiPort:
+  \_port: (enaA), line:1:49, endln:1:53
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:enaA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.enaA.enaA), line:1:49, endln:1:53
+      |vpiParent:
+      \_port: (enaA), line:1:49, endln:1:53
+      |vpiName:enaA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaA.enaA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.enaA), line:1:49, endln:1:53
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.enaA)
+      |vpiParent:
+      \_port: (enaA), line:1:49, endln:1:53
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaA
+      |vpiActual:
+      \_logic_typespec: , line:13:7, endln:13:7
+  |vpiPort:
+  \_port: (weA), line:1:55, endln:1:58
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:weA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.weA.weA), line:1:55, endln:1:58
+      |vpiParent:
+      \_port: (weA), line:1:55, endln:1:58
+      |vpiName:weA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weA.weA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.weA), line:1:55, endln:1:58
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.weA)
+      |vpiParent:
+      \_port: (weA), line:1:55, endln:1:58
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weA
+      |vpiActual:
+      \_logic_typespec: , line:12:7, endln:12:7
+  |vpiPort:
+  \_port: (enaB), line:1:60, endln:1:64
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:enaB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.enaB.enaB), line:1:60, endln:1:64
+      |vpiParent:
+      \_port: (enaB), line:1:60, endln:1:64
+      |vpiName:enaB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB.enaB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.enaB)
+      |vpiParent:
+      \_port: (enaB), line:1:60, endln:1:64
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+      |vpiActual:
+      \_logic_typespec: , line:13:7, endln:13:7
+  |vpiPort:
+  \_port: (weB), line:1:66, endln:1:69
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:weB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.weB.weB), line:1:66, endln:1:69
+      |vpiParent:
+      \_port: (weB), line:1:66, endln:1:69
+      |vpiName:weB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weB.weB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.weB)
+      |vpiParent:
+      \_port: (weB), line:1:66, endln:1:69
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+      |vpiActual:
+      \_logic_typespec: , line:12:7, endln:12:7
+  |vpiPort:
+  \_port: (addrA), line:1:71, endln:1:76
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:addrA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrA.addrA), line:1:71, endln:1:76
+      |vpiParent:
+      \_port: (addrA), line:1:71, endln:1:76
+      |vpiName:addrA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrA.addrA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.addrA), line:1:71, endln:1:76
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.addrA)
+      |vpiParent:
+      \_port: (addrA), line:1:71, endln:1:76
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrA
+      |vpiActual:
+      \_logic_typespec: , line:14:7, endln:14:23
+  |vpiPort:
+  \_port: (addrB), line:1:78, endln:1:83
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:addrB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrB.addrB), line:1:78, endln:1:83
+      |vpiParent:
+      \_port: (addrB), line:1:78, endln:1:83
+      |vpiName:addrB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB.addrB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.addrB)
+      |vpiParent:
+      \_port: (addrB), line:1:78, endln:1:83
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+      |vpiActual:
+      \_logic_typespec: , line:15:7, endln:15:23
+  |vpiPort:
+  \_port: (diA), line:1:85, endln:1:88
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:diA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.diA.diA), line:1:85, endln:1:88
+      |vpiParent:
+      \_port: (diA), line:1:85, endln:1:88
+      |vpiName:diA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diA.diA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.diA), line:1:85, endln:1:88
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.diA)
+      |vpiParent:
+      \_port: (diA), line:1:85, endln:1:88
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diA
+      |vpiActual:
+      \_logic_typespec: , line:16:7, endln:16:19
+  |vpiPort:
+  \_port: (doA), line:1:90, endln:1:93
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:doA
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doA.doA), line:1:90, endln:1:93
+      |vpiParent:
+      \_port: (doA), line:1:90, endln:1:93
+      |vpiName:doA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doA.doA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.doA)
+      |vpiParent:
+      \_port: (doA), line:1:90, endln:1:93
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+      |vpiActual:
+      \_logic_typespec: , line:18:8, endln:18:20
+  |vpiPort:
+  \_port: (diB), line:1:95, endln:1:98
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:diB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.diB.diB), line:1:95, endln:1:98
+      |vpiParent:
+      \_port: (diB), line:1:95, endln:1:98
+      |vpiName:diB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diB.diB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.diB)
+      |vpiParent:
+      \_port: (diB), line:1:95, endln:1:98
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+      |vpiActual:
+      \_logic_typespec: , line:17:7, endln:17:19
+  |vpiPort:
+  \_port: (doB), line:1:100, endln:1:103
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:doB
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doB.doB), line:1:100, endln:1:103
+      |vpiParent:
+      \_port: (doB), line:1:100, endln:1:103
+      |vpiName:doB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doB.doB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.doB)
+      |vpiParent:
+      \_port: (doB), line:1:100, endln:1:103
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+      |vpiActual:
+      \_logic_typespec: , line:19:8, endln:19:20
+  |vpiProcess:
+  \_always: , line:50:1, endln:58:4
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiStmt:
+    \_event_control: , line:50:8, endln:50:23
+      |vpiParent:
+      \_always: , line:50:1, endln:58:4
+      |vpiCondition:
+      \_operation: , line:50:10, endln:50:22
+        |vpiParent:
+        \_event_control: , line:50:8, endln:50:23
+        |vpiOpType:39
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.clkB), line:50:18, endln:50:22
+          |vpiParent:
+          \_operation: , line:50:10, endln:50:22
+          |vpiName:clkB
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+          |vpiActual:
+          \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+      |vpiStmt:
+      \_begin: (work@asym_ram_tdp_write_first_dc), line:51:1, endln:58:4
+        |vpiParent:
+        \_event_control: , line:50:8, endln:50:23
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiStmt:
+        \_if_stmt: , line:52:5, endln:57:8
+          |vpiParent:
+          \_begin: (work@asym_ram_tdp_write_first_dc), line:51:1, endln:58:4
+          |vpiCondition:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.enaB), line:52:9, endln:52:13
+            |vpiParent:
+            \_begin: (work@asym_ram_tdp_write_first_dc), line:51:1, endln:58:4
+            |vpiName:enaB
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+            |vpiActual:
+            \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+          |vpiStmt:
+          \_begin: (work@asym_ram_tdp_write_first_dc), line:53:5, endln:57:8
+            |vpiParent:
+            \_if_stmt: , line:52:5, endln:57:8
+            |vpiFullName:work@asym_ram_tdp_write_first_dc
+            |vpiStmt:
+            \_if_stmt: , line:54:9, endln:55:30
+              |vpiParent:
+              \_begin: (work@asym_ram_tdp_write_first_dc), line:53:5, endln:57:8
+              |vpiCondition:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.weB), line:54:13, endln:54:16
+                |vpiParent:
+                \_begin: (work@asym_ram_tdp_write_first_dc), line:53:5, endln:57:8
+                |vpiName:weB
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+                |vpiActual:
+                \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+              |vpiStmt:
+              \_assignment: , line:55:13, endln:55:29
+                |vpiParent:
+                \_if_stmt: , line:54:9, endln:55:30
+                |vpiOpType:82
+                |vpiBlocking:1
+                |vpiRhs:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.diB), line:55:26, endln:55:29
+                  |vpiParent:
+                  \_assignment: , line:55:13, endln:55:29
+                  |vpiName:diB
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+                  |vpiActual:
+                  \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+                |vpiLhs:
+                \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:55:13, endln:55:23
+                  |vpiParent:
+                  \_assignment: , line:55:13, endln:55:29
+                  |vpiName:RAM
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+                  |vpiIndex:
+                  \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrB), line:55:17, endln:55:22
+                    |vpiParent:
+                    \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:55:13, endln:55:23
+                    |vpiName:addrB
+                    |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+                    |vpiActual:
+                    \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+            |vpiStmt:
+            \_assignment: , line:56:9, endln:56:27
+              |vpiParent:
+              \_begin: (work@asym_ram_tdp_write_first_dc), line:53:5, endln:57:8
+              |vpiOpType:82
+              |vpiBlocking:1
+              |vpiRhs:
+              \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:56:21, endln:56:26
+                |vpiParent:
+                \_assignment: , line:56:9, endln:56:27
+                |vpiName:RAM
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+                |vpiIndex:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrB), line:56:21, endln:56:26
+                  |vpiParent:
+                  \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:56:21, endln:56:26
+                  |vpiName:addrB
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+                  |vpiActual:
+                  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+              |vpiLhs:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.readB), line:56:9, endln:56:14
+                |vpiParent:
+                \_assignment: , line:56:9, endln:56:27
+                |vpiName:readB
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.readB
+                |vpiActual:
+                \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+    |vpiAlwaysType:1
+  |vpiContAssign:
+  \_cont_assign: , line:76:8, endln:76:19
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.readA), line:76:14, endln:76:19
+      |vpiParent:
+      \_cont_assign: , line:76:8, endln:76:19
+      |vpiName:readA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.readA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.readA), line:48:18, endln:48:23
+    |vpiLhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doA), line:76:8, endln:76:11
+      |vpiParent:
+      \_cont_assign: , line:76:8, endln:76:19
+      |vpiName:doA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+  |vpiContAssign:
+  \_cont_assign: , line:77:8, endln:77:19
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.readB), line:77:14, endln:77:19
+      |vpiParent:
+      \_cont_assign: , line:77:8, endln:77:19
+      |vpiName:readB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.readB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+    |vpiLhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doB), line:77:8, endln:77:11
+      |vpiParent:
+      \_cont_assign: , line:77:8, endln:77:19
+      |vpiName:doB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+|uhdmtopModules:
+\_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiName:work@asym_ram_tdp_write_first_dc
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:3:11, endln:3:17
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:4
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.WIDTHB)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:3:11, endln:3:17
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+      |vpiActual:
+      \_int_typespec: , line:3:1, endln:3:21
+    |vpiName:WIDTHB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHB
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEB), line:4:11, endln:4:16
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:1024
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.SIZEB)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEB), line:4:11, endln:4:16
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEB
+      |vpiActual:
+      \_int_typespec: , line:4:1, endln:4:23
+    |vpiName:SIZEB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEB
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB), line:5:11, endln:5:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB), line:5:11, endln:5:21
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHB
+      |vpiActual:
+      \_int_typespec: , line:5:1, endln:5:26
+    |vpiName:ADDRWIDTHB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHB
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:6:11, endln:6:17
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:16
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.WIDTHA)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:6:11, endln:6:17
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+      |vpiActual:
+      \_int_typespec: , line:6:1, endln:6:22
+    |vpiName:WIDTHA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.WIDTHA
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEA), line:7:11, endln:7:16
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:256
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.SIZEA)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEA), line:7:11, endln:7:16
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEA
+      |vpiActual:
+      \_int_typespec: , line:7:1, endln:7:22
+    |vpiName:SIZEA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.SIZEA
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA), line:8:11, endln:8:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |UINT:8
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA)
+      |vpiParent:
+      \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA), line:8:11, endln:8:21
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHA
+      |vpiActual:
+      \_int_typespec: , line:8:1, endln:8:25
+    |vpiName:ADDRWIDTHA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.ADDRWIDTHA
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.maxSIZE), line:41:12, endln:41:19
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:maxSIZE
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.maxSIZE
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.maxWIDTH), line:42:12, endln:42:20
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:maxWIDTH
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.maxWIDTH
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.minWIDTH), line:43:12, endln:43:20
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:minWIDTH
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.minWIDTH
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.RATIO), line:44:12, endln:44:17
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:RATIO
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.RATIO
+  |vpiParameter:
+  \_parameter: (work@asym_ram_tdp_write_first_dc.log2RATIO), line:45:12, endln:45:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiLocalParam:1
+    |vpiName:log2RATIO
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.log2RATIO
+  |vpiParamAssign:
+  \_param_assign: , line:3:11, endln:3:21
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:3:20, endln:3:21
+      |vpiParent:
+      \_param_assign: , line:3:11, endln:3:21
+      |vpiDecompile:4
+      |vpiSize:32
+      |UINT:4
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:3:20, endln:3:21
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:3:1, endln:3:21
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHB), line:3:11, endln:3:17
+  |vpiParamAssign:
+  \_param_assign: , line:4:11, endln:4:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:4:19, endln:4:23
+      |vpiParent:
+      \_param_assign: , line:4:11, endln:4:23
+      |vpiDecompile:1024
+      |vpiSize:32
+      |UINT:1024
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:4:19, endln:4:23
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:4:1, endln:4:23
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEB), line:4:11, endln:4:16
+  |vpiParamAssign:
+  \_param_assign: , line:5:11, endln:5:26
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:5:24, endln:5:26
+      |vpiParent:
+      \_param_assign: , line:5:11, endln:5:26
+      |vpiDecompile:10
+      |vpiSize:32
+      |UINT:10
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:5:24, endln:5:26
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:5:1, endln:5:26
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB), line:5:11, endln:5:21
+  |vpiParamAssign:
+  \_param_assign: , line:6:11, endln:6:22
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:6:20, endln:6:22
+      |vpiParent:
+      \_param_assign: , line:6:11, endln:6:22
+      |vpiDecompile:16
+      |vpiSize:32
+      |UINT:16
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:6:20, endln:6:22
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:6:1, endln:6:22
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.WIDTHA), line:6:11, endln:6:17
+  |vpiParamAssign:
+  \_param_assign: , line:7:11, endln:7:22
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:7:19, endln:7:22
+      |vpiParent:
+      \_param_assign: , line:7:11, endln:7:22
+      |vpiDecompile:256
+      |vpiSize:32
+      |UINT:256
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:7:19, endln:7:22
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:7:1, endln:7:22
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.SIZEA), line:7:11, endln:7:16
+  |vpiParamAssign:
+  \_param_assign: , line:8:11, endln:8:25
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:8:24, endln:8:25
+      |vpiParent:
+      \_param_assign: , line:8:11, endln:8:25
+      |vpiDecompile:8
+      |vpiSize:32
+      |UINT:8
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc)
+        |vpiParent:
+        \_constant: , line:8:24, endln:8:25
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiActual:
+        \_int_typespec: , line:8:1, endln:8:25
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA), line:8:11, endln:8:21
+  |vpiParamAssign:
+  \_param_assign: , line:41:12, endln:41:61
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:41:22, endln:41:61
+      |vpiParent:
+      \_param_assign: , line:41:12, endln:41:61
+      |vpiDecompile:32'b00000000000000000000010000000000
+      |vpiSize:32
+      |BIN:00000000000000000000010000000000
+      |vpiConstType:3
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.maxSIZE), line:41:12, endln:41:19
+  |vpiParamAssign:
+  \_param_assign: , line:42:12, endln:42:66
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:42:23, endln:42:66
+      |vpiParent:
+      \_param_assign: , line:42:12, endln:42:66
+      |vpiDecompile:32'b00000000000000000000000000010000
+      |vpiSize:32
+      |BIN:00000000000000000000000000010000
+      |vpiConstType:3
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.maxWIDTH), line:42:12, endln:42:20
+  |vpiParamAssign:
+  \_param_assign: , line:43:12, endln:43:66
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:43:23, endln:43:66
+      |vpiParent:
+      \_param_assign: , line:43:12, endln:43:66
+      |vpiDecompile:32'b00000000000000000000000000000100
+      |vpiSize:32
+      |BIN:00000000000000000000000000000100
+      |vpiConstType:3
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.minWIDTH), line:43:12, endln:43:20
+  |vpiParamAssign:
+  \_param_assign: , line:44:12, endln:44:39
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:44:20, endln:44:39
+      |vpiParent:
+      \_param_assign: , line:44:12, endln:44:39
+      |vpiDecompile:4
+      |vpiSize:64
+      |INT:4
+      |vpiConstType:7
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.RATIO), line:44:12, endln:44:17
+  |vpiParamAssign:
+  \_param_assign: , line:45:12, endln:45:35
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_constant: , line:45:24, endln:45:35
+      |vpiParent:
+      \_param_assign: , line:45:12, endln:45:35
+      |vpiDecompile:2
+      |vpiSize:64
+      |UINT:2
+      |vpiConstType:9
+    |vpiLhs:
+    \_parameter: (work@asym_ram_tdp_write_first_dc.log2RATIO), line:45:12, endln:45:21
+  |vpiDefName:work@asym_ram_tdp_write_first_dc
+  |vpiTop:1
+  |vpiTaskFunc:
+  \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:log2
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+    |vpiVariables:
+    \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.log2.shifted)
+        |vpiParent:
+        \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+        |vpiActual:
+        \_logic_typespec: , line:26:1, endln:26:11
+      |vpiName:shifted
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+      |vpiAutomatic:1
+    |vpiVariables:
+    \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.log2.res)
+        |vpiParent:
+        \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+        |vpiActual:
+        \_integer_typespec: , line:27:1, endln:27:8
+      |vpiName:res
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+      |vpiSigned:1
+      |vpiAutomatic:1
+    |vpiVisibility:1
+    |vpiReturn:
+    \_integer_var: (work@asym_ram_tdp_write_first_dc.log2), line:24:10, endln:24:17
+    |vpiIODecl:
+    \_io_decl: (value), line:25:15, endln:25:20
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiDirection:1
+      |vpiName:value
+      |vpiTypedef:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.log2.value)
+        |vpiParent:
+        \_io_decl: (value), line:25:15, endln:25:20
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+        |vpiActual:
+        \_integer_typespec: , line:25:7, endln:25:14
+    |vpiStmt:
+    \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:28:1, endln:38:4
+      |vpiParent:
+      \_function: (work@asym_ram_tdp_write_first_dc.log2), line:24:1, endln:39:12
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+      |vpiStmt:
+      \_if_else: , line:29:5, endln:37:8
+        |vpiParent:
+        \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:28:1, endln:38:4
+        |vpiCondition:
+        \_operation: , line:29:9, endln:29:18
+          |vpiParent:
+          \_if_else: , line:29:5, endln:37:8
+          |vpiOpType:20
+          |vpiOperand:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.value), line:29:9, endln:29:14
+            |vpiParent:
+            \_operation: , line:29:9, endln:29:18
+            |vpiName:value
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+            |vpiActual:
+            \_io_decl: (value), line:25:15, endln:25:20
+          |vpiOperand:
+          \_constant: , line:29:17, endln:29:18
+        |vpiStmt:
+        \_assignment: , line:30:9, endln:30:21
+          |vpiParent:
+          \_if_else: , line:29:5, endln:37:8
+          |vpiOpType:82
+          |vpiBlocking:1
+          |vpiRhs:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.value), line:30:16, endln:30:21
+            |vpiParent:
+            \_assignment: , line:30:9, endln:30:21
+            |vpiName:value
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+            |vpiActual:
+            \_io_decl: (value), line:25:15, endln:25:20
+          |vpiLhs:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.log2), line:30:9, endln:30:13
+            |vpiParent:
+            \_assignment: , line:30:9, endln:30:21
+            |vpiName:log2
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.log2
+            |vpiActual:
+            \_integer_var: (work@asym_ram_tdp_write_first_dc.log2), line:24:10, endln:24:17
+        |vpiElseStmt:
+        \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+          |vpiParent:
+          \_if_else: , line:29:5, endln:37:8
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+          |vpiStmt:
+          \_assignment: , line:33:9, endln:33:26
+            |vpiParent:
+            \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_operation: , line:33:19, endln:33:26
+              |vpiParent:
+              \_assignment: , line:33:9, endln:33:26
+              |vpiOpType:11
+              |vpiOperand:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.value), line:33:19, endln:33:24
+                |vpiParent:
+                \_operation: , line:33:19, endln:33:26
+                |vpiName:value
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.value
+                |vpiActual:
+                \_io_decl: (value), line:25:15, endln:25:20
+              |vpiOperand:
+              \_constant: , line:33:25, endln:33:26
+            |vpiLhs:
+            \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:33:9, endln:33:16
+              |vpiParent:
+              \_assignment: , line:33:9, endln:33:26
+              |vpiName:shifted
+              |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+              |vpiActual:
+              \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+          |vpiStmt:
+          \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+            |vpiParent:
+            \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.log2
+            |vpiForInitStmt:
+            \_assignment: , line:34:18, endln:34:23
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiRhs:
+              \_constant: , line:34:22, endln:34:23
+              |vpiLhs:
+              \_ref_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:34:18, endln:34:21
+                |vpiParent:
+                \_assignment: , line:34:18, endln:34:23
+                |vpiName:res
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+                |vpiActual:
+                \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+            |vpiForIncStmt:
+            \_assignment: , line:34:36, endln:34:45
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiOpType:82
+              |vpiBlocking:1
+              |vpiRhs:
+              \_operation: , line:34:40, endln:34:45
+                |vpiParent:
+                \_assignment: , line:34:36, endln:34:45
+                |vpiOpType:24
+                |vpiOperand:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.res), line:34:40, endln:34:43
+                  |vpiParent:
+                  \_operation: , line:34:40, endln:34:45
+                  |vpiName:res
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+                  |vpiActual:
+                  \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+                |vpiOperand:
+                \_constant: , line:34:44, endln:34:45
+              |vpiLhs:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.res), line:34:36, endln:34:39
+                |vpiParent:
+                \_assignment: , line:34:36, endln:34:45
+                |vpiName:res
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+                |vpiActual:
+                \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+            |vpiCondition:
+            \_operation: , line:34:25, endln:34:34
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiOpType:18
+              |vpiOperand:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:34:25, endln:34:32
+                |vpiParent:
+                \_operation: , line:34:25, endln:34:34
+                |vpiName:shifted
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+                |vpiActual:
+                \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+              |vpiOperand:
+              \_constant: , line:34:33, endln:34:34
+            |vpiStmt:
+            \_assignment: , line:35:17, endln:35:37
+              |vpiParent:
+              \_for_stmt: (work@asym_ram_tdp_write_first_dc.log2), line:34:13, endln:34:16
+              |vpiOpType:82
+              |vpiBlocking:1
+              |vpiRhs:
+              \_operation: , line:35:27, endln:35:37
+                |vpiParent:
+                \_assignment: , line:35:17, endln:35:37
+                |vpiOpType:23
+                |vpiOperand:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:35:27, endln:35:34
+                  |vpiParent:
+                  \_operation: , line:35:27, endln:35:37
+                  |vpiName:shifted
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+                  |vpiActual:
+                  \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+                |vpiOperand:
+                \_constant: , line:35:36, endln:35:37
+              |vpiLhs:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:35:17, endln:35:24
+                |vpiParent:
+                \_assignment: , line:35:17, endln:35:37
+                |vpiName:shifted
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.shifted
+                |vpiActual:
+                \_logic_var: (work@asym_ram_tdp_write_first_dc.log2.shifted), line:26:1, endln:26:11
+          |vpiStmt:
+          \_assignment: , line:36:17, endln:36:27
+            |vpiParent:
+            \_begin: (work@asym_ram_tdp_write_first_dc.log2), line:32:5, endln:37:8
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.res), line:36:24, endln:36:27
+              |vpiParent:
+              \_assignment: , line:36:17, endln:36:27
+              |vpiName:res
+              |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.res
+              |vpiActual:
+              \_integer_var: (work@asym_ram_tdp_write_first_dc.log2.res), line:27:1, endln:27:8
+            |vpiLhs:
+            \_ref_obj: (work@asym_ram_tdp_write_first_dc.log2.log2), line:36:17, endln:36:21
+              |vpiParent:
+              \_assignment: , line:36:17, endln:36:27
+              |vpiName:log2
+              |vpiFullName:work@asym_ram_tdp_write_first_dc.log2.log2
+              |vpiActual:
+              \_integer_var: (work@asym_ram_tdp_write_first_dc.log2), line:24:10, endln:24:17
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.readA), line:48:18, endln:48:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.readA)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.readA), line:48:18, endln:48:23
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.readA
+      |vpiActual:
+      \_logic_typespec: , line:48:1, endln:48:17
+    |vpiName:readA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.readA
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.readB)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.readB
+      |vpiActual:
+      \_logic_typespec: , line:49:1, endln:49:17
+    |vpiName:readB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.readB
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.clkA), line:1:37, endln:1:41
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.clkA)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.clkA), line:1:37, endln:1:41
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkA
+      |vpiActual:
+      \_logic_typespec: , line:10:7, endln:10:7
+    |vpiName:clkA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.clkA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.clkB)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+      |vpiActual:
+      \_logic_typespec: , line:11:7, endln:11:7
+    |vpiName:clkB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.enaA), line:1:49, endln:1:53
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.enaA)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.enaA), line:1:49, endln:1:53
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaA
+      |vpiActual:
+      \_logic_typespec: , line:13:7, endln:13:7
+    |vpiName:enaA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.enaA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.weA), line:1:55, endln:1:58
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.weA)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.weA), line:1:55, endln:1:58
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weA
+      |vpiActual:
+      \_logic_typespec: , line:12:7, endln:12:7
+    |vpiName:weA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.weA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.enaB)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+      |vpiActual:
+      \_logic_typespec: , line:13:7, endln:13:7
+    |vpiName:enaB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.weB)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+      |vpiActual:
+      \_logic_typespec: , line:12:7, endln:12:7
+    |vpiName:weB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrA), line:1:71, endln:1:76
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.addrA)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.addrA), line:1:71, endln:1:76
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrA
+      |vpiActual:
+      \_logic_typespec: , line:14:7, endln:14:23
+    |vpiName:addrA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.addrA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.addrB)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+      |vpiActual:
+      \_logic_typespec: , line:15:7, endln:15:23
+    |vpiName:addrB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.diA), line:1:85, endln:1:88
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.diA)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.diA), line:1:85, endln:1:88
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diA
+      |vpiActual:
+      \_logic_typespec: , line:16:7, endln:16:19
+    |vpiName:diA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.diA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.doA)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+      |vpiActual:
+      \_logic_typespec: , line:18:8, endln:18:20
+    |vpiName:doA
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.diB)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+      |vpiActual:
+      \_logic_typespec: , line:17:7, endln:17:19
+    |vpiName:diB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+  |vpiNet:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiTypespec:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.doB)
+      |vpiParent:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+      |vpiActual:
+      \_logic_typespec: , line:19:8, endln:19:20
+    |vpiName:doB
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+  |vpiArrayNet:
+  \_array_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiSize:1024
+    |vpiName:RAM
+    |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+    |vpiRange:
+    \_range: , line:47:24, endln:47:37
+      |vpiParent:
+      \_array_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+      |vpiLeftRange:
+      \_constant: , line:47:25, endln:47:26
+        |vpiParent:
+        \_range: , line:47:24, endln:47:37
+        |vpiDecompile:0
+        |vpiSize:64
+        |UINT:0
+        |vpiConstType:9
+      |vpiRightRange:
+      \_constant: , line:47:27, endln:47:34
+        |vpiParent:
+        \_range: , line:47:24, endln:47:37
+        |vpiDecompile:1023
+        |vpiSize:64
+        |INT:1023
+        |vpiConstType:7
+    |vpiNet:
+    \_logic_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+      |vpiParent:
+      \_array_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+      |vpiTypespec:
+      \_ref_typespec: (work@asym_ram_tdp_write_first_dc.RAM)
+        |vpiParent:
+        \_logic_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+        |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+        |vpiActual:
+        \_logic_typespec: , line:47:1, endln:47:19
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+      |vpiNetType:48
+  |vpiTopModule:1
+  |vpiPort:
+  \_port: (clkA), line:1:37, endln:1:41
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:clkA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.clkA), line:1:37, endln:1:41
+      |vpiParent:
+      \_port: (clkA), line:1:37, endln:1:41
+      |vpiName:clkA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.clkA), line:1:37, endln:1:41
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.clkA)
+      |vpiParent:
+      \_port: (clkA), line:1:37, endln:1:41
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkA
+      |vpiActual:
+      \_logic_typespec: , line:10:7, endln:10:7
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (clkB), line:1:43, endln:1:47
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:clkB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+      |vpiParent:
+      \_port: (clkB), line:1:43, endln:1:47
+      |vpiName:clkB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.clkB)
+      |vpiParent:
+      \_port: (clkB), line:1:43, endln:1:47
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+      |vpiActual:
+      \_logic_typespec: , line:11:7, endln:11:7
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (enaA), line:1:49, endln:1:53
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:enaA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.enaA), line:1:49, endln:1:53
+      |vpiParent:
+      \_port: (enaA), line:1:49, endln:1:53
+      |vpiName:enaA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.enaA), line:1:49, endln:1:53
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.enaA)
+      |vpiParent:
+      \_port: (enaA), line:1:49, endln:1:53
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaA
+      |vpiActual:
+      \_logic_typespec: , line:13:7, endln:13:7
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (weA), line:1:55, endln:1:58
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:weA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.weA), line:1:55, endln:1:58
+      |vpiParent:
+      \_port: (weA), line:1:55, endln:1:58
+      |vpiName:weA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.weA), line:1:55, endln:1:58
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.weA)
+      |vpiParent:
+      \_port: (weA), line:1:55, endln:1:58
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weA
+      |vpiActual:
+      \_logic_typespec: , line:12:7, endln:12:7
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (enaB), line:1:60, endln:1:64
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:enaB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+      |vpiParent:
+      \_port: (enaB), line:1:60, endln:1:64
+      |vpiName:enaB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.enaB)
+      |vpiParent:
+      \_port: (enaB), line:1:60, endln:1:64
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+      |vpiActual:
+      \_logic_typespec: , line:13:7, endln:13:7
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (weB), line:1:66, endln:1:69
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:weB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+      |vpiParent:
+      \_port: (weB), line:1:66, endln:1:69
+      |vpiName:weB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.weB)
+      |vpiParent:
+      \_port: (weB), line:1:66, endln:1:69
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+      |vpiActual:
+      \_logic_typespec: , line:12:7, endln:12:7
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (addrA), line:1:71, endln:1:76
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:addrA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrA), line:1:71, endln:1:76
+      |vpiParent:
+      \_port: (addrA), line:1:71, endln:1:76
+      |vpiName:addrA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.addrA), line:1:71, endln:1:76
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.addrA)
+      |vpiParent:
+      \_port: (addrA), line:1:71, endln:1:76
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrA
+      |vpiActual:
+      \_logic_typespec: , line:14:7, endln:14:23
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (addrB), line:1:78, endln:1:83
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:addrB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+      |vpiParent:
+      \_port: (addrB), line:1:78, endln:1:83
+      |vpiName:addrB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.addrB)
+      |vpiParent:
+      \_port: (addrB), line:1:78, endln:1:83
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+      |vpiActual:
+      \_logic_typespec: , line:15:7, endln:15:23
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (diA), line:1:85, endln:1:88
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:diA
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.diA), line:1:85, endln:1:88
+      |vpiParent:
+      \_port: (diA), line:1:85, endln:1:88
+      |vpiName:diA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.diA), line:1:85, endln:1:88
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.diA)
+      |vpiParent:
+      \_port: (diA), line:1:85, endln:1:88
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diA
+      |vpiActual:
+      \_logic_typespec: , line:16:7, endln:16:19
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (doA), line:1:90, endln:1:93
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:doA
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+      |vpiParent:
+      \_port: (doA), line:1:90, endln:1:93
+      |vpiName:doA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.doA)
+      |vpiParent:
+      \_port: (doA), line:1:90, endln:1:93
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+      |vpiActual:
+      \_logic_typespec: , line:18:8, endln:18:20
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (diB), line:1:95, endln:1:98
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:diB
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+      |vpiParent:
+      \_port: (diB), line:1:95, endln:1:98
+      |vpiName:diB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.diB)
+      |vpiParent:
+      \_port: (diB), line:1:95, endln:1:98
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+      |vpiActual:
+      \_logic_typespec: , line:17:7, endln:17:19
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiPort:
+  \_port: (doB), line:1:100, endln:1:103
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiName:doB
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+      |vpiParent:
+      \_port: (doB), line:1:100, endln:1:103
+      |vpiName:doB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+    |vpiTypedef:
+    \_ref_typespec: (work@asym_ram_tdp_write_first_dc.doB)
+      |vpiParent:
+      \_port: (doB), line:1:100, endln:1:103
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+      |vpiActual:
+      \_logic_typespec: , line:19:8, endln:19:20
+    |vpiInstance:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+  |vpiProcess:
+  \_always: , line:50:1, endln:58:4
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiStmt:
+    \_event_control: , line:50:8, endln:50:23
+      |vpiParent:
+      \_always: , line:50:1, endln:58:4
+      |vpiCondition:
+      \_operation: , line:50:10, endln:50:22
+        |vpiParent:
+        \_event_control: , line:50:8, endln:50:23
+        |vpiOpType:39
+        |vpiOperand:
+        \_ref_obj: (work@asym_ram_tdp_write_first_dc.clkB), line:50:18, endln:50:22
+          |vpiParent:
+          \_operation: , line:50:10, endln:50:22
+          |vpiName:clkB
+          |vpiFullName:work@asym_ram_tdp_write_first_dc.clkB
+          |vpiActual:
+          \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+      |vpiStmt:
+      \_begin: (work@asym_ram_tdp_write_first_dc), line:51:1, endln:58:4
+        |vpiParent:
+        \_event_control: , line:50:8, endln:50:23
+        |vpiFullName:work@asym_ram_tdp_write_first_dc
+        |vpiStmt:
+        \_if_stmt: , line:52:5, endln:57:8
+          |vpiParent:
+          \_begin: (work@asym_ram_tdp_write_first_dc), line:51:1, endln:58:4
+          |vpiCondition:
+          \_ref_obj: (work@asym_ram_tdp_write_first_dc.enaB), line:52:9, endln:52:13
+            |vpiParent:
+            \_if_stmt: , line:52:5, endln:57:8
+            |vpiName:enaB
+            |vpiFullName:work@asym_ram_tdp_write_first_dc.enaB
+            |vpiActual:
+            \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+          |vpiStmt:
+          \_begin: (work@asym_ram_tdp_write_first_dc), line:53:5, endln:57:8
+            |vpiParent:
+            \_if_stmt: , line:52:5, endln:57:8
+            |vpiFullName:work@asym_ram_tdp_write_first_dc
+            |vpiStmt:
+            \_if_stmt: , line:54:9, endln:55:30
+              |vpiParent:
+              \_begin: (work@asym_ram_tdp_write_first_dc), line:53:5, endln:57:8
+              |vpiCondition:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.weB), line:54:13, endln:54:16
+                |vpiParent:
+                \_if_stmt: , line:54:9, endln:55:30
+                |vpiName:weB
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.weB
+                |vpiActual:
+                \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+              |vpiStmt:
+              \_assignment: , line:55:13, endln:55:29
+                |vpiParent:
+                \_if_stmt: , line:54:9, endln:55:30
+                |vpiOpType:82
+                |vpiRhs:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.diB), line:55:26, endln:55:29
+                  |vpiParent:
+                  \_assignment: , line:55:13, endln:55:29
+                  |vpiName:diB
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.diB
+                  |vpiActual:
+                  \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+                |vpiLhs:
+                \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:55:13, endln:55:23
+                  |vpiParent:
+                  \_assignment: , line:55:13, endln:55:29
+                  |vpiName:RAM
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+                  |vpiActual:
+                  \_array_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+                  |vpiIndex:
+                  \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrB), line:55:17, endln:55:22
+                    |vpiParent:
+                    \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:55:13, endln:55:23
+                    |vpiName:addrB
+                    |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+                    |vpiActual:
+                    \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+            |vpiStmt:
+            \_assignment: , line:56:9, endln:56:27
+              |vpiParent:
+              \_begin: (work@asym_ram_tdp_write_first_dc), line:53:5, endln:57:8
+              |vpiOpType:82
+              |vpiRhs:
+              \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:56:21, endln:56:26
+                |vpiParent:
+                \_assignment: , line:56:9, endln:56:27
+                |vpiName:RAM
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.RAM
+                |vpiActual:
+                \_array_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+                |vpiIndex:
+                \_ref_obj: (work@asym_ram_tdp_write_first_dc.addrB), line:56:21, endln:56:26
+                  |vpiParent:
+                  \_bit_select: (work@asym_ram_tdp_write_first_dc.RAM), line:56:21, endln:56:26
+                  |vpiName:addrB
+                  |vpiFullName:work@asym_ram_tdp_write_first_dc.addrB
+                  |vpiActual:
+                  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+              |vpiLhs:
+              \_ref_obj: (work@asym_ram_tdp_write_first_dc.readB), line:56:9, endln:56:14
+                |vpiParent:
+                \_assignment: , line:56:9, endln:56:27
+                |vpiName:readB
+                |vpiFullName:work@asym_ram_tdp_write_first_dc.readB
+                |vpiActual:
+                \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+    |vpiAlwaysType:1
+  |vpiContAssign:
+  \_cont_assign: , line:76:8, endln:76:19
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.readA), line:76:14, endln:76:19
+      |vpiParent:
+      \_cont_assign: , line:76:8, endln:76:19
+      |vpiName:readA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.readA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.readA), line:48:18, endln:48:23
+    |vpiLhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doA), line:76:8, endln:76:11
+      |vpiParent:
+      \_cont_assign: , line:76:8, endln:76:19
+      |vpiName:doA
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doA
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doA), line:1:90, endln:1:93
+  |vpiContAssign:
+  \_cont_assign: , line:77:8, endln:77:19
+    |vpiParent:
+    \_module_inst: work@asym_ram_tdp_write_first_dc (work@asym_ram_tdp_write_first_dc), file:${SURELOG_DIR}/tests/BlockingAssignRewrite/dut.sv, line:1:1, endln:79:10
+    |vpiRhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.readB), line:77:14, endln:77:19
+      |vpiParent:
+      \_cont_assign: , line:77:8, endln:77:19
+      |vpiName:readB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.readB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+    |vpiLhs:
+    \_ref_obj: (work@asym_ram_tdp_write_first_dc.doB), line:77:8, endln:77:11
+      |vpiParent:
+      \_cont_assign: , line:77:8, endln:77:19
+      |vpiName:doB
+      |vpiFullName:work@asym_ram_tdp_write_first_dc.doB
+      |vpiActual:
+      \_logic_net: (work@asym_ram_tdp_write_first_dc.doB), line:1:100, endln:1:103
+\_weaklyReferenced:
+\_int_typespec: , line:3:1, endln:3:21
+\_int_typespec: , line:4:1, endln:4:23
+\_int_typespec: , line:5:1, endln:5:26
+\_int_typespec: , line:6:1, endln:6:22
+\_int_typespec: , line:7:1, endln:7:22
+\_int_typespec: , line:8:1, endln:8:25
+\_integer_typespec: , line:24:10, endln:24:17
+  |vpiSigned:1
+\_integer_typespec: , line:25:7, endln:25:14
+  |vpiSigned:1
+\_logic_typespec: , line:26:1, endln:26:11
+  |vpiRange:
+  \_range: , line:26:5, endln:26:11
+    |vpiParent:
+    \_logic_typespec: , line:26:1, endln:26:11
+    |vpiLeftRange:
+    \_constant: , line:26:6, endln:26:8
+      |vpiParent:
+      \_range: , line:26:5, endln:26:11
+      |vpiDecompile:31
+      |vpiSize:64
+      |UINT:31
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:26:9, endln:26:10
+      |vpiParent:
+      \_range: , line:26:5, endln:26:11
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_integer_typespec: , line:27:1, endln:27:8
+  |vpiSigned:1
+\_logic_typespec: , line:10:7, endln:10:7
+\_logic_typespec: , line:11:7, endln:11:7
+\_logic_typespec: , line:13:7, endln:13:7
+\_logic_typespec: , line:12:7, endln:12:7
+\_logic_typespec: , line:14:7, endln:14:23
+  |vpiRange:
+  \_range: , line:14:7, endln:14:23
+    |vpiParent:
+    \_logic_typespec: , line:14:7, endln:14:23
+    |vpiLeftRange:
+    \_constant: , line:14:8, endln:14:18
+      |vpiParent:
+      \_range: , line:14:7, endln:14:23
+      |vpiDecompile:7
+      |vpiSize:64
+      |INT:7
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:14:21, endln:14:22
+      |vpiParent:
+      \_range: , line:14:7, endln:14:23
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:15:7, endln:15:23
+  |vpiRange:
+  \_range: , line:15:7, endln:15:23
+    |vpiParent:
+    \_logic_typespec: , line:15:7, endln:15:23
+    |vpiLeftRange:
+    \_constant: , line:15:8, endln:15:18
+      |vpiParent:
+      \_range: , line:15:7, endln:15:23
+      |vpiDecompile:9
+      |vpiSize:64
+      |INT:9
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:15:21, endln:15:22
+      |vpiParent:
+      \_range: , line:15:7, endln:15:23
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:16:7, endln:16:19
+  |vpiRange:
+  \_range: , line:16:7, endln:16:19
+    |vpiParent:
+    \_logic_typespec: , line:16:7, endln:16:19
+    |vpiLeftRange:
+    \_constant: , line:16:8, endln:16:14
+      |vpiParent:
+      \_range: , line:16:7, endln:16:19
+      |vpiDecompile:15
+      |vpiSize:64
+      |INT:15
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:16:17, endln:16:18
+      |vpiParent:
+      \_range: , line:16:7, endln:16:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:18:8, endln:18:20
+  |vpiRange:
+  \_range: , line:18:8, endln:18:20
+    |vpiParent:
+    \_logic_typespec: , line:18:8, endln:18:20
+    |vpiLeftRange:
+    \_constant: , line:18:9, endln:18:15
+      |vpiParent:
+      \_range: , line:18:8, endln:18:20
+      |vpiDecompile:15
+      |vpiSize:64
+      |INT:15
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:18:18, endln:18:19
+      |vpiParent:
+      \_range: , line:18:8, endln:18:20
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:17:7, endln:17:19
+  |vpiRange:
+  \_range: , line:17:7, endln:17:19
+    |vpiParent:
+    \_logic_typespec: , line:17:7, endln:17:19
+    |vpiLeftRange:
+    \_constant: , line:17:8, endln:17:14
+      |vpiParent:
+      \_range: , line:17:7, endln:17:19
+      |vpiDecompile:3
+      |vpiSize:64
+      |INT:3
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:17:17, endln:17:18
+      |vpiParent:
+      \_range: , line:17:7, endln:17:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:19:8, endln:19:20
+  |vpiRange:
+  \_range: , line:19:8, endln:19:20
+    |vpiParent:
+    \_logic_typespec: , line:19:8, endln:19:20
+    |vpiLeftRange:
+    \_constant: , line:19:9, endln:19:15
+      |vpiParent:
+      \_range: , line:19:8, endln:19:20
+      |vpiDecompile:3
+      |vpiSize:64
+      |INT:3
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:19:18, endln:19:19
+      |vpiParent:
+      \_range: , line:19:8, endln:19:20
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:47:1, endln:47:19
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.RAM), line:47:20, endln:47:23
+  |vpiRange:
+  \_range: , line:47:5, endln:47:19
+    |vpiParent:
+    \_logic_typespec: , line:47:1, endln:47:19
+    |vpiLeftRange:
+    \_constant: , line:47:6, endln:47:14
+      |vpiParent:
+      \_range: , line:47:5, endln:47:19
+      |vpiDecompile:3
+      |vpiSize:64
+      |INT:3
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:47:17, endln:47:18
+      |vpiParent:
+      \_range: , line:47:5, endln:47:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:48:1, endln:48:17
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.readA), line:48:18, endln:48:23
+  |vpiRange:
+  \_range: , line:48:5, endln:48:17
+    |vpiParent:
+    \_logic_typespec: , line:48:1, endln:48:17
+    |vpiLeftRange:
+    \_constant: , line:48:6, endln:48:12
+      |vpiParent:
+      \_range: , line:48:5, endln:48:17
+      |vpiDecompile:15
+      |vpiSize:64
+      |INT:15
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:48:15, endln:48:16
+      |vpiParent:
+      \_range: , line:48:5, endln:48:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:49:1, endln:49:17
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.readB), line:49:18, endln:49:23
+  |vpiRange:
+  \_range: , line:49:5, endln:49:17
+    |vpiParent:
+    \_logic_typespec: , line:49:1, endln:49:17
+    |vpiLeftRange:
+    \_constant: , line:49:6, endln:49:12
+      |vpiParent:
+      \_range: , line:49:5, endln:49:17
+      |vpiDecompile:3
+      |vpiSize:64
+      |INT:3
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:49:15, endln:49:16
+      |vpiParent:
+      \_range: , line:49:5, endln:49:17
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:10:7, endln:10:7
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.clkA), line:1:37, endln:1:41
+\_logic_typespec: , line:11:7, endln:11:7
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.clkB), line:1:43, endln:1:47
+\_logic_typespec: , line:13:7, endln:13:7
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.enaB), line:1:60, endln:1:64
+\_logic_typespec: , line:12:7, endln:12:7
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.weB), line:1:66, endln:1:69
+\_logic_typespec: , line:14:7, endln:14:23
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrA), line:1:71, endln:1:76
+  |vpiRange:
+  \_range: , line:14:7, endln:14:23
+    |vpiParent:
+    \_logic_typespec: , line:14:7, endln:14:23
+    |vpiLeftRange:
+    \_constant: , line:14:8, endln:14:18
+      |vpiParent:
+      \_range: , line:14:7, endln:14:23
+      |vpiDecompile:7
+      |vpiSize:64
+      |INT:7
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:14:21, endln:14:22
+      |vpiParent:
+      \_range: , line:14:7, endln:14:23
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:15:7, endln:15:23
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.addrB), line:1:78, endln:1:83
+  |vpiRange:
+  \_range: , line:15:7, endln:15:23
+    |vpiParent:
+    \_logic_typespec: , line:15:7, endln:15:23
+    |vpiLeftRange:
+    \_constant: , line:15:8, endln:15:18
+      |vpiParent:
+      \_range: , line:15:7, endln:15:23
+      |vpiDecompile:9
+      |vpiSize:64
+      |INT:9
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:15:21, endln:15:22
+      |vpiParent:
+      \_range: , line:15:7, endln:15:23
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:16:7, endln:16:19
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.diA), line:1:85, endln:1:88
+  |vpiRange:
+  \_range: , line:16:7, endln:16:19
+    |vpiParent:
+    \_logic_typespec: , line:16:7, endln:16:19
+    |vpiLeftRange:
+    \_constant: , line:16:8, endln:16:14
+      |vpiParent:
+      \_range: , line:16:7, endln:16:19
+      |vpiDecompile:15
+      |vpiSize:64
+      |INT:15
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:16:17, endln:16:18
+      |vpiParent:
+      \_range: , line:16:7, endln:16:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:18:8, endln:18:20
+  |vpiRange:
+  \_range: , line:18:8, endln:18:20
+    |vpiParent:
+    \_logic_typespec: , line:18:8, endln:18:20
+    |vpiLeftRange:
+    \_constant: , line:18:9, endln:18:15
+      |vpiParent:
+      \_range: , line:18:8, endln:18:20
+      |vpiDecompile:15
+      |vpiSize:64
+      |INT:15
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:18:18, endln:18:19
+      |vpiParent:
+      \_range: , line:18:8, endln:18:20
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:17:7, endln:17:19
+  |vpiParent:
+  \_logic_net: (work@asym_ram_tdp_write_first_dc.diB), line:1:95, endln:1:98
+  |vpiRange:
+  \_range: , line:17:7, endln:17:19
+    |vpiParent:
+    \_logic_typespec: , line:17:7, endln:17:19
+    |vpiLeftRange:
+    \_constant: , line:17:8, endln:17:14
+      |vpiParent:
+      \_range: , line:17:7, endln:17:19
+      |vpiDecompile:3
+      |vpiSize:64
+      |INT:3
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:17:17, endln:17:18
+      |vpiParent:
+      \_range: , line:17:7, endln:17:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:19:8, endln:19:20
+  |vpiRange:
+  \_range: , line:19:8, endln:19:20
+    |vpiParent:
+    \_logic_typespec: , line:19:8, endln:19:20
+    |vpiLeftRange:
+    \_constant: , line:19:9, endln:19:15
+      |vpiParent:
+      \_range: , line:19:8, endln:19:20
+      |vpiDecompile:3
+      |vpiSize:64
+      |INT:3
+      |vpiConstType:7
+    |vpiRightRange:
+    \_constant: , line:19:18, endln:19:19
+      |vpiParent:
+      \_range: , line:19:8, endln:19:20
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:10:7, endln:10:7
+\_logic_typespec: , line:11:7, endln:11:7
+\_logic_typespec: , line:13:7, endln:13:7
+\_logic_typespec: , line:12:7, endln:12:7
+\_logic_typespec: , line:13:7, endln:13:7
+\_logic_typespec: , line:12:7, endln:12:7
+\_logic_typespec: , line:14:7, endln:14:23
+  |vpiRange:
+  \_range: , line:14:7, endln:14:23
+    |vpiParent:
+    \_logic_typespec: , line:14:7, endln:14:23
+    |vpiLeftRange:
+    \_operation: , line:14:8, endln:14:20
+      |vpiParent:
+      \_range: , line:14:7, endln:14:23
+      |vpiOpType:11
+      |vpiOperand:
+      \_ref_obj: (ADDRWIDTHA), line:14:8, endln:14:18
+        |vpiParent:
+        \_operation: , line:14:8, endln:14:20
+        |vpiName:ADDRWIDTHA
+      |vpiOperand:
+      \_constant: , line:14:19, endln:14:20
+        |vpiParent:
+        \_operation: , line:14:8, endln:14:20
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:14:21, endln:14:22
+      |vpiParent:
+      \_range: , line:14:7, endln:14:23
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:15:7, endln:15:23
+  |vpiRange:
+  \_range: , line:15:7, endln:15:23
+    |vpiParent:
+    \_logic_typespec: , line:15:7, endln:15:23
+    |vpiLeftRange:
+    \_operation: , line:15:8, endln:15:20
+      |vpiParent:
+      \_range: , line:15:7, endln:15:23
+      |vpiOpType:11
+      |vpiOperand:
+      \_ref_obj: (ADDRWIDTHB), line:15:8, endln:15:18
+        |vpiParent:
+        \_operation: , line:15:8, endln:15:20
+        |vpiName:ADDRWIDTHB
+      |vpiOperand:
+      \_constant: , line:15:19, endln:15:20
+        |vpiParent:
+        \_operation: , line:15:8, endln:15:20
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:15:21, endln:15:22
+      |vpiParent:
+      \_range: , line:15:7, endln:15:23
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:16:7, endln:16:19
+  |vpiRange:
+  \_range: , line:16:7, endln:16:19
+    |vpiParent:
+    \_logic_typespec: , line:16:7, endln:16:19
+    |vpiLeftRange:
+    \_operation: , line:16:8, endln:16:16
+      |vpiParent:
+      \_range: , line:16:7, endln:16:19
+      |vpiOpType:11
+      |vpiOperand:
+      \_ref_obj: (WIDTHA), line:16:8, endln:16:14
+        |vpiParent:
+        \_operation: , line:16:8, endln:16:16
+        |vpiName:WIDTHA
+      |vpiOperand:
+      \_constant: , line:16:15, endln:16:16
+        |vpiParent:
+        \_operation: , line:16:8, endln:16:16
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:16:17, endln:16:18
+      |vpiParent:
+      \_range: , line:16:7, endln:16:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:18:8, endln:18:20
+  |vpiRange:
+  \_range: , line:18:8, endln:18:20
+    |vpiParent:
+    \_logic_typespec: , line:18:8, endln:18:20
+    |vpiLeftRange:
+    \_operation: , line:18:9, endln:18:17
+      |vpiParent:
+      \_range: , line:18:8, endln:18:20
+      |vpiOpType:11
+      |vpiOperand:
+      \_ref_obj: (WIDTHA), line:18:9, endln:18:15
+        |vpiParent:
+        \_operation: , line:18:9, endln:18:17
+        |vpiName:WIDTHA
+      |vpiOperand:
+      \_constant: , line:18:16, endln:18:17
+        |vpiParent:
+        \_operation: , line:18:9, endln:18:17
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:18:18, endln:18:19
+      |vpiParent:
+      \_range: , line:18:8, endln:18:20
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:17:7, endln:17:19
+  |vpiRange:
+  \_range: , line:17:7, endln:17:19
+    |vpiParent:
+    \_logic_typespec: , line:17:7, endln:17:19
+    |vpiLeftRange:
+    \_operation: , line:17:8, endln:17:16
+      |vpiParent:
+      \_range: , line:17:7, endln:17:19
+      |vpiOpType:11
+      |vpiOperand:
+      \_ref_obj: (WIDTHB), line:17:8, endln:17:14
+        |vpiParent:
+        \_operation: , line:17:8, endln:17:16
+        |vpiName:WIDTHB
+      |vpiOperand:
+      \_constant: , line:17:15, endln:17:16
+        |vpiParent:
+        \_operation: , line:17:8, endln:17:16
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:17:17, endln:17:18
+      |vpiParent:
+      \_range: , line:17:7, endln:17:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:19:8, endln:19:20
+  |vpiRange:
+  \_range: , line:19:8, endln:19:20
+    |vpiParent:
+    \_logic_typespec: , line:19:8, endln:19:20
+    |vpiLeftRange:
+    \_operation: , line:19:9, endln:19:17
+      |vpiParent:
+      \_range: , line:19:8, endln:19:20
+      |vpiOpType:11
+      |vpiOperand:
+      \_ref_obj: (WIDTHB), line:19:9, endln:19:15
+        |vpiParent:
+        \_operation: , line:19:9, endln:19:17
+        |vpiName:WIDTHB
+      |vpiOperand:
+      \_constant: , line:19:16, endln:19:17
+        |vpiParent:
+        \_operation: , line:19:9, endln:19:17
+        |vpiDecompile:1
+        |vpiSize:64
+        |UINT:1
+        |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:19:18, endln:19:19
+      |vpiParent:
+      \_range: , line:19:8, endln:19:20
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_int_typespec: , line:3:1, endln:3:21
+  |vpiParent:
+  \_ref_typespec: (work@asym_ram_tdp_write_first_dc.WIDTHB)
+\_int_typespec: , line:4:1, endln:4:23
+  |vpiParent:
+  \_ref_typespec: (work@asym_ram_tdp_write_first_dc.SIZEB)
+\_int_typespec: , line:5:1, endln:5:26
+  |vpiParent:
+  \_ref_typespec: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHB)
+\_int_typespec: , line:6:1, endln:6:22
+  |vpiParent:
+  \_ref_typespec: (work@asym_ram_tdp_write_first_dc.WIDTHA)
+\_int_typespec: , line:7:1, endln:7:22
+  |vpiParent:
+  \_ref_typespec: (work@asym_ram_tdp_write_first_dc.SIZEA)
+\_int_typespec: , line:8:1, endln:8:25
+  |vpiParent:
+  \_ref_typespec: (work@asym_ram_tdp_write_first_dc.ADDRWIDTHA)
+===================
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 0
+[   NOTE] : 6
diff --git a/tests/BlockingAssignRewrite/BlockingAssignRewrite.sl b/tests/BlockingAssignRewrite/BlockingAssignRewrite.sl
new file mode 100644
index 0000000000..dc1636045b
--- /dev/null
+++ b/tests/BlockingAssignRewrite/BlockingAssignRewrite.sl
@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -synth -d ast dut.sv -nobuiltin
diff --git a/tests/BlockingAssignRewrite/dut.sv b/tests/BlockingAssignRewrite/dut.sv
new file mode 100644
index 0000000000..2d78478710
--- /dev/null
+++ b/tests/BlockingAssignRewrite/dut.sv
@@ -0,0 +1,79 @@
+module asym_ram_tdp_write_first_dc (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
+
+parameter WIDTHB = 4;
+parameter SIZEB = 1024;
+parameter ADDRWIDTHB = 10;
+parameter WIDTHA = 16;
+parameter SIZEA = 256;
+parameter ADDRWIDTHA = 8;
+
+input clkA;
+input clkB;
+input weA, weB;
+input enaA, enaB;
+input [ADDRWIDTHA-1:0] addrA;
+input [ADDRWIDTHB-1:0] addrB;
+input [WIDTHA-1:0] diA;
+input [WIDTHB-1:0] diB;
+output [WIDTHA-1:0] doA;
+output [WIDTHB-1:0] doB;
+
+`define max(a,b) {(a) > (b) ? (a) : (b)}
+`define min(a,b) {(a) < (b) ? (a) : (b)}
+
+function integer log2;
+input integer value;
+reg [31:0] shifted;
+integer res;
+begin
+    if (value < 2)
+        log2 = value;
+    else
+    begin
+        shifted = value-1;
+            for (res=0; shifted>0; res=res+1)
+                shifted = shifted>>1;
+                log2 = res;
+    end
+end
+endfunction
+
+localparam maxSIZE = `max(SIZEA, SIZEB);
+localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+localparam minWIDTH = `min(WIDTHA, WIDTHB);
+localparam RATIO = maxWIDTH / minWIDTH;
+localparam log2RATIO = log2(RATIO);
+
+reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+reg [WIDTHA-1:0] readA;
+reg [WIDTHB-1:0] readB;
+always @(posedge clkB)
+begin
+    if (enaB) 
+    begin
+        if (weB)
+            RAM[addrB] = diB;
+        readB = RAM[addrB] ;
+    end
+end
+/*
+always @(posedge clkA)
+begin : portA
+integer i;
+reg [log2RATIO-1:0] lsbaddr ;
+    for (i=0; i< RATIO; i= i+ 1) 
+    begin
+        lsbaddr = i;
+            if (enaA) 
+            begin
+                if (weA)
+                    RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
+                    readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
+            end
+    end
+end
+*/
+assign doA = readA;
+assign doB = readB;
+
+endmodule
diff --git a/third_party/UHDM b/third_party/UHDM
index e86ba8acac..57efaa067a 160000
--- a/third_party/UHDM
+++ b/third_party/UHDM
@@ -1 +1 @@
-Subproject commit e86ba8acac8e3053e1238560c56dc62299956303
+Subproject commit 57efaa067a5989e1239c1353b557774a0669c2dd
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index 8a134efc61..2631215223 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -72,9 +72,9 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 [ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 2_ahb_to_axi4.sv
-[ 62%] Generating 1_lsu_stbuf.sv
+[ 56%] Generating 1_lsu_stbuf.sv
+[ 62%] Generating 3_rvjtag_tap.sv
 [ 68%] Generating 4_dec_tlu_ctl.sv
-[ 56%] Generating 3_rvjtag_tap.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
 [ 87%] Generating 7_axi4_to_ahb.sv