From e96db9bbf687769691f8e097031c34e358b01bae Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 7 Nov 2024 12:07:52 +0100 Subject: [PATCH 1/3] Route a core_enable signal to conditionally disable internal core TAP access This integrates changes from caliptra-rtl: https://github.com/chipsalliance/caliptra-rtl/commit/22c08e12334afa5a408393155ec97c5141f3d2a7 Signed-off-by: Wojciech Sipak --- design/dmi/dmi_mux.v | 6 ++++-- design/el2_veer_wrapper.sv | 2 ++ testbench/tb_top.sv | 5 +++++ testbench/veer_wrapper.sv | 2 ++ 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/design/dmi/dmi_mux.v b/design/dmi/dmi_mux.v index b428d6442cd..1d3b1e86673 100644 --- a/design/dmi/dmi_mux.v +++ b/design/dmi/dmi_mux.v @@ -3,6 +3,8 @@ module dmi_mux ( + // Core access enable + input wire core_enable, // Uncore access enable input wire uncore_enable, @@ -33,8 +35,8 @@ module dmi_mux ( assign is_uncore_aperture = (dmi_addr[6] & (dmi_addr[5] | dmi_addr[4])); // Core signals - assign dmi_core_en = dmi_en & ~is_uncore_aperture; - assign dmi_core_wr_en = dmi_wr_en & ~is_uncore_aperture; + assign dmi_core_en = dmi_en & ~is_uncore_aperture & core_enable; + assign dmi_core_wr_en = dmi_wr_en & ~is_uncore_aperture & core_enable; assign dmi_core_addr = dmi_addr; assign dmi_core_wdata = dmi_wdata; diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index d331503d685..22c9bc165c1 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -435,6 +435,7 @@ import el2_pkg::*; input logic mbist_mode, // to enable mbist // DMI port for uncore + input logic dmi_core_enable, input logic dmi_uncore_enable, output logic dmi_uncore_en, output logic dmi_uncore_wr_en, @@ -907,6 +908,7 @@ import el2_pkg::*; // DMI core/uncore mux dmi_mux dmi_mux ( + .core_enable (dmi_core_enable), .uncore_enable (dmi_uncore_enable), .dmi_en (dmi_en), diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 70d0877b585..601d99e1a75 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -156,6 +156,10 @@ module tb_top logic [11:0] wb_csr_dest; logic [31:0] wb_csr_data; + logic dmi_core_enable; + + always_comb dmi_core_enable = ~(o_cpu_halt_status); + `ifdef RV_OPENOCD_TEST // SB and LSU AHB master mux ahb_lite_2to1_mux #( @@ -1302,6 +1306,7 @@ veer_wrapper rvtop_wrapper ( .scan_mode ( 1'b0 ), // To enable scan mode .mbist_mode ( 1'b0 ), // to enable mbist + .dmi_core_enable (dmi_core_enable), .dmi_uncore_enable (), .dmi_uncore_en (), .dmi_uncore_wr_en (), diff --git a/testbench/veer_wrapper.sv b/testbench/veer_wrapper.sv index ff9a956f0e8..967ddc29928 100644 --- a/testbench/veer_wrapper.sv +++ b/testbench/veer_wrapper.sv @@ -350,6 +350,7 @@ module veer_wrapper input logic scan_mode, // To enable scan mode input logic mbist_mode, // to enable mbist + input logic dmi_core_enable, // DMI port for uncore input logic dmi_uncore_enable, output logic dmi_uncore_en, @@ -378,6 +379,7 @@ module veer_wrapper el2_veer_wrapper rvtop ( .el2_mem_export(mem_export.veer_sram_src), + .dmi_core_enable(dmi_core_enable), .* ); From 85fdbb8cb06dec1a59348f7d0a0c498c9b995a01 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 7 Nov 2024 12:12:36 +0100 Subject: [PATCH 2/3] Add a dmi_active output signal This integrates changes from caliptra-rtl: https://github.com/chipsalliance/caliptra-rtl/commit/41173449344e8270515cde48aae5dc7a90f3ce10 Signed-off-by: Wojciech Sipak --- design/el2_veer_wrapper.sv | 5 ++++- testbench/tb_top.sv | 3 ++- testbench/veer_wrapper.sv | 5 ++++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index 22c9bc165c1..34e80334e6e 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -441,7 +441,8 @@ import el2_pkg::*; output logic dmi_uncore_wr_en, output logic [ 6:0] dmi_uncore_addr, output logic [31:0] dmi_uncore_wdata, - input logic [31:0] dmi_uncore_rdata + input logic [31:0] dmi_uncore_rdata, + output logic dmi_active /* verilator coverage_on */ ); @@ -930,6 +931,8 @@ import el2_pkg::*; .dmi_uncore_rdata (dmi_uncore_rdata) ); + always_comb dmi_active = dmi_en; + `ifdef RV_ASSERT_ON // to avoid internal assertions failure at time 0 initial begin diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 601d99e1a75..594bedc77fe 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -1312,7 +1312,8 @@ veer_wrapper rvtop_wrapper ( .dmi_uncore_wr_en (), .dmi_uncore_addr (), .dmi_uncore_wdata (), - .dmi_uncore_rdata () + .dmi_uncore_rdata (), + .dmi_active () ); diff --git a/testbench/veer_wrapper.sv b/testbench/veer_wrapper.sv index 967ddc29928..2a3dcfa7ba8 100644 --- a/testbench/veer_wrapper.sv +++ b/testbench/veer_wrapper.sv @@ -357,7 +357,9 @@ module veer_wrapper output logic dmi_uncore_wr_en, output logic [ 6:0] dmi_uncore_addr, output logic [31:0] dmi_uncore_wdata, - input logic [31:0] dmi_uncore_rdata + input logic [31:0] dmi_uncore_rdata, + + output logic dmi_active ); el2_mem_if mem_export (); @@ -380,6 +382,7 @@ module veer_wrapper el2_veer_wrapper rvtop ( .el2_mem_export(mem_export.veer_sram_src), .dmi_core_enable(dmi_core_enable), + .dmi_active(dmi_active), .* ); From 2d868166ce389e51e65f03577759ad1bb9ab1624 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 7 Nov 2024 14:38:12 +0100 Subject: [PATCH 3/3] use core_enable in dmi test wrapper Signed-off-by: Wojciech Sipak --- verification/block/dmi/dmi_test_wrapper.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/verification/block/dmi/dmi_test_wrapper.sv b/verification/block/dmi/dmi_test_wrapper.sv index 3237053fd1c..01285a8ca64 100644 --- a/verification/block/dmi/dmi_test_wrapper.sv +++ b/verification/block/dmi/dmi_test_wrapper.sv @@ -49,6 +49,9 @@ module dmi_test_wrapper logic [ 6:0] dmi_addr; logic [31:0] dmi_wdata; logic [31:0] dmi_rdata; + logic core_enable; + + assign core_enable = '1; assign dmi_en = reg_en; assign dmi_wr_en = reg_wr_en;