Inconsistency in ROM AHB-Lite bus connectivity between Caliptra Main Specification and Integration Specification

[myviewfinder]

Incomplete and discrepancy about Caliptra ROM integration requirements.

1. Inconsistencies between:

• Main spec Figure 8: Caliptra Core block diagram with AHB-Lite connecting to its ROM, vs
• Integration Specification Figure 1: SoC Interface Block Diagram, ROM and its AHB-Lite interface are missing.

2. Missing ROM AHB-Lite interface in the Caliptra Main specification & [Caliptra Integration Spec's Interface section] (https://github.com/chipsalliance/caliptra-rtl/blob/main/docs/CaliptraIntegrationSpecification.md#interface).
   Or are the interface signals imem_cs/imem_addr/imem_data in Table 8: SRAM interface meant for connecting the Caliptra ROM?

3. Search for "imem" in soc_ifc_top.sv returns zero match. Please clarify.

4. What are imem signals intended for, if not for ROM in bullet no.2 above?

5. What is the AHB bus in Table 5 intended for, if not for ROM in bullet no.2 above?

6. Related to the answer in two bullets above, what are the supported address width and data width for the respective APB and imem interface to ROM or other usages?

7. Is there any other SoC integration requirements about Caliptra ROM?

[calebofearth]

1. Figure 1 only depicts the SoC interface connections (these are connections to the block that is used to expose an API for the SoC to interact with). ROM is not a part of the SoC interface, so it is omitted from this diagram, although it is still connected to the RiscV.
2. imem (Instruction Memory) is the ROM.
3. imem is instantiated in caliptra_top.sv.
4. imem is the ROM
5. Table 5 shows an APB interface, not an AHB interface. This is the interface connected to the SoC, which is used by the SoC for various API flows, including Fuse programming, mailbox operation, error/status handling, TRNG requests, etc.
6. config_defines.svh shows the address and data width configured for APB. Data width = 32 bits, Address width = 32. ROM size is hard-coded to 48KiB, and signal size must be left as configured in caliptra_top.
7. ROM is an internal Caliptra component and must not be modified from the provided configuration. However, the memory control signals are exported from caliptra_top (as described here https://github.com/chipsalliance/caliptra-rtl/blob/main/docs/CaliptraIntegrationSpecification.md#overview-2) and it is the integrator's responsibility to instantiate the memory and connect it to the imem signals.