powergood and CPTRA_OBF_KEY discrepancy and typo

[myviewfinder]

1. Given the following 2 Caliptra Integration Specification requirements about powergood and CPTRA_OBF_KEY as background. Please kindly provide suggestion/option in the Caliptra Integration Specification when SoC is not ready to provide the Caliptra input strap "CPTRA_OBF_KEY" yet, among other Caliptra input signals, during SoC power good assertion (active hi). I.e. can cptra_pwrgood signal != SoC powergood signal but other option...?
   In fact, Figure 5: Device manufacturing identity flow shows some SoC activities (SoC infrastructure bring up, SoC specific UDS Program Flow, etc) prior to the "cptra_pwrgood assert" arrow, implying that the cptra_pwrgood signal != SoC powergood.

Section SoC integration requirements
Table 17: SoC integration requirements, row "Resets and Clocks"

SoC shall ensure Caliptra's powergood is tied to SoC’s own powergood or any other reset that triggers SoC’s cold boot flow.

Section Interface
Table 11: Security and miscellaneous, row CPTRA_OBF_KEY

The key is latched by Caliptra on caliptra powergood deassertion. It is cleared after its use and can only re-latched on a power cycle (powergood deassertion to assertion).

2. Is it a polarity typo in Table 11 first sentence's latching requirement description above? Does the first sentence intend to say CPTRA_OBF_KEY input strap is being "latched by Caliptra on cptra_pwrgood assertion", i.e. = logic '1' level since it is an active high signal?

3. The Caliptra Integration specification Strap section defines multiple latching/sampling requirements than that in the Interface section. Please kindly fix the input signal latching requirement(s) and timing consistency across various Caliptra specifications and sections, including Figure 5: Device manufacturing identity flow .
   
   Section Straps

Straps are signal inputs to Caliptra that are sampled once on reset exit, and the latched value persists throughout the remaining uptime of the system. Straps are sampled on either caliptra pwrgood signal deassertion or cptra_noncore_rst_b deassertion – refer to interface table for list of straps.