© 2019 Abner Chang, Hewlett Packard Enterprise <[email protected]>
Refer to ACPI specification for the license and copyright details.
MADT is a ACPI table whcich provides the interrupt model information of particular
interrupt controller implementation. Please check ACPI spec v6.3 section 5.2.12 for
the details.
The contents mentinoed here is the proposal of ACPI specification change
for adding RISC-V PLIC to ACPI MADT table.
Table 5-46 Interrupt Controller Structure Types
Value |
Description |
_MAT for Processor object |
_MAT for an I/O APIC object |
Reference |
0x10 |
RISC-V Platform Level Interrupt Controller (PLIC) |
no |
no |
Section 5.2.12.19 |
PLIC is used as platform global external interrupt controller for RISC-V platforms. PLIC can be connected
to RISC-V processor and the Harts in the processor according to the platform design. Multiple PLIC
structures is possible reported in MDAT for multiple RISC-V physical processor on platform.
The Hart ID the interrupt source is connected and the Privilege Mode which triggered by interrupt source
is platform implementation-specific, which is out of ACPI specification scope. This infomation is reported in Hart Context
Interrupt Description (HCID) sub-table described below.
The properties of interrupt event source and settings of PLIC should be configured by system firmware during
POST according to the platform design. The settings of PLIC must be reported in MADT PLIC structure
by system firmware. ACPI compliant OS can install the corresponding interrupt handler for handling
Supervisor Mode external interrupts. In the case if external interrupt is triggered as Machine Mode
external interrupt and the Machine Mode external interrupt is not delegated to Supervisor Mode according
to ACPI SDEI table, OS will have to register event handler on Machine Mode external interrupt using
Supervisor Binary Interface.
Table 5-67 PLIC Structure
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
0x10 PLIC structure |
Length |
1 |
1 |
28 + n + n * x (See below description) |
PLIC Version |
1 |
2 |
The version of this PLIC |
Processor UID |
1 |
3 |
Processor UID, this value matches to _UID value in ACPI processor device object. This also means the processor core index. |
PLIC Base Address |
8 |
4 |
64-bit physical base address of PLIC registers, this also the identifier of PLIC instance. |
Total External Interrupt Sources Supported in this PLIC |
2 |
12 |
Number of external interrupts supported on this PLIC. |
Number of Harts Connected with PLIC |
1 |
14 |
Number of Harts which are connected by PLIC. The value declared in this filed is equal to the “n” in next field. |
PLIC Target Hart ID [n] |
n |
15 |
An array of Hart ID in which are connected by PLIC. |
Global System Interrupt Vector Base |
2 |
15 + n |
Base interrupt number of Global System Interrupt of this PLIC. Refer to section 5.2.13 for Global System Interrupts |
Maximum Interrupt Priority Levels |
1 |
16 + n |
Number of interrupt priority levels supported by this PLIC. A value of zero permit all interrupts with non-zero priority. The maximum interrupt priority is 255. |
Starting Offset to Interrupt Source Priority block |
4 |
18 + n |
The relative offset to PLIC physical base address, which points to interrupt priority block of interrupt sources supported by this PLIC core. Value of zero means no interrupt priority supported in PLIC. |
Length in Bits of each Interrupt Source Priority |
2 |
22 + n |
Length in bits of interrupt source priority. |
Starting Offset to Interrupt Pending Bits Block |
4 |
24 + n |
The relative offset to PLIC physical base address which points to interrupt pending block. Value of zero means no interrupt pending bits supported in PLIC core. |
Starting Offset to Interrupt Edge/Level Trigger block |
4 |
28 + n |
The relative offset to PLIC physical base address, which points to interrupt trigger mode register block of interrupt sources supported by this PLIC core. Value of zero means no interrupt trigger mode supported in PLIC. |
Number of Hart Context Interrupt Description Structures |
1 |
32 + n |
Number of Hart context interrupt structures follow PLIC structure. See Table 5-68. |
Hart Context Interrupt Description (HCID) Structures |
n * x |
23 + n |
The first HCID structure. Total length in byte for each HCID is referred as “x”. |
Table 5-68 PLIC HCID Structure
Field |
Byte Length |
*Byte Offset * |
Description |
HCID ID |
2 |
0 |
The identifier of this HCID. |
Hart ID |
1 |
2 |
ID of Hart owns these interrupt sources. The value specified in this field must be one of value in PLIC Target Hart ID [n] in Table 5-67 PLIC structure. |
Privilege Level |
1 |
3 |
The privilege levels of this Hart. |
Starting Offset to Interrupt Enable Bits Block |
4 |
4 |
The relative offset to PLIC physical address which points to interrupt enable bits block. Value of zero means no interrupt enable bits supported in PLIC. The interrupt enable bits block is used to enable specific interrupt source for the Hart specified in Hart ID and Privilege Mode specified in Privilege Level in this table (PLIC HCID Structure) |
Offset to the Interrupt Priority Threshold |
4 |
8 |
The relative offset to PLIC physical address which points to interrupt priority threshold of the Hart specified in Hart ID and Privilege Mode specified in Privilege Level in this table (PLIC HCID Structure). The valid value is in the range of Maximum Interrupt Priority Levels in Table 5-67 PLIC structure. The bit length of interrupt priority is specified in Length in Bits of each Interrupt Source Priority in Table 5-67 PLIC structure. |
Offset to Interrupt Claim/Complete |
4 |
12 |
The relative offset to PLIC physical address which points to interrupt Claim/Complete register of the Hart specified in Hart ID and Privilege Mode specified in Privilege Level in this table (PLIC HCID Structure). |
