diff --git a/verilog/ALU.v b/verilog/ALU.v deleted file mode 100644 index 1c0ecc8..0000000 --- a/verilog/ALU.v +++ /dev/null @@ -1,40 +0,0 @@ -module Add_unit(data1,data2,result); - input [31:0] data1; - input [31:0] data2; - output [31:0] result; - reg [31:0] result; - always @(*) begin - result = data1 + data2; - end -endmodule - -module XOR_unit(data1,data2,result); - input [31:0] data1; - input [31:0] data2; - output [31:0] result; - reg [31:0] result; - always @(*) begin - result = data1 ^ data2; - end -endmodule - -module AND_unit(data1,data2,result); - input [31:0] data1; - input [31:0] data2; - output [31:0] result; - reg [31:0] result; - always @(*) begin - result = data1 & data2; - end -endmodule - -module OR_unit(data1,data2,result); - input [31:0] data1; - input [31:0] data2; - output [31:0] result; - reg [31:0] result; - always @(*) begin - result = data1 | data2; - end -endmodule - diff --git a/verilog/ALU/ALU.v b/verilog/ALU/ALU.v new file mode 100644 index 0000000..d054671 --- /dev/null +++ b/verilog/ALU/ALU.v @@ -0,0 +1,187 @@ +module Add_unit(data1,data2,result); + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + + assign result = data1 + data2; +endmodule + +module XOR_unit(data1,data2,result); + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + assign result = data1 ^ data2; +endmodule + +module AND_unit(data1,data2,result); + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + assign result = data1 & data2; +endmodule + +module OR_unit(data1,data2,result); + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + + assign result = data1 | data2; +endmodule + +module MUL_unit(data1,data2,result); //multplication of high instruction MULH + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + + reg [64:0] result1; + always @(*) begin + result1 = $signed(data1) * $signed(data2); + end + assign result = result1[31:0]; +endmodule + +module MULH_unit(data1,data2,result); //multplication of high instruction MULH + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + reg [64:0] result1; + always @(*) begin + result1 = $signed(data1) * $signed(data2); + + end + assign result = result1[63:32]; +endmodule + +module MULHU_unit(data1,data2,result); //multplication of high instruction MULHU (unsigned values) + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + reg [63:0] result1; + + always @(*) begin + result1 = $unsigned(data1) * $unsigned(data2); + end + assign result = result[63:32]; +endmodule + +module MULHSU_unit(data1,data2,result); //multplication of high instruction MULHSU (signed and unsigned values) + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + reg [63:0] result1; + always @(*) begin + result1 = $signed(data1) * $unsigned(data2); + end + assign result = result1[63:32]; +endmodule + +module DIV_unit(data1,data2,result); //division instruction signed values + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + + assign result = $signed(data1) / $signed(data2); +endmodule + +module DIVU_unit(data1,data2,result); //division instruction unsigned values + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + + assign result = $unsigned(data1) / $unsigned(data2); + +endmodule + +module REM_unit(data1,data2,result); //remainder instruction signed values + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + + assign result = $signed(data1) % $signed(data2); +endmodule + +module REMU_unit(data1,data2,result); //remainder instruction unsigned values + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + assign result = $unsigned(data1) % $unsigned(data2); +endmodule + +module Forward_Unit(data2,result); + input [31:0] data2; + output [31:0] result; + assign result = data2; +endmodule + +module SLL_Unit(data1,data2,result);// logical left (to get logical write data 2 will be negative) + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + assign result = data1 << data2; +endmodule + +module SRA_Unit(data1,data2,result);// logical right (to get logical write data 2 will be negative) + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + assign result = $signed(data1) >> data2; +endmodule + +module SLT_Unit(data1,data2,result);// set less than + input [31:0] data1; + input [31:0] data2; + output [31:0] result; + + assign result = (data1 < data2) ? 32'b1 : 32'b0; + +endmodule + +module ALU_unit(Opcode, data1, data2, result); + input [4:0] Opcode; + input [31:0] data1; + input [31:0] data2; + + output reg [31:0] result; + + wire [31:0] result00, result01, result02, result03, result04, result05, result06, result07, result08, result09, result10, result11, result12, result13, result14, result15; + + Add_unit add_unit(data1, data2, result00); + XOR_unit xor_unit(data1, data2, result01); + AND_unit and_unit(data1, data2, result02); + OR_unit or_unit(data1, data2, result03); + MUL_unit mul_unit(data1, data2, result04); + MULH_unit mulh_unit(data1, data2, result05); + MULHU_unit mulhu_unit(data1, data2, result06); + MULHSU_unit mulhsu_unit(data1, data2, result07); + DIV_unit div_unit(data1, data2, result08); + DIVU_unit divu_unit(data1, data2, result09); + REM_unit rem_unit(data1, data2, result10); + REMU_unit remu_unit(data1, data2, result11); + Forward_Unit forward_unit(data2, result12); + SLL_Unit sll_unit(data1, data2, result13); + SRA_Unit sra_unit(data1, data2, result14); + SLT_Unit slt_unit(data1, data2, result15); + + //mux for selecting the result + always @(*) begin + case(Opcode) + 5'b00000: result = result00; // add + 5'b00001: result = result01; // xor + 5'b00010: result = result02; // and + 5'b00011: result = result03; // or + 5'b00100: result = result04; // mul + 5'b00101: result = result05; // mulh + 5'b00110: result = result06; // mulhu + 5'b00111: result = result07; // mulhsu + 5'b01000: result = result08; // div + 5'b01001: result = result09; // divu + 5'b01010: result = result10; // rem + 5'b01011: result = result11; // remu + 5'b01100: result = result12; // forward + 5'b01101: result = result13; // sll + 5'b01110: result = result14; // sra + 5'b01111: result = result15; // slt + default: result = 32'bx; + endcase + end +endmodule \ No newline at end of file diff --git a/verilog/ALU/ALU.v.out b/verilog/ALU/ALU.v.out new file mode 100644 index 0000000..009bd8f --- /dev/null +++ b/verilog/ALU/ALU.v.out @@ -0,0 +1,385 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "D:\verilog\iverilog\lib\ivl\system.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\va_math.vpi"; +S_0000022eb4275b90 .scope module, "ALU_unit" "ALU_unit" 2 139; + .timescale 0 0; + .port_info 0 /INPUT 5 "Opcode"; + .port_info 1 /INPUT 32 "data1"; + .port_info 2 /INPUT 32 "data2"; + .port_info 3 /OUTPUT 32 "result"; +o0000022eb429ed38 .functor BUFZ 5, C4; HiZ drive +v0000022eb42f6520_0 .net "Opcode", 4 0, o0000022eb429ed38; 0 drivers +o0000022eb429dfb8 .functor BUFZ 32, C4; HiZ drive +v0000022eb42f5440_0 .net "data1", 31 0, o0000022eb429dfb8; 0 drivers +o0000022eb429dfe8 .functor BUFZ 32, C4; HiZ drive +v0000022eb42f6840_0 .net "data2", 31 0, o0000022eb429dfe8; 0 drivers +v0000022eb42f65c0_0 .var "result", 31 0; +v0000022eb42f6660_0 .net "result00", 31 0, L_0000022eb42f9e00; 1 drivers +v0000022eb42f6700_0 .net "result01", 31 0, L_0000022eb426fb50; 1 drivers +v0000022eb42f6980_0 .net "result02", 31 0, L_0000022eb426fca0; 1 drivers +v0000022eb42f6a20_0 .net "result03", 31 0, L_0000022eb426fae0; 1 drivers +v0000022eb42f6d40_0 .net "result04", 31 0, L_0000022eb42f9cc0; 1 drivers +v0000022eb42f6de0_0 .net "result05", 31 0, L_0000022eb42f86e0; 1 drivers +L_0000022eb4330088 .functor BUFT 1, C4, C4<0>, C4<0>, C4<0>; +v0000022eb42f6c00_0 .net "result06", 31 0, L_0000022eb4330088; 1 drivers +v0000022eb42f6ac0_0 .net "result07", 31 0, L_0000022eb42f9f40; 1 drivers +v0000022eb42f6ca0_0 .net "result08", 31 0, L_0000022eb42f9c20; 1 drivers +v0000022eb42f6f20_0 .net "result09", 31 0, L_0000022eb42f9220; 1 drivers +v0000022eb42f5080_0 .net "result10", 31 0, L_0000022eb42f8320; 1 drivers +v0000022eb42f54e0_0 .net "result11", 31 0, L_0000022eb42f9d60; 1 drivers +v0000022eb42f5620_0 .net "result12", 31 0, L_0000022eb426fbc0; 1 drivers +v0000022eb42f9360_0 .net "result13", 31 0, L_0000022eb42f9ea0; 1 drivers +v0000022eb42f8d20_0 .net "result14", 31 0, L_0000022eb42f8280; 1 drivers +v0000022eb42f9680_0 .net "result15", 31 0, L_0000022eb42f9ae0; 1 drivers +E_0000022eb42722c0/0 .event anyedge, v0000022eb42f6520_0, v0000022eb429c9e0_0, v0000022eb42f5bc0_0, v0000022eb429bfe0_0; +E_0000022eb42722c0/1 .event anyedge, v0000022eb42f5c60_0, v0000022eb429c760_0, v0000022eb429c120_0, v0000022eb42f6200_0; +E_0000022eb42722c0/2 .event anyedge, v0000022eb42f6b60_0, v0000022eb429c8a0_0, v0000022eb429c260_0, v0000022eb42f5260_0; +E_0000022eb42722c0/3 .event anyedge, v0000022eb42f5940_0, v0000022eb429cee0_0, v0000022eb42f5580_0, v0000022eb42f5b20_0; +E_0000022eb42722c0/4 .event anyedge, v0000022eb42f62a0_0; +E_0000022eb42722c0 .event/or E_0000022eb42722c0/0, E_0000022eb42722c0/1, E_0000022eb42722c0/2, E_0000022eb42722c0/3, E_0000022eb42722c0/4; +S_0000022eb4275d20 .scope module, "add_unit" "Add_unit" 2 148, 2 1 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb429c580_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb429c620_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb429c9e0_0 .net "result", 31 0, L_0000022eb42f9e00; alias, 1 drivers +L_0000022eb42f9e00 .arith/sum 32, o0000022eb429dfb8, o0000022eb429dfe8; +S_0000022eb42883a0 .scope module, "and_unit" "AND_unit" 2 150, 2 16 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +L_0000022eb426fca0 .functor AND 32, o0000022eb429dfb8, o0000022eb429dfe8, C4<11111111111111111111111111111111>, C4<11111111111111111111111111111111>; +v0000022eb429cc60_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb429c440_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb429bfe0_0 .net "result", 31 0, L_0000022eb426fca0; alias, 1 drivers +S_0000022eb4288530 .scope module, "div_unit" "DIV_unit" 2 156, 2 78 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb429ca80_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb429c4e0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb429c8a0_0 .net "result", 31 0, L_0000022eb42f9c20; alias, 1 drivers +L_0000022eb42f9c20 .arith/div.s 32, o0000022eb429dfb8, o0000022eb429dfe8; +S_0000022eb42898e0 .scope module, "divu_unit" "DIVU_unit" 2 157, 2 86 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb429c6c0_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb429c1c0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb429c260_0 .net "result", 31 0, L_0000022eb42f9220; alias, 1 drivers +L_0000022eb42f9220 .arith/div 32, o0000022eb429dfb8, o0000022eb429dfe8; +S_0000022eb4289a70 .scope module, "forward_unit" "Forward_Unit" 2 160, 2 110 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data2"; + .port_info 1 /OUTPUT 32 "result"; +L_0000022eb426fbc0 .functor BUFZ 32, o0000022eb429dfe8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0000022eb429c3a0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb429cee0_0 .net "result", 31 0, L_0000022eb426fbc0; alias, 1 drivers +S_0000022eb4287e70 .scope module, "mul_unit" "MUL_unit" 2 152, 2 31 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb429c080_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb429cda0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb429c760_0 .net "result", 31 0, L_0000022eb42f9cc0; alias, 1 drivers +v0000022eb429c940_0 .var "result1", 64 0; +E_0000022eb4271dc0 .event anyedge, v0000022eb429c580_0, v0000022eb429c620_0; +L_0000022eb42f9cc0 .part v0000022eb429c940_0, 0, 32; +S_0000022eb4288000 .scope module, "mulh_unit" "MULH_unit" 2 153, 2 43 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb429cbc0_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb429ce40_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb429c120_0 .net "result", 31 0, L_0000022eb42f86e0; alias, 1 drivers +v0000022eb42f5120_0 .var "result1", 64 0; +L_0000022eb42f86e0 .part v0000022eb42f5120_0, 32, 32; +S_0000022eb4281a80 .scope module, "mulhsu_unit" "MULHSU_unit" 2 155, 2 67 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb42f6340_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f5800_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f6b60_0 .net "result", 31 0, L_0000022eb42f9f40; alias, 1 drivers +v0000022eb42f5d00_0 .var "result1", 63 0; +L_0000022eb42f9f40 .part v0000022eb42f5d00_0, 32, 32; +S_0000022eb4281c10 .scope module, "mulhu_unit" "MULHU_unit" 2 154, 2 55 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb42f5a80_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f60c0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f6200_0 .net "result", 31 0, L_0000022eb4330088; alias, 1 drivers +v0000022eb42f67a0_0 .var "result1", 63 0; +S_0000022eb4284be0 .scope module, "or_unit" "OR_unit" 2 151, 2 23 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +L_0000022eb426fae0 .functor OR 32, o0000022eb429dfb8, o0000022eb429dfe8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0000022eb42f58a0_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f56c0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f5c60_0 .net "result", 31 0, L_0000022eb426fae0; alias, 1 drivers +S_0000022eb4284d70 .scope module, "rem_unit" "REM_unit" 2 158, 2 95 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb42f5760_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f5da0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f5260_0 .net "result", 31 0, L_0000022eb42f8320; alias, 1 drivers +L_0000022eb42f8320 .arith/mod.s 32, o0000022eb429dfb8, o0000022eb429dfe8; +S_0000022eb422e010 .scope module, "remu_unit" "REMU_unit" 2 159, 2 103 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb42f68e0_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f5e40_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f5940_0 .net "result", 31 0, L_0000022eb42f9d60; alias, 1 drivers +L_0000022eb42f9d60 .arith/mod 32, o0000022eb429dfb8, o0000022eb429dfe8; +S_0000022eb422e1a0 .scope module, "sll_unit" "SLL_Unit" 2 161, 2 116 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb42f63e0_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f51c0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f5580_0 .net "result", 31 0, L_0000022eb42f9ea0; alias, 1 drivers +L_0000022eb42f9ea0 .shift/l 32, o0000022eb429dfb8, o0000022eb429dfe8; +S_0000022eb4276f70 .scope module, "slt_unit" "SLT_Unit" 2 163, 2 130 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb42f5ee0_0 .net *"_ivl_0", 0 0, L_0000022eb42f8640; 1 drivers +L_0000022eb43300d0 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>; +v0000022eb42f5f80_0 .net/2u *"_ivl_2", 31 0, L_0000022eb43300d0; 1 drivers +L_0000022eb4330118 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0000022eb42f5300_0 .net/2u *"_ivl_4", 31 0, L_0000022eb4330118; 1 drivers +v0000022eb42f53a0_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f59e0_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f62a0_0 .net "result", 31 0, L_0000022eb42f9ae0; alias, 1 drivers +L_0000022eb42f8640 .cmp/gt 32, o0000022eb429dfe8, o0000022eb429dfb8; +L_0000022eb42f9ae0 .functor MUXZ 32, L_0000022eb4330118, L_0000022eb43300d0, L_0000022eb42f8640, C4<>; +S_0000022eb4277100 .scope module, "sra_unit" "SRA_Unit" 2 162, 2 123 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v0000022eb42f6020_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f6480_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f5b20_0 .net "result", 31 0, L_0000022eb42f8280; alias, 1 drivers +L_0000022eb42f8280 .shift/r 32, o0000022eb429dfb8, o0000022eb429dfe8; +S_0000022eb427c960 .scope module, "xor_unit" "XOR_unit" 2 149, 2 9 0, S_0000022eb4275b90; + .timescale 0 0; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +L_0000022eb426fb50 .functor XOR 32, o0000022eb429dfb8, o0000022eb429dfe8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0000022eb42f6e80_0 .net "data1", 31 0, o0000022eb429dfb8; alias, 0 drivers +v0000022eb42f6160_0 .net "data2", 31 0, o0000022eb429dfe8; alias, 0 drivers +v0000022eb42f5bc0_0 .net "result", 31 0, L_0000022eb426fb50; alias, 1 drivers + .scope S_0000022eb4287e70; +T_0 ; + %wait E_0000022eb4271dc0; + %load/vec4 v0000022eb429c080_0; + %pad/s 65; + %load/vec4 v0000022eb429cda0_0; + %pad/s 65; + %mul; + %store/vec4 v0000022eb429c940_0, 0, 65; + %jmp T_0; + .thread T_0, $push; + .scope S_0000022eb4288000; +T_1 ; + %wait E_0000022eb4271dc0; + %load/vec4 v0000022eb429cbc0_0; + %pad/s 65; + %load/vec4 v0000022eb429ce40_0; + %pad/s 65; + %mul; + %store/vec4 v0000022eb42f5120_0, 0, 65; + %jmp T_1; + .thread T_1, $push; + .scope S_0000022eb4281c10; +T_2 ; + %wait E_0000022eb4271dc0; + %load/vec4 v0000022eb42f5a80_0; + %pad/u 64; + %load/vec4 v0000022eb42f60c0_0; + %pad/u 64; + %mul; + %store/vec4 v0000022eb42f67a0_0, 0, 64; + %jmp T_2; + .thread T_2, $push; + .scope S_0000022eb4281a80; +T_3 ; + %wait E_0000022eb4271dc0; + %load/vec4 v0000022eb42f6340_0; + %pad/u 64; + %load/vec4 v0000022eb42f5800_0; + %pad/u 64; + %mul; + %store/vec4 v0000022eb42f5d00_0, 0, 64; + %jmp T_3; + .thread T_3, $push; + .scope S_0000022eb4275b90; +T_4 ; + %wait E_0000022eb42722c0; + %load/vec4 v0000022eb42f6520_0; + %dup/vec4; + %pushi/vec4 0, 0, 5; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 5; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 5; + %cmp/u; + %jmp/1 T_4.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 5; + %cmp/u; + %jmp/1 T_4.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 5; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 5; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 5; + %cmp/u; + %jmp/1 T_4.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 5; + %cmp/u; + %jmp/1 T_4.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 5; + %cmp/u; + %jmp/1 T_4.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 5; + %cmp/u; + %jmp/1 T_4.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 5; + %cmp/u; + %jmp/1 T_4.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 5; + %cmp/u; + %jmp/1 T_4.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 5; + %cmp/u; + %jmp/1 T_4.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 5; + %cmp/u; + %jmp/1 T_4.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 5; + %cmp/u; + %jmp/1 T_4.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 5; + %cmp/u; + %jmp/1 T_4.15, 6; + %pushi/vec4 4294967295, 4294967295, 32; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.0 ; + %load/vec4 v0000022eb42f6660_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.1 ; + %load/vec4 v0000022eb42f6700_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.2 ; + %load/vec4 v0000022eb42f6980_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.3 ; + %load/vec4 v0000022eb42f6a20_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.4 ; + %load/vec4 v0000022eb42f6d40_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.5 ; + %load/vec4 v0000022eb42f6de0_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.6 ; + %load/vec4 v0000022eb42f6c00_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.7 ; + %load/vec4 v0000022eb42f6ac0_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.8 ; + %load/vec4 v0000022eb42f6ca0_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.9 ; + %load/vec4 v0000022eb42f6f20_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.10 ; + %load/vec4 v0000022eb42f5080_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.11 ; + %load/vec4 v0000022eb42f54e0_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.12 ; + %load/vec4 v0000022eb42f5620_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.13 ; + %load/vec4 v0000022eb42f9360_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.14 ; + %load/vec4 v0000022eb42f8d20_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.15 ; + %load/vec4 v0000022eb42f9680_0; + %store/vec4 v0000022eb42f65c0_0, 0, 32; + %jmp T_4.17; +T_4.17 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4, $push; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "ALU.v"; diff --git a/verilog/ALU/ALU_tb.v b/verilog/ALU/ALU_tb.v new file mode 100644 index 0000000..90ec0f9 --- /dev/null +++ b/verilog/ALU/ALU_tb.v @@ -0,0 +1,29 @@ +`timescale 1ps/1ps +`include "ALU.v" + +module tb_ALU ; + reg[31:0]DATA1,DATA2; + reg[4:0]OPCODE; + wire[31:0]ALU_OUTPUT; + + integer i; + + ALU_unit test_unit(OPCODE,DATA1,DATA2,ALU_OUTPUT); // initiating the alu module + initial begin + $monitor("Time=%0t, Data1=%d, Data2=%d, Output=%d", $time, DATA1, DATA2,ALU_OUTPUT); + + + DATA1 = 32'd6; + DATA2 = 32'd3; + OPCODE = 5'd0; + + + for (i=0;i<=17;i++) + begin + OPCODE =i; + #5; + end + $finish; + end + +endmodule \ No newline at end of file diff --git a/verilog/ALU/ALU_tb.v.out b/verilog/ALU/ALU_tb.v.out new file mode 100644 index 0000000..b1ccd4a --- /dev/null +++ b/verilog/ALU/ALU_tb.v.out @@ -0,0 +1,420 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "D:\verilog\iverilog\lib\ivl\system.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\va_math.vpi"; +S_000001d690544ab0 .scope module, "tb_ALU" "tb_ALU" 2 4; + .timescale -12 -12; +v000001d6905d1e60_0 .net "ALU_OUTPUT", 31 0, v000001d6905cd7f0_0; 1 drivers +v000001d6905d2720_0 .var "DATA1", 31 0; +v000001d6905d1280_0 .var "DATA2", 31 0; +v000001d6905d1b40_0 .var "OPCODE", 4 0; +v000001d6905d1a00_0 .var/i "i", 31 0; +S_000001d690578ca0 .scope module, "test_unit" "ALU_unit" 2 11, 3 139 0, S_000001d690544ab0; + .timescale -12 -12; + .port_info 0 /INPUT 5 "Opcode"; + .port_info 1 /INPUT 32 "data1"; + .port_info 2 /INPUT 32 "data2"; + .port_info 3 /OUTPUT 32 "result"; +v000001d6905ce1f0_0 .net "Opcode", 4 0, v000001d6905d1b40_0; 1 drivers +v000001d6905cd750_0 .net "data1", 31 0, v000001d6905d2720_0; 1 drivers +v000001d6905ce510_0 .net "data2", 31 0, v000001d6905d1280_0; 1 drivers +v000001d6905cd7f0_0 .var "result", 31 0; +v000001d6905cd890_0 .net "result00", 31 0, L_000001d6905d2540; 1 drivers +v000001d6905ce010_0 .net "result01", 31 0, L_000001d6905431a0; 1 drivers +v000001d6905cee70_0 .net "result02", 31 0, L_000001d690542e90; 1 drivers +v000001d6905cd1b0_0 .net "result03", 31 0, L_000001d690542f00; 1 drivers +v000001d6905ce830_0 .net "result04", 31 0, L_000001d6905d20e0; 1 drivers +v000001d6905cded0_0 .net "result05", 31 0, L_000001d6905d2900; 1 drivers +L_000001d690600088 .functor BUFT 1, C4, C4<0>, C4<0>, C4<0>; +v000001d6905cdf70_0 .net "result06", 31 0, L_000001d690600088; 1 drivers +v000001d6905cef10_0 .net "result07", 31 0, L_000001d6905d2ea0; 1 drivers +v000001d6905ce3d0_0 .net "result08", 31 0, L_000001d6905d24a0; 1 drivers +v000001d6905ce0b0_0 .net "result09", 31 0, L_000001d6905d13c0; 1 drivers +v000001d6905ce470_0 .net "result10", 31 0, L_000001d6905d1820; 1 drivers +v000001d6905ce6f0_0 .net "result11", 31 0, L_000001d6905d2220; 1 drivers +v000001d6905cd110_0 .net "result12", 31 0, L_000001d6905432f0; 1 drivers +v000001d6905d29a0_0 .net "result13", 31 0, L_000001d6905d2cc0; 1 drivers +v000001d6905d1960_0 .net "result14", 31 0, L_000001d6905d1460; 1 drivers +v000001d6905d1aa0_0 .net "result15", 31 0, L_000001d6905d25e0; 1 drivers +E_000001d690541280/0 .event anyedge, v000001d6905ce1f0_0, v000001d690572d10_0, v000001d6905cde30_0, v000001d6905721d0_0; +E_000001d690541280/1 .event anyedge, v000001d6905ce330_0, v000001d690572810_0, v000001d690572bd0_0, v000001d6905ceab0_0; +E_000001d690541280/2 .event anyedge, v000001d6905ce970_0, v000001d690572590_0, v000001d690572450_0, v000001d6905ce790_0; +E_000001d690541280/3 .event anyedge, v000001d6905ceb50_0, v000001d690572270_0, v000001d6905cec90_0, v000001d6905cd6b0_0; +E_000001d690541280/4 .event anyedge, v000001d6905ced30_0; +E_000001d690541280 .event/or E_000001d690541280/0, E_000001d690541280/1, E_000001d690541280/2, E_000001d690541280/3, E_000001d690541280/4; +S_000001d690578e30 .scope module, "add_unit" "Add_unit" 3 148, 3 1 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d690572c70_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d690572950_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d690572d10_0 .net "result", 31 0, L_000001d6905d2540; alias, 1 drivers +L_000001d6905d2540 .arith/sum 32, v000001d6905d2720_0, v000001d6905d1280_0; +S_000001d690558410 .scope module, "and_unit" "AND_unit" 3 150, 3 16 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +L_000001d690542e90 .functor AND 32, v000001d6905d2720_0, v000001d6905d1280_0, C4<11111111111111111111111111111111>, C4<11111111111111111111111111111111>; +v000001d690572db0_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d690572130_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905721d0_0 .net "result", 31 0, L_000001d690542e90; alias, 1 drivers +S_000001d6905585a0 .scope module, "div_unit" "DIV_unit" 3 156, 3 78 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905728b0_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d690572e50_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d690572590_0 .net "result", 31 0, L_000001d6905d24a0; alias, 1 drivers +L_000001d6905d24a0 .arith/div.s 32, v000001d6905d2720_0, v000001d6905d1280_0; +S_000001d690559950 .scope module, "divu_unit" "DIVU_unit" 3 157, 3 86 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d690572310_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d690572ef0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d690572450_0 .net "result", 31 0, L_000001d6905d13c0; alias, 1 drivers +L_000001d6905d13c0 .arith/div 32, v000001d6905d2720_0, v000001d6905d1280_0; +S_000001d690559ae0 .scope module, "forward_unit" "Forward_Unit" 3 160, 3 110 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data2"; + .port_info 1 /OUTPUT 32 "result"; +L_000001d6905432f0 .functor BUFZ 32, v000001d6905d1280_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v000001d6905729f0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d690572270_0 .net "result", 31 0, L_000001d6905432f0; alias, 1 drivers +S_000001d690557ee0 .scope module, "mul_unit" "MUL_unit" 3 152, 3 31 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d690572090_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d690572770_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d690572810_0 .net "result", 31 0, L_000001d6905d20e0; alias, 1 drivers +v000001d690572a90_0 .var "result1", 64 0; +E_000001d690540900 .event anyedge, v000001d690572c70_0, v000001d690572950_0; +L_000001d6905d20e0 .part v000001d690572a90_0, 0, 32; +S_000001d690558070 .scope module, "mulh_unit" "MULH_unit" 3 153, 3 43 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d690572b30_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905724f0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d690572bd0_0 .net "result", 31 0, L_000001d6905d2900; alias, 1 drivers +v000001d6905ce290_0 .var "result1", 64 0; +L_000001d6905d2900 .part v000001d6905ce290_0, 32, 32; +S_000001d690551a80 .scope module, "mulhsu_unit" "MULHSU_unit" 3 155, 3 67 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905cd610_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cdb10_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905ce970_0 .net "result", 31 0, L_000001d6905d2ea0; alias, 1 drivers +v000001d6905ce5b0_0 .var "result1", 63 0; +L_000001d6905d2ea0 .part v000001d6905ce5b0_0, 32, 32; +S_000001d690551c10 .scope module, "mulhu_unit" "MULHU_unit" 3 154, 3 55 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905cea10_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cd9d0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905ceab0_0 .net "result", 31 0, L_000001d690600088; alias, 1 drivers +v000001d6905ce650_0 .var "result1", 63 0; +S_000001d690554c50 .scope module, "or_unit" "OR_unit" 3 151, 3 23 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +L_000001d690542f00 .functor OR 32, v000001d6905d2720_0, v000001d6905d1280_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v000001d6905cd930_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cdc50_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905ce330_0 .net "result", 31 0, L_000001d690542f00; alias, 1 drivers +S_000001d690554de0 .scope module, "rem_unit" "REM_unit" 3 158, 3 95 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905cd250_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cda70_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905ce790_0 .net "result", 31 0, L_000001d6905d1820; alias, 1 drivers +L_000001d6905d1820 .arith/mod.s 32, v000001d6905d2720_0, v000001d6905d1280_0; +S_000001d6904fe010 .scope module, "remu_unit" "REMU_unit" 3 159, 3 103 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905cdbb0_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cd2f0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905ceb50_0 .net "result", 31 0, L_000001d6905d2220; alias, 1 drivers +L_000001d6905d2220 .arith/mod 32, v000001d6905d2720_0, v000001d6905d1280_0; +S_000001d6904fe1a0 .scope module, "sll_unit" "SLL_Unit" 3 161, 3 116 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905cd390_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cebf0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905cec90_0 .net "result", 31 0, L_000001d6905d2cc0; alias, 1 drivers +L_000001d6905d2cc0 .shift/l 32, v000001d6905d2720_0, v000001d6905d1280_0; +S_000001d690546f70 .scope module, "slt_unit" "SLT_Unit" 3 163, 3 130 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905cdcf0_0 .net *"_ivl_0", 0 0, L_000001d6905d1be0; 1 drivers +L_000001d6906000d0 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>; +v000001d6905cd070_0 .net/2u *"_ivl_2", 31 0, L_000001d6906000d0; 1 drivers +L_000001d690600118 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v000001d6905cd430_0 .net/2u *"_ivl_4", 31 0, L_000001d690600118; 1 drivers +v000001d6905ce150_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cd4d0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905ced30_0 .net "result", 31 0, L_000001d6905d25e0; alias, 1 drivers +L_000001d6905d1be0 .cmp/gt 32, v000001d6905d1280_0, v000001d6905d2720_0; +L_000001d6905d25e0 .functor MUXZ 32, L_000001d690600118, L_000001d6906000d0, L_000001d6905d1be0, C4<>; +S_000001d690547100 .scope module, "sra_unit" "SRA_Unit" 3 162, 3 123 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +v000001d6905cd570_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cdd90_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905cd6b0_0 .net "result", 31 0, L_000001d6905d1460; alias, 1 drivers +L_000001d6905d1460 .shift/r 32, v000001d6905d2720_0, v000001d6905d1280_0; +S_000001d6905d0220 .scope module, "xor_unit" "XOR_unit" 3 149, 3 9 0, S_000001d690578ca0; + .timescale -12 -12; + .port_info 0 /INPUT 32 "data1"; + .port_info 1 /INPUT 32 "data2"; + .port_info 2 /OUTPUT 32 "result"; +L_000001d6905431a0 .functor XOR 32, v000001d6905d2720_0, v000001d6905d1280_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v000001d6905ce8d0_0 .net "data1", 31 0, v000001d6905d2720_0; alias, 1 drivers +v000001d6905cedd0_0 .net "data2", 31 0, v000001d6905d1280_0; alias, 1 drivers +v000001d6905cde30_0 .net "result", 31 0, L_000001d6905431a0; alias, 1 drivers + .scope S_000001d690557ee0; +T_0 ; + %wait E_000001d690540900; + %load/vec4 v000001d690572090_0; + %pad/s 65; + %load/vec4 v000001d690572770_0; + %pad/s 65; + %mul; + %store/vec4 v000001d690572a90_0, 0, 65; + %jmp T_0; + .thread T_0, $push; + .scope S_000001d690558070; +T_1 ; + %wait E_000001d690540900; + %load/vec4 v000001d690572b30_0; + %pad/s 65; + %load/vec4 v000001d6905724f0_0; + %pad/s 65; + %mul; + %store/vec4 v000001d6905ce290_0, 0, 65; + %jmp T_1; + .thread T_1, $push; + .scope S_000001d690551c10; +T_2 ; + %wait E_000001d690540900; + %load/vec4 v000001d6905cea10_0; + %pad/u 64; + %load/vec4 v000001d6905cd9d0_0; + %pad/u 64; + %mul; + %store/vec4 v000001d6905ce650_0, 0, 64; + %jmp T_2; + .thread T_2, $push; + .scope S_000001d690551a80; +T_3 ; + %wait E_000001d690540900; + %load/vec4 v000001d6905cd610_0; + %pad/u 64; + %load/vec4 v000001d6905cdb10_0; + %pad/u 64; + %mul; + %store/vec4 v000001d6905ce5b0_0, 0, 64; + %jmp T_3; + .thread T_3, $push; + .scope S_000001d690578ca0; +T_4 ; + %wait E_000001d690541280; + %load/vec4 v000001d6905ce1f0_0; + %dup/vec4; + %pushi/vec4 0, 0, 5; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 5; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 5; + %cmp/u; + %jmp/1 T_4.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 5; + %cmp/u; + %jmp/1 T_4.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 5; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 5; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 5; + %cmp/u; + %jmp/1 T_4.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 5; + %cmp/u; + %jmp/1 T_4.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 5; + %cmp/u; + %jmp/1 T_4.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 5; + %cmp/u; + %jmp/1 T_4.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 5; + %cmp/u; + %jmp/1 T_4.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 5; + %cmp/u; + %jmp/1 T_4.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 5; + %cmp/u; + %jmp/1 T_4.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 5; + %cmp/u; + %jmp/1 T_4.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 5; + %cmp/u; + %jmp/1 T_4.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 5; + %cmp/u; + %jmp/1 T_4.15, 6; + %pushi/vec4 4294967295, 4294967295, 32; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.0 ; + %load/vec4 v000001d6905cd890_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.1 ; + %load/vec4 v000001d6905ce010_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.2 ; + %load/vec4 v000001d6905cee70_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.3 ; + %load/vec4 v000001d6905cd1b0_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.4 ; + %load/vec4 v000001d6905ce830_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.5 ; + %load/vec4 v000001d6905cded0_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.6 ; + %load/vec4 v000001d6905cdf70_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.7 ; + %load/vec4 v000001d6905cef10_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.8 ; + %load/vec4 v000001d6905ce3d0_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.9 ; + %load/vec4 v000001d6905ce0b0_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.10 ; + %load/vec4 v000001d6905ce470_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.11 ; + %load/vec4 v000001d6905ce6f0_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.12 ; + %load/vec4 v000001d6905cd110_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.13 ; + %load/vec4 v000001d6905d29a0_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.14 ; + %load/vec4 v000001d6905d1960_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.15 ; + %load/vec4 v000001d6905d1aa0_0; + %store/vec4 v000001d6905cd7f0_0, 0, 32; + %jmp T_4.17; +T_4.17 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4, $push; + .scope S_000001d690544ab0; +T_5 ; + %vpi_call 2 13 "$monitor", "Time=%0t, Data1=%d, Data2=%d, Output=%d", $time, v000001d6905d2720_0, v000001d6905d1280_0, v000001d6905d1e60_0 {0 0 0}; + %pushi/vec4 6, 0, 32; + %store/vec4 v000001d6905d2720_0, 0, 32; + %pushi/vec4 3, 0, 32; + %store/vec4 v000001d6905d1280_0, 0, 32; + %pushi/vec4 0, 0, 5; + %store/vec4 v000001d6905d1b40_0, 0, 5; + %pushi/vec4 0, 0, 32; + %store/vec4 v000001d6905d1a00_0, 0, 32; +T_5.0 ; + %load/vec4 v000001d6905d1a00_0; + %cmpi/s 17, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_5.1, 5; + %load/vec4 v000001d6905d1a00_0; + %pad/s 5; + %store/vec4 v000001d6905d1b40_0, 0, 5; + %delay 5, 0; + ; show_stmt_assign_vector: Get l-value for compressed += operand + %load/vec4 v000001d6905d1a00_0; + %pushi/vec4 1, 0, 32; + %add; + %store/vec4 v000001d6905d1a00_0, 0, 32; + %jmp T_5.0; +T_5.1 ; + %vpi_call 2 26 "$finish" {0 0 0}; + %end; + .thread T_5; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "ALU_tb.v"; + "./ALU.v"; diff --git a/verilog/control_unit.v b/verilog/Control Unit/control_unit.v similarity index 96% rename from verilog/control_unit.v rename to verilog/Control Unit/control_unit.v index 2a5d12a..ed4f744 100644 --- a/verilog/control_unit.v +++ b/verilog/Control Unit/control_unit.v @@ -1,7 +1,7 @@ -// Advanced Computer Architecture (CO502) -// Design: Control Unit -// Group Number: 03 -// E Numbers: E/20/369, E/20/381, E/20/385 -// Last Modified: 04.12.2024 - +// Advanced Computer Architecture (CO502) +// Design: Control Unit +// Group Number: 03 +// E Numbers: E/20/369, E/20/381, E/20/385 +// Last Modified: 04.12.2024 + `timescale 1ns/100ps \ No newline at end of file diff --git a/verilog/PC/PC.v b/verilog/PC/PC.v new file mode 100644 index 0000000..7161e94 --- /dev/null +++ b/verilog/PC/PC.v @@ -0,0 +1,16 @@ +module pc(CLK, RESET, pc); + input CLK, RESET; + output reg [31:0] pc; + + always @(posedge CLK) + begin + if (RESET == 1'b1) + begin + pc <= #1 0; + end + else + begin + pc <= #1 pc + 4; + end + end +endmodule \ No newline at end of file diff --git a/verilog/PC/PC.v.out b/verilog/PC/PC.v.out new file mode 100644 index 0000000..67a6c2e --- /dev/null +++ b/verilog/PC/PC.v.out @@ -0,0 +1,41 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "D:\verilog\iverilog\lib\ivl\system.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "D:\verilog\iverilog\lib\ivl\va_math.vpi"; +S_000001e78f6d6a50 .scope module, "pc" "pc" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "CLK"; + .port_info 1 /INPUT 1 "RESET"; + .port_info 2 /OUTPUT 32 "pc"; +o000001e78f726fd8 .functor BUFZ 1, C4; HiZ drive +v000001e78f6d6be0_0 .net "CLK", 0 0, o000001e78f726fd8; 0 drivers +o000001e78f727008 .functor BUFZ 1, C4; HiZ drive +v000001e78f6d6c80_0 .net "RESET", 0 0, o000001e78f727008; 0 drivers +v000001e78f6d6d20_0 .var "pc", 31 0; +E_000001e78f725010 .event posedge, v000001e78f6d6be0_0; + .scope S_000001e78f6d6a50; +T_0 ; + %wait E_000001e78f725010; + %load/vec4 v000001e78f6d6c80_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_0.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v000001e78f6d6d20_0, 1; + %jmp T_0.1; +T_0.0 ; + %load/vec4 v000001e78f6d6d20_0; + %addi 4, 0, 32; + %assign/vec4 v000001e78f6d6d20_0, 1; +T_0.1 ; + %jmp T_0; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "PC.v"; diff --git a/verilog/register.v b/verilog/Register/register.v similarity index 100% rename from verilog/register.v rename to verilog/Register/register.v diff --git a/verilog/mux.v b/verilog/mux.v index b980301..589b599 100644 --- a/verilog/mux.v +++ b/verilog/mux.v @@ -12,5 +12,4 @@ module mux(IN1, IN2, SELECT, OUT); else OUT = IN2 end - endmodule \ No newline at end of file