diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json
new file mode 100644
index 0000000..f912847
--- /dev/null
+++ b/.vscode/c_cpp_properties.json
@@ -0,0 +1,18 @@
+{
+  "configurations": [
+    {
+      "name": "windows-gcc-x86",
+      "includePath": [
+        "${workspaceFolder}/**"
+      ],
+      "compilerPath": "C:/MinGW/bin/gcc.exe",
+      "cStandard": "${default}",
+      "cppStandard": "${default}",
+      "intelliSenseMode": "windows-gcc-x86",
+      "compilerArgs": [
+        ""
+      ]
+    }
+  ],
+  "version": 4
+}
\ No newline at end of file
diff --git a/.vscode/launch.json b/.vscode/launch.json
new file mode 100644
index 0000000..4338e23
--- /dev/null
+++ b/.vscode/launch.json
@@ -0,0 +1,24 @@
+{
+  "version": "0.2.0",
+  "configurations": [
+    {
+      "name": "C/C++ Runner: Debug Session",
+      "type": "cppdbg",
+      "request": "launch",
+      "args": [],
+      "stopAtEntry": false,
+      "externalConsole": true,
+      "cwd": "e:/CO502-2024  Advanced Computer Architecture (Nov 2024)/e20-co502-RV32IM-pipeline-implementation-group-2/ControlUnit",
+      "program": "e:/CO502-2024  Advanced Computer Architecture (Nov 2024)/e20-co502-RV32IM-pipeline-implementation-group-2/ControlUnit/build/Debug/outDebug",
+      "MIMode": "gdb",
+      "miDebuggerPath": "gdb",
+      "setupCommands": [
+        {
+          "description": "Enable pretty-printing for gdb",
+          "text": "-enable-pretty-printing",
+          "ignoreFailures": true
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 0000000..bb879da
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,59 @@
+{
+  "C_Cpp_Runner.cCompilerPath": "gcc",
+  "C_Cpp_Runner.cppCompilerPath": "g++",
+  "C_Cpp_Runner.debuggerPath": "gdb",
+  "C_Cpp_Runner.cStandard": "",
+  "C_Cpp_Runner.cppStandard": "",
+  "C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/VR_NR/Community/VC/Auxiliary/Build/vcvarsall.bat",
+  "C_Cpp_Runner.useMsvc": false,
+  "C_Cpp_Runner.warnings": [
+    "-Wall",
+    "-Wextra",
+    "-Wpedantic",
+    "-Wshadow",
+    "-Wformat=2",
+    "-Wcast-align",
+    "-Wconversion",
+    "-Wsign-conversion",
+    "-Wnull-dereference"
+  ],
+  "C_Cpp_Runner.msvcWarnings": [
+    "/W4",
+    "/permissive-",
+    "/w14242",
+    "/w14287",
+    "/w14296",
+    "/w14311",
+    "/w14826",
+    "/w44062",
+    "/w44242",
+    "/w14905",
+    "/w14906",
+    "/w14263",
+    "/w44265",
+    "/w14928"
+  ],
+  "C_Cpp_Runner.enableWarnings": true,
+  "C_Cpp_Runner.warningsAsError": false,
+  "C_Cpp_Runner.compilerArgs": [],
+  "C_Cpp_Runner.linkerArgs": [],
+  "C_Cpp_Runner.includePaths": [],
+  "C_Cpp_Runner.includeSearch": [
+    "*",
+    "**/*"
+  ],
+  "C_Cpp_Runner.excludeSearch": [
+    "**/build",
+    "**/build/**",
+    "**/.*",
+    "**/.*/**",
+    "**/.vscode",
+    "**/.vscode/**"
+  ],
+  "C_Cpp_Runner.useAddressSanitizer": false,
+  "C_Cpp_Runner.useUndefinedSanitizer": false,
+  "C_Cpp_Runner.useLeakSanitizer": false,
+  "C_Cpp_Runner.showCompilationTime": false,
+  "C_Cpp_Runner.useLinkTimeOptimization": false,
+  "C_Cpp_Runner.msvcSecureNoWarnings": false
+}
\ No newline at end of file
diff --git a/ALUunit/ALU.v b/ALUunit/ALU.v
new file mode 100644
index 0000000..044b5a7
--- /dev/null
+++ b/ALUunit/ALU.v
@@ -0,0 +1,46 @@
+// ALU unit
+
+module alu (data1,data2,opcode,Output);
+    input [31:0] data1,data2;
+    input [4:0] opcode;
+
+    output reg [31:0] Output;
+
+    wire [31:0] MULH_result,MULHU_result,MULHSU_result;
+    wire [63:0] mulh_result,mulhu_result,mulhsu_result;
+
+    assign mulh_result = $signed (data1)*$signed(data2) ;           // Calculation of Multiplication High instruction
+    assign MULH_result = mulh_result[63:32];
+
+    assign mulhu_result = $signed (data1)*$unsigned(data2) ;        // Calculation of Multiplication high unsigned values instruction
+    assign MULHU_result = mulhu_result[63:32];
+
+    assign mulhsu_result = $unsigned (data1)*$unsigned(data2) ;     // Calculation of Multiplication high signed unsigned instruction
+    assign MULHSU_result = mulhsu_result[63:32];
+
+    
+    always @(*) begin
+        case (opcode)
+            5'b00000:Output = data1+data2;                          //ADD instruction
+            5'b00001:Output = data1-data2;                          //SUB instruction
+            5'b00010:Output = data1|data2;                          //OR instruction
+            5'b00011:Output = data1^data2;                          //XOR instruction
+            5'b00100:Output = data1&data2;                          //AND instruction
+            5'b00101:Output = data1>>data2;                         //SLR instruction
+            5'b00110:Output = data1<<data2;                         //SLL instruction
+            5'b00111:Output = data1>>>data2;                        //SRA instruction
+            5'b01000:Output = data1*data2;                          //MUL instruction
+            5'b01001:Output = MULH_result;                          //MULH instruction
+            5'b01010:Output = MULHU_result;                         //MULHU instruction
+            5'b01011:Output = MULHSU_result;                        //MULHSU instruction
+            5'b01100:Output = $signed(data1)/$signed(data2);        //DIV instruction
+            5'b01101:Output = $unsigned(data1)/$unsigned(data2);    //DIVH instruction
+            5'b01110:Output = $signed(data1)% $signed(data2);       //REM instuction
+            5'b01111:Output = $unsigned(data1)% $unsigned(data2);   //REMU instruction
+            5'b10000:Output = (data1<data2)?32'b1:32'b0;            //SLT instruction
+            5'b10001:Output = data2;                                //Forwarding instruction
+            default:Output = 32'b0;
+        endcase
+    end
+   
+endmodule
diff --git a/ALUunit/ALUResult b/ALUunit/ALUResult
new file mode 100644
index 0000000..d99e154
--- /dev/null
+++ b/ALUunit/ALUResult
@@ -0,0 +1,296 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_000002881310c630 .scope module, "tb_ALU" "tb_ALU" 2 4;
+ .timescale -12 -12;
+v0000028812f73540_0 .net "ALU_OUTPUT", 31 0, v0000028812f73900_0;  1 drivers
+v0000028812f739a0_0 .var "DATA1", 31 0;
+v0000028812f73d60_0 .var "DATA2", 31 0;
+v0000028812f73b80_0 .var "OPCODE", 4 0;
+v0000028812f73e00_0 .var/i "i", 31 0;
+S_000002881310c7c0 .scope module, "test_unit" "alu" 2 11, 3 3 0, S_000002881310c630;
+ .timescale -12 -12;
+    .port_info 0 /INPUT 32 "data1";
+    .port_info 1 /INPUT 32 "data2";
+    .port_info 2 /INPUT 5 "opcode";
+    .port_info 3 /OUTPUT 32 "Output";
+v0000028812f42510_0 .net "MULHSU_result", 31 0, L_0000028812fd4150;  1 drivers
+v0000028812f6bcf0_0 .net "MULHU_result", 31 0, L_0000028812fd4790;  1 drivers
+v0000028812f6bd90_0 .net "MULH_result", 31 0, L_0000028812fd3070;  1 drivers
+v0000028812f73900_0 .var "Output", 31 0;
+v0000028812f735e0_0 .net/s *"_ivl_0", 63 0, L_0000028812fd37f0;  1 drivers
+v0000028812f73c20_0 .net *"_ivl_10", 63 0, L_0000028812fd43d0;  1 drivers
+L_0000028812fd5038 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000028812f730e0_0 .net *"_ivl_13", 31 0, L_0000028812fd5038;  1 drivers
+v0000028812f73180_0 .net *"_ivl_14", 63 0, L_0000028812fd4ab0;  1 drivers
+L_0000028812fd5080 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000028812f73ea0_0 .net *"_ivl_17", 31 0, L_0000028812fd5080;  1 drivers
+v0000028812f732c0_0 .net/s *"_ivl_2", 63 0, L_0000028812fd3890;  1 drivers
+v0000028812f73220_0 .net *"_ivl_21", 32 0, L_0000028812fd3930;  1 drivers
+v0000028812f73a40_0 .net *"_ivl_24", 63 0, L_0000028812fd4830;  1 drivers
+L_0000028812fd50c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000028812f72fa0_0 .net *"_ivl_27", 31 0, L_0000028812fd50c8;  1 drivers
+v0000028812f73720_0 .net *"_ivl_28", 63 0, L_0000028812fd4510;  1 drivers
+L_0000028812fd5110 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000028812f737c0_0 .net *"_ivl_31", 31 0, L_0000028812fd5110;  1 drivers
+v0000028812f734a0_0 .net *"_ivl_35", 32 0, L_0000028812fd3f70;  1 drivers
+v0000028812f73860_0 .net *"_ivl_7", 32 0, L_0000028812fd40b0;  1 drivers
+v0000028812f73cc0_0 .net "data1", 31 0, v0000028812f739a0_0;  1 drivers
+v0000028812f73680_0 .net "data2", 31 0, v0000028812f73d60_0;  1 drivers
+v0000028812f73ae0_0 .net "mulh_result", 63 0, L_0000028812fd36b0;  1 drivers
+v0000028812f73040_0 .net "mulhsu_result", 63 0, L_0000028812fd4470;  1 drivers
+v0000028812f73360_0 .net "mulhu_result", 63 0, L_0000028812fd3610;  1 drivers
+v0000028812f73400_0 .net "opcode", 4 0, v0000028812f73b80_0;  1 drivers
+E_0000028812f6df30/0 .event anyedge, v0000028812f73400_0, v0000028812f73cc0_0, v0000028812f73680_0, v0000028812f6bd90_0;
+E_0000028812f6df30/1 .event anyedge, v0000028812f6bcf0_0, v0000028812f42510_0;
+E_0000028812f6df30 .event/or E_0000028812f6df30/0, E_0000028812f6df30/1;
+L_0000028812fd37f0 .extend/s 64, v0000028812f739a0_0;
+L_0000028812fd3890 .extend/s 64, v0000028812f73d60_0;
+L_0000028812fd36b0 .arith/mult 64, L_0000028812fd37f0, L_0000028812fd3890;
+L_0000028812fd40b0 .part L_0000028812fd36b0, 31, 33;
+L_0000028812fd3070 .part L_0000028812fd40b0, 0, 32;
+L_0000028812fd43d0 .concat [ 32 32 0 0], v0000028812f739a0_0, L_0000028812fd5038;
+L_0000028812fd4ab0 .concat [ 32 32 0 0], v0000028812f73d60_0, L_0000028812fd5080;
+L_0000028812fd3610 .arith/mult 64, L_0000028812fd43d0, L_0000028812fd4ab0;
+L_0000028812fd3930 .part L_0000028812fd3610, 31, 33;
+L_0000028812fd4790 .part L_0000028812fd3930, 0, 32;
+L_0000028812fd4830 .concat [ 32 32 0 0], v0000028812f739a0_0, L_0000028812fd50c8;
+L_0000028812fd4510 .concat [ 32 32 0 0], v0000028812f73d60_0, L_0000028812fd5110;
+L_0000028812fd4470 .arith/mult 64, L_0000028812fd4830, L_0000028812fd4510;
+L_0000028812fd3f70 .part L_0000028812fd4470, 31, 33;
+L_0000028812fd4150 .part L_0000028812fd3f70, 0, 32;
+    .scope S_000002881310c7c0;
+T_0 ;
+    %wait E_0000028812f6df30;
+    %load/vec4 v0000028812f73400_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.0, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.1, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.2, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.3, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.4, 6;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.5, 6;
+    %dup/vec4;
+    %pushi/vec4 6, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.6, 6;
+    %dup/vec4;
+    %pushi/vec4 7, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.7, 6;
+    %dup/vec4;
+    %pushi/vec4 8, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.8, 6;
+    %dup/vec4;
+    %pushi/vec4 9, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.9, 6;
+    %dup/vec4;
+    %pushi/vec4 10, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.10, 6;
+    %dup/vec4;
+    %pushi/vec4 11, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.11, 6;
+    %dup/vec4;
+    %pushi/vec4 12, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.12, 6;
+    %dup/vec4;
+    %pushi/vec4 13, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.13, 6;
+    %dup/vec4;
+    %pushi/vec4 14, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.14, 6;
+    %dup/vec4;
+    %pushi/vec4 15, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.15, 6;
+    %dup/vec4;
+    %pushi/vec4 16, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.16, 6;
+    %dup/vec4;
+    %pushi/vec4 17, 0, 5;
+    %cmp/u;
+    %jmp/1 T_0.17, 6;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.0 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %add;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.1 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %sub;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.2 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %or;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.3 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %xor;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.4 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %and;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.5 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %ix/getv 4, v0000028812f73680_0;
+    %shiftr 4;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.6 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %ix/getv 4, v0000028812f73680_0;
+    %shiftl 4;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.7 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %ix/getv 4, v0000028812f73680_0;
+    %shiftr 4;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.8 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %mul;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.9 ;
+    %load/vec4 v0000028812f6bd90_0;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.10 ;
+    %load/vec4 v0000028812f6bcf0_0;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.11 ;
+    %load/vec4 v0000028812f42510_0;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.12 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %div/s;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.13 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %div;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.14 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %mod/s;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.15 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %mod;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.16 ;
+    %load/vec4 v0000028812f73cc0_0;
+    %load/vec4 v0000028812f73680_0;
+    %cmp/u;
+    %flag_mov 8, 5;
+    %jmp/0 T_0.20, 8;
+    %pushi/vec4 1, 0, 32;
+    %jmp/1 T_0.21, 8;
+T_0.20 ; End of true expr.
+    %pushi/vec4 0, 0, 32;
+    %jmp/0 T_0.21, 8;
+ ; End of false expr.
+    %blend;
+T_0.21;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.17 ;
+    %load/vec4 v0000028812f73680_0;
+    %store/vec4 v0000028812f73900_0, 0, 32;
+    %jmp T_0.19;
+T_0.19 ;
+    %pop/vec4 1;
+    %jmp T_0;
+    .thread T_0, $push;
+    .scope S_000002881310c630;
+T_1 ;
+    %vpi_call 2 13 "$monitor", "Time=%0t, Data1=%d, Data2=%d, Output=%d", $time, v0000028812f739a0_0, v0000028812f73d60_0, v0000028812f73540_0 {0 0 0};
+    %pushi/vec4 6, 0, 32;
+    %store/vec4 v0000028812f739a0_0, 0, 32;
+    %pushi/vec4 3, 0, 32;
+    %store/vec4 v0000028812f73d60_0, 0, 32;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v0000028812f73b80_0, 0, 5;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0000028812f73e00_0, 0, 32;
+T_1.0 ;
+    %load/vec4 v0000028812f73e00_0;
+    %cmpi/s 17, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_1.1, 5;
+    %load/vec4 v0000028812f73e00_0;
+    %pad/s 5;
+    %store/vec4 v0000028812f73b80_0, 0, 5;
+    %delay 5, 0;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0000028812f73e00_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0000028812f73e00_0, 0, 32;
+    %jmp T_1.0;
+T_1.1 ;
+    %vpi_call 2 26 "$finish" {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "ALUtestbench.v";
+    "alu.v";
diff --git a/ALUunit/ALUtestbench.v b/ALUunit/ALUtestbench.v
new file mode 100644
index 0000000..ea24f6d
--- /dev/null
+++ b/ALUunit/ALUtestbench.v
@@ -0,0 +1,29 @@
+//ALU testbench
+`timescale 1ps/1ps
+
+module tb_ALU ;
+    reg[31:0]DATA1,DATA2;
+    reg[4:0]OPCODE;
+    wire[31:0]ALU_OUTPUT;
+
+    integer i;
+
+    alu test_unit(DATA1,DATA2,OPCODE,ALU_OUTPUT);                       // initiating the alu module 
+    initial begin
+        $monitor("Time=%0t, Data1=%d, Data2=%d, Output=%d", $time, DATA1, DATA2,ALU_OUTPUT);
+
+            
+        DATA1 = 32'd6;
+        DATA2 = 32'd3;
+        OPCODE = 5'd0;
+            
+
+        for (i=0;i<=17;i++)
+        begin
+            OPCODE =i;
+            #5;
+        end
+        $finish;
+    end
+    
+endmodule
\ No newline at end of file
diff --git a/ALUunit/waveform.vcd b/ALUunit/waveform.vcd
new file mode 100644
index 0000000..216e5b5
--- /dev/null
+++ b/ALUunit/waveform.vcd
@@ -0,0 +1,146 @@
+$date
+	Fri Dec 06 12:59:24 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module tb_ALU $end
+$var wire 32 ! ALU_OUTPUT [31:0] $end
+$var reg 32 " DATA1 [31:0] $end
+$var reg 32 # DATA2 [31:0] $end
+$var reg 5 $ OPCODE [4:0] $end
+$var integer 32 % i [31:0] $end
+$scope module test_unit $end
+$var wire 32 & data1 [31:0] $end
+$var wire 32 ' data2 [31:0] $end
+$var wire 5 ( opcode [4:0] $end
+$var wire 64 ) mulhu_result [63:0] $end
+$var wire 64 * mulhsu_result [63:0] $end
+$var wire 64 + mulh_result [63:0] $end
+$var wire 32 , SLT_result [31:0] $end
+$var wire 32 - MULH_result [31:0] $end
+$var wire 32 . MULHU_result [31:0] $end
+$var wire 32 / MULHSU_result [31:0] $end
+$var reg 32 0 Output [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+b1001 0
+b0 /
+b0 .
+b0 -
+b0 ,
+b10010 +
+b10010 *
+b10010 )
+b0 (
+b11 '
+b110 &
+b0 %
+b0 $
+b11 #
+b110 "
+b1001 !
+$end
+#5
+b11 !
+b11 0
+b1 $
+b1 (
+b1 %
+#10
+b111 !
+b111 0
+b10 $
+b10 (
+b10 %
+#15
+b101 !
+b101 0
+b11 $
+b11 (
+b11 %
+#20
+b10 !
+b10 0
+b100 $
+b100 (
+b100 %
+#25
+b0 !
+b0 0
+b101 $
+b101 (
+b101 %
+#30
+b110000 !
+b110000 0
+b110 $
+b110 (
+b110 %
+#35
+b0 !
+b0 0
+b111 $
+b111 (
+b111 %
+#40
+b10010 !
+b10010 0
+b1000 $
+b1000 (
+b1000 %
+#45
+b0 !
+b0 0
+b1001 $
+b1001 (
+b1001 %
+#50
+b1010 $
+b1010 (
+b1010 %
+#55
+b1011 $
+b1011 (
+b1011 %
+#60
+b10 !
+b10 0
+b1100 $
+b1100 (
+b1100 %
+#65
+b1101 $
+b1101 (
+b1101 %
+#70
+b0 !
+b0 0
+b1110 $
+b1110 (
+b1110 %
+#75
+b1111 $
+b1111 (
+b1111 %
+#80
+b10000 $
+b10000 (
+b10000 %
+#85
+b11 !
+b11 0
+b10001 $
+b10001 (
+b10001 %
+#90
+b10010 %
diff --git a/BranchController/BranchController.v b/BranchController/BranchController.v
new file mode 100644
index 0000000..bd9b7e0
--- /dev/null
+++ b/BranchController/BranchController.v
@@ -0,0 +1,32 @@
+module BranchController (data1,data2,func3,ALUresult,Branch,Jump,TargetedAddress,PCAddressController);
+    input signed[31:0] data1,data2,ALUresult;
+    input[2:0] func3;
+    input Branch,Jump;
+
+    output reg[31:0] TargetedAddress;
+    output reg PCAddressController;
+
+    always @(data1,data2,func3,Branch,Jump,ALUresult) begin
+        PCAddressController = 1'b0;                     // Initially the control flag set to 0(choose the PC+4 address)
+        if (Branch==1'b1) begin 
+            TargetedAddress = ALUresult;
+            case (func3)
+                3'b000:PCAddressController=(data1==data2)?1'b1:1'b0;                            //BEQ instruction
+                3'b001:PCAddressController=(data1!=data2)?1'b1:1'b0;                            //BNE instruction
+                3'b100:PCAddressController=($signed(data1)<$signed(data2))?1'b1:1'b0;           //BLT instruction
+                3'b101:PCAddressController=($signed(data1)>=$signed(data2))?1'b1:1'b0;          //BGE instruction
+                3'b110:PCAddressController=($unsigned(data1)<$unsigned(data2))?1'b1:1'b0;       //BLTU instruction
+                3'b111:PCAddressController=($unsigned(data1)>=$unsigned(data2))?1'b1:1'b0;      //BGEU instruction
+                default: PCAddressController=1'b0;
+            endcase    
+        end
+        if (Jump==1'b1) begin
+            TargetedAddress =ALUresult;
+            PCAddressController =1'b1;                                                          //Jump Insruction
+        end
+        
+        
+    end
+
+    
+endmodule
\ No newline at end of file
diff --git a/BranchController/BranchControllerresult b/BranchController/BranchControllerresult
new file mode 100644
index 0000000..5e86e62
--- /dev/null
+++ b/BranchController/BranchControllerresult
@@ -0,0 +1,234 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_00000170337070b0 .scope module, "BranchController_tb" "BranchController_tb" 2 3;
+ .timescale -12 -12;
+v0000017033759b70_0 .var/s "ALUresult", 31 0;
+v0000017033759c10_0 .var "Branch_tb", 0 0;
+v0000017033759cb0_0 .var "Jump_tb", 0 0;
+v000001703375a2a0_0 .net "PCAddressController", 0 0, v0000017033759850_0;  1 drivers
+v000001703375a020_0 .net "TargetedAddress", 31 0, v00000170337598f0_0;  1 drivers
+v0000017033759da0_0 .var/s "data1", 31 0;
+v0000017033759e40_0 .var/s "data2", 31 0;
+v0000017033759ee0_0 .var "func3", 2 0;
+S_0000017033707240 .scope module, "Test_unit" "BranchController" 2 11, 3 1 0, S_00000170337070b0;
+ .timescale -12 -12;
+    .port_info 0 /INPUT 32 "data1";
+    .port_info 1 /INPUT 32 "data2";
+    .port_info 2 /INPUT 3 "func3";
+    .port_info 3 /INPUT 32 "ALUresult";
+    .port_info 4 /INPUT 1 "Branch";
+    .port_info 5 /INPUT 1 "Jump";
+    .port_info 6 /OUTPUT 32 "TargetedAddress";
+    .port_info 7 /OUTPUT 1 "PCAddressController";
+v00000170338b62e0_0 .net/s "ALUresult", 31 0, v0000017033759b70_0;  1 drivers
+v00000170338bbcd0_0 .net "Branch", 0 0, v0000017033759c10_0;  1 drivers
+v00000170338bbd70_0 .net "Jump", 0 0, v0000017033759cb0_0;  1 drivers
+v0000017033759850_0 .var "PCAddressController", 0 0;
+v00000170337598f0_0 .var "TargetedAddress", 31 0;
+v0000017033759990_0 .net/s "data1", 31 0, v0000017033759da0_0;  1 drivers
+v0000017033759a30_0 .net/s "data2", 31 0, v0000017033759e40_0;  1 drivers
+v0000017033759ad0_0 .net "func3", 2 0, v0000017033759ee0_0;  1 drivers
+E_00000170338b9e30/0 .event anyedge, v00000170338b62e0_0, v00000170338bbd70_0, v00000170338bbcd0_0, v0000017033759ad0_0;
+E_00000170338b9e30/1 .event anyedge, v0000017033759a30_0, v0000017033759990_0;
+E_00000170338b9e30 .event/or E_00000170338b9e30/0, E_00000170338b9e30/1;
+    .scope S_0000017033707240;
+T_0 ;
+    %wait E_00000170338b9e30;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %load/vec4 v00000170338bbcd0_0;
+    %cmpi/e 1, 0, 1;
+    %jmp/0xz  T_0.0, 4;
+    %load/vec4 v00000170338b62e0_0;
+    %store/vec4 v00000170337598f0_0, 0, 32;
+    %load/vec4 v0000017033759ad0_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.2, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.3, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.4, 6;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.5, 6;
+    %dup/vec4;
+    %pushi/vec4 6, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.6, 6;
+    %dup/vec4;
+    %pushi/vec4 7, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.7, 6;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %jmp T_0.9;
+T_0.2 ;
+    %load/vec4 v0000017033759990_0;
+    %load/vec4 v0000017033759a30_0;
+    %cmp/e;
+    %flag_mov 8, 4;
+    %jmp/0 T_0.10, 8;
+    %pushi/vec4 1, 0, 1;
+    %jmp/1 T_0.11, 8;
+T_0.10 ; End of true expr.
+    %pushi/vec4 0, 0, 1;
+    %jmp/0 T_0.11, 8;
+ ; End of false expr.
+    %blend;
+T_0.11;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %jmp T_0.9;
+T_0.3 ;
+    %load/vec4 v0000017033759990_0;
+    %load/vec4 v0000017033759a30_0;
+    %cmp/ne;
+    %flag_mov 8, 4;
+    %jmp/0 T_0.12, 8;
+    %pushi/vec4 1, 0, 1;
+    %jmp/1 T_0.13, 8;
+T_0.12 ; End of true expr.
+    %pushi/vec4 0, 0, 1;
+    %jmp/0 T_0.13, 8;
+ ; End of false expr.
+    %blend;
+T_0.13;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %jmp T_0.9;
+T_0.4 ;
+    %load/vec4 v0000017033759990_0;
+    %load/vec4 v0000017033759a30_0;
+    %cmp/s;
+    %flag_mov 8, 5;
+    %jmp/0 T_0.14, 8;
+    %pushi/vec4 1, 0, 1;
+    %jmp/1 T_0.15, 8;
+T_0.14 ; End of true expr.
+    %pushi/vec4 0, 0, 1;
+    %jmp/0 T_0.15, 8;
+ ; End of false expr.
+    %blend;
+T_0.15;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %jmp T_0.9;
+T_0.5 ;
+    %load/vec4 v0000017033759a30_0;
+    %load/vec4 v0000017033759990_0;
+    %cmp/s;
+    %flag_or 5, 4;
+    %flag_mov 8, 5;
+    %jmp/0 T_0.16, 8;
+    %pushi/vec4 1, 0, 1;
+    %jmp/1 T_0.17, 8;
+T_0.16 ; End of true expr.
+    %pushi/vec4 0, 0, 1;
+    %jmp/0 T_0.17, 8;
+ ; End of false expr.
+    %blend;
+T_0.17;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %jmp T_0.9;
+T_0.6 ;
+    %load/vec4 v0000017033759990_0;
+    %load/vec4 v0000017033759a30_0;
+    %cmp/u;
+    %flag_mov 8, 5;
+    %jmp/0 T_0.18, 8;
+    %pushi/vec4 1, 0, 1;
+    %jmp/1 T_0.19, 8;
+T_0.18 ; End of true expr.
+    %pushi/vec4 0, 0, 1;
+    %jmp/0 T_0.19, 8;
+ ; End of false expr.
+    %blend;
+T_0.19;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %jmp T_0.9;
+T_0.7 ;
+    %load/vec4 v0000017033759a30_0;
+    %load/vec4 v0000017033759990_0;
+    %cmp/u;
+    %flag_or 5, 4;
+    %flag_mov 8, 5;
+    %jmp/0 T_0.20, 8;
+    %pushi/vec4 1, 0, 1;
+    %jmp/1 T_0.21, 8;
+T_0.20 ; End of true expr.
+    %pushi/vec4 0, 0, 1;
+    %jmp/0 T_0.21, 8;
+ ; End of false expr.
+    %blend;
+T_0.21;
+    %store/vec4 v0000017033759850_0, 0, 1;
+    %jmp T_0.9;
+T_0.9 ;
+    %pop/vec4 1;
+T_0.0 ;
+    %load/vec4 v00000170338bbd70_0;
+    %cmpi/e 1, 0, 1;
+    %jmp/0xz  T_0.22, 4;
+    %load/vec4 v00000170338b62e0_0;
+    %store/vec4 v00000170337598f0_0, 0, 32;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000017033759850_0, 0, 1;
+T_0.22 ;
+    %jmp T_0;
+    .thread T_0, $push;
+    .scope S_00000170337070b0;
+T_1 ;
+    %vpi_call 2 24 "$monitor", "Time=%0t, Output=%b, Branch=%b, Jump=%b , TargetAddress=%d", $time, v000001703375a2a0_0, v0000017033759c10_0, v0000017033759cb0_0, v000001703375a020_0 {0 0 0};
+    %pushi/vec4 24, 0, 32;
+    %store/vec4 v0000017033759b70_0, 0, 32;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000017033759c10_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000017033759cb0_0, 0, 1;
+    %pushi/vec4 12, 0, 32;
+    %store/vec4 v0000017033759da0_0, 0, 32;
+    %pushi/vec4 15, 0, 32;
+    %store/vec4 v0000017033759e40_0, 0, 32;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v0000017033759ee0_0, 0, 3;
+    %delay 10, 0;
+    %pushi/vec4 5, 0, 3;
+    %store/vec4 v0000017033759ee0_0, 0, 3;
+    %delay 10, 0;
+    %pushi/vec4 15, 0, 32;
+    %store/vec4 v0000017033759da0_0, 0, 32;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0000017033759ee0_0, 0, 3;
+    %delay 10, 0;
+    %pushi/vec4 4294967281, 0, 32;
+    %store/vec4 v0000017033759da0_0, 0, 32;
+    %pushi/vec4 5, 0, 3;
+    %store/vec4 v0000017033759ee0_0, 0, 3;
+    %delay 10, 0;
+    %pushi/vec4 7, 0, 3;
+    %store/vec4 v0000017033759ee0_0, 0, 3;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000017033759cb0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000017033759c10_0, 0, 1;
+    %vpi_call 2 51 "$finish" {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "BranchControllertb.v";
+    "BranchController.v";
diff --git a/BranchController/BranchControllertb.v b/BranchController/BranchControllertb.v
new file mode 100644
index 0000000..3a344f2
--- /dev/null
+++ b/BranchController/BranchControllertb.v
@@ -0,0 +1,53 @@
+`timescale 1ps/1ps
+
+module BranchController_tb ();
+    reg signed [31:0] data1, data2, ALUresult;
+    reg [2:0] func3;
+    wire[31:0]TargetedAddress;
+    reg Branch_tb, Jump_tb; 
+    wire PCAddressController;
+
+    // Instantiate the Unit Under Test (UUT)
+    BranchController Test_unit (        
+        .data1(data1),
+        .data2(data2),
+        .func3(func3),
+        .ALUresult(ALUresult),
+        .Branch(Branch_tb),
+        .Jump(Jump_tb),
+        .TargetedAddress(TargetedAddress),
+        .PCAddressController(PCAddressController)
+    );
+
+    initial begin
+        // Display monitored values
+        $monitor("Time=%0t, Output=%b, Branch=%b, Jump=%b , TargetAddress=%d", $time, PCAddressController, Branch_tb, Jump_tb, TargetedAddress);
+        
+        // Initialize signals
+        ALUresult = 32'd24; // Correct integer assignment syntax
+    
+        Branch_tb = 1;         // Correct binary literal
+        Jump_tb = 0;           // Correct binary literal
+        data1 = 32'd12;     // Decimal assignment
+        data2 = 32'd15;     // Decimal assignment
+        func3 = 3'b100;    // Correct binary assignment
+        
+        #10;                // Wait 10 time units
+        func3 = 3'b101;    // Assign new value to funct3
+        #10;                // Wait 10 time units
+
+        data1 = 32'd15;     // Assign new value to DATA1
+        func3 = 3'b000;    // Assign new value to funct3
+        
+        #10;
+
+        data1=-32'd15;
+        func3 = 3'b101;
+        #10;
+        func3 = 3'b111;
+        #10;
+        Jump_tb=1'b1;
+        Branch_tb=1'b0;
+        $finish;              // Stop the simulation
+    end
+endmodule
diff --git a/ControlUnit/controlUnit.v b/ControlUnit/controlUnit.v
new file mode 100644
index 0000000..ffbf7e7
--- /dev/null
+++ b/ControlUnit/controlUnit.v
@@ -0,0 +1,182 @@
+module controlUnit(INSTRUCTION,WRITE_ENABLE,MEMORY_ACCESS,MEM_WRITE,MEM_READ,JUMP_AND_LINK,ALU_OPCODE,IMMEDIATE_SELECT,OFFSET_GENARATOR,BRANCH,JUMP,IMMEDIATE_TYPE);
+input[31:0] INSTRUCTION;
+output reg[4:0] ALU_OPCODE;
+output reg[2:0] IMMEDIATE_TYPE;
+output reg WRITE_ENABLE,MEMORY_ACCESS,MEM_WRITE,MEM_READ,JUMP_AND_LINK,IMMEDIATE_SELECT,OFFSET_GENARATOR,BRANCH,JUMP;
+
+wire [6:0] OPCODE,FUNCT7;
+wire [2:0] FUNCT3;
+
+assign OPCODE = INSTRUCTION[6:0];
+assign FUNCT3 = INSTRUCTION[14:12];
+assign FUNCT7 = INSTRUCTION[31:25];
+
+always @(OPCODE,FUNCT3,FUNCT7) begin
+    case(OPCODE)
+    7'b0110011:begin //R type istruction
+        IMMEDIATE_TYPE = 3'bxxx;
+        WRITE_ENABLE = 1'b1;
+        MEMORY_ACCESS = 1'b0;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b0;
+        IMMEDIATE_SELECT = 1'b0;
+        OFFSET_GENARATOR = 1'b0;
+        BRANCH = 1'b0;
+        JUMP = 1'b0 ;
+        case({FUNCT7,FUNCT3})
+        10'b0000000000:ALU_OPCODE = 5'b00000; // ADD
+        10'b0100000000:ALU_OPCODE = 5'b00001; // SUB
+        10'b0000000110:ALU_OPCODE = 5'b00010; // OR
+        10'b0000000100:ALU_OPCODE = 5'b00011; // XOR
+        10'b0000000111:ALU_OPCODE = 5'b00100; // AND 
+        10'b0000000101:ALU_OPCODE = 5'b00101; // SRL
+        10'b0000000001:ALU_OPCODE = 5'b00110; // SLL
+        10'b0100000101:ALU_OPCODE = 5'b00111; // SRA
+        10'b0000001000:ALU_OPCODE = 5'b01000; // MUL
+        10'b0000001001:ALU_OPCODE = 5'b01001; // MULH
+        10'b0000001011:ALU_OPCODE = 5'b01010; // MULHU
+        10'b0000001010:ALU_OPCODE = 5'b01011; // MULHSU
+        10'b0000001100:ALU_OPCODE = 5'b01100; // DIV
+        10'b0000001101:ALU_OPCODE = 5'b01101; // DIVH
+        10'b0000001110:ALU_OPCODE = 5'b01110; // REM
+        10'b0000001111:ALU_OPCODE = 5'b01111; // REMU
+        10'b0000000010:ALU_OPCODE = 5'b10000; // SLT 
+        endcase
+    end
+
+    7'b0010011:begin //I type istruction
+        IMMEDIATE_TYPE = 3'b000;
+        WRITE_ENABLE = 1'b1;
+        MEMORY_ACCESS = 1'b0;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b0;
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b0;
+        BRANCH = 1'b0;
+        JUMP = 1'b0 ;
+        case(FUNCT3)
+        3'b000:ALU_OPCODE = 5'b00000; // ADDI
+        3'b010:ALU_OPCODE = 5'b10000; // SLTI
+        3'b111:ALU_OPCODE = 5'b00100; // ANDI
+        3'b110:ALU_OPCODE = 5'b00010; // ORI
+        3'b100:ALU_OPCODE = 5'b00011; // XORI
+        endcase
+        case(FUNCT7)
+        7'b0000000:begin
+            case (FUNCT3)
+                3'b001: ALU_OPCODE = 5'b00110; //SLLI
+                3'b101: ALU_OPCODE = 5'b00101; //SRLI 
+            endcase
+        end
+        7'b0100000:begin
+            case (FUNCT3)
+                3'b101: ALU_OPCODE = 5'b00111; //SRAI
+                endcase
+        end
+        endcase
+    
+    end
+
+    7'b0000011:begin //LW istruction
+        IMMEDIATE_TYPE = 3'b000;
+        WRITE_ENABLE = 1'b1;
+        MEMORY_ACCESS = 1'b1;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b1;
+        JUMP_AND_LINK = 1'b0;
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b0;
+        BRANCH = 1'b0;
+        JUMP = 1'b0 ;
+        ALU_OPCODE = 5'b00000;
+        end 
+    7'b0100011:begin //S type istruction
+        IMMEDIATE_TYPE = 3'b001;
+        WRITE_ENABLE = 1'b0;
+        MEMORY_ACCESS = 1'b1;
+        MEM_WRITE = 1'b1;    
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b0;    
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b0;
+        BRANCH = 1'b0;
+        JUMP = 1'b0 ;
+        ALU_OPCODE = 5'b00000; 
+    end
+    7'b1101111:begin //J type istruction
+        IMMEDIATE_TYPE = 3'b010;
+        WRITE_ENABLE = 1'b1;
+        MEMORY_ACCESS = 1'b0;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b1;
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b1;
+        BRANCH = 1'b0;
+        JUMP = 1'b1 ;
+        ALU_OPCODE = 5'b00000;
+    end
+    7'b1100111:begin //JALR istruction
+        IMMEDIATE_TYPE = 3'b000;
+        WRITE_ENABLE = 1'b1;
+        MEMORY_ACCESS = 1'b0;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b1;
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b0;
+        BRANCH = 1'b0;
+        JUMP = 1'b1;
+        ALU_OPCODE = 5'b00000;
+    end
+    7'b0110111:begin // LUI
+        IMMEDIATE_TYPE = 3'b011;
+        WRITE_ENABLE = 1'b1;
+        MEMORY_ACCESS = 1'b0;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b0;
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b0;
+        BRANCH = 1'b0;
+        JUMP = 1'b0;
+        ALU_OPCODE = 5'b10001;
+    end
+     7'b0010111:begin // AUIPC
+        IMMEDIATE_TYPE = 3'b011;
+        WRITE_ENABLE = 1'b1;
+        MEMORY_ACCESS = 1'b0;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b0;
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b1;
+        BRANCH = 1'b0;
+        JUMP = 1'b0;
+        ALU_OPCODE = 5'b00000;
+    end
+    7'b1100011:begin // B type instruction
+        IMMEDIATE_TYPE = 3'b100;
+        WRITE_ENABLE = 1'b0;
+        MEMORY_ACCESS = 1'b0;
+        MEM_WRITE = 1'b0;
+        MEM_READ = 1'b0;
+        JUMP_AND_LINK = 1'b0;
+        IMMEDIATE_SELECT = 1'b1;
+        OFFSET_GENARATOR = 1'b1;
+        BRANCH = 1'b1;
+        JUMP = 1'b0;
+        ALU_OPCODE = 5'b00000;
+    end
+    
+
+    endcase
+end
+
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/ControlUnit/controlUnit_tb.v b/ControlUnit/controlUnit_tb.v
new file mode 100644
index 0000000..d1817fe
--- /dev/null
+++ b/ControlUnit/controlUnit_tb.v
@@ -0,0 +1,67 @@
+`timescale 1ns/1ps
+
+
+
+module controlUnit_tb;
+
+    // Inputs
+    reg [31:0] INSTRUCTION;
+
+    // Outputs
+    wire [4:0] ALU_OPCODE;
+    wire [2:0] IMMEDIATE_TYPE;
+    wire WRITE_ENABLE, MEMORY_ACCESS, MEM_WRITE, MEM_READ, JUMP_AND_LINK;
+    wire IMMEDIATE_SELECT, OFFSET_GENARATOR, BRANCH, JUMP;
+
+    // Instantiate the controlUnit module
+    controlUnit uut (
+        .INSTRUCTION(INSTRUCTION),
+        .ALU_OPCODE(ALU_OPCODE),
+        .IMMEDIATE_TYPE(IMMEDIATE_TYPE),
+        .WRITE_ENABLE(WRITE_ENABLE),
+        .MEMORY_ACCESS(MEMORY_ACCESS),
+        .MEM_WRITE(MEM_WRITE),
+        .MEM_READ(MEM_READ),
+        .JUMP_AND_LINK(JUMP_AND_LINK),
+        .IMMEDIATE_SELECT(IMMEDIATE_SELECT),
+        .OFFSET_GENARATOR(OFFSET_GENARATOR),
+        .BRANCH(BRANCH),
+        .JUMP(JUMP)
+    );
+
+    initial begin
+        // Initialize the input
+        INSTRUCTION = 32'b0;
+
+        // Test R-type ADD instruction
+        #10 INSTRUCTION = 32'b0000000_00001_00010_000_00011_1100011; // ADD
+        #10 $display("ADD Test: ALU_OPCODE=%b", ALU_OPCODE);
+
+        // Test I-type ADDI instruction
+        #10 INSTRUCTION = 32'b000000000001_00010_000_00011_0010011; // ADDI
+        #10 $display("ADDI Test: ALU_OPCODE=%b", ALU_OPCODE);
+
+        // Test LW instruction
+        #10 INSTRUCTION = 32'b000000000001_00010_010_00011_0000011; // LW
+        #10 $display("LW Test: MEMORY_ACCESS=%b, MEM_READ=%b", MEMORY_ACCESS, MEM_READ);
+
+        // Test SW instruction
+        #10 INSTRUCTION = 32'b0000000_00001_00010_010_00011_0100011; // SW
+        #10 $display("SW Test: MEMORY_ACCESS=%b, MEM_WRITE=%b", MEMORY_ACCESS, MEM_WRITE);
+
+        // Test JAL instruction
+        #10 INSTRUCTION = 32'b00000000000000000001_00000_1101111; // JAL
+        #10 $display("JAL Test: JUMP=%b, JUMP_AND_LINK=%b", JUMP, JUMP_AND_LINK);
+
+        // Test LUI instruction
+        #10 INSTRUCTION = 32'b00000000000000000001_00000_0110111; // LUI
+        #10 $display("LUI Test: IMMEDIATE_TYPE=%b, ALU_OPCODE=%b", IMMEDIATE_TYPE, ALU_OPCODE);
+
+        // Test B-type instruction (e.g., BEQ)
+        #10 INSTRUCTION = 32'b0000000_00001_00010_000_00011_1100011; // BEQ
+        #10 $display("BEQ Test: BRANCH=%b, ALU_OPCODE=%b", BRANCH, ALU_OPCODE);
+
+        // Finish simulation
+        #10 $finish;
+    end
+endmodule
diff --git a/ControlUnit/controlUnit_tb.vvp b/ControlUnit/controlUnit_tb.vvp
new file mode 100644
index 0000000..63f87ef
--- /dev/null
+++ b/ControlUnit/controlUnit_tb.vvp
@@ -0,0 +1,596 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1110-g18392a46)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_000001ed08d60600 .scope module, "controlUnit_tb" "controlUnit_tb" 2 5;
+ .timescale -9 -12;
+v000001ed08dddd00_0 .net "ALU_OPCODE", 4 0, v000001ed08d619c0_0;  1 drivers
+v000001ed08ddd580_0 .net "BRANCH", 0 0, v000001ed08d61a60_0;  1 drivers
+v000001ed08ddd080_0 .net "IMMEDIATE_SELECT", 0 0, v000001ed08d82080_0;  1 drivers
+v000001ed08ddd6c0_0 .net "IMMEDIATE_TYPE", 2 0, v000001ed08d82120_0;  1 drivers
+v000001ed08ddd120_0 .var "INSTRUCTION", 31 0;
+v000001ed08ddd1c0_0 .net "JUMP", 0 0, v000001ed08dddc60_0;  1 drivers
+v000001ed08ddd8a0_0 .net "JUMP_AND_LINK", 0 0, v000001ed08ddd300_0;  1 drivers
+v000001ed08dddda0_0 .net "MEMORY_ACCESS", 0 0, v000001ed08ddd800_0;  1 drivers
+v000001ed08ddd260_0 .net "MEM_READ", 0 0, v000001ed08dddbc0_0;  1 drivers
+v000001ed08ddd3a0_0 .net "MEM_WRITE", 0 0, v000001ed08dddee0_0;  1 drivers
+v000001ed08ddd440_0 .net "OFFSET_GENARATOR", 0 0, v000001ed08dddf80_0;  1 drivers
+v000001ed08ddda80_0 .net "WRITE_ENABLE", 0 0, v000001ed08ddd940_0;  1 drivers
+S_000001ed08d61830 .scope module, "uut" "controlUnit" 2 17, 3 1 0, S_000001ed08d60600;
+ .timescale 0 0;
+    .port_info 0 /INPUT 32 "INSTRUCTION";
+    .port_info 1 /OUTPUT 1 "WRITE_ENABLE";
+    .port_info 2 /OUTPUT 1 "MEMORY_ACCESS";
+    .port_info 3 /OUTPUT 1 "MEM_WRITE";
+    .port_info 4 /OUTPUT 1 "MEM_READ";
+    .port_info 5 /OUTPUT 1 "JUMP_AND_LINK";
+    .port_info 6 /OUTPUT 5 "ALU_OPCODE";
+    .port_info 7 /OUTPUT 1 "IMMEDIATE_SELECT";
+    .port_info 8 /OUTPUT 1 "OFFSET_GENARATOR";
+    .port_info 9 /OUTPUT 1 "BRANCH";
+    .port_info 10 /OUTPUT 1 "JUMP";
+    .port_info 11 /OUTPUT 3 "IMMEDIATE_TYPE";
+v000001ed08d619c0_0 .var "ALU_OPCODE", 4 0;
+v000001ed08d61a60_0 .var "BRANCH", 0 0;
+v000001ed08d79b00_0 .net "FUNCT3", 2 0, L_000001ed08dddb20;  1 drivers
+v000001ed08d81fe0_0 .net "FUNCT7", 6 0, L_000001ed08ddde40;  1 drivers
+v000001ed08d82080_0 .var "IMMEDIATE_SELECT", 0 0;
+v000001ed08d82120_0 .var "IMMEDIATE_TYPE", 2 0;
+v000001ed08d821c0_0 .net "INSTRUCTION", 31 0, v000001ed08ddd120_0;  1 drivers
+v000001ed08dddc60_0 .var "JUMP", 0 0;
+v000001ed08ddd300_0 .var "JUMP_AND_LINK", 0 0;
+v000001ed08ddd800_0 .var "MEMORY_ACCESS", 0 0;
+v000001ed08dddbc0_0 .var "MEM_READ", 0 0;
+v000001ed08dddee0_0 .var "MEM_WRITE", 0 0;
+v000001ed08dddf80_0 .var "OFFSET_GENARATOR", 0 0;
+v000001ed08ddd9e0_0 .net "OPCODE", 6 0, L_000001ed08ddd4e0;  1 drivers
+v000001ed08ddd940_0 .var "WRITE_ENABLE", 0 0;
+E_000001ed08d809f0 .event anyedge, v000001ed08d81fe0_0, v000001ed08d79b00_0, v000001ed08ddd9e0_0;
+L_000001ed08ddd4e0 .part v000001ed08ddd120_0, 0, 7;
+L_000001ed08dddb20 .part v000001ed08ddd120_0, 12, 3;
+L_000001ed08ddde40 .part v000001ed08ddd120_0, 25, 7;
+    .scope S_000001ed08d61830;
+T_0 ;
+    %wait E_000001ed08d809f0;
+    %load/vec4 v000001ed08ddd9e0_0;
+    %dup/vec4;
+    %pushi/vec4 51, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.0, 6;
+    %dup/vec4;
+    %pushi/vec4 19, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.1, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.2, 6;
+    %dup/vec4;
+    %pushi/vec4 35, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.3, 6;
+    %dup/vec4;
+    %pushi/vec4 111, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.4, 6;
+    %dup/vec4;
+    %pushi/vec4 103, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.5, 6;
+    %dup/vec4;
+    %pushi/vec4 55, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.6, 6;
+    %dup/vec4;
+    %pushi/vec4 23, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.7, 6;
+    %dup/vec4;
+    %pushi/vec4 99, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.8, 6;
+    %jmp T_0.9;
+T_0.0 ;
+    %pushi/vec4 7, 7, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %load/vec4 v000001ed08d81fe0_0;
+    %load/vec4 v000001ed08d79b00_0;
+    %concat/vec4; draw_concat_vec4
+    %dup/vec4;
+    %pushi/vec4 0, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.10, 6;
+    %dup/vec4;
+    %pushi/vec4 256, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.11, 6;
+    %dup/vec4;
+    %pushi/vec4 6, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.12, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.13, 6;
+    %dup/vec4;
+    %pushi/vec4 7, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.14, 6;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.15, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.16, 6;
+    %dup/vec4;
+    %pushi/vec4 261, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.17, 6;
+    %dup/vec4;
+    %pushi/vec4 8, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.18, 6;
+    %dup/vec4;
+    %pushi/vec4 9, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.19, 6;
+    %dup/vec4;
+    %pushi/vec4 11, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.20, 6;
+    %dup/vec4;
+    %pushi/vec4 10, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.21, 6;
+    %dup/vec4;
+    %pushi/vec4 12, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.22, 6;
+    %dup/vec4;
+    %pushi/vec4 13, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.23, 6;
+    %dup/vec4;
+    %pushi/vec4 14, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.24, 6;
+    %dup/vec4;
+    %pushi/vec4 15, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.25, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 10;
+    %cmp/u;
+    %jmp/1 T_0.26, 6;
+    %jmp T_0.27;
+T_0.10 ;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.11 ;
+    %pushi/vec4 1, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.12 ;
+    %pushi/vec4 2, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.13 ;
+    %pushi/vec4 3, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.14 ;
+    %pushi/vec4 4, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.15 ;
+    %pushi/vec4 5, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.16 ;
+    %pushi/vec4 6, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.17 ;
+    %pushi/vec4 7, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.18 ;
+    %pushi/vec4 8, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.19 ;
+    %pushi/vec4 9, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.20 ;
+    %pushi/vec4 10, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.21 ;
+    %pushi/vec4 11, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.22 ;
+    %pushi/vec4 12, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.23 ;
+    %pushi/vec4 13, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.24 ;
+    %pushi/vec4 14, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.25 ;
+    %pushi/vec4 15, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.26 ;
+    %pushi/vec4 16, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.27;
+T_0.27 ;
+    %pop/vec4 1;
+    %jmp T_0.9;
+T_0.1 ;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %load/vec4 v000001ed08d79b00_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.28, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.29, 6;
+    %dup/vec4;
+    %pushi/vec4 7, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.30, 6;
+    %dup/vec4;
+    %pushi/vec4 6, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.31, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.32, 6;
+    %jmp T_0.33;
+T_0.28 ;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.33;
+T_0.29 ;
+    %pushi/vec4 16, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.33;
+T_0.30 ;
+    %pushi/vec4 4, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.33;
+T_0.31 ;
+    %pushi/vec4 2, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.33;
+T_0.32 ;
+    %pushi/vec4 3, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.33;
+T_0.33 ;
+    %pop/vec4 1;
+    %load/vec4 v000001ed08d81fe0_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.34, 6;
+    %dup/vec4;
+    %pushi/vec4 32, 0, 7;
+    %cmp/u;
+    %jmp/1 T_0.35, 6;
+    %jmp T_0.36;
+T_0.34 ;
+    %load/vec4 v000001ed08d79b00_0;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.37, 6;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.38, 6;
+    %jmp T_0.39;
+T_0.37 ;
+    %pushi/vec4 6, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.39;
+T_0.38 ;
+    %pushi/vec4 5, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.39;
+T_0.39 ;
+    %pop/vec4 1;
+    %jmp T_0.36;
+T_0.35 ;
+    %load/vec4 v000001ed08d79b00_0;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.40, 6;
+    %jmp T_0.41;
+T_0.40 ;
+    %pushi/vec4 7, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.41;
+T_0.41 ;
+    %pop/vec4 1;
+    %jmp T_0.36;
+T_0.36 ;
+    %pop/vec4 1;
+    %jmp T_0.9;
+T_0.2 ;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.9;
+T_0.3 ;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.9;
+T_0.4 ;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.9;
+T_0.5 ;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.9;
+T_0.6 ;
+    %pushi/vec4 3, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %pushi/vec4 17, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.9;
+T_0.7 ;
+    %pushi/vec4 3, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.9;
+T_0.8 ;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v000001ed08d82120_0, 0, 3;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd940_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd800_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddee0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddbc0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08ddd300_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d82080_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08dddf80_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001ed08d61a60_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001ed08dddc60_0, 0, 1;
+    %pushi/vec4 0, 0, 5;
+    %store/vec4 v000001ed08d619c0_0, 0, 5;
+    %jmp T_0.9;
+T_0.9 ;
+    %pop/vec4 1;
+    %jmp T_0;
+    .thread T_0, $push;
+    .scope S_000001ed08d60600;
+T_1 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %pushi/vec4 1114595, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %vpi_call 2 38 "$display", "ADD Test: ALU_OPCODE=%b", v000001ed08dddd00_0 {0 0 0};
+    %delay 10000, 0;
+    %pushi/vec4 1114515, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %vpi_call 2 42 "$display", "ADDI Test: ALU_OPCODE=%b", v000001ed08dddd00_0 {0 0 0};
+    %delay 10000, 0;
+    %pushi/vec4 1122691, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %vpi_call 2 46 "$display", "LW Test: MEMORY_ACCESS=%b, MEM_READ=%b", v000001ed08dddda0_0, v000001ed08ddd260_0 {0 0 0};
+    %delay 10000, 0;
+    %pushi/vec4 1122723, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %vpi_call 2 50 "$display", "SW Test: MEMORY_ACCESS=%b, MEM_WRITE=%b", v000001ed08dddda0_0, v000001ed08ddd3a0_0 {0 0 0};
+    %delay 10000, 0;
+    %pushi/vec4 4207, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %vpi_call 2 54 "$display", "JAL Test: JUMP=%b, JUMP_AND_LINK=%b", v000001ed08ddd1c0_0, v000001ed08ddd8a0_0 {0 0 0};
+    %delay 10000, 0;
+    %pushi/vec4 4151, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %vpi_call 2 58 "$display", "LUI Test: IMMEDIATE_TYPE=%b, ALU_OPCODE=%b", v000001ed08ddd6c0_0, v000001ed08dddd00_0 {0 0 0};
+    %delay 10000, 0;
+    %pushi/vec4 1114595, 0, 32;
+    %store/vec4 v000001ed08ddd120_0, 0, 32;
+    %delay 10000, 0;
+    %vpi_call 2 62 "$display", "BEQ Test: BRANCH=%b, ALU_OPCODE=%b", v000001ed08ddd580_0, v000001ed08dddd00_0 {0 0 0};
+    %delay 10000, 0;
+    %vpi_call 2 65 "$finish" {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "controlUnit_tb.v";
+    "controlUnit.v";
diff --git a/ImidiateGenarator/imidiateGenarator.v b/ImidiateGenarator/imidiateGenarator.v
new file mode 100644
index 0000000..f4ab8ae
--- /dev/null
+++ b/ImidiateGenarator/imidiateGenarator.v
@@ -0,0 +1,21 @@
+module imidiateGenarator(INSTRUCTION,IMMEDIATE_TYPE,IMMEDIATE_VALUE);
+input [31:0] INSTRUCTION;
+input [2:0] IMMEDIATE_TYPE;
+output reg[31:0] IMMEDIATE_VALUE;
+
+always @(INSTRUCTION,IMMEDIATE_TYPE) begin
+    case (IMMEDIATE_TYPE)
+
+        3'b000: IMMEDIATE_VALUE = {{21{INSTRUCTION[31]}},INSTRUCTION[30:25],INSTRUCTION[24:21],INSTRUCTION[20]};
+        3'b001: IMMEDIATE_VALUE = {{21{INSTRUCTION[31]}},INSTRUCTION[30:25],INSTRUCTION[11:8],INSTRUCTION[7]};
+        3'b010: IMMEDIATE_VALUE = {{12{INSTRUCTION[31]}},INSTRUCTION[19:12],INSTRUCTION[20],INSTRUCTION[30:25],INSTRUCTION[24:21],1'b0};
+        3'b011: IMMEDIATE_VALUE = {INSTRUCTION[31],INSTRUCTION[30:20],INSTRUCTION[19:12],12'b0};
+        3'b100: IMMEDIATE_VALUE = {{20{INSTRUCTION[31]}},INSTRUCTION[7],INSTRUCTION[30:25],INSTRUCTION[11:8],1'b0};
+        
+    endcase
+
+
+    end
+
+
+endmodule
\ No newline at end of file
diff --git a/ImidiateGenarator/imidiateGenarator_tb.v b/ImidiateGenarator/imidiateGenarator_tb.v
new file mode 100644
index 0000000..f06086a
--- /dev/null
+++ b/ImidiateGenarator/imidiateGenarator_tb.v
@@ -0,0 +1,73 @@
+module immediateGenerator_tb;
+
+    // Testbench inputs and outputs
+    reg [31:0] INSTRUCTION;
+    reg [2:0] IMMEDIATE_TYPE;
+    wire [31:0] IMMEDIATE_VALUE;
+
+    // Instantiate the module under test
+    imidiateGenarator uut (
+        .INSTRUCTION(INSTRUCTION),
+        .IMMEDIATE_TYPE(IMMEDIATE_TYPE),
+        .IMMEDIATE_VALUE(IMMEDIATE_VALUE)
+    );
+
+    // Test sequence
+    initial begin
+        $display("Testbench started...");
+
+        // Test case 1: IMMEDIATE_TYPE = 3'b000
+        INSTRUCTION = 32'b00010010001101000101011001111000; // Example instruction
+        IMMEDIATE_TYPE = 3'b000;
+        #10; 
+       $display("IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b",
+    IMMEDIATE_VALUE[31:28], IMMEDIATE_VALUE[27:24],
+    IMMEDIATE_VALUE[23:20], IMMEDIATE_VALUE[19:16],
+    IMMEDIATE_VALUE[15:12], IMMEDIATE_VALUE[11:8],
+    IMMEDIATE_VALUE[7:4], IMMEDIATE_VALUE[3:0]);
+
+        // Test case 2: IMMEDIATE_TYPE = 3'b001
+        INSTRUCTION = 32'b10000111011001010100001100100001; // Example instruction
+        IMMEDIATE_TYPE = 3'b001;
+        #10; 
+       $display("IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b",
+    IMMEDIATE_VALUE[31:28], IMMEDIATE_VALUE[27:24],
+    IMMEDIATE_VALUE[23:20], IMMEDIATE_VALUE[19:16],
+    IMMEDIATE_VALUE[15:12], IMMEDIATE_VALUE[11:8],
+    IMMEDIATE_VALUE[7:4], IMMEDIATE_VALUE[3:0]);
+
+        // Test case 3: IMMEDIATE_TYPE = 3'b010
+        INSTRUCTION = 32'b11111110110111001011101010011000; // Example instruction
+        IMMEDIATE_TYPE = 3'b010;
+        #10; 
+       $display("IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b",
+    IMMEDIATE_VALUE[31:28], IMMEDIATE_VALUE[27:24],
+    IMMEDIATE_VALUE[23:20], IMMEDIATE_VALUE[19:16],
+    IMMEDIATE_VALUE[15:12], IMMEDIATE_VALUE[11:8],
+    IMMEDIATE_VALUE[7:4], IMMEDIATE_VALUE[3:0]);
+
+        // Test case 4: IMMEDIATE_TYPE = 3'b011
+        INSTRUCTION = 32'b00001010101111001101111011110000; // Example instruction
+        IMMEDIATE_TYPE = 3'b011;
+        #10; 
+       $display("IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b",
+    IMMEDIATE_VALUE[31:28], IMMEDIATE_VALUE[27:24],
+    IMMEDIATE_VALUE[23:20], IMMEDIATE_VALUE[19:16],
+    IMMEDIATE_VALUE[15:12], IMMEDIATE_VALUE[11:8],
+    IMMEDIATE_VALUE[7:4], IMMEDIATE_VALUE[3:0]);
+
+        // Test case 5: IMMEDIATE_TYPE = 3'b100
+        INSTRUCTION = 32'b10100001101100101100001111010100; // Example instruction
+        IMMEDIATE_TYPE = 3'b100;
+        #10; 
+        $display("IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b",
+    IMMEDIATE_VALUE[31:28], IMMEDIATE_VALUE[27:24],
+    IMMEDIATE_VALUE[23:20], IMMEDIATE_VALUE[19:16],
+    IMMEDIATE_VALUE[15:12], IMMEDIATE_VALUE[11:8],
+    IMMEDIATE_VALUE[7:4], IMMEDIATE_VALUE[3:0]);
+
+        $display("Testbench finished.");
+        $finish;
+    end
+
+endmodule
diff --git a/ImidiateGenarator/imidiateGenarator_tb.vvp b/ImidiateGenarator/imidiateGenarator_tb.vvp
new file mode 100644
index 0000000..c7beecd
--- /dev/null
+++ b/ImidiateGenarator/imidiateGenarator_tb.vvp
@@ -0,0 +1,172 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1110-g18392a46)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_000001fa56ccac90 .scope module, "immediateGenerator_tb" "immediateGenerator_tb" 2 1;
+ .timescale 0 0;
+v000001fa56cce4a0_0 .var "IMMEDIATE_TYPE", 2 0;
+v000001fa56cce540_0 .net "IMMEDIATE_VALUE", 31 0, v000001fa56ccbdb0_0;  1 drivers
+v000001fa56cce5e0_0 .var "INSTRUCTION", 31 0;
+S_000001fa56ccbb80 .scope module, "uut" "imidiateGenarator" 2 9, 3 1 0, S_000001fa56ccac90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 32 "INSTRUCTION";
+    .port_info 1 /INPUT 3 "IMMEDIATE_TYPE";
+    .port_info 2 /OUTPUT 32 "IMMEDIATE_VALUE";
+v000001fa56ccbd10_0 .net "IMMEDIATE_TYPE", 2 0, v000001fa56cce4a0_0;  1 drivers
+v000001fa56ccbdb0_0 .var "IMMEDIATE_VALUE", 31 0;
+v000001fa56cce400_0 .net "INSTRUCTION", 31 0, v000001fa56cce5e0_0;  1 drivers
+E_000001fa56b17fa0 .event anyedge, v000001fa56ccbd10_0, v000001fa56cce400_0;
+    .scope S_000001fa56ccbb80;
+T_0 ;
+    %wait E_000001fa56b17fa0;
+    %load/vec4 v000001fa56ccbd10_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.0, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.1, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.2, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.3, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.4, 6;
+    %jmp T_0.5;
+T_0.0 ;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 31, 6;
+    %replicate 21;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 6, 25, 6;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 4, 21, 6;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 20, 6;
+    %concat/vec4; draw_concat_vec4
+    %store/vec4 v000001fa56ccbdb0_0, 0, 32;
+    %jmp T_0.5;
+T_0.1 ;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 31, 6;
+    %replicate 21;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 6, 25, 6;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 4, 8, 5;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 7, 4;
+    %concat/vec4; draw_concat_vec4
+    %store/vec4 v000001fa56ccbdb0_0, 0, 32;
+    %jmp T_0.5;
+T_0.2 ;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 31, 6;
+    %replicate 12;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 8, 12, 5;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 20, 6;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 6, 25, 6;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 4, 21, 6;
+    %concat/vec4; draw_concat_vec4
+    %concati/vec4 0, 0, 1;
+    %store/vec4 v000001fa56ccbdb0_0, 0, 32;
+    %jmp T_0.5;
+T_0.3 ;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 31, 6;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 11, 20, 6;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 8, 12, 5;
+    %concat/vec4; draw_concat_vec4
+    %concati/vec4 0, 0, 12;
+    %store/vec4 v000001fa56ccbdb0_0, 0, 32;
+    %jmp T_0.5;
+T_0.4 ;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 31, 6;
+    %replicate 20;
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 1, 7, 4;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 6, 25, 6;
+    %concat/vec4; draw_concat_vec4
+    %load/vec4 v000001fa56cce400_0;
+    %parti/s 4, 8, 5;
+    %concat/vec4; draw_concat_vec4
+    %concati/vec4 0, 0, 1;
+    %store/vec4 v000001fa56ccbdb0_0, 0, 32;
+    %jmp T_0.5;
+T_0.5 ;
+    %pop/vec4 1;
+    %jmp T_0;
+    .thread T_0, $push;
+    .scope S_000001fa56ccac90;
+T_1 ;
+    %vpi_call 2 17 "$display", "Testbench started..." {0 0 0};
+    %pushi/vec4 305419896, 0, 32;
+    %store/vec4 v000001fa56cce5e0_0, 0, 32;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v000001fa56cce4a0_0, 0, 3;
+    %delay 10, 0;
+    %vpi_call 2 23 "$display", "IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b", &PV<v000001fa56cce540_0, 28, 4>, &PV<v000001fa56cce540_0, 24, 4>, &PV<v000001fa56cce540_0, 20, 4>, &PV<v000001fa56cce540_0, 16, 4>, &PV<v000001fa56cce540_0, 12, 4>, &PV<v000001fa56cce540_0, 8, 4>, &PV<v000001fa56cce540_0, 4, 4>, &PV<v000001fa56cce540_0, 0, 4> {0 0 0};
+    %pushi/vec4 2271560481, 0, 32;
+    %store/vec4 v000001fa56cce5e0_0, 0, 32;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v000001fa56cce4a0_0, 0, 3;
+    %delay 10, 0;
+    %vpi_call 2 33 "$display", "IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b", &PV<v000001fa56cce540_0, 28, 4>, &PV<v000001fa56cce540_0, 24, 4>, &PV<v000001fa56cce540_0, 20, 4>, &PV<v000001fa56cce540_0, 16, 4>, &PV<v000001fa56cce540_0, 12, 4>, &PV<v000001fa56cce540_0, 8, 4>, &PV<v000001fa56cce540_0, 4, 4>, &PV<v000001fa56cce540_0, 0, 4> {0 0 0};
+    %pushi/vec4 4275878552, 0, 32;
+    %store/vec4 v000001fa56cce5e0_0, 0, 32;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v000001fa56cce4a0_0, 0, 3;
+    %delay 10, 0;
+    %vpi_call 2 43 "$display", "IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b", &PV<v000001fa56cce540_0, 28, 4>, &PV<v000001fa56cce540_0, 24, 4>, &PV<v000001fa56cce540_0, 20, 4>, &PV<v000001fa56cce540_0, 16, 4>, &PV<v000001fa56cce540_0, 12, 4>, &PV<v000001fa56cce540_0, 8, 4>, &PV<v000001fa56cce540_0, 4, 4>, &PV<v000001fa56cce540_0, 0, 4> {0 0 0};
+    %pushi/vec4 180150000, 0, 32;
+    %store/vec4 v000001fa56cce5e0_0, 0, 32;
+    %pushi/vec4 3, 0, 3;
+    %store/vec4 v000001fa56cce4a0_0, 0, 3;
+    %delay 10, 0;
+    %vpi_call 2 53 "$display", "IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b", &PV<v000001fa56cce540_0, 28, 4>, &PV<v000001fa56cce540_0, 24, 4>, &PV<v000001fa56cce540_0, 20, 4>, &PV<v000001fa56cce540_0, 16, 4>, &PV<v000001fa56cce540_0, 12, 4>, &PV<v000001fa56cce540_0, 8, 4>, &PV<v000001fa56cce540_0, 4, 4>, &PV<v000001fa56cce540_0, 0, 4> {0 0 0};
+    %pushi/vec4 2712847316, 0, 32;
+    %store/vec4 v000001fa56cce5e0_0, 0, 32;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v000001fa56cce4a0_0, 0, 3;
+    %delay 10, 0;
+    %vpi_call 2 63 "$display", "IMMEDIATE_VALUE = %b %b %b %b %b %b %b %b", &PV<v000001fa56cce540_0, 28, 4>, &PV<v000001fa56cce540_0, 24, 4>, &PV<v000001fa56cce540_0, 20, 4>, &PV<v000001fa56cce540_0, 16, 4>, &PV<v000001fa56cce540_0, 12, 4>, &PV<v000001fa56cce540_0, 8, 4>, &PV<v000001fa56cce540_0, 4, 4>, &PV<v000001fa56cce540_0, 0, 4> {0 0 0};
+    %vpi_call 2 69 "$display", "Testbench finished." {0 0 0};
+    %vpi_call 2 70 "$finish" {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "imidiateGenarator_tb.v";
+    "imidiateGenarator.v";
diff --git a/MUX_32bit/MUX_32bit.v b/MUX_32bit/MUX_32bit.v
new file mode 100644
index 0000000..28addca
--- /dev/null
+++ b/MUX_32bit/MUX_32bit.v
@@ -0,0 +1,15 @@
+module MUX_32bit(INPUT_0,INPUT_1,SELECT,OUTPUT);
+input [31:0] INPUT_0,INPUT_1;
+input SELECT;
+output reg [31:0] OUTPUT;
+
+always @(INPUT_0,INPUT_1,SELECT) begin
+    if (SELECT == 1'b0) begin
+        OUTPUT = INPUT_0;
+    end
+    else begin
+        OUTPUT = INPUT_1;
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/README.md b/README.md
index 3742bec..a71c4bd 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,13 @@
-___
-# DELETE THIS INSTRUCTIONS AND ADD A SHORT INTRODUCTION ABOUT YOUR PROJECT
-___
+# co502 RV32IM pipeline implementation group 2
+This Git repository contains the implementation of a RISC32IM processor pipeline using Verilog. The pipeline includes stages for instruction fetch, decode, execute, memory access, and write-back. The implementation includes a testbench for verification.
 
-## Please refer the instructions in below URL:
 
-https://projects.ce.pdn.ac.lk/docs/how-to-add-a-project
+
+
+ ### Team Members: 
+1) E/20/419 - Wakkumbura M.M.S.S. , e20419@eng.pdn.ac.lk
+2) E/20/439 - Wickramasinghe J.M.W.G.R.L. , e20439@eng.pdn.ac.lk
+3) E/20/036 - Bandara K.G.R.I , e20036@eng.pdn.ac.lk 
+ ### Project Supervisors: 
+1) Dr. Isuru Nawinne , isurunawinne@eng.pdn.ac.lk
+
diff --git a/docs/README.md b/docs/README.md
index 1240660..8f84542 100644
--- a/docs/README.md
+++ b/docs/README.md
@@ -3,14 +3,14 @@ layout: home
 permalink: index.html
 
 # Please update this with your repository name and title
-repository-name: eYY-XXX-project-template
-title:
+repository-name: e20-co502-RV32IM-pipeline-implementation-group-2
+title: RV32MI pipeline Implementation group 02
 ---
 
 [comment]: # "This is the standard layout for the project, but you can clean this and use your own template"
 
 # Project Title
-
+RV32MI pipeline Implementation
 ---
 
 <!-- 
@@ -20,9 +20,13 @@ This is a sample image, to show how to add images to your page. To learn more op
  -->
 
 ## Team
--  eNumber, Name, [email](mailto:name@email.com)
--  eNumber, Name, [email](mailto:name@email.com)
--  eNumber, Name, [email](mailto:name@email.com)
+- **E/20/419** - Wakkumbura M.M.S.S. ([e20419@eng.pdn.ac.lk](mailto:e20419@eng.pdn.ac.lk))
+- **E/20/439** - Wickramasinghe J.M.W.G.R.L. ([e20439@eng.pdn.ac.lk](mailto:e20439@eng.pdn.ac.lk))
+- **E/20/036** - Bandara K.G.R.I ([e20036@eng.pdn.ac.lk](mailto:e20036@eng.pdn.ac.lk))
+
+## Supervisors
+
+- Dr. Isuru Nawinne ([isurunawinne@eng.pdn.ac.lk](mailto:isurunawinne@eng.pdn.ac.lk))
 
 ## Table of Contents
 1. [Introduction](#introduction)
@@ -33,7 +37,7 @@ This is a sample image, to show how to add images to your page. To learn more op
 
 ## Introduction
 
- description of the real world problem and solution, impact
+This project aims to implement an in-order 5-stage pipelined CPU which implements the RV32I base instruction set and the M instruction set extension for multiplication/division operations as per the RISC-V ISA specification.
 
 ## Other Sub Topics
 
@@ -41,8 +45,8 @@ This is a sample image, to show how to add images to your page. To learn more op
 
 ## Links
 
-- [Project Repository](https://github.com/cepdnaclk/{{ page.repository-name }}){:target="_blank"}
-- [Project Page](https://cepdnaclk.github.io/{{ page.repository-name}}){:target="_blank"}
+- [Project Repository](https://github.com/cepdnaclk/e20-co502-RV32IM-pipeline-implementation-group-2)
+- [Project Page](https://cepdnaclk.github.io/e20-co502-RV32IM-pipeline-implementation-group-2)
 - [Department of Computer Engineering](http://www.ce.pdn.ac.lk/)
 - [University of Peradeniya](https://eng.pdn.ac.lk/)