From 7e005c33dd411660b532e0ccb4c698b5b95974a3 Mon Sep 17 00:00:00 2001 From: Diego Nehab <1635557+diegonehab@users.noreply.github.com> Date: Fri, 20 Dec 2024 23:42:18 +0000 Subject: [PATCH] refactor: simplify register addresses even more --- src/clua-cartesi.cpp | 1 - src/interpret.cpp | 2 +- src/machine-c-api.cpp | 315 ++++++++- src/machine-c-api.h | 2 - src/machine-reg.h | 300 ++++---- src/machine.cpp | 86 ++- src/record-state-access.h | 6 +- src/record-step-state-access.h | 172 ++--- src/replay-state-access.h | 8 +- src/replay-step-state-access.h | 152 ++--- src/shadow-state-factory.cpp | 72 +- src/shadow-state.h | 359 ---------- src/shadow-uarch-state-factory.cpp | 35 +- src/shadow-uarch-state.h | 142 ---- src/uarch-bridge.h | 1013 ++++++++++++++-------------- src/uarch-record-state-access.h | 27 +- src/uarch-replay-state-access.h | 20 +- uarch/uarch-machine-state-access.h | 157 +++-- 18 files changed, 1410 insertions(+), 1459 deletions(-) diff --git a/src/clua-cartesi.cpp b/src/clua-cartesi.cpp index beccff0f..9d513eda 100644 --- a/src/clua-cartesi.cpp +++ b/src/clua-cartesi.cpp @@ -192,7 +192,6 @@ CM_API int luaopen_cartesi(lua_State *L) { clua_setintegerfield(L, CM_VERSION_MINOR, "VERSION_MINOR", -1); clua_setintegerfield(L, CM_VERSION_PATCH, "VERSION_PATCH", -1); clua_setintegerfield(L, CM_HASH_SIZE, "HASH_SIZE", -1); - clua_setintegerfield(L, CM_REG_COUNT, "REG_COUNT", -1); clua_setintegerfield(L, CM_TREE_LOG2_WORD_SIZE, "TREE_LOG2_WORD_SIZE", -1); clua_setintegerfield(L, CM_TREE_LOG2_PAGE_SIZE, "TREE_LOG2_PAGE_SIZE", -1); clua_setintegerfield(L, CM_TREE_LOG2_ROOT_SIZE, "TREE_LOG2_ROOT_SIZE", -1); diff --git a/src/interpret.cpp b/src/interpret.cpp index 572d317e..65109d2a 100644 --- a/src/interpret.cpp +++ b/src/interpret.cpp @@ -5638,7 +5638,7 @@ interpreter_break_reason interpret(STATE_ACCESS &a, uint64_t mcycle_end) { } if (status == execute_status::success_and_yield) { return interpreter_break_reason::yielded_softly; - } // Reached mcycle_end + } // Reached mcycle_end assert(a.read_mcycle() == mcycle_end); // LCOV_EXCL_LINE return interpreter_break_reason::reached_target_mcycle; } diff --git a/src/machine-c-api.cpp b/src/machine-c-api.cpp index c93060cc..148c5832 100644 --- a/src/machine-c-api.cpp +++ b/src/machine-c-api.cpp @@ -125,6 +125,315 @@ cm_error cm_result_success() { // -------------------------------------------- // Conversion functions // -------------------------------------------- + +static cartesi::machine_reg convert_from_c(cm_reg r) { + using reg = cartesi::machine_reg; + switch (r) { + case CM_REG_X0: + return reg::x0; + case CM_REG_X1: + return reg::x1; + case CM_REG_X2: + return reg::x2; + case CM_REG_X3: + return reg::x3; + case CM_REG_X4: + return reg::x4; + case CM_REG_X5: + return reg::x5; + case CM_REG_X6: + return reg::x6; + case CM_REG_X7: + return reg::x7; + case CM_REG_X8: + return reg::x8; + case CM_REG_X9: + return reg::x9; + case CM_REG_X10: + return reg::x10; + case CM_REG_X11: + return reg::x11; + case CM_REG_X12: + return reg::x12; + case CM_REG_X13: + return reg::x13; + case CM_REG_X14: + return reg::x14; + case CM_REG_X15: + return reg::x15; + case CM_REG_X16: + return reg::x16; + case CM_REG_X17: + return reg::x17; + case CM_REG_X18: + return reg::x18; + case CM_REG_X19: + return reg::x19; + case CM_REG_X20: + return reg::x20; + case CM_REG_X21: + return reg::x21; + case CM_REG_X22: + return reg::x22; + case CM_REG_X23: + return reg::x23; + case CM_REG_X24: + return reg::x24; + case CM_REG_X25: + return reg::x25; + case CM_REG_X26: + return reg::x26; + case CM_REG_X27: + return reg::x27; + case CM_REG_X28: + return reg::x28; + case CM_REG_X29: + return reg::x29; + case CM_REG_X30: + return reg::x30; + case CM_REG_X31: + return reg::x31; + case CM_REG_F0: + return reg::f0; + case CM_REG_F1: + return reg::f1; + case CM_REG_F2: + return reg::f2; + case CM_REG_F3: + return reg::f3; + case CM_REG_F4: + return reg::f4; + case CM_REG_F5: + return reg::f5; + case CM_REG_F6: + return reg::f6; + case CM_REG_F7: + return reg::f7; + case CM_REG_F8: + return reg::f8; + case CM_REG_F9: + return reg::f9; + case CM_REG_F10: + return reg::f10; + case CM_REG_F11: + return reg::f11; + case CM_REG_F12: + return reg::f12; + case CM_REG_F13: + return reg::f13; + case CM_REG_F14: + return reg::f14; + case CM_REG_F15: + return reg::f15; + case CM_REG_F16: + return reg::f16; + case CM_REG_F17: + return reg::f17; + case CM_REG_F18: + return reg::f18; + case CM_REG_F19: + return reg::f19; + case CM_REG_F20: + return reg::f20; + case CM_REG_F21: + return reg::f21; + case CM_REG_F22: + return reg::f22; + case CM_REG_F23: + return reg::f23; + case CM_REG_F24: + return reg::f24; + case CM_REG_F25: + return reg::f25; + case CM_REG_F26: + return reg::f26; + case CM_REG_F27: + return reg::f27; + case CM_REG_F28: + return reg::f28; + case CM_REG_F29: + return reg::f29; + case CM_REG_F30: + return reg::f30; + case CM_REG_F31: + return reg::f31; + case CM_REG_PC: + return reg::pc; + case CM_REG_FCSR: + return reg::fcsr; + case CM_REG_MVENDORID: + return reg::mvendorid; + case CM_REG_MARCHID: + return reg::marchid; + case CM_REG_MIMPID: + return reg::mimpid; + case CM_REG_MCYCLE: + return reg::mcycle; + case CM_REG_ICYCLEINSTRET: + return reg::icycleinstret; + case CM_REG_MSTATUS: + return reg::mstatus; + case CM_REG_MTVEC: + return reg::mtvec; + case CM_REG_MSCRATCH: + return reg::mscratch; + case CM_REG_MEPC: + return reg::mepc; + case CM_REG_MCAUSE: + return reg::mcause; + case CM_REG_MTVAL: + return reg::mtval; + case CM_REG_MISA: + return reg::misa; + case CM_REG_MIE: + return reg::mie; + case CM_REG_MIP: + return reg::mip; + case CM_REG_MEDELEG: + return reg::medeleg; + case CM_REG_MIDELEG: + return reg::mideleg; + case CM_REG_MCOUNTEREN: + return reg::mcounteren; + case CM_REG_MENVCFG: + return reg::menvcfg; + case CM_REG_STVEC: + return reg::stvec; + case CM_REG_SSCRATCH: + return reg::sscratch; + case CM_REG_SEPC: + return reg::sepc; + case CM_REG_SCAUSE: + return reg::scause; + case CM_REG_STVAL: + return reg::stval; + case CM_REG_SATP: + return reg::satp; + case CM_REG_SCOUNTEREN: + return reg::scounteren; + case CM_REG_SENVCFG: + return reg::senvcfg; + case CM_REG_ILRSC: + return reg::ilrsc; + case CM_REG_IFLAGS: + return reg::iflags; + case CM_REG_IUNREP: + return reg::iunrep; + case CM_REG_CLINT_MTIMECMP: + return reg::clint_mtimecmp; + case CM_REG_PLIC_GIRQPEND: + return reg::plic_girqpend; + case CM_REG_PLIC_GIRQSRVD: + return reg::plic_girqsrvd; + case CM_REG_HTIF_TOHOST: + return reg::htif_tohost; + case CM_REG_HTIF_FROMHOST: + return reg::htif_fromhost; + case CM_REG_HTIF_IHALT: + return reg::htif_ihalt; + case CM_REG_HTIF_ICONSOLE: + return reg::htif_iconsole; + case CM_REG_HTIF_IYIELD: + return reg::htif_iyield; + case CM_REG_UARCH_X0: + return reg::uarch_x0; + case CM_REG_UARCH_X1: + return reg::uarch_x1; + case CM_REG_UARCH_X2: + return reg::uarch_x2; + case CM_REG_UARCH_X3: + return reg::uarch_x3; + case CM_REG_UARCH_X4: + return reg::uarch_x4; + case CM_REG_UARCH_X5: + return reg::uarch_x5; + case CM_REG_UARCH_X6: + return reg::uarch_x6; + case CM_REG_UARCH_X7: + return reg::uarch_x7; + case CM_REG_UARCH_X8: + return reg::uarch_x8; + case CM_REG_UARCH_X9: + return reg::uarch_x9; + case CM_REG_UARCH_X10: + return reg::uarch_x10; + case CM_REG_UARCH_X11: + return reg::uarch_x11; + case CM_REG_UARCH_X12: + return reg::uarch_x12; + case CM_REG_UARCH_X13: + return reg::uarch_x13; + case CM_REG_UARCH_X14: + return reg::uarch_x14; + case CM_REG_UARCH_X15: + return reg::uarch_x15; + case CM_REG_UARCH_X16: + return reg::uarch_x16; + case CM_REG_UARCH_X17: + return reg::uarch_x17; + case CM_REG_UARCH_X18: + return reg::uarch_x18; + case CM_REG_UARCH_X19: + return reg::uarch_x19; + case CM_REG_UARCH_X20: + return reg::uarch_x20; + case CM_REG_UARCH_X21: + return reg::uarch_x21; + case CM_REG_UARCH_X22: + return reg::uarch_x22; + case CM_REG_UARCH_X23: + return reg::uarch_x23; + case CM_REG_UARCH_X24: + return reg::uarch_x24; + case CM_REG_UARCH_X25: + return reg::uarch_x25; + case CM_REG_UARCH_X26: + return reg::uarch_x26; + case CM_REG_UARCH_X27: + return reg::uarch_x27; + case CM_REG_UARCH_X28: + return reg::uarch_x28; + case CM_REG_UARCH_X29: + return reg::uarch_x29; + case CM_REG_UARCH_X30: + return reg::uarch_x30; + case CM_REG_UARCH_X31: + return reg::uarch_x31; + case CM_REG_UARCH_PC: + return reg::uarch_pc; + case CM_REG_UARCH_CYCLE: + return reg::uarch_cycle; + case CM_REG_UARCH_HALT_FLAG: + return reg::uarch_halt_flag; + case CM_REG_IFLAGS_PRV: + return reg::iflags_prv; + case CM_REG_IFLAGS_X: + return reg::iflags_x; + case CM_REG_IFLAGS_Y: + return reg::iflags_y; + case CM_REG_IFLAGS_H: + return reg::iflags_h; + case CM_REG_HTIF_TOHOST_DEV: + return reg::htif_tohost_dev; + case CM_REG_HTIF_TOHOST_CMD: + return reg::htif_tohost_cmd; + case CM_REG_HTIF_TOHOST_REASON: + return reg::htif_tohost_reason; + case CM_REG_HTIF_TOHOST_DATA: + return reg::htif_tohost_data; + case CM_REG_HTIF_FROMHOST_DEV: + return reg::htif_fromhost_dev; + case CM_REG_HTIF_FROMHOST_CMD: + return reg::htif_fromhost_cmd; + case CM_REG_HTIF_FROMHOST_REASON: + return reg::htif_fromhost_reason; + case CM_REG_HTIF_FROMHOST_DATA: + return reg::htif_fromhost_data; + case CM_REG_UNKNOWN: + return reg::unknown_; + } +} + static cartesi::i_virtual_machine *convert_from_c(cm_machine *m) { if (m == nullptr) { throw std::invalid_argument("invalid machine"); @@ -482,7 +791,7 @@ cm_error cm_read_reg(const cm_machine *m, cm_reg reg, uint64_t *val) try { throw std::invalid_argument("invalid val output"); } const auto *cpp_m = convert_from_c(m); - auto cpp_reg = static_cast(reg); + auto cpp_reg = convert_from_c(reg); *val = cpp_m->read_reg(cpp_reg); return cm_result_success(); } catch (...) { @@ -494,7 +803,7 @@ cm_error cm_read_reg(const cm_machine *m, cm_reg reg, uint64_t *val) try { cm_error cm_write_reg(cm_machine *m, cm_reg reg, uint64_t val) try { auto *cpp_m = convert_from_c(m); - auto cpp_reg = static_cast(reg); + auto cpp_reg = convert_from_c(reg); cpp_m->write_reg(cpp_reg, val); return cm_result_success(); } catch (...) { @@ -505,7 +814,7 @@ cm_error cm_get_reg_address(const cm_machine *m, cm_reg reg, uint64_t *val) try if (val == nullptr) { throw std::invalid_argument("invalid val output"); } - auto cpp_reg = static_cast(reg); + auto cpp_reg = convert_from_c(reg); if (m != nullptr) { const auto *cpp_m = convert_from_c(m); *val = cpp_m->get_reg_address(cpp_reg); diff --git a/src/machine-c-api.h b/src/machine-c-api.h index 91dee133..9b10b506 100644 --- a/src/machine-c-api.h +++ b/src/machine-c-api.h @@ -273,8 +273,6 @@ typedef enum cm_reg { CM_REG_UARCH_PC, CM_REG_UARCH_CYCLE, CM_REG_UARCH_HALT_FLAG, - // Amount of registers - CM_REG_COUNT, // Views of registers CM_REG_IFLAGS_PRV, CM_REG_IFLAGS_X, diff --git a/src/machine-reg.h b/src/machine-reg.h index 3774915c..9ccc571c 100644 --- a/src/machine-reg.h +++ b/src/machine-reg.h @@ -17,160 +17,162 @@ #ifndef MACHINE_REG_H #define MACHINE_REG_H +#include "pma-constants.h" +#include "shadow-state.h" +#include "shadow-uarch-state.h" + /// \file /// \brief Cartesi machine registers namespace cartesi { /// \brief List of machine registers -enum class machine_reg { +enum class machine_reg : uint64_t { // Processor x registers - first_ = 0, - x0 = first_, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - // Processor f registers - f0, - f1, - f2, - f3, - f4, - f5, - f6, - f7, - f8, - f9, - f10, - f11, - f12, - f13, - f14, - f15, - f16, - f17, - f18, - f19, - f20, - f21, - f22, - f23, - f24, - f25, - f26, - f27, - f28, - f29, - f30, - f31, - // Processor CSRs - pc, - fcsr, - mvendorid, - marchid, - mimpid, - mcycle, - icycleinstret, - mstatus, - mtvec, - mscratch, - mepc, - mcause, - mtval, - misa, - mie, - mip, - medeleg, - mideleg, - mcounteren, - menvcfg, - stvec, - sscratch, - sepc, - scause, - stval, - satp, - scounteren, - senvcfg, - ilrsc, - iflags, - iunrep, - clint_mtimecmp, - plic_girqpend, - plic_girqsrvd, - htif_tohost, - htif_fromhost, - htif_ihalt, - htif_iconsole, - htif_iyield, + x0 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[0]), + x1 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[1]), + x2 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[2]), + x3 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[3]), + x4 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[4]), + x5 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[5]), + x6 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[6]), + x7 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[7]), + x8 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[8]), + x9 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[9]), + x10 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[10]), + x11 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[11]), + x12 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[12]), + x13 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[13]), + x14 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[14]), + x15 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[15]), + x16 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[16]), + x17 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[17]), + x18 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[18]), + x19 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[19]), + x20 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[20]), + x21 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[21]), + x22 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[22]), + x23 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[23]), + x24 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[24]), + x25 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[25]), + x26 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[26]), + x27 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[27]), + x28 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[28]), + x29 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[29]), + x30 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[30]), + x31 = PMA_SHADOW_STATE_START + offsetof(shadow_state, x[31]), + f0 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[0]), + f1 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[1]), + f2 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[2]), + f3 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[3]), + f4 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[4]), + f5 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[5]), + f6 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[6]), + f7 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[7]), + f8 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[8]), + f9 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[9]), + f10 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[10]), + f11 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[11]), + f12 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[12]), + f13 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[13]), + f14 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[14]), + f15 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[15]), + f16 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[16]), + f17 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[17]), + f18 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[18]), + f19 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[19]), + f20 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[20]), + f21 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[21]), + f22 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[22]), + f23 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[23]), + f24 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[24]), + f25 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[25]), + f26 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[26]), + f27 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[27]), + f28 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[28]), + f29 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[29]), + f30 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[30]), + f31 = PMA_SHADOW_STATE_START + offsetof(shadow_state, f[31]), + pc = PMA_SHADOW_STATE_START + offsetof(shadow_state, pc), + fcsr = PMA_SHADOW_STATE_START + offsetof(shadow_state, fcsr), + mvendorid = PMA_SHADOW_STATE_START + offsetof(shadow_state, mvendorid), + marchid = PMA_SHADOW_STATE_START + offsetof(shadow_state, marchid), + mimpid = PMA_SHADOW_STATE_START + offsetof(shadow_state, mimpid), + mcycle = PMA_SHADOW_STATE_START + offsetof(shadow_state, mcycle), + icycleinstret = PMA_SHADOW_STATE_START + offsetof(shadow_state, icycleinstret), + mstatus = PMA_SHADOW_STATE_START + offsetof(shadow_state, mstatus), + mtvec = PMA_SHADOW_STATE_START + offsetof(shadow_state, mtvec), + mscratch = PMA_SHADOW_STATE_START + offsetof(shadow_state, mscratch), + mepc = PMA_SHADOW_STATE_START + offsetof(shadow_state, mepc), + mcause = PMA_SHADOW_STATE_START + offsetof(shadow_state, mcause), + mtval = PMA_SHADOW_STATE_START + offsetof(shadow_state, mtval), + misa = PMA_SHADOW_STATE_START + offsetof(shadow_state, misa), + mie = PMA_SHADOW_STATE_START + offsetof(shadow_state, mie), + mip = PMA_SHADOW_STATE_START + offsetof(shadow_state, mip), + medeleg = PMA_SHADOW_STATE_START + offsetof(shadow_state, medeleg), + mideleg = PMA_SHADOW_STATE_START + offsetof(shadow_state, mideleg), + mcounteren = PMA_SHADOW_STATE_START + offsetof(shadow_state, mcounteren), + menvcfg = PMA_SHADOW_STATE_START + offsetof(shadow_state, menvcfg), + stvec = PMA_SHADOW_STATE_START + offsetof(shadow_state, stvec), + sscratch = PMA_SHADOW_STATE_START + offsetof(shadow_state, sscratch), + sepc = PMA_SHADOW_STATE_START + offsetof(shadow_state, sepc), + scause = PMA_SHADOW_STATE_START + offsetof(shadow_state, scause), + stval = PMA_SHADOW_STATE_START + offsetof(shadow_state, stval), + satp = PMA_SHADOW_STATE_START + offsetof(shadow_state, satp), + scounteren = PMA_SHADOW_STATE_START + offsetof(shadow_state, scounteren), + senvcfg = PMA_SHADOW_STATE_START + offsetof(shadow_state, senvcfg), + ilrsc = PMA_SHADOW_STATE_START + offsetof(shadow_state, ilrsc), + iflags = PMA_SHADOW_STATE_START + offsetof(shadow_state, iflags), + iunrep = PMA_SHADOW_STATE_START + offsetof(shadow_state, iunrep), + clint_mtimecmp = PMA_SHADOW_STATE_START + offsetof(shadow_state, clint_mtimecmp), + plic_girqpend = PMA_SHADOW_STATE_START + offsetof(shadow_state, plic_girqpend), + plic_girqsrvd = PMA_SHADOW_STATE_START + offsetof(shadow_state, plic_girqsrvd), + htif_tohost = PMA_SHADOW_STATE_START + offsetof(shadow_state, htif_tohost), + htif_fromhost = PMA_SHADOW_STATE_START + offsetof(shadow_state, htif_fromhost), + htif_ihalt = PMA_SHADOW_STATE_START + offsetof(shadow_state, htif_ihalt), + htif_iconsole = PMA_SHADOW_STATE_START + offsetof(shadow_state, htif_iconsole), + htif_iyield = PMA_SHADOW_STATE_START + offsetof(shadow_state, htif_iyield), + first_ = x0, last_ = htif_iyield, - // Microarchitecture processor - uarch_first_, - uarch_x0 = uarch_first_, - uarch_x1, - uarch_x2, - uarch_x3, - uarch_x4, - uarch_x5, - uarch_x6, - uarch_x7, - uarch_x8, - uarch_x9, - uarch_x10, - uarch_x11, - uarch_x12, - uarch_x13, - uarch_x14, - uarch_x15, - uarch_x16, - uarch_x17, - uarch_x18, - uarch_x19, - uarch_x20, - uarch_x21, - uarch_x22, - uarch_x23, - uarch_x24, - uarch_x25, - uarch_x26, - uarch_x27, - uarch_x28, - uarch_x29, - uarch_x30, - uarch_x31, - uarch_pc, - uarch_cycle, - uarch_halt_flag, - uarch_last_ = uarch_halt_flag, - count_, + + uarch_halt_flag = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, halt_flag), + uarch_cycle = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, cycle), + uarch_pc = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, pc), + uarch_x0 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[0]), + uarch_x1 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[1]), + uarch_x2 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[2]), + uarch_x3 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[3]), + uarch_x4 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[4]), + uarch_x5 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[5]), + uarch_x6 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[6]), + uarch_x7 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[7]), + uarch_x8 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[8]), + uarch_x9 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[9]), + uarch_x10 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[10]), + uarch_x11 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[11]), + uarch_x12 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[12]), + uarch_x13 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[13]), + uarch_x14 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[14]), + uarch_x15 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[15]), + uarch_x16 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[16]), + uarch_x17 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[17]), + uarch_x18 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[18]), + uarch_x19 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[19]), + uarch_x20 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[20]), + uarch_x21 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[21]), + uarch_x22 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[22]), + uarch_x23 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[23]), + uarch_x24 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[24]), + uarch_x25 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[25]), + uarch_x26 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[26]), + uarch_x27 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[27]), + uarch_x28 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[28]), + uarch_x29 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[29]), + uarch_x30 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[30]), + uarch_x31 = PMA_SHADOW_UARCH_STATE_START + offsetof(shadow_uarch_state, x[31]), + uarch_first_ = uarch_halt_flag, + uarch_last_ = uarch_x31, + // Views of registers iflags_prv, iflags_x, @@ -187,6 +189,12 @@ enum class machine_reg { unknown_, }; +constexpr uint64_t machine_reg_address(machine_reg reg, int i = 0) { + return static_cast(reg) + i * sizeof(uint64_t); +} + +static_assert(machine_reg_address(machine_reg::uarch_first_) > machine_reg_address(machine_reg::last_)); + } // namespace cartesi #endif // MACHINE_REG_H diff --git a/src/machine.cpp b/src/machine.cpp index 7b2353fc..d3b2951c 100644 --- a/src/machine.cpp +++ b/src/machine.cpp @@ -305,14 +305,71 @@ machine::machine(const machine_config &c, const machine_runtime_config &r) : m_c m_s.soft_yield = r.soft_yield; // General purpose registers - for (int i = 1; i < X_REG_COUNT; i++) { - write_reg(static_cast(static_cast(reg::x0) + i), m_c.processor.x[i]); - } + write_reg(reg::x1, m_c.processor.x[1]); + write_reg(reg::x2, m_c.processor.x[2]); + write_reg(reg::x3, m_c.processor.x[3]); + write_reg(reg::x4, m_c.processor.x[4]); + write_reg(reg::x5, m_c.processor.x[5]); + write_reg(reg::x6, m_c.processor.x[6]); + write_reg(reg::x7, m_c.processor.x[7]); + write_reg(reg::x8, m_c.processor.x[8]); + write_reg(reg::x9, m_c.processor.x[9]); + write_reg(reg::x10, m_c.processor.x[10]); + write_reg(reg::x11, m_c.processor.x[11]); + write_reg(reg::x12, m_c.processor.x[12]); + write_reg(reg::x13, m_c.processor.x[13]); + write_reg(reg::x14, m_c.processor.x[14]); + write_reg(reg::x15, m_c.processor.x[15]); + write_reg(reg::x16, m_c.processor.x[16]); + write_reg(reg::x17, m_c.processor.x[17]); + write_reg(reg::x18, m_c.processor.x[18]); + write_reg(reg::x19, m_c.processor.x[19]); + write_reg(reg::x20, m_c.processor.x[20]); + write_reg(reg::x21, m_c.processor.x[21]); + write_reg(reg::x22, m_c.processor.x[22]); + write_reg(reg::x23, m_c.processor.x[23]); + write_reg(reg::x24, m_c.processor.x[24]); + write_reg(reg::x25, m_c.processor.x[25]); + write_reg(reg::x26, m_c.processor.x[26]); + write_reg(reg::x27, m_c.processor.x[27]); + write_reg(reg::x28, m_c.processor.x[28]); + write_reg(reg::x29, m_c.processor.x[29]); + write_reg(reg::x30, m_c.processor.x[30]); + write_reg(reg::x31, m_c.processor.x[31]); // Floating-point registers - for (int i = 0; i < F_REG_COUNT; i++) { - write_reg(static_cast(static_cast(reg::f0) + i), m_c.processor.f[i]); - } + write_reg(reg::f0, m_c.processor.f[0]); + write_reg(reg::f1, m_c.processor.f[1]); + write_reg(reg::f2, m_c.processor.f[2]); + write_reg(reg::f3, m_c.processor.f[3]); + write_reg(reg::f4, m_c.processor.f[4]); + write_reg(reg::f5, m_c.processor.f[5]); + write_reg(reg::f6, m_c.processor.f[6]); + write_reg(reg::f7, m_c.processor.f[7]); + write_reg(reg::f8, m_c.processor.f[8]); + write_reg(reg::f9, m_c.processor.f[9]); + write_reg(reg::f10, m_c.processor.f[10]); + write_reg(reg::f11, m_c.processor.f[11]); + write_reg(reg::f12, m_c.processor.f[12]); + write_reg(reg::f13, m_c.processor.f[13]); + write_reg(reg::f14, m_c.processor.f[14]); + write_reg(reg::f15, m_c.processor.f[15]); + write_reg(reg::f16, m_c.processor.f[16]); + write_reg(reg::f17, m_c.processor.f[17]); + write_reg(reg::f18, m_c.processor.f[18]); + write_reg(reg::f19, m_c.processor.f[19]); + write_reg(reg::f20, m_c.processor.f[20]); + write_reg(reg::f21, m_c.processor.f[21]); + write_reg(reg::f22, m_c.processor.f[22]); + write_reg(reg::f23, m_c.processor.f[23]); + write_reg(reg::f24, m_c.processor.f[24]); + write_reg(reg::f25, m_c.processor.f[25]); + write_reg(reg::f26, m_c.processor.f[26]); + write_reg(reg::f27, m_c.processor.f[27]); + write_reg(reg::f28, m_c.processor.f[28]); + write_reg(reg::f29, m_c.processor.f[29]); + write_reg(reg::f30, m_c.processor.f[30]); + write_reg(reg::f31, m_c.processor.f[31]); write_reg(reg::pc, m_c.processor.pc); write_reg(reg::fcsr, m_c.processor.fcsr); @@ -633,10 +690,10 @@ machine_config machine::get_serialization_config() const { machine_config c = m_c; // Copy current processor state to config for (int i = 1; i < X_REG_COUNT; ++i) { - c.processor.x[i] = read_reg(static_cast(static_cast(reg::x0) + i)); + c.processor.x[i] = m_s.x[i]; } for (int i = 0; i < F_REG_COUNT; ++i) { - c.processor.f[i] = read_reg(static_cast(static_cast(reg::f0) + i)); + c.processor.f[i] = m_s.f[i]; } c.processor.pc = read_reg(reg::pc); c.processor.fcsr = read_reg(reg::fcsr); @@ -699,7 +756,7 @@ machine_config machine::get_serialization_config() const { c.uarch.processor.halt_flag = (read_reg(reg::uarch_halt_flag) != 0); c.uarch.processor.pc = read_reg(reg::uarch_pc); for (int i = 1; i < UARCH_X_REG_COUNT; i++) { - c.uarch.processor.x[i] = read_reg(static_cast(static_cast(reg::uarch_x0) + i)); + c.uarch.processor.x[i] = m_uarch.get_state().x[i]; } return c; } @@ -1642,12 +1699,13 @@ void machine::write_reg(reg w, uint64_t value) { } uint64_t machine::get_reg_address(reg r) { - if (static_cast(r) >= static_cast(reg::uarch_first_) && - static_cast(r) <= static_cast(reg::uarch_last_)) { - return shadow_uarch_state_get_reg_abs_addr(r); + if (machine_reg_address(r) >= machine_reg_address(reg::uarch_first_) && + machine_reg_address(r) <= machine_reg_address(reg::uarch_last_)) { + return machine_reg_address(r); } - if (static_cast(r) >= static_cast(reg::first_) && static_cast(r) <= static_cast(reg::last_)) { - return shadow_state_get_reg_abs_addr(r); + if (machine_reg_address(r) >= machine_reg_address(reg::first_) && + machine_reg_address(r) <= machine_reg_address(reg::last_)) { + return machine_reg_address(r); } throw std::domain_error{"invalid register"}; } diff --git a/src/record-state-access.h b/src/record-state-access.h index 7dabf9a5..f7e7a480 100644 --- a/src/record-state-access.h +++ b/src/record-state-access.h @@ -202,7 +202,7 @@ class record_state_access : public i_state_access(m_m.get_state().iflags.X), 0 /* Y */, static_cast(m_m.get_state().iflags.H)); - const uint64_t iflags_addr = shadow_state_get_reg_abs_addr(machine_reg::iflags); + const uint64_t iflags_addr = machine_reg_address(machine_reg::iflags); log_read(iflags_addr, "iflags.Y"); log_before_write(iflags_addr, new_iflags, "iflags.Y"); m_m.get_state().iflags.Y = false; @@ -210,12 +210,12 @@ class record_state_access : public i_state_access(shadow_state_get_x_abs_addr(reg)); + return raw_read_memory(machine_reg_address(machine_reg::x0, reg)); } void do_write_x(int reg, uint64_t val) { - raw_write_memory(shadow_state_get_x_abs_addr(reg), val); + raw_write_memory(machine_reg_address(machine_reg::x0, reg), val); } uint64_t do_read_f(int reg) { - return raw_read_memory(shadow_state_get_f_abs_addr(reg)); + return raw_read_memory(machine_reg_address(machine_reg::f0, reg)); } void do_write_f(int reg, uint64_t val) { - raw_write_memory(shadow_state_get_f_abs_addr(reg), val); + raw_write_memory(machine_reg_address(machine_reg::f0, reg), val); } uint64_t do_read_pc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::pc)); + return raw_read_memory(machine_reg_address(machine_reg::pc)); } void do_write_pc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::pc), val); + raw_write_memory(machine_reg_address(machine_reg::pc), val); } uint64_t do_read_fcsr() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr)); + return raw_read_memory(machine_reg_address(machine_reg::fcsr)); } void do_write_fcsr(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr), val); + raw_write_memory(machine_reg_address(machine_reg::fcsr), val); } uint64_t do_read_icycleinstret() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret)); + return raw_read_memory(machine_reg_address(machine_reg::icycleinstret)); } void do_write_icycleinstret(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret), val); + raw_write_memory(machine_reg_address(machine_reg::icycleinstret), val); } uint64_t do_read_mvendorid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mvendorid)); + return raw_read_memory(machine_reg_address(machine_reg::mvendorid)); } uint64_t do_read_marchid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::marchid)); + return raw_read_memory(machine_reg_address(machine_reg::marchid)); } uint64_t do_read_mimpid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mimpid)); + return raw_read_memory(machine_reg_address(machine_reg::mimpid)); } uint64_t do_read_mcycle() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle)); + return raw_read_memory(machine_reg_address(machine_reg::mcycle)); } void do_write_mcycle(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle), val); + raw_write_memory(machine_reg_address(machine_reg::mcycle), val); } uint64_t do_read_mstatus() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus)); + return raw_read_memory(machine_reg_address(machine_reg::mstatus)); } void do_write_mstatus(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus), val); + raw_write_memory(machine_reg_address(machine_reg::mstatus), val); } uint64_t do_read_mtvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec)); + return raw_read_memory(machine_reg_address(machine_reg::mtvec)); } void do_write_mtvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec), val); + raw_write_memory(machine_reg_address(machine_reg::mtvec), val); } uint64_t do_read_mscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch)); + return raw_read_memory(machine_reg_address(machine_reg::mscratch)); } void do_write_mscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch), val); + raw_write_memory(machine_reg_address(machine_reg::mscratch), val); } uint64_t do_read_mepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc)); + return raw_read_memory(machine_reg_address(machine_reg::mepc)); } void do_write_mepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc), val); + raw_write_memory(machine_reg_address(machine_reg::mepc), val); } uint64_t do_read_mcause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause)); + return raw_read_memory(machine_reg_address(machine_reg::mcause)); } void do_write_mcause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause), val); + raw_write_memory(machine_reg_address(machine_reg::mcause), val); } uint64_t do_read_mtval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval)); + return raw_read_memory(machine_reg_address(machine_reg::mtval)); } void do_write_mtval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval), val); + raw_write_memory(machine_reg_address(machine_reg::mtval), val); } uint64_t do_read_misa() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::misa)); + return raw_read_memory(machine_reg_address(machine_reg::misa)); } void do_write_misa(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::misa), val); + raw_write_memory(machine_reg_address(machine_reg::misa), val); } uint64_t do_read_mie() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mie)); + return raw_read_memory(machine_reg_address(machine_reg::mie)); } void do_write_mie(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mie), val); + raw_write_memory(machine_reg_address(machine_reg::mie), val); } uint64_t do_read_mip() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mip)); + return raw_read_memory(machine_reg_address(machine_reg::mip)); } void do_write_mip(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mip), val); + raw_write_memory(machine_reg_address(machine_reg::mip), val); } uint64_t do_read_medeleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg)); + return raw_read_memory(machine_reg_address(machine_reg::medeleg)); } void do_write_medeleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg), val); + raw_write_memory(machine_reg_address(machine_reg::medeleg), val); } uint64_t do_read_mideleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg)); + return raw_read_memory(machine_reg_address(machine_reg::mideleg)); } void do_write_mideleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg), val); + raw_write_memory(machine_reg_address(machine_reg::mideleg), val); } uint64_t do_read_mcounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren)); + return raw_read_memory(machine_reg_address(machine_reg::mcounteren)); } void do_write_mcounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren), val); + raw_write_memory(machine_reg_address(machine_reg::mcounteren), val); } uint64_t do_read_senvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg)); + return raw_read_memory(machine_reg_address(machine_reg::senvcfg)); } void do_write_senvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg), val); + raw_write_memory(machine_reg_address(machine_reg::senvcfg), val); } uint64_t do_read_menvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg)); + return raw_read_memory(machine_reg_address(machine_reg::menvcfg)); } void do_write_menvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg), val); + raw_write_memory(machine_reg_address(machine_reg::menvcfg), val); } uint64_t do_read_stvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec)); + return raw_read_memory(machine_reg_address(machine_reg::stvec)); } void do_write_stvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec), val); + raw_write_memory(machine_reg_address(machine_reg::stvec), val); } uint64_t do_read_sscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch)); + return raw_read_memory(machine_reg_address(machine_reg::sscratch)); } void do_write_sscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch), val); + raw_write_memory(machine_reg_address(machine_reg::sscratch), val); } uint64_t do_read_sepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc)); + return raw_read_memory(machine_reg_address(machine_reg::sepc)); } void do_write_sepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc), val); + raw_write_memory(machine_reg_address(machine_reg::sepc), val); } uint64_t do_read_scause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scause)); + return raw_read_memory(machine_reg_address(machine_reg::scause)); } void do_write_scause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scause), val); + raw_write_memory(machine_reg_address(machine_reg::scause), val); } uint64_t do_read_stval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stval)); + return raw_read_memory(machine_reg_address(machine_reg::stval)); } void do_write_stval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stval), val); + raw_write_memory(machine_reg_address(machine_reg::stval), val); } uint64_t do_read_satp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::satp)); + return raw_read_memory(machine_reg_address(machine_reg::satp)); } void do_write_satp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::satp), val); + raw_write_memory(machine_reg_address(machine_reg::satp), val); } uint64_t do_read_scounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren)); + return raw_read_memory(machine_reg_address(machine_reg::scounteren)); } void do_write_scounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren), val); + raw_write_memory(machine_reg_address(machine_reg::scounteren), val); } uint64_t do_read_ilrsc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc)); + return raw_read_memory(machine_reg_address(machine_reg::ilrsc)); } void do_write_ilrsc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc), val); + raw_write_memory(machine_reg_address(machine_reg::ilrsc), val); } uint64_t do_read_iflags() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags)); + return raw_read_memory(machine_reg_address(machine_reg::iflags)); } void do_write_iflags(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags), val); + raw_write_memory(machine_reg_address(machine_reg::iflags), val); } void do_set_iflags_H() { @@ -788,63 +788,63 @@ class replay_step_state_access : public i_state_access(shadow_state_get_reg_abs_addr(machine_reg::iunrep)); + return raw_read_memory(machine_reg_address(machine_reg::iunrep)); } void do_write_iunrep(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iunrep), val); + raw_write_memory(machine_reg_address(machine_reg::iunrep), val); } uint64_t do_read_clint_mtimecmp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp)); + return raw_read_memory(machine_reg_address(machine_reg::clint_mtimecmp)); } void do_write_clint_mtimecmp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp), val); + raw_write_memory(machine_reg_address(machine_reg::clint_mtimecmp), val); } uint64_t do_read_plic_girqpend() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend)); + return raw_read_memory(machine_reg_address(machine_reg::plic_girqpend)); } void do_write_plic_girqpend(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend), val); + raw_write_memory(machine_reg_address(machine_reg::plic_girqpend), val); } uint64_t do_read_plic_girqsrvd() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd)); + return raw_read_memory(machine_reg_address(machine_reg::plic_girqsrvd)); } void do_write_plic_girqsrvd(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd), val); + raw_write_memory(machine_reg_address(machine_reg::plic_girqsrvd), val); } uint64_t do_read_htif_fromhost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost)); + return raw_read_memory(machine_reg_address(machine_reg::htif_fromhost)); } void do_write_htif_fromhost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost), val); + raw_write_memory(machine_reg_address(machine_reg::htif_fromhost), val); } uint64_t do_read_htif_tohost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost)); + return raw_read_memory(machine_reg_address(machine_reg::htif_tohost)); } void do_write_htif_tohost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost), val); + raw_write_memory(machine_reg_address(machine_reg::htif_tohost), val); } uint64_t do_read_htif_ihalt() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_ihalt)); + return raw_read_memory(machine_reg_address(machine_reg::htif_ihalt)); } uint64_t do_read_htif_iconsole() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iconsole)); + return raw_read_memory(machine_reg_address(machine_reg::htif_iconsole)); } uint64_t do_read_htif_iyield() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iyield)); + return raw_read_memory(machine_reg_address(machine_reg::htif_iyield)); } // NOLINTNEXTLINE(readability-convert-member-functions-to-static) diff --git a/src/shadow-state-factory.cpp b/src/shadow-state-factory.cpp index 2eaa53fa..64dce91d 100644 --- a/src/shadow-state-factory.cpp +++ b/src/shadow-state-factory.cpp @@ -45,13 +45,73 @@ static bool shadow_state_peek(const pma_entry & /*pma*/, const machine &m, uint6 auto *s = reinterpret_cast(scratch); // Copy general-purpose registers - for (int i = 0; i < X_REG_COUNT; ++i) { - s->x[i] = m.read_reg(static_cast(static_cast(machine_reg::x0) + i)); - } + s->x[0] = m.read_reg(machine_reg::x0); + s->x[1] = m.read_reg(machine_reg::x1); + s->x[2] = m.read_reg(machine_reg::x2); + s->x[3] = m.read_reg(machine_reg::x3); + s->x[4] = m.read_reg(machine_reg::x4); + s->x[5] = m.read_reg(machine_reg::x5); + s->x[6] = m.read_reg(machine_reg::x6); + s->x[7] = m.read_reg(machine_reg::x7); + s->x[8] = m.read_reg(machine_reg::x8); + s->x[9] = m.read_reg(machine_reg::x9); + s->x[10] = m.read_reg(machine_reg::x10); + s->x[11] = m.read_reg(machine_reg::x11); + s->x[12] = m.read_reg(machine_reg::x12); + s->x[13] = m.read_reg(machine_reg::x13); + s->x[14] = m.read_reg(machine_reg::x14); + s->x[15] = m.read_reg(machine_reg::x15); + s->x[16] = m.read_reg(machine_reg::x16); + s->x[17] = m.read_reg(machine_reg::x17); + s->x[18] = m.read_reg(machine_reg::x18); + s->x[19] = m.read_reg(machine_reg::x19); + s->x[20] = m.read_reg(machine_reg::x20); + s->x[21] = m.read_reg(machine_reg::x21); + s->x[22] = m.read_reg(machine_reg::x22); + s->x[23] = m.read_reg(machine_reg::x23); + s->x[24] = m.read_reg(machine_reg::x24); + s->x[25] = m.read_reg(machine_reg::x25); + s->x[26] = m.read_reg(machine_reg::x26); + s->x[27] = m.read_reg(machine_reg::x27); + s->x[28] = m.read_reg(machine_reg::x28); + s->x[29] = m.read_reg(machine_reg::x29); + s->x[30] = m.read_reg(machine_reg::x30); + s->x[31] = m.read_reg(machine_reg::x31); + // Copy floating-point registers - for (int i = 0; i < F_REG_COUNT; ++i) { - s->f[i] = m.read_reg(static_cast(static_cast(machine_reg::f0) + i)); - } + s->f[0] = m.read_reg(machine_reg::f0); + s->f[1] = m.read_reg(machine_reg::f1); + s->f[2] = m.read_reg(machine_reg::f2); + s->f[3] = m.read_reg(machine_reg::f3); + s->f[4] = m.read_reg(machine_reg::f4); + s->f[5] = m.read_reg(machine_reg::f5); + s->f[6] = m.read_reg(machine_reg::f6); + s->f[7] = m.read_reg(machine_reg::f7); + s->f[8] = m.read_reg(machine_reg::f8); + s->f[9] = m.read_reg(machine_reg::f9); + s->f[10] = m.read_reg(machine_reg::f10); + s->f[11] = m.read_reg(machine_reg::f11); + s->f[12] = m.read_reg(machine_reg::f12); + s->f[13] = m.read_reg(machine_reg::f13); + s->f[14] = m.read_reg(machine_reg::f14); + s->f[15] = m.read_reg(machine_reg::f15); + s->f[16] = m.read_reg(machine_reg::f16); + s->f[17] = m.read_reg(machine_reg::f17); + s->f[18] = m.read_reg(machine_reg::f18); + s->f[19] = m.read_reg(machine_reg::f19); + s->f[20] = m.read_reg(machine_reg::f20); + s->f[21] = m.read_reg(machine_reg::f21); + s->f[22] = m.read_reg(machine_reg::f22); + s->f[23] = m.read_reg(machine_reg::f23); + s->f[24] = m.read_reg(machine_reg::f24); + s->f[25] = m.read_reg(machine_reg::f25); + s->f[26] = m.read_reg(machine_reg::f26); + s->f[27] = m.read_reg(machine_reg::f27); + s->f[28] = m.read_reg(machine_reg::f28); + s->f[29] = m.read_reg(machine_reg::f29); + s->f[30] = m.read_reg(machine_reg::f30); + s->f[31] = m.read_reg(machine_reg::f31); + // Copy named registers s->pc = m.read_reg(machine_reg::pc); s->fcsr = m.read_reg(machine_reg::fcsr); diff --git a/src/shadow-state.h b/src/shadow-state.h index ad9396d1..30abf2f3 100644 --- a/src/shadow-state.h +++ b/src/shadow-state.h @@ -22,8 +22,6 @@ #include #include "compiler-defines.h" -#include "machine-reg.h" -#include "pma-constants.h" #include "pma-driver.h" #include "riscv-constants.h" @@ -80,363 +78,6 @@ struct PACKED shadow_state { /// \brief Global instance of the processor shadow device driver. extern const pma_driver shadow_state_driver; -/// \brief Mapping between registers and their relative addresses in shadow memory -enum class shadow_state_reg_rel_addr : uint64_t { - x0 = offsetof(shadow_state, x[0]), - x1 = offsetof(shadow_state, x[1]), - x2 = offsetof(shadow_state, x[2]), - x3 = offsetof(shadow_state, x[3]), - x4 = offsetof(shadow_state, x[4]), - x5 = offsetof(shadow_state, x[5]), - x6 = offsetof(shadow_state, x[6]), - x7 = offsetof(shadow_state, x[7]), - x8 = offsetof(shadow_state, x[8]), - x9 = offsetof(shadow_state, x[9]), - x10 = offsetof(shadow_state, x[10]), - x11 = offsetof(shadow_state, x[11]), - x12 = offsetof(shadow_state, x[12]), - x13 = offsetof(shadow_state, x[13]), - x14 = offsetof(shadow_state, x[14]), - x15 = offsetof(shadow_state, x[15]), - x16 = offsetof(shadow_state, x[16]), - x17 = offsetof(shadow_state, x[17]), - x18 = offsetof(shadow_state, x[18]), - x19 = offsetof(shadow_state, x[19]), - x20 = offsetof(shadow_state, x[20]), - x21 = offsetof(shadow_state, x[21]), - x22 = offsetof(shadow_state, x[22]), - x23 = offsetof(shadow_state, x[23]), - x24 = offsetof(shadow_state, x[24]), - x25 = offsetof(shadow_state, x[25]), - x26 = offsetof(shadow_state, x[26]), - x27 = offsetof(shadow_state, x[27]), - x28 = offsetof(shadow_state, x[28]), - x29 = offsetof(shadow_state, x[29]), - x30 = offsetof(shadow_state, x[30]), - x31 = offsetof(shadow_state, x[31]), - f0 = offsetof(shadow_state, f[0]), - f1 = offsetof(shadow_state, f[1]), - f2 = offsetof(shadow_state, f[2]), - f3 = offsetof(shadow_state, f[3]), - f4 = offsetof(shadow_state, f[4]), - f5 = offsetof(shadow_state, f[5]), - f6 = offsetof(shadow_state, f[6]), - f7 = offsetof(shadow_state, f[7]), - f8 = offsetof(shadow_state, f[8]), - f9 = offsetof(shadow_state, f[9]), - f10 = offsetof(shadow_state, f[10]), - f11 = offsetof(shadow_state, f[11]), - f12 = offsetof(shadow_state, f[12]), - f13 = offsetof(shadow_state, f[13]), - f14 = offsetof(shadow_state, f[14]), - f15 = offsetof(shadow_state, f[15]), - f16 = offsetof(shadow_state, f[16]), - f17 = offsetof(shadow_state, f[17]), - f18 = offsetof(shadow_state, f[18]), - f19 = offsetof(shadow_state, f[19]), - f20 = offsetof(shadow_state, f[20]), - f21 = offsetof(shadow_state, f[21]), - f22 = offsetof(shadow_state, f[22]), - f23 = offsetof(shadow_state, f[23]), - f24 = offsetof(shadow_state, f[24]), - f25 = offsetof(shadow_state, f[25]), - f26 = offsetof(shadow_state, f[26]), - f27 = offsetof(shadow_state, f[27]), - f28 = offsetof(shadow_state, f[28]), - f29 = offsetof(shadow_state, f[29]), - f30 = offsetof(shadow_state, f[30]), - f31 = offsetof(shadow_state, f[31]), - pc = offsetof(shadow_state, pc), - fcsr = offsetof(shadow_state, fcsr), - mvendorid = offsetof(shadow_state, mvendorid), - marchid = offsetof(shadow_state, marchid), - mimpid = offsetof(shadow_state, mimpid), - mcycle = offsetof(shadow_state, mcycle), - icycleinstret = offsetof(shadow_state, icycleinstret), - mstatus = offsetof(shadow_state, mstatus), - mtvec = offsetof(shadow_state, mtvec), - mscratch = offsetof(shadow_state, mscratch), - mepc = offsetof(shadow_state, mepc), - mcause = offsetof(shadow_state, mcause), - mtval = offsetof(shadow_state, mtval), - misa = offsetof(shadow_state, misa), - mie = offsetof(shadow_state, mie), - mip = offsetof(shadow_state, mip), - medeleg = offsetof(shadow_state, medeleg), - mideleg = offsetof(shadow_state, mideleg), - mcounteren = offsetof(shadow_state, mcounteren), - menvcfg = offsetof(shadow_state, menvcfg), - stvec = offsetof(shadow_state, stvec), - sscratch = offsetof(shadow_state, sscratch), - sepc = offsetof(shadow_state, sepc), - scause = offsetof(shadow_state, scause), - stval = offsetof(shadow_state, stval), - satp = offsetof(shadow_state, satp), - scounteren = offsetof(shadow_state, scounteren), - senvcfg = offsetof(shadow_state, senvcfg), - ilrsc = offsetof(shadow_state, ilrsc), - iflags = offsetof(shadow_state, iflags), - iunrep = offsetof(shadow_state, iunrep), - clint_mtimecmp = offsetof(shadow_state, clint_mtimecmp), - plic_girqpend = offsetof(shadow_state, plic_girqpend), - plic_girqsrvd = offsetof(shadow_state, plic_girqsrvd), - htif_tohost = offsetof(shadow_state, htif_tohost), - htif_fromhost = offsetof(shadow_state, htif_fromhost), - htif_ihalt = offsetof(shadow_state, htif_ihalt), - htif_iconsole = offsetof(shadow_state, htif_iconsole), - htif_iyield = offsetof(shadow_state, htif_iyield), -}; - -/// \brief Obtains the relative address of a general purpose register -/// in shadow memory. -/// \param reg Register index in 0...31, for x0...x31, respectively. -/// \returns The address. -static inline uint64_t shadow_state_get_x_rel_addr(int reg) { - assert(reg >= 0 && reg < X_REG_COUNT); - return offsetof(shadow_state, x) + reg * sizeof(uint64_t); -} - -/// \brief Obtains the relative address of a floating-point register -static inline uint64_t shadow_state_get_f_rel_addr(int reg) { - assert(reg >= 0 && reg < F_REG_COUNT); - return offsetof(shadow_state, f) + reg * sizeof(uint64_t); -} - -/// \brief Obtains the relative address of a register in shadow memory. -/// \param r Register name. -/// \returns The address. -static inline uint64_t shadow_state_get_reg_rel_addr(machine_reg r) { - using reg = machine_reg; - switch (r) { - case reg::x0: - return static_cast(shadow_state_reg_rel_addr::x0); - case reg::x1: - return static_cast(shadow_state_reg_rel_addr::x1); - case reg::x2: - return static_cast(shadow_state_reg_rel_addr::x2); - case reg::x3: - return static_cast(shadow_state_reg_rel_addr::x3); - case reg::x4: - return static_cast(shadow_state_reg_rel_addr::x4); - case reg::x5: - return static_cast(shadow_state_reg_rel_addr::x5); - case reg::x6: - return static_cast(shadow_state_reg_rel_addr::x6); - case reg::x7: - return static_cast(shadow_state_reg_rel_addr::x7); - case reg::x8: - return static_cast(shadow_state_reg_rel_addr::x8); - case reg::x9: - return static_cast(shadow_state_reg_rel_addr::x9); - case reg::x10: - return static_cast(shadow_state_reg_rel_addr::x10); - case reg::x11: - return static_cast(shadow_state_reg_rel_addr::x11); - case reg::x12: - return static_cast(shadow_state_reg_rel_addr::x12); - case reg::x13: - return static_cast(shadow_state_reg_rel_addr::x13); - case reg::x14: - return static_cast(shadow_state_reg_rel_addr::x14); - case reg::x15: - return static_cast(shadow_state_reg_rel_addr::x15); - case reg::x16: - return static_cast(shadow_state_reg_rel_addr::x16); - case reg::x17: - return static_cast(shadow_state_reg_rel_addr::x17); - case reg::x18: - return static_cast(shadow_state_reg_rel_addr::x18); - case reg::x19: - return static_cast(shadow_state_reg_rel_addr::x19); - case reg::x20: - return static_cast(shadow_state_reg_rel_addr::x20); - case reg::x21: - return static_cast(shadow_state_reg_rel_addr::x21); - case reg::x22: - return static_cast(shadow_state_reg_rel_addr::x22); - case reg::x23: - return static_cast(shadow_state_reg_rel_addr::x23); - case reg::x24: - return static_cast(shadow_state_reg_rel_addr::x24); - case reg::x25: - return static_cast(shadow_state_reg_rel_addr::x25); - case reg::x26: - return static_cast(shadow_state_reg_rel_addr::x26); - case reg::x27: - return static_cast(shadow_state_reg_rel_addr::x27); - case reg::x28: - return static_cast(shadow_state_reg_rel_addr::x28); - case reg::x29: - return static_cast(shadow_state_reg_rel_addr::x29); - case reg::x30: - return static_cast(shadow_state_reg_rel_addr::x30); - case reg::x31: - return static_cast(shadow_state_reg_rel_addr::x31); - case reg::f0: - return static_cast(shadow_state_reg_rel_addr::f0); - case reg::f1: - return static_cast(shadow_state_reg_rel_addr::f1); - case reg::f2: - return static_cast(shadow_state_reg_rel_addr::f2); - case reg::f3: - return static_cast(shadow_state_reg_rel_addr::f3); - case reg::f4: - return static_cast(shadow_state_reg_rel_addr::f4); - case reg::f5: - return static_cast(shadow_state_reg_rel_addr::f5); - case reg::f6: - return static_cast(shadow_state_reg_rel_addr::f6); - case reg::f7: - return static_cast(shadow_state_reg_rel_addr::f7); - case reg::f8: - return static_cast(shadow_state_reg_rel_addr::f8); - case reg::f9: - return static_cast(shadow_state_reg_rel_addr::f9); - case reg::f10: - return static_cast(shadow_state_reg_rel_addr::f10); - case reg::f11: - return static_cast(shadow_state_reg_rel_addr::f11); - case reg::f12: - return static_cast(shadow_state_reg_rel_addr::f12); - case reg::f13: - return static_cast(shadow_state_reg_rel_addr::f13); - case reg::f14: - return static_cast(shadow_state_reg_rel_addr::f14); - case reg::f15: - return static_cast(shadow_state_reg_rel_addr::f15); - case reg::f16: - return static_cast(shadow_state_reg_rel_addr::f16); - case reg::f17: - return static_cast(shadow_state_reg_rel_addr::f17); - case reg::f18: - return static_cast(shadow_state_reg_rel_addr::f18); - case reg::f19: - return static_cast(shadow_state_reg_rel_addr::f19); - case reg::f20: - return static_cast(shadow_state_reg_rel_addr::f20); - case reg::f21: - return static_cast(shadow_state_reg_rel_addr::f21); - case reg::f22: - return static_cast(shadow_state_reg_rel_addr::f22); - case reg::f23: - return static_cast(shadow_state_reg_rel_addr::f23); - case reg::f24: - return static_cast(shadow_state_reg_rel_addr::f24); - case reg::f25: - return static_cast(shadow_state_reg_rel_addr::f25); - case reg::f26: - return static_cast(shadow_state_reg_rel_addr::f26); - case reg::f27: - return static_cast(shadow_state_reg_rel_addr::f27); - case reg::f28: - return static_cast(shadow_state_reg_rel_addr::f28); - case reg::f29: - return static_cast(shadow_state_reg_rel_addr::f29); - case reg::f30: - return static_cast(shadow_state_reg_rel_addr::f30); - case reg::f31: - return static_cast(shadow_state_reg_rel_addr::f31); - case reg::pc: - return static_cast(shadow_state_reg_rel_addr::pc); - case reg::fcsr: - return static_cast(shadow_state_reg_rel_addr::fcsr); - case reg::mvendorid: - return static_cast(shadow_state_reg_rel_addr::mvendorid); - case reg::marchid: - return static_cast(shadow_state_reg_rel_addr::marchid); - case reg::mimpid: - return static_cast(shadow_state_reg_rel_addr::mimpid); - case reg::mcycle: - return static_cast(shadow_state_reg_rel_addr::mcycle); - case reg::icycleinstret: - return static_cast(shadow_state_reg_rel_addr::icycleinstret); - case reg::mstatus: - return static_cast(shadow_state_reg_rel_addr::mstatus); - case reg::mtvec: - return static_cast(shadow_state_reg_rel_addr::mtvec); - case reg::mscratch: - return static_cast(shadow_state_reg_rel_addr::mscratch); - case reg::mepc: - return static_cast(shadow_state_reg_rel_addr::mepc); - case reg::mcause: - return static_cast(shadow_state_reg_rel_addr::mcause); - case reg::mtval: - return static_cast(shadow_state_reg_rel_addr::mtval); - case reg::misa: - return static_cast(shadow_state_reg_rel_addr::misa); - case reg::mie: - return static_cast(shadow_state_reg_rel_addr::mie); - case reg::mip: - return static_cast(shadow_state_reg_rel_addr::mip); - case reg::medeleg: - return static_cast(shadow_state_reg_rel_addr::medeleg); - case reg::mideleg: - return static_cast(shadow_state_reg_rel_addr::mideleg); - case reg::mcounteren: - return static_cast(shadow_state_reg_rel_addr::mcounteren); - case reg::menvcfg: - return static_cast(shadow_state_reg_rel_addr::menvcfg); - case reg::stvec: - return static_cast(shadow_state_reg_rel_addr::stvec); - case reg::sscratch: - return static_cast(shadow_state_reg_rel_addr::sscratch); - case reg::sepc: - return static_cast(shadow_state_reg_rel_addr::sepc); - case reg::scause: - return static_cast(shadow_state_reg_rel_addr::scause); - case reg::stval: - return static_cast(shadow_state_reg_rel_addr::stval); - case reg::satp: - return static_cast(shadow_state_reg_rel_addr::satp); - case reg::scounteren: - return static_cast(shadow_state_reg_rel_addr::scounteren); - case reg::senvcfg: - return static_cast(shadow_state_reg_rel_addr::senvcfg); - case reg::ilrsc: - return static_cast(shadow_state_reg_rel_addr::ilrsc); - case reg::iflags: - return static_cast(shadow_state_reg_rel_addr::iflags); - case reg::iunrep: - return static_cast(shadow_state_reg_rel_addr::iunrep); - case reg::clint_mtimecmp: - return static_cast(shadow_state_reg_rel_addr::clint_mtimecmp); - case reg::plic_girqpend: - return static_cast(shadow_state_reg_rel_addr::plic_girqpend); - case reg::plic_girqsrvd: - return static_cast(shadow_state_reg_rel_addr::plic_girqsrvd); - case reg::htif_tohost: - return static_cast(shadow_state_reg_rel_addr::htif_tohost); - case reg::htif_fromhost: - return static_cast(shadow_state_reg_rel_addr::htif_fromhost); - case reg::htif_ihalt: - return static_cast(shadow_state_reg_rel_addr::htif_ihalt); - case reg::htif_iconsole: - return static_cast(shadow_state_reg_rel_addr::htif_iconsole); - case reg::htif_iyield: - return static_cast(shadow_state_reg_rel_addr::htif_iyield); - default: - assert(0); - return 0; - } -} - -/// \brief Obtains the absolute address of a register in shadow memory. -/// \param r Register name. -/// \returns The address. -static inline uint64_t shadow_state_get_reg_abs_addr(machine_reg r) { - return PMA_SHADOW_STATE_START + shadow_state_get_reg_rel_addr(r); -} - -/// \brief Obtains the absolute address of a general purpose register -static inline uint64_t shadow_state_get_x_abs_addr(int reg) { - return PMA_SHADOW_STATE_START + shadow_state_get_x_rel_addr(reg); -} - -/// \brief Obtains the absolute address of a floating-point register -static inline uint64_t shadow_state_get_f_abs_addr(int reg) { - return PMA_SHADOW_STATE_START + shadow_state_get_f_rel_addr(reg); -} - } // namespace cartesi #endif diff --git a/src/shadow-uarch-state-factory.cpp b/src/shadow-uarch-state-factory.cpp index 00ec433f..519a3602 100644 --- a/src/shadow-uarch-state-factory.cpp +++ b/src/shadow-uarch-state-factory.cpp @@ -47,9 +47,38 @@ static bool shadow_uarch_state_peek(const pma_entry & /*pma*/, const machine &m, s->halt_flag = m.read_reg(machine_reg::uarch_halt_flag); s->cycle = m.read_reg(machine_reg::uarch_cycle); s->pc = m.read_reg(machine_reg::uarch_pc); - for (int i = 0; i < UARCH_X_REG_COUNT; ++i) { - s->x[i] = m.read_reg(static_cast(static_cast(machine_reg::uarch_x0) + i)); - } + s->x[0] = m.read_reg(machine_reg::uarch_x0); + s->x[1] = m.read_reg(machine_reg::uarch_x1); + s->x[2] = m.read_reg(machine_reg::uarch_x2); + s->x[3] = m.read_reg(machine_reg::uarch_x3); + s->x[4] = m.read_reg(machine_reg::uarch_x4); + s->x[5] = m.read_reg(machine_reg::uarch_x5); + s->x[6] = m.read_reg(machine_reg::uarch_x6); + s->x[7] = m.read_reg(machine_reg::uarch_x7); + s->x[8] = m.read_reg(machine_reg::uarch_x8); + s->x[9] = m.read_reg(machine_reg::uarch_x9); + s->x[10] = m.read_reg(machine_reg::uarch_x10); + s->x[11] = m.read_reg(machine_reg::uarch_x11); + s->x[12] = m.read_reg(machine_reg::uarch_x12); + s->x[13] = m.read_reg(machine_reg::uarch_x13); + s->x[14] = m.read_reg(machine_reg::uarch_x14); + s->x[15] = m.read_reg(machine_reg::uarch_x15); + s->x[16] = m.read_reg(machine_reg::uarch_x16); + s->x[17] = m.read_reg(machine_reg::uarch_x17); + s->x[18] = m.read_reg(machine_reg::uarch_x18); + s->x[19] = m.read_reg(machine_reg::uarch_x19); + s->x[20] = m.read_reg(machine_reg::uarch_x20); + s->x[21] = m.read_reg(machine_reg::uarch_x21); + s->x[22] = m.read_reg(machine_reg::uarch_x22); + s->x[23] = m.read_reg(machine_reg::uarch_x23); + s->x[24] = m.read_reg(machine_reg::uarch_x24); + s->x[25] = m.read_reg(machine_reg::uarch_x25); + s->x[26] = m.read_reg(machine_reg::uarch_x26); + s->x[27] = m.read_reg(machine_reg::uarch_x27); + s->x[28] = m.read_reg(machine_reg::uarch_x28); + s->x[29] = m.read_reg(machine_reg::uarch_x29); + s->x[30] = m.read_reg(machine_reg::uarch_x30); + s->x[31] = m.read_reg(machine_reg::uarch_x31); *page_data = scratch; return true; } diff --git a/src/shadow-uarch-state.h b/src/shadow-uarch-state.h index efc0c7e5..36c7ea34 100644 --- a/src/shadow-uarch-state.h +++ b/src/shadow-uarch-state.h @@ -22,8 +22,6 @@ #include #include "compiler-defines.h" -#include "machine-reg.h" -#include "pma-constants.h" #include "pma-driver.h" #include "riscv-constants.h" @@ -43,146 +41,6 @@ struct PACKED shadow_uarch_state { /// \brief Global instance of theprocessor shadow uarch state device driver. extern const pma_driver shadow_uarch_state_driver; -/// \brief Mapping between registers and their relative addresses in shadow uarch state memory -enum class shadow_uarch_state_reg_rel_addr : uint64_t { - uarch_halt_flag = offsetof(shadow_uarch_state, halt_flag), - uarch_cycle = offsetof(shadow_uarch_state, cycle), - uarch_pc = offsetof(shadow_uarch_state, pc), - uarch_x0 = offsetof(shadow_uarch_state, x[0]), - uarch_x1 = offsetof(shadow_uarch_state, x[1]), - uarch_x2 = offsetof(shadow_uarch_state, x[2]), - uarch_x3 = offsetof(shadow_uarch_state, x[3]), - uarch_x4 = offsetof(shadow_uarch_state, x[4]), - uarch_x5 = offsetof(shadow_uarch_state, x[5]), - uarch_x6 = offsetof(shadow_uarch_state, x[6]), - uarch_x7 = offsetof(shadow_uarch_state, x[7]), - uarch_x8 = offsetof(shadow_uarch_state, x[8]), - uarch_x9 = offsetof(shadow_uarch_state, x[9]), - uarch_x10 = offsetof(shadow_uarch_state, x[10]), - uarch_x11 = offsetof(shadow_uarch_state, x[11]), - uarch_x12 = offsetof(shadow_uarch_state, x[12]), - uarch_x13 = offsetof(shadow_uarch_state, x[13]), - uarch_x14 = offsetof(shadow_uarch_state, x[14]), - uarch_x15 = offsetof(shadow_uarch_state, x[15]), - uarch_x16 = offsetof(shadow_uarch_state, x[16]), - uarch_x17 = offsetof(shadow_uarch_state, x[17]), - uarch_x18 = offsetof(shadow_uarch_state, x[18]), - uarch_x19 = offsetof(shadow_uarch_state, x[19]), - uarch_x20 = offsetof(shadow_uarch_state, x[20]), - uarch_x21 = offsetof(shadow_uarch_state, x[21]), - uarch_x22 = offsetof(shadow_uarch_state, x[22]), - uarch_x23 = offsetof(shadow_uarch_state, x[23]), - uarch_x24 = offsetof(shadow_uarch_state, x[24]), - uarch_x25 = offsetof(shadow_uarch_state, x[25]), - uarch_x26 = offsetof(shadow_uarch_state, x[26]), - uarch_x27 = offsetof(shadow_uarch_state, x[27]), - uarch_x28 = offsetof(shadow_uarch_state, x[28]), - uarch_x29 = offsetof(shadow_uarch_state, x[29]), - uarch_x30 = offsetof(shadow_uarch_state, x[30]), - uarch_x31 = offsetof(shadow_uarch_state, x[31]), -}; - -/// \brief Obtains the relative address of a register in shadow uarch state memory. -/// \param r Register name. -/// \returns The address. -static inline uint64_t shadow_uarch_state_get_reg_rel_addr(machine_reg r) { - using reg = machine_reg; - switch (r) { - case reg::uarch_halt_flag: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_halt_flag); - case reg::uarch_cycle: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_cycle); - case reg::uarch_pc: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_pc); - case reg::uarch_x0: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x0); - case reg::uarch_x1: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x1); - case reg::uarch_x2: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x2); - case reg::uarch_x3: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x3); - case reg::uarch_x4: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x4); - case reg::uarch_x5: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x5); - case reg::uarch_x6: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x6); - case reg::uarch_x7: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x7); - case reg::uarch_x8: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x8); - case reg::uarch_x9: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x9); - case reg::uarch_x10: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x10); - case reg::uarch_x11: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x11); - case reg::uarch_x12: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x12); - case reg::uarch_x13: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x13); - case reg::uarch_x14: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x14); - case reg::uarch_x15: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x15); - case reg::uarch_x16: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x16); - case reg::uarch_x17: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x17); - case reg::uarch_x18: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x18); - case reg::uarch_x19: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x19); - case reg::uarch_x20: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x20); - case reg::uarch_x21: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x21); - case reg::uarch_x22: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x22); - case reg::uarch_x23: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x23); - case reg::uarch_x24: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x24); - case reg::uarch_x25: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x25); - case reg::uarch_x26: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x26); - case reg::uarch_x27: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x27); - case reg::uarch_x28: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x28); - case reg::uarch_x29: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x29); - case reg::uarch_x30: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x30); - case reg::uarch_x31: - return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x31); - default: - assert(0); - return 0; - } -} - -/// \brief Obtains the absolute address of a register in shadow uarch state memory. -/// \param reg Register name. -static inline uint64_t shadow_uarch_state_get_reg_abs_addr(machine_reg reg) { - return PMA_SHADOW_UARCH_STATE_START + shadow_uarch_state_get_reg_rel_addr(reg); -} - -/// \brief Obtains the relative address of a microarchitecture general purpose register in shadow uarch state memory -/// \param reg Register index in 0...31, for x0...x31, respectively. -static inline uint64_t shadow_uarch_state_get_x_rel_addr(int reg) { - assert(reg >= 0 && reg < UARCH_X_REG_COUNT); - return offsetof(shadow_uarch_state, x) + reg * sizeof(uint64_t); -} - -/// \brief Obtains the absolute address of a microarchitecture general purpose register in shadow uarch state memory -/// \param reg Register index in 0...31, for x0...x31, respectively. -static inline uint64_t shadow_uarch_state_get_x_abs_addr(int reg) { - return PMA_SHADOW_UARCH_STATE_START + shadow_uarch_state_get_x_rel_addr(reg); -} - } // namespace cartesi #endif diff --git a/src/uarch-bridge.h b/src/uarch-bridge.h index 0f516fde..b4862fe4 100644 --- a/src/uarch-bridge.h +++ b/src/uarch-bridge.h @@ -23,6 +23,7 @@ #include #include +#include "machine-reg.h" #include "machine-state.h" #include "pma-constants.h" #include "riscv-constants.h" @@ -43,301 +44,298 @@ class uarch_bridge { /// An exception is thrown if paddr can't me mapped to a valid state register. //// \} static void write_register(uint64_t paddr, machine_state &s, uint64_t data) { - if (paddr >= PMA_SHADOW_STATE_START) { - using reg = shadow_state_reg_rel_addr; - paddr -= PMA_SHADOW_STATE_START; - switch (static_cast(paddr)) { - case reg::x0: - s.x[0] = data; - return; - case reg::x1: - s.x[1] = data; - return; - case reg::x2: - s.x[2] = data; - return; - case reg::x3: - s.x[3] = data; - return; - case reg::x4: - s.x[4] = data; - return; - case reg::x5: - s.x[5] = data; - return; - case reg::x6: - s.x[6] = data; - return; - case reg::x7: - s.x[7] = data; - return; - case reg::x8: - s.x[8] = data; - return; - case reg::x9: - s.x[9] = data; - return; - case reg::x10: - s.x[10] = data; - return; - case reg::x11: - s.x[11] = data; - return; - case reg::x12: - s.x[12] = data; - return; - case reg::x13: - s.x[13] = data; - return; - case reg::x14: - s.x[14] = data; - return; - case reg::x15: - s.x[15] = data; - return; - case reg::x16: - s.x[16] = data; - return; - case reg::x17: - s.x[17] = data; - return; - case reg::x18: - s.x[18] = data; - return; - case reg::x19: - s.x[19] = data; - return; - case reg::x20: - s.x[20] = data; - return; - case reg::x21: - s.x[21] = data; - return; - case reg::x22: - s.x[22] = data; - return; - case reg::x23: - s.x[23] = data; - return; - case reg::x24: - s.x[24] = data; - return; - case reg::x25: - s.x[25] = data; - return; - case reg::x26: - s.x[26] = data; - return; - case reg::x27: - s.x[27] = data; - return; - case reg::x28: - s.x[28] = data; - return; - case reg::x29: - s.x[29] = data; - return; - case reg::x30: - s.x[30] = data; - return; - case reg::x31: - s.x[31] = data; - return; - case reg::f0: - s.f[0] = data; - return; - case reg::f1: - s.f[1] = data; - return; - case reg::f2: - s.f[2] = data; - return; - case reg::f3: - s.f[3] = data; - return; - case reg::f4: - s.f[4] = data; - return; - case reg::f5: - s.f[5] = data; - return; - case reg::f6: - s.f[6] = data; - return; - case reg::f7: - s.f[7] = data; - return; - case reg::f8: - s.f[8] = data; - return; - case reg::f9: - s.f[9] = data; - return; - case reg::f10: - s.f[10] = data; - return; - case reg::f11: - s.f[11] = data; - return; - case reg::f12: - s.f[12] = data; - return; - case reg::f13: - s.f[13] = data; - return; - case reg::f14: - s.f[14] = data; - return; - case reg::f15: - s.f[15] = data; - return; - case reg::f16: - s.f[16] = data; - return; - case reg::f17: - s.f[17] = data; - return; - case reg::f18: - s.f[18] = data; - return; - case reg::f19: - s.f[19] = data; - return; - case reg::f20: - s.f[20] = data; - return; - case reg::f21: - s.f[21] = data; - return; - case reg::f22: - s.f[22] = data; - return; - case reg::f23: - s.f[23] = data; - return; - case reg::f24: - s.f[24] = data; - return; - case reg::f25: - s.f[25] = data; - return; - case reg::f26: - s.f[26] = data; - return; - case reg::f27: - s.f[27] = data; - return; - case reg::f28: - s.f[28] = data; - return; - case reg::f29: - s.f[29] = data; - return; - case reg::f30: - s.f[30] = data; - return; - case reg::f31: - s.f[31] = data; - return; - case reg::pc: - s.pc = data; - return; - case reg::fcsr: - s.fcsr = data; - return; - case reg::mcycle: - s.mcycle = data; - return; - case reg::icycleinstret: - s.icycleinstret = data; - return; - case reg::mstatus: - s.mstatus = data; - return; - case reg::mtvec: - s.mtvec = data; - return; - case reg::mscratch: - s.mscratch = data; - return; - case reg::mepc: - s.mepc = data; - return; - case reg::mcause: - s.mcause = data; - return; - case reg::mtval: - s.mtval = data; - return; - case reg::misa: - s.misa = data; - return; - case reg::mie: - s.mie = data; - return; - case reg::mip: - s.mip = data; - return; - case reg::medeleg: - s.medeleg = data; - return; - case reg::mideleg: - s.mideleg = data; - return; - case reg::mcounteren: - s.mcounteren = data; - return; - case reg::menvcfg: - s.menvcfg = data; - return; - case reg::stvec: - s.stvec = data; - return; - case reg::sscratch: - s.sscratch = data; - return; - case reg::sepc: - s.sepc = data; - return; - case reg::scause: - s.scause = data; - return; - case reg::stval: - s.stval = data; - return; - case reg::satp: - s.satp = data; - return; - case reg::scounteren: - s.scounteren = data; - return; - case reg::senvcfg: - s.senvcfg = data; - return; - case reg::ilrsc: - s.ilrsc = data; - return; - case reg::iflags: - s.write_iflags(data); - return; - case reg::clint_mtimecmp: - s.clint.mtimecmp = data; - return; - case reg::plic_girqpend: - s.plic.girqpend = data; - return; - case reg::plic_girqsrvd: - s.plic.girqsrvd = data; - return; - case reg::htif_tohost: - s.htif.tohost = data; - return; - case reg::htif_fromhost: - s.htif.fromhost = data; - return; - default: - break; - } + using reg = machine_reg; + switch (static_cast(paddr)) { + case reg::x0: + s.x[0] = data; + return; + case reg::x1: + s.x[1] = data; + return; + case reg::x2: + s.x[2] = data; + return; + case reg::x3: + s.x[3] = data; + return; + case reg::x4: + s.x[4] = data; + return; + case reg::x5: + s.x[5] = data; + return; + case reg::x6: + s.x[6] = data; + return; + case reg::x7: + s.x[7] = data; + return; + case reg::x8: + s.x[8] = data; + return; + case reg::x9: + s.x[9] = data; + return; + case reg::x10: + s.x[10] = data; + return; + case reg::x11: + s.x[11] = data; + return; + case reg::x12: + s.x[12] = data; + return; + case reg::x13: + s.x[13] = data; + return; + case reg::x14: + s.x[14] = data; + return; + case reg::x15: + s.x[15] = data; + return; + case reg::x16: + s.x[16] = data; + return; + case reg::x17: + s.x[17] = data; + return; + case reg::x18: + s.x[18] = data; + return; + case reg::x19: + s.x[19] = data; + return; + case reg::x20: + s.x[20] = data; + return; + case reg::x21: + s.x[21] = data; + return; + case reg::x22: + s.x[22] = data; + return; + case reg::x23: + s.x[23] = data; + return; + case reg::x24: + s.x[24] = data; + return; + case reg::x25: + s.x[25] = data; + return; + case reg::x26: + s.x[26] = data; + return; + case reg::x27: + s.x[27] = data; + return; + case reg::x28: + s.x[28] = data; + return; + case reg::x29: + s.x[29] = data; + return; + case reg::x30: + s.x[30] = data; + return; + case reg::x31: + s.x[31] = data; + return; + case reg::f0: + s.f[0] = data; + return; + case reg::f1: + s.f[1] = data; + return; + case reg::f2: + s.f[2] = data; + return; + case reg::f3: + s.f[3] = data; + return; + case reg::f4: + s.f[4] = data; + return; + case reg::f5: + s.f[5] = data; + return; + case reg::f6: + s.f[6] = data; + return; + case reg::f7: + s.f[7] = data; + return; + case reg::f8: + s.f[8] = data; + return; + case reg::f9: + s.f[9] = data; + return; + case reg::f10: + s.f[10] = data; + return; + case reg::f11: + s.f[11] = data; + return; + case reg::f12: + s.f[12] = data; + return; + case reg::f13: + s.f[13] = data; + return; + case reg::f14: + s.f[14] = data; + return; + case reg::f15: + s.f[15] = data; + return; + case reg::f16: + s.f[16] = data; + return; + case reg::f17: + s.f[17] = data; + return; + case reg::f18: + s.f[18] = data; + return; + case reg::f19: + s.f[19] = data; + return; + case reg::f20: + s.f[20] = data; + return; + case reg::f21: + s.f[21] = data; + return; + case reg::f22: + s.f[22] = data; + return; + case reg::f23: + s.f[23] = data; + return; + case reg::f24: + s.f[24] = data; + return; + case reg::f25: + s.f[25] = data; + return; + case reg::f26: + s.f[26] = data; + return; + case reg::f27: + s.f[27] = data; + return; + case reg::f28: + s.f[28] = data; + return; + case reg::f29: + s.f[29] = data; + return; + case reg::f30: + s.f[30] = data; + return; + case reg::f31: + s.f[31] = data; + return; + case reg::pc: + s.pc = data; + return; + case reg::fcsr: + s.fcsr = data; + return; + case reg::mcycle: + s.mcycle = data; + return; + case reg::icycleinstret: + s.icycleinstret = data; + return; + case reg::mstatus: + s.mstatus = data; + return; + case reg::mtvec: + s.mtvec = data; + return; + case reg::mscratch: + s.mscratch = data; + return; + case reg::mepc: + s.mepc = data; + return; + case reg::mcause: + s.mcause = data; + return; + case reg::mtval: + s.mtval = data; + return; + case reg::misa: + s.misa = data; + return; + case reg::mie: + s.mie = data; + return; + case reg::mip: + s.mip = data; + return; + case reg::medeleg: + s.medeleg = data; + return; + case reg::mideleg: + s.mideleg = data; + return; + case reg::mcounteren: + s.mcounteren = data; + return; + case reg::menvcfg: + s.menvcfg = data; + return; + case reg::stvec: + s.stvec = data; + return; + case reg::sscratch: + s.sscratch = data; + return; + case reg::sepc: + s.sepc = data; + return; + case reg::scause: + s.scause = data; + return; + case reg::stval: + s.stval = data; + return; + case reg::satp: + s.satp = data; + return; + case reg::scounteren: + s.scounteren = data; + return; + case reg::senvcfg: + s.senvcfg = data; + return; + case reg::ilrsc: + s.ilrsc = data; + return; + case reg::iflags: + s.write_iflags(data); + return; + case reg::clint_mtimecmp: + s.clint.mtimecmp = data; + return; + case reg::plic_girqpend: + s.plic.girqpend = data; + return; + case reg::plic_girqsrvd: + s.plic.girqsrvd = data; + return; + case reg::htif_tohost: + s.htif.tohost = data; + return; + case reg::htif_fromhost: + s.htif.fromhost = data; + return; + default: + break; } if (try_write_tlb(s, paddr, data)) { return; @@ -353,217 +351,214 @@ class uarch_bridge { /// An exception is thrown if paddr can't me mapped to a valid state register. //// \} static uint64_t read_register(uint64_t paddr, machine_state &s) { - if (paddr >= PMA_SHADOW_STATE_START) { - using reg = shadow_state_reg_rel_addr; - paddr -= PMA_SHADOW_STATE_START; - switch (static_cast(paddr)) { - case reg::x0: - return s.x[0]; - case reg::x1: - return s.x[1]; - case reg::x2: - return s.x[2]; - case reg::x3: - return s.x[3]; - case reg::x4: - return s.x[4]; - case reg::x5: - return s.x[5]; - case reg::x6: - return s.x[6]; - case reg::x7: - return s.x[7]; - case reg::x8: - return s.x[8]; - case reg::x9: - return s.x[9]; - case reg::x10: - return s.x[10]; - case reg::x11: - return s.x[11]; - case reg::x12: - return s.x[12]; - case reg::x13: - return s.x[13]; - case reg::x14: - return s.x[14]; - case reg::x15: - return s.x[15]; - case reg::x16: - return s.x[16]; - case reg::x17: - return s.x[17]; - case reg::x18: - return s.x[18]; - case reg::x19: - return s.x[19]; - case reg::x20: - return s.x[20]; - case reg::x21: - return s.x[21]; - case reg::x22: - return s.x[22]; - case reg::x23: - return s.x[23]; - case reg::x24: - return s.x[24]; - case reg::x25: - return s.x[25]; - case reg::x26: - return s.x[26]; - case reg::x27: - return s.x[27]; - case reg::x28: - return s.x[28]; - case reg::x29: - return s.x[29]; - case reg::x30: - return s.x[30]; - case reg::x31: - return s.x[31]; - case reg::f0: - return s.f[0]; - case reg::f1: - return s.f[1]; - case reg::f2: - return s.f[2]; - case reg::f3: - return s.f[3]; - case reg::f4: - return s.f[4]; - case reg::f5: - return s.f[5]; - case reg::f6: - return s.f[6]; - case reg::f7: - return s.f[7]; - case reg::f8: - return s.f[8]; - case reg::f9: - return s.f[9]; - case reg::f10: - return s.f[10]; - case reg::f11: - return s.f[11]; - case reg::f12: - return s.f[12]; - case reg::f13: - return s.f[13]; - case reg::f14: - return s.f[14]; - case reg::f15: - return s.f[15]; - case reg::f16: - return s.f[16]; - case reg::f17: - return s.f[17]; - case reg::f18: - return s.f[18]; - case reg::f19: - return s.f[19]; - case reg::f20: - return s.f[20]; - case reg::f21: - return s.f[21]; - case reg::f22: - return s.f[22]; - case reg::f23: - return s.f[23]; - case reg::f24: - return s.f[24]; - case reg::f25: - return s.f[25]; - case reg::f26: - return s.f[26]; - case reg::f27: - return s.f[27]; - case reg::f28: - return s.f[28]; - case reg::f29: - return s.f[29]; - case reg::f30: - return s.f[30]; - case reg::f31: - return s.f[31]; - case reg::pc: - return s.pc; - case reg::fcsr: - return s.fcsr; - case reg::mvendorid: - return MVENDORID_INIT; - case reg::marchid: - return MARCHID_INIT; - case reg::mimpid: - return MIMPID_INIT; - case reg::mcycle: - return s.mcycle; - case reg::icycleinstret: - return s.icycleinstret; - case reg::mstatus: - return s.mstatus; - case reg::mtvec: - return s.mtvec; - case reg::mscratch: - return s.mscratch; - case reg::mepc: - return s.mepc; - case reg::mcause: - return s.mcause; - case reg::mtval: - return s.mtval; - case reg::misa: - return s.misa; - case reg::mie: - return s.mie; - case reg::mip: - return s.mip; - case reg::medeleg: - return s.medeleg; - case reg::mideleg: - return s.mideleg; - case reg::mcounteren: - return s.mcounteren; - case reg::menvcfg: - return s.menvcfg; - case reg::stvec: - return s.stvec; - case reg::sscratch: - return s.sscratch; - case reg::sepc: - return s.sepc; - case reg::scause: - return s.scause; - case reg::stval: - return s.stval; - case reg::satp: - return s.satp; - case reg::scounteren: - return s.scounteren; - case reg::senvcfg: - return s.senvcfg; - case reg::ilrsc: - return s.ilrsc; - case reg::iflags: - return s.read_iflags(); - case reg::clint_mtimecmp: - return s.clint.mtimecmp; - case reg::plic_girqpend: - return s.plic.girqpend; - case reg::plic_girqsrvd: - return s.plic.girqsrvd; - case reg::htif_tohost: - return s.htif.tohost; - case reg::htif_fromhost: - return s.htif.fromhost; - case reg::htif_ihalt: - return s.htif.ihalt; - case reg::htif_iconsole: - return s.htif.iconsole; - case reg::htif_iyield: - return s.htif.iyield; - default: - break; - } + using reg = machine_reg; + switch (static_cast(paddr)) { + case reg::x0: + return s.x[0]; + case reg::x1: + return s.x[1]; + case reg::x2: + return s.x[2]; + case reg::x3: + return s.x[3]; + case reg::x4: + return s.x[4]; + case reg::x5: + return s.x[5]; + case reg::x6: + return s.x[6]; + case reg::x7: + return s.x[7]; + case reg::x8: + return s.x[8]; + case reg::x9: + return s.x[9]; + case reg::x10: + return s.x[10]; + case reg::x11: + return s.x[11]; + case reg::x12: + return s.x[12]; + case reg::x13: + return s.x[13]; + case reg::x14: + return s.x[14]; + case reg::x15: + return s.x[15]; + case reg::x16: + return s.x[16]; + case reg::x17: + return s.x[17]; + case reg::x18: + return s.x[18]; + case reg::x19: + return s.x[19]; + case reg::x20: + return s.x[20]; + case reg::x21: + return s.x[21]; + case reg::x22: + return s.x[22]; + case reg::x23: + return s.x[23]; + case reg::x24: + return s.x[24]; + case reg::x25: + return s.x[25]; + case reg::x26: + return s.x[26]; + case reg::x27: + return s.x[27]; + case reg::x28: + return s.x[28]; + case reg::x29: + return s.x[29]; + case reg::x30: + return s.x[30]; + case reg::x31: + return s.x[31]; + case reg::f0: + return s.f[0]; + case reg::f1: + return s.f[1]; + case reg::f2: + return s.f[2]; + case reg::f3: + return s.f[3]; + case reg::f4: + return s.f[4]; + case reg::f5: + return s.f[5]; + case reg::f6: + return s.f[6]; + case reg::f7: + return s.f[7]; + case reg::f8: + return s.f[8]; + case reg::f9: + return s.f[9]; + case reg::f10: + return s.f[10]; + case reg::f11: + return s.f[11]; + case reg::f12: + return s.f[12]; + case reg::f13: + return s.f[13]; + case reg::f14: + return s.f[14]; + case reg::f15: + return s.f[15]; + case reg::f16: + return s.f[16]; + case reg::f17: + return s.f[17]; + case reg::f18: + return s.f[18]; + case reg::f19: + return s.f[19]; + case reg::f20: + return s.f[20]; + case reg::f21: + return s.f[21]; + case reg::f22: + return s.f[22]; + case reg::f23: + return s.f[23]; + case reg::f24: + return s.f[24]; + case reg::f25: + return s.f[25]; + case reg::f26: + return s.f[26]; + case reg::f27: + return s.f[27]; + case reg::f28: + return s.f[28]; + case reg::f29: + return s.f[29]; + case reg::f30: + return s.f[30]; + case reg::f31: + return s.f[31]; + case reg::pc: + return s.pc; + case reg::fcsr: + return s.fcsr; + case reg::mvendorid: + return MVENDORID_INIT; + case reg::marchid: + return MARCHID_INIT; + case reg::mimpid: + return MIMPID_INIT; + case reg::mcycle: + return s.mcycle; + case reg::icycleinstret: + return s.icycleinstret; + case reg::mstatus: + return s.mstatus; + case reg::mtvec: + return s.mtvec; + case reg::mscratch: + return s.mscratch; + case reg::mepc: + return s.mepc; + case reg::mcause: + return s.mcause; + case reg::mtval: + return s.mtval; + case reg::misa: + return s.misa; + case reg::mie: + return s.mie; + case reg::mip: + return s.mip; + case reg::medeleg: + return s.medeleg; + case reg::mideleg: + return s.mideleg; + case reg::mcounteren: + return s.mcounteren; + case reg::menvcfg: + return s.menvcfg; + case reg::stvec: + return s.stvec; + case reg::sscratch: + return s.sscratch; + case reg::sepc: + return s.sepc; + case reg::scause: + return s.scause; + case reg::stval: + return s.stval; + case reg::satp: + return s.satp; + case reg::scounteren: + return s.scounteren; + case reg::senvcfg: + return s.senvcfg; + case reg::ilrsc: + return s.ilrsc; + case reg::iflags: + return s.read_iflags(); + case reg::clint_mtimecmp: + return s.clint.mtimecmp; + case reg::plic_girqpend: + return s.plic.girqpend; + case reg::plic_girqsrvd: + return s.plic.girqsrvd; + case reg::htif_tohost: + return s.htif.tohost; + case reg::htif_fromhost: + return s.htif.fromhost; + case reg::htif_ihalt: + return s.htif.ihalt; + case reg::htif_iconsole: + return s.htif.iconsole; + case reg::htif_iyield: + return s.htif.iyield; + default: + break; } uint64_t data = 0; if (try_read_tlb(s, paddr, &data)) { @@ -579,7 +574,7 @@ class uarch_bridge { /// \param paddr Address of the state register. /// \returns The register name, if paddr maps to a register, or nullptr otherwise. static const char *get_register_name(uint64_t paddr) { - using reg = shadow_state_reg_rel_addr; + using reg = machine_reg; switch (static_cast(paddr)) { case reg::x0: return "x0"; @@ -788,12 +783,12 @@ class uarch_bridge { default: break; } - if (paddr >= shadow_state_get_x_abs_addr(0) && paddr <= shadow_state_get_x_abs_addr(X_REG_COUNT - 1) && + if (paddr >= machine_reg_address(machine_reg::x0) && paddr <= machine_reg_address(machine_reg::x31) && (paddr & 0b111) == 0) { return "x"; } - if (paddr >= shadow_state_get_f_abs_addr(0) && paddr <= shadow_state_get_f_abs_addr(F_REG_COUNT - 1) && + if (paddr >= machine_reg_address(machine_reg::f0) && paddr <= machine_reg_address(machine_reg::f31) && (paddr & 0b111) == 0) { return "f"; } diff --git a/src/uarch-record-state-access.h b/src/uarch-record-state-access.h index 4528c08f..bec3a9c7 100644 --- a/src/uarch-record-state-access.h +++ b/src/uarch-record-state-access.h @@ -300,45 +300,44 @@ class uarch_record_state_access : public i_uarch_state_access(m_us.halt_flag), "uarch.halt_flag") != 0; + return log_read(machine_reg_address(machine_reg::uarch_halt_flag), static_cast(m_us.halt_flag), + "uarch.halt_flag") != 0; } void do_set_halt_flag() { - log_before_write_write_and_update(shadow_uarch_state_get_reg_abs_addr(machine_reg::uarch_halt_flag), - m_us.halt_flag, true, "uarch.halt_flag"); + log_before_write_write_and_update(machine_reg_address(machine_reg::uarch_halt_flag), m_us.halt_flag, true, + "uarch.halt_flag"); } void do_reset_halt_flag() { - log_before_write_write_and_update(shadow_uarch_state_get_reg_abs_addr(machine_reg::uarch_halt_flag), - m_us.halt_flag, false, "uarch.halt_flag"); + log_before_write_write_and_update(machine_reg_address(machine_reg::uarch_halt_flag), m_us.halt_flag, false, + "uarch.halt_flag"); } uint64_t do_read_word(uint64_t paddr) { diff --git a/src/uarch-replay-state-access.h b/src/uarch-replay-state-access.h index 8f05f219..ab53c31b 100644 --- a/src/uarch-replay-state-access.h +++ b/src/uarch-replay-state-access.h @@ -266,42 +266,40 @@ class uarch_replay_state_access : public i_uarch_state_access(true), - "uarch.halt_flag"); + check_write(machine_reg_address(machine_reg::uarch_halt_flag), static_cast(true), "uarch.halt_flag"); } void do_reset_halt_flag() { - check_write(shadow_uarch_state_get_reg_abs_addr(machine_reg::uarch_halt_flag), static_cast(false), - "uarch.halt_flag"); + check_write(machine_reg_address(machine_reg::uarch_halt_flag), static_cast(false), "uarch.halt_flag"); } uint64_t do_read_word(uint64_t paddr) { diff --git a/uarch/uarch-machine-state-access.h b/uarch/uarch-machine-state-access.h index 448ba6f1..f9b33cdf 100644 --- a/uarch/uarch-machine-state-access.h +++ b/uarch/uarch-machine-state-access.h @@ -26,8 +26,7 @@ #include "i-state-access.h" #include "pma-constants.h" #include "riscv-constants.h" -#include "shadow-state.h" -#include "shadow-uarch-state.h" +#include "machine-reg.h" #include "shadow-pmas.h" #include "uarch-constants.h" #include "uarch-defines.h" @@ -171,247 +170,247 @@ class uarch_machine_state_access : public i_state_access(shadow_state_get_x_abs_addr(reg)); + return raw_read_memory(machine_reg_address(machine_reg::x0, reg)); } void do_write_x(int reg, uint64_t val) { - raw_write_memory(shadow_state_get_x_abs_addr(reg), val); + raw_write_memory(machine_reg_address(machine_reg::x0, reg), val); } uint64_t do_read_f(int reg) { - return raw_read_memory(shadow_state_get_f_abs_addr(reg)); + return raw_read_memory(machine_reg_address(machine_reg::f0, reg)); } void do_write_f(int reg, uint64_t val) { - raw_write_memory(shadow_state_get_f_abs_addr(reg), val); + raw_write_memory(machine_reg_address(machine_reg::f0, reg), val); } uint64_t do_read_pc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::pc)); + return raw_read_memory(machine_reg_address(machine_reg::pc)); } void do_write_pc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::pc), val); + raw_write_memory(machine_reg_address(machine_reg::pc), val); } uint64_t do_read_fcsr() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr)); + return raw_read_memory(machine_reg_address(machine_reg::fcsr)); } void do_write_fcsr(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr), val); + raw_write_memory(machine_reg_address(machine_reg::fcsr), val); } uint64_t do_read_icycleinstret() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret)); + return raw_read_memory(machine_reg_address(machine_reg::icycleinstret)); } void do_write_icycleinstret(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret), val); + raw_write_memory(machine_reg_address(machine_reg::icycleinstret), val); } uint64_t do_read_mvendorid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mvendorid)); + return raw_read_memory(machine_reg_address(machine_reg::mvendorid)); } uint64_t do_read_marchid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::marchid)); + return raw_read_memory(machine_reg_address(machine_reg::marchid)); } uint64_t do_read_mimpid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mimpid)); + return raw_read_memory(machine_reg_address(machine_reg::mimpid)); } uint64_t do_read_mcycle() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle)); + return raw_read_memory(machine_reg_address(machine_reg::mcycle)); } void do_write_mcycle(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle), val); + raw_write_memory(machine_reg_address(machine_reg::mcycle), val); } uint64_t do_read_mstatus() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus)); + return raw_read_memory(machine_reg_address(machine_reg::mstatus)); } void do_write_mstatus(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus), val); + raw_write_memory(machine_reg_address(machine_reg::mstatus), val); } uint64_t do_read_mtvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec)); + return raw_read_memory(machine_reg_address(machine_reg::mtvec)); } void do_write_mtvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec), val); + raw_write_memory(machine_reg_address(machine_reg::mtvec), val); } uint64_t do_read_mscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch)); + return raw_read_memory(machine_reg_address(machine_reg::mscratch)); } void do_write_mscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch), val); + raw_write_memory(machine_reg_address(machine_reg::mscratch), val); } uint64_t do_read_mepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc)); + return raw_read_memory(machine_reg_address(machine_reg::mepc)); } void do_write_mepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc), val); + raw_write_memory(machine_reg_address(machine_reg::mepc), val); } uint64_t do_read_mcause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause)); + return raw_read_memory(machine_reg_address(machine_reg::mcause)); } void do_write_mcause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause), val); + raw_write_memory(machine_reg_address(machine_reg::mcause), val); } uint64_t do_read_mtval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval)); + return raw_read_memory(machine_reg_address(machine_reg::mtval)); } void do_write_mtval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval), val); + raw_write_memory(machine_reg_address(machine_reg::mtval), val); } uint64_t do_read_misa() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::misa)); + return raw_read_memory(machine_reg_address(machine_reg::misa)); } void do_write_misa(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::misa), val); + raw_write_memory(machine_reg_address(machine_reg::misa), val); } uint64_t do_read_mie() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mie)); + return raw_read_memory(machine_reg_address(machine_reg::mie)); } void do_write_mie(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mie), val); + raw_write_memory(machine_reg_address(machine_reg::mie), val); } uint64_t do_read_mip() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mip)); + return raw_read_memory(machine_reg_address(machine_reg::mip)); } void do_write_mip(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mip), val); + raw_write_memory(machine_reg_address(machine_reg::mip), val); } uint64_t do_read_medeleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg)); + return raw_read_memory(machine_reg_address(machine_reg::medeleg)); } void do_write_medeleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg), val); + raw_write_memory(machine_reg_address(machine_reg::medeleg), val); } uint64_t do_read_mideleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg)); + return raw_read_memory(machine_reg_address(machine_reg::mideleg)); } void do_write_mideleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg), val); + raw_write_memory(machine_reg_address(machine_reg::mideleg), val); } uint64_t do_read_mcounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren)); + return raw_read_memory(machine_reg_address(machine_reg::mcounteren)); } void do_write_mcounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren), val); + raw_write_memory(machine_reg_address(machine_reg::mcounteren), val); } uint64_t do_read_senvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg)); + return raw_read_memory(machine_reg_address(machine_reg::senvcfg)); } void do_write_senvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg), val); + raw_write_memory(machine_reg_address(machine_reg::senvcfg), val); } uint64_t do_read_menvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg)); + return raw_read_memory(machine_reg_address(machine_reg::menvcfg)); } void do_write_menvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg), val); + raw_write_memory(machine_reg_address(machine_reg::menvcfg), val); } uint64_t do_read_stvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec)); + return raw_read_memory(machine_reg_address(machine_reg::stvec)); } void do_write_stvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec), val); + raw_write_memory(machine_reg_address(machine_reg::stvec), val); } uint64_t do_read_sscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch)); + return raw_read_memory(machine_reg_address(machine_reg::sscratch)); } void do_write_sscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch), val); + raw_write_memory(machine_reg_address(machine_reg::sscratch), val); } uint64_t do_read_sepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc)); + return raw_read_memory(machine_reg_address(machine_reg::sepc)); } void do_write_sepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc), val); + raw_write_memory(machine_reg_address(machine_reg::sepc), val); } uint64_t do_read_scause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scause)); + return raw_read_memory(machine_reg_address(machine_reg::scause)); } void do_write_scause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scause), val); + raw_write_memory(machine_reg_address(machine_reg::scause), val); } uint64_t do_read_stval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stval)); + return raw_read_memory(machine_reg_address(machine_reg::stval)); } void do_write_stval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stval), val); + raw_write_memory(machine_reg_address(machine_reg::stval), val); } uint64_t do_read_satp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::satp)); + return raw_read_memory(machine_reg_address(machine_reg::satp)); } void do_write_satp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::satp), val); + raw_write_memory(machine_reg_address(machine_reg::satp), val); } uint64_t do_read_scounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren)); + return raw_read_memory(machine_reg_address(machine_reg::scounteren)); } void do_write_scounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren), val); + raw_write_memory(machine_reg_address(machine_reg::scounteren), val); } uint64_t do_read_ilrsc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc)); + return raw_read_memory(machine_reg_address(machine_reg::ilrsc)); } void do_write_ilrsc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc), val); + raw_write_memory(machine_reg_address(machine_reg::ilrsc), val); } uint64_t do_read_iflags() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags)); + return raw_read_memory(machine_reg_address(machine_reg::iflags)); } void do_write_iflags(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags), val); + raw_write_memory(machine_reg_address(machine_reg::iflags), val); } void do_set_iflags_H() { @@ -472,69 +471,69 @@ class uarch_machine_state_access : public i_state_access(shadow_state_get_reg_abs_addr(machine_reg::iunrep)); + return raw_read_memory(machine_reg_address(machine_reg::iunrep)); } void do_write_iunrep(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iunrep), val); + raw_write_memory(machine_reg_address(machine_reg::iunrep), val); } uint64_t do_read_clint_mtimecmp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp)); + return raw_read_memory(machine_reg_address(machine_reg::clint_mtimecmp)); } void do_write_clint_mtimecmp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp), val); + raw_write_memory(machine_reg_address(machine_reg::clint_mtimecmp), val); } uint64_t do_read_plic_girqpend() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend)); + return raw_read_memory(machine_reg_address(machine_reg::plic_girqpend)); } void do_write_plic_girqpend(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend), val); + raw_write_memory(machine_reg_address(machine_reg::plic_girqpend), val); } uint64_t do_read_plic_girqsrvd() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd)); + return raw_read_memory(machine_reg_address(machine_reg::plic_girqsrvd)); } void do_write_plic_girqsrvd(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd), val); + raw_write_memory(machine_reg_address(machine_reg::plic_girqsrvd), val); } uint64_t do_read_htif_fromhost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost)); + return raw_read_memory(machine_reg_address(machine_reg::htif_fromhost)); } void do_write_htif_fromhost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost), val); + raw_write_memory(machine_reg_address(machine_reg::htif_fromhost), val); } uint64_t do_read_htif_tohost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost)); + return raw_read_memory(machine_reg_address(machine_reg::htif_tohost)); } void do_write_htif_tohost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost), val); + raw_write_memory(machine_reg_address(machine_reg::htif_tohost), val); } uint64_t do_read_htif_ihalt() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_ihalt)); + return raw_read_memory(machine_reg_address(machine_reg::htif_ihalt)); } uint64_t do_read_htif_iconsole() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iconsole)); + return raw_read_memory(machine_reg_address(machine_reg::htif_iconsole)); } uint64_t do_read_htif_iyield() { - return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iyield)); + return raw_read_memory(machine_reg_address(machine_reg::htif_iyield)); } std::pair do_poll_external_interrupts(uint64_t mcycle, uint64_t /*mcycle_max*/) { return {mcycle, false}; } - + uint64_t do_read_pma_istart(int i) { return raw_read_memory(shadow_pmas_get_pma_abs_addr(i)); }