From 5271d12520b25ecc69dae9f318d4b132c44d75e5 Mon Sep 17 00:00:00 2001 From: Eduardo Bart Date: Sun, 7 Apr 2024 17:35:27 -0300 Subject: [PATCH] feat: optimized interpreter with computed gotos --- src/Makefile | 4 +- src/interpret.cpp | 2608 ++++++++++++++++++++++++++++++++++++----- src/riscv-constants.h | 152 --- 3 files changed, 2340 insertions(+), 424 deletions(-) diff --git a/src/Makefile b/src/Makefile index 31f2b203c..92f1f8987 100644 --- a/src/Makefile +++ b/src/Makefile @@ -205,8 +205,8 @@ ifneq (,$(filter gcc,$(CC))) # but we don't use -O3 because it enables some other flags that are not worth for the interpreter. OPTFLAGS+=-fgcse-after-reload -fpredictive-commoning -fsplit-paths -ftree-partial-pre endif -# Enable large jump tables to improve performance of instruction decoding in interpret.cpp -OPTFLAGS+=-fjump-tables --param jump-table-max-growth-ratio-for-speed=4096 +# Disable jump tables to improve performance of instruction decoding in interpret.cpp +OPTFLAGS+=-fno-jump-tables endif # Link time optimizations diff --git a/src/interpret.cpp b/src/interpret.cpp index cbdde6c3c..98c23e3bc 100644 --- a/src/interpret.cpp +++ b/src/interpret.cpp @@ -533,10 +533,10 @@ static inline void set_rtc_interrupt(STATE_ACCESS &a, uint64_t mcycle) { } } -/// \brief Obtains the funct3 and opcode fields an instruction. +/// \brief Obtains the id fields an instruction. /// \param insn Instruction. -static FORCE_INLINE uint32_t insn_get_funct3_opcode(uint32_t insn) { - return ((insn >> 5) & 0b111'0000000) | (insn & 0b1111111); +static FORCE_INLINE uint32_t insn_get_id(uint32_t insn) { + return ((insn >> 5) & 0b1111'0000000) | (insn & 0b1111111); } /// \brief Obtains the funct3 and trailing 0 bits from an instruction. @@ -658,12 +658,6 @@ static inline uint32_t insn_get_rs3(uint32_t insn) { return (insn >> 27); } -/// \brief Obtains the compressed instruction funct3 and opcode fields an instruction. -/// \param insn Instruction. -static FORCE_INLINE uint32_t insn_get_c_funct3(uint32_t insn) { - return ((insn >> 11) & 0b111'00) | (insn & 0b11); -} - /// \brief Obtains the compressed instruction funct6, funct2 and opcode fields an instruction. /// \param insn Instruction. static inline uint32_t insn_get_CA_funct6_funct2(uint32_t insn) { @@ -5174,265 +5168,6 @@ static FORCE_INLINE execute_status execute_C_SDSP(STATE_ACCESS &a, uint64_t &pc, return execute_C_S(a, pc, mcycle, rs2, 0x2, imm); } -/// \brief Decodes and executes an instruction. -/// \tparam STATE_ACCESS Class of machine state accessor object. -/// \param a Machine state accessor object. -/// \param pc Current pc. -/// \param insn Instruction. -/// \return execute_status::failure if an exception was raised, or -/// execute_status::success otherwise. -/// \details The execute_insn function decodes the instruction in multiple levels. When we know for sure that -/// the instruction could only be a <FOO>, a function with the name execute_<FOO> will be called. -/// See [RV32/64G Instruction Set -/// Listings](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#chapter.19) and [Instruction -/// listings for RISC-V](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#table.19.2). -template -static FORCE_INLINE execute_status execute_insn(STATE_ACCESS &a, uint64_t &pc, uint64_t &mcycle, uint32_t insn) { - // Is compressed instruction - if ((insn & 3) != 3) { - // The fetch may read 4 bytes as an optimization, - // but the compressed instruction uses only the 2 less significant bytes - insn = static_cast(insn); - auto c_funct3 = static_cast(insn_get_c_funct3(insn)); - switch (c_funct3) { - case insn_c_funct3::C_ADDI4SPN: - return execute_C_ADDI4SPN(a, pc, insn); - case insn_c_funct3::C_LW: - return execute_C_LW(a, pc, mcycle, insn); - case insn_c_funct3::C_LD: - return execute_C_LD(a, pc, mcycle, insn); - case insn_c_funct3::C_SW: - return execute_C_SW(a, pc, mcycle, insn); - case insn_c_funct3::C_SD: - return execute_C_SD(a, pc, mcycle, insn); - case insn_c_funct3::C_Q1_SET0: - return execute_C_Q1_SET0(a, pc, insn); - case insn_c_funct3::C_ADDIW: - return execute_C_ADDIW(a, pc, insn); - case insn_c_funct3::C_LI: - return execute_C_LI(a, pc, insn); - case insn_c_funct3::C_Q1_SET1: - return execute_C_Q1_SET1(a, pc, insn); - case insn_c_funct3::C_Q1_SET2: - return execute_C_Q1_SET2(a, pc, insn); - case insn_c_funct3::C_J: - return execute_C_J(a, pc, insn); - case insn_c_funct3::C_BEQZ: - return execute_C_BEQZ(a, pc, insn); - case insn_c_funct3::C_BNEZ: - return execute_C_BNEZ(a, pc, insn); - case insn_c_funct3::C_SLLI: - return execute_C_SLLI(a, pc, insn); - case insn_c_funct3::C_LWSP: - return execute_C_LWSP(a, pc, mcycle, insn); - case insn_c_funct3::C_LDSP: - return execute_C_LDSP(a, pc, mcycle, insn); - case insn_c_funct3::C_Q2_SET0: - return execute_C_Q2_SET0(a, pc, insn); - case insn_c_funct3::C_SWSP: - return execute_C_SWSP(a, pc, mcycle, insn); - case insn_c_funct3::C_SDSP: - return execute_C_SDSP(a, pc, mcycle, insn); - case insn_c_funct3::C_FLD: - return execute_C_FLD(a, pc, mcycle, insn); - case insn_c_funct3::C_FSD: - return execute_C_FSD(a, pc, mcycle, insn); - case insn_c_funct3::C_FLDSP: - return execute_C_FLDSP(a, pc, mcycle, insn); - case insn_c_funct3::C_FSDSP: - return execute_C_FSDSP(a, pc, mcycle, insn); - default: - return raise_illegal_insn_exception(a, pc, insn); - } - } else { - auto funct3_opcode = static_cast(insn_get_funct3_opcode(insn)); - // This switch will be optimized as a single jump in conjuction with GCC flags - // -fjump-tables --param jump-table-max-growth-ratio-for-speed=4096 - switch (funct3_opcode) { - case insn_funct3_opcode::LB: - return execute_LB(a, pc, mcycle, insn); - case insn_funct3_opcode::LH: - return execute_LH(a, pc, mcycle, insn); - case insn_funct3_opcode::LW: - return execute_LW(a, pc, mcycle, insn); - case insn_funct3_opcode::LD: - return execute_LD(a, pc, mcycle, insn); - case insn_funct3_opcode::LBU: - return execute_LBU(a, pc, mcycle, insn); - case insn_funct3_opcode::LHU: - return execute_LHU(a, pc, mcycle, insn); - case insn_funct3_opcode::LWU: - return execute_LWU(a, pc, mcycle, insn); - case insn_funct3_opcode::SB: - return execute_SB(a, pc, mcycle, insn); - case insn_funct3_opcode::SH: - return execute_SH(a, pc, mcycle, insn); - case insn_funct3_opcode::SW: - return execute_SW(a, pc, mcycle, insn); - case insn_funct3_opcode::SD: - return execute_SD(a, pc, mcycle, insn); - case insn_funct3_opcode::FENCE: - return execute_FENCE(a, pc, insn); - case insn_funct3_opcode::FENCE_I: - return execute_FENCE_I(a, pc, insn); - case insn_funct3_opcode::ADDI: - return execute_ADDI(a, pc, insn); - case insn_funct3_opcode::SLLI: - return execute_SLLI(a, pc, insn); - case insn_funct3_opcode::SLTI: - return execute_SLTI(a, pc, insn); - case insn_funct3_opcode::SLTIU: - return execute_SLTIU(a, pc, insn); - case insn_funct3_opcode::XORI: - return execute_XORI(a, pc, insn); - case insn_funct3_opcode::ORI: - return execute_ORI(a, pc, insn); - case insn_funct3_opcode::ANDI: - return execute_ANDI(a, pc, insn); - case insn_funct3_opcode::ADDIW: - return execute_ADDIW(a, pc, insn); - case insn_funct3_opcode::SLLIW: - return execute_SLLIW(a, pc, insn); - case insn_funct3_opcode::SLLW: - return execute_SLLW(a, pc, insn); - case insn_funct3_opcode::DIVW: - return execute_DIVW(a, pc, insn); - case insn_funct3_opcode::REMW: - return execute_REMW(a, pc, insn); - case insn_funct3_opcode::REMUW: - return execute_REMUW(a, pc, insn); - case insn_funct3_opcode::BEQ: - return execute_BEQ(a, pc, insn); - case insn_funct3_opcode::BNE: - return execute_BNE(a, pc, insn); - case insn_funct3_opcode::BLT: - return execute_BLT(a, pc, insn); - case insn_funct3_opcode::BGE: - return execute_BGE(a, pc, insn); - case insn_funct3_opcode::BLTU: - return execute_BLTU(a, pc, insn); - case insn_funct3_opcode::BGEU: - return execute_BGEU(a, pc, insn); - case insn_funct3_opcode::JALR: - return execute_JALR(a, pc, insn); - case insn_funct3_opcode::CSRRW: - return execute_CSRRW(a, pc, mcycle, insn); - case insn_funct3_opcode::CSRRS: - return execute_CSRRS(a, pc, mcycle, insn); - case insn_funct3_opcode::CSRRC: - return execute_CSRRC(a, pc, mcycle, insn); - case insn_funct3_opcode::CSRRWI: - return execute_CSRRWI(a, pc, mcycle, insn); - case insn_funct3_opcode::CSRRSI: - return execute_CSRRSI(a, pc, mcycle, insn); - case insn_funct3_opcode::CSRRCI: - return execute_CSRRCI(a, pc, mcycle, insn); - case insn_funct3_opcode::AUIPC_000: - case insn_funct3_opcode::AUIPC_001: - case insn_funct3_opcode::AUIPC_010: - case insn_funct3_opcode::AUIPC_011: - case insn_funct3_opcode::AUIPC_100: - case insn_funct3_opcode::AUIPC_101: - case insn_funct3_opcode::AUIPC_110: - case insn_funct3_opcode::AUIPC_111: - return execute_AUIPC(a, pc, insn); - case insn_funct3_opcode::LUI_000: - case insn_funct3_opcode::LUI_001: - case insn_funct3_opcode::LUI_010: - case insn_funct3_opcode::LUI_011: - case insn_funct3_opcode::LUI_100: - case insn_funct3_opcode::LUI_101: - case insn_funct3_opcode::LUI_110: - case insn_funct3_opcode::LUI_111: - return execute_LUI(a, pc, insn); - case insn_funct3_opcode::JAL_000: - case insn_funct3_opcode::JAL_001: - case insn_funct3_opcode::JAL_010: - case insn_funct3_opcode::JAL_011: - case insn_funct3_opcode::JAL_100: - case insn_funct3_opcode::JAL_101: - case insn_funct3_opcode::JAL_110: - case insn_funct3_opcode::JAL_111: - return execute_JAL(a, pc, insn); - case insn_funct3_opcode::SRLI_SRAI: - return execute_SRLI_SRAI(a, pc, insn); - case insn_funct3_opcode::SRLIW_SRAIW: - return execute_SRLIW_SRAIW(a, pc, insn); - case insn_funct3_opcode::AMO_W: - return execute_AMO_W(a, pc, mcycle, insn); - case insn_funct3_opcode::AMO_D: - return execute_AMO_D(a, pc, mcycle, insn); - case insn_funct3_opcode::ADD_MUL_SUB: - return execute_ADD_MUL_SUB(a, pc, insn); - case insn_funct3_opcode::SLL_MULH: - return execute_SLL_MULH(a, pc, insn); - case insn_funct3_opcode::SLT_MULHSU: - return execute_SLT_MULHSU(a, pc, insn); - case insn_funct3_opcode::SLTU_MULHU: - return execute_SLTU_MULHU(a, pc, insn); - case insn_funct3_opcode::XOR_DIV: - return execute_XOR_DIV(a, pc, insn); - case insn_funct3_opcode::SRL_DIVU_SRA: - return execute_SRL_DIVU_SRA(a, pc, insn); - case insn_funct3_opcode::OR_REM: - return execute_OR_REM(a, pc, insn); - case insn_funct3_opcode::AND_REMU: - return execute_AND_REMU(a, pc, insn); - case insn_funct3_opcode::ADDW_MULW_SUBW: - return execute_ADDW_MULW_SUBW(a, pc, insn); - case insn_funct3_opcode::SRLW_DIVUW_SRAW: - return execute_SRLW_DIVUW_SRAW(a, pc, insn); - case insn_funct3_opcode::PRIVILEGED: - return execute_privileged(a, pc, mcycle, insn); - case insn_funct3_opcode::FSW: - return execute_FSW(a, pc, mcycle, insn); - case insn_funct3_opcode::FSD: - return execute_FSD(a, pc, mcycle, insn); - case insn_funct3_opcode::FLW: - return execute_FLW(a, pc, mcycle, insn); - case insn_funct3_opcode::FLD: - return execute_FLD(a, pc, mcycle, insn); - case insn_funct3_opcode::FMADD_RNE: - case insn_funct3_opcode::FMADD_RTZ: - case insn_funct3_opcode::FMADD_RDN: - case insn_funct3_opcode::FMADD_RUP: - case insn_funct3_opcode::FMADD_RMM: - case insn_funct3_opcode::FMADD_DYN: - return execute_FMADD(a, pc, insn); - case insn_funct3_opcode::FMSUB_RNE: - case insn_funct3_opcode::FMSUB_RTZ: - case insn_funct3_opcode::FMSUB_RDN: - case insn_funct3_opcode::FMSUB_RUP: - case insn_funct3_opcode::FMSUB_RMM: - case insn_funct3_opcode::FMSUB_DYN: - return execute_FMSUB(a, pc, insn); - case insn_funct3_opcode::FNMSUB_RNE: - case insn_funct3_opcode::FNMSUB_RTZ: - case insn_funct3_opcode::FNMSUB_RDN: - case insn_funct3_opcode::FNMSUB_RUP: - case insn_funct3_opcode::FNMSUB_RMM: - case insn_funct3_opcode::FNMSUB_DYN: - return execute_FNMSUB(a, pc, insn); - case insn_funct3_opcode::FNMADD_RNE: - case insn_funct3_opcode::FNMADD_RTZ: - case insn_funct3_opcode::FNMADD_RDN: - case insn_funct3_opcode::FNMADD_RUP: - case insn_funct3_opcode::FNMADD_RMM: - case insn_funct3_opcode::FNMADD_DYN: - return execute_FNMADD(a, pc, insn); - case insn_funct3_opcode::FD_000: - case insn_funct3_opcode::FD_001: - case insn_funct3_opcode::FD_010: - case insn_funct3_opcode::FD_011: - case insn_funct3_opcode::FD_100: - case insn_funct3_opcode::FD_111: - return execute_FD(a, pc, insn); - default: - return raise_illegal_insn_exception(a, pc, insn); - } - } -} - /// \brief Instruction fetch status code enum class fetch_status : int { exception, ///< Instruction fetch failed: exception raised @@ -5625,8 +5360,2341 @@ static NO_INLINE execute_status interpret_loop(STATE_ACCESS &a, uint64_t mcycle_ // Try to fetch the next instruction if (likely(fetch_insn(a, pc, insn, fetch_vaddr_page, fetch_vh_offset) == fetch_status::success)) { - // Try to execute it - const execute_status status = execute_insn(a, pc, mcycle, insn); + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" + // This table was auto generated by a script + static const void *insn_labels[2048] = { + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&LB, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FENCE, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ADDI, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&AUIPC, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ADDIW, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&SB, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ADD_MUL_SUB, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&LUI, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ADDW_MULW_SUBW, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FMADD, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FMSUB, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FNMSUB, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FNMADD, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FD, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&BEQ, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&JALR, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&JAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&PRIVILEGED, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&LH, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FENCE_I, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&SLLI, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&AUIPC, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&SLLIW, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&SH, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&SLL_MULH, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&LUI, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&SLLW, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FMADD, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FMSUB, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FNMSUB, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FNMADD, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&FD, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&BNE, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&JAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&CSRRW, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_ADDI4SPN, + &&C_Q1_SET0, + &&C_SLLI, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&LW, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FLW, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&SLTI, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&AUIPC, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&SW, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FSW, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&AMO_W, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&SLT_MULHSU, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&LUI, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FMADD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FMSUB, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FNMSUB, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FNMADD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&JAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&CSRRS, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&LD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FLD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&SLTIU, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&AUIPC, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&SD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FSD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&AMO_D, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&SLTU_MULHU, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&LUI, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FMADD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FMSUB, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FNMSUB, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FNMADD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&FD, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&JAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&CSRRC, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_FLD, + &&C_ADDIW, + &&C_FLDSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&LBU, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&XORI, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&AUIPC, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&XOR_DIV, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&LUI, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&DIVW, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&FMADD, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&FMSUB, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&FNMSUB, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&FNMADD, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&FD, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&BLT, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&JAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&LHU, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&SRLI_SRAI, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&AUIPC, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&SRLIW_SRAIW, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&SRL_DIVU_SRA, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&LUI, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&SRLW_DIVUW_SRAW, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&BGE, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&JAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&CSRRWI, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LW, + &&C_LI, + &&C_LWSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&LWU, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ORI, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&AUIPC, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&OR_REM, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&LUI, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&REMW, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&BLTU, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&JAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&CSRRSI, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ANDI, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&AUIPC, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&AND_REMU, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&LUI, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&REMUW, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&FMADD, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&FMSUB, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&FNMSUB, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&FNMADD, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&FD, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&BGEU, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&JAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&CSRRCI, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&C_LD, + &&C_Q1_SET1, + &&C_LDSP, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&LB, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FENCE, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ADDI, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&AUIPC, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ADDIW, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&SB, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ADD_MUL_SUB, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&LUI, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ADDW_MULW_SUBW, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FMADD, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FMSUB, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FNMSUB, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FNMADD, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FD, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&BEQ, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&JALR, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&JAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&PRIVILEGED, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&LH, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FENCE_I, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&SLLI, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&AUIPC, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&SLLIW, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&SH, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&SLL_MULH, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&LUI, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&SLLW, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FMADD, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FMSUB, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FNMSUB, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FNMADD, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&FD, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&BNE, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&JAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&CSRRW, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&ILLEGAL, + &&C_Q1_SET2, + &&C_Q2_SET0, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&LW, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FLW, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&SLTI, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&AUIPC, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&SW, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FSW, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&AMO_W, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&SLT_MULHSU, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&LUI, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FMADD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FMSUB, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FNMSUB, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FNMADD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&JAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&CSRRS, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&LD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FLD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&SLTIU, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&AUIPC, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&SD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FSD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&AMO_D, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&SLTU_MULHU, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&LUI, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FMADD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FMSUB, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FNMSUB, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FNMADD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&FD, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&JAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&CSRRC, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_FSD, + &&C_J, + &&C_FSDSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&LBU, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&XORI, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&AUIPC, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&XOR_DIV, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&LUI, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&DIVW, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&FMADD, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&FMSUB, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&FNMSUB, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&FNMADD, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&FD, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&BLT, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&JAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&LHU, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&SRLI_SRAI, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&AUIPC, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&SRLIW_SRAIW, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&SRL_DIVU_SRA, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&LUI, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&SRLW_DIVUW_SRAW, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&BGE, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&JAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&CSRRWI, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SW, + &&C_BEQZ, + &&C_SWSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&LWU, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ORI, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&AUIPC, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&OR_REM, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&LUI, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&REMW, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&BLTU, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&JAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&CSRRSI, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ANDI, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&AUIPC, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&AND_REMU, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&LUI, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&REMUW, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&FMADD, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&FMSUB, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&FNMSUB, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&FNMADD, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&FD, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&BGEU, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&JAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&CSRRCI, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + &&C_SD, + &&C_BNEZ, + &&C_SDSP, + &&ILLEGAL, + }; + + // NOLINTNEXTLINE(cppcoreguidelines-init-variables) + execute_status status; + + // ??(edubart): computed goto is not supported by all compilers, + // we should fallback to use a normal switch in that case. + goto *insn_labels[insn_get_id(insn)]; +#pragma GCC diagnostic pop + { + LB: + status = execute_LB(a, pc, mcycle, insn); + goto NEXT_INSN; + LH: + status = execute_LH(a, pc, mcycle, insn); + goto NEXT_INSN; + LW: + status = execute_LW(a, pc, mcycle, insn); + goto NEXT_INSN; + LD: + status = execute_LD(a, pc, mcycle, insn); + goto NEXT_INSN; + LBU: + status = execute_LBU(a, pc, mcycle, insn); + goto NEXT_INSN; + LHU: + status = execute_LHU(a, pc, mcycle, insn); + goto NEXT_INSN; + LWU: + status = execute_LWU(a, pc, mcycle, insn); + goto NEXT_INSN; + SB: + status = execute_SB(a, pc, mcycle, insn); + goto NEXT_INSN; + SH: + status = execute_SH(a, pc, mcycle, insn); + goto NEXT_INSN; + SW: + status = execute_SW(a, pc, mcycle, insn); + goto NEXT_INSN; + SD: + status = execute_SD(a, pc, mcycle, insn); + goto NEXT_INSN; + FENCE: + status = execute_FENCE(a, pc, insn); + goto NEXT_INSN; + FENCE_I: + status = execute_FENCE_I(a, pc, insn); + goto NEXT_INSN; + ADDI: + status = execute_ADDI(a, pc, insn); + goto NEXT_INSN; + SLLI: + status = execute_SLLI(a, pc, insn); + goto NEXT_INSN; + SLTI: + status = execute_SLTI(a, pc, insn); + goto NEXT_INSN; + SLTIU: + status = execute_SLTIU(a, pc, insn); + goto NEXT_INSN; + XORI: + status = execute_XORI(a, pc, insn); + goto NEXT_INSN; + ORI: + status = execute_ORI(a, pc, insn); + goto NEXT_INSN; + ANDI: + status = execute_ANDI(a, pc, insn); + goto NEXT_INSN; + ADDIW: + status = execute_ADDIW(a, pc, insn); + goto NEXT_INSN; + SLLIW: + status = execute_SLLIW(a, pc, insn); + goto NEXT_INSN; + SLLW: + status = execute_SLLW(a, pc, insn); + goto NEXT_INSN; + DIVW: + status = execute_DIVW(a, pc, insn); + goto NEXT_INSN; + REMW: + status = execute_REMW(a, pc, insn); + goto NEXT_INSN; + REMUW: + status = execute_REMUW(a, pc, insn); + goto NEXT_INSN; + BEQ: + status = execute_BEQ(a, pc, insn); + goto NEXT_INSN; + BNE: + status = execute_BNE(a, pc, insn); + goto NEXT_INSN; + BLT: + status = execute_BLT(a, pc, insn); + goto NEXT_INSN; + BGE: + status = execute_BGE(a, pc, insn); + goto NEXT_INSN; + BLTU: + status = execute_BLTU(a, pc, insn); + goto NEXT_INSN; + BGEU: + status = execute_BGEU(a, pc, insn); + goto NEXT_INSN; + JALR: + status = execute_JALR(a, pc, insn); + goto NEXT_INSN; + CSRRW: + status = execute_CSRRW(a, pc, mcycle, insn); + goto NEXT_INSN; + CSRRS: + status = execute_CSRRS(a, pc, mcycle, insn); + goto NEXT_INSN; + CSRRC: + status = execute_CSRRC(a, pc, mcycle, insn); + goto NEXT_INSN; + CSRRWI: + status = execute_CSRRWI(a, pc, mcycle, insn); + goto NEXT_INSN; + CSRRSI: + status = execute_CSRRSI(a, pc, mcycle, insn); + goto NEXT_INSN; + CSRRCI: + status = execute_CSRRCI(a, pc, mcycle, insn); + goto NEXT_INSN; + AUIPC: + status = execute_AUIPC(a, pc, insn); + goto NEXT_INSN; + LUI: + status = execute_LUI(a, pc, insn); + goto NEXT_INSN; + JAL: + status = execute_JAL(a, pc, insn); + goto NEXT_INSN; + SRLI_SRAI: + status = execute_SRLI_SRAI(a, pc, insn); + goto NEXT_INSN; + SRLIW_SRAIW: + status = execute_SRLIW_SRAIW(a, pc, insn); + goto NEXT_INSN; + AMO_W: + status = execute_AMO_W(a, pc, mcycle, insn); + goto NEXT_INSN; + AMO_D: + status = execute_AMO_D(a, pc, mcycle, insn); + goto NEXT_INSN; + ADD_MUL_SUB: + status = execute_ADD_MUL_SUB(a, pc, insn); + goto NEXT_INSN; + SLL_MULH: + status = execute_SLL_MULH(a, pc, insn); + goto NEXT_INSN; + SLT_MULHSU: + status = execute_SLT_MULHSU(a, pc, insn); + goto NEXT_INSN; + SLTU_MULHU: + status = execute_SLTU_MULHU(a, pc, insn); + goto NEXT_INSN; + XOR_DIV: + status = execute_XOR_DIV(a, pc, insn); + goto NEXT_INSN; + SRL_DIVU_SRA: + status = execute_SRL_DIVU_SRA(a, pc, insn); + goto NEXT_INSN; + OR_REM: + status = execute_OR_REM(a, pc, insn); + goto NEXT_INSN; + AND_REMU: + status = execute_AND_REMU(a, pc, insn); + goto NEXT_INSN; + ADDW_MULW_SUBW: + status = execute_ADDW_MULW_SUBW(a, pc, insn); + goto NEXT_INSN; + SRLW_DIVUW_SRAW: + status = execute_SRLW_DIVUW_SRAW(a, pc, insn); + goto NEXT_INSN; + PRIVILEGED: + status = execute_privileged(a, pc, mcycle, insn); + goto NEXT_INSN; + FSW: + status = execute_FSW(a, pc, mcycle, insn); + goto NEXT_INSN; + FSD: + status = execute_FSD(a, pc, mcycle, insn); + goto NEXT_INSN; + FLW: + status = execute_FLW(a, pc, mcycle, insn); + goto NEXT_INSN; + FLD: + status = execute_FLD(a, pc, mcycle, insn); + goto NEXT_INSN; + FMADD: + status = execute_FMADD(a, pc, insn); + goto NEXT_INSN; + FMSUB: + status = execute_FMSUB(a, pc, insn); + goto NEXT_INSN; + FNMSUB: + status = execute_FNMSUB(a, pc, insn); + goto NEXT_INSN; + FNMADD: + status = execute_FNMADD(a, pc, insn); + goto NEXT_INSN; + FD: + status = execute_FD(a, pc, insn); + goto NEXT_INSN; + C_ADDI4SPN: + status = execute_C_ADDI4SPN(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_LW: + status = execute_C_LW(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_LD: + status = execute_C_LD(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_SW: + status = execute_C_SW(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_SD: + status = execute_C_SD(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_Q1_SET0: + status = execute_C_Q1_SET0(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_ADDIW: + status = execute_C_ADDIW(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_LI: + status = execute_C_LI(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_Q1_SET1: + status = execute_C_Q1_SET1(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_Q1_SET2: + status = execute_C_Q1_SET2(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_J: + status = execute_C_J(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_BEQZ: + status = execute_C_BEQZ(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_BNEZ: + status = execute_C_BNEZ(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_SLLI: + status = execute_C_SLLI(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_LWSP: + status = execute_C_LWSP(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_LDSP: + status = execute_C_LDSP(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_Q2_SET0: + status = execute_C_Q2_SET0(a, pc, static_cast(insn)); + goto NEXT_INSN; + C_SWSP: + status = execute_C_SWSP(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_SDSP: + status = execute_C_SDSP(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_FLD: + status = execute_C_FLD(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_FSD: + status = execute_C_FSD(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_FLDSP: + status = execute_C_FLDSP(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + C_FSDSP: + status = execute_C_FSDSP(a, pc, mcycle, static_cast(insn)); + goto NEXT_INSN; + ILLEGAL: + status = raise_illegal_insn_exception(a, pc, insn); + goto NEXT_INSN; + } + NEXT_INSN: // When execute status is above success, we have to deal with special loop conditions, // this is very unlikely to happen most of the time diff --git a/src/riscv-constants.h b/src/riscv-constants.h index d3132df8b..50cf8c966 100644 --- a/src/riscv-constants.h +++ b/src/riscv-constants.h @@ -630,40 +630,6 @@ enum class CSR_address : uint32_t { tdata3 = 0x7a3, }; -/// \brief The result of insn_get_c_funct3(insn) can be used to identify -/// most compressed instructions directly -enum class insn_c_funct3 : uint32_t { - // Quadrant 0 - C_ADDI4SPN = 0b000'00, - C_FLD = 0b001'00, - C_LW = 0b010'00, - C_LD = 0b011'00, - C_FSD = 0b101'00, - C_SW = 0b110'00, - C_SD = 0b111'00, - - // Quadrant 1 - C_Q1_SET0 = 0b000'01, // C_NOP and C_ADDI - C_ADDIW = 0b001'01, - C_LI = 0b010'01, - C_Q1_SET1 = 0b011'01, // C_ADDI16SP and C_LUI - C_Q1_SET2 = 0b100'01, // C_SRLI64, C_SRAI64, C_ANDI, C_SUB - // C_XOR, C_OR, C_AND, C_SUBW and C_ADDW - C_J = 0b101'01, - C_BEQZ = 0b110'01, - C_BNEZ = 0b111'01, - - // Quadrant 2 - C_SLLI = 0b000'10, - C_FLDSP = 0b001'10, - C_LWSP = 0b010'10, - C_LDSP = 0b011'10, - C_Q2_SET0 = 0b100'10, // C_JR, C_MV, C_EBREAK, C_JALR, C_ADD - C_FSDSP = 0b101'10, - C_SWSP = 0b110'10, - C_SDSP = 0b111'10, -}; - /// \brief The result of insn & 0b1110110000000011 can be used to identify /// most compressed instructions directly enum class insn_CB_funct2 : uint32_t { @@ -683,124 +649,6 @@ enum class insn_CA_funct6_funct2 : uint32_t { C_ADDW = 0b1001110000100001, }; -/// \brief The result of insn_get_funct3_opcode(insn), can be used to identify -/// most instructions directly -enum class insn_funct3_opcode : uint32_t { - LB = 0b000'0000011, - LH = 0b001'0000011, - LW = 0b010'0000011, - LD = 0b011'0000011, - LBU = 0b100'0000011, - LHU = 0b101'0000011, - LWU = 0b110'0000011, - SB = 0b000'0100011, - SH = 0b001'0100011, - SW = 0b010'0100011, - SD = 0b011'0100011, - FENCE = 0b000'0001111, - FENCE_I = 0b001'0001111, - ADDI = 0b000'0010011, - SLLI = 0b001'0010011, - SLTI = 0b010'0010011, - SLTIU = 0b011'0010011, - XORI = 0b100'0010011, - ORI = 0b110'0010011, - ANDI = 0b111'0010011, - ADDIW = 0b000'0011011, - SLLIW = 0b001'0011011, - SLLW = 0b001'0111011, - DIVW = 0b100'0111011, - REMW = 0b110'0111011, - REMUW = 0b111'0111011, - BEQ = 0b000'1100011, - BNE = 0b001'1100011, - BLT = 0b100'1100011, - BGE = 0b101'1100011, - BLTU = 0b110'1100011, - BGEU = 0b111'1100011, - JALR = 0b000'1100111, - CSRRW = 0b001'1110011, - CSRRS = 0b010'1110011, - CSRRC = 0b011'1110011, - CSRRWI = 0b101'1110011, - CSRRSI = 0b110'1110011, - CSRRCI = 0b111'1110011, - AUIPC_000 = 0b000'0010111, - AUIPC_001 = 0b001'0010111, - AUIPC_010 = 0b010'0010111, - AUIPC_011 = 0b011'0010111, - AUIPC_100 = 0b100'0010111, - AUIPC_101 = 0b101'0010111, - AUIPC_110 = 0b110'0010111, - AUIPC_111 = 0b111'0010111, - LUI_000 = 0b000'0110111, - LUI_001 = 0b001'0110111, - LUI_010 = 0b010'0110111, - LUI_011 = 0b011'0110111, - LUI_100 = 0b100'0110111, - LUI_101 = 0b101'0110111, - LUI_110 = 0b110'0110111, - LUI_111 = 0b111'0110111, - JAL_000 = 0b000'1101111, - JAL_001 = 0b001'1101111, - JAL_010 = 0b010'1101111, - JAL_011 = 0b011'1101111, - JAL_100 = 0b100'1101111, - JAL_101 = 0b101'1101111, - JAL_110 = 0b110'1101111, - JAL_111 = 0b111'1101111, - FSW = 0b010'0100111, - FSD = 0b011'0100111, - FLW = 0b010'0000111, - FLD = 0b011'0000111, - FMADD_RNE = 0b000'1000011, - FMADD_RTZ = 0b001'1000011, - FMADD_RDN = 0b010'1000011, - FMADD_RUP = 0b011'1000011, - FMADD_RMM = 0b100'1000011, - FMADD_DYN = 0b111'1000011, - FMSUB_RNE = 0b000'1000111, - FMSUB_RTZ = 0b001'1000111, - FMSUB_RDN = 0b010'1000111, - FMSUB_RUP = 0b011'1000111, - FMSUB_RMM = 0b100'1000111, - FMSUB_DYN = 0b111'1000111, - FNMSUB_RNE = 0b000'1001011, - FNMSUB_RTZ = 0b001'1001011, - FNMSUB_RDN = 0b010'1001011, - FNMSUB_RUP = 0b011'1001011, - FNMSUB_RMM = 0b100'1001011, - FNMSUB_DYN = 0b111'1001011, - FNMADD_RNE = 0b000'1001111, - FNMADD_RTZ = 0b001'1001111, - FNMADD_RDN = 0b010'1001111, - FNMADD_RUP = 0b011'1001111, - FNMADD_RMM = 0b100'1001111, - FNMADD_DYN = 0b111'1001111, - // some instructions need additional inspection of funct7 (or part thereof) - FD_000 = 0b000'1010011, - FD_001 = 0b001'1010011, - FD_010 = 0b010'1010011, - FD_011 = 0b011'1010011, - FD_100 = 0b100'1010011, - FD_111 = 0b111'1010011, - SRLI_SRAI = 0b101'0010011, - SRLIW_SRAIW = 0b101'0011011, - AMO_W = 0b010'0101111, - AMO_D = 0b011'0101111, - ADD_MUL_SUB = 0b000'0110011, - SLL_MULH = 0b001'0110011, - SLT_MULHSU = 0b010'0110011, - SLTU_MULHU = 0b011'0110011, - XOR_DIV = 0b100'0110011, - SRL_DIVU_SRA = 0b101'0110011, - OR_REM = 0b110'0110011, - AND_REMU = 0b111'0110011, - ADDW_MULW_SUBW = 0b000'0111011, - SRLW_DIVUW_SRAW = 0b101'0111011, - PRIVILEGED = 0b000'1110011, -}; - /// \brief The result of insn >> 26 (6 most significant bits of funct7) can be /// used to identify the SRI instructions enum insn_SRLI_SRAI_funct7_sr1 : uint32_t { SRLI = 0b000000, SRAI = 0b010000 };