diff --git a/src/i-virtual-machine.h b/src/i-virtual-machine.h index 3d5d2f22d..2ea1dd3cd 100644 --- a/src/i-virtual-machine.h +++ b/src/i-virtual-machine.h @@ -45,7 +45,7 @@ namespace cartesi { class i_virtual_machine { public: using hash_type = machine_merkle_tree::hash_type; - using reg = machine::reg; + using reg = machine_reg; /// \brief Constructor i_virtual_machine() = default; diff --git a/src/machine-reg.h b/src/machine-reg.h new file mode 100644 index 000000000..3774915c3 --- /dev/null +++ b/src/machine-reg.h @@ -0,0 +1,192 @@ +// Copyright Cartesi and individual authors (see AUTHORS) +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// This program is free software: you can redistribute it and/or modify it under +// the terms of the GNU Lesser General Public License as published by the Free +// Software Foundation, either version 3 of the License, or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +// PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public License along +// with this program (see COPYING). If not, see . +// + +#ifndef MACHINE_REG_H +#define MACHINE_REG_H + +/// \file +/// \brief Cartesi machine registers + +namespace cartesi { + +/// \brief List of machine registers +enum class machine_reg { + // Processor x registers + first_ = 0, + x0 = first_, + x1, + x2, + x3, + x4, + x5, + x6, + x7, + x8, + x9, + x10, + x11, + x12, + x13, + x14, + x15, + x16, + x17, + x18, + x19, + x20, + x21, + x22, + x23, + x24, + x25, + x26, + x27, + x28, + x29, + x30, + x31, + // Processor f registers + f0, + f1, + f2, + f3, + f4, + f5, + f6, + f7, + f8, + f9, + f10, + f11, + f12, + f13, + f14, + f15, + f16, + f17, + f18, + f19, + f20, + f21, + f22, + f23, + f24, + f25, + f26, + f27, + f28, + f29, + f30, + f31, + // Processor CSRs + pc, + fcsr, + mvendorid, + marchid, + mimpid, + mcycle, + icycleinstret, + mstatus, + mtvec, + mscratch, + mepc, + mcause, + mtval, + misa, + mie, + mip, + medeleg, + mideleg, + mcounteren, + menvcfg, + stvec, + sscratch, + sepc, + scause, + stval, + satp, + scounteren, + senvcfg, + ilrsc, + iflags, + iunrep, + clint_mtimecmp, + plic_girqpend, + plic_girqsrvd, + htif_tohost, + htif_fromhost, + htif_ihalt, + htif_iconsole, + htif_iyield, + last_ = htif_iyield, + // Microarchitecture processor + uarch_first_, + uarch_x0 = uarch_first_, + uarch_x1, + uarch_x2, + uarch_x3, + uarch_x4, + uarch_x5, + uarch_x6, + uarch_x7, + uarch_x8, + uarch_x9, + uarch_x10, + uarch_x11, + uarch_x12, + uarch_x13, + uarch_x14, + uarch_x15, + uarch_x16, + uarch_x17, + uarch_x18, + uarch_x19, + uarch_x20, + uarch_x21, + uarch_x22, + uarch_x23, + uarch_x24, + uarch_x25, + uarch_x26, + uarch_x27, + uarch_x28, + uarch_x29, + uarch_x30, + uarch_x31, + uarch_pc, + uarch_cycle, + uarch_halt_flag, + uarch_last_ = uarch_halt_flag, + count_, + // Views of registers + iflags_prv, + iflags_x, + iflags_y, + iflags_h, + htif_tohost_dev, + htif_tohost_cmd, + htif_tohost_reason, + htif_tohost_data, + htif_fromhost_dev, + htif_fromhost_cmd, + htif_fromhost_reason, + htif_fromhost_data, + unknown_, +}; + +} // namespace cartesi + +#endif // MACHINE_REG_H diff --git a/src/machine.cpp b/src/machine.cpp index 715e85775..7b2353fc9 100644 --- a/src/machine.cpp +++ b/src/machine.cpp @@ -306,12 +306,12 @@ machine::machine(const machine_config &c, const machine_runtime_config &r) : m_c // General purpose registers for (int i = 1; i < X_REG_COUNT; i++) { - write_reg(static_cast(reg::x0 + i), m_c.processor.x[i]); + write_reg(static_cast(static_cast(reg::x0) + i), m_c.processor.x[i]); } // Floating-point registers for (int i = 0; i < F_REG_COUNT; i++) { - write_reg(static_cast(reg::f0 + i), m_c.processor.f[i]); + write_reg(static_cast(static_cast(reg::f0) + i), m_c.processor.f[i]); } write_reg(reg::pc, m_c.processor.pc); @@ -633,10 +633,10 @@ machine_config machine::get_serialization_config() const { machine_config c = m_c; // Copy current processor state to config for (int i = 1; i < X_REG_COUNT; ++i) { - c.processor.x[i] = read_reg(static_cast(reg::x0 + i)); + c.processor.x[i] = read_reg(static_cast(static_cast(reg::x0) + i)); } for (int i = 0; i < F_REG_COUNT; ++i) { - c.processor.f[i] = read_reg(static_cast(reg::f0 + i)); + c.processor.f[i] = read_reg(static_cast(static_cast(reg::f0) + i)); } c.processor.pc = read_reg(reg::pc); c.processor.fcsr = read_reg(reg::fcsr); @@ -699,7 +699,7 @@ machine_config machine::get_serialization_config() const { c.uarch.processor.halt_flag = (read_reg(reg::uarch_halt_flag) != 0); c.uarch.processor.pc = read_reg(reg::uarch_pc); for (int i = 1; i < UARCH_X_REG_COUNT; i++) { - c.uarch.processor.x[i] = read_reg(static_cast(reg::uarch_x0 + i)); + c.uarch.processor.x[i] = read_reg(static_cast(static_cast(reg::uarch_x0) + i)); } return c; } @@ -1642,286 +1642,14 @@ void machine::write_reg(reg w, uint64_t value) { } uint64_t machine::get_reg_address(reg r) { - switch (r) { - case reg::x0: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x0); - case reg::x1: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x1); - case reg::x2: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x2); - case reg::x3: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x3); - case reg::x4: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x4); - case reg::x5: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x5); - case reg::x6: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x6); - case reg::x7: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x7); - case reg::x8: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x8); - case reg::x9: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x9); - case reg::x10: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x10); - case reg::x11: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x11); - case reg::x12: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x12); - case reg::x13: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x13); - case reg::x14: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x14); - case reg::x15: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x15); - case reg::x16: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x16); - case reg::x17: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x17); - case reg::x18: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x18); - case reg::x19: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x19); - case reg::x20: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x20); - case reg::x21: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x21); - case reg::x22: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x22); - case reg::x23: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x23); - case reg::x24: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x24); - case reg::x25: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x25); - case reg::x26: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x26); - case reg::x27: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x27); - case reg::x28: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x28); - case reg::x29: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x29); - case reg::x30: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x30); - case reg::x31: - return shadow_state_get_reg_abs_addr(shadow_state_reg::x31); - case reg::f0: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f0); - case reg::f1: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f1); - case reg::f2: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f2); - case reg::f3: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f3); - case reg::f4: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f4); - case reg::f5: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f5); - case reg::f6: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f6); - case reg::f7: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f7); - case reg::f8: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f8); - case reg::f9: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f9); - case reg::f10: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f10); - case reg::f11: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f11); - case reg::f12: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f12); - case reg::f13: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f13); - case reg::f14: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f14); - case reg::f15: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f15); - case reg::f16: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f16); - case reg::f17: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f17); - case reg::f18: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f18); - case reg::f19: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f19); - case reg::f20: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f20); - case reg::f21: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f21); - case reg::f22: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f22); - case reg::f23: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f23); - case reg::f24: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f24); - case reg::f25: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f25); - case reg::f26: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f26); - case reg::f27: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f27); - case reg::f28: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f28); - case reg::f29: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f29); - case reg::f30: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f30); - case reg::f31: - return shadow_state_get_reg_abs_addr(shadow_state_reg::f31); - case reg::pc: - return shadow_state_get_reg_abs_addr(shadow_state_reg::pc); - case reg::fcsr: - return shadow_state_get_reg_abs_addr(shadow_state_reg::fcsr); - case reg::mvendorid: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mvendorid); - case reg::marchid: - return shadow_state_get_reg_abs_addr(shadow_state_reg::marchid); - case reg::mimpid: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mimpid); - case reg::mcycle: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mcycle); - case reg::icycleinstret: - return shadow_state_get_reg_abs_addr(shadow_state_reg::icycleinstret); - case reg::mstatus: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mstatus); - case reg::mtvec: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mtvec); - case reg::mscratch: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mscratch); - case reg::mepc: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mepc); - case reg::mcause: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mcause); - case reg::mtval: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mtval); - case reg::misa: - return shadow_state_get_reg_abs_addr(shadow_state_reg::misa); - case reg::mie: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mie); - case reg::mip: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mip); - case reg::medeleg: - return shadow_state_get_reg_abs_addr(shadow_state_reg::medeleg); - case reg::mideleg: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mideleg); - case reg::mcounteren: - return shadow_state_get_reg_abs_addr(shadow_state_reg::mcounteren); - case reg::menvcfg: - return shadow_state_get_reg_abs_addr(shadow_state_reg::menvcfg); - case reg::stvec: - return shadow_state_get_reg_abs_addr(shadow_state_reg::stvec); - case reg::sscratch: - return shadow_state_get_reg_abs_addr(shadow_state_reg::sscratch); - case reg::sepc: - return shadow_state_get_reg_abs_addr(shadow_state_reg::sepc); - case reg::scause: - return shadow_state_get_reg_abs_addr(shadow_state_reg::scause); - case reg::stval: - return shadow_state_get_reg_abs_addr(shadow_state_reg::stval); - case reg::satp: - return shadow_state_get_reg_abs_addr(shadow_state_reg::satp); - case reg::scounteren: - return shadow_state_get_reg_abs_addr(shadow_state_reg::scounteren); - case reg::senvcfg: - return shadow_state_get_reg_abs_addr(shadow_state_reg::senvcfg); - case reg::ilrsc: - return shadow_state_get_reg_abs_addr(shadow_state_reg::ilrsc); - case reg::iflags: - return shadow_state_get_reg_abs_addr(shadow_state_reg::iflags); - case reg::iunrep: - return shadow_state_get_reg_abs_addr(shadow_state_reg::iunrep); - case reg::htif_tohost: - return shadow_state_get_reg_abs_addr(shadow_state_reg::htif_tohost); - case reg::htif_fromhost: - return shadow_state_get_reg_abs_addr(shadow_state_reg::htif_fromhost); - case reg::htif_ihalt: - return shadow_state_get_reg_abs_addr(shadow_state_reg::htif_ihalt); - case reg::htif_iconsole: - return shadow_state_get_reg_abs_addr(shadow_state_reg::htif_iconsole); - case reg::htif_iyield: - return shadow_state_get_reg_abs_addr(shadow_state_reg::htif_iyield); - case reg::clint_mtimecmp: - return shadow_state_get_reg_abs_addr(shadow_state_reg::clint_mtimecmp); - case reg::plic_girqpend: - return shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqpend); - case reg::plic_girqsrvd: - return shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqsrvd); - case reg::uarch_x0: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x0); - case reg::uarch_x1: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x1); - case reg::uarch_x2: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x2); - case reg::uarch_x3: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x3); - case reg::uarch_x4: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x4); - case reg::uarch_x5: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x5); - case reg::uarch_x6: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x6); - case reg::uarch_x7: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x7); - case reg::uarch_x8: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x8); - case reg::uarch_x9: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x9); - case reg::uarch_x10: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x10); - case reg::uarch_x11: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x11); - case reg::uarch_x12: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x12); - case reg::uarch_x13: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x13); - case reg::uarch_x14: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x14); - case reg::uarch_x15: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x15); - case reg::uarch_x16: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x16); - case reg::uarch_x17: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x17); - case reg::uarch_x18: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x18); - case reg::uarch_x19: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x19); - case reg::uarch_x20: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x20); - case reg::uarch_x21: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x21); - case reg::uarch_x22: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x22); - case reg::uarch_x23: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x23); - case reg::uarch_x24: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x24); - case reg::uarch_x25: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x25); - case reg::uarch_x26: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x26); - case reg::uarch_x27: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x27); - case reg::uarch_x28: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x28); - case reg::uarch_x29: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x29); - case reg::uarch_x30: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x30); - case reg::uarch_x31: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::x31); - case reg::uarch_pc: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::pc); - case reg::uarch_cycle: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::cycle); - case reg::uarch_halt_flag: - return shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::halt_flag); - default: - throw std::invalid_argument{"unknown register"}; + if (static_cast(r) >= static_cast(reg::uarch_first_) && + static_cast(r) <= static_cast(reg::uarch_last_)) { + return shadow_uarch_state_get_reg_abs_addr(r); + } + if (static_cast(r) >= static_cast(reg::first_) && static_cast(r) <= static_cast(reg::last_)) { + return shadow_state_get_reg_abs_addr(r); } + throw std::domain_error{"invalid register"}; } void machine::mark_write_tlb_dirty_pages() const { diff --git a/src/machine.h b/src/machine.h index 859905149..2c500d33c 100644 --- a/src/machine.h +++ b/src/machine.h @@ -33,6 +33,7 @@ #include "machine-config.h" #include "machine-memory-range-descr.h" #include "machine-merkle-tree.h" +#include "machine-reg.h" #include "machine-runtime-config.h" #include "machine-state.h" #include "os.h" @@ -128,168 +129,7 @@ class machine final { /// \brief Type of hash using hash_type = machine_merkle_tree::hash_type; - /// \brief List of register to use with read_reg and write_reg - enum reg { - // Processor x registers - x0 = 0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - // Processor f registers - f0, - f1, - f2, - f3, - f4, - f5, - f6, - f7, - f8, - f9, - f10, - f11, - f12, - f13, - f14, - f15, - f16, - f17, - f18, - f19, - f20, - f21, - f22, - f23, - f24, - f25, - f26, - f27, - f28, - f29, - f30, - f31, - // Processor CSRs - pc, - fcsr, - mvendorid, - marchid, - mimpid, - mcycle, - icycleinstret, - mstatus, - mtvec, - mscratch, - mepc, - mcause, - mtval, - misa, - mie, - mip, - medeleg, - mideleg, - mcounteren, - menvcfg, - stvec, - sscratch, - sepc, - scause, - stval, - satp, - scounteren, - senvcfg, - ilrsc, - iflags, - iunrep, - clint_mtimecmp, - plic_girqpend, - plic_girqsrvd, - htif_tohost, - htif_fromhost, - htif_ihalt, - htif_iconsole, - htif_iyield, - // Microarchitecture processor - uarch_x0, - uarch_x1, - uarch_x2, - uarch_x3, - uarch_x4, - uarch_x5, - uarch_x6, - uarch_x7, - uarch_x8, - uarch_x9, - uarch_x10, - uarch_x11, - uarch_x12, - uarch_x13, - uarch_x14, - uarch_x15, - uarch_x16, - uarch_x17, - uarch_x18, - uarch_x19, - uarch_x20, - uarch_x21, - uarch_x22, - uarch_x23, - uarch_x24, - uarch_x25, - uarch_x26, - uarch_x27, - uarch_x28, - uarch_x29, - uarch_x30, - uarch_x31, - uarch_pc, - uarch_cycle, - uarch_halt_flag, - last, - // Views of registers - iflags_prv, - iflags_x, - iflags_y, - iflags_h, - htif_tohost_dev, - htif_tohost_cmd, - htif_tohost_reason, - htif_tohost_data, - htif_fromhost_dev, - htif_fromhost_cmd, - htif_fromhost_reason, - htif_fromhost_data, - unknown, - }; - - static constexpr auto num_reg = static_cast(reg::last); + using reg = machine_reg; /// \brief Constructor from machine configuration /// \param config Machine config to use instantiating machine diff --git a/src/record-state-access.h b/src/record-state-access.h index fcc0800dd..7dabf9a51 100644 --- a/src/record-state-access.h +++ b/src/record-state-access.h @@ -202,7 +202,7 @@ class record_state_access : public i_state_access(m_m.get_state().iflags.X), 0 /* Y */, static_cast(m_m.get_state().iflags.H)); - const uint64_t iflags_addr = shadow_state_get_reg_abs_addr(shadow_state_reg::iflags); + const uint64_t iflags_addr = shadow_state_get_reg_abs_addr(machine_reg::iflags); log_read(iflags_addr, "iflags.Y"); log_before_write(iflags_addr, new_iflags, "iflags.Y"); m_m.get_state().iflags.Y = false; @@ -210,12 +210,12 @@ class record_state_access : public i_state_access(shadow_state_get_reg_abs_addr(shadow_state_reg::pc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::pc)); } void do_write_pc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::pc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::pc), val); } uint64_t do_read_fcsr() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::fcsr)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr)); } void do_write_fcsr(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::fcsr), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr), val); } uint64_t do_read_icycleinstret() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::icycleinstret)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret)); } void do_write_icycleinstret(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::icycleinstret), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret), val); } uint64_t do_read_mvendorid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mvendorid)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mvendorid)); } uint64_t do_read_marchid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::marchid)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::marchid)); } uint64_t do_read_mimpid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mimpid)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mimpid)); } uint64_t do_read_mcycle() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcycle)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle)); } void do_write_mcycle(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcycle), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle), val); } uint64_t do_read_mstatus() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mstatus)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus)); } void do_write_mstatus(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mstatus), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus), val); } uint64_t do_read_mtvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtvec)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec)); } void do_write_mtvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtvec), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec), val); } uint64_t do_read_mscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mscratch)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch)); } void do_write_mscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mscratch), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch), val); } uint64_t do_read_mepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mepc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc)); } void do_write_mepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mepc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc), val); } uint64_t do_read_mcause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcause)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause)); } void do_write_mcause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcause), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause), val); } uint64_t do_read_mtval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtval)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval)); } void do_write_mtval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtval), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval), val); } uint64_t do_read_misa() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::misa)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::misa)); } void do_write_misa(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::misa), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::misa), val); } uint64_t do_read_mie() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mie)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mie)); } void do_write_mie(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mie), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mie), val); } uint64_t do_read_mip() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mip)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mip)); } void do_write_mip(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mip), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mip), val); } uint64_t do_read_medeleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::medeleg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg)); } void do_write_medeleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::medeleg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg), val); } uint64_t do_read_mideleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mideleg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg)); } void do_write_mideleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mideleg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg), val); } uint64_t do_read_mcounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcounteren)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren)); } void do_write_mcounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcounteren), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren), val); } uint64_t do_read_senvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::senvcfg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg)); } void do_write_senvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::senvcfg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg), val); } uint64_t do_read_menvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::menvcfg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg)); } void do_write_menvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::menvcfg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg), val); } uint64_t do_read_stvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stvec)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec)); } void do_write_stvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stvec), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec), val); } uint64_t do_read_sscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sscratch)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch)); } void do_write_sscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sscratch), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch), val); } uint64_t do_read_sepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sepc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc)); } void do_write_sepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sepc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc), val); } uint64_t do_read_scause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scause)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scause)); } void do_write_scause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scause), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scause), val); } uint64_t do_read_stval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stval)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stval)); } void do_write_stval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stval), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stval), val); } uint64_t do_read_satp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::satp)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::satp)); } void do_write_satp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::satp), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::satp), val); } uint64_t do_read_scounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scounteren)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren)); } void do_write_scounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scounteren), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren), val); } uint64_t do_read_ilrsc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::ilrsc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc)); } void do_write_ilrsc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::ilrsc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc), val); } uint64_t do_read_iflags() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::iflags)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags)); } void do_write_iflags(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::iflags), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags), val); } void do_set_iflags_H() { @@ -788,63 +788,63 @@ class replay_step_state_access : public i_state_access(shadow_state_get_reg_abs_addr(shadow_state_reg::iunrep)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::iunrep)); } void do_write_iunrep(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::iunrep), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iunrep), val); } uint64_t do_read_clint_mtimecmp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::clint_mtimecmp)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp)); } void do_write_clint_mtimecmp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::clint_mtimecmp), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp), val); } uint64_t do_read_plic_girqpend() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqpend)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend)); } void do_write_plic_girqpend(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqpend), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend), val); } uint64_t do_read_plic_girqsrvd() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqsrvd)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd)); } void do_write_plic_girqsrvd(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqsrvd), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd), val); } uint64_t do_read_htif_fromhost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_fromhost)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost)); } void do_write_htif_fromhost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_fromhost), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost), val); } uint64_t do_read_htif_tohost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_tohost)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost)); } void do_write_htif_tohost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_tohost), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost), val); } uint64_t do_read_htif_ihalt() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_ihalt)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_ihalt)); } uint64_t do_read_htif_iconsole() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_iconsole)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iconsole)); } uint64_t do_read_htif_iyield() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_iyield)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iyield)); } // NOLINTNEXTLINE(readability-convert-member-functions-to-static) diff --git a/src/shadow-state-factory.cpp b/src/shadow-state-factory.cpp index 2739d279e..2eaa53faa 100644 --- a/src/shadow-state-factory.cpp +++ b/src/shadow-state-factory.cpp @@ -46,52 +46,52 @@ static bool shadow_state_peek(const pma_entry & /*pma*/, const machine &m, uint6 // Copy general-purpose registers for (int i = 0; i < X_REG_COUNT; ++i) { - s->x[i] = m.read_reg(static_cast(machine::reg::x0 + i)); + s->x[i] = m.read_reg(static_cast(static_cast(machine_reg::x0) + i)); } // Copy floating-point registers for (int i = 0; i < F_REG_COUNT; ++i) { - s->f[i] = m.read_reg(static_cast(machine::reg::f0 + i)); + s->f[i] = m.read_reg(static_cast(static_cast(machine_reg::f0) + i)); } // Copy named registers - s->pc = m.read_reg(machine::reg::pc); - s->fcsr = m.read_reg(machine::reg::fcsr); - s->mvendorid = m.read_reg(machine::reg::mvendorid); - s->marchid = m.read_reg(machine::reg::marchid); - s->mimpid = m.read_reg(machine::reg::mimpid); - s->mcycle = m.read_reg(machine::reg::mcycle); - s->icycleinstret = m.read_reg(machine::reg::icycleinstret); - s->mstatus = m.read_reg(machine::reg::mstatus); - s->mtvec = m.read_reg(machine::reg::mtvec); - s->mscratch = m.read_reg(machine::reg::mscratch); - s->mepc = m.read_reg(machine::reg::mepc); - s->mcause = m.read_reg(machine::reg::mcause); - s->mtval = m.read_reg(machine::reg::mtval); - s->misa = m.read_reg(machine::reg::misa); - s->mie = m.read_reg(machine::reg::mie); - s->mip = m.read_reg(machine::reg::mip); - s->medeleg = m.read_reg(machine::reg::medeleg); - s->mideleg = m.read_reg(machine::reg::mideleg); - s->mcounteren = m.read_reg(machine::reg::mcounteren); - s->menvcfg = m.read_reg(machine::reg::menvcfg); - s->stvec = m.read_reg(machine::reg::stvec); - s->sscratch = m.read_reg(machine::reg::sscratch); - s->sepc = m.read_reg(machine::reg::sepc); - s->scause = m.read_reg(machine::reg::scause); - s->stval = m.read_reg(machine::reg::stval); - s->satp = m.read_reg(machine::reg::satp); - s->scounteren = m.read_reg(machine::reg::scounteren); - s->senvcfg = m.read_reg(machine::reg::senvcfg); - s->ilrsc = m.read_reg(machine::reg::ilrsc); - s->iflags = m.read_reg(machine::reg::iflags); - s->iunrep = m.read_reg(machine::reg::iunrep); - s->clint_mtimecmp = m.read_reg(machine::reg::clint_mtimecmp); - s->plic_girqpend = m.read_reg(machine::reg::plic_girqpend); - s->plic_girqsrvd = m.read_reg(machine::reg::plic_girqsrvd); - s->htif_tohost = m.read_reg(machine::reg::htif_tohost); - s->htif_fromhost = m.read_reg(machine::reg::htif_fromhost); - s->htif_ihalt = m.read_reg(machine::reg::htif_ihalt); - s->htif_iconsole = m.read_reg(machine::reg::htif_iconsole); - s->htif_iyield = m.read_reg(machine::reg::htif_iyield); + s->pc = m.read_reg(machine_reg::pc); + s->fcsr = m.read_reg(machine_reg::fcsr); + s->mvendorid = m.read_reg(machine_reg::mvendorid); + s->marchid = m.read_reg(machine_reg::marchid); + s->mimpid = m.read_reg(machine_reg::mimpid); + s->mcycle = m.read_reg(machine_reg::mcycle); + s->icycleinstret = m.read_reg(machine_reg::icycleinstret); + s->mstatus = m.read_reg(machine_reg::mstatus); + s->mtvec = m.read_reg(machine_reg::mtvec); + s->mscratch = m.read_reg(machine_reg::mscratch); + s->mepc = m.read_reg(machine_reg::mepc); + s->mcause = m.read_reg(machine_reg::mcause); + s->mtval = m.read_reg(machine_reg::mtval); + s->misa = m.read_reg(machine_reg::misa); + s->mie = m.read_reg(machine_reg::mie); + s->mip = m.read_reg(machine_reg::mip); + s->medeleg = m.read_reg(machine_reg::medeleg); + s->mideleg = m.read_reg(machine_reg::mideleg); + s->mcounteren = m.read_reg(machine_reg::mcounteren); + s->menvcfg = m.read_reg(machine_reg::menvcfg); + s->stvec = m.read_reg(machine_reg::stvec); + s->sscratch = m.read_reg(machine_reg::sscratch); + s->sepc = m.read_reg(machine_reg::sepc); + s->scause = m.read_reg(machine_reg::scause); + s->stval = m.read_reg(machine_reg::stval); + s->satp = m.read_reg(machine_reg::satp); + s->scounteren = m.read_reg(machine_reg::scounteren); + s->senvcfg = m.read_reg(machine_reg::senvcfg); + s->ilrsc = m.read_reg(machine_reg::ilrsc); + s->iflags = m.read_reg(machine_reg::iflags); + s->iunrep = m.read_reg(machine_reg::iunrep); + s->clint_mtimecmp = m.read_reg(machine_reg::clint_mtimecmp); + s->plic_girqpend = m.read_reg(machine_reg::plic_girqpend); + s->plic_girqsrvd = m.read_reg(machine_reg::plic_girqsrvd); + s->htif_tohost = m.read_reg(machine_reg::htif_tohost); + s->htif_fromhost = m.read_reg(machine_reg::htif_fromhost); + s->htif_ihalt = m.read_reg(machine_reg::htif_ihalt); + s->htif_iconsole = m.read_reg(machine_reg::htif_iconsole); + s->htif_iyield = m.read_reg(machine_reg::htif_iyield); *page_data = scratch; return true; } diff --git a/src/shadow-state.h b/src/shadow-state.h index 96b85b57f..ad9396d14 100644 --- a/src/shadow-state.h +++ b/src/shadow-state.h @@ -22,6 +22,7 @@ #include #include "compiler-defines.h" +#include "machine-reg.h" #include "pma-constants.h" #include "pma-driver.h" #include "riscv-constants.h" @@ -80,7 +81,7 @@ struct PACKED shadow_state { extern const pma_driver shadow_state_driver; /// \brief Mapping between registers and their relative addresses in shadow memory -enum class shadow_state_reg { +enum class shadow_state_reg_rel_addr : uint64_t { x0 = offsetof(shadow_state, x[0]), x1 = offsetof(shadow_state, x[1]), x2 = offsetof(shadow_state, x[2]), @@ -186,18 +187,6 @@ enum class shadow_state_reg { htif_iyield = offsetof(shadow_state, htif_iyield), }; -/// \brief Obtains the relative address of a register in shadow memory. -/// \param reg Register name. -/// \returns The address. -constexpr uint64_t shadow_state_get_reg_rel_addr(shadow_state_reg reg) { - return static_cast(reg); -} - -/// \brief Obtains the absolute address of a register in shadow memory. -constexpr uint64_t shadow_state_get_reg_abs_addr(shadow_state_reg reg) { - return PMA_SHADOW_STATE_START + shadow_state_get_reg_rel_addr(reg); -} - /// \brief Obtains the relative address of a general purpose register /// in shadow memory. /// \param reg Register index in 0...31, for x0...x31, respectively. @@ -207,16 +196,242 @@ static inline uint64_t shadow_state_get_x_rel_addr(int reg) { return offsetof(shadow_state, x) + reg * sizeof(uint64_t); } -/// \brief Obtains the absolute address of a general purpose register -static inline uint64_t shadow_state_get_x_abs_addr(int reg) { - return PMA_SHADOW_STATE_START + shadow_state_get_x_rel_addr(reg); -} /// \brief Obtains the relative address of a floating-point register static inline uint64_t shadow_state_get_f_rel_addr(int reg) { assert(reg >= 0 && reg < F_REG_COUNT); return offsetof(shadow_state, f) + reg * sizeof(uint64_t); } +/// \brief Obtains the relative address of a register in shadow memory. +/// \param r Register name. +/// \returns The address. +static inline uint64_t shadow_state_get_reg_rel_addr(machine_reg r) { + using reg = machine_reg; + switch (r) { + case reg::x0: + return static_cast(shadow_state_reg_rel_addr::x0); + case reg::x1: + return static_cast(shadow_state_reg_rel_addr::x1); + case reg::x2: + return static_cast(shadow_state_reg_rel_addr::x2); + case reg::x3: + return static_cast(shadow_state_reg_rel_addr::x3); + case reg::x4: + return static_cast(shadow_state_reg_rel_addr::x4); + case reg::x5: + return static_cast(shadow_state_reg_rel_addr::x5); + case reg::x6: + return static_cast(shadow_state_reg_rel_addr::x6); + case reg::x7: + return static_cast(shadow_state_reg_rel_addr::x7); + case reg::x8: + return static_cast(shadow_state_reg_rel_addr::x8); + case reg::x9: + return static_cast(shadow_state_reg_rel_addr::x9); + case reg::x10: + return static_cast(shadow_state_reg_rel_addr::x10); + case reg::x11: + return static_cast(shadow_state_reg_rel_addr::x11); + case reg::x12: + return static_cast(shadow_state_reg_rel_addr::x12); + case reg::x13: + return static_cast(shadow_state_reg_rel_addr::x13); + case reg::x14: + return static_cast(shadow_state_reg_rel_addr::x14); + case reg::x15: + return static_cast(shadow_state_reg_rel_addr::x15); + case reg::x16: + return static_cast(shadow_state_reg_rel_addr::x16); + case reg::x17: + return static_cast(shadow_state_reg_rel_addr::x17); + case reg::x18: + return static_cast(shadow_state_reg_rel_addr::x18); + case reg::x19: + return static_cast(shadow_state_reg_rel_addr::x19); + case reg::x20: + return static_cast(shadow_state_reg_rel_addr::x20); + case reg::x21: + return static_cast(shadow_state_reg_rel_addr::x21); + case reg::x22: + return static_cast(shadow_state_reg_rel_addr::x22); + case reg::x23: + return static_cast(shadow_state_reg_rel_addr::x23); + case reg::x24: + return static_cast(shadow_state_reg_rel_addr::x24); + case reg::x25: + return static_cast(shadow_state_reg_rel_addr::x25); + case reg::x26: + return static_cast(shadow_state_reg_rel_addr::x26); + case reg::x27: + return static_cast(shadow_state_reg_rel_addr::x27); + case reg::x28: + return static_cast(shadow_state_reg_rel_addr::x28); + case reg::x29: + return static_cast(shadow_state_reg_rel_addr::x29); + case reg::x30: + return static_cast(shadow_state_reg_rel_addr::x30); + case reg::x31: + return static_cast(shadow_state_reg_rel_addr::x31); + case reg::f0: + return static_cast(shadow_state_reg_rel_addr::f0); + case reg::f1: + return static_cast(shadow_state_reg_rel_addr::f1); + case reg::f2: + return static_cast(shadow_state_reg_rel_addr::f2); + case reg::f3: + return static_cast(shadow_state_reg_rel_addr::f3); + case reg::f4: + return static_cast(shadow_state_reg_rel_addr::f4); + case reg::f5: + return static_cast(shadow_state_reg_rel_addr::f5); + case reg::f6: + return static_cast(shadow_state_reg_rel_addr::f6); + case reg::f7: + return static_cast(shadow_state_reg_rel_addr::f7); + case reg::f8: + return static_cast(shadow_state_reg_rel_addr::f8); + case reg::f9: + return static_cast(shadow_state_reg_rel_addr::f9); + case reg::f10: + return static_cast(shadow_state_reg_rel_addr::f10); + case reg::f11: + return static_cast(shadow_state_reg_rel_addr::f11); + case reg::f12: + return static_cast(shadow_state_reg_rel_addr::f12); + case reg::f13: + return static_cast(shadow_state_reg_rel_addr::f13); + case reg::f14: + return static_cast(shadow_state_reg_rel_addr::f14); + case reg::f15: + return static_cast(shadow_state_reg_rel_addr::f15); + case reg::f16: + return static_cast(shadow_state_reg_rel_addr::f16); + case reg::f17: + return static_cast(shadow_state_reg_rel_addr::f17); + case reg::f18: + return static_cast(shadow_state_reg_rel_addr::f18); + case reg::f19: + return static_cast(shadow_state_reg_rel_addr::f19); + case reg::f20: + return static_cast(shadow_state_reg_rel_addr::f20); + case reg::f21: + return static_cast(shadow_state_reg_rel_addr::f21); + case reg::f22: + return static_cast(shadow_state_reg_rel_addr::f22); + case reg::f23: + return static_cast(shadow_state_reg_rel_addr::f23); + case reg::f24: + return static_cast(shadow_state_reg_rel_addr::f24); + case reg::f25: + return static_cast(shadow_state_reg_rel_addr::f25); + case reg::f26: + return static_cast(shadow_state_reg_rel_addr::f26); + case reg::f27: + return static_cast(shadow_state_reg_rel_addr::f27); + case reg::f28: + return static_cast(shadow_state_reg_rel_addr::f28); + case reg::f29: + return static_cast(shadow_state_reg_rel_addr::f29); + case reg::f30: + return static_cast(shadow_state_reg_rel_addr::f30); + case reg::f31: + return static_cast(shadow_state_reg_rel_addr::f31); + case reg::pc: + return static_cast(shadow_state_reg_rel_addr::pc); + case reg::fcsr: + return static_cast(shadow_state_reg_rel_addr::fcsr); + case reg::mvendorid: + return static_cast(shadow_state_reg_rel_addr::mvendorid); + case reg::marchid: + return static_cast(shadow_state_reg_rel_addr::marchid); + case reg::mimpid: + return static_cast(shadow_state_reg_rel_addr::mimpid); + case reg::mcycle: + return static_cast(shadow_state_reg_rel_addr::mcycle); + case reg::icycleinstret: + return static_cast(shadow_state_reg_rel_addr::icycleinstret); + case reg::mstatus: + return static_cast(shadow_state_reg_rel_addr::mstatus); + case reg::mtvec: + return static_cast(shadow_state_reg_rel_addr::mtvec); + case reg::mscratch: + return static_cast(shadow_state_reg_rel_addr::mscratch); + case reg::mepc: + return static_cast(shadow_state_reg_rel_addr::mepc); + case reg::mcause: + return static_cast(shadow_state_reg_rel_addr::mcause); + case reg::mtval: + return static_cast(shadow_state_reg_rel_addr::mtval); + case reg::misa: + return static_cast(shadow_state_reg_rel_addr::misa); + case reg::mie: + return static_cast(shadow_state_reg_rel_addr::mie); + case reg::mip: + return static_cast(shadow_state_reg_rel_addr::mip); + case reg::medeleg: + return static_cast(shadow_state_reg_rel_addr::medeleg); + case reg::mideleg: + return static_cast(shadow_state_reg_rel_addr::mideleg); + case reg::mcounteren: + return static_cast(shadow_state_reg_rel_addr::mcounteren); + case reg::menvcfg: + return static_cast(shadow_state_reg_rel_addr::menvcfg); + case reg::stvec: + return static_cast(shadow_state_reg_rel_addr::stvec); + case reg::sscratch: + return static_cast(shadow_state_reg_rel_addr::sscratch); + case reg::sepc: + return static_cast(shadow_state_reg_rel_addr::sepc); + case reg::scause: + return static_cast(shadow_state_reg_rel_addr::scause); + case reg::stval: + return static_cast(shadow_state_reg_rel_addr::stval); + case reg::satp: + return static_cast(shadow_state_reg_rel_addr::satp); + case reg::scounteren: + return static_cast(shadow_state_reg_rel_addr::scounteren); + case reg::senvcfg: + return static_cast(shadow_state_reg_rel_addr::senvcfg); + case reg::ilrsc: + return static_cast(shadow_state_reg_rel_addr::ilrsc); + case reg::iflags: + return static_cast(shadow_state_reg_rel_addr::iflags); + case reg::iunrep: + return static_cast(shadow_state_reg_rel_addr::iunrep); + case reg::clint_mtimecmp: + return static_cast(shadow_state_reg_rel_addr::clint_mtimecmp); + case reg::plic_girqpend: + return static_cast(shadow_state_reg_rel_addr::plic_girqpend); + case reg::plic_girqsrvd: + return static_cast(shadow_state_reg_rel_addr::plic_girqsrvd); + case reg::htif_tohost: + return static_cast(shadow_state_reg_rel_addr::htif_tohost); + case reg::htif_fromhost: + return static_cast(shadow_state_reg_rel_addr::htif_fromhost); + case reg::htif_ihalt: + return static_cast(shadow_state_reg_rel_addr::htif_ihalt); + case reg::htif_iconsole: + return static_cast(shadow_state_reg_rel_addr::htif_iconsole); + case reg::htif_iyield: + return static_cast(shadow_state_reg_rel_addr::htif_iyield); + default: + assert(0); + return 0; + } +} + +/// \brief Obtains the absolute address of a register in shadow memory. +/// \param r Register name. +/// \returns The address. +static inline uint64_t shadow_state_get_reg_abs_addr(machine_reg r) { + return PMA_SHADOW_STATE_START + shadow_state_get_reg_rel_addr(r); +} + +/// \brief Obtains the absolute address of a general purpose register +static inline uint64_t shadow_state_get_x_abs_addr(int reg) { + return PMA_SHADOW_STATE_START + shadow_state_get_x_rel_addr(reg); +} + /// \brief Obtains the absolute address of a floating-point register static inline uint64_t shadow_state_get_f_abs_addr(int reg) { return PMA_SHADOW_STATE_START + shadow_state_get_f_rel_addr(reg); diff --git a/src/shadow-uarch-state-factory.cpp b/src/shadow-uarch-state-factory.cpp index bf4659dbe..00ec433fb 100644 --- a/src/shadow-uarch-state-factory.cpp +++ b/src/shadow-uarch-state-factory.cpp @@ -44,11 +44,11 @@ static bool shadow_uarch_state_peek(const pma_entry & /*pma*/, const machine &m, // NOLINTNEXTLINE(cppcoreguidelines-pro-type-reinterpret-cast) auto *s = reinterpret_cast(scratch); - s->halt_flag = m.read_reg(machine::reg::uarch_halt_flag); - s->cycle = m.read_reg(machine::reg::uarch_cycle); - s->pc = m.read_reg(machine::reg::uarch_pc); + s->halt_flag = m.read_reg(machine_reg::uarch_halt_flag); + s->cycle = m.read_reg(machine_reg::uarch_cycle); + s->pc = m.read_reg(machine_reg::uarch_pc); for (int i = 0; i < UARCH_X_REG_COUNT; ++i) { - s->x[i] = m.read_reg(static_cast(machine::reg::uarch_x0 + i)); + s->x[i] = m.read_reg(static_cast(static_cast(machine_reg::uarch_x0) + i)); } *page_data = scratch; return true; diff --git a/src/shadow-uarch-state.h b/src/shadow-uarch-state.h index 564528867..efc0c7e5b 100644 --- a/src/shadow-uarch-state.h +++ b/src/shadow-uarch-state.h @@ -22,6 +22,7 @@ #include #include "compiler-defines.h" +#include "machine-reg.h" #include "pma-constants.h" #include "pma-driver.h" #include "riscv-constants.h" @@ -43,66 +44,141 @@ struct PACKED shadow_uarch_state { extern const pma_driver shadow_uarch_state_driver; /// \brief Mapping between registers and their relative addresses in shadow uarch state memory -enum class shadow_uarch_state_reg { - halt_flag = offsetof(shadow_uarch_state, halt_flag), - cycle = offsetof(shadow_uarch_state, cycle), - pc = offsetof(shadow_uarch_state, pc), - x0 = offsetof(shadow_uarch_state, x[0]), - x1 = offsetof(shadow_uarch_state, x[1]), - x2 = offsetof(shadow_uarch_state, x[2]), - x3 = offsetof(shadow_uarch_state, x[3]), - x4 = offsetof(shadow_uarch_state, x[4]), - x5 = offsetof(shadow_uarch_state, x[5]), - x6 = offsetof(shadow_uarch_state, x[6]), - x7 = offsetof(shadow_uarch_state, x[7]), - x8 = offsetof(shadow_uarch_state, x[8]), - x9 = offsetof(shadow_uarch_state, x[9]), - x10 = offsetof(shadow_uarch_state, x[10]), - x11 = offsetof(shadow_uarch_state, x[11]), - x12 = offsetof(shadow_uarch_state, x[12]), - x13 = offsetof(shadow_uarch_state, x[13]), - x14 = offsetof(shadow_uarch_state, x[14]), - x15 = offsetof(shadow_uarch_state, x[15]), - x16 = offsetof(shadow_uarch_state, x[16]), - x17 = offsetof(shadow_uarch_state, x[17]), - x18 = offsetof(shadow_uarch_state, x[18]), - x19 = offsetof(shadow_uarch_state, x[19]), - x20 = offsetof(shadow_uarch_state, x[20]), - x21 = offsetof(shadow_uarch_state, x[21]), - x22 = offsetof(shadow_uarch_state, x[22]), - x23 = offsetof(shadow_uarch_state, x[23]), - x24 = offsetof(shadow_uarch_state, x[24]), - x25 = offsetof(shadow_uarch_state, x[25]), - x26 = offsetof(shadow_uarch_state, x[26]), - x27 = offsetof(shadow_uarch_state, x[27]), - x28 = offsetof(shadow_uarch_state, x[28]), - x29 = offsetof(shadow_uarch_state, x[29]), - x30 = offsetof(shadow_uarch_state, x[30]), - x31 = offsetof(shadow_uarch_state, x[31]), +enum class shadow_uarch_state_reg_rel_addr : uint64_t { + uarch_halt_flag = offsetof(shadow_uarch_state, halt_flag), + uarch_cycle = offsetof(shadow_uarch_state, cycle), + uarch_pc = offsetof(shadow_uarch_state, pc), + uarch_x0 = offsetof(shadow_uarch_state, x[0]), + uarch_x1 = offsetof(shadow_uarch_state, x[1]), + uarch_x2 = offsetof(shadow_uarch_state, x[2]), + uarch_x3 = offsetof(shadow_uarch_state, x[3]), + uarch_x4 = offsetof(shadow_uarch_state, x[4]), + uarch_x5 = offsetof(shadow_uarch_state, x[5]), + uarch_x6 = offsetof(shadow_uarch_state, x[6]), + uarch_x7 = offsetof(shadow_uarch_state, x[7]), + uarch_x8 = offsetof(shadow_uarch_state, x[8]), + uarch_x9 = offsetof(shadow_uarch_state, x[9]), + uarch_x10 = offsetof(shadow_uarch_state, x[10]), + uarch_x11 = offsetof(shadow_uarch_state, x[11]), + uarch_x12 = offsetof(shadow_uarch_state, x[12]), + uarch_x13 = offsetof(shadow_uarch_state, x[13]), + uarch_x14 = offsetof(shadow_uarch_state, x[14]), + uarch_x15 = offsetof(shadow_uarch_state, x[15]), + uarch_x16 = offsetof(shadow_uarch_state, x[16]), + uarch_x17 = offsetof(shadow_uarch_state, x[17]), + uarch_x18 = offsetof(shadow_uarch_state, x[18]), + uarch_x19 = offsetof(shadow_uarch_state, x[19]), + uarch_x20 = offsetof(shadow_uarch_state, x[20]), + uarch_x21 = offsetof(shadow_uarch_state, x[21]), + uarch_x22 = offsetof(shadow_uarch_state, x[22]), + uarch_x23 = offsetof(shadow_uarch_state, x[23]), + uarch_x24 = offsetof(shadow_uarch_state, x[24]), + uarch_x25 = offsetof(shadow_uarch_state, x[25]), + uarch_x26 = offsetof(shadow_uarch_state, x[26]), + uarch_x27 = offsetof(shadow_uarch_state, x[27]), + uarch_x28 = offsetof(shadow_uarch_state, x[28]), + uarch_x29 = offsetof(shadow_uarch_state, x[29]), + uarch_x30 = offsetof(shadow_uarch_state, x[30]), + uarch_x31 = offsetof(shadow_uarch_state, x[31]), }; /// \brief Obtains the relative address of a register in shadow uarch state memory. -/// \param reg Register name. +/// \param r Register name. /// \returns The address. -constexpr uint64_t shadow_uarch_state_get_reg_rel_addr(shadow_uarch_state_reg reg) { - return static_cast(reg); +static inline uint64_t shadow_uarch_state_get_reg_rel_addr(machine_reg r) { + using reg = machine_reg; + switch (r) { + case reg::uarch_halt_flag: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_halt_flag); + case reg::uarch_cycle: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_cycle); + case reg::uarch_pc: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_pc); + case reg::uarch_x0: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x0); + case reg::uarch_x1: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x1); + case reg::uarch_x2: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x2); + case reg::uarch_x3: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x3); + case reg::uarch_x4: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x4); + case reg::uarch_x5: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x5); + case reg::uarch_x6: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x6); + case reg::uarch_x7: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x7); + case reg::uarch_x8: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x8); + case reg::uarch_x9: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x9); + case reg::uarch_x10: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x10); + case reg::uarch_x11: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x11); + case reg::uarch_x12: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x12); + case reg::uarch_x13: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x13); + case reg::uarch_x14: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x14); + case reg::uarch_x15: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x15); + case reg::uarch_x16: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x16); + case reg::uarch_x17: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x17); + case reg::uarch_x18: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x18); + case reg::uarch_x19: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x19); + case reg::uarch_x20: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x20); + case reg::uarch_x21: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x21); + case reg::uarch_x22: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x22); + case reg::uarch_x23: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x23); + case reg::uarch_x24: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x24); + case reg::uarch_x25: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x25); + case reg::uarch_x26: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x26); + case reg::uarch_x27: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x27); + case reg::uarch_x28: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x28); + case reg::uarch_x29: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x29); + case reg::uarch_x30: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x30); + case reg::uarch_x31: + return static_cast(shadow_uarch_state_reg_rel_addr::uarch_x31); + default: + assert(0); + return 0; + } } /// \brief Obtains the absolute address of a register in shadow uarch state memory. -constexpr uint64_t shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg reg) { +/// \param reg Register name. +static inline uint64_t shadow_uarch_state_get_reg_abs_addr(machine_reg reg) { return PMA_SHADOW_UARCH_STATE_START + shadow_uarch_state_get_reg_rel_addr(reg); } -/// \brief Obtains the relative address of a general purpose uarch register -/// in shadow uarch state memory. -/// \param reg Register index in 0...31, for x0...x31, respectively. /// \brief Obtains the relative address of a microarchitecture general purpose register in shadow uarch state memory +/// \param reg Register index in 0...31, for x0...x31, respectively. static inline uint64_t shadow_uarch_state_get_x_rel_addr(int reg) { assert(reg >= 0 && reg < UARCH_X_REG_COUNT); return offsetof(shadow_uarch_state, x) + reg * sizeof(uint64_t); } -/// \brief Obtains the absolute address of a microarchitecture general purpose register +/// \brief Obtains the absolute address of a microarchitecture general purpose register in shadow uarch state memory +/// \param reg Register index in 0...31, for x0...x31, respectively. static inline uint64_t shadow_uarch_state_get_x_abs_addr(int reg) { return PMA_SHADOW_UARCH_STATE_START + shadow_uarch_state_get_x_rel_addr(reg); } diff --git a/src/uarch-bridge.h b/src/uarch-bridge.h index 4e4810ffb..0f516fde8 100644 --- a/src/uarch-bridge.h +++ b/src/uarch-bridge.h @@ -43,297 +43,301 @@ class uarch_bridge { /// An exception is thrown if paddr can't me mapped to a valid state register. //// \} static void write_register(uint64_t paddr, machine_state &s, uint64_t data) { - switch (static_cast(paddr)) { - case shadow_state_reg::x0: - s.x[0] = data; - return; - case shadow_state_reg::x1: - s.x[1] = data; - return; - case shadow_state_reg::x2: - s.x[2] = data; - return; - case shadow_state_reg::x3: - s.x[3] = data; - return; - case shadow_state_reg::x4: - s.x[4] = data; - return; - case shadow_state_reg::x5: - s.x[5] = data; - return; - case shadow_state_reg::x6: - s.x[6] = data; - return; - case shadow_state_reg::x7: - s.x[7] = data; - return; - case shadow_state_reg::x8: - s.x[8] = data; - return; - case shadow_state_reg::x9: - s.x[9] = data; - return; - case shadow_state_reg::x10: - s.x[10] = data; - return; - case shadow_state_reg::x11: - s.x[11] = data; - return; - case shadow_state_reg::x12: - s.x[12] = data; - return; - case shadow_state_reg::x13: - s.x[13] = data; - return; - case shadow_state_reg::x14: - s.x[14] = data; - return; - case shadow_state_reg::x15: - s.x[15] = data; - return; - case shadow_state_reg::x16: - s.x[16] = data; - return; - case shadow_state_reg::x17: - s.x[17] = data; - return; - case shadow_state_reg::x18: - s.x[18] = data; - return; - case shadow_state_reg::x19: - s.x[19] = data; - return; - case shadow_state_reg::x20: - s.x[20] = data; - return; - case shadow_state_reg::x21: - s.x[21] = data; - return; - case shadow_state_reg::x22: - s.x[22] = data; - return; - case shadow_state_reg::x23: - s.x[23] = data; - return; - case shadow_state_reg::x24: - s.x[24] = data; - return; - case shadow_state_reg::x25: - s.x[25] = data; - return; - case shadow_state_reg::x26: - s.x[26] = data; - return; - case shadow_state_reg::x27: - s.x[27] = data; - return; - case shadow_state_reg::x28: - s.x[28] = data; - return; - case shadow_state_reg::x29: - s.x[29] = data; - return; - case shadow_state_reg::x30: - s.x[30] = data; - return; - case shadow_state_reg::x31: - s.x[31] = data; - return; - case shadow_state_reg::f0: - s.f[0] = data; - return; - case shadow_state_reg::f1: - s.f[1] = data; - return; - case shadow_state_reg::f2: - s.f[2] = data; - return; - case shadow_state_reg::f3: - s.f[3] = data; - return; - case shadow_state_reg::f4: - s.f[4] = data; - return; - case shadow_state_reg::f5: - s.f[5] = data; - return; - case shadow_state_reg::f6: - s.f[6] = data; - return; - case shadow_state_reg::f7: - s.f[7] = data; - return; - case shadow_state_reg::f8: - s.f[8] = data; - return; - case shadow_state_reg::f9: - s.f[9] = data; - return; - case shadow_state_reg::f10: - s.f[10] = data; - return; - case shadow_state_reg::f11: - s.f[11] = data; - return; - case shadow_state_reg::f12: - s.f[12] = data; - return; - case shadow_state_reg::f13: - s.f[13] = data; - return; - case shadow_state_reg::f14: - s.f[14] = data; - return; - case shadow_state_reg::f15: - s.f[15] = data; - return; - case shadow_state_reg::f16: - s.f[16] = data; - return; - case shadow_state_reg::f17: - s.f[17] = data; - return; - case shadow_state_reg::f18: - s.f[18] = data; - return; - case shadow_state_reg::f19: - s.f[19] = data; - return; - case shadow_state_reg::f20: - s.f[20] = data; - return; - case shadow_state_reg::f21: - s.f[21] = data; - return; - case shadow_state_reg::f22: - s.f[22] = data; - return; - case shadow_state_reg::f23: - s.f[23] = data; - return; - case shadow_state_reg::f24: - s.f[24] = data; - return; - case shadow_state_reg::f25: - s.f[25] = data; - return; - case shadow_state_reg::f26: - s.f[26] = data; - return; - case shadow_state_reg::f27: - s.f[27] = data; - return; - case shadow_state_reg::f28: - s.f[28] = data; - return; - case shadow_state_reg::f29: - s.f[29] = data; - return; - case shadow_state_reg::f30: - s.f[30] = data; - return; - case shadow_state_reg::f31: - s.f[31] = data; - return; - case shadow_state_reg::pc: - s.pc = data; - return; - case shadow_state_reg::fcsr: - s.fcsr = data; - return; - case shadow_state_reg::mcycle: - s.mcycle = data; - return; - case shadow_state_reg::icycleinstret: - s.icycleinstret = data; - return; - case shadow_state_reg::mstatus: - s.mstatus = data; - return; - case shadow_state_reg::mtvec: - s.mtvec = data; - return; - case shadow_state_reg::mscratch: - s.mscratch = data; - return; - case shadow_state_reg::mepc: - s.mepc = data; - return; - case shadow_state_reg::mcause: - s.mcause = data; - return; - case shadow_state_reg::mtval: - s.mtval = data; - return; - case shadow_state_reg::misa: - s.misa = data; - return; - case shadow_state_reg::mie: - s.mie = data; - return; - case shadow_state_reg::mip: - s.mip = data; - return; - case shadow_state_reg::medeleg: - s.medeleg = data; - return; - case shadow_state_reg::mideleg: - s.mideleg = data; - return; - case shadow_state_reg::mcounteren: - s.mcounteren = data; - return; - case shadow_state_reg::menvcfg: - s.menvcfg = data; - return; - case shadow_state_reg::stvec: - s.stvec = data; - return; - case shadow_state_reg::sscratch: - s.sscratch = data; - return; - case shadow_state_reg::sepc: - s.sepc = data; - return; - case shadow_state_reg::scause: - s.scause = data; - return; - case shadow_state_reg::stval: - s.stval = data; - return; - case shadow_state_reg::satp: - s.satp = data; - return; - case shadow_state_reg::scounteren: - s.scounteren = data; - return; - case shadow_state_reg::senvcfg: - s.senvcfg = data; - return; - case shadow_state_reg::ilrsc: - s.ilrsc = data; - return; - case shadow_state_reg::iflags: - s.write_iflags(data); - return; - case shadow_state_reg::clint_mtimecmp: - s.clint.mtimecmp = data; - return; - case shadow_state_reg::plic_girqpend: - s.plic.girqpend = data; - return; - case shadow_state_reg::plic_girqsrvd: - s.plic.girqsrvd = data; - return; - case shadow_state_reg::htif_tohost: - s.htif.tohost = data; - return; - case shadow_state_reg::htif_fromhost: - s.htif.fromhost = data; - return; - default: - break; + if (paddr >= PMA_SHADOW_STATE_START) { + using reg = shadow_state_reg_rel_addr; + paddr -= PMA_SHADOW_STATE_START; + switch (static_cast(paddr)) { + case reg::x0: + s.x[0] = data; + return; + case reg::x1: + s.x[1] = data; + return; + case reg::x2: + s.x[2] = data; + return; + case reg::x3: + s.x[3] = data; + return; + case reg::x4: + s.x[4] = data; + return; + case reg::x5: + s.x[5] = data; + return; + case reg::x6: + s.x[6] = data; + return; + case reg::x7: + s.x[7] = data; + return; + case reg::x8: + s.x[8] = data; + return; + case reg::x9: + s.x[9] = data; + return; + case reg::x10: + s.x[10] = data; + return; + case reg::x11: + s.x[11] = data; + return; + case reg::x12: + s.x[12] = data; + return; + case reg::x13: + s.x[13] = data; + return; + case reg::x14: + s.x[14] = data; + return; + case reg::x15: + s.x[15] = data; + return; + case reg::x16: + s.x[16] = data; + return; + case reg::x17: + s.x[17] = data; + return; + case reg::x18: + s.x[18] = data; + return; + case reg::x19: + s.x[19] = data; + return; + case reg::x20: + s.x[20] = data; + return; + case reg::x21: + s.x[21] = data; + return; + case reg::x22: + s.x[22] = data; + return; + case reg::x23: + s.x[23] = data; + return; + case reg::x24: + s.x[24] = data; + return; + case reg::x25: + s.x[25] = data; + return; + case reg::x26: + s.x[26] = data; + return; + case reg::x27: + s.x[27] = data; + return; + case reg::x28: + s.x[28] = data; + return; + case reg::x29: + s.x[29] = data; + return; + case reg::x30: + s.x[30] = data; + return; + case reg::x31: + s.x[31] = data; + return; + case reg::f0: + s.f[0] = data; + return; + case reg::f1: + s.f[1] = data; + return; + case reg::f2: + s.f[2] = data; + return; + case reg::f3: + s.f[3] = data; + return; + case reg::f4: + s.f[4] = data; + return; + case reg::f5: + s.f[5] = data; + return; + case reg::f6: + s.f[6] = data; + return; + case reg::f7: + s.f[7] = data; + return; + case reg::f8: + s.f[8] = data; + return; + case reg::f9: + s.f[9] = data; + return; + case reg::f10: + s.f[10] = data; + return; + case reg::f11: + s.f[11] = data; + return; + case reg::f12: + s.f[12] = data; + return; + case reg::f13: + s.f[13] = data; + return; + case reg::f14: + s.f[14] = data; + return; + case reg::f15: + s.f[15] = data; + return; + case reg::f16: + s.f[16] = data; + return; + case reg::f17: + s.f[17] = data; + return; + case reg::f18: + s.f[18] = data; + return; + case reg::f19: + s.f[19] = data; + return; + case reg::f20: + s.f[20] = data; + return; + case reg::f21: + s.f[21] = data; + return; + case reg::f22: + s.f[22] = data; + return; + case reg::f23: + s.f[23] = data; + return; + case reg::f24: + s.f[24] = data; + return; + case reg::f25: + s.f[25] = data; + return; + case reg::f26: + s.f[26] = data; + return; + case reg::f27: + s.f[27] = data; + return; + case reg::f28: + s.f[28] = data; + return; + case reg::f29: + s.f[29] = data; + return; + case reg::f30: + s.f[30] = data; + return; + case reg::f31: + s.f[31] = data; + return; + case reg::pc: + s.pc = data; + return; + case reg::fcsr: + s.fcsr = data; + return; + case reg::mcycle: + s.mcycle = data; + return; + case reg::icycleinstret: + s.icycleinstret = data; + return; + case reg::mstatus: + s.mstatus = data; + return; + case reg::mtvec: + s.mtvec = data; + return; + case reg::mscratch: + s.mscratch = data; + return; + case reg::mepc: + s.mepc = data; + return; + case reg::mcause: + s.mcause = data; + return; + case reg::mtval: + s.mtval = data; + return; + case reg::misa: + s.misa = data; + return; + case reg::mie: + s.mie = data; + return; + case reg::mip: + s.mip = data; + return; + case reg::medeleg: + s.medeleg = data; + return; + case reg::mideleg: + s.mideleg = data; + return; + case reg::mcounteren: + s.mcounteren = data; + return; + case reg::menvcfg: + s.menvcfg = data; + return; + case reg::stvec: + s.stvec = data; + return; + case reg::sscratch: + s.sscratch = data; + return; + case reg::sepc: + s.sepc = data; + return; + case reg::scause: + s.scause = data; + return; + case reg::stval: + s.stval = data; + return; + case reg::satp: + s.satp = data; + return; + case reg::scounteren: + s.scounteren = data; + return; + case reg::senvcfg: + s.senvcfg = data; + return; + case reg::ilrsc: + s.ilrsc = data; + return; + case reg::iflags: + s.write_iflags(data); + return; + case reg::clint_mtimecmp: + s.clint.mtimecmp = data; + return; + case reg::plic_girqpend: + s.plic.girqpend = data; + return; + case reg::plic_girqsrvd: + s.plic.girqsrvd = data; + return; + case reg::htif_tohost: + s.htif.tohost = data; + return; + case reg::htif_fromhost: + s.htif.fromhost = data; + return; + default: + break; + } } if (try_write_tlb(s, paddr, data)) { return; @@ -349,213 +353,217 @@ class uarch_bridge { /// An exception is thrown if paddr can't me mapped to a valid state register. //// \} static uint64_t read_register(uint64_t paddr, machine_state &s) { - switch (static_cast(paddr)) { - case shadow_state_reg::x0: - return s.x[0]; - case shadow_state_reg::x1: - return s.x[1]; - case shadow_state_reg::x2: - return s.x[2]; - case shadow_state_reg::x3: - return s.x[3]; - case shadow_state_reg::x4: - return s.x[4]; - case shadow_state_reg::x5: - return s.x[5]; - case shadow_state_reg::x6: - return s.x[6]; - case shadow_state_reg::x7: - return s.x[7]; - case shadow_state_reg::x8: - return s.x[8]; - case shadow_state_reg::x9: - return s.x[9]; - case shadow_state_reg::x10: - return s.x[10]; - case shadow_state_reg::x11: - return s.x[11]; - case shadow_state_reg::x12: - return s.x[12]; - case shadow_state_reg::x13: - return s.x[13]; - case shadow_state_reg::x14: - return s.x[14]; - case shadow_state_reg::x15: - return s.x[15]; - case shadow_state_reg::x16: - return s.x[16]; - case shadow_state_reg::x17: - return s.x[17]; - case shadow_state_reg::x18: - return s.x[18]; - case shadow_state_reg::x19: - return s.x[19]; - case shadow_state_reg::x20: - return s.x[20]; - case shadow_state_reg::x21: - return s.x[21]; - case shadow_state_reg::x22: - return s.x[22]; - case shadow_state_reg::x23: - return s.x[23]; - case shadow_state_reg::x24: - return s.x[24]; - case shadow_state_reg::x25: - return s.x[25]; - case shadow_state_reg::x26: - return s.x[26]; - case shadow_state_reg::x27: - return s.x[27]; - case shadow_state_reg::x28: - return s.x[28]; - case shadow_state_reg::x29: - return s.x[29]; - case shadow_state_reg::x30: - return s.x[30]; - case shadow_state_reg::x31: - return s.x[31]; - case shadow_state_reg::f0: - return s.f[0]; - case shadow_state_reg::f1: - return s.f[1]; - case shadow_state_reg::f2: - return s.f[2]; - case shadow_state_reg::f3: - return s.f[3]; - case shadow_state_reg::f4: - return s.f[4]; - case shadow_state_reg::f5: - return s.f[5]; - case shadow_state_reg::f6: - return s.f[6]; - case shadow_state_reg::f7: - return s.f[7]; - case shadow_state_reg::f8: - return s.f[8]; - case shadow_state_reg::f9: - return s.f[9]; - case shadow_state_reg::f10: - return s.f[10]; - case shadow_state_reg::f11: - return s.f[11]; - case shadow_state_reg::f12: - return s.f[12]; - case shadow_state_reg::f13: - return s.f[13]; - case shadow_state_reg::f14: - return s.f[14]; - case shadow_state_reg::f15: - return s.f[15]; - case shadow_state_reg::f16: - return s.f[16]; - case shadow_state_reg::f17: - return s.f[17]; - case shadow_state_reg::f18: - return s.f[18]; - case shadow_state_reg::f19: - return s.f[19]; - case shadow_state_reg::f20: - return s.f[20]; - case shadow_state_reg::f21: - return s.f[21]; - case shadow_state_reg::f22: - return s.f[22]; - case shadow_state_reg::f23: - return s.f[23]; - case shadow_state_reg::f24: - return s.f[24]; - case shadow_state_reg::f25: - return s.f[25]; - case shadow_state_reg::f26: - return s.f[26]; - case shadow_state_reg::f27: - return s.f[27]; - case shadow_state_reg::f28: - return s.f[28]; - case shadow_state_reg::f29: - return s.f[29]; - case shadow_state_reg::f30: - return s.f[30]; - case shadow_state_reg::f31: - return s.f[31]; - case shadow_state_reg::pc: - return s.pc; - case shadow_state_reg::fcsr: - return s.fcsr; - case shadow_state_reg::mvendorid: - return MVENDORID_INIT; - case shadow_state_reg::marchid: - return MARCHID_INIT; - case shadow_state_reg::mimpid: - return MIMPID_INIT; - case shadow_state_reg::mcycle: - return s.mcycle; - case shadow_state_reg::icycleinstret: - return s.icycleinstret; - case shadow_state_reg::mstatus: - return s.mstatus; - case shadow_state_reg::mtvec: - return s.mtvec; - case shadow_state_reg::mscratch: - return s.mscratch; - case shadow_state_reg::mepc: - return s.mepc; - case shadow_state_reg::mcause: - return s.mcause; - case shadow_state_reg::mtval: - return s.mtval; - case shadow_state_reg::misa: - return s.misa; - case shadow_state_reg::mie: - return s.mie; - case shadow_state_reg::mip: - return s.mip; - case shadow_state_reg::medeleg: - return s.medeleg; - case shadow_state_reg::mideleg: - return s.mideleg; - case shadow_state_reg::mcounteren: - return s.mcounteren; - case shadow_state_reg::menvcfg: - return s.menvcfg; - case shadow_state_reg::stvec: - return s.stvec; - case shadow_state_reg::sscratch: - return s.sscratch; - case shadow_state_reg::sepc: - return s.sepc; - case shadow_state_reg::scause: - return s.scause; - case shadow_state_reg::stval: - return s.stval; - case shadow_state_reg::satp: - return s.satp; - case shadow_state_reg::scounteren: - return s.scounteren; - case shadow_state_reg::senvcfg: - return s.senvcfg; - case shadow_state_reg::ilrsc: - return s.ilrsc; - case shadow_state_reg::iflags: - return s.read_iflags(); - case shadow_state_reg::clint_mtimecmp: - return s.clint.mtimecmp; - case shadow_state_reg::plic_girqpend: - return s.plic.girqpend; - case shadow_state_reg::plic_girqsrvd: - return s.plic.girqsrvd; - case shadow_state_reg::htif_tohost: - return s.htif.tohost; - case shadow_state_reg::htif_fromhost: - return s.htif.fromhost; - case shadow_state_reg::htif_ihalt: - return s.htif.ihalt; - case shadow_state_reg::htif_iconsole: - return s.htif.iconsole; - case shadow_state_reg::htif_iyield: - return s.htif.iyield; - default: - break; + if (paddr >= PMA_SHADOW_STATE_START) { + using reg = shadow_state_reg_rel_addr; + paddr -= PMA_SHADOW_STATE_START; + switch (static_cast(paddr)) { + case reg::x0: + return s.x[0]; + case reg::x1: + return s.x[1]; + case reg::x2: + return s.x[2]; + case reg::x3: + return s.x[3]; + case reg::x4: + return s.x[4]; + case reg::x5: + return s.x[5]; + case reg::x6: + return s.x[6]; + case reg::x7: + return s.x[7]; + case reg::x8: + return s.x[8]; + case reg::x9: + return s.x[9]; + case reg::x10: + return s.x[10]; + case reg::x11: + return s.x[11]; + case reg::x12: + return s.x[12]; + case reg::x13: + return s.x[13]; + case reg::x14: + return s.x[14]; + case reg::x15: + return s.x[15]; + case reg::x16: + return s.x[16]; + case reg::x17: + return s.x[17]; + case reg::x18: + return s.x[18]; + case reg::x19: + return s.x[19]; + case reg::x20: + return s.x[20]; + case reg::x21: + return s.x[21]; + case reg::x22: + return s.x[22]; + case reg::x23: + return s.x[23]; + case reg::x24: + return s.x[24]; + case reg::x25: + return s.x[25]; + case reg::x26: + return s.x[26]; + case reg::x27: + return s.x[27]; + case reg::x28: + return s.x[28]; + case reg::x29: + return s.x[29]; + case reg::x30: + return s.x[30]; + case reg::x31: + return s.x[31]; + case reg::f0: + return s.f[0]; + case reg::f1: + return s.f[1]; + case reg::f2: + return s.f[2]; + case reg::f3: + return s.f[3]; + case reg::f4: + return s.f[4]; + case reg::f5: + return s.f[5]; + case reg::f6: + return s.f[6]; + case reg::f7: + return s.f[7]; + case reg::f8: + return s.f[8]; + case reg::f9: + return s.f[9]; + case reg::f10: + return s.f[10]; + case reg::f11: + return s.f[11]; + case reg::f12: + return s.f[12]; + case reg::f13: + return s.f[13]; + case reg::f14: + return s.f[14]; + case reg::f15: + return s.f[15]; + case reg::f16: + return s.f[16]; + case reg::f17: + return s.f[17]; + case reg::f18: + return s.f[18]; + case reg::f19: + return s.f[19]; + case reg::f20: + return s.f[20]; + case reg::f21: + return s.f[21]; + case reg::f22: + return s.f[22]; + case reg::f23: + return s.f[23]; + case reg::f24: + return s.f[24]; + case reg::f25: + return s.f[25]; + case reg::f26: + return s.f[26]; + case reg::f27: + return s.f[27]; + case reg::f28: + return s.f[28]; + case reg::f29: + return s.f[29]; + case reg::f30: + return s.f[30]; + case reg::f31: + return s.f[31]; + case reg::pc: + return s.pc; + case reg::fcsr: + return s.fcsr; + case reg::mvendorid: + return MVENDORID_INIT; + case reg::marchid: + return MARCHID_INIT; + case reg::mimpid: + return MIMPID_INIT; + case reg::mcycle: + return s.mcycle; + case reg::icycleinstret: + return s.icycleinstret; + case reg::mstatus: + return s.mstatus; + case reg::mtvec: + return s.mtvec; + case reg::mscratch: + return s.mscratch; + case reg::mepc: + return s.mepc; + case reg::mcause: + return s.mcause; + case reg::mtval: + return s.mtval; + case reg::misa: + return s.misa; + case reg::mie: + return s.mie; + case reg::mip: + return s.mip; + case reg::medeleg: + return s.medeleg; + case reg::mideleg: + return s.mideleg; + case reg::mcounteren: + return s.mcounteren; + case reg::menvcfg: + return s.menvcfg; + case reg::stvec: + return s.stvec; + case reg::sscratch: + return s.sscratch; + case reg::sepc: + return s.sepc; + case reg::scause: + return s.scause; + case reg::stval: + return s.stval; + case reg::satp: + return s.satp; + case reg::scounteren: + return s.scounteren; + case reg::senvcfg: + return s.senvcfg; + case reg::ilrsc: + return s.ilrsc; + case reg::iflags: + return s.read_iflags(); + case reg::clint_mtimecmp: + return s.clint.mtimecmp; + case reg::plic_girqpend: + return s.plic.girqpend; + case reg::plic_girqsrvd: + return s.plic.girqsrvd; + case reg::htif_tohost: + return s.htif.tohost; + case reg::htif_fromhost: + return s.htif.fromhost; + case reg::htif_ihalt: + return s.htif.ihalt; + case reg::htif_iconsole: + return s.htif.iconsole; + case reg::htif_iyield: + return s.htif.iyield; + default: + break; + } } uint64_t data = 0; if (try_read_tlb(s, paddr, &data)) { @@ -571,210 +579,211 @@ class uarch_bridge { /// \param paddr Address of the state register. /// \returns The register name, if paddr maps to a register, or nullptr otherwise. static const char *get_register_name(uint64_t paddr) { - switch (static_cast(paddr)) { - case shadow_state_reg::x0: + using reg = shadow_state_reg_rel_addr; + switch (static_cast(paddr)) { + case reg::x0: return "x0"; - case shadow_state_reg::x1: + case reg::x1: return "x1"; - case shadow_state_reg::x2: + case reg::x2: return "x2"; - case shadow_state_reg::x3: + case reg::x3: return "x3"; - case shadow_state_reg::x4: + case reg::x4: return "x4"; - case shadow_state_reg::x5: + case reg::x5: return "x5"; - case shadow_state_reg::x6: + case reg::x6: return "x6"; - case shadow_state_reg::x7: + case reg::x7: return "x7"; - case shadow_state_reg::x8: + case reg::x8: return "x8"; - case shadow_state_reg::x9: + case reg::x9: return "x9"; - case shadow_state_reg::x10: + case reg::x10: return "x10"; - case shadow_state_reg::x11: + case reg::x11: return "x11"; - case shadow_state_reg::x12: + case reg::x12: return "x12"; - case shadow_state_reg::x13: + case reg::x13: return "x13"; - case shadow_state_reg::x14: + case reg::x14: return "x14"; - case shadow_state_reg::x15: + case reg::x15: return "x15"; - case shadow_state_reg::x16: + case reg::x16: return "x16"; - case shadow_state_reg::x17: + case reg::x17: return "x17"; - case shadow_state_reg::x18: + case reg::x18: return "x18"; - case shadow_state_reg::x19: + case reg::x19: return "x19"; - case shadow_state_reg::x20: + case reg::x20: return "x20"; - case shadow_state_reg::x21: + case reg::x21: return "x21"; - case shadow_state_reg::x22: + case reg::x22: return "x22"; - case shadow_state_reg::x23: + case reg::x23: return "x23"; - case shadow_state_reg::x24: + case reg::x24: return "x24"; - case shadow_state_reg::x25: + case reg::x25: return "x25"; - case shadow_state_reg::x26: + case reg::x26: return "x26"; - case shadow_state_reg::x27: + case reg::x27: return "x27"; - case shadow_state_reg::x28: + case reg::x28: return "x28"; - case shadow_state_reg::x29: + case reg::x29: return "x29"; - case shadow_state_reg::x30: + case reg::x30: return "x30"; - case shadow_state_reg::x31: + case reg::x31: return "x31"; - case shadow_state_reg::f0: + case reg::f0: return "f0"; - case shadow_state_reg::f1: + case reg::f1: return "f1"; - case shadow_state_reg::f2: + case reg::f2: return "f2"; - case shadow_state_reg::f3: + case reg::f3: return "f3"; - case shadow_state_reg::f4: + case reg::f4: return "f4"; - case shadow_state_reg::f5: + case reg::f5: return "f5"; - case shadow_state_reg::f6: + case reg::f6: return "f6"; - case shadow_state_reg::f7: + case reg::f7: return "f7"; - case shadow_state_reg::f8: + case reg::f8: return "f8"; - case shadow_state_reg::f9: + case reg::f9: return "f9"; - case shadow_state_reg::f10: + case reg::f10: return "f10"; - case shadow_state_reg::f11: + case reg::f11: return "f11"; - case shadow_state_reg::f12: + case reg::f12: return "f12"; - case shadow_state_reg::f13: + case reg::f13: return "f13"; - case shadow_state_reg::f14: + case reg::f14: return "f14"; - case shadow_state_reg::f15: + case reg::f15: return "f15"; - case shadow_state_reg::f16: + case reg::f16: return "f16"; - case shadow_state_reg::f17: + case reg::f17: return "f17"; - case shadow_state_reg::f18: + case reg::f18: return "f18"; - case shadow_state_reg::f19: + case reg::f19: return "f19"; - case shadow_state_reg::f20: + case reg::f20: return "f20"; - case shadow_state_reg::f21: + case reg::f21: return "f21"; - case shadow_state_reg::f22: + case reg::f22: return "f22"; - case shadow_state_reg::f23: + case reg::f23: return "f23"; - case shadow_state_reg::f24: + case reg::f24: return "f24"; - case shadow_state_reg::f25: + case reg::f25: return "f25"; - case shadow_state_reg::f26: + case reg::f26: return "f26"; - case shadow_state_reg::f27: + case reg::f27: return "f27"; - case shadow_state_reg::f28: + case reg::f28: return "f28"; - case shadow_state_reg::f29: + case reg::f29: return "f29"; - case shadow_state_reg::f30: + case reg::f30: return "f30"; - case shadow_state_reg::f31: + case reg::f31: return "f31"; - case shadow_state_reg::pc: + case reg::pc: return "pc"; - case shadow_state_reg::fcsr: + case reg::fcsr: return "fcsr"; - case shadow_state_reg::mvendorid: + case reg::mvendorid: return "mvendorid"; - case shadow_state_reg::marchid: + case reg::marchid: return "marchid"; - case shadow_state_reg::mimpid: + case reg::mimpid: return "mimpid"; - case shadow_state_reg::mcycle: + case reg::mcycle: return "mcycle"; - case shadow_state_reg::icycleinstret: + case reg::icycleinstret: return "icycleinstret"; - case shadow_state_reg::mstatus: + case reg::mstatus: return "mstatus"; - case shadow_state_reg::mtvec: + case reg::mtvec: return "mtvec"; - case shadow_state_reg::mscratch: + case reg::mscratch: return "mscratch"; - case shadow_state_reg::mepc: + case reg::mepc: return "mepc"; - case shadow_state_reg::mcause: + case reg::mcause: return "mcause"; - case shadow_state_reg::mtval: + case reg::mtval: return "mtval"; - case shadow_state_reg::misa: + case reg::misa: return "misa"; - case shadow_state_reg::mie: + case reg::mie: return "mie"; - case shadow_state_reg::mip: + case reg::mip: return "mip"; - case shadow_state_reg::medeleg: + case reg::medeleg: return "medeleg"; - case shadow_state_reg::mideleg: + case reg::mideleg: return "mideleg"; - case shadow_state_reg::mcounteren: + case reg::mcounteren: return "mcounteren"; - case shadow_state_reg::menvcfg: + case reg::menvcfg: return "menvcfg"; - case shadow_state_reg::stvec: + case reg::stvec: return "stvec"; - case shadow_state_reg::sscratch: + case reg::sscratch: return "sscratch"; - case shadow_state_reg::sepc: + case reg::sepc: return "sepc"; - case shadow_state_reg::scause: + case reg::scause: return "scause"; - case shadow_state_reg::stval: + case reg::stval: return "stval"; - case shadow_state_reg::satp: + case reg::satp: return "satp"; - case shadow_state_reg::scounteren: + case reg::scounteren: return "scounteren"; - case shadow_state_reg::senvcfg: + case reg::senvcfg: return "senvcfg"; - case shadow_state_reg::ilrsc: + case reg::ilrsc: return "ilrsc"; - case shadow_state_reg::iflags: + case reg::iflags: return "iflags"; - case shadow_state_reg::clint_mtimecmp: + case reg::clint_mtimecmp: return "clint.mtimecmp"; - case shadow_state_reg::plic_girqpend: + case reg::plic_girqpend: return "plic.girqpend"; - case shadow_state_reg::plic_girqsrvd: + case reg::plic_girqsrvd: return "plic.girqsrvd"; - case shadow_state_reg::htif_tohost: + case reg::htif_tohost: return "htif.tohost"; - case shadow_state_reg::htif_fromhost: + case reg::htif_fromhost: return "htif.fromhost"; - case shadow_state_reg::htif_ihalt: + case reg::htif_ihalt: return "htif.ihalt"; - case shadow_state_reg::htif_iconsole: + case reg::htif_iconsole: return "htif.iconsole"; - case shadow_state_reg::htif_iyield: + case reg::htif_iyield: return "htif.iyield"; default: break; diff --git a/src/uarch-record-state-access.h b/src/uarch-record-state-access.h index 4b664c5f2..4528c08f0 100644 --- a/src/uarch-record-state-access.h +++ b/src/uarch-record-state-access.h @@ -309,35 +309,35 @@ class uarch_record_state_access : public i_uarch_state_access(m_us.halt_flag), "uarch.halt_flag") != 0; } void do_set_halt_flag() { - log_before_write_write_and_update(shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::halt_flag), + log_before_write_write_and_update(shadow_uarch_state_get_reg_abs_addr(machine_reg::uarch_halt_flag), m_us.halt_flag, true, "uarch.halt_flag"); } void do_reset_halt_flag() { - log_before_write_write_and_update(shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::halt_flag), + log_before_write_write_and_update(shadow_uarch_state_get_reg_abs_addr(machine_reg::uarch_halt_flag), m_us.halt_flag, false, "uarch.halt_flag"); } diff --git a/src/uarch-replay-state-access.h b/src/uarch-replay-state-access.h index 939466630..8f05f219a 100644 --- a/src/uarch-replay-state-access.h +++ b/src/uarch-replay-state-access.h @@ -275,34 +275,33 @@ class uarch_replay_state_access : public i_uarch_state_access(true), + check_write(shadow_uarch_state_get_reg_abs_addr(machine_reg::uarch_halt_flag), static_cast(true), "uarch.halt_flag"); } void do_reset_halt_flag() { - check_write(shadow_uarch_state_get_reg_abs_addr(shadow_uarch_state_reg::halt_flag), - static_cast(false), "uarch.halt_flag"); + check_write(shadow_uarch_state_get_reg_abs_addr(machine_reg::uarch_halt_flag), static_cast(false), + "uarch.halt_flag"); } uint64_t do_read_word(uint64_t paddr) { diff --git a/tests/lua/htif-console.lua b/tests/lua/htif-console.lua index 8d296c539..de1b69bff 100755 --- a/tests/lua/htif-console.lua +++ b/tests/lua/htif-console.lua @@ -33,8 +33,8 @@ local function stderr(...) io.stderr:write(string.format(...)) end -local final_mcycle = 2137 -local exit_payload = 42 +local expected_final_mcycle = 2137 +local expected_exit_payload = 42 local function test(config, console_getchar_enable) stderr(" testing console_getchar:%s\n", console_getchar_enable and "on" or "off") @@ -48,15 +48,17 @@ local function test(config, console_getchar_enable) assert(machine:read_iflags_H(), "expected iflags_H set") -- with the expected payload + local exit_payload = machine:read_reg("htif_tohost_data") >> 1 assert( - (machine:read_reg("htif_tohost_data") >> 1) == exit_payload, - string.format("exit payload: expected %u, got %u\n", exit_payload, machine:read_reg("htif_tohost_data") >> 1) + exit_payload == expected_exit_payload, + string.format("exit payload: expected %u, got %u\n", expected_exit_payload, exit_payload) ) -- at the expected mcycle + local final_mcycle = machine:read_mcycle() assert( - machine:read_mcycle() == final_mcycle, - string.format("mcycle: expected, %u got %u", final_mcycle, machine:read_mcycle()) + final_mcycle == expected_final_mcycle, + string.format("mcycle: expected, %u got %u", expected_final_mcycle, final_mcycle) ) stderr(" passed\n") diff --git a/uarch/uarch-machine-state-access.h b/uarch/uarch-machine-state-access.h index 01254115a..448ba6f11 100644 --- a/uarch/uarch-machine-state-access.h +++ b/uarch/uarch-machine-state-access.h @@ -187,231 +187,231 @@ class uarch_machine_state_access : public i_state_access(shadow_state_get_reg_abs_addr(shadow_state_reg::pc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::pc)); } void do_write_pc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::pc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::pc), val); } uint64_t do_read_fcsr() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::fcsr)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr)); } void do_write_fcsr(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::fcsr), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::fcsr), val); } uint64_t do_read_icycleinstret() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::icycleinstret)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret)); } void do_write_icycleinstret(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::icycleinstret), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::icycleinstret), val); } uint64_t do_read_mvendorid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mvendorid)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mvendorid)); } uint64_t do_read_marchid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::marchid)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::marchid)); } uint64_t do_read_mimpid() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mimpid)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mimpid)); } uint64_t do_read_mcycle() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcycle)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle)); } void do_write_mcycle(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcycle), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcycle), val); } uint64_t do_read_mstatus() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mstatus)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus)); } void do_write_mstatus(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mstatus), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mstatus), val); } uint64_t do_read_mtvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtvec)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec)); } void do_write_mtvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtvec), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtvec), val); } uint64_t do_read_mscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mscratch)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch)); } void do_write_mscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mscratch), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mscratch), val); } uint64_t do_read_mepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mepc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc)); } void do_write_mepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mepc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mepc), val); } uint64_t do_read_mcause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcause)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause)); } void do_write_mcause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcause), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcause), val); } uint64_t do_read_mtval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtval)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval)); } void do_write_mtval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mtval), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mtval), val); } uint64_t do_read_misa() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::misa)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::misa)); } void do_write_misa(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::misa), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::misa), val); } uint64_t do_read_mie() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mie)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mie)); } void do_write_mie(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mie), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mie), val); } uint64_t do_read_mip() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mip)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mip)); } void do_write_mip(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mip), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mip), val); } uint64_t do_read_medeleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::medeleg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg)); } void do_write_medeleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::medeleg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::medeleg), val); } uint64_t do_read_mideleg() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mideleg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg)); } void do_write_mideleg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mideleg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mideleg), val); } uint64_t do_read_mcounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcounteren)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren)); } void do_write_mcounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::mcounteren), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::mcounteren), val); } uint64_t do_read_senvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::senvcfg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg)); } void do_write_senvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::senvcfg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::senvcfg), val); } uint64_t do_read_menvcfg() const { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::menvcfg)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg)); } void do_write_menvcfg(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::menvcfg), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::menvcfg), val); } uint64_t do_read_stvec() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stvec)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec)); } void do_write_stvec(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stvec), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stvec), val); } uint64_t do_read_sscratch() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sscratch)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch)); } void do_write_sscratch(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sscratch), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sscratch), val); } uint64_t do_read_sepc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sepc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc)); } void do_write_sepc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::sepc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::sepc), val); } uint64_t do_read_scause() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scause)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scause)); } void do_write_scause(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scause), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scause), val); } uint64_t do_read_stval() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stval)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::stval)); } void do_write_stval(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::stval), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::stval), val); } uint64_t do_read_satp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::satp)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::satp)); } void do_write_satp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::satp), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::satp), val); } uint64_t do_read_scounteren() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scounteren)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren)); } void do_write_scounteren(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::scounteren), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::scounteren), val); } uint64_t do_read_ilrsc() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::ilrsc)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc)); } void do_write_ilrsc(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::ilrsc), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::ilrsc), val); } uint64_t do_read_iflags() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::iflags)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags)); } void do_write_iflags(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::iflags), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iflags), val); } void do_set_iflags_H() { @@ -472,63 +472,63 @@ class uarch_machine_state_access : public i_state_access(shadow_state_get_reg_abs_addr(shadow_state_reg::iunrep)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::iunrep)); } void do_write_iunrep(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::iunrep), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::iunrep), val); } uint64_t do_read_clint_mtimecmp() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::clint_mtimecmp)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp)); } void do_write_clint_mtimecmp(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::clint_mtimecmp), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::clint_mtimecmp), val); } uint64_t do_read_plic_girqpend() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqpend)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend)); } void do_write_plic_girqpend(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqpend), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqpend), val); } uint64_t do_read_plic_girqsrvd() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqsrvd)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd)); } void do_write_plic_girqsrvd(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::plic_girqsrvd), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::plic_girqsrvd), val); } uint64_t do_read_htif_fromhost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_fromhost)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost)); } void do_write_htif_fromhost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_fromhost), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_fromhost), val); } uint64_t do_read_htif_tohost() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_tohost)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost)); } void do_write_htif_tohost(uint64_t val) { - raw_write_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_tohost), val); + raw_write_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_tohost), val); } uint64_t do_read_htif_ihalt() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_ihalt)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_ihalt)); } uint64_t do_read_htif_iconsole() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_iconsole)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iconsole)); } uint64_t do_read_htif_iyield() { - return raw_read_memory(shadow_state_get_reg_abs_addr(shadow_state_reg::htif_iyield)); + return raw_read_memory(shadow_state_get_reg_abs_addr(machine_reg::htif_iyield)); } std::pair do_poll_external_interrupts(uint64_t mcycle, uint64_t /*mcycle_max*/) {