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prev_cmp_DE2_i2sound.qmsg
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prev_cmp_DE2_i2sound.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 20 16:33:13 2007 " "Info: Processing started: Wed Jun 20 16:33:13 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_i2sound -c DE2_i2sound " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_i2sound -c DE2_i2sound" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_i2sound.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_i2sound.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_i2sound " "Info: Found entity 1: DE2_i2sound" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLOCK_500.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CLOCK_500.v" { { "Info" "ISGN_ENTITY_NAME" "1 CLOCK_500 " "Info: Found entity 1: CLOCK_500" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 44 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 42 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keytr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file keytr.v" { { "Info" "ISGN_ENTITY_NAME" "1 keytr " "Info: Found entity 1: keytr" { } { { "keytr.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/keytr.v" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_i2sound " "Info: Elaborating entity \"DE2_i2sound\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PIN_IGNORED" "AUD_BCLK " "Warning: Pin \"AUD_BCLK\" not connected" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 400 1048 1216 416 "AUD_BCLK" "" } } } } } 0 0 "Pin \"%1!s!\" not connected" 0 0 "" 0}
{ "Warning" "WGDFX_PIN_IGNORED" "AUD_DACLRCK " "Warning: Pin \"AUD_DACLRCK\" not connected" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 432 1048 1216 448 "AUD_DACLRCK" "" } } } } } 0 0 "Pin \"%1!s!\" not connected" 0 0 "" 0}
{ "Warning" "WGDFX_PIN_IGNORED" "AUD_ADCLRCK " "Warning: Pin \"AUD_ADCLRCK\" not connected" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 448 1048 1216 464 "AUD_ADCLRCK" "" } } } } } 0 0 "Pin \"%1!s!\" not connected" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c i2c:inst " "Info: Elaborating entity \"i2c\" for hierarchy \"i2c:inst\"" { } { { "DE2_i2sound.bdf" "inst" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 72 696 936 232 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(78) " "Warning (10230): Verilog HDL assignment warning at i2c.v(78): truncated value with size 32 to match size of target (1)" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 78 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(77) " "Warning (10230): Verilog HDL assignment warning at i2c.v(77): truncated value with size 32 to match size of target (1)" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 77 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 i2c.v(90) " "Warning (10230): Verilog HDL assignment warning at i2c.v(90): truncated value with size 32 to match size of target (6)" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 90 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLOCK_500 CLOCK_500:inst4 " "Info: Elaborating entity \"CLOCK_500\" for hierarchy \"CLOCK_500:inst4\"" { } { { "DE2_i2sound.bdf" "inst4" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 72 400 552 200 "inst4" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CLOCK_500.v(72) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(72): truncated value with size 32 to match size of target (1)" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 72 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 CLOCK_500.v(76) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(76): truncated value with size 32 to match size of target (6)" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 76 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 CLOCK_500.v(82) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(82): truncated value with size 32 to match size of target (8)" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 82 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 CLOCK_500.v(104) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(104): truncated value with size 32 to match size of target (11)" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keytr keytr:inst1 " "Info: Elaborating entity \"keytr\" for hierarchy \"keytr:inst1\"" { } { { "DE2_i2sound.bdf" "inst1" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 272 392 536 368 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 keytr.v(65) " "Warning (10230): Verilog HDL assignment warning at keytr.v(65): truncated value with size 32 to match size of target (1)" { } { { "keytr.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/keytr.v" 65 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 keytr.v(71) " "Warning (10230): Verilog HDL assignment warning at keytr.v(71): truncated value with size 32 to match size of target (10)" { } { { "keytr.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/keytr.v" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CLOCK_500:inst4\|DATA_A\[15\] data_in GND " "Warning: Reduced register \"CLOCK_500:inst4\|DATA_A\[15\]\" with stuck data_in port to stuck value GND" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CLOCK_500:inst4\|DATA_A\[14\] data_in GND " "Warning: Reduced register \"CLOCK_500:inst4\|DATA_A\[14\]\" with stuck data_in port to stuck value GND" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CLOCK_500:inst4\|DATA_A\[13\] data_in GND " "Warning: Reduced register \"CLOCK_500:inst4\|DATA_A\[13\]\" with stuck data_in port to stuck value GND" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CLOCK_500:inst4\|DATA_A\[8\] data_in GND " "Warning: Reduced register \"CLOCK_500:inst4\|DATA_A\[8\]\" with stuck data_in port to stuck value GND" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[23\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[23\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[22\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[22\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst\|SD\[21\] High " "Info: Power-up level of register \"i2c:inst\|SD\[21\]\" is not specified -- using power-up level of High to minimize register" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[21\] data_in VCC " "Warning: Reduced register \"i2c:inst\|SD\[21\]\" with stuck data_in port to stuck value VCC" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst\|SD\[20\] High " "Info: Power-up level of register \"i2c:inst\|SD\[20\]\" is not specified -- using power-up level of High to minimize register" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[20\] data_in VCC " "Warning: Reduced register \"i2c:inst\|SD\[20\]\" with stuck data_in port to stuck value VCC" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[19\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[19\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst\|SD\[18\] High " "Info: Power-up level of register \"i2c:inst\|SD\[18\]\" is not specified -- using power-up level of High to minimize register" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[18\] data_in VCC " "Warning: Reduced register \"i2c:inst\|SD\[18\]\" with stuck data_in port to stuck value VCC" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[17\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[17\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[16\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[16\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[15\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[15\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[14\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[14\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[13\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[13\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[8\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[8\]\" with stuck data_in port to stuck value GND" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst4/vol\[7\] " "Info: Register \"inst4/vol\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "AUD_BCLK " "Warning: No output dependent on input pin \"AUD_BCLK\"" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 400 1048 1216 416 "AUD_BCLK" "" } } } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "AUD_DACLRCK " "Warning: No output dependent on input pin \"AUD_DACLRCK\"" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 432 1048 1216 448 "AUD_DACLRCK" "" } } } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "AUD_ADCLRCK " "Warning: No output dependent on input pin \"AUD_ADCLRCK\"" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 448 1048 1216 464 "AUD_ADCLRCK" "" } } } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "113 " "Info: Implemented 113 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "102 " "Info: Implemented 102 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 20 16:33:16 2007 " "Info: Processing ended: Wed Jun 20 16:33:16 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 20 16:33:17 2007 " "Info: Processing started: Wed Jun 20 16:33:17 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_i2sound -c DE2_i2sound " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_i2sound -c DE2_i2sound" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_i2sound EP2C35F672C8 " "Info: Selected device EP2C35F672C8 for design \"DE2_i2sound\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F672I8 " "Info: Device EP2C35F672I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C8 " "Info: Device EP2C50F672C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672I8 " "Info: Device EP2C50F672I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C8 " "Info: Device EP2C70F672C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672I8 " "Info: Device EP2C70F672I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 11 " "Warning: No exact pin location assignment(s) for 1 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "KEYON " "Info: Pin KEYON not assigned to an exact location on the device" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 312 616 792 328 "KEYON" "" } { 304 536 616 320 "KEYON" "" } { 120 344 400 136 "KEYON" "" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEYON } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEYON } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "50MHZ (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node 50MHZ (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CLOCK_500:inst4\|COUNTER_500\[9\] " "Info: Destination node CLOCK_500:inst4\|COUNTER_500\[9\]" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0} } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "50MHZ" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_500:inst4\|COUNTER_500\[9\] " "Info: Automatically promoted node CLOCK_500:inst4\|COUNTER_500\[9\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c:inst\|I2C_SCLK~253 " "Info: Destination node i2c:inst\|I2C_SCLK~253" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 62 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|I2C_SCLK~253 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|I2C_SCLK~253 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "keytr:inst1\|KEYON " "Info: Destination node keytr:inst1\|KEYON" { } { { "keytr.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/keytr.v" 57 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { keytr:inst1|KEYON } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { keytr:inst1|KEYON } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c:inst\|END " "Info: Destination node i2c:inst\|END" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|END } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CLOCK_500:inst4\|COUNTER_500\[9\]~42 " "Info: Destination node CLOCK_500:inst4\|COUNTER_500\[9\]~42" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|COUNTER_500[9]~42 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|COUNTER_500[9]~42 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0} } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "i2c:inst\|END " "Info: Automatically promoted node i2c:inst\|END " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CLOCK_500:inst4\|GO~33 " "Info: Destination node CLOCK_500:inst4\|GO~33" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 58 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|GO~33 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|GO~33 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c:inst\|END~120 " "Info: Destination node i2c:inst\|END~120" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|END~120 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|END~120 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0} } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|END } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "keytr:inst1\|KEYON " "Info: Automatically promoted node keytr:inst1\|KEYON " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "KEYON " "Info: Destination node KEYON" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 312 616 792 328 "KEYON" "" } { 304 536 616 320 "KEYON" "" } { 120 344 400 136 "KEYON" "" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEYON } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEYON } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0} } { { "keytr.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/keytr.v" 57 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { keytr:inst1|KEYON } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { keytr:inst1|KEYON } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "keytr:inst1\|comb~0 " "Info: Automatically promoted node keytr:inst1\|comb~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { keytr:inst1|comb~0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { keytr:inst1|comb~0 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0} } { } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 64 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 64 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 3 56 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 56 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 8 48 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used -- 48 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 58 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 1 64 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 64 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 1 58 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 58 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 58 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 56 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 56 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ACK " "Warning: Node \"ACK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ACK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.520 ns register register " "Info: Estimated most critical path is register to register delay of 4.520 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLOCK_500:inst4\|address\[0\] 1 REG LAB_X37_Y11 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X37_Y11; Fanout = 13; REG Node = 'CLOCK_500:inst4\|address\[0\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|address[0] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 76 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.624 ns) 1.602 ns CLOCK_500:inst4\|LessThan0~84 2 COMB LAB_X37_Y13 1 " "Info: 2: + IC(0.978 ns) + CELL(0.624 ns) = 1.602 ns; Loc. = LAB_X37_Y13; Fanout = 1; COMB Node = 'CLOCK_500:inst4\|LessThan0~84'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.602 ns" { CLOCK_500:inst4|address[0] CLOCK_500:inst4|LessThan0~84 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.206 ns) 2.414 ns CLOCK_500:inst4\|LessThan0~85 3 COMB LAB_X37_Y13 7 " "Info: 3: + IC(0.606 ns) + CELL(0.206 ns) = 2.414 ns; Loc. = LAB_X37_Y13; Fanout = 7; COMB Node = 'CLOCK_500:inst4\|LessThan0~85'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.812 ns" { CLOCK_500:inst4|LessThan0~84 CLOCK_500:inst4|LessThan0~85 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.161 ns) + CELL(0.615 ns) 3.190 ns CLOCK_500:inst4\|GO~33 4 COMB LAB_X37_Y13 6 " "Info: 4: + IC(0.161 ns) + CELL(0.615 ns) = 3.190 ns; Loc. = LAB_X37_Y13; Fanout = 6; COMB Node = 'CLOCK_500:inst4\|GO~33'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.776 ns" { CLOCK_500:inst4|LessThan0~85 CLOCK_500:inst4|GO~33 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 58 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.660 ns) 4.520 ns i2c:inst\|SD_COUNTER\[1\] 5 REG LAB_X38_Y13 12 " "Info: 5: + IC(0.670 ns) + CELL(0.660 ns) = 4.520 ns; Loc. = LAB_X38_Y13; Fanout = 12; REG Node = 'i2c:inst\|SD_COUNTER\[1\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.330 ns" { CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[1] } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.105 ns ( 46.57 % ) " "Info: Total cell delay = 2.105 ns ( 46.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.415 ns ( 53.43 % ) " "Info: Total interconnect delay = 2.415 ns ( 53.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.520 ns" { CLOCK_500:inst4|address[0] CLOCK_500:inst4|LessThan0~84 CLOCK_500:inst4|LessThan0~85 CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[1] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X33_Y0 X43_Y11 " "Info: The peak interconnect region extends from location X33_Y0 to location X43_Y11" { } { } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "KEYON 0 " "Info: Pin \"KEYON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "i2c:inst\|SDO (inverted) " "Info: Following pins have the same output enable: i2c:inst\|SDO (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional I2C_SDAT 3.3-V LVTTL " "Info: Type bidirectional pin I2C_SDAT uses the 3.3-V LVTTL I/O standard" { } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 1024 1200 112 "I2C_SDAT" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} } { } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.fit.smsg " "Info: Generated suppressed messages file D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Allocated 242 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 20 16:33:32 2007 " "Info: Processing ended: Wed Jun 20 16:33:32 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 20 16:33:33 2007 " "Info: Processing started: Wed Jun 20 16:33:33 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DE2_i2sound -c DE2_i2sound " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE2_i2sound -c DE2_i2sound" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Allocated 194 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 20 16:33:48 2007 " "Info: Processing ended: Wed Jun 20 16:33:48 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 20 16:33:49 2007 " "Info: Processing started: Wed Jun 20 16:33:49 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DE2_i2sound -c DE2_i2sound --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE2_i2sound -c DE2_i2sound --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "keytr:inst1\|KEYON " "Info: Detected ripple clock \"keytr:inst1\|KEYON\" as buffer" { } { { "keytr.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/keytr.v" 57 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "keytr:inst1\|KEYON" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst\|END " "Info: Detected ripple clock \"i2c:inst\|END\" as buffer" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst\|END" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CLOCK_500:inst4\|COUNTER_500\[9\] " "Info: Detected ripple clock \"CLOCK_500:inst4\|COUNTER_500\[9\]\" as buffer" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_500:inst4\|COUNTER_500\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "50MHZ register i2c:inst\|SD_COUNTER\[4\] register i2c:inst\|END 13.162 ns " "Info: Slack time is 13.162 ns for clock \"50MHZ\" between source register \"i2c:inst\|SD_COUNTER\[4\]\" and destination register \"i2c:inst\|END\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "146.24 MHz 6.838 ns " "Info: Fmax is 146.24 MHz (period= 6.838 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "15.860 ns + Largest register register " "Info: + Largest register to register requirement is 15.860 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.876 ns + Largest " "Info: + Largest clock skew is -3.876 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ destination 6.370 ns + Shortest register " "Info: + Shortest clock path from clock \"50MHZ\" to destination register is 6.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns 50MHZ 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.526 ns) + CELL(0.970 ns) 4.606 ns CLOCK_500:inst4\|COUNTER_500\[9\] 2 REG LCFF_X37_Y13_N27 6 " "Info: 2: + IC(2.526 ns) + CELL(0.970 ns) = 4.606 ns; Loc. = LCFF_X37_Y13_N27; Fanout = 6; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.496 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.666 ns) 6.370 ns i2c:inst\|END 3 REG LCFF_X37_Y12_N29 3 " "Info: 3: + IC(1.098 ns) + CELL(0.666 ns) = 6.370 ns; Loc. = LCFF_X37_Y12_N29; Fanout = 3; REG Node = 'i2c:inst\|END'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.764 ns" { CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.746 ns ( 43.11 % ) " "Info: Total cell delay = 2.746 ns ( 43.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.624 ns ( 56.89 % ) " "Info: Total interconnect delay = 3.624 ns ( 56.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.370 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.370 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } { 0.000ns 0.000ns 2.526ns 1.098ns } { 0.000ns 1.110ns 0.970ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ source 10.246 ns - Longest register " "Info: - Longest clock path from clock \"50MHZ\" to source register is 10.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns 50MHZ 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.526 ns) + CELL(0.970 ns) 4.606 ns CLOCK_500:inst4\|COUNTER_500\[9\] 2 REG LCFF_X37_Y13_N27 6 " "Info: 2: + IC(2.526 ns) + CELL(0.970 ns) = 4.606 ns; Loc. = LCFF_X37_Y13_N27; Fanout = 6; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.496 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.792 ns) + CELL(0.000 ns) 8.398 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 3 COMB CLKCTRL_G13 30 " "Info: 3: + IC(3.792 ns) + CELL(0.000 ns) = 8.398 ns; Loc. = CLKCTRL_G13; Fanout = 30; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.792 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.666 ns) 10.246 ns i2c:inst\|SD_COUNTER\[4\] 4 REG LCFF_X38_Y13_N25 7 " "Info: 4: + IC(1.182 ns) + CELL(0.666 ns) = 10.246 ns; Loc. = LCFF_X38_Y13_N25; Fanout = 7; REG Node = 'i2c:inst\|SD_COUNTER\[4\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.746 ns ( 26.80 % ) " "Info: Total cell delay = 2.746 ns ( 26.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 73.20 % ) " "Info: Total interconnect delay = 7.500 ns ( 73.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.370 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.370 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } { 0.000ns 0.000ns 2.526ns 1.098ns } { 0.000ns 1.110ns 0.970ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.370 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.370 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } { 0.000ns 0.000ns 2.526ns 1.098ns } { 0.000ns 1.110ns 0.970ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.698 ns - Longest register register " "Info: - Longest register to register delay is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c:inst\|SD_COUNTER\[4\] 1 REG LCFF_X38_Y13_N25 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y13_N25; Fanout = 7; REG Node = 'i2c:inst\|SD_COUNTER\[4\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|SD_COUNTER[4] } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.370 ns) 0.886 ns i2c:inst\|Decoder0~214 2 COMB LCCOMB_X38_Y13_N8 4 " "Info: 2: + IC(0.516 ns) + CELL(0.370 ns) = 0.886 ns; Loc. = LCCOMB_X38_Y13_N8; Fanout = 4; COMB Node = 'i2c:inst\|Decoder0~214'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.886 ns" { i2c:inst|SD_COUNTER[4] i2c:inst|Decoder0~214 } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.624 ns) 2.590 ns i2c:inst\|END~120 3 COMB LCCOMB_X37_Y12_N28 1 " "Info: 3: + IC(1.080 ns) + CELL(0.624 ns) = 2.590 ns; Loc. = LCCOMB_X37_Y12_N28; Fanout = 1; COMB Node = 'i2c:inst\|END~120'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.704 ns" { i2c:inst|Decoder0~214 i2c:inst|END~120 } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.698 ns i2c:inst\|END 4 REG LCFF_X37_Y12_N29 3 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.698 ns; Loc. = LCFF_X37_Y12_N29; Fanout = 3; REG Node = 'i2c:inst\|END'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { i2c:inst|END~120 i2c:inst|END } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.102 ns ( 40.85 % ) " "Info: Total cell delay = 1.102 ns ( 40.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.596 ns ( 59.15 % ) " "Info: Total interconnect delay = 1.596 ns ( 59.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { i2c:inst|SD_COUNTER[4] i2c:inst|Decoder0~214 i2c:inst|END~120 i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { i2c:inst|SD_COUNTER[4] i2c:inst|Decoder0~214 i2c:inst|END~120 i2c:inst|END } { 0.000ns 0.516ns 1.080ns 0.000ns } { 0.000ns 0.370ns 0.624ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.370 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.370 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] i2c:inst|END } { 0.000ns 0.000ns 2.526ns 1.098ns } { 0.000ns 1.110ns 0.970ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[4] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { i2c:inst|SD_COUNTER[4] i2c:inst|Decoder0~214 i2c:inst|END~120 i2c:inst|END } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { i2c:inst|SD_COUNTER[4] i2c:inst|Decoder0~214 i2c:inst|END~120 i2c:inst|END } { 0.000ns 0.516ns 1.080ns 0.000ns } { 0.000ns 0.370ns 0.624ns 0.108ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "50MHZ register CLOCK_500:inst4\|COUNTER_500\[10\] register i2c:inst\|SD_COUNTER\[2\] -4.917 ns " "Info: Minimum slack time is -4.917 ns for clock \"50MHZ\" between source register \"CLOCK_500:inst4\|COUNTER_500\[10\]\" and destination register \"i2c:inst\|SD_COUNTER\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.142 ns + Shortest register register " "Info: + Shortest register to register delay is 2.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLOCK_500:inst4\|COUNTER_500\[10\] 1 REG LCFF_X37_Y13_N29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y13_N29; Fanout = 2; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[10\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|COUNTER_500[10] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.505 ns) 0.955 ns CLOCK_500:inst4\|GO~33 2 COMB LCCOMB_X37_Y13_N30 6 " "Info: 2: + IC(0.450 ns) + CELL(0.505 ns) = 0.955 ns; Loc. = LCCOMB_X37_Y13_N30; Fanout = 6; COMB Node = 'CLOCK_500:inst4\|GO~33'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.955 ns" { CLOCK_500:inst4|COUNTER_500[10] CLOCK_500:inst4|GO~33 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 58 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.660 ns) 2.142 ns i2c:inst\|SD_COUNTER\[2\] 3 REG LCFF_X38_Y13_N21 12 " "Info: 3: + IC(0.527 ns) + CELL(0.660 ns) = 2.142 ns; Loc. = LCFF_X38_Y13_N21; Fanout = 12; REG Node = 'i2c:inst\|SD_COUNTER\[2\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.165 ns ( 54.39 % ) " "Info: Total cell delay = 1.165 ns ( 54.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.977 ns ( 45.61 % ) " "Info: Total interconnect delay = 0.977 ns ( 45.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { CLOCK_500:inst4|COUNTER_500[10] CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.142 ns" { CLOCK_500:inst4|COUNTER_500[10] CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[2] } { 0.000ns 0.450ns 0.527ns } { 0.000ns 0.505ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.059 ns - Smallest register register " "Info: - Smallest register to register requirement is 7.059 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.057 ns + Smallest " "Info: + Smallest clock skew is 7.057 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ destination 10.246 ns + Longest register " "Info: + Longest clock path from clock \"50MHZ\" to destination register is 10.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns 50MHZ 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.526 ns) + CELL(0.970 ns) 4.606 ns CLOCK_500:inst4\|COUNTER_500\[9\] 2 REG LCFF_X37_Y13_N27 6 " "Info: 2: + IC(2.526 ns) + CELL(0.970 ns) = 4.606 ns; Loc. = LCFF_X37_Y13_N27; Fanout = 6; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.496 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.792 ns) + CELL(0.000 ns) 8.398 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 3 COMB CLKCTRL_G13 30 " "Info: 3: + IC(3.792 ns) + CELL(0.000 ns) = 8.398 ns; Loc. = CLKCTRL_G13; Fanout = 30; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.792 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.666 ns) 10.246 ns i2c:inst\|SD_COUNTER\[2\] 4 REG LCFF_X38_Y13_N21 12 " "Info: 4: + IC(1.182 ns) + CELL(0.666 ns) = 10.246 ns; Loc. = LCFF_X38_Y13_N21; Fanout = 12; REG Node = 'i2c:inst\|SD_COUNTER\[2\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.746 ns ( 26.80 % ) " "Info: Total cell delay = 2.746 ns ( 26.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 73.20 % ) " "Info: Total interconnect delay = 7.500 ns ( 73.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ source 3.189 ns - Shortest register " "Info: - Shortest clock path from clock \"50MHZ\" to source register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns 50MHZ 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns 50MHZ~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = '50MHZ~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { 50MHZ 50MHZ~clkctrl } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.174 ns) + CELL(0.666 ns) 3.189 ns CLOCK_500:inst4\|COUNTER_500\[10\] 3 REG LCFF_X37_Y13_N29 2 " "Info: 3: + IC(1.174 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X37_Y13_N29; Fanout = 2; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[10\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.840 ns" { 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.69 % ) " "Info: Total cell delay = 1.776 ns ( 55.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.413 ns ( 44.31 % ) " "Info: Total interconnect delay = 1.413 ns ( 44.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" { } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { CLOCK_500:inst4|COUNTER_500[10] CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.142 ns" { CLOCK_500:inst4|COUNTER_500[10] CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[2] } { 0.000ns 0.450ns 0.527ns } { 0.000ns 0.505ns 0.660ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[2] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[10] } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "50MHZ 12 " "Warning: Can't achieve minimum setup and hold requirement 50MHZ along 12 path(s). See Report window for details." { } { } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "50MHZ I2C_SCLK i2c:inst\|SD_COUNTER\[0\] 21.068 ns register " "Info: tco from clock \"50MHZ\" to destination pin \"I2C_SCLK\" through register \"i2c:inst\|SD_COUNTER\[0\]\" is 21.068 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ source 10.246 ns + Longest register " "Info: + Longest clock path from clock \"50MHZ\" to source register is 10.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns 50MHZ 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.526 ns) + CELL(0.970 ns) 4.606 ns CLOCK_500:inst4\|COUNTER_500\[9\] 2 REG LCFF_X37_Y13_N27 6 " "Info: 2: + IC(2.526 ns) + CELL(0.970 ns) = 4.606 ns; Loc. = LCFF_X37_Y13_N27; Fanout = 6; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.496 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.792 ns) + CELL(0.000 ns) 8.398 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 3 COMB CLKCTRL_G13 30 " "Info: 3: + IC(3.792 ns) + CELL(0.000 ns) = 8.398 ns; Loc. = CLKCTRL_G13; Fanout = 30; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.792 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.666 ns) 10.246 ns i2c:inst\|SD_COUNTER\[0\] 4 REG LCFF_X38_Y13_N17 15 " "Info: 4: + IC(1.182 ns) + CELL(0.666 ns) = 10.246 ns; Loc. = LCFF_X38_Y13_N17; Fanout = 15; REG Node = 'i2c:inst\|SD_COUNTER\[0\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.746 ns ( 26.80 % ) " "Info: Total cell delay = 2.746 ns ( 26.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 73.20 % ) " "Info: Total interconnect delay = 7.500 ns ( 73.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.518 ns + Longest register pin " "Info: + Longest register to pin delay is 10.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c:inst\|SD_COUNTER\[0\] 1 REG LCFF_X38_Y13_N17 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y13_N17; Fanout = 15; REG Node = 'i2c:inst\|SD_COUNTER\[0\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.614 ns) 1.152 ns i2c:inst\|LessThan2~72 2 COMB LCCOMB_X38_Y13_N10 2 " "Info: 2: + IC(0.538 ns) + CELL(0.614 ns) = 1.152 ns; Loc. = LCCOMB_X38_Y13_N10; Fanout = 2; COMB Node = 'i2c:inst\|LessThan2~72'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.152 ns" { i2c:inst|SD_COUNTER[0] i2c:inst|LessThan2~72 } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 90 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.684 ns) + CELL(0.370 ns) 2.206 ns i2c:inst\|I2C_SCLK~252 3 COMB LCCOMB_X37_Y13_N8 1 " "Info: 3: + IC(0.684 ns) + CELL(0.370 ns) = 2.206 ns; Loc. = LCCOMB_X37_Y13_N8; Fanout = 1; COMB Node = 'i2c:inst\|I2C_SCLK~252'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.054 ns" { i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 62 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.624 ns) 3.195 ns i2c:inst\|I2C_SCLK~253 4 COMB LCCOMB_X37_Y13_N4 1 " "Info: 4: + IC(0.365 ns) + CELL(0.624 ns) = 3.195 ns; Loc. = LCCOMB_X37_Y13_N4; Fanout = 1; COMB Node = 'i2c:inst\|I2C_SCLK~253'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.989 ns" { i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 } "NODE_NAME" } } { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 62 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.077 ns) + CELL(3.246 ns) 10.518 ns I2C_SCLK 5 PIN PIN_A6 0 " "Info: 5: + IC(4.077 ns) + CELL(3.246 ns) = 10.518 ns; Loc. = PIN_A6; Fanout = 0; PIN Node = 'I2C_SCLK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.323 ns" { i2c:inst|I2C_SCLK~253 I2C_SCLK } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 112 1024 1200 128 "I2C_SCLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.854 ns ( 46.15 % ) " "Info: Total cell delay = 4.854 ns ( 46.15 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.664 ns ( 53.85 % ) " "Info: Total interconnect delay = 5.664 ns ( 53.85 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.518 ns" { i2c:inst|SD_COUNTER[0] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.518 ns" { i2c:inst|SD_COUNTER[0] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } { 0.000ns 0.538ns 0.684ns 0.365ns 4.077ns } { 0.000ns 0.614ns 0.370ns 0.624ns 3.246ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.246 ns" { 50MHZ CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.246 ns" { 50MHZ 50MHZ~combout CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } { 0.000ns 0.000ns 2.526ns 3.792ns 1.182ns } { 0.000ns 1.110ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.518 ns" { i2c:inst|SD_COUNTER[0] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.518 ns" { i2c:inst|SD_COUNTER[0] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } { 0.000ns 0.538ns 0.684ns 0.365ns 4.077ns } { 0.000ns 0.614ns 0.370ns 0.624ns 3.246ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "AUD_ADCDAT AUD_DACDAT 10.515 ns Longest " "Info: Longest tpd from source pin \"AUD_ADCDAT\" to destination pin \"AUD_DACDAT\" is 10.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns AUD_ADCDAT 1 PIN PIN_B5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_B5; Fanout = 1; PIN Node = 'AUD_ADCDAT'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 368 1048 1216 384 "AUD_ADCDAT" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.295 ns) + CELL(3.256 ns) 10.515 ns AUD_DACDAT 2 PIN PIN_A4 0 " "Info: 2: + IC(6.295 ns) + CELL(3.256 ns) = 10.515 ns; Loc. = PIN_A4; Fanout = 0; PIN Node = 'AUD_DACDAT'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.551 ns" { AUD_ADCDAT AUD_DACDAT } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 280 1032 1208 296 "AUD_DACDAT" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.220 ns ( 40.13 % ) " "Info: Total cell delay = 4.220 ns ( 40.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.295 ns ( 59.87 % ) " "Info: Total interconnect delay = 6.295 ns ( 59.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.515 ns" { AUD_ADCDAT AUD_DACDAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.515 ns" { AUD_ADCDAT AUD_ADCDAT~combout AUD_DACDAT } { 0.000ns 0.000ns 6.295ns } { 0.000ns 0.964ns 3.256ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Critical Warning" "WTAN_REQUIREMENTS_NOT_MET_SLOW" "" "Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details." { } { } 1 0 "Timing requirements for slow timing model timing analysis were not met. See Report window for details." 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 20 16:33:51 2007 " "Info: Processing ended: Wed Jun 20 16:33:51 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 40 s " "Info: Quartus II Full Compilation was successful. 0 errors, 40 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}