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audio_serial_to_parallel_testbench.v.bak
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audio_serial_to_parallel_testbench.v.bak
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module audio_serial_to_parallel_testbench;
reg bck;
reg lrck;
reg dat;
reg [15:0] outl;
reg [15:0] outr;
parameter stimDelay = 10;
audio_serial_to_parallel DUT(bck, lrck, dat, outl, outr);
initial
begin
bck = 0; lrck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; lrck=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;//msb 1
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;//9
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0; //lsb
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; //no data
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; //no data
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; lrck=0; //lrclk switch to left channel
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1; //MSB left
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=0;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1;
#(stimDelay) bck = 1;
#(stimDelay) bck = 0; dat=1; //LSB left
#(stimDelay) bck = 1;
#(stimDelay) bck = 0;
#100; //Let simulation finish
end
endmodule