lab5_pong.vhd.bak

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lab5_pong is
  port(CLOCK_50            : in  std_logic;
       KEY                 : in  std_logic_vector(3 downto 0);
       SW                  : in  std_logic_vector(17 downto 0);
		 
		 LEDR						: out std_logic_vector(17 downto 0);		-- for debugging
		 
       VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);  -- The outs go to VGA controller
       VGA_HS              : out std_logic;
       VGA_VS              : out std_logic;
       VGA_BLANK           : out std_logic;
       VGA_SYNC            : out std_logic;
       VGA_CLK             : out std_logic
	);
end lab5_pong;

architecture rtl of lab5_pong is

 --Component from the Verilog file: vga_adapter.v

  component vga_adapter
    generic(RESOLUTION : string);
    port (resetn                                       : in  std_logic;
          clock                                        : in  std_logic;
          colour                                       : in  std_logic_vector(2 downto 0);
          x                                            : in  std_logic_vector(7 downto 0);
          y                                            : in  std_logic_vector(6 downto 0);
          plot                                         : in  std_logic;
          VGA_R, VGA_G, VGA_B                          : out std_logic_vector(9 downto 0);
          VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic);
  end component;

  
	component fsm is
		port( clock: in std_logic;
				nextStep: in std_logic;
				reset: in std_logic;
				done : in std_logic;
				x0: out std_logic_vector( 7 downto 0);
				y0: out std_logic_vector( 6 downto 0);
				mode: out std_logic_vector(1 downto 0) -- 0 = erase, 1 = idle, 2 = drawLine
				
			);
	end component;
	
	component DataPath IS
		PORT(
			clock : IN STD_LOGIC;
--			reset : IN std_logic;
			mode  : IN std_logic_vector(1 downto 0);
			done 	: out std_logic;
			x0			: in  std_logic_vector(7 downto 0);
			y0			: in  std_logic_vector(6 downto 0);
			x1			: in  std_logic_vector(7 downto 0);
			y1			: in  std_logic_vector(6 downto 0);	
			colour   : out  std_logic_vector(2 downto 0);
			colour_sw: in	 std_logic_vector(2 downto 0);
			x        : out  std_logic_vector(7 downto 0);
			y        : out  std_logic_vector(6 downto 0);
			plot		: out std_logic
		);
	END component;
  
  signal x      : std_logic_vector(7 downto 0);
  signal y      : std_logic_vector(6 downto 0);
  signal x0     : std_logic_vector(7 downto 0);
  signal y0     : std_logic_vector(6 downto 0);
  signal mode   : std_logic_vector(1 downto 0);
  signal colour : std_logic_vector(2 downto 0);
  signal plot   : std_logic;
  signal done	 : std_logic;
  
  
begin

  -- includes the vga adapter, which should be in your project 
  vga_u0 : vga_adapter
    generic map(RESOLUTION => "160x120") 
    port map(resetn    => KEY(3),
             clock     => CLOCK_50,
             colour    => colour,
             x         => x,
             y         => y,
             plot      => plot,
             VGA_R     => VGA_R,
             VGA_G     => VGA_G,
             VGA_B     => VGA_B,
             VGA_HS    => VGA_HS,
             VGA_VS    => VGA_VS,
             VGA_BLANK => VGA_BLANK,
             VGA_SYNC  => VGA_SYNC,
             VGA_CLK   => VGA_CLK);
	
		U0: fsm 
		port map( clock => CLOCK_50, nextStep => KEY(0), reset => KEY(3), x0 => x0, y0 => y0, done => done, mode => mode);
		
		U1: dataPath
		port map(clock => CLOCK_50, mode => mode, done => done, x0 => x0, y0 => y0, x1 => SW(17 downto 10), 
		y1 => SW(9 downto 3), colour => colour, colour_sw => SW(2 downto 0), x => x, y => y, plot => plot);
		  

end RTL;