diff --git a/ports/stm/boards/STM32L433_boot.ld b/ports/stm/boards/STM32L433_boot.ld new file mode 100644 index 000000000000..8169eadebe11 --- /dev/null +++ b/ports/stm/boards/STM32L433_boot.ld @@ -0,0 +1,38 @@ +/* + GNU linker script for STM32L433 with bootloader +*/ + +/* Specify the memory areas */ +/* +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k + FLASH_ISR (rx) : ORIGIN = 0x08010000, LENGTH = 4K + FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 156K-64K-4K + FLASH_FS (rw) : ORIGIN = 0x08027000, LENGTH = 88K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} +*/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */ + FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 1024K-128K-64K-4K /* For now, limit to 1MB so that bank switching is still possible. */ + FLASH_FS (rw) : ORIGIN = 0x08100000, LENGTH = 1024K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K +} + + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 24K; +_minimum_heap_size = 16K; + +/* Define the top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); diff --git a/ports/stm/boards/STM32L433_default.ld b/ports/stm/boards/STM32L433_default.ld new file mode 100644 index 000000000000..23454521bb9f --- /dev/null +++ b/ports/stm/boards/STM32L433_default.ld @@ -0,0 +1,33 @@ +/* + GNU linker script for STM32L433 with filesystem +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 4K /* ISR vector. Kind of wasteful. */ + /* + FLASH_FIRMWARE (rx) : ORIGIN = 0x08001000, LENGTH = 60K + FLASH_FS (rw) : ORIGIN = 0x08010000, LENGTH = 60K + */ + FLASH_FIRMWARE (rx) : ORIGIN = 0x08001000, LENGTH = 4K + FLASH_FS (rw) : ORIGIN = 0x08004000, LENGTH = 60K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 24K; +_minimum_heap_size = 16K; + +/* Define the top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); + +/* ensure the firmware is within bounds */ +ASSERT ( (ORIGIN(FLASH_FIRMWARE) + LENGTH(FLASH_FIRMWARE)) <= (ORIGIN(FLASH)+LENGTH(FLASH)), "FLASH_FIRMWARE out of bounds" ); diff --git a/ports/stm/boards/STM32L4R5_default.ld b/ports/stm/boards/STM32L4R5_default.ld index 1bffcee04ed6..b58db53b3769 100644 --- a/ports/stm/boards/STM32L4R5_default.ld +++ b/ports/stm/boards/STM32L4R5_default.ld @@ -16,7 +16,7 @@ MEMORY _minimum_stack_size = 24K; _minimum_heap_size = 16K; -/* Define tho top end of the stack. The stack is full descending so begins just +/* Define the top end of the stack. The stack is full descending so begins just above last byte of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ _estack = ORIGIN(RAM) + LENGTH(RAM); diff --git a/ports/stm/boards/cygnet/board.c b/ports/stm/boards/cygnet/board.c new file mode 100644 index 000000000000..80875e837584 --- /dev/null +++ b/ports/stm/boards/cygnet/board.c @@ -0,0 +1,75 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries +// +// SPDX-License-Identifier: MIT + +#include "supervisor/board.h" +#include "mpconfigboard.h" + +#include "stm32l4xx.h" +#include "stm32l433xx.h" + +#include "shared-bindings/microcontroller/Pin.h" +#include "shared-bindings/digitalio/DigitalInOut.h" +#include "shared-bindings/digitalio/Direction.h" +#include "shared-bindings/digitalio/DriveMode.h" +#include "board.h" + +digitalio_digitalinout_obj_t power_pin = { .base.type = &digitalio_digitalinout_type }; +digitalio_digitalinout_obj_t discharge_pin = { .base.type = &digitalio_digitalinout_type }; + +void initialize_discharge_pin(void) { + + /* Initialize the 3V3 discharge to be OFF and the output power to be ON */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + + common_hal_digitalio_digitalinout_construct(&power_pin, &pin_PE04); + common_hal_digitalio_digitalinout_construct(&discharge_pin, &pin_PE06); + common_hal_digitalio_digitalinout_never_reset(&power_pin); + common_hal_digitalio_digitalinout_never_reset(&discharge_pin); + + GPIO_InitTypeDef GPIO_InitStruct; + /* Set the DISCHARGE pin and the USB_DETECT pin to FLOAT */ + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pin = GPIO_PIN_6; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); /* PE6 DISCHRG */ + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /* PC6 is USB_DETECT */ + + /* Turn on the 3V3 regulator */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_LOW; + GPIO_InitStruct.Pin = GPIO_PIN_4; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_SET); + +} + +void board_init(void) { + // enable the debugger while sleeping. Todo move somewhere more central (kind of generally useful in a debug build) + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + + // Set tick interrupt priority, default HAL value is intentionally invalid + // Without this, USB does not function. + HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_LOW; + GPIO_InitStruct.Pin = GPIO_PIN_2; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_SET); + HAL_Delay(50); + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_RESET); +} + +void reset_board(void) { + initialize_discharge_pin(); +} + +// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. diff --git a/ports/stm/boards/cygnet/board.h b/ports/stm/boards/cygnet/board.h new file mode 100644 index 000000000000..ce199359ba49 --- /dev/null +++ b/ports/stm/boards/cygnet/board.h @@ -0,0 +1,12 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries +// +// SPDX-License-Identifier: MIT + +#pragma once + +#include "common-hal/digitalio/DigitalInOut.h" + +extern digitalio_digitalinout_obj_t power_pin; +extern digitalio_digitalinout_obj_t discharge_pin; diff --git a/ports/stm/boards/cygnet/mpconfigboard.h b/ports/stm/boards/cygnet/mpconfigboard.h new file mode 100644 index 000000000000..f3b1fcc2eb72 --- /dev/null +++ b/ports/stm/boards/cygnet/mpconfigboard.h @@ -0,0 +1,47 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2024 Blues Wireless Contributors. +// +// SPDX-License-Identifier: MIT + +#pragma once + +// Micropython setup + +#define MICROPY_HW_BOARD_NAME "Cygnet" +#define MICROPY_HW_MCU_NAME "STM32L433CCT6" + +#define MICROPY_PY_SYS_PLATFORM MICROPY_HW_BOARD_NAME + +#define STM32L433XX +#define BOARD_CYGNET + +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) +#define BOARD_HAS_HIGH_SPEED_CRYSTAL (0) + +// Increase drive strength of 32kHz external crystal, in line with calculations specified in ST AN2867 sections 3.3, 3.4, and STM32L4 datasheet DS12023 Table 58. LSE oscillator characteristics. +// The drive strength RCC_LSEDRIVE_LOW is marginal for the 32kHz crystal oscillator stability, and RCC_LSEDRIVE_MEDIUMLOW meets the calculated drive strength with a small margin for parasitic capacitance. +#define BOARD_LSE_DRIVE_LEVEL RCC_LSEDRIVE_MEDIUMLOW + +// Bootloader only +#ifdef UF2_BOOTLOADER_ENABLED + #define BOARD_VTOR_DEFER (1) // Leave VTOR relocation to bootloader +#endif + +#define BOARD_NO_VBUS_SENSE (1) +#define BOARD_NO_USB_OTG_ID_SENSE (1) + +#define DEFAULT_I2C_BUS_SCL (&pin_PB06) +#define DEFAULT_I2C_BUS_SDA (&pin_PB07) + +#define DEFAULT_SPI_BUS_SS (&pin_PB08) +#define DEFAULT_SPI_BUS_SCK (&pin_PA05) +#define DEFAULT_SPI_BUS_MOSI (&pin_PB05) +#define DEFAULT_SPI_BUS_MISO (&pin_PB06) + +#define DEFAULT_UART_BUS_RX (&pin_PA10) +#define DEFAULT_UART_BUS_TX (&pin_PA09) + +#define CYGNET_DISCHARGE_3V3 (&pin_PH01) +#define CYGNET_ENABLE_3V3 (&pin_PH00) diff --git a/ports/stm/boards/cygnet/mpconfigboard.mk b/ports/stm/boards/cygnet/mpconfigboard.mk new file mode 100644 index 000000000000..fa0516a5a3aa --- /dev/null +++ b/ports/stm/boards/cygnet/mpconfigboard.mk @@ -0,0 +1,58 @@ +USB_VID = 0x30A4 +USB_PID = 0x03 +USB_PRODUCT = "Cygnet" +USB_MANUFACTURER = "Blues Inc." + +MCU_SERIES = L4 +MCU_VARIANT = STM32L433xx +MCU_PACKAGE = LQFP48 + +LD_COMMON = boards/common_default.ld +LD_DEFAULT = boards/STM32L433_default.ld +# UF2 boot option +LD_BOOT = boards/STM32L433_boot.ld +UF2_OFFSET = 0x8010000 +UF2_BOOTLOADER ?= 1 +CIRCUITPY_BUILD_EXTENSIONS = bin,uf2 + +INTERNAL_FLASH_FILESYSTEM = 1 +LONGINT_IMPL = NONE +CIRCUITPY_FULL_BUILD = 0 + +CIRCUITPY_ALARM = 0 +CIRCUITPY_ANALOGIO = 1 +CIRCUITPY_AUDIOBUSIO = 0 +CIRCUITPY_AUDIOBUSIO_I2SOUT = 0 +CIRCUITPY_AUDIOBUSIO_PDMIN = 0 +CIRCUITPY_AUDIOPWMIO = 0 +CIRCUITPY_BITBANGIO = 1 +CIRCUITPY_BLEIO = 0 +CIRCUITPY_BLEIO_HCI = 0 +CIRCUITPY_BUSDEVICE = 0 +CIRCUITPY_BUSIO = 1 +CIRCUITPY_CANIO = 0 +CIRCUITPY_DIGITALIO = 1 +CIRCUITPY_DISPLAYIO = 0 +CIRCUITPY_ENABLE_MPY_NATIVE = 1 +CIRCUITPY_I2CTARGET = 0 +CIRCUITPY_KEYPAD = 0 +CIRCUITPY_MICROCONTROLLER = 1 +CIRCUITPY_NEOPIXEL_WRITE = 0 +CIRCUITPY_NVM = 0 +CIRCUITPY_OS = 1 +CIRCUITPY_PIXELBUF = 0 +CIRCUITPY_PULSEIO = 1 +CIRCUITPY_PWMIO = 1 +CIRCUITPY_RANDOM = 1 +CIRCUITPY_REQUIRE_I2C_PULLUPS = 0 +CIRCUITPY_RGBMATRIX = 0 +CIRCUITPY_RTC = 1 +CIRCUITPY_SDCARDIO = 0 +CIRCUITPY_STORAGE = 1 +CIRCUITPY_TOUCHIO = 0 +CIRCUITPY_UDB_CDC = 1 +CIRCUITPY_ULAB = 1 +CIRCUITPY_USB_HID = 0 +CIRCUITPY_USB_MIDI = 0 +CIRCUITPY_USB_MSC = 1 +CIRCUITPY_USB_VENDOR = 1 diff --git a/ports/stm/boards/cygnet/pins.c b/ports/stm/boards/cygnet/pins.c new file mode 100644 index 000000000000..ed392adc75d3 --- /dev/null +++ b/ports/stm/boards/cygnet/pins.c @@ -0,0 +1,108 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries +// +// SPDX-License-Identifier: MIT + +#include "py/objtuple.h" +#include "shared-bindings/board/__init__.h" +#include "board.h" + +// extended pins +static const mp_rom_map_elem_t board_module_carrier_table[] = { + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PE01) }, + + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA04) }, + + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_CS), MP_ROM_PTR(&pin_PB08) }, + + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) }, + + { MP_ROM_QSTR(MP_QSTR_EN), MP_ROM_PTR(&pin_PH00) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB14) }, + + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, +}; + +MP_DEFINE_CONST_DICT(board_module_carrier, board_module_carrier_table); + +MP_DEFINE_CONST_OBJ_TYPE( + carrier_type, + MP_QSTR_Ext, + MP_TYPE_FLAG_NONE, + locals_dict, &board_module_carrier + ); + + +// Core Feather Pins +static const mp_rom_map_elem_t board_module_globals_table[] = { + CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS + + { MP_ROM_QSTR(MP_QSTR_ext), MP_ROM_PTR(&carrier_type) }, + + { MP_ROM_QSTR(MP_QSTR_ENABLE_3V3), &power_pin }, + { MP_ROM_QSTR(MP_QSTR_DISCHARGE_3V3), &discharge_pin }, + + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA04) }, + + { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_SWITCH), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PB02) }, + + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PE01) }, + + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PB04) }, // ADC, PWM, DAC2 output also + + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, // PWM + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, // PWM + + { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, // D10 + { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, // D13 + + { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA05) }, + + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) }, // ADC, PWM + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) }, // PWM + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/cygnet/tests/analog_output.py b/ports/stm/boards/cygnet/tests/analog_output.py new file mode 100644 index 000000000000..6af931e65d6f --- /dev/null +++ b/ports/stm/boards/cygnet/tests/analog_output.py @@ -0,0 +1,85 @@ +import board +import analogio +import digitalio + + +def test_dac_analog(p_in, p_out): + print(f"Running dac analog test with pin {p_in} as input and {p_out} as output\n") + pin_in = analogio.AnalogIn(p_in) + pin_out = analogio.AnalogOut(p_out) + + for v in range(0, 65536, 4096): + pin_out.value = v + print(f"Value {v} read as {pin_in.value}") + + pin_in.deinit() + pin_out.deinit() + + +def test_dac_digital(p_in, p_out): + print(f"Running dac digital test with pin {p_in} as input and {p_out} as output") + pin_in = digitalio.DigitalInOut(p_in) + pin_out = analogio.AnalogOut(p_out) + + for v in range(0, 65536, 4096): + pin_out.value = v + print(f"Value {v} read as {pin_in.value}") + + pin_in.deinit() + pin_out.deinit() + + +def test_dual(pair1, pair2): + # verifies that the DACs can be set independently + print(f"Running pair test\n") + pin1_in = analogio.AnalogIn(pair1[0]) + pin1_out = analogio.AnalogOut(pair1[1]) + pin2_in = analogio.AnalogIn(pair2[0]) + pin2_out = analogio.AnalogOut(pair2[1]) + + for v in range(0, 65536, 4096): + v2 = 65535 - v + pin1_out.value = v + pin2_out.value = v2 + print(f"Pair1: Value {v} read as {pin1_in.value}") + print(f"Pair2: Value {v2} read as {pin2_in.value}") + + pin1_in.deinit() + pin1_out.deinit() + pin2_in.deinit() + pin2_out.deinit() + + +def test_analog_hilo(p_in, p_out): + print(f"Running analog hilo test with pin {p_in} as input and {p_out} as output") + pin_in = analogio.AnalogIn(p_in) + pin_out = digitalio.DigitalInOut(p_out) + pin_out.switch_to_output() + + for v in (False, True, False, True): + pin_out.value = v + print(f"Value {v} read as {pin_in.value}") + + pin_in.deinit() + pin_out.deinit() + + +def test_pair(pair): + # FIXME: test_analog_hilo works fine alone, but fails when the other dac functions are executed + test_analog_hilo(*pair) + test_dac_analog(*pair) + test_dac_digital(*pair) + + +def main(): + pair1 = (board.A3, board.DAC1) + pair2 = (board.A2, board.DAC2) + print("running DAC1 tests") + test_pair(pair1) + print("running DAC2 tests") + test_pair(pair2) + print("running dual DAC tests") + test_dual(pair1, pair2) + + +main() diff --git a/ports/stm/boards/cygnet/tests/board_voltage.py b/ports/stm/boards/cygnet/tests/board_voltage.py new file mode 100644 index 000000000000..2cb0ad4cc0f8 --- /dev/null +++ b/ports/stm/boards/cygnet/tests/board_voltage.py @@ -0,0 +1,146 @@ +# SPDX-FileCopyrightText: 2018 Shawn Hymel for Adafruit Industries +# +# SPDX-License-Identifier: MIT + +print("pins test") + +""" +`adafruit_boardtest.boardtest_gpio` +==================================================== +Toggles all available GPIO on a board. Verify their operation with an LED, +multimeter, another microcontroller, etc. + +Run this script as its own main.py to individually run the test, or compile +with mpy-cross and call from separate test script. + +* Author(s): Shawn Hymel for Adafruit Industries + +Implementation Notes +-------------------- + +**Software and Dependencies:** + +* Adafruit CircuitPython firmware for the supported boards: + https://github.com/adafruit/circuitpython/releases + +""" + +import time + +import board +import digitalio +import supervisor + +__version__ = "0.0.0-auto.0" +__repo__ = "https://github.com/adafruit/Adafruit_CircuitPython_BoardTest.git" + +# Constants +LED_ON_DELAY_TIME = 0.2 # Seconds +LED_OFF_DELAY_TIME = 0.2 # Seconds +LED_PIN_NAMES = ["L", "LED", "RED_LED", "GREEN_LED", "BLUE_LED"] + +# Test result strings +PASS = "PASS" +FAIL = "FAIL" +NA = "N/A" + + +# Determine if given value is a number +def _is_number(val): + try: + float(val) + return True + except ValueError: + return False + + +# Release pins +def _deinit_pins(gpios): + for g in gpios: + g.deinit() + + +# Toggle IO pins while waiting for answer +def _toggle_wait(pin_gpios): + timestamp = time.monotonic() + led_state = False + failed = [] + for pg in pin_gpios: + (pin, gpio) = pg + print("Is pin %s toggling? [y/n]" % pin) + done = False + while not done: + if led_state: + if time.monotonic() > timestamp + LED_ON_DELAY_TIME: + led_state = False + timestamp = time.monotonic() + else: + if time.monotonic() > timestamp + LED_OFF_DELAY_TIME: + led_state = True + timestamp = time.monotonic() + + gpio.value = led_state + if supervisor.runtime.serial_bytes_available: + answer = input() + if bool(answer == "y"): + done = True + elif bool(answer == "n"): + failed += pin + done = True + return failed + + +def buildPin(pin): + gpio = digitalio.DigitalInOut(pin) + return gpio + + +def run_test(pins): + """ + Toggles all available GPIO on and off repeatedly. + + :param list[str] pins: list of pins to run the test on + :return: tuple(str, list[str]): test result followed by list of pins tested + """ + + # Create a list of analog GPIO pins + analog_pins = [p for p in pins if p[0] == "A" and _is_number(p[1])] + + # Create a list of digital GPIO + digital_pins = [p for p in pins if p[0] == "D" and _is_number(p[1])] + + # Toggle LEDs if we find any + gpio_pins = analog_pins + digital_pins + + if gpio_pins: + # Print out the LEDs found + print("GPIO pins found:", end=" ") + for pin in gpio_pins: + print(pin, end=" ") + print("\n") + + # Create a list of IO objects for us to toggle + gpios = [buildPin(getattr(board, p)) for p in gpio_pins] + + print("built GPIOs") + # Set all IO to output + for gpio in gpios: + gpio.direction = digitalio.Direction.OUTPUT + + # Toggle pins while waiting for user to verify LEDs blinking + result = _toggle_wait(zip(gpio_pins, gpios)) + + # Release pins + _deinit_pins(gpios) + + if result: + return FAIL, gpio_pins + + return PASS, gpio_pins + + # Else (no pins found) + print("No GPIO pins found") + return NA, [] + + +run_test([p for p in dir(board)]) diff --git a/ports/stm/boards/cygnet/tests/button.py b/ports/stm/boards/cygnet/tests/button.py new file mode 100644 index 000000000000..4f00254ddb6d --- /dev/null +++ b/ports/stm/boards/cygnet/tests/button.py @@ -0,0 +1,22 @@ +import board +import digitalio +import time + + +def monitor_button(pin, callback): + with digitalio.DigitalInOut(pin) as button: + newstate = not button.value # state is inverted + state = not newstate # ensure change reported to start with + while callback(newstate, newstate != state): + state = newstate + newstate = button.value + time.sleep(0.01) + + +def print_changes(state, changed): + if changed: + print(f"button pressed {state}") + return True + + +monitor_button(board.BUTTON_USR, print_changes) diff --git a/ports/stm/boards/cygnet/tests/enable_3v3.py b/ports/stm/boards/cygnet/tests/enable_3v3.py new file mode 100644 index 000000000000..c32bbc58b80e --- /dev/null +++ b/ports/stm/boards/cygnet/tests/enable_3v3.py @@ -0,0 +1,35 @@ +# Background: I have a Swan R5 board running circuit python +# And I import the "board" module +import board +import digitalio +import supervisor +import time + +# Scenario: Enable 3V3 pin definition +# Then the symbol "board.ENABLE_3V3" is defined +assert board.ENABLE_3V3 is not None + +# Scenario: Discharge 3V3 definition +# Then the symbol "board.DISCHARGE_3V3" is defined +assert board.DISCHARGE_3V3 is not None +# And the symbol "board.DISABLE_DISCHARGING" is defined to be "True" +assert board.DISABLE_DISCHARGING is not None and board.DISABLE_DISCHARGING == True +# And the symbol "board.ENABLE_DISCHARGING" is defined to be "False" +assert board.ENABLE_DISCHARGING is not None and board.ENABLE_DISCHARGING == False + +# Scenario: Toggle ENBLE_3V3 +# Given I have a LED connected between the 3V3 and GND pins +# And ENABLE_3V3 is configured for output +_3v3 = digitalio.DigitalInOut(board.ENABLE_3V3) +_3v3.direction = digitalio.Direction.OUTPUT +# When I run code to toggle the pin at 0.5Hz +# Then I see the LED switch on and off at 0.5Hz +print("Toggling 3V3. Press a key to stop.") + +while not supervisor.runtime.serial_bytes_available: + _3v3.value = True + time.sleep(1.0) + _3v3.value = False + time.sleep(1.0) + +print("Toggling stopped.") diff --git a/ports/stm/boards/cygnet/tests/i2c_scan.py b/ports/stm/boards/cygnet/tests/i2c_scan.py new file mode 100644 index 000000000000..8e3ef557d136 --- /dev/null +++ b/ports/stm/boards/cygnet/tests/i2c_scan.py @@ -0,0 +1,20 @@ +import board +import busio + +i2c = busio.I2C(board.SCL, board.SDA) +count = 0 + +# Wait for I2C lock +while not i2c.try_lock(): + pass + +# Scan for devices on the I2C bus +print("Scanning I2C bus") +for x in i2c.scan(): + print(hex(x)) + count += 1 + +print("%d device(s) found on I2C bus" % count) + +# Release the I2C bus +i2c.unlock() diff --git a/ports/stm/boards/cygnet/tests/pwnio.py b/ports/stm/boards/cygnet/tests/pwnio.py new file mode 100644 index 000000000000..71888d867b8e --- /dev/null +++ b/ports/stm/boards/cygnet/tests/pwnio.py @@ -0,0 +1,17 @@ +import time +import pwmio + + +def fade(pin): + led = pwmio.PWMOut(pin, frequency=5000, duty_cycle=0) + # LED setup for QT Py M0: + # led = pwmio.PWMOut(board.SCK, frequency=5000, duty_cycle=0) + + while True: + for i in range(100): + # PWM LED up and down + if i < 50: + led.duty_cycle = int(i * 2 * 65535 / 100) # Up + else: + led.duty_cycle = 65535 - int((i - 50) * 2 * 65535 / 100) # Down + time.sleep(0.01) diff --git a/ports/stm/boards/cygnet/tests/spi_bme680_smoke_test.py b/ports/stm/boards/cygnet/tests/spi_bme680_smoke_test.py new file mode 100644 index 000000000000..01e98bfd31b2 --- /dev/null +++ b/ports/stm/boards/cygnet/tests/spi_bme680_smoke_test.py @@ -0,0 +1,58 @@ +import board +import busio +import digitalio + +cs = digitalio.DigitalInOut(board.SS) +cs.direction = digitalio.Direction.OUTPUT +cs.value = True + +BME680_SPI_REGISTER = 0x73 +BME680_CHIPID_REGISTER = 0xD0 +BME680_CHIPID = 0x61 +SPI_HERZ = 0x500000 + +spi = busio.SPI(board.SCK, MISO=board.MISO, MOSI=board.MOSI) + + +def readByte(addr): + value = -1 + while not spi.try_lock(): + pass + try: + spi.configure(baudrate=500000, phase=0, polarity=0) + + cs.value = False + result = bytearray(1) + result[0] = addr | 0x80 + spi.write(result) + spi.readinto(result) + value = result[0] + return value + finally: + spi.unlock() + cs.value = True + + +def writeByte(addr, value): + while not spi.try_lock(): + pass + try: + spi.configure(baudrate=500000, phase=0, polarity=0) + + cs.value = False + result = bytearray(2) + result[0] = addr & ~0x80 + result[1] = value + spi.write(result) + finally: + spi.unlock() + + +# put the device in the correct mode to read the ID +reg = readByte(BME680_SPI_REGISTER) +if (reg & 16) != 0: + writeByte(BME680_SPI_REGISTER, reg & ~16) + +id = readByte(BME680_CHIPID_REGISTER) + +print(f"id is {id}, expected {BME680_CHIPID}") diff --git a/ports/stm/boards/cygnet/tests/uart.py b/ports/stm/boards/cygnet/tests/uart.py new file mode 100644 index 000000000000..a8dbc272a899 --- /dev/null +++ b/ports/stm/boards/cygnet/tests/uart.py @@ -0,0 +1,37 @@ +import board +import busio +import digitalio +import usb_cdc +import time + +while not usb_cdc.console.in_waiting: + time.sleep(0.1) + +print("USART test") + +# For most CircuitPython boards: +led = digitalio.DigitalInOut(board.LED) +# For QT Py M0: +# led = digitalio.DigitalInOut(board.SCK) +led.direction = digitalio.Direction.OUTPUT + +uart = busio.UART(board.TX, board.RX, baudrate=9600) + +while True: + data = uart.read(32) # read up to 32 bytes + # print(data) # this is a bytearray type + + if data is not None: + led.value = True + + # convert bytearray to string + data_string = "*".join([chr(b) for b in data]) + print(data_string, end="") + + led.value = False + + if usb_cdc.console.in_waiting: + data = usb_cdc.console.read() + data_string = "*".join([chr(b) for b in data]) + print("writing " + data_string) + uart.write(data) diff --git a/ports/stm/boards/cygnet/tests/urandom.py b/ports/stm/boards/cygnet/tests/urandom.py new file mode 100644 index 000000000000..25ff655596b1 --- /dev/null +++ b/ports/stm/boards/cygnet/tests/urandom.py @@ -0,0 +1,10 @@ +import os + + +def main(): + print("Random number test") + r = os.urandom(32) + print(f"urandom TRNG string is {r}") + + +main() diff --git a/ports/stm/common-hal/microcontroller/Pin.c b/ports/stm/common-hal/microcontroller/Pin.c index e0ff3f138dfc..8a6f57f9ab63 100644 --- a/ports/stm/common-hal/microcontroller/Pin.c +++ b/ports/stm/common-hal/microcontroller/Pin.c @@ -11,6 +11,8 @@ #if defined(TFBGA216) GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK}; +#elif defined(LQFP48) +GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC}; #elif defined(LQFP144) || defined(WLCSP144) GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG}; #elif defined(LQFP100_f4) || (LQFP100_x7) diff --git a/ports/stm/packages/LQFP48.c b/ports/stm/packages/LQFP48.c new file mode 100644 index 000000000000..1092b8df15f5 --- /dev/null +++ b/ports/stm/packages/LQFP48.c @@ -0,0 +1,63 @@ +#include "shared-bindings/microcontroller/__init__.h" +#include "common-hal/microcontroller/Pin.h" +#include "py/obj.h" + +static const mp_rom_map_elem_t mcu_pin_globals_table[] = { +// Pins 1-12 + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + +// Pins 13-24 + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + // VCAP1 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 25-36 + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 37-48 + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index 438db7938672..4960125d90f1 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -21,11 +21,11 @@ typedef struct { } mcu_periph_obj_t; #define PERIPH(index, alt, p_pin) \ - { \ - .periph_index = index, \ - .altfn_index = alt, \ - .pin = p_pin, \ - } + { \ + .periph_index = index, \ + .altfn_index = alt, \ + .pin = p_pin, \ + } // Timer Peripheral @@ -37,12 +37,12 @@ typedef struct { } mcu_tim_pin_obj_t; #define TIM(index, alt, channel, tim_pin) \ - { \ - .tim_index = index - 1, \ - .altfn_index = alt, \ - .channel_index = channel - 1, \ - .pin = tim_pin, \ - } + { \ + .tim_index = index - 1, \ + .altfn_index = alt, \ + .channel_index = channel - 1, \ + .pin = tim_pin, \ + } // F4 Series // Access Lines @@ -84,6 +84,13 @@ typedef struct { #include "stm32l4/stm32l4r5xx/periph.h" #endif +#ifdef STM32L433xx +#define HAS_DAC 1 +#define HAS_TRNG 1 +#define HAS_BASIC_TIM 1 +#include "stm32l4/stm32l433xx/periph.h" +#endif + #ifdef STM32F405xx #define HAS_DAC 1 #define HAS_TRNG 1 diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h index 999f8172d971..c91879939552 100644 --- a/ports/stm/peripherals/pins.h +++ b/ports/stm/peripherals/pins.h @@ -32,24 +32,24 @@ typedef struct { // but all 3 ADCs will share the same input number per pin. // F4 family has 3 ADC max, 24 channels max. #define ADC_INPUT(mask, number) \ - .adc_unit = mask, \ - .adc_channel = number, + .adc_unit = mask, \ + .adc_channel = number, #define NO_ADC \ - .adc_unit = 0x00, \ - .adc_channel = 0x1f + .adc_unit = 0x00, \ + .adc_channel = 0x1f extern const mp_obj_type_t mcu_pin_type; // STM32 can have up to 9 ports, each restricted to 16 pins // We split the pin/port evenly, in contrast to nrf. #define PIN(p_port, p_number, p_adc) \ - { \ - { &mcu_pin_type }, \ - .port = p_port, \ - .number = p_number, \ - p_adc \ - } + { \ + { &mcu_pin_type }, \ + .port = p_port, \ + .number = p_number, \ + p_adc \ + } // Use illegal pin value to mark unassigned pins. #define NO_PIN 0xff @@ -70,6 +70,9 @@ extern const mp_obj_type_t mcu_pin_type; #ifdef STM32L4R5xx #include "stm32l4/stm32l4r5xx/pins.h" #endif +#ifdef STM32L433xx +#include "stm32l4/stm32l433xx/pins.h" +#endif #ifdef STM32F405xx #include "stm32f4/stm32f405xx/pins.h" #endif diff --git a/ports/stm/peripherals/stm32l4/clocks.c b/ports/stm/peripherals/stm32l4/clocks.c index a005c2bf7908..a46c64de4963 100644 --- a/ports/stm/peripherals/stm32l4/clocks.c +++ b/ports/stm/peripherals/stm32l4/clocks.c @@ -11,6 +11,8 @@ // L4 Series #ifdef STM32L4R5xx #include "stm32l4/stm32l4r5xx/clocks.h" +#elif STM32L433xx +#include "stm32l4/stm32l433xx/clocks.h" #else #error Please add other MCUs here so that they are not silently ignored due to #define typos #endif @@ -44,9 +46,15 @@ void stm32_peripherals_clocks_init(void) { /** Configure the main internal regulator output voltage */ + #if STM32L4R5xx if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } + #elif STM32L433xx + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + #endif /* Activate PLL with MSI , stabilizied via PLL by LSE */ @@ -80,7 +88,11 @@ void stm32_peripherals_clocks_init(void) { /* AHB prescaler divider at 1 as second step */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + #ifdef STM32L4R5xx HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5)); + #elif STM32L433xx + HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4)); + #endif /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ADC; diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/clocks.h b/ports/stm/peripherals/stm32l4/stm32l433xx/clocks.h new file mode 100644 index 000000000000..b9335f7e6331 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/clocks.h @@ -0,0 +1,49 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#pragma once + +#include "stm32l4xx_hal.h" + +// Chip: STM32L433 +// Line Type: Foundation Line +// Speed: 80MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) // up to 80MHz +#endif +#ifndef CPY_CLK_PLLM +#define CPY_CLK_PLLM (12) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (60) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (2) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_4) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif + +#ifndef BOARD_HAS_HIGH_SPEED_CRYSTAL +#define BOARD_HAS_HIGH_SPEED_CRYSTAL (1) +#endif diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/gpio.c b/ports/stm/peripherals/stm32l4/stm32l433xx/gpio.c new file mode 100644 index 000000000000..d1721dda3e96 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/gpio.c @@ -0,0 +1,27 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#include "peripherals/gpio.h" +#include "common-hal/microcontroller/Pin.h" + +void stm32_peripherals_gpio_init(void) { + // Enable all GPIO for now + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + + // Never reset pins + never_reset_pin_number(2, 14); // PC14 OSC32_IN + never_reset_pin_number(2, 15); // PC15 OSC32_OUT + never_reset_pin_number(0, 13); // PA13 SWDIO + never_reset_pin_number(0, 14); // PA14 SWCLK +} + +void stm32l4_peripherals_status_led(uint8_t led, uint8_t state) { + +} diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/periph.c b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.c new file mode 100644 index 000000000000..193bd7562006 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.c @@ -0,0 +1,167 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" + +I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3}; + +const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN] = { + PERIPH(3, 4, &pin_PB04), + PERIPH(1, 4, &pin_PB07), + PERIPH(1, 4, &pin_PB09), + PERIPH(2, 4, &pin_PB11), + PERIPH(2, 4, &pin_PB14), + PERIPH(3, 4, &pin_PC01), +}; + +const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN] = { + PERIPH(1, 4, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(3, 4, &pin_PA07), + PERIPH(2, 4, &pin_PB10), + PERIPH(2, 4, &pin_PB13), + PERIPH(3, 4, &pin_PC00), +}; + +SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3}; + +const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PA01), + PERIPH(1, 5, &pin_PA05), + PERIPH(1, 5, &pin_PB03), + PERIPH(3, 6, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(3, 6, &pin_PC10), + PERIPH(2, 5, &pin_PD01), + PERIPH(1, 5, &pin_PE13), +}; +const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(1, 5, &pin_PA12), + PERIPH(1, 5, &pin_PB05), + PERIPH(3, 6, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PC12), + PERIPH(2, 5, &pin_PD04), + PERIPH(1, 5, &pin_PE15), +}; +const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(1, 5, &pin_PA11), + PERIPH(1, 5, &pin_PB04), + PERIPH(3, 6, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PC11), + PERIPH(2, 5, &pin_PD03), + PERIPH(1, 5, &pin_PE14), +}; +const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PA04), + PERIPH(3, 6, &pin_PA04), + PERIPH(1, 5, &pin_PA15), + PERIPH(3, 6, &pin_PA15), + PERIPH(1, 5, &pin_PB00), + PERIPH(2, 5, &pin_PB09), + PERIPH(2, 5, &pin_PB12), + PERIPH(2, 5, &pin_PD00), + PERIPH(1, 5, &pin_PE12), +}; + +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3}; +bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false}; + +const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN] = { + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(1, 7, &pin_PB06), + PERIPH(3, 7, &pin_PB10), + PERIPH(3, 7, &pin_PC04), + PERIPH(3, 7, &pin_PC10), + PERIPH(2, 7, &pin_PD05), + PERIPH(3, 7, &pin_PD08), +}; +const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN] = { + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(2, 3, &pin_PA15), + PERIPH(1, 7, &pin_PB07), + PERIPH(3, 7, &pin_PB11), + PERIPH(3, 7, &pin_PC05), + PERIPH(3, 7, &pin_PC11), + PERIPH(2, 7, &pin_PD06), + PERIPH(3, 7, &pin_PD09), +}; + +// Timers +TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, TIM15, TIM16, NULL}; + +const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = { + TIM(2, 1, 1, &pin_PA00), + TIM(2, 1, 2, &pin_PA01), + TIM(2, 1, 3, &pin_PA02), + TIM(15, 15, 1, &pin_PA02), + TIM(2, 1, 4, &pin_PA03), + TIM(15, 15, 2, &pin_PA03), + TIM(2, 1, 1, &pin_PA05), + TIM(16, 15, 1, &pin_PA06), + TIM(1, 1, 1, &pin_PA08), + TIM(1, 1, 2, &pin_PA09), + TIM(1, 1, 3, &pin_PA10), + TIM(1, 1, 4, &pin_PA11), + TIM(2, 1, 1, &pin_PA15), + TIM(2, 1, 2, &pin_PB03), + TIM(16, 15, 1, &pin_PB08), + TIM(2, 1, 3, &pin_PB10), + TIM(2, 1, 4, &pin_PB11), + TIM(15, 15, 1, &pin_PB14), + TIM(15, 15, 2, &pin_PB15), + TIM(16, 15, 1, &pin_PE00), + TIM(1, 1, 1, &pin_PE09), + TIM(1, 1, 2, &pin_PE11), + TIM(1, 1, 3, &pin_PE13), + TIM(1, 1, 4, &pin_PE14), +}; +// SDIO +// SDIO_TypeDef *mcu_sdio_banks[1] = {SDIO}; +// todo - the L4 has a SDMMC pripheral +const mcu_periph_obj_t mcu_sdio_clock_list[1] = { + PERIPH(1, 12, &pin_PC12), +}; +const mcu_periph_obj_t mcu_sdio_command_list[1] = { + PERIPH(1, 12, &pin_PD02), +}; +const mcu_periph_obj_t mcu_sdio_data0_list[1] = { + PERIPH(1, 12, &pin_PC08), +}; +const mcu_periph_obj_t mcu_sdio_data1_list[1] = { + PERIPH(1, 12, &pin_PC09), +}; +const mcu_periph_obj_t mcu_sdio_data2_list[1] = { + PERIPH(1, 12, &pin_PC10), +}; +const mcu_periph_obj_t mcu_sdio_data3_list[1] = { + PERIPH(1, 12, &pin_PC11), +}; + +// CAN +CAN_TypeDef *mcu_can_banks[] = {CAN1}; + +const mcu_periph_obj_t mcu_can_tx_list[4] = { + PERIPH(1, 10, &pin_PA12), + PERIPH(1, 10, &pin_PB09), + PERIPH(1, 10, &pin_PD01), +}; +const mcu_periph_obj_t mcu_can_rx_list[4] = { + PERIPH(1, 10, &pin_PA11), + PERIPH(1, 10, &pin_PB08), + PERIPH(1, 10, &pin_PD00), +}; diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/periph.h b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.h new file mode 100644 index 000000000000..3e45a17c811c --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.h @@ -0,0 +1,56 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#pragma once + +// I2C +#define I2C_BANK_ARRAY_LEN 4 +#define I2C_SDA_ARRAY_LEN 16 +#define I2C_SCL_ARRAY_LEN 15 +extern I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN]; + +// SPI +#define SPI_BANK_ARRAY_LEN 3 +#define SPI_SCK_ARRAY_LEN 14 +#define SPI_MOSI_ARRAY_LEN 14 +#define SPI_MISO_ARRAY_LEN 12 +#define SPI_NSS_ARRAY_LEN 12 +extern SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN]; + +// UART +#define UART_TX_ARRAY_LEN 12 +#define UART_RX_ARRAY_LEN 13 +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; +extern bool mcu_uart_has_usart[MAX_UART]; +extern const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN]; + +// Timers +#define TIM_BANK_ARRAY_LEN 17 +#define TIM_PIN_ARRAY_LEN (73 - 3) +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; + +// SDIO +// extern SDIO_TypeDef *mcu_sdio_banks[1]; + +// extern const mcu_periph_obj_t mcu_sdio_clock_list[1]; +// extern const mcu_periph_obj_t mcu_sdio_command_list[1]; +// extern const mcu_periph_obj_t mcu_sdio_data0_list[1]; +// extern const mcu_periph_obj_t mcu_sdio_data1_list[1]; +// extern const mcu_periph_obj_t mcu_sdio_data2_list[1]; +// extern const mcu_periph_obj_t mcu_sdio_data3_list[1]; + +// CAN +extern CAN_TypeDef *mcu_can_banks[1]; +extern const mcu_periph_obj_t mcu_can_tx_list[4]; +extern const mcu_periph_obj_t mcu_can_rx_list[4]; diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/pins.c b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.c new file mode 100644 index 000000000000..5ff6b5aea206 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.c @@ -0,0 +1,95 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" + +#include STM32_HAL_H + +const mcu_pin_obj_t pin_PA00 = PIN(0, 0, ADC_INPUT(ADC_1, 5)); +const mcu_pin_obj_t pin_PA01 = PIN(0, 1, ADC_INPUT(ADC_1, 6)); +const mcu_pin_obj_t pin_PA02 = PIN(0, 2, ADC_INPUT(ADC_1, 7)); +const mcu_pin_obj_t pin_PA03 = PIN(0, 3, ADC_INPUT(ADC_1, 8)); +const mcu_pin_obj_t pin_PA04 = PIN(0, 4, ADC_INPUT(ADC_1, 9)); +const mcu_pin_obj_t pin_PA05 = PIN(0, 5, ADC_INPUT(ADC_1, 10)); +const mcu_pin_obj_t pin_PA06 = PIN(0, 6, ADC_INPUT(ADC_1, 11)); +const mcu_pin_obj_t pin_PA07 = PIN(0, 7, ADC_INPUT(ADC_1, 12)); +const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC); +const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); +const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); +const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); +const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); +const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_1, 15)); +const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_1, 16)); +const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); +const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC); +const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC); +const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC); +const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC); +const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC); +const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); +const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); +const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); +const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); +const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); +const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); +const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC); +const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1, 1)); +const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1, 2)); +const mcu_pin_obj_t pin_PC02 = PIN(2, 2, ADC_INPUT(ADC_1, 3)); +const mcu_pin_obj_t pin_PC03 = PIN(2, 3, ADC_INPUT(ADC_1, 4)); +const mcu_pin_obj_t pin_PC04 = PIN(2, 4, ADC_INPUT(ADC_1, 13)); +const mcu_pin_obj_t pin_PC05 = PIN(2, 5, ADC_INPUT(ADC_1, 14)); +const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC); +const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC); +const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC); +const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC); +const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); +const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); +const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC); +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); +const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC); +const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC); +const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC); +const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC); +const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC); +const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC); +const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC); +const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC); +const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC); +const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC); +const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC); +const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC); +const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC); +const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC); +const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC); +const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC); +const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); +const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); +const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); +const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); +const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); +const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); +const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); +const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); +const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); +const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC); +const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC); +const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC); +const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC); +const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC); +const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); +const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); +const mcu_pin_obj_t pin_PH00 = PIN(7, 0, NO_ADC); +const mcu_pin_obj_t pin_PH01 = PIN(7, 1, NO_ADC); +const mcu_pin_obj_t pin_PH03 = PIN(7, 3, NO_ADC); diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/pins.h b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.h new file mode 100644 index 000000000000..fefebbe15258 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.h @@ -0,0 +1,107 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#pragma once + +extern const mcu_pin_obj_t pin_PA00; +extern const mcu_pin_obj_t pin_PA01; +extern const mcu_pin_obj_t pin_PA02; +extern const mcu_pin_obj_t pin_PA03; +extern const mcu_pin_obj_t pin_PA04; +extern const mcu_pin_obj_t pin_PA05; +extern const mcu_pin_obj_t pin_PA06; +extern const mcu_pin_obj_t pin_PA07; +extern const mcu_pin_obj_t pin_PA08; +extern const mcu_pin_obj_t pin_PA09; +extern const mcu_pin_obj_t pin_PA10; +extern const mcu_pin_obj_t pin_PA11; +extern const mcu_pin_obj_t pin_PA12; +extern const mcu_pin_obj_t pin_PA13; +extern const mcu_pin_obj_t pin_PA14; +extern const mcu_pin_obj_t pin_PA15; +extern const mcu_pin_obj_t pin_PB00; +extern const mcu_pin_obj_t pin_PB01; +extern const mcu_pin_obj_t pin_PB02; +extern const mcu_pin_obj_t pin_PB03; +extern const mcu_pin_obj_t pin_PB04; +extern const mcu_pin_obj_t pin_PB05; +extern const mcu_pin_obj_t pin_PB06; +extern const mcu_pin_obj_t pin_PB07; +extern const mcu_pin_obj_t pin_PB08; +extern const mcu_pin_obj_t pin_PB09; +extern const mcu_pin_obj_t pin_PB10; +extern const mcu_pin_obj_t pin_PB11; +extern const mcu_pin_obj_t pin_PB12; +extern const mcu_pin_obj_t pin_PB13; +extern const mcu_pin_obj_t pin_PB14; +extern const mcu_pin_obj_t pin_PB15; +extern const mcu_pin_obj_t pin_PC00; +extern const mcu_pin_obj_t pin_PC01; +extern const mcu_pin_obj_t pin_PC02; +extern const mcu_pin_obj_t pin_PC03; +extern const mcu_pin_obj_t pin_PC04; +extern const mcu_pin_obj_t pin_PC05; +extern const mcu_pin_obj_t pin_PC06; +extern const mcu_pin_obj_t pin_PC07; +extern const mcu_pin_obj_t pin_PC08; +extern const mcu_pin_obj_t pin_PC09; +extern const mcu_pin_obj_t pin_PC10; +extern const mcu_pin_obj_t pin_PC11; +extern const mcu_pin_obj_t pin_PC12; +extern const mcu_pin_obj_t pin_PC13; +extern const mcu_pin_obj_t pin_PC14; +extern const mcu_pin_obj_t pin_PC15; +extern const mcu_pin_obj_t pin_PD00; +extern const mcu_pin_obj_t pin_PD01; +extern const mcu_pin_obj_t pin_PD02; +extern const mcu_pin_obj_t pin_PD03; +extern const mcu_pin_obj_t pin_PD04; +extern const mcu_pin_obj_t pin_PD05; +extern const mcu_pin_obj_t pin_PD06; +extern const mcu_pin_obj_t pin_PD07; +extern const mcu_pin_obj_t pin_PD08; +extern const mcu_pin_obj_t pin_PD09; +extern const mcu_pin_obj_t pin_PD10; +extern const mcu_pin_obj_t pin_PD11; +extern const mcu_pin_obj_t pin_PD12; +extern const mcu_pin_obj_t pin_PD13; +extern const mcu_pin_obj_t pin_PD14; +extern const mcu_pin_obj_t pin_PD15; +extern const mcu_pin_obj_t pin_PE00; +extern const mcu_pin_obj_t pin_PE01; +extern const mcu_pin_obj_t pin_PE02; +extern const mcu_pin_obj_t pin_PE03; +extern const mcu_pin_obj_t pin_PE04; +extern const mcu_pin_obj_t pin_PE05; +extern const mcu_pin_obj_t pin_PE06; +extern const mcu_pin_obj_t pin_PE07; +extern const mcu_pin_obj_t pin_PE08; +extern const mcu_pin_obj_t pin_PE09; +extern const mcu_pin_obj_t pin_PE10; +extern const mcu_pin_obj_t pin_PE11; +extern const mcu_pin_obj_t pin_PE12; +extern const mcu_pin_obj_t pin_PE13; +extern const mcu_pin_obj_t pin_PE14; +extern const mcu_pin_obj_t pin_PE15; +extern const mcu_pin_obj_t pin_PH00; +extern const mcu_pin_obj_t pin_PH01; +extern const mcu_pin_obj_t pin_PH02; +extern const mcu_pin_obj_t pin_PH03; +extern const mcu_pin_obj_t pin_PH04; +extern const mcu_pin_obj_t pin_PH05; +extern const mcu_pin_obj_t pin_PH06; +extern const mcu_pin_obj_t pin_PH07; +extern const mcu_pin_obj_t pin_PH08; +extern const mcu_pin_obj_t pin_PH09; +extern const mcu_pin_obj_t pin_PH10; +extern const mcu_pin_obj_t pin_PH11; +extern const mcu_pin_obj_t pin_PH12; +extern const mcu_pin_obj_t pin_PH13; +extern const mcu_pin_obj_t pin_PH14; +extern const mcu_pin_obj_t pin_PH15; +extern const mcu_pin_obj_t pin_PI00; +extern const mcu_pin_obj_t pin_PI01; +extern const mcu_pin_obj_t pin_PI03; diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 273af300a80b..02ea9cd514f5 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -69,12 +69,18 @@ static const flash_layout_t flash_layout[] = { }; static uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); -#elif defined(STM32L4) +#elif defined(STM32L4R5XX) static const flash_layout_t flash_layout[] = { { 0x08100000, 0x1000, 256 }, }; static uint8_t _flash_cache[0x1000] __attribute__((aligned(4))); +#elif defined(STM32L433XX) +static const flash_layout_t flash_layout[] = { + { 0x08000000, 0x2000, 128 }, +}; +static uint8_t _flash_cache[0x2000] __attribute__((aligned(4))); + #else #error Unsupported processor #endif @@ -175,8 +181,13 @@ void port_internal_flash_flush(void) { // set up for erase FLASH_EraseInitTypeDef EraseInitStruct = {}; #if CPY_STM32L4 + #if defined(STM32L4R5) EraseInitStruct.TypeErase = TYPEERASE_PAGES; - EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode + EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode + #elif defined(STM32L433) + EraseInitStruct.TypeErase = FLASH_TYPEERASE_MASSERASE; + EraseInitStruct.Banks = FLASH_BANK_1; + #endif #else EraseInitStruct.TypeErase = TYPEERASE_SECTORS; EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 68704805f339..1f0d815723ca 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -87,9 +87,15 @@ #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08100000 #endif +#ifdef STM32L433xx +#define STM32_FLASH_SIZE 0x80000 // 256KiB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x19000 // 100KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08026000 +#endif + #define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #define STM32_FLASH_OFFSET 0x8000000 // All STM32 chips map to this flash location #define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms -#define INTERNAL_FLASH_IDLE_TICK(tick) (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2) +#define INTERNAL_FLASH_IDLE_TICK(tick) (((tick)&INTERNAL_FLASH_SYSTICK_MASK) == 2) diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 61a7d54f08b7..5601b27b0f8a 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -29,7 +29,7 @@ static void init_usb_vbus_sense(void) { // B-peripheral session valid override enable USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - #else + #elif !defined(STM32L433XX) USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; @@ -69,7 +69,7 @@ void init_usb_hardware(void) { GPIO_InitStruct.Pull = GPIO_NOPULL; #if CPY_STM32H7 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif CPY_STM32F4 || CPY_STM32F7 || CPY_STM32L4 + #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5XX) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -117,7 +117,7 @@ void init_usb_hardware(void) { #if CPY_STM32H7 HAL_PWREx_EnableUSBVoltageDetector(); __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); - #else + #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5XX) /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); #endif