From 36d544aab4cd5c6b20686fd11d109e44efb96866 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Fri, 22 Sep 2023 20:09:16 +0300 Subject: [PATCH 1/9] cortexa: Prevent disruptive target_halt in cortexa_probe --- src/target/cortexa.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 38c1d0735e6..353375d49ae 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -508,6 +508,8 @@ bool cortexa_probe(adiv5_access_port_s *ap, target_addr_t base_address) target->halt_poll = cortexa_halt_poll; target->halt_resume = cortexa_halt_resume; +#if 0 /* Trying to halt STM32MP15x Cortex-A cores during probe locks up BMDA/BMF! */ + /* Try to halt the target core */ target_halt_request(target); platform_timeout_s timeout; @@ -518,6 +520,7 @@ bool cortexa_probe(adiv5_access_port_s *ap, target_addr_t base_address) /* If we did not succeed, we must abort at this point. */ if (reason == TARGET_HALT_FAULT || reason == TARGET_HALT_ERROR) return false; +#endif cortex_read_cpuid(target); /* The format of the debug identification register is described in DDI0406C §C11.11.15 pg2217 */ From 528724900e30304234cfb12d1c8ad6aad6070892 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Fri, 22 Sep 2023 20:07:14 +0300 Subject: [PATCH 2/9] cortexa: Avoid resuming *not halted* cores --- src/target/cortexa.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 353375d49ae..ba3aa3eae9f 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -837,6 +837,11 @@ static target_halt_reason_e cortexa_halt_poll(target_s *t, target_addr_t *watch) void cortexa_halt_resume(target_s *t, bool step) { cortexa_priv_s *priv = t->priv; + + uint32_t dbgdscr = cortex_dbg_read32(t, CORTEXAR_DBG_DSCR); + if (!(dbgdscr & CORTEXAR_DBG_DSCR_HALTED)) /* Not halted */ + return; + /* Set breakpoint comparator for single stepping if needed */ if (step) { uint32_t addr = priv->reg_cache.r[15]; @@ -856,7 +861,7 @@ void cortexa_halt_resume(target_s *t, bool step) cortexar_run_insn(t, MCR | ICIALLU); /* invalidate cache */ /* Disable DBGITR. Not sure why, but RRQ is ignored otherwise. */ - uint32_t dbgdscr = cortex_dbg_read32(t, CORTEXAR_DBG_DSCR); + dbgdscr = cortex_dbg_read32(t, CORTEXAR_DBG_DSCR); if (step) dbgdscr |= DBGDSCR_INTDIS; else From f0d49ef6ae50eb599f358bcefdbb53d4c1654d3d Mon Sep 17 00:00:00 2001 From: ALTracer Date: Fri, 22 Sep 2023 20:00:47 +0300 Subject: [PATCH 3/9] cortexa: Implement logging of DBG_DSCR bitfields decoded into names Example output: cortexa_attach: DBGOSLSR = 0x00000008 cortexa_attach: DBGDSCR = 0x02000002 (1) Bits set in reg DBGDSCR: RESTARTED PipeAdv cortexa_attach: DBGDSCR = 0x02006002 (2) Bits set in reg DBGDSCR: RESTARTED ITRen HDBGen PipeAdv cortexa_halt_poll: DBGDSCR = 0x03086003 --- src/target/cortexa.c | 61 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 58 insertions(+), 3 deletions(-) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index ba3aa3eae9f..9934e3d98f5 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -317,6 +317,54 @@ static size_t create_tdesc_cortex_a(char *buffer, size_t max_len) return (size_t)total; } +typedef struct bitfield_entry { + char *desc; + uint8_t bitnum; +} bitfields_lut_s; + +static const bitfields_lut_s cortexa_dbg_dscr_lut[] = { + {"HALTED", 0U}, + {"RESTARTED", 1U}, + {"SDABORT_l", 6U}, + {"ADABORT_l", 7U}, + {"UND_l", 8U}, + {"FS", 9U}, + {"ITRen", 13U}, + {"HDBGen", 14U}, + {"MDBGen", 15U}, + {"InstrCompl_l", 24U}, + {"PipeAdv", 25U}, + {"TXfull_l", 26U}, + {"RXfull_l", 27U}, + {"TXfull", 29U}, + {"RXfull", 30U}, +}; + +static void helper_print_bitfields(const uint32_t val, const bitfields_lut_s lut[], const size_t array_length) +{ + for (size_t i = 0; i < array_length; i++) { + if (val & (1U << lut[i].bitnum)) { + DEBUG_TARGET("%s ", lut[i].desc); + } + } +}; + +static void cortexa_decode_bitfields(const uint32_t reg, const uint32_t val) +{ + DEBUG_TARGET("Bits set in reg "); + switch (reg) { + case CORTEXAR_DBG_DSCR: + DEBUG_TARGET("DBGDSCR: "); + helper_print_bitfields(val, cortexa_dbg_dscr_lut, ARRAY_LENGTH(cortexa_dbg_dscr_lut)); + break; + default: + DEBUG_TARGET("unknown reg"); + break; + } + + DEBUG_TARGET("\n"); +} + static void cortexar_run_insn(target_s *const target, const uint32_t insn) { /* Issue the requested instruction to the core */ @@ -572,12 +620,19 @@ bool cortexa_attach(target_s *target) /* Clear any pending fault condition */ target_check_error(target); - /* Enable halting debug mode */ uint32_t dbgdscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR); - dbgdscr |= CORTEXAR_DBG_DSCR_ITR_ENABLE | CORTEXAR_DBG_DSCR_ITR_ENABLE; + DEBUG_INFO("%s: DBGDSCR = 0x%08" PRIx32 " (1)\n", __func__, dbgdscr); + cortexa_decode_bitfields(CORTEXAR_DBG_DSCR, dbgdscr); + + /* Enable halting debug mode */ + dbgdscr |= CORTEXAR_DBG_DSCR_HALT_DBG_ENABLE | CORTEXAR_DBG_DSCR_ITR_ENABLE; + cortex_dbg_write32(target, CORTEXAR_DBG_DSCR, dbgdscr); dbgdscr &= ~DBGDSCR_EXTDCCMODE_MASK; cortex_dbg_write32(target, CORTEXAR_DBG_DSCR, dbgdscr); - DEBUG_INFO("DBGDSCR = 0x%08" PRIx32 "\n", dbgdscr); + + dbgdscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR); + DEBUG_INFO("%s: DBGDSCR = 0x%08" PRIx32 " (2)\n", __func__, dbgdscr); + cortexa_decode_bitfields(CORTEXAR_DBG_DSCR, dbgdscr); target_halt_request(target); size_t tries = 10; From 845cc11da9389ef8e05b69d2c1332bf234662111 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Fri, 22 Sep 2023 20:05:12 +0300 Subject: [PATCH 4/9] cortexa: Check and clear OS Lock * This fixes the BMD hang on scanning STM32MP15x SoCs --- src/target/cortexa.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 9934e3d98f5..77cb77b70ba 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -91,6 +91,15 @@ typedef struct cortexa_priv { #define CORTEXAR_DBG_WCR 0x1c0U #define CORTEXAR_CTR 0xd04U +#define CORTEXAR_DBG_OSLAR 0x300U +#define CORTEXAR_DBG_OSLSR 0x304U + +#define DBGOSLSR_OSLM0 (1U << 0U) +#define DBGOSLSR_OSLK (1U << 1U) +#define DBGOSLSR_NTT (1U << 2U) +#define DBGOSLSR_OSLM1 (1U << 3U) +#define DBGOSLSR_OSLM (DBGOSLSR_OSLM0 | DBGOSLSR_OSLM1) + #define CORTEXAR_DBG_IDR_BREAKPOINT_MASK 0xfU #define CORTEXAR_DBG_IDR_BREAKPOINT_SHIFT 24U #define CORTEXAR_DBG_IDR_WATCHPOINT_MASK 0xfU @@ -620,6 +629,22 @@ bool cortexa_attach(target_s *target) /* Clear any pending fault condition */ target_check_error(target); + uint32_t dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); + DEBUG_INFO("%s: DBGOSLSR = 0x%08X\n", __func__, dbg_osreg); + /* Is OS Lock implemented? */ + if (((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM0) || ((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM1)) { + /* Is OS Lock set? */ + if (dbg_osreg & DBGOSLSR_OSLK) { + DEBUG_WARN("%s: OSLock set! Trying to unlock\n", __func__); + cortex_dbg_write32(target, CORTEXAR_DBG_OSLAR, 0U); + dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); + + if ((dbg_osreg & DBGOSLSR_OSLK) != 0) { + DEBUG_ERROR("%s: OSLock sticky, core not powered?\n", __func__); + } + } + } + uint32_t dbgdscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR); DEBUG_INFO("%s: DBGDSCR = 0x%08" PRIx32 " (1)\n", __func__, dbgdscr); cortexa_decode_bitfields(CORTEXAR_DBG_DSCR, dbgdscr); From d82c2a5ed880b6385b59cf3c3263495e609c3aa8 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Fri, 22 Sep 2023 20:06:05 +0300 Subject: [PATCH 5/9] cortexa: Port over some more of OpenOCD manipulations --- src/target/cortexa.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 77cb77b70ba..f62ddf1cb20 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -91,8 +91,12 @@ typedef struct cortexa_priv { #define CORTEXAR_DBG_WCR 0x1c0U #define CORTEXAR_CTR 0xd04U +#define CORTEXAR_DBG_DSCCR 0x028U +#define CORTEXAR_DBG_DSMCR 0x02cU #define CORTEXAR_DBG_OSLAR 0x300U #define CORTEXAR_DBG_OSLSR 0x304U +#define CORTEXAR_DBG_LAR 0xfb0U /* Lock Access */ +#define CORTEXAR_DBG_LSR 0xfb4U /* Lock Status */ #define DBGOSLSR_OSLM0 (1U << 0U) #define DBGOSLSR_OSLK (1U << 1U) @@ -629,6 +633,15 @@ bool cortexa_attach(target_s *target) /* Clear any pending fault condition */ target_check_error(target); +#if 0 + /* Reset 0xc5acce55 lock access to deter software */ + cortex_dbg_write32(target, CORTEXAR_DBG_LAR, 0U); + /* Cache write-through */ + cortex_dbg_write32(target, CORTEXAR_DBG_DSCCR, 0U); + /* Disable TLB lookup and refill/eviction */ + cortex_dbg_write32(target, CORTEXAR_DBG_DSMCR, 0U); +#endif + uint32_t dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); DEBUG_INFO("%s: DBGOSLSR = 0x%08X\n", __func__, dbg_osreg); /* Is OS Lock implemented? */ From 73e8ab7d226380324fb20ee99e76156f322494ab Mon Sep 17 00:00:00 2001 From: ALTracer Date: Fri, 22 Sep 2023 20:30:44 +0300 Subject: [PATCH 6/9] cortexa: Move OSLock/HDBGen/ITRen writes to run earlier, in cortexa_probe() * Unblock the target_halt in cortexa_probe * Move code setting up debug access from cortexa_detach() up to cortexa_probe() * Scans of STM32MP15x still work, gdb shows $pc and registers --- src/target/cortexa.c | 79 +++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 41 deletions(-) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index f62ddf1cb20..756a334cf8b 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -569,7 +569,44 @@ bool cortexa_probe(adiv5_access_port_s *ap, target_addr_t base_address) target->halt_poll = cortexa_halt_poll; target->halt_resume = cortexa_halt_resume; -#if 0 /* Trying to halt STM32MP15x Cortex-A cores during probe locks up BMDA/BMF! */ +#if 0 + /* Reset 0xc5acce55 lock access to deter software */ + cortex_dbg_write32(target, CORTEXAR_DBG_LAR, 0U); + /* Cache write-through */ + cortex_dbg_write32(target, CORTEXAR_DBG_DSCCR, 0U); + /* Disable TLB lookup and refill/eviction */ + cortex_dbg_write32(target, CORTEXAR_DBG_DSMCR, 0U); +#endif + + uint32_t dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); + DEBUG_INFO("%s: DBGOSLSR = 0x%08X\n", __func__, dbg_osreg); + /* Is OS Lock implemented? */ + if (((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM0) || ((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM1)) { + /* Is OS Lock set? */ + if (dbg_osreg & DBGOSLSR_OSLK) { + DEBUG_WARN("%s: OSLock set! Trying to unlock\n", __func__); + cortex_dbg_write32(target, CORTEXAR_DBG_OSLAR, 0U); + dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); + + if ((dbg_osreg & DBGOSLSR_OSLK) != 0) { + DEBUG_ERROR("%s: OSLock sticky, core not powered?\n", __func__); + } + } + } + + uint32_t dbgdscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR); + DEBUG_INFO("%s: DBGDSCR = 0x%08" PRIx32 " (1)\n", __func__, dbgdscr); + cortexa_decode_bitfields(CORTEXAR_DBG_DSCR, dbgdscr); + + /* Enable halting debug mode */ + dbgdscr |= CORTEXAR_DBG_DSCR_HALT_DBG_ENABLE | CORTEXAR_DBG_DSCR_ITR_ENABLE; + cortex_dbg_write32(target, CORTEXAR_DBG_DSCR, dbgdscr); + dbgdscr &= ~DBGDSCR_EXTDCCMODE_MASK; + cortex_dbg_write32(target, CORTEXAR_DBG_DSCR, dbgdscr); + + dbgdscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR); + DEBUG_INFO("%s: DBGDSCR = 0x%08" PRIx32 " (2)\n", __func__, dbgdscr); + cortexa_decode_bitfields(CORTEXAR_DBG_DSCR, dbgdscr); /* Try to halt the target core */ target_halt_request(target); @@ -581,7 +618,6 @@ bool cortexa_probe(adiv5_access_port_s *ap, target_addr_t base_address) /* If we did not succeed, we must abort at this point. */ if (reason == TARGET_HALT_FAULT || reason == TARGET_HALT_ERROR) return false; -#endif cortex_read_cpuid(target); /* The format of the debug identification register is described in DDI0406C §C11.11.15 pg2217 */ @@ -633,45 +669,6 @@ bool cortexa_attach(target_s *target) /* Clear any pending fault condition */ target_check_error(target); -#if 0 - /* Reset 0xc5acce55 lock access to deter software */ - cortex_dbg_write32(target, CORTEXAR_DBG_LAR, 0U); - /* Cache write-through */ - cortex_dbg_write32(target, CORTEXAR_DBG_DSCCR, 0U); - /* Disable TLB lookup and refill/eviction */ - cortex_dbg_write32(target, CORTEXAR_DBG_DSMCR, 0U); -#endif - - uint32_t dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); - DEBUG_INFO("%s: DBGOSLSR = 0x%08X\n", __func__, dbg_osreg); - /* Is OS Lock implemented? */ - if (((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM0) || ((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM1)) { - /* Is OS Lock set? */ - if (dbg_osreg & DBGOSLSR_OSLK) { - DEBUG_WARN("%s: OSLock set! Trying to unlock\n", __func__); - cortex_dbg_write32(target, CORTEXAR_DBG_OSLAR, 0U); - dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); - - if ((dbg_osreg & DBGOSLSR_OSLK) != 0) { - DEBUG_ERROR("%s: OSLock sticky, core not powered?\n", __func__); - } - } - } - - uint32_t dbgdscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR); - DEBUG_INFO("%s: DBGDSCR = 0x%08" PRIx32 " (1)\n", __func__, dbgdscr); - cortexa_decode_bitfields(CORTEXAR_DBG_DSCR, dbgdscr); - - /* Enable halting debug mode */ - dbgdscr |= CORTEXAR_DBG_DSCR_HALT_DBG_ENABLE | CORTEXAR_DBG_DSCR_ITR_ENABLE; - cortex_dbg_write32(target, CORTEXAR_DBG_DSCR, dbgdscr); - dbgdscr &= ~DBGDSCR_EXTDCCMODE_MASK; - cortex_dbg_write32(target, CORTEXAR_DBG_DSCR, dbgdscr); - - dbgdscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR); - DEBUG_INFO("%s: DBGDSCR = 0x%08" PRIx32 " (2)\n", __func__, dbgdscr); - cortexa_decode_bitfields(CORTEXAR_DBG_DSCR, dbgdscr); - target_halt_request(target); size_t tries = 10; while (!platform_nrst_get_val() && !target_halt_poll(target, NULL) && --tries) From 9cad82537ddfd1ef38d4ef4d46a66005d5ef2098 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Fri, 22 Sep 2023 20:33:58 +0300 Subject: [PATCH 7/9] Revert "cortexa: Avoid resuming *not halted* cores" This reverts commit fc93f6fa0df5d618c4c2027f52a003cba86ac386. --- src/target/cortexa.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 756a334cf8b..049daa49321 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -927,11 +927,6 @@ static target_halt_reason_e cortexa_halt_poll(target_s *t, target_addr_t *watch) void cortexa_halt_resume(target_s *t, bool step) { cortexa_priv_s *priv = t->priv; - - uint32_t dbgdscr = cortex_dbg_read32(t, CORTEXAR_DBG_DSCR); - if (!(dbgdscr & CORTEXAR_DBG_DSCR_HALTED)) /* Not halted */ - return; - /* Set breakpoint comparator for single stepping if needed */ if (step) { uint32_t addr = priv->reg_cache.r[15]; @@ -951,7 +946,7 @@ void cortexa_halt_resume(target_s *t, bool step) cortexar_run_insn(t, MCR | ICIALLU); /* invalidate cache */ /* Disable DBGITR. Not sure why, but RRQ is ignored otherwise. */ - dbgdscr = cortex_dbg_read32(t, CORTEXAR_DBG_DSCR); + uint32_t dbgdscr = cortex_dbg_read32(t, CORTEXAR_DBG_DSCR); if (step) dbgdscr |= DBGDSCR_INTDIS; else From 46deb65d24d87851a41f8c5061d006764b490e7d Mon Sep 17 00:00:00 2001 From: ALTracer Date: Sat, 23 Sep 2023 21:21:56 +0300 Subject: [PATCH 8/9] cortexa: style fixes * Drop extraneous parentheses * Hide the helper behind ENABLE_DEBUG and a dummy implementation * Replace one introduced %08X with %08PRIx32 for *firmware* builds --- src/target/cortexa.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 049daa49321..19ed8087cdf 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -330,6 +330,7 @@ static size_t create_tdesc_cortex_a(char *buffer, size_t max_len) return (size_t)total; } +#ifdef ENABLE_DEBUG typedef struct bitfield_entry { char *desc; uint8_t bitnum; @@ -353,14 +354,13 @@ static const bitfields_lut_s cortexa_dbg_dscr_lut[] = { {"RXfull", 30U}, }; -static void helper_print_bitfields(const uint32_t val, const bitfields_lut_s lut[], const size_t array_length) +static void helper_print_bitfields(const uint32_t val, const bitfields_lut_s *lut, const size_t array_length) { for (size_t i = 0; i < array_length; i++) { - if (val & (1U << lut[i].bitnum)) { + if (val & (1U << lut[i].bitnum)) DEBUG_TARGET("%s ", lut[i].desc); - } } -}; +} static void cortexa_decode_bitfields(const uint32_t reg, const uint32_t val) { @@ -377,6 +377,13 @@ static void cortexa_decode_bitfields(const uint32_t reg, const uint32_t val) DEBUG_TARGET("\n"); } +#else +static void cortexa_decode_bitfields(const uint32_t reg, const uint32_t val) +{ + (void)reg; + (void)val; +} +#endif static void cortexar_run_insn(target_s *const target, const uint32_t insn) { @@ -579,9 +586,9 @@ bool cortexa_probe(adiv5_access_port_s *ap, target_addr_t base_address) #endif uint32_t dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); - DEBUG_INFO("%s: DBGOSLSR = 0x%08X\n", __func__, dbg_osreg); + DEBUG_INFO("%s: DBGOSLSR = 0x%08" PRIx32 "\n", __func__, dbg_osreg); /* Is OS Lock implemented? */ - if (((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM0) || ((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM1)) { + if ((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM0 || (dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM1) { /* Is OS Lock set? */ if (dbg_osreg & DBGOSLSR_OSLK) { DEBUG_WARN("%s: OSLock set! Trying to unlock\n", __func__); From 35fdb2b02f9b02f0e2c9937298b77b2f75b36101 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Sat, 23 Sep 2023 22:50:30 +0300 Subject: [PATCH 9/9] cortexa: Extend macro names for OS Lock related registers and bitfields --- src/target/cortexa.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 19ed8087cdf..a1e45ceebd5 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -98,11 +98,11 @@ typedef struct cortexa_priv { #define CORTEXAR_DBG_LAR 0xfb0U /* Lock Access */ #define CORTEXAR_DBG_LSR 0xfb4U /* Lock Status */ -#define DBGOSLSR_OSLM0 (1U << 0U) -#define DBGOSLSR_OSLK (1U << 1U) -#define DBGOSLSR_NTT (1U << 2U) -#define DBGOSLSR_OSLM1 (1U << 3U) -#define DBGOSLSR_OSLM (DBGOSLSR_OSLM0 | DBGOSLSR_OSLM1) +#define CORTEXAR_DBG_OSLSR_OSLM0 (1U << 0U) +#define CORTEXAR_DBG_OSLSR_OSLK (1U << 1U) +#define CORTEXAR_DBG_OSLSR_NTT (1U << 2U) +#define CORTEXAR_DBG_OSLSR_OSLM1 (1U << 3U) +#define CORTEXAR_DBG_OSLSR_OSLM (CORTEXAR_DBG_OSLSR_OSLM0 | CORTEXAR_DBG_OSLSR_OSLM1) #define CORTEXAR_DBG_IDR_BREAKPOINT_MASK 0xfU #define CORTEXAR_DBG_IDR_BREAKPOINT_SHIFT 24U @@ -588,14 +588,15 @@ bool cortexa_probe(adiv5_access_port_s *ap, target_addr_t base_address) uint32_t dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); DEBUG_INFO("%s: DBGOSLSR = 0x%08" PRIx32 "\n", __func__, dbg_osreg); /* Is OS Lock implemented? */ - if ((dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM0 || (dbg_osreg & DBGOSLSR_OSLM) == DBGOSLSR_OSLM1) { + if ((dbg_osreg & CORTEXAR_DBG_OSLSR_OSLM) == CORTEXAR_DBG_OSLSR_OSLM0 || + (dbg_osreg & CORTEXAR_DBG_OSLSR_OSLM) == CORTEXAR_DBG_OSLSR_OSLM1) { /* Is OS Lock set? */ - if (dbg_osreg & DBGOSLSR_OSLK) { + if (dbg_osreg & CORTEXAR_DBG_OSLSR_OSLK) { DEBUG_WARN("%s: OSLock set! Trying to unlock\n", __func__); cortex_dbg_write32(target, CORTEXAR_DBG_OSLAR, 0U); dbg_osreg = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR); - if ((dbg_osreg & DBGOSLSR_OSLK) != 0) { + if ((dbg_osreg & CORTEXAR_DBG_OSLSR_OSLK) != 0) { DEBUG_ERROR("%s: OSLock sticky, core not powered?\n", __func__); } }