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memory.c
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memory.c
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/* gameplaySP
*
* Copyright (C) 2006 Exophase <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define IN_MEMORY_C
#include "common.h"
static uint8_t IsNintendoBIOS = 0;
// This table is configured for sequential access on system defaults
u32 waitstate_cycles_sequential[16][3] =
{
{ 1, 1, 1 }, // BIOS
{ 1, 1, 1 }, // Invalid
{ 3, 3, 6 }, // EWRAM (default settings)
{ 1, 1, 1 }, // IWRAM
{ 1, 1, 1 }, // IO Registers
{ 1, 1, 2 }, // Palette RAM
{ 1, 1, 2 }, // VRAM
{ 1, 1, 2 }, // OAM
{ 3, 3, 6 }, // Gamepak (wait 0)
{ 3, 3, 6 }, // Gamepak (wait 0)
{ 5, 5, 9 }, // Gamepak (wait 1)
{ 5, 5, 9 }, // Gamepak (wait 1)
{ 9, 9, 17 }, // Gamepak (wait 2)
{ 9, 9, 17 }, // Gamepak (wait 2)
};
// Different settings for gamepak ws0-2 sequential (2nd) access
u32 gamepak_waitstate_sequential[2][3][3] =
{
{
{ 3, 3, 6 },
{ 5, 5, 9 },
{ 9, 9, 17 }
},
{
{ 2, 2, 3 },
{ 2, 2, 3 },
{ 2, 2, 3 }
}
};
FULLY_UNINITIALIZED(uint16_t palette_ram[0x200]);
FULLY_UNINITIALIZED(uint16_t oam_ram[0x200]);
FULLY_UNINITIALIZED(uint16_t palette_ram_converted[0x200]);
FULLY_UNINITIALIZED(uint16_t io_registers[1024 * 16]);
FULLY_UNINITIALIZED(uint8_t ewram[1024 * 256 * 2]);
FULLY_UNINITIALIZED(uint8_t iwram[1024 * 32 * 2]);
FULLY_UNINITIALIZED(uint8_t vram[1024 * 96 * 2]);
FULLY_UNINITIALIZED(uint8_t bios_rom[1024 * 32]);
uint32_t bios_read_protect;
// Up to 128kb, store SRAM, flash ROM, or EEPROM here.
uint8_t gamepak_backup[0x20000];
// Keeps us knowing how much we have left.
uint8_t *gamepak_rom;
uint32_t gamepak_size;
dma_transfer_type dma[4];
uint8_t *memory_regions[16];
uint32_t memory_limits[16];
typedef struct
{
uint32_t page_timestamp;
uint32_t physical_index;
} gamepak_swap_entry_type;
uint32_t gamepak_ram_buffer_size;
uint32_t gamepak_ram_pages;
// Enough to map the gamepak RAM space.
gamepak_swap_entry_type *gamepak_memory_map;
// This is global so that it can be kept open for large ROMs to swap
// pages from, so there's no slowdown with opening and closing the file
// a lot.
#ifdef PSP_BUILD
file_tag_type gamepak_file_large = -1;
#else
file_tag_type gamepak_file_large = NULL;
#endif
u32 direct_map_vram = 0;
// Writes to these respective locations should trigger an update
// so the related subsystem may react to it.
// If OAM is written to:
u32 oam_update = 1;
// If GBC audio is written to:
u32 gbc_sound_update = 0;
// If the GBC audio waveform is modified:
u32 gbc_sound_wave_update = 0;
// If the backup space is written (only update once this hits 0)
u32 backup_update = 0;
// Write out backup file this many cycles after the most recent
// backup write.
const u32 write_backup_delay = 10;
typedef enum
{
BACKUP_SRAM,
BACKUP_FLASH,
BACKUP_EEPROM,
BACKUP_NONE
} backup_type_type;
typedef enum
{
SRAM_SIZE_32KB,
SRAM_SIZE_64KB
} sram_size_type;
// Keep it 32KB until the upper 64KB is accessed, then make it 64KB.
backup_type_type backup_type = BACKUP_NONE;
sram_size_type sram_size = SRAM_SIZE_32KB;
typedef enum
{
FLASH_BASE_MODE,
FLASH_ERASE_MODE,
FLASH_ID_MODE,
FLASH_WRITE_MODE,
FLASH_BANKSWITCH_MODE
} flash_mode_type;
typedef enum
{
FLASH_SIZE_64KB,
FLASH_SIZE_128KB
} flash_size_type;
flash_mode_type flash_mode = FLASH_BASE_MODE;
u32 flash_command_position = 0;
u32 flash_bank_offset = 0;
flash_device_id_type flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
flash_manufacturer_id_type flash_manufacturer_id =
FLASH_MANUFACTURER_MACRONIX;
flash_size_type flash_size = FLASH_SIZE_64KB;
u8 read_backup(u32 address)
{
u8 value = 0;
if(backup_type == BACKUP_NONE)
backup_type = BACKUP_SRAM;
if(backup_type == BACKUP_SRAM)
{
value = gamepak_backup[address];
}
else
if(flash_mode == FLASH_ID_MODE)
{
/* ID manufacturer type */
if(address == 0x0000)
value = flash_manufacturer_id;
else
/* ID device type */
if(address == 0x0001)
value = flash_device_id;
}
else
{
value = gamepak_backup[flash_bank_offset + address];
}
return value;
}
#define read_backup8() \
value = read_backup(address & 0xFFFF) \
#define read_backup16() \
value = 0 \
#define read_backup32() \
value = 0 \
// EEPROM is 512 bytes by default; it is autodetecte as 8KB if
// 14bit address DMAs are made (this is done in the DMA handler).
typedef enum
{
EEPROM_512_BYTE,
EEPROM_8_KBYTE
} eeprom_size_type;
typedef enum
{
EEPROM_BASE_MODE,
EEPROM_READ_MODE,
EEPROM_READ_HEADER_MODE,
EEPROM_ADDRESS_MODE,
EEPROM_WRITE_MODE,
EEPROM_WRITE_ADDRESS_MODE,
EEPROM_ADDRESS_FOOTER_MODE,
EEPROM_WRITE_FOOTER_MODE
} eeprom_mode_type;
eeprom_size_type eeprom_size = EEPROM_512_BYTE;
eeprom_mode_type eeprom_mode = EEPROM_BASE_MODE;
u32 eeprom_address_length;
u32 eeprom_address = 0;
s32 eeprom_counter = 0;
u8 eeprom_buffer[8];
void function_cc write_eeprom(u32 address, u32 value)
{
switch(eeprom_mode)
{
case EEPROM_BASE_MODE:
backup_type = BACKUP_EEPROM;
eeprom_buffer[0] |= (value & 0x01) << (1 - eeprom_counter);
eeprom_counter++;
if(eeprom_counter == 2)
{
if(eeprom_size == EEPROM_512_BYTE)
eeprom_address_length = 6;
else
eeprom_address_length = 14;
eeprom_counter = 0;
switch(eeprom_buffer[0] & 0x03)
{
case 0x02:
eeprom_mode = EEPROM_WRITE_ADDRESS_MODE;
break;
case 0x03:
eeprom_mode = EEPROM_ADDRESS_MODE;
break;
}
address16(eeprom_buffer, 0) = 0;
}
break;
case EEPROM_ADDRESS_MODE:
case EEPROM_WRITE_ADDRESS_MODE:
eeprom_buffer[eeprom_counter / 8]
|= (value & 0x01) << (7 - (eeprom_counter % 8));
eeprom_counter++;
if(eeprom_counter == eeprom_address_length)
{
if(eeprom_size == EEPROM_512_BYTE)
{
eeprom_address =
(address16(eeprom_buffer, 0) >> 2) * 8;
}
else
{
eeprom_address = (((u32)eeprom_buffer[1] >> 2) |
((u32)eeprom_buffer[0] << 6)) * 8;
}
address16(eeprom_buffer, 0) = 0;
eeprom_counter = 0;
if(eeprom_mode == EEPROM_ADDRESS_MODE)
{
eeprom_mode = EEPROM_ADDRESS_FOOTER_MODE;
}
else
{
eeprom_mode = EEPROM_WRITE_MODE;
memset(gamepak_backup + eeprom_address, 0, 8);
}
}
break;
case EEPROM_WRITE_MODE:
gamepak_backup[eeprom_address + (eeprom_counter / 8)] |=
(value & 0x01) << (7 - (eeprom_counter % 8));
eeprom_counter++;
if(eeprom_counter == 64)
{
backup_update = write_backup_delay;
eeprom_counter = 0;
eeprom_mode = EEPROM_WRITE_FOOTER_MODE;
}
break;
case EEPROM_ADDRESS_FOOTER_MODE:
case EEPROM_WRITE_FOOTER_MODE:
eeprom_counter = 0;
if(eeprom_mode == EEPROM_ADDRESS_FOOTER_MODE)
{
eeprom_mode = EEPROM_READ_HEADER_MODE;
}
else
{
eeprom_mode = EEPROM_BASE_MODE;
}
break;
default:
break;
}
}
#define read_memory_gamepak(type) \
u32 gamepak_index = address >> 15; \
u8 *map = memory_map_read[gamepak_index]; \
\
if(map == NULL) \
map = load_gamepak_page(gamepak_index & 0x3FF); \
\
value = address##type(map, address & 0x7FFF) \
#define read_open8() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory8(reg[REG_PC] + 4 + (address & 0x03)); \
else \
value = read_memory8(reg[REG_PC] + 2 + (address & 0x01)) \
#define read_open16() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory16(reg[REG_PC] + 4 + (address & 0x02)); \
else \
value = read_memory16(reg[REG_PC] + 2) \
#define read_open32() \
if(!(reg[REG_CPSR] & 0x20)) \
{ \
value = read_memory32(reg[REG_PC] + 4); \
} \
else \
{ \
u32 current_instruction = read_memory16(reg[REG_PC] + 2); \
value = current_instruction | (current_instruction << 16); \
} \
u32 function_cc read_eeprom()
{
u32 value;
switch(eeprom_mode)
{
case EEPROM_BASE_MODE:
value = 1;
break;
case EEPROM_READ_MODE:
value = (gamepak_backup[eeprom_address + (eeprom_counter / 8)] >>
(7 - (eeprom_counter % 8))) & 0x01;
eeprom_counter++;
if(eeprom_counter == 64)
{
eeprom_counter = 0;
eeprom_mode = EEPROM_BASE_MODE;
}
break;
case EEPROM_READ_HEADER_MODE:
value = 0;
eeprom_counter++;
if(eeprom_counter == 4)
{
eeprom_mode = EEPROM_READ_MODE;
eeprom_counter = 0;
}
break;
default:
value = 0;
break;
}
return value;
}
#define read_memory(type) \
switch(address >> 24) \
{ \
case 0x00: \
/* BIOS */ \
if(reg[REG_PC] >= 0x4000) \
value = address##type(&bios_read_protect, address & 0x03); \
else \
value = address##type(bios_rom, address & 0x3FFF); \
break; \
\
case 0x02: \
/* external work RAM */ \
address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \
value = address##type(ewram, address); \
break; \
\
case 0x03: \
/* internal work RAM */ \
value = address##type(iwram, (address & 0x7FFF) + 0x8000); \
break; \
\
case 0x04: \
/* I/O registers */ \
value = address##type(io_registers, address & 0x3FF); \
break; \
\
case 0x05: \
/* palette RAM */ \
value = address##type(palette_ram, address & 0x3FF); \
break; \
\
case 0x06: \
/* VRAM */ \
address &= 0x1FFFF; \
if(address > 0x18000) \
address -= 0x8000; \
\
value = address##type(vram, address); \
break; \
\
case 0x07: \
/* OAM RAM */ \
value = address##type(oam_ram, address & 0x3FF); \
break; \
\
case 0x08: \
case 0x09: \
case 0x0A: \
case 0x0B: \
case 0x0C: \
/* gamepak ROM */ \
if((address & 0x1FFFFFF) >= gamepak_size) \
{ \
value = 0; \
} \
else \
{ \
read_memory_gamepak(type); \
} \
break; \
\
case 0x0D: \
if((address & 0x1FFFFFF) < gamepak_size) \
{ \
read_memory_gamepak(type); \
} \
else \
{ \
value = read_eeprom(); \
} \
\
break; \
\
case 0x0E: \
case 0x0F: \
read_backup##type(); \
break; \
\
default: \
read_open##type(); \
break; \
} \
#define trigger_dma(dma_number) \
if(value & 0x8000) \
{ \
if(dma[dma_number].start_type == DMA_INACTIVE) \
{ \
u32 start_type = (value >> 12) & 0x03; \
u32 dest_address = address32(io_registers, (dma_number * 12) + 0xB4) & \
0xFFFFFFF; \
\
dma[dma_number].dma_channel = dma_number; \
dma[dma_number].source_address = \
address32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF; \
dma[dma_number].dest_address = dest_address; \
dma[dma_number].source_direction = (value >> 7) & 0x03; \
dma[dma_number].repeat_type = (value >> 9) & 0x01; \
dma[dma_number].start_type = start_type; \
dma[dma_number].irq = (value >> 14) & 0x01; \
\
/* If it is sound FIFO DMA make sure the settings are a certain way */ \
if((dma_number >= 1) && (dma_number <= 2) && \
(start_type == DMA_START_SPECIAL)) \
{ \
dma[dma_number].length_type = DMA_32BIT; \
dma[dma_number].length = 4; \
dma[dma_number].dest_direction = DMA_FIXED; \
if(dest_address == 0x40000A4) \
dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_B; \
else \
dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_A; \
} \
else \
{ \
u32 length = \
address16(io_registers, (dma_number * 12) + 0xB8); \
\
if((dma_number == 3) && ((dest_address >> 24) == 0x0D) && \
((length & 0x1F) == 17)) \
{ \
eeprom_size = EEPROM_8_KBYTE; \
} \
\
if(dma_number < 3) \
length &= 0x3FFF; \
\
if(length == 0) \
{ \
if(dma_number == 3) \
length = 0x10000; \
else \
length = 0x04000; \
} \
\
dma[dma_number].length = length; \
dma[dma_number].length_type = (value >> 10) & 0x01; \
dma[dma_number].dest_direction = (value >> 5) & 0x03; \
} \
\
address16(io_registers, (dma_number * 12) + 0xBA) = value; \
if(start_type == DMA_START_IMMEDIATELY) \
return dma_transfer(dma + dma_number); \
} \
} \
else \
{ \
dma[dma_number].start_type = DMA_INACTIVE; \
dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND; \
address16(io_registers, (dma_number * 12) + 0xBA) = value; \
} \
#define access_register8_high(address) \
value = (value << 8) | (address8(io_registers, address)) \
#define access_register8_low(address) \
value = ((address8(io_registers, address + 1)) << 8) | value \
#define access_register16_high(address) \
value = (value << 16) | (address16(io_registers, address)) \
#define access_register16_low(address) \
value = ((address16(io_registers, address + 2)) << 16) | value \
cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
{
switch(address)
{
case 0x00:
{
u32 dispcnt = io_registers[REG_DISPCNT];
if((value & 0x07) != (dispcnt & 0x07))
oam_update = 1;
address8(io_registers, 0x00) = value;
break;
}
// DISPSTAT (lower byte)
case 0x04:
address8(io_registers, 0x04) =
(address8(io_registers, 0x04) & 0x07) | (value & ~0x07);
break;
// VCOUNT
case 0x06:
case 0x07:
break;
// BG2 reference X
case 0x28:
access_register8_low(0x28);
access_register16_low(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x28) = value;
break;
case 0x29:
access_register8_high(0x28);
access_register16_low(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x28) = value;
break;
case 0x2A:
access_register8_low(0x2A);
access_register16_high(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x28) = value;
break;
case 0x2B:
access_register8_high(0x2A);
access_register16_high(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x28) = value;
break;
// BG2 reference Y
case 0x2C:
access_register8_low(0x2C);
access_register16_low(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x2C) = value;
break;
case 0x2D:
access_register8_high(0x2C);
access_register16_low(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x2C) = value;
break;
case 0x2E:
access_register8_low(0x2E);
access_register16_high(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x2C) = value;
break;
case 0x2F:
access_register8_high(0x2E);
access_register16_high(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
address32(io_registers, 0x2C) = value;
break;
// BG3 reference X
case 0x38:
access_register8_low(0x38);
access_register16_low(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x38) = value;
break;
case 0x39:
access_register8_high(0x38);
access_register16_low(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x38) = value;
break;
case 0x3A:
access_register8_low(0x3A);
access_register16_high(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x38) = value;
break;
case 0x3B:
access_register8_high(0x3A);
access_register16_high(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x38) = value;
break;
// BG3 reference Y
case 0x3C:
access_register8_low(0x3C);
access_register16_low(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x3C) = value;
break;
case 0x3D:
access_register8_high(0x3C);
access_register16_low(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x3C) = value;
break;
case 0x3E:
access_register8_low(0x3E);
access_register16_high(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x3C) = value;
break;
case 0x3F:
access_register8_high(0x3E);
access_register16_high(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
address32(io_registers, 0x3C) = value;
break;
// Sound 1 control sweep
case 0x60:
access_register8_low(0x60);
gbc_sound_tone_control_sweep();
break;
case 0x61:
access_register8_low(0x60);
gbc_sound_tone_control_sweep();
break;
// Sound 1 control duty/length/envelope
case 0x62:
access_register8_low(0x62);
gbc_sound_tone_control_low(0, 0x62);
break;
case 0x63:
access_register8_high(0x62);
gbc_sound_tone_control_low(0, 0x62);
break;
// Sound 1 control frequency
case 0x64:
access_register8_low(0x64);
gbc_sound_tone_control_high(0, 0x64);
break;
case 0x65:
access_register8_high(0x64);
gbc_sound_tone_control_high(0, 0x64);
break;
// Sound 2 control duty/length/envelope
case 0x68:
access_register8_low(0x68);
gbc_sound_tone_control_low(1, 0x68);
break;
case 0x69:
access_register8_high(0x68);
gbc_sound_tone_control_low(1, 0x68);
break;
// Sound 2 control frequency
case 0x6C:
access_register8_low(0x6C);
gbc_sound_tone_control_high(1, 0x6C);
break;
case 0x6D:
access_register8_high(0x6C);
gbc_sound_tone_control_high(1, 0x6C);
break;
// Sound 3 control wave
case 0x70:
access_register8_low(0x70);
gbc_sound_wave_control();
break;
case 0x71:
access_register8_high(0x70);
gbc_sound_wave_control();
break;
// Sound 3 control length/volume
case 0x72:
access_register8_low(0x72);
gbc_sound_tone_control_low_wave();
break;
case 0x73:
access_register8_high(0x72);
gbc_sound_tone_control_low_wave();
break;
// Sound 3 control frequency
case 0x74:
access_register8_low(0x74);
gbc_sound_tone_control_high_wave();
break;
case 0x75:
access_register8_high(0x74);
gbc_sound_tone_control_high_wave();
break;
// Sound 4 control length/envelope
case 0x78:
access_register8_low(0x78);
gbc_sound_tone_control_low(3, 0x78);
break;
case 0x79:
access_register8_high(0x78);
gbc_sound_tone_control_low(3, 0x78);
break;
// Sound 4 control frequency
case 0x7C:
access_register8_low(0x7C);
gbc_sound_noise_control();
break;
case 0x7D:
access_register8_high(0x7C);
gbc_sound_noise_control();
break;
// Sound control L
case 0x80:
access_register8_low(0x80);
gbc_trigger_sound();
break;
case 0x81:
access_register8_high(0x80);
gbc_trigger_sound();
break;
// Sound control H
case 0x82:
access_register8_low(0x82);
trigger_sound();
break;
case 0x83:
access_register8_high(0x82);
trigger_sound();
break;
// Sound control X
case 0x84:
sound_on();
break;
// Sound wave RAM
case 0x90 ... 0x9F:
gbc_sound_wave_update = 1;
address8(io_registers, address) = value;
break;
// Sound FIFO A
case 0xA0 ... 0xA3:
address8(io_registers, address) = value;
sound_timer_queue32(0, value);
break;
// Sound FIFO B
case 0xA4 ... 0xA7:
address8(io_registers, address) = value;
sound_timer_queue32(1, value);
break;
// DMA control (trigger byte)
case 0xBB: // DMA channel 0
case 0xC7: // DMA channel 1
case 0xD3: // DMA channel 2
case 0xDF: // DMA channel 3
access_register8_high(address - 1);
trigger_dma((address - 0xBB) / 12);
break;
// Timer counts
case 0x100:
access_register8_low(0x100);
count_timer(0);
break;
case 0x101:
access_register8_high(0x100);
count_timer(0);
break;
case 0x104:
access_register8_low(0x104);
count_timer(1);
break;
case 0x105:
access_register8_high(0x104);
count_timer(1);
break;
case 0x108:
access_register8_low(0x108);
count_timer(2);
break;
case 0x109:
access_register8_high(0x108);
count_timer(2);
break;
case 0x10C:
access_register8_low(0x10C);
count_timer(3);
break;
case 0x10D:
access_register8_high(0x10C);
count_timer(3);
break;
// Timer control (trigger byte)
case 0x103: // Timer 0
case 0x107: // Timer 1
case 0x10B: // Timer 2
case 0x10F: // Timer 3
access_register8_high(address - 1);
trigger_timer((address - 0x103) / 4);
break;
case 0x128:
case 0x129:
case 0x134:
case 0x135:
// P1
case 0x130:
case 0x131:
/* Read only */
break;
// IE
case 0x200:
address8(io_registers, 0x200) = value;
break;
// IF
case 0x202:
address8(io_registers, 0x202) &= ~value;
break;
case 0x203:
address8(io_registers, 0x203) &= ~value;
break;
// Halt
case 0x301:
if((value & 0x01) == 0)
reg[CPU_HALT_STATE] = CPU_HALT;
else
reg[CPU_HALT_STATE] = CPU_STOP;
return CPU_ALERT_HALT;
break;
default:
address8(io_registers, address) = value;
break;
}
return CPU_ALERT_NONE;
}
cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
{
switch(address)
{
case 0x00:
{
u32 dispcnt = io_registers[REG_DISPCNT];
if((value & 0x07) != (dispcnt & 0x07))
oam_update = 1;
address16(io_registers, 0x00) = value;
break;
}
// DISPSTAT
case 0x04:
address16(io_registers, 0x04) =
(address16(io_registers, 0x04) & 0x07) | (value & ~0x07);
break;
// VCOUNT
case 0x06:
break;