From 3e29db25ff6c8fb93804fb4eeb6cc1ce81790ab7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bob=20Dr=C3=B6ge?= Date: Tue, 7 May 2024 23:34:43 +0200 Subject: [PATCH] add RISC-V support --- easybuild/easyblocks/c/clang.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/easybuild/easyblocks/c/clang.py b/easybuild/easyblocks/c/clang.py index b945553969..af9c105910 100644 --- a/easybuild/easyblocks/c/clang.py +++ b/easybuild/easyblocks/c/clang.py @@ -49,13 +49,13 @@ from easybuild.tools.filetools import apply_regex_substitutions, change_dir, mkdir, symlink, which from easybuild.tools.modules import get_software_root from easybuild.tools.run import run_cmd -from easybuild.tools.systemtools import AARCH32, AARCH64, POWER, X86_64 +from easybuild.tools.systemtools import AARCH32, AARCH64, POWER, RISCV64, X86_64 from easybuild.tools.systemtools import get_cpu_architecture, get_os_name, get_os_version, get_shared_lib_ext from easybuild.tools.environment import setvar # List of all possible build targets for Clang CLANG_TARGETS = ["all", "AArch64", "AMDGPU", "ARM", "CppBackend", "Hexagon", "Mips", - "MBlaze", "MSP430", "NVPTX", "PowerPC", "R600", "Sparc", + "MBlaze", "MSP430", "NVPTX", "PowerPC", "R600", "RISCV", "Sparc", "SystemZ", "X86", "XCore"] # Mapping of EasyBuild CPU architecture names to list of default LLVM target names @@ -63,6 +63,7 @@ AARCH32: ['ARM'], AARCH64: ['AArch64'], POWER: ['PowerPC'], + RISCV64: ['RISCV'], X86_64: ['X86'], }