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project.jelib
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project.jelib
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# header information:
Hproject|8.05
# Views:
Vicon|ic
Vlayout|lay
Vnetlist.als|net.als
Vschematic|sch
VVHDL|vhdl
# Technologies:
Tfpga|ScaleFORfpga()D1000.0
Tmocmos|MoCMOSAlternateActivePolyRules()BT|ScaleFORmocmos()D300.0|mocmosNumberOfMetalLayers()I3|mocmosSecondPolysilicon()BF
Trcmos|ScaleFORrcmos()D1000.0
# Cell and2;1{ic}
Cand2;1{ic}||artwork|977243566000|1194494622626|E
NOpened-Polygon|art@0||1|5|2|6|||trace()V[1/-3,-1/-3,-1/3,1/3]
NCircle|art@1||2|5|6|6|RRR||ART_degrees()F[0.0,3.1415927]
NOpened-Polygon|art@2||6|5|2||||trace()V[1/0,-1/0]
NOpened-Polygon|art@3||-1|3|2||||trace()V[-1/0,1/0]
NOpened-Polygon|art@4||-1|7|2||||trace()V[-1/0,1/0]
Ngeneric:Invisible-Pin|pin@0||2|5|||||ART_message(D5G1;)S[and2]
Ngeneric:Invisible-Pin|pin@1||7|5||||
Ngeneric:Invisible-Pin|pin@2||-2|3||||
Ngeneric:Invisible-Pin|pin@3||-2|7||||
Ea||D5G1;|pin@3||I/A
Eb||D5G1;|pin@2||I/A
Ey||D5G1;|pin@1||O/A
X
# Cell and2;1{lay}
Cand2;1{lay}||mocmos|1189297628000|1194494622626||DRC_last_good_drc()I1191785648|NET_ncc_last_result1()S[TIME 1191785677,MATCH lab3_BC:and2{sch},EXPORT a:a,EXPORT b:b,EXPORT y:y]|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
Iinv;1{lay}|inv@0||-147|16|||D0G4;
Inand2;1{lay}|nand2@0||-170|16|||D0G4;
NMetal-1-Pin|pin@0||-144|65||||
AMetal-1|net@0||1|S1800|nand2@0|y|-160|65|pin@0||-144|65
AMetal-1|net@1||1|S900|pin@0||-144|65|inv@0|a|-144|55
AMetal-2|net@2||1|S0|inv@0|vdd|-147|96|nand2@0|vdd|-170|96
AMetal-2|net@3||1|S0|inv@0|gnd|-147|16|nand2@0|gnd|-170|16
Ea||D5G2;|nand2@0|a|I
Eb||D5G2;|nand2@0|b|I
Egnd||D5G2;|inv@0|gnd|G
Evdd||D5G2;|nand2@0|vdd|P
Ey||D5G2;|inv@0|y|O
X
# Cell and2;1{sch}
Cand2;1{sch}||schematic|1189297316000|1194494622626||NET_ncc_last_result1()S[TIME 1191785677,MATCH lab3_BC:and2{lay},EXPORT a:a,EXPORT b:b,EXPORT y:y]|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
Iinv;1{ic}|inv@0||5|-5|||D0G4;
Inand2;1{ic}|nand2@0||-4|0|||D0G4;
Awire|yb|D8G1;||1800|nand2@0|y|1|0|inv@0|a|3|0
Ea||D5G1;|nand2@0|a|I
Eb||D5G1;|nand2@0|b|I
Ey||D5G1;|inv@0|y|O
X
# Cell cam;1{net.als}
Ccam;1{net.als}||artwork|1194677141121|1194677141122||FACET_message()S[#*************************************************,# ALS Netlist file,#,"# File Creation: Sat Nov 10, 2007 06:45:41",#-------------------------------------------------,"","model inv(a, y)",gnd_0: ground(gnd),"nmos_0: nMOStran(a, gnd, y)","pmos_0: PMOStran(a, y, vdd)",pwr_0: power(vdd),"","model nand2(a, b, y)",gnd_0: ground(gnd),"nmos_0: nMOStran(a, gnd, net_19)","nmos_1: nMOStran(b, net_19, y)","pmos_0: PMOStran(a, y, vdd)","pmos_1: PMOStran(b, y, vdd)",pwr_0: power(vdd),"","model and2(a, b, y)","inv_0: inv(yb, y)","nand2_0: nand2(a, b, yb)","","model found(match, notFoundPrev, notFound, use_)","and2_5: and2(notFoundPrev, match, use_)","and2_6: and2(notFoundPrev, net_63, notFound)","inv_5: inv(match, net_63)","","model latch(D, en, Q, Qbar)","nand2_0: nand2(D, en, net_9)","nand2_1: nand2(net_9, Qbar, Q)","nand2_3: nand2(net_9, en, net_10)","nand2_4: nand2(Q, net_10, Qbar)","","model nor2(a, b, y)",gnd_0: ground(gnd),"nmos_0: nMOStran(b, gnd, y)","nmos_1: nMOStran(a, gnd, y)","pmos_0: PMOStran(b, y, net_17)","pmos_1: PMOStran(a, net_17, vdd)",pwr_0: power(vdd),"","model or2(a, b, y)","inv_0: inv(yb, y)","nor2_0: nor2(a, b, yb)","","model xnor2(a, b, y)","inv_0: inv(b, net_5)","inv_1: inv(a, net_4)","nand2_0: nand2(a, b, net_0)","nand2_1: nand2(net_5, net_4, net_2)","nand2_3: nand2(net_0, net_2, y)","","model match(input, key, mask, matchPrev, match)","and2_0: and2(matchPrev, net_1, match)","or2_0: or2(mask, net_23, net_1)","xnor2_0: xnor2(input, key, net_23)","","model slice(data_0_, data_1_, data_2_, delete, fullPrev, input_0_, input_1_, mask_0_, mask_1_, notFoundPrev, outputPrev_0_, outputPrev_1_, outputPrev_2_, pass, reset, write, full, notFound, output_0_, output_1_, output_2_)","and2_0: and2(net_38, net_39, net_56)","and2_4: and2(net_139, net_40, net_92)","and2_5: and2(net_90, net_92, net_95)","and2_6: and2(net_122, net_92, net_127)","and2_8: and2(net_130, net_92, net_135)","found_0: found(net_14, notFoundPrev, notFound, net_40)","found_1: found(net_246, fullPrev, full, net_47)","inv_2: inv(pass, net_139)","inv_3: inv(net_263, net_260)","latch_1: latch(input_0_, net_56, net_7, n0)","latch_2: latch(input_1_, net_56, net_10, n1)","latch_3: latch(data_0_, net_56, net_90, n2)","latch_4: latch(data_1_, net_56, net_122, n3)","latch_5: latch(data_2_, net_56, net_130, n4)","latch_6: latch(net_257, net_258, net_211, net_246)","match_0: match(input_0_, net_7, mask_0_, net_211, net_9)","match_1: match(input_1_, net_10, mask_1_, net_9, net_14)","or2_1: or2(delete, write, net_38)","or2_2: or2(net_40, net_47, net_39)","or2_3: or2(outputPrev_0_, net_95, output_0_)","or2_4: or2(outputPrev_1_, net_127, output_1_)","or2_5: or2(outputPrev_2_, net_135, output_2_)","or2_7: or2(net_260, write, net_257)","or2_8: or2(net_263, net_56, net_258)","or2_9: or2(reset, delete, net_263)","","model cam(data_0_, data_1_, data_2_, delete, input_0_, input_1_, mask_0_, mask_1_, pass, reset, write, full, notFound, output_0_, output_1_, output_2_)",pwr_0: power(vdd),"and2_0: and2(data_1_, pass, net_47)","and2_1: and2(data_2_, pass, net_51)","and2_2: and2(data_0_, pass, net_43)","slice_0: slice(data_0_, data_1_, data_2_, delete, notFound, input_0_, input_1_, mask_0_, mask_1_, vdd, net_43, net_47, net_51, pass, reset, write, net_8, net_6, net_4, net_2, net_0)","slice_1: slice(data_0_, data_1_, data_2_, delete, net_8, input_0_, input_1_, mask_0_, mask_1_, net_6, net_4, net_2, net_0, pass, reset, write, net_58, net_60, net_62, net_64, net_66)","slice_2: slice(data_0_, data_1_, data_2_, delete, net_58, input_0_, input_1_, mask_0_, mask_1_, net_60, net_62, net_64, net_66, pass, reset, write, full, notFound, output_0_, output_1_, output_2_)","",#********* End of netlist *******************,"",# Built-in model for PMOStran,"function PMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8,"",# Built-in model for nMOStran,"function nMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8,"",# Built-in model for ground,gate ground(g),set g=L@3,t: delta=0,"",# Built-in model for power,gate power(p),set p=H@3,t: delta=0]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell cam;1{sch}
Ccam;1{sch}||schematic|1194658516931|1194659234499|
Iand2;1{ic}|and2@0||-33|39|||D5G4;
Iand2;1{ic}|and2@1||-33|48|||D5G4;
Iand2;1{ic}|and2@2||-33|30|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NWire_Pin|pin@0||-17|-7||||
NWire_Pin|pin@1||-13|-5||||
NWire_Pin|pin@2||-14|6||||
NWire_Pin|pin@3||-5|-1||||
NWire_Pin|pin@4||-1|-13||||
NWire_Pin|pin@5||-31|19||||
NWire_Pin|pin@6||-30|21||||
NWire_Pin|pin@7||-42|23||||
NWire_Pin|pin@8||19|19||||
NWire_Pin|pin@9||16|21||||
NWire_Pin|pin@10||13|23||||
NWire_Pin|pin@11||14|25||||
NWire_Pin|pin@13||-11.5|5||||
NWire_Pin|pin@14||-11.5|6||||
NWire_Pin|pin@15||0|36||||
NWire_Pin|pin@16||30|23||||
NWire_Pin|pin@17||29|25||||
NWire_Pin|pin@18||27|27||||
NWire_Pin|pin@19||-35|23||||
NWire_Pin|pin@20||-35|27||||
NWire_Pin|pin@21||-26|29||||
NWire_Pin|pin@22||-35|25||||
NWire_Pin|pin@23||-26|27||||
NWire_Pin|pin@24||30|55||||
NWire_Pin|pin@25||-26|25||||
NWire_Pin|pin@27||-5|-32||||
NWire_Pin|pin@29||-1|-47||||
NWire_Pin|pin@30||-5|-35||||
NWire_Pin|pin@31||-9|-37||||
NWire_Pin|pin@32||-13|-39||||
NWire_Pin|pin@33||-17|-41||||
NWire_Pin|pin@34||-2|-57||||
NWire_Pin|pin@35||-5|-68||||
NWire_Pin|pin@36||-1|-64||||
NWire_Pin|pin@37||-9|-63||||
NWire_Pin|pin@38||-13|-65||||
NWire_Pin|pin@39||-17|-68||||
NPower|pwr@0||-12|41||||
Islice;1{ic}|slice@0||-9|14|||D5G4;
Islice;1{ic}|slice@1||-9|-18|||D5G4;
Islice;1{ic}|slice@2||-9|-52|||D5G4;
Awire|net@0|||1800|slice@1|outputPrev[2]|-18|-7|pin@0||-17|-7
Awire|net@1|||2700|pin@0||-17|-7|slice@0|output[2]|-17|9
Awire|net@2|||1800|slice@1|outputPrev[1]|-16|-5|pin@1||-13|-5
Awire|net@3|||2700|pin@1||-13|-5|slice@0|output[1]|-13|7
Awire|net@4|||2700|slice@1|outputPrev[0]|-14|-3|pin@2||-14|6
Awire|net@5|||900|pin@14||-11.5|6|pin@13||-11.5|5
Awire|net@6|||1800|slice@1|notFoundPrev|-12|-1|pin@3||-5|-1
Awire|net@7|||2700|pin@3||-5|-1|slice@0|notFound|-5|9
Awire|net@8|||1800|slice@1|fullPrev|-2|-13|pin@4||-1|-13
Awire|net@9|||2700|pin@4||-1|-13|slice@0|full|-1|7
Awire|net@10|||2700|slice@1|write|-24|-13|slice@0|write|-24|19
Awire|net@11|||0|slice@0|write|-24|19|pin@5||-31|19
Awire|net@12|||2700|slice@1|reset|-22|-11|slice@0|reset|-22|21
Awire|net@13|||0|slice@0|reset|-22|21|pin@6||-30|21
Awire|net@14|||2700|slice@1|pass|-20|-9|slice@0|pass|-20|23
Awire|net@15|||0|slice@0|pass|-20|23|pin@19||-35|23
Awire|net@16|||2700|slice@1|mask[1]|-10|-13|slice@0|mask[1]|-10|19
Awire|net@17|||1800|slice@0|mask[1]|-10|19|pin@8||19|19
Awire|net@18|||2700|slice@1|mask[0]|-8|-11|slice@0|mask[0]|-8|21
Awire|net@19|||1800|slice@0|mask[0]|-8|21|pin@9||16|21
Awire|net@20|||2700|slice@1|input[1]|-6|-9|slice@0|input[1]|-6|23
Awire|net@21|||1800|slice@0|input[1]|-6|23|pin@10||13|23
Awire|net@22|||2700|slice@1|input[0]|-4|-7|slice@0|input[0]|-4|25
Awire|net@23|||1800|slice@0|input[0]|-4|25|pin@11||14|25
Awire|net@26|||1800|pin@2||-14|6|pin@14||-11.5|6
Awire|net@28|||1800|pin@13||-11.5|5|slice@0|output[0]|-9|5
Awire|net@29|||2700|slice@1|delete|0|-11|slice@0|delete|0|21
Awire|net@30|||2700|slice@0|delete|0|21|pin@15||0|36
Awire|net@31|||2700|slice@1|data[2]|2|-9|slice@0|data[2]|2|23
Awire|net@32|||1800|slice@0|data[2]|2|23|pin@16||30|23
Awire|net@33|||2700|slice@1|data[1]|4|-7|slice@0|data[1]|4|25
Awire|net@34|||1800|slice@0|data[1]|4|25|pin@17||29|25
Awire|net@35|||2700|slice@1|data[0]|6|-5|slice@0|data[0]|6|27
Awire|net@36|||1800|slice@0|data[0]|6|27|pin@18||27|27
Awire|net@37|||0|pin@19||-35|23|pin@7||-42|23
Awire|net@38|||2700|pin@19||-35|23|and2@2|b|-35|33
Awire|net@39|||2700|and2@2|b|-35|33|and2@0|b|-35|42
Awire|net@40|||2700|and2@0|b|-35|42|and2@1|b|-35|51
Awire|net@41|||0|pin@18||27|27|pin@20||-35|27
Awire|net@42|||2700|pin@20||-35|27|and2@2|a|-35|37
Awire|net@43|||900|and2@2|y|-26|35|pin@21||-26|29
Awire|net@44|||1800|pin@21||-26|29|slice@0|outputPrev[0]|-14|29
Awire|net@45|||0|pin@17||29|25|pin@22||-35|25
Awire|net@46|||2700|pin@22||-35|25|and2@0|a|-35|46
Awire|net@47|||900|and2@0|y|-26|44|pin@23||-26|27
Awire|net@48|||1800|pin@23||-26|27|slice@0|outputPrev[1]|-16|27
Awire|net@49|||2700|pin@16||30|23|pin@24||30|55
Awire|net@50|||0|pin@24||30|55|and2@1|a|-35|55
Awire|net@51|||900|and2@1|y|-26|53|pin@25||-26|25
Awire|net@52|||1800|pin@25||-26|25|slice@0|outputPrev[2]|-18|25
Awire|net@53|||2700|slice@0|notFoundPrev|-12|31|pwr@0||-12|41
Awire|net@58|||1800|slice@2|fullPrev|-2|-47|pin@29||-1|-47
Awire|net@59|||2700|pin@29||-1|-47|slice@1|full|-1|-25
Awire|net@60|||1800|slice@2|notFoundPrev|-12|-35|pin@30||-5|-35
Awire|net@61|||2700|pin@30||-5|-35|slice@1|notFound|-5|-23
Awire|net@62|||900|slice@1|output[0]|-9|-27|pin@31||-9|-37
Awire|net@63|||0|pin@31||-9|-37|slice@2|outputPrev[0]|-14|-37
Awire|net@64|||900|slice@1|output[1]|-13|-25|pin@32||-13|-39
Awire|net@65|||0|pin@32||-13|-39|slice@2|outputPrev[1]|-16|-39
Awire|net@66|||900|slice@1|output[2]|-17|-23|pin@33||-17|-41
Awire|net@67|||0|pin@33||-17|-41|slice@2|outputPrev[2]|-18|-41
Awire|net@68|||2700|slice@2|write|-24|-47|slice@1|write|-24|-13
Awire|net@69|||2700|slice@2|reset|-22|-45|slice@1|reset|-22|-11
Awire|net@70|||2700|slice@2|pass|-20|-43|slice@1|pass|-20|-9
Awire|net@71|||2700|slice@2|mask[1]|-10|-47|slice@1|mask[1]|-10|-13
Awire|net@72|||2700|slice@2|mask[0]|-8|-45|slice@1|mask[0]|-8|-11
Awire|net@73|||2700|slice@2|input[1]|-6|-43|slice@1|input[1]|-6|-9
Awire|net@74|||2700|slice@2|input[0]|-4|-41|slice@1|input[0]|-4|-7
Awire|net@75|||2700|slice@2|delete|0|-45|slice@1|delete|0|-11
Awire|net@76|||2700|slice@2|data[2]|2|-43|slice@1|data[2]|2|-9
Awire|net@77|||2700|slice@2|data[1]|4|-41|slice@1|data[1]|4|-7
Awire|net@78|||2700|slice@2|data[0]|6|-39|slice@1|data[0]|6|-5
Awire|net@79|||900|slice@0|fullPrev|-2|19|pin@34||-2|-57
Awire|net@80|||0|pin@34||-2|-57|slice@2|notFound|-5|-57
Awire|net@81|||900|slice@2|notFound|-5|-57|pin@35||-5|-68
Awire|net@82|||900|slice@2|full|-1|-59|pin@36||-1|-64
Awire|net@83|||900|slice@2|output[0]|-9|-61|pin@37||-9|-63
Awire|net@84|||900|slice@2|output[1]|-13|-59|pin@38||-13|-65
Awire|net@85|||900|slice@2|output[2]|-17|-57|pin@39||-17|-68
Edata[0]||D5G2;|pin@18||I
Edata[1]@392009634|data[1]|D5G2;|pin@17||I
Edata[1]|data[2]|D5G2;|pin@16||I
Edelete||D5G2;|pin@15||I
Efull||D5G2;|pin@36||O
Einput[0]||D5G2;|pin@11||I
Einput[1]||D5G2;|pin@10||I
Emask[0]||D5G2;|pin@9||I
Emask[1]||D5G2;|pin@8||I
EnotFound||D5G2;|pin@35||O
Eoutput[0]||D5G2;|pin@37||O
Eoutput[1]||D5G2;|pin@38||O
Eoutput[2]||D5G2;|pin@39||O
Epass||D5G2;|pin@7||I
Ereset||D5G2;|pin@6||I
Ewrite||D5G2;|pin@5||I
X
# Cell cam;1{vhdl}
Ccam;1{vhdl}||artwork|1194677141102|1194677141122||FACET_message()S[-- VHDL automatically generated by Electric 8.05 for cell 'cam{sch}',"entity cam is port(data_0_, data_1_, data_2_, delete, input_0_, input_1_, mask_0_, mask_1_, pass, reset, write: in BIT; full, notFound, output_0_, output_1_, output_2_: out BIT);", end cam;,"",architecture cam_BODY of cam is," component and2 port(a, b: in BIT; y: out BIT);", end component;, component power port(vdd: out BIT);, end component;," component slice port(data_0_, data_1_, data_2_, delete, fullPrev, input_0_, input_1_, mask_0_, mask_1_, notFoundPrev, outputPrev_0_, outputPrev_1_, outputPrev_2_, pass, reset, write: in BIT; full, notFound, output_0_, output_1_, output_2_: out BIT);", end component;,""," signal net_51, net_47, vdd, net_43, net_64, net_66, net_62, net_60, net_0, "," net_8, net_6, net_4, net_2, net_58: BIT;","",begin, pwr_0: power port map(vdd);," and2_0: and2 port map(data_1_, pass, net_47);"," and2_1: and2 port map(data_2_, pass, net_51);"," and2_2: and2 port map(data_0_, pass, net_43);"," slice_0: slice port map(data_0_, data_1_, data_2_, delete, notFound, input_0_, input_1_, mask_0_, mask_1_, vdd, net_43, net_47, net_51, pass, reset, write, net_8, net_6, net_4, net_2, net_0);"," slice_1: slice port map(data_0_, data_1_, data_2_, delete, net_8, input_0_, input_1_, mask_0_, mask_1_, net_6, net_4, net_2, net_0, pass, reset, write, net_58, net_60, net_62, net_64, net_66);"," slice_2: slice port map(data_0_, data_1_, data_2_, delete, net_58, input_0_, input_1_, mask_0_, mask_1_, net_60, net_62, net_64, net_66, pass, reset, write, full, notFound, output_0_, output_1_, output_2_);",end cam_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'and2{sch}',"entity and2 is port(a, b: in BIT; y: out BIT);", end and2;,"",architecture and2_BODY of and2 is, component inv port(a: in BIT; y: out BIT);, end component;," component nand2 port(a, b: in BIT; y: out BIT);", end component;,"", signal yb: BIT;,"",begin," inv_0: inv port map(yb, y);"," nand2_0: nand2 port map(a, b, yb);",end and2_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'inv{sch}',entity inv is port(a: in BIT; y: out BIT);, end inv;,"",architecture inv_BODY of inv is, component ground port(gnd: out BIT);, end component;," component nMOStran port(g: in BIT; s, d: inout BIT);", end component;," component PMOStran port(g: in BIT; s, d: inout BIT);", end component;, component power port(vdd: out BIT);, end component;,""," signal gnd, vdd: BIT;","",begin, gnd_0: ground port map(gnd);," nmos_0: nMOStran port map(a, gnd, y);"," pmos_0: PMOStran port map(a, y, vdd);", pwr_0: power port map(vdd);,end inv_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'nand2{sch}',"entity nand2 is port(a, b: in BIT; y: out BIT);", end nand2;,"",architecture nand2_BODY of nand2 is, component ground port(gnd: out BIT);, end component;," component nMOStran port(g: in BIT; s, d: inout BIT);", end component;," component PMOStran port(g: in BIT; s, d: inout BIT);", end component;, component power port(vdd: out BIT);, end component;,""," signal gnd, vdd, net_19: BIT;","",begin, gnd_0: ground port map(gnd);," nmos_0: nMOStran port map(a, gnd, net_19);"," nmos_1: nMOStran port map(b, net_19, y);"," pmos_0: PMOStran port map(a, y, vdd);"," pmos_1: PMOStran port map(b, y, vdd);", pwr_0: power port map(vdd);,end nand2_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'slice{sch}',"entity slice is port(data_0_, data_1_, data_2_, delete, fullPrev, input_0_, input_1_, mask_0_, mask_1_, notFoundPrev, outputPrev_0_, outputPrev_1_, outputPrev_2_, pass, reset, write: in BIT; full, notFound, output_0_, output_1_, output_2_: out BIT);", end slice;,"",architecture slice_BODY of slice is," component and2 port(a, b: in BIT; y: out BIT);", end component;," component found port(match_, notFoundPrev: in BIT; notFound, use_: out BIT);", end component;, component inv port(a: in BIT; y: out BIT);, end component;," component latch port(D, en: in BIT; Q, Qbar: out BIT);", end component;," component match port(input, key, mask, matchPrev: in BIT; match_: out BIT);", end component;," component or2 port(a, b: in BIT; y: out BIT);", end component;,""," signal net_263, net_95, net_90, net_260, net_92, net_122, net_47, net_127, "," net_246, net_40, net_130, net_38, net_9, net_211, net_135, net_10, net_7, "," net_139, net_14, net_56, net_257, net_258, net_39: BIT;","",begin," and2_0: and2 port map(net_38, net_39, net_56);"," and2_4: and2 port map(net_139, net_40, net_92);"," and2_5: and2 port map(net_90, net_92, net_95);"," and2_6: and2 port map(net_122, net_92, net_127);"," and2_8: and2 port map(net_130, net_92, net_135);"," found_0: found port map(net_14, notFoundPrev, notFound, net_40);"," found_1: found port map(net_246, fullPrev, full, net_47);"," inv_2: inv port map(pass, net_139);"," inv_3: inv port map(net_263, net_260);"," latch_1: latch port map(input_0_, net_56, net_7, open);"," latch_2: latch port map(input_1_, net_56, net_10, open);"," latch_3: latch port map(data_0_, net_56, net_90, open);"," latch_4: latch port map(data_1_, net_56, net_122, open);"," latch_5: latch port map(data_2_, net_56, net_130, open);"," latch_6: latch port map(net_257, net_258, net_211, net_246);"," match_0: match port map(input_0_, net_7, mask_0_, net_211, net_9);"," match_1: match port map(input_1_, net_10, mask_1_, net_9, net_14);"," or2_1: or2 port map(delete, write, net_38);"," or2_2: or2 port map(net_40, net_47, net_39);"," or2_3: or2 port map(outputPrev_0_, net_95, output_0_);"," or2_4: or2 port map(outputPrev_1_, net_127, output_1_);"," or2_5: or2 port map(outputPrev_2_, net_135, output_2_);"," or2_7: or2 port map(net_260, write, net_257);"," or2_8: or2 port map(net_263, net_56, net_258);"," or2_9: or2 port map(reset, delete, net_263);",end slice_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'found{sch}',"entity found is port(match, notFoundPrev: in BIT; notFound, use_: out BIT);", end found;,"",architecture found_BODY of found is," component and2 port(a, b: in BIT; y: out BIT);", end component;, component inv port(a: in BIT; y: out BIT);, end component;,"", signal net_63: BIT;,"",begin," and2_5: and2 port map(notFoundPrev, match, use_);"," and2_6: and2 port map(notFoundPrev, net_63, notFound);"," inv_5: inv port map(match, net_63);",end found_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'latch{sch}',"entity latch is port(D, en: in BIT; Q, Qbar: out BIT);", end latch;,"",architecture latch_BODY of latch is," component nand2 port(a, b: in BIT; y: out BIT);", end component;,""," signal net_9, net_10: BIT;","",begin," nand2_0: nand2 port map(D, en, net_9);"," nand2_1: nand2 port map(net_9, Qbar, Q);"," nand2_3: nand2 port map(net_9, en, net_10);"," nand2_4: nand2 port map(Q, net_10, Qbar);",end latch_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'match{sch}',"entity match is port(input, key, mask, matchPrev: in BIT; match: out BIT);", end match;,"",architecture match_BODY of match is," component and2 port(a, b: in BIT; y: out BIT);", end component;," component or2 port(a, b: in BIT; y: out BIT);", end component;," component xnor2 port(a, b: in BIT; y: out BIT);", end component;,""," signal net_23, net_1: BIT;","",begin," and2_0: and2 port map(matchPrev, net_1, match);"," or2_0: or2 port map(mask, net_23, net_1);"," xnor2_0: xnor2 port map(input, key, net_23);",end match_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'or2{sch}',"entity or2 is port(a, b: in BIT; y: out BIT);", end or2;,"",architecture or2_BODY of or2 is, component inv port(a: in BIT; y: out BIT);, end component;," component nor2 port(a, b: in BIT; y: out BIT);", end component;,"", signal yb: BIT;,"",begin," inv_0: inv port map(yb, y);"," nor2_0: nor2 port map(a, b, yb);",end or2_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'nor2{sch}',"entity nor2 is port(a, b: in BIT; y: out BIT);", end nor2;,"",architecture nor2_BODY of nor2 is, component ground port(gnd: out BIT);, end component;," component nMOStran port(g: in BIT; s, d: inout BIT);", end component;," component PMOStran port(g: in BIT; s, d: inout BIT);", end component;, component power port(vdd: out BIT);, end component;,""," signal gnd, vdd, net_17: BIT;","",begin, gnd_0: ground port map(gnd);," nmos_0: nMOStran port map(b, gnd, y);"," nmos_1: nMOStran port map(a, gnd, y);"," pmos_0: PMOStran port map(b, y, net_17);"," pmos_1: PMOStran port map(a, net_17, vdd);", pwr_0: power port map(vdd);,end nor2_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'xnor2{sch}',"entity xnor2 is port(a, b: in BIT; y: out BIT);", end xnor2;,"",architecture xnor2_BODY of xnor2 is, component inv port(a: in BIT; y: out BIT);, end component;," component nand2 port(a, b: in BIT; y: out BIT);", end component;,""," signal net_4, net_5, net_2, net_0: BIT;","",begin," inv_0: inv port map(b, net_5);"," inv_1: inv port map(a, net_4);"," nand2_0: nand2 port map(a, b, net_0);"," nand2_1: nand2 port map(net_5, net_4, net_2);"," nand2_3: nand2 port map(net_0, net_2, y);",end xnor2_BODY;]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell d_latch;1{ic}
Cd_latch;1{ic}||artwork|1195020067727|1195020067838|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||0|0|6|10|||SCHEM_function(D5G1;)Sd_latch|trace()V[-3/-5,-3/5,3/5,3/-5,-3/-5]
Nschematic:Bus_Pin|pin@0||-5|1||||
Nschematic:Wire_Pin|pin@1||-3|1||||
Nschematic:Bus_Pin|pin@2||5|0||||
Nschematic:Wire_Pin|pin@3||3|0||||
Nschematic:Bus_Pin|pin@4||-5|-1||||
Nschematic:Wire_Pin|pin@5||-3|-1||||
Aschematic:wire|net@0|||0|pin@1||-3|1|pin@0||-5|1
Aschematic:wire|net@1|||1800|pin@3||3|0|pin@2||5|0
Aschematic:wire|net@2|||0|pin@5||-3|-1|pin@4||-5|-1
ED||D5G2;|pin@0||I
EQ||D5G2;|pin@2||O
Een||D5G2;|pin@4||I
X
# Cell d_latch;1{net.als}
Cd_latch;1{net.als}||artwork|1195251274084|1195251602733||FACET_message()S[#*************************************************,# ALS Netlist file,#,"# File Creation: Fri Nov 16, 2007 22:20:02",#-------------------------------------------------,"","model inv(a, y)",gnd_0: ground(gnd),"nmos_0: nMOStran(a, gnd, y)","pmos_0: PMOStran(a, y, vdd)",pwr_0: power(vdd),"","model d_latch(D, en, Q)",gnd_0: ground(gnd),"nmos_2: nMOStran(net_22, gnd, net_6)","nmos_3: nMOStran(net_6, gnd, Q)","nmos_5: nMOStran(net_68, net_22, Q)","nmos_6: nMOStran(en, D, net_22)","pmos_1: PMOStran(net_22, net_6, vdd)","pmos_2: PMOStran(net_6, Q, vdd)","pmos_5: PMOStran(en, Q, n0)","pmos_6: PMOStran(net_68, net_22, D)",pwr_0: power(vdd),"inv_0: inv(en, net_68)","",#********* End of netlist *******************,"",# Built-in model for power,gate power(p),set p=H@3,t: delta=0,"",# Built-in model for PMOStran,"function PMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8,"",# Built-in model for nMOStran,"function nMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8,"",# Built-in model for ground,gate ground(g),set g=L@3,t: delta=0]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell d_latch;1{sch}
Cd_latch;1{sch}||schematic|1195018919091|1195251633269|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-24|-23.5||||
Iinv;1{ic}|inv@0||-39.5|1|RRR||D5G4;
NTransistor|nmos@2||-29|-18|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S2
NTransistor|nmos@3||-22|-18|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S2
NTransistor|nmos@5||-28|-5|||XRR||ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S2
NTransistor|nmos@6||-34.5|-17|||XRR||ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S2
NWire_Pin|pin@0||-40.5|-15||||
NWire_Pin|pin@2||-24|-12||||
NWire_Pin|pin@3||-24|-15||||
NWire_Pin|pin@4||-27|-15||||
NWire_Pin|pin@5||-24|-18||||
NWire_Pin|pin@6||-24|-20||||
NWire_Pin|pin@7||-24|-10||||
NWire_Pin|pin@8||-20|-15.5||||
NWire_Pin|pin@9||-15|-15.5||||
NWire_Pin|pin@10||-31|-12||||
NWire_Pin|pin@11||-31|-18||||
NWire_Pin|pin@13||-31|-3||||
NWire_Pin|pin@14||-19|-3||||
NWire_Pin|pin@15||-19|-15.5||||
NWire_Pin|pin@17||-28|4||||
NWire_Pin|pin@20||-34.5|8||||
NWire_Pin|pin@21||-34.5|4||||
NWire_Pin|pin@22||-38|4||||
NWire_Pin|pin@23||-38|-20||||
NWire_Pin|pin@24||-34.5|-20||||
NWire_Pin|pin@34||-31|-15||||
NWire_Pin|pin@35||-34.5|-6||||
NTransistor|pmos@1||-29|-12|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S4
NTransistor|pmos@2||-22|-12|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S4
NTransistor|pmos@5||-28|-1|||X|2|ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S4
NTransistor|pmos@6||-34.5|-13|||X|2|ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S4
NPower|pwr@0||-24|-7.5||||
Awire|net@6|||900|pin@4||-27|-15|nmos@2|d|-27|-16
Awire|net@7|||900|pmos@2|s|-20|-14|pin@8||-20|-15.5
Awire|net@8|||0|pmos@2|g|-23|-12|pin@2||-24|-12
Awire|net@9|||900|pin@2||-24|-12|pin@3||-24|-15
Awire|net@10|||900|pmos@1|s|-27|-14|pin@4||-27|-15
Awire|net@11|||0|pin@3||-24|-15|pin@4||-27|-15
Awire|net@12|||900|pin@3||-24|-15|pin@5||-24|-18
Awire|net@13|||1800|pin@5||-24|-18|nmos@3|g|-23|-18
Awire|net@14|||1800|pin@6||-24|-20|nmos@3|s|-20|-20
Awire|net@15|||1800|nmos@2|s|-27|-20|pin@6||-24|-20
Awire|net@16|||2700|gnd@0||-24|-21.5|pin@6||-24|-20
Awire|net@17|||0|pmos@2|d|-20|-10|pin@7||-24|-10
Awire|net@18|||0|pin@7||-24|-10|pmos@1|d|-27|-10
Awire|net@19|||900|pwr@0||-24|-7.5|pin@7||-24|-10
Awire|net@20|||900|pin@8||-20|-15.5|nmos@3|d|-20|-16
Awire|net@21|||1800|pin@15||-19|-15.5|pin@9||-15|-15.5
Awire|net@22|||0|pmos@1|g|-30|-12|pin@10||-31|-12
Awire|net@24|||1800|pin@11||-31|-18|nmos@2|g|-30|-18
Awire|net@27|||2700|pin@10||-31|-12|pin@13||-31|-3
Awire|net@30|||1800|pin@8||-20|-15.5|pin@15||-19|-15.5
Awire|net@31|||900|pin@14||-19|-3|pin@15||-19|-15.5
Awire|net@41|||900|pin@20||-34.5|8|pin@21||-34.5|4
Awire|net@42|||900|pin@21||-34.5|4|inv@0|a|-34.5|3
Awire|net@43|||0|pin@17||-28|4|pin@21||-34.5|4
Awire|net@46|||0|pin@21||-34.5|4|pin@22||-38|4
Awire|net@47|||900|pin@22||-38|4|pin@23||-38|-20
Awire|net@48|||1800|pin@23||-38|-20|pin@24||-34.5|-20
Awire|net@52|||2700|nmos@5|d|-26|-3|pmos@5|s|-26|-3
Awire|net@56|||2700|pin@34||-31|-15|pin@10||-31|-12
Awire|net@57|||2700|nmos@6|d|-32.5|-15|pmos@6|s|-32.5|-15
Awire|net@58|||2700|nmos@6|s|-36.5|-15|pmos@6|d|-36.5|-15
Awire|net@68|||900|pin@35||-34.5|-6|pmos@6|g|-34.5|-12
Awire|net@69|||1800|pin@0||-40.5|-15|pmos@6|d|-36.5|-15
Awire|net@70|||2700|pin@11||-31|-18|pin@34||-31|-15
Awire|net@71|||1800|pmos@6|s|-32.5|-15|pin@34||-31|-15
Awire|net@72|||2700|pin@24||-34.5|-20|nmos@6|g|-34.5|-18
Awire|net@73|||2700|pmos@5|g|-28|0|pin@17||-28|4
Awire|net@74|||0|nmos@5|s|-30|-3|pin@13||-31|-3
Awire|net@75|||1800|nmos@5|d|-26|-3|pin@14||-19|-3
Awire|net@76|||900|inv@0|y|-34.5|-5|pin@35||-34.5|-6
Awire|net@77|||0|nmos@5|g|-28|-6|pin@35||-34.5|-6
Awire|net@78|||0|nmos@5|s|-30|-3|nmos@5|s|-30|-3
ED||D5G2;|pin@0||I
EQ||D5G2;|pin@9||O
Een||D5G2;|pin@20||I
X
# Cell d_latch;1{vhdl}
Cd_latch;1{vhdl}||artwork|1195251274024|1195251602733||FACET_message()S[-- VHDL automatically generated by Electric 8.05 for cell 'd_latch{sch}',"entity d_latch is port(D, en: in BIT; Q: out BIT);", end d_latch;,"",architecture d_latch_BODY of d_latch is, component ground port(gnd: out BIT);, end component;, component inv port(a: in BIT; y: out BIT);, end component;," component nMOStran port(g: in BIT; s, d: inout BIT);", end component;," component PMOStran port(g: in BIT; s, d: inout BIT);", end component;, component power port(vdd: out BIT);, end component;,""," signal gnd, vdd, net_6, net_22, net_68: BIT;","",begin, gnd_0: ground port map(gnd);," nmos_2: nMOStran port map(net_22, gnd, net_6);"," nmos_3: nMOStran port map(net_6, gnd, Q);"," nmos_5: nMOStran port map(net_68, net_22, Q);"," nmos_6: nMOStran port map(en, D, net_22);"," pmos_1: PMOStran port map(net_22, net_6, vdd);"," pmos_2: PMOStran port map(net_6, Q, vdd);"," pmos_5: PMOStran port map(en, Q, open);"," pmos_6: PMOStran port map(net_68, net_22, D);", pwr_0: power port map(vdd);," inv_0: inv port map(en, net_68);",end d_latch_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'inv{sch}',entity inv is port(a: in BIT; y: out BIT);, end inv;,"",architecture inv_BODY of inv is, component ground port(gnd: out BIT);, end component;," component nMOStran port(g: in BIT; s, d: inout BIT);", end component;," component PMOStran port(g: in BIT; s, d: inout BIT);", end component;, component power port(vdd: out BIT);, end component;,""," signal gnd, vdd: BIT;","",begin, gnd_0: ground port map(gnd);," nmos_0: nMOStran port map(a, gnd, y);"," pmos_0: PMOStran port map(a, y, vdd);", pwr_0: power port map(vdd);,end inv_BODY;]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell found;1{ic}
Cfound;1{ic}||artwork|1194573881412|1194574047006|E
Ngeneric:Facet-Center|art@0||0|0||||AV
Nschematic:Bbox|node@0||0|0.5|-5|-4|||SCHEM_function(D5G1;)Sfound
Nschematic:Wire_Pin|pin@0||0|-3.5||||
Nschematic:Wire_Pin|pin@1||0|4.5||||
Nschematic:Wire_Pin|pin@2||-3.5|0.5||||
Nschematic:Wire_Pin|pin@3||3.5|0.5||||
Aschematic:wire|net@0|||900|node@0|d|0|-2.5|pin@0||0|-3.5
Aschematic:wire|net@1|||2700|node@0|b|0|3.5|pin@1||0|4.5
Aschematic:wire|net@2|||0|node@0|c|-2.5|0.5|pin@2||-3.5|0.5
Aschematic:wire|net@3|||1800|node@0|a|2.5|0.5|pin@3||3.5|0.5
Ematch||D5G2;|pin@2||I
EnotFound||D5G2;|pin@0||O
EnotFoundPrev||D5G2;|pin@1||I
Euse||D5G2;|pin@3||O
X
# Cell found;1{sch}
Cfound;1{sch}||schematic|1194495840180|1194568620988|
Iand2;1{ic}|and2@5||-5.5|9|||D5G4;
Iand2;1{ic}|and2@6||-5.5|2|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
Iinv;1{ic}|inv@5||-15|0|||D5G4;
NWire_Pin|pin@37||3|7||||
NWire_Pin|pin@38||3|14||||
NWire_Pin|pin@39||-19|5||||
NWire_Pin|pin@40||-19|12||||
NWire_Pin|pin@41||-21|12||||
NWire_Pin|pin@42||-21|16||||
NWire_Pin|pin@43||-9|9||||
NWire_Pin|pin@44||-9|16||||
Awire|net@63|||1800|inv@5|y|-9|5|and2@6|b|-7.5|5
Awire|net@64|||1800|and2@6|y|1.5|7|pin@37||3|7
Awire|net@65|||1800|and2@5|y|1.5|14|pin@38||3|14
Awire|net@66|||0|inv@5|a|-17|5|pin@39||-19|5
Awire|net@67|||2700|pin@39||-19|5|pin@40||-19|12
Awire|net@68|||1800|pin@40||-19|12|and2@5|b|-7.5|12
Awire|net@69|||0|pin@40||-19|12|pin@41||-21|12
Awire|net@70|||0|pin@44||-9|16|pin@42||-21|16
Awire|net@71|||0|and2@6|a|-7.5|9|pin@43||-9|9
Awire|net@72|||0|and2@5|a|-7.5|16|pin@44||-9|16
Awire|net@73|||2700|pin@43||-9|9|pin@44||-9|16
Ematch||D5G2;|pin@41||I
EnotFound||D5G2;|pin@37||O
EnotFoundPrev||D5G2;|pin@42||I
Euse||D5G2;|pin@38||O
X
# Cell inv;1{ic}
Cinv;1{ic}||artwork|977188259000|1194494622626|E
NOpened-Polygon|art@0||5.5|5|1||||trace()V[0.5/0,-0.5/0]
NOpened-Polygon|art@1||-1|5|2||||trace()V[-1/0,1/0]
NTriangle|art@2||2|5|4|4|RRR|
NCircle|art@3||4.5|5|1|1||
Ngeneric:Invisible-Pin|pin@0||6|5||||
Ngeneric:Invisible-Pin|pin@1||-2|5||||
Ngeneric:Invisible-Pin|pin@2||1.5|5|||||ART_message(D5G1;)S[inv]
Ea||D5G1;|pin@1||I
Ey||D5G1;|pin@0||O
X
# Cell inv;1{lay}
Cinv;1{lay}||mocmos|977525865000|1194494622626||DRC_last_good_drc()I1189301979|NET_ncc_last_result1()S[TIME 1189302046,MATCH lab1_BC:inv{sch},EXPORT y:y,EXPORT a:a]|prototype_center()I[23400,-24000]
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-N-Active-Con|contact@0||10|9||2||
NMetal-1-P-Active-Con|contact@1||10|68||8||
NMetal-1-P-Active-Con|contact@2||2|68||8||
NMetal-1-N-Active-Con|contact@3||2|9||2||
NMetal-1-Metal-2-Con|contact@4||2|0||||
NMetal-1-Metal-2-Con|contact@5||2|80||||
NMetal-1-Polysilicon-1-Con|contact@6||3|39||||
NN-Transistor|nmos@0||6|9|3||R|
NMetal-2-Pin|pin@0||0|0||||
NMetal-2-Pin|pin@1||12|0||||
NMetal-2-Pin|pin@2||2|0||||
NMetal-2-Pin|pin@3||0|80||||
NMetal-2-Pin|pin@4||12|80||||
NMetal-2-Pin|pin@5||2|80||||
NPolysilicon-1-Pin|pin@6||6|39||||
NMetal-1-Pin|pin@7||3|39||||
NMetal-1-Pin|pin@8||10|46||||
NP-Well-Node|plnode@0||6|6|24|24||A
NN-Select-Node|plnode@1||6|9|16|10||A
NN-Well-Node|plnode@2||6|71|24|30||A
NP-Select-Node|plnode@3||6|68|16|16||A
NP-Transistor|pmos@0||6|68|9||R|
NMetal-1-N-Well-Con|substr@0||10|80|||RR|
NMetal-1-P-Well-Con|well@0||10|0||||
AP-Active|net@0|||S1800|pmos@0|p-trans-diff-bottom|10|71.5|contact@1||10.5|71.5
AP-Active|net@1|||S1800|pmos@0|p-trans-diff-top|2|64|contact@2||2.5|64
AN-Active|net@2|||S1800|nmos@0|n-trans-diff-bottom|10|9.5|contact@0||10|9.5
AN-Active|net@3|||S1800|nmos@0|n-trans-diff-top|2|9.5|contact@3||2.5|9.5
AMetal-2|net@4||1|S0|pin@2||2|0|pin@0||0|0
AMetal-2|net@5||1|S0|pin@1||12|0|pin@2||2|0
AMetal-2|net@6|||S2700|pin@2||2|0|contact@4||2|0.5
AMetal-1|net@7||1|S900|contact@3||2|10|contact@4||2|0
AMetal-2|net@8||1|S0|pin@5||2|80|pin@3||0|80
AMetal-2|net@9|||S900|pin@5||2|80|contact@5||2|79.5
AMetal-2|net@10||1|S0|pin@4||12|80|pin@5||2|80
AMetal-1|net@11||1|S900|contact@5||2|80|contact@2||2|71
APolysilicon-1|net@12|||S2700|pin@6||6|39|pmos@0|p-trans-poly-left|6|60
APolysilicon-1|net@13|||S2700|nmos@0|n-trans-poly-right|6|14|pin@6||6|39
APolysilicon-1|net@14|||S0|pin@6||6|39|contact@6||3.5|39
AMetal-1|net@15||1|S2700|pin@7||3|39|contact@6||3|39
AMetal-1|net@16||1|S900|contact@1||10|64|pin@8||10|46
AMetal-1|net@17||1|S900|pin@8||10|46|contact@0||10|10
AMetal-1|net@18||1|S1800|contact@5||2|80|substr@0||10|80
AMetal-1|net@19||1|S0|well@0||9.5|0|contact@4||2|0
Ea||D5G2;|pin@7||I
Egnd||D5G2;|pin@0||G
Evdd||D5G2;|pin@3||P
Ey||D5G2;|pin@8||O
X
# Cell inv;1{sch}
Cinv;1{sch}||schematic|977187370000|1194494622626||NET_ncc_last_result1()S[TIME 1189302046,MATCH lab1_BC:inv{lay},EXPORT y:y,EXPORT a:a]
NOff-Page|conn@0||-8|3||||
NOff-Page|conn@1||5|3||||
NGround|gnd@0||0|-5|-1|||
NTransistor|nmos@0||-2|0|||R||ATTR_length(D5G0.5;X-0.5;)I2|ATTR_width(D5G1;X0.5;)I6
NWire_Pin|pin@0||0|3||||
NWire_Pin|pin@1||-4|0||||
NWire_Pin|pin@2||-4|6||||
NWire_Pin|pin@3||-4|3||||
NTransistor|pmos@0||-2|6|||R|2|ATTR_length(D5G0.5;X-0.5;)I2|ATTR_width(D5G1;X0.5;)I12
NPower|pwr@0||0|10|-1|-1||
Awire|net@0|||0|pin@3||-4|3|conn@0|y|-6|3
Awire|net@1|||1800|pin@0||0|3|conn@1|a|3|3
Awire|net@2|||0|pmos@0|g|-3|6|pin@2||-4|6
Awire|net@3|||900|pin@3||-4|3|pin@1||-4|0
Awire|net@4|||1800|pin@1||-4|0|nmos@0|g|-3|0
Awire|net@5|||900|pin@2||-4|6|pin@3||-4|3
Awire|net@6|||900|pin@0||0|3|nmos@0|d|0|2
Awire|net@7|||900|pmos@0|s|0|4|pin@0||0|3
Awire|net@8|||900|nmos@0|s|0|-2|gnd@0||0|-3
Awire|net@9|||900|pwr@0||0|10|pmos@0|d|0|8
Ea||D5G2;|conn@0|y|I
Ey||D5G2;|conn@1|y|O
X
# Cell latch;1{ic}
Clatch;1{ic}||artwork|1194573566645|1194573840961|E
Ngeneric:Facet-Center|art@0||0|0||||AV
Nschematic:Bbox|node@0||0.5|4.5|-5|-4|||SCHEM_function(D5G1;)Slatch
Nschematic:Wire_Pin|pin@0||-3|4.5||||
Nschematic:Wire_Pin|pin@2||3|6.5||||
Nschematic:Wire_Pin|pin@3||4|6.5||||
Nschematic:Wire_Pin|pin@4||3|2.5||||
Nschematic:Wire_Pin|pin@5||4|2.5||||
Nschematic:Wire_Pin|pin@6||0.5|0.5||||
Aschematic:wire|net@0|||0|node@0|c|-2|4.5|pin@0||-3|4.5
Aschematic:wire|net@2|||2700|node@0|a|3|4.5|pin@2||3|6.5
Aschematic:wire|net@3|||1800|pin@2||3|6.5|pin@3||4|6.5
Aschematic:wire|net@4|||900|node@0|a|3|4.5|pin@4||3|2.5
Aschematic:wire|net@5|||1800|pin@4||3|2.5|pin@5||4|2.5
Aschematic:wire|net@6|||900|node@0|d|0.5|1.5|pin@6||0.5|0.5
ED||D5G2;|pin@0||I
EQ||D5G2;|pin@3||O
EQbar||D5G2;|pin@5||O
Een||D5G2;|pin@6||I
X
# Cell latch;1{lay}
Clatch;1{lay}||mocmos|1195250543753|1195253546700||DRC_last_good_drc_bit()I19|DRC_last_good_drc_date()G1195253551327
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Metal-2-Con|contact@0||-36|1||||
NMetal-1-Metal-2-Con|contact@1||-7|1||||
NMetal-1-Metal-2-Con|contact@2||-50|12||||
NMetal-1-Metal-2-Con|contact@3||-21|12||||
NMetal-1-Metal-2-Con|contact@4||-43|8||||
NMetal-1-Metal-2-Con|contact@5||8|12||||
NMetal-1-Metal-2-Con|contact@6||1|-9||||
NMetal-1-Metal-2-Con|contact@7||51|1||||
NMetal-1-Metal-2-Con|contact@8||37|12||||
Inand2;1{lay}|nand2@0||-24|-41|||D5G4;
Inand2;1{lay}|nand2@1||5|-41|||D5G4;
Inand2;1{lay}|nand2@2||34|-41|||D5G4;
Inand2;1{lay}|nand2@3||-53|-41|||D5G4;
NMetal-2-Pin|pin@0||-26|1||||
NMetal-2-Pin|pin@2||-31.5|8||||
NMetal-2-Pin|pin@3||-31.5|12||||
NMetal-2-Pin|pin@4||-4|12||||
NMetal-1-Pin|pin@5||1|8.5||||
NMetal-1-Pin|pin@6||-14|8.5||||
NMetal-2-Pin|pin@9||51|-9||||
NMetal-1-Pin|pin@10||15|12||||
NMetal-1-Pin|pin@11||44|1||||
NMetal-2-Pin|pin@12||58|12||||
NMetal-2-Pin|pin@14||-63|12||||
NMetal-2-Pin|pin@15||-63|1||||
NMetal-1-Pin|pin@16||44|-13.5||||
NMetal-1-Pin|pin@17||58.5|-13.5||||
AMetal-2|net@8||1|S1800|nand2@3|gnd|-53|-41|nand2@0|gnd|-24|-41
AMetal-2|net@9||1|S1800|nand2@0|gnd|-24|-41|nand2@1|gnd|5|-41
AMetal-2|net@10||1|S1800|nand2@1|gnd|5|-41|nand2@2|gnd|34|-41
AMetal-2|net@11||1|S0|nand2@2|vdd|34|39|nand2@1|vdd|5|39
AMetal-2|net@12||1|S0|nand2@1|vdd|5|39|nand2@0|vdd|-24|39
AMetal-2|net@13||1|S0|nand2@0|vdd|-24|39|nand2@3|vdd|-53|39
AMetal-2|net@14||1|S0|pin@0||-26|1|contact@0||-36|1
AMetal-1|net@15||1|S0|nand2@3|b|-36|1|contact@0||-36|1
AMetal-2|net@16||1|S1800|pin@0||-26|1|contact@1||-7|1
AMetal-1|net@17||1|S0|nand2@0|b|-7|1|contact@1||-7|1
AMetal-1|net@19||1|S900|nand2@3|a|-50|12|contact@2||-50|12
AMetal-1|net@21||1|S900|nand2@0|a|-21|12|contact@3||-21|12
AMetal-2|net@22||1|S0|pin@2||-31.5|8|contact@4||-43|8
AMetal-1|net@23||1|S900|nand2@3|y|-43|8|contact@4||-43|8
AMetal-2|net@24||1|S2700|pin@2||-31.5|8|pin@3||-31.5|12
AMetal-2|net@25||1|S1800|pin@3||-31.5|12|contact@3||-21|12
AMetal-2|net@26||1|S0|pin@4||-4|12|contact@3||-21|12
AMetal-2|net@27||1|S1800|pin@4||-4|12|contact@5||8|12
AMetal-1|net@28||1|S900|nand2@1|a|8|12|contact@5||8|12
AMetal-1|net@29||1|S0|pin@5||1|8.5|pin@6||-14|8.5
AMetal-1|net@30||1|S900|pin@6||-14|8.5|nand2@0|y|-14|8
AMetal-1|net@31||1|S900|pin@5||1|8.5|contact@6||1|-9
AMetal-2|net@32||1|S0|pin@9||51|-9|contact@6||1|-9
AMetal-2|net@33||1|S2700|pin@9||51|-9|contact@7||51|1
AMetal-1|net@34||1|S0|nand2@2|b|51|1|contact@7||51|1
AMetal-1|net@35||1|S2700|nand2@1|y|15|8|pin@10||15|12
AMetal-1|net@36||1|S1800|pin@10||15|12|nand2@2|a|37|12
AMetal-1|net@37||1|S0|pin@11||44|1|nand2@1|b|22|1
AMetal-1|net@38||1|S2700|pin@11||44|1|nand2@2|y|44|8
AMetal-2|net@39||1|S0|pin@12||58|12|contact@8||37|12
AMetal-1|net@40||1|S900|nand2@2|a|37|12|contact@8||37|12
AMetal-2|net@42||1|S1800|pin@14||-63|12|contact@2||-50|12
AMetal-2|net@43||1|S0|contact@0||-36|1|pin@15||-63|1
AMetal-1|net@44||1|S900|pin@11||44|1|pin@16||44|-13.5
AMetal-1|net@45||1|S1800|pin@16||44|-13.5|pin@17||58.5|-13.5
ED||D5G2;|pin@14||I
EQ||D5G2;|pin@12||O
EQbar||D5G2;|pin@17||O
Een||D5G2;|pin@15||I
Egnd||D5G2;|nand2@3|gnd|G
Evdd||D5G2;|nand2@3|vdd|P
X
# Cell latch;1{net.als}
Clatch;1{net.als}||artwork|1195253363640|1195266706815||FACET_message()S[#*************************************************,# ALS Netlist file,#,"# File Creation: Sat Nov 17, 2007 02:31:46",#-------------------------------------------------,"","model nand2(a, b, y, vdd, gnd)","nmos_0: nMOStran(n0, net_37, y)","nmos_1: nMOStran(n1, gnd, net_37)",pin_0: ground(gnd),pin_7: power(vdd),"pmos_0: PMOStran(b, y, vdd)","pmos_1: PMOStran(a, vdd, y)","","model latch(D, en, Q, Qbar, vdd, gnd)","nand2_0: nand2(net_21, en, net_29, vdd, gnd)","nand2_1: nand2(net_21, Qbar, Q, vdd, gnd)","nand2_2: nand2(Q, net_29, Qbar, vdd, gnd)","nand2_3: nand2(D, en, net_21, vdd, gnd)","",#********* End of netlist *******************,"",# Built-in model for PMOStran,"function PMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8,"",# Built-in model for power,gate power(p),set p=H@3,t: delta=0,"",# Built-in model for ground,gate ground(g),set g=L@3,t: delta=0,"",# Built-in model for nMOStran,"function nMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell latch;1{sch}
Clatch;1{sch}||schematic|1194569272773|1194569681639|
Ngeneric:Facet-Center|art@0||0|0||||AV
Inand2;1{ic}|nand2@0||-29.5|12|||D5G4;
Inand2;1{ic}|nand2@1||-15|11|||D5G4;
Inand2;1{ic}|nand2@3||-29.5|1|||D5G4;
Inand2;1{ic}|nand2@4||-15|2|||D5G4;
NWire_Pin|pin@0||-10|7||||
NWire_Pin|pin@1||-19|7||||
NWire_Pin|pin@2||-10|6||||
NWire_Pin|pin@3||-20|6||||
NWire_Pin|pin@4||-20|10||||
NWire_Pin|pin@5||-8|11||||
NWire_Pin|pin@6||-8|2||||
NWire_Pin|pin@7||-33.5|8||||
NWire_Pin|pin@8||-24|8||||
NWire_Pin|pin@9||-24|12||||
NWire_Pin|pin@10||-36|0||||
NWire_Pin|pin@11||-36|11||||
NWire_Pin|pin@12||-39|13||||
NWire_Pin|pin@13||-39|0||||
Awire|net@0|||900|nand2@1|y|-10|11|pin@0||-10|7
Awire|net@1|||0|pin@0||-10|7|pin@1||-19|7
Awire|net@2|||900|pin@1||-19|7|nand2@4|a|-19|3
Awire|net@3|||2700|nand2@4|y|-10|2|pin@2||-10|6
Awire|net@4|||0|pin@2||-10|6|pin@3||-20|6
Awire|net@5|||2700|pin@3||-20|6|pin@4||-20|10
Awire|net@6|||1800|pin@4||-20|10|nand2@1|b|-19|10
Awire|net@7|||1800|nand2@1|y|-10|11|pin@5||-8|11
Awire|net@8|||1800|nand2@4|y|-10|2|pin@6||-8|2
Awire|net@9|||1800|pin@9||-24|12|nand2@1|a|-19|12
Awire|net@10|||1800|nand2@3|y|-24.5|1|nand2@4|b|-19|1
Awire|net@11|||2700|nand2@3|a|-33.5|2|pin@7||-33.5|8
Awire|net@12|||1800|pin@7||-33.5|8|pin@8||-24|8
Awire|net@13|||1800|nand2@0|y|-24.5|12|pin@9||-24|12
Awire|net@14|||2700|pin@8||-24|8|pin@9||-24|12
Awire|net@15|||0|nand2@3|b|-33.5|0|pin@10||-36|0
Awire|net@16|||2700|pin@10||-36|0|pin@11||-36|11
Awire|net@17|||1800|pin@11||-36|11|nand2@0|b|-33.5|11
Awire|net@18|||0|nand2@0|a|-33.5|13|pin@12||-39|13
Awire|net@19|||0|pin@10||-36|0|pin@13||-39|0
ED||D5G2;|pin@12||I
EQ||D5G2;|pin@5||O
EQ_|Qbar|D5G2;|pin@6||O
Een||D5G2;|pin@13||I
X
# Cell latch;1{vhdl}
Clatch;1{vhdl}||artwork|1195253363634|1195253557491||FACET_message()S[-- VHDL automatically generated by Electric 8.05 for cell 'latch{lay}',"entity latch is port(D, en: in BIT; Q, Qbar: out BIT; vdd: out BIT; gnd: out BIT);", end latch;,"",architecture latch_BODY of latch is," component nand2 port(a, b: in BIT; y: out BIT; vdd: out BIT; gnd: out BIT);", end component;,""," signal net_21, net_29: BIT;","",begin," nand2_0: nand2 port map(net_21, en, net_29, vdd, gnd);"," nand2_1: nand2 port map(net_21, Qbar, Q, vdd, gnd);"," nand2_2: nand2 port map(Q, net_29, Qbar, vdd, gnd);"," nand2_3: nand2 port map(D, en, net_21, vdd, gnd);",end latch_BODY;,"","",-- VHDL automatically generated by Electric 8.05 for cell 'nand2{lay}',"entity nand2 is port(a, b: in BIT; y: out BIT; vdd: out BIT; gnd: out BIT);", end nand2;,"",architecture nand2_BODY of nand2 is," component nMOStran port(n_trans_poly_left, n_trans_diff_top, n_trans_diff_bottom: inout BIT);", end component;, component ground port(metal_2: inout BIT);, end component;, component power port(metal_2: inout BIT);, end component;," component PMOStran port(p_trans_poly_left, p_trans_diff_top, p_trans_diff_bottom: inout BIT);", end component;,"", signal net_37: BIT;,"",begin," nmos_0: nMOStran port map(open, net_37, y);"," nmos_1: nMOStran port map(open, gnd, net_37);", pin_0: ground port map(gnd);, pin_7: power port map(vdd);," pmos_0: PMOStran port map(b, y, vdd);"," pmos_1: PMOStran port map(a, vdd, y);",end nand2_BODY;]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell match;1{ic}
Cmatch;1{ic}||artwork|1194574006649|1194574202041|E
Ngeneric:Facet-Center|art@0||0|0||||AV
Nschematic:Bbox|node@0||0|0|-5|-4|||SCHEM_function(D5G1;)Smatch
Nschematic:Wire_Pin|pin@0||-4|0||||
Nschematic:Wire_Pin|pin@1||4|0||||
Nschematic:Wire_Pin|pin@2||-2|3||||
Nschematic:Wire_Pin|pin@3||-2|4||||
Nschematic:Wire_Pin|pin@4||0|4||||
Nschematic:Wire_Pin|pin@5||2|3||||
Nschematic:Wire_Pin|pin@6||2|4||||
Aschematic:wire|net@0|||0|node@0|c|-2.5|0|pin@0||-4|0
Aschematic:wire|net@1|||1800|node@0|a|2.5|0|pin@1||4|0
Aschematic:wire|net@2|||0|node@0|b|0|3|pin@2||-2|3
Aschematic:wire|net@3|||2700|pin@2||-2|3|pin@3||-2|4
Aschematic:wire|net@4|||2700|node@0|b|0|3|pin@4||0|4
Aschematic:wire|net@5|||1800|node@0|b|0|3|pin@5||2|3
Aschematic:wire|net@6|||2700|pin@5||2|3|pin@6||2|4
Einput||D5G2;|pin@4||I
Ekey||D5G2;|pin@3||I
Emask||D5G2;|pin@6||I
Ematch||D5G2;|pin@1||O
Eocc|matchPrev|D5G2;|pin@0||I
X
# Cell match;1{sch}
Cmatch;1{sch}||schematic|1194495598964|1194670100510|
Iand2;1{ic}|and2@0||-13|8.5|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
Ior2;1{ic}|or2@0||-22|6.5|||D5G4;
NWire_Pin|pin@0||-25|13.5||||
NWire_Pin|pin@1||-16|15.5||||
NWire_Pin|pin@4||-5|13.5||||
NWire_Pin|pin@12||-42|10.5||||
NWire_Pin|pin@13||-43.5|8.5||||
Ixnor2;1{ic}|xnor2@0||-32.5|9.5|||D5G4;
Awire|net@1|||0|and2@0|b|-15|11.5|or2@0|y|-16|11.5
Awire|net@2|||0|or2@0|a|-24|13.5|pin@0||-25|13.5
Awire|net@3|||0|and2@0|a|-15|15.5|pin@1||-16|15.5
Awire|net@6|||1800|and2@0|y|-6|13.5|pin@4||-5|13.5
Awire|net@20|||0|xnor2@0|a|-37.5|10.5|pin@12||-42|10.5
Awire|net@21|||0|xnor2@0|b|-37.5|8.5|pin@13||-43.5|8.5
Awire|net@23|||0|or2@0|b|-24|9.5|xnor2@0|y|-27.5|9.5
Einput||D5G2;|pin@12||I
Ekey||D5G2;|pin@13||I
Emask||D5G2;|pin@0||I
Euse|match|D5G2;|pin@4||O
Eocc|matchPrev|D5G2;|pin@1||I
X
# Cell nand2;1{ic}
Cnand2;1{ic}||artwork|977187855000|1194494622626|E|prototype_center()I[12000,20000]
Ngeneric:Facet-Center|art@0||0|0||||AV
NCircle|art@1||3.5|0|1|1||
NOpened-Polygon|art@2||-1|0|2|6|||trace()V[1/-3,-1/-3,-1/3,1/3]
NCircle|art@3||0|0|6|6|RRR||ART_degrees()F[0.0,3.1415927]
NOpened-Polygon|art@4||4.5|0|1||||trace()V[0.5/0,-0.5/0]
NOpened-Polygon|art@5||-3|-1|2||||trace()V[-1/0,1/0]
NOpened-Polygon|art@6||-3|1|2||||trace()V[-1/0,1/0]
Ngeneric:Invisible-Pin|pin@0||0|0|||||ART_message(D5G1;)S[nand2]
Ngeneric:Invisible-Pin|pin@1||5|0||||
Ngeneric:Invisible-Pin|pin@2||-4|-1||||
Ngeneric:Invisible-Pin|pin@3||-4|1||||
Ea||D5G1;|pin@3||I
Eb||D5G1;|pin@2||I
Ey||D5G1;|pin@1||O
X
# Cell nand2;1{lay}
Cnand2;1{lay}||mocmos|1189283443000|1194494622626||DRC_last_good_drc()I1191785648|DRC_last_good_drc_bit()I19|DRC_last_good_drc_date()G1195252703395|NET_ncc_last_result1()S[TIME 1191785677,MATCH lab3_BC:nand2{sch},EXPORT b:b,EXPORT a:a,EXPORT y:y]|prototype_center()I[-84600,7800]
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Metal-2-Con|contact@0||2|0||||
NMetal-1-Metal-2-Con|contact@1||18|80||||
NMetal-1-Metal-2-Con|contact@2||2|80||||
NMetal-1-Polysilicon-1-Con|contact@3||3|49||||
NMetal-1-Polysilicon-1-Con|contact@4||17|38||||
NMetal-1-P-Active-Con|contact@5||18|68||8||
NMetal-1-P-Active-Con|contact@6||10|68||8||
NMetal-1-P-Active-Con|contact@7||2|68||8||
NMetal-1-N-Active-Con|contact@8||2|12||8||
NMetal-1-N-Active-Con|contact@9||15|12||8||
NN-Transistor|nmos@0||11|12|9||R|
NN-Transistor|nmos@1||6|12|9||R|
NMetal-2-Pin|pin@0||0|0||||
NMetal-1-Pin|pin@1||10|49||||
NMetal-1-Pin|pin@2||10|49||||
NMetal-1-Pin|pin@3||17|42||||
NMetal-1-Pin|pin@4||3|53||||
NMetal-2-Pin|pin@5||2|0||||
NMetal-2-Pin|pin@6||20|80||||
NMetal-2-Pin|pin@7||0|80||||
NMetal-2-Pin|pin@8||2|80||||
NMetal-2-Pin|pin@9||20|0||||
NMetal-2-Pin|pin@10||0|0||||
NMetal-2-Pin|pin@11||18|80||||
NMetal-2-Pin|pin@12||2|80||||
NPolysilicon-1-Pin|pin@13||6|49||||
NPolysilicon-1-Pin|pin@14||14|38||||
NMetal-1-Pin|pin@15||15|16||||
NMetal-1-Pin|pin@16||10|16||||
NPolysilicon-1-Pin|pin@17||11|36.5||||
NPolysilicon-1-Pin|pin@18||14|36.5||||
NP-Well-Node|plnode@0||8.5|9.5|29|29||A
NN-Well-Node|plnode@1||10|71.5|32|31||A
NP-Select-Node|plnode@2||10|68|24|16||A
NN-Select-Node|plnode@3||8.5|12|21|16||A
NP-Transistor|pmos@0||14|68|9||R|
NP-Transistor|pmos@1||6|68|9||R|
NMetal-1-N-Well-Con|substr@0||13|80||||
NMetal-1-P-Well-Con|well@0||12|0||||
AMetal-2|net@0||1|S2700|pin@10||0|0|pin@0||0|0
AMetal-1|net@1||1|S2700|pin@1||10|49|pin@2||10|49
AMetal-1|net@2||1|S2700|pin@16||10|16|pin@1||10|49
AMetal-1|net@3||1|S2700|pin@1||10|49|contact@6||10|64
AMetal-1|net@4||1|S900|pin@3||17|42|contact@4||17|38
AMetal-1|net@5||1|S900|pin@4||3|53|contact@3||3|49
AMetal-1|net@6||1|S1800|contact@0||2|0|well@0||12|0
AMetal-2|net@7||1|S1800|pin@5||2|0|pin@9||20|0
AMetal-1|net@8||1|S900|contact@8||2|8|contact@0||2|0
AMetal-2|net@9||1|S2700|pin@5||2|0|contact@0||2|0
AMetal-2|net@10||1|S0|pin@5||2|0|pin@10||0|0
AMetal-2|net@11||1|S1800|pin@11||18|80|pin@6||20|80
AMetal-2|net@12||1|S0|pin@12||2|80|pin@7||0|80
AMetal-1|net@13||1|S0|contact@1||18|80|substr@0||13|80
AMetal-1|net@14||1|S2700|contact@5||18|72|contact@1||18|80
AMetal-2|net@15||1|S2700|pin@11||18|80|contact@1||18|80
AMetal-1|net@16||1|S0|substr@0||13|80|contact@2||2|80
AMetal-1|net@17||1|S2700|contact@7||2|72|contact@2||2|80
AMetal-2|net@18||1|S2700|pin@12||2|80|pin@8||2|80
AMetal-2|net@19||1|S2700|pin@8||2|80|contact@2||2|80
AMetal-2|net@20||1|S0|pin@11||18|80|pin@12||2|80
APolysilicon-1|net@21|||S0|pin@13||6|49|contact@3||2.5|49
APolysilicon-1|net@22|||S2700|nmos@1|n-trans-poly-right|6|20|pin@13||6|49
APolysilicon-1|net@23|||S2700|pin@13||6|49|pmos@1|p-trans-poly-left|6|60
APolysilicon-1|net@24|||S1800|pin@14||14|38|contact@4||16.5|38
APolysilicon-1|net@25|||S2700|pin@18||14|36.5|pin@14||14|38
APolysilicon-1|net@26|||S2700|pin@14||14|38|pmos@0|p-trans-poly-left|14|60
AP-Active|net@27|||S1800|pmos@0|p-trans-diff-top|10|68|contact@6||10.5|68
AP-Active|net@28|||S1800|contact@5||17.5|68|pmos@0|p-trans-diff-bottom|18|68
AMetal-1|net@29||1|S2700|contact@9||15|12|pin@15||15|16
AMetal-1|net@30||1|S0|pin@15||15|16|pin@16||10|16
APolysilicon-1|net@31|||S2700|nmos@0|n-trans-poly-right|11|20|pin@17||11|36.5
APolysilicon-1|net@32|||S1800|pin@17||11|36.5|pin@18||14|36.5
AP-Active|net@33|||S1800|contact@6||9.5|68|pmos@1|p-trans-diff-bottom|10|68
AP-Active|net@34|||S1800|pmos@1|p-trans-diff-top|2|68|contact@7||2.5|68
AN-Active|net@35|||S0|nmos@0|n-trans-diff-bottom|15|12|contact@9||14.5|12
AN-Active|net@36|||S1800|nmos@1|n-trans-diff-top|2|11|contact@8||2.5|11
AN-Active|net@37|||S0|nmos@1|n-trans-diff-bottom|10|12|nmos@0|n-trans-diff-top|7|12
Ea||D5G2;|pin@4||I
Eb||D5G2;|pin@3||I
Egnd||D5G2;|pin@0||G
Evdd||D5G2;|pin@7||P
Ey||D5G2;|pin@2||O
X
# Cell nand2;1{net.als}
Cnand2;1{net.als}||artwork|1195266827401|1195266827402||FACET_message()S[#*************************************************,# ALS Netlist file,#,"# File Creation: Sat Nov 17, 2007 02:33:47",#-------------------------------------------------,"","model nand2(a, b, y, vdd, gnd)","nmos_0: nMOStran(n0, net_37, y)","nmos_1: nMOStran(n1, gnd, net_37)",pin_0: ground(gnd),pin_7: power(vdd),"pmos_0: PMOStran(b, y, vdd)","pmos_1: PMOStran(a, vdd, y)","",#********* End of netlist *******************,"",# Built-in model for PMOStran,"function PMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8,"",# Built-in model for power,gate power(p),set p=H@3,t: delta=0,"",# Built-in model for ground,gate ground(g),set g=L@3,t: delta=0,"",# Built-in model for nMOStran,"function nMOStran(g, a1, a2)","i: g, a1, a2","o: a1, a2",t: delta=1e-8]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell nand2;1{sch}
Cnand2;1{sch}||schematic|1189131232000|1194494622626||NET_ncc_last_result1()S[TIME 1191785677,MATCH lab3_BC:nand2{lay},EXPORT b:b,EXPORT a:a,EXPORT y:y]|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-3|-12||||
NTransistor|nmos@0||-5|-6|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I12
NTransistor|nmos@1||-5|0|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I12
NWire_Pin|pin@0||-1|3||||
NWire_Pin|pin@1||-18|-6||||
NWire_Pin|pin@2||-18|0||||
NWire_Pin|pin@3||-15|-6||||
NWire_Pin|pin@4||-15|7||||
NWire_Pin|pin@5||-8|0||||
NWire_Pin|pin@6||-8|7||||
NWire_Pin|pin@7||-11|3||||
NWire_Pin|pin@8||-3|3||||
NWire_Pin|pin@9||-3|12||||
NWire_Pin|pin@10||-11|12||||
NWire_Pin|pin@11||-7|12||||
NTransistor|pmos@0||-13|7|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I12
NTransistor|pmos@1||-5|7|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I12
NPower|pwr@0||-7|15||||
Awire|net@0|||0|pin@0||-1|3|pin@8||-3|3
Awire|net@1|||1800|pin@1||-18|-6|pin@3||-15|-6
Awire|net@2|||1800|pin@2||-18|0|pin@5||-8|0
Awire|net@3|||0|nmos@0|g|-6|-6|pin@3||-15|-6
Awire|net@4|||2700|pin@3||-15|-6|pin@4||-15|7
Awire|net@5|||1800|pin@4||-15|7|pmos@0|g|-14|7
Awire|net@6|||0|nmos@1|g|-6|0|pin@5||-8|0
Awire|net@7|||2700|pin@5||-8|0|pin@6||-8|7
Awire|net@8|||1800|pin@6||-8|7|pmos@1|g|-6|7
Awire|net@9|||900|pmos@0|s|-11|5|pin@7||-11|3
Awire|net@10|||1800|pin@7||-11|3|pin@8||-3|3
Awire|net@11|||2700|nmos@1|d|-3|2|pin@8||-3|3
Awire|net@12|||2700|pin@8||-3|3|pmos@1|s|-3|5
Awire|net@13|||2700|pmos@1|d|-3|9|pin@9||-3|12
Awire|net@14|||0|pin@9||-3|12|pin@11||-7|12
Awire|net@15|||2700|pmos@0|d|-11|9|pin@10||-11|12
Awire|net@16|||1800|pin@10||-11|12|pin@11||-7|12
Awire|net@17|||2700|pin@11||-7|12|pwr@0||-7|15
Awire|net@18|||2700|gnd@0||-3|-10|nmos@0|s|-3|-8
Awire|net@19|||2700|nmos@0|d|-3|-4|nmos@1|s|-3|-2
Ea||D5G2;|pin@1||I
Eb||D5G2;|pin@2||I
Ey||D5G2;|pin@0||O
X
# Cell nand2;1{vhdl}
Cnand2;1{vhdl}||artwork|1195266827396|1195266827402||FACET_message()S[-- VHDL automatically generated by Electric 8.05 for cell 'nand2{lay}',"entity nand2 is port(a, b: in BIT; y: out BIT; vdd: out BIT; gnd: out BIT);", end nand2;,"",architecture nand2_BODY of nand2 is," component nMOStran port(n_trans_poly_left, n_trans_diff_top, n_trans_diff_bottom: inout BIT);", end component;, component ground port(metal_2: inout BIT);, end component;, component power port(metal_2: inout BIT);, end component;," component PMOStran port(p_trans_poly_left, p_trans_diff_top, p_trans_diff_bottom: inout BIT);", end component;,"", signal net_37: BIT;,"",begin," nmos_0: nMOStran port map(open, net_37, y);"," nmos_1: nMOStran port map(open, gnd, net_37);", pin_0: ground port map(gnd);, pin_7: power port map(vdd);," pmos_0: PMOStran port map(b, y, vdd);"," pmos_1: PMOStran port map(a, vdd, y);",end nand2_BODY;]
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell nand3;1{ic}
Cnand3;1{ic}||artwork|979627662000|1194494635013|E
NCircle|art@0||5.5|5|1|1||
NOpened-Polygon|art@1||1|5|2|6|||trace()V[1/-3,-1/-3,-1/3,1/3]
NCircle|art@2||2|5|6|6|RRR||ART_degrees()F[0.0,3.1415927]
NOpened-Polygon|art@3||-1|3|2||||trace()V[-1/0,1/0]
NOpened-Polygon|art@4||-1|5|2||||trace()V[-1/0,1/0]
NOpened-Polygon|art@5||-1|7|2||||trace()V[-1/0,1/0]
NOpened-Polygon|art@6||6.5|5|1||||trace()V[0.5/0,-0.5/0]
Ngeneric:Invisible-Pin|pin@0||2|5.3|||||ART_message(D5G1;)S[nand3]
Ngeneric:Invisible-Pin|pin@1||-2|3||||
Ngeneric:Invisible-Pin|pin@2||-2|5||||
Ngeneric:Invisible-Pin|pin@3||-2|7||||
Ngeneric:Invisible-Pin|pin@4||7|5||||
Ea||D5G1;|pin@1||I
Eb||D5G1;|pin@2||I
Ec||D5G1;|pin@3||I
Ey||D5G1;|pin@4||O
X
# Cell nand3;1{lay}
Cnand3;1{lay}||mocmos|977349375000|1194494635013||DRC_last_good_drc()I1191793307|NET_ncc_last_result1()S[TIME 1191794549,MATCH lab3_BC:nand3{sch},EXPORT b:b,EXPORT c:c,EXPORT y:y,EXPORT a:a]|prototype_center()I[-25800,-84000]
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Polysilicon-1-Con|contact@0||19|40||||
NMetal-1-P-Active-Con|contact@1||26|68|8||R|
NMetal-1-N-Active-Con|contact@2||20|15||14||
NMetal-1-N-Active-Con|contact@3||2|15||14||
NMetal-1-P-Active-Con|contact@4||10|68|8||R|
NMetal-1-P-Active-Con|contact@5||2|68|8||R|
NMetal-1-P-Active-Con|contact@6||18|68|8||R|
NMetal-1-Metal-2-Con|contact@7||2|0||||
NMetal-1-Metal-2-Con|contact@8||2|80||||
NMetal-1-Metal-2-Con|contact@9||18|80||||
NMetal-1-Polysilicon-1-Con|contact@10||13|48||||
NMetal-1-Polysilicon-1-Con|contact@11||3|56||||
NN-Transistor|nmos@0||16|15|15||R|
NN-Transistor|nmos@1||6|15|15||R|
NN-Transistor|nmos@2||11|15|15||R|
NMetal-1-Pin|pin@0||20|22||||
NMetal-1-Pin|pin@1||26|22||||
NPolysilicon-1-Pin|pin@2||22|40.5||||
NPolysilicon-1-Pin|pin@3||16|27||||
NPolysilicon-1-Pin|pin@4||22|27||||
NPolysilicon-1-Pin|pin@5||14|48.5||||
NMetal-1-Pin|pin@6||10|57||||
NMetal-1-Pin|pin@7||26|57||||
NMetal-2-Pin|pin@8||0|80||||
NPolysilicon-1-Pin|pin@9||11|49||||
NPolysilicon-1-Pin|pin@10||14|49||||
NMetal-2-Pin|pin@11||2|80||||
NMetal-2-Pin|pin@12||0|0||||
NMetal-2-Pin|pin@13||28|0||||
NMetal-2-Pin|pin@14||28|80||||
NMetal-1-Pin|pin@15||2|80||||
NPolysilicon-1-Pin|pin@16||6|56||||
NN-Well-Node|plnode@0||14|70.5|40|29||A
NP-Select-Node|plnode@1||14|68|32|16||A
NP-Well-Node|plnode@2||11|12.5|34|35||A
NN-Select-Node|plnode@3||11|15|26|22||A
NP-Transistor|pmos@0||22|68|9||R|
NP-Transistor|pmos@1||14|68|9||R|
NP-Transistor|pmos@2||6|68|9||R|
NMetal-1-N-Well-Con|substr@0||10|80||||
NMetal-1-P-Well-Con|well@0||12|0||||
AMetal-2|net@0||1|S1800|contact@8||2|80|contact@9||18|80
AMetal-1|net@1||1|S2700|contact@2||20|16|pin@0||20|22
AMetal-1|net@2||1|S1800|pin@0||20|22|pin@1||26|22
AMetal-1|net@3||1|S2700|pin@1||26|22|pin@7||26|57
APolysilicon-1|net@4|||S0|pin@2||22|40.5|contact@0||19.5|40.5
APolysilicon-1|net@5|||S2700|pin@4||22|27|pin@2||22|40.5
APolysilicon-1|net@6|||S2700|pin@2||22|40.5|pmos@0|p-trans-poly-left|22|60
APolysilicon-1|net@7|||S2700|nmos@0|n-trans-poly-right|16|26|pin@3||16|27
APolysilicon-1|net@8|||S1800|pin@3||16|27|pin@4||22|27
APolysilicon-1|net@9|||S2700|pin@5||14|48.5|pmos@1|p-trans-poly-left|14|60
APolysilicon-1|net@10|||S900|pin@10||14|49|pin@5||14|48.5
APolysilicon-1|net@11|||S0|pin@5||14|48.5|contact@10||12.5|48.5
AMetal-1|net@12||1|S1800|pin@6||10|57|pin@7||26|57
AMetal-1|net@13||1|S2700|pin@6||10|57|contact@4||10|64
AMetal-1|net@14||1|S2700|pin@7||26|57|contact@1||26|68
AP-Active|net@15|||S0|pmos@0|p-trans-diff-bottom|26|71.5|contact@1||26|71.5
AP-Active|net@16|||S1800|contact@6||18|64|pmos@0|p-trans-diff-top|18|64
AN-Active|net@17|||S1800|nmos@0|n-trans-diff-bottom|20|16|contact@2||20.5|16
AN-Active|net@18|||S0|nmos@2|n-trans-diff-bottom|14.5|12|nmos@0|n-trans-diff-top|12.5|12
AN-Active|net@19|||S0|nmos@1|n-trans-diff-bottom|10|16.5|nmos@2|n-trans-diff-top|7|16.5
AN-Active|net@20|||S1800|nmos@1|n-trans-diff-top|2|15.5|contact@3||2.5|15.5
APolysilicon-1|net@21|||S900|pin@9||11|49|nmos@2|n-trans-poly-right|11|26
APolysilicon-1|net@22|||S0|pin@10||14|49|pin@9||11|49
AMetal-2|net@23||1|S0|pin@11||2|80|pin@8||0|80
AP-Active|net@24|||S0|contact@4||10.5|67.5|pmos@1|p-trans-diff-top|10|67.5
AP-Active|net@25|||S0|pmos@2|p-trans-diff-bottom|10|67.5|contact@4||9.5|67.5
AP-Active|net@26|||S0|contact@5||2.5|67.5|pmos@2|p-trans-diff-top|2|67.5
AP-Active|net@27|||S1800|pmos@1|p-trans-diff-bottom|18|67|contact@6||18|67
AMetal-1|net@28||1|S1800|contact@7||2|0|well@0||11.5|0
AMetal-1|net@29||1|S900|contact@3||2|16|contact@7||2|0
AMetal-2|net@30||1|S0|contact@7||2|0|pin@12||0|0
AMetal-2|net@31||1|S0|pin@13||28|0|contact@7||2|0
AMetal-2|net@32||1|S1800|pin@8||0|80|contact@8||2|80
AMetal-2|net@33||1|S0|pin@14||28|80|contact@9||18|80
AMetal-1|net@34|||S900|pin@15||2|80|contact@8||2|80
AMetal-1|net@35||1|S0|substr@0||9.5|80|pin@15||2|80
AMetal-1|net@36||1|S900|pin@15||2|80|contact@5||2|70
AMetal-1|net@37||1|S900|contact@9||18|80|contact@6||18|70
APolysilicon-1|net@38|||S900|pin@16||6|56|nmos@1|n-trans-poly-right|6|26
APolysilicon-1|net@39|||S900|pmos@2|p-trans-poly-left|6|60|pin@16||6|56
APolysilicon-1|net@40|||S0|pin@16||6|56|contact@11||3|56
AMetal-1|net@41||1|S0|contact@9||18|80|substr@0||10.5|80
Ea||D5G2;|contact@11||I
Eb||D5G2;|contact@10||I
Ec||D5G2;|contact@0||I
Egnd||D5G2;|pin@12||G
Evdd||D5G2;|pin@8||P
Ey||D5G2;|pin@1||O
X
# Cell nand3;1{sch}
Cnand3;1{sch}||schematic|979627229000|1194494635013||NET_ncc_last_result1()S[TIME 1191794549,MATCH lab3_BC:nand3{lay},EXPORT b:b,EXPORT c:c,EXPORT y:y,EXPORT a:a]
NOff-Page|conn@0||-33|6||||
NOff-Page|conn@1||-33|0.5||||
NOff-Page|conn@2||-33|-5||||
NOff-Page|conn@3||-4.5|10||||
NGround|gnd@0||-16|-11||||
NTransistor|nmos@0||-18|-5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I18
NTransistor|nmos@1||-18|0.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I18
NTransistor|nmos@2||-18|6|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I18
NWire_Pin|pin@0||-13|-5||||
NWire_Pin|pin@1||-13|12||||
NWire_Pin|pin@2||-20.5|0.5||||
NWire_Pin|pin@3||-20.5|12||||
NWire_Pin|pin@4||-28|6||||
NWire_Pin|pin@5||-28|12||||
NTransistor|pmos@0||-10.5|12|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I12
NTransistor|pmos@1||-18|12|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I12
NTransistor|pmos@2||-25.5|12|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)I2|ATTR_width(D5G1;X0.5;Y-1;)I12
NPower|pwr@0||-16|17||||
Awire|net@0|||1800|pmos@0|s|-8.5|10|conn@3|a|-6.5|10
Awire|net@1|||0|pin@4||-28|6|conn@0|y|-31|6
Awire|net@2|||0|nmos@0|g|-19|-5|conn@2|y|-31|-5
Awire|net@3|||0|pin@2||-20.5|0.5|conn@1|y|-31|0.5
Awire|net@4|||1800|nmos@0|g|-19|-5|pin@0||-13|-5
Awire|net@5|||2700|pin@0||-13|-5|pin@1||-13|12
Awire|net@6|||1800|pin@1||-13|12|pmos@0|g|-11.5|12
Awire|net@7|||0|nmos@1|g|-19|0.5|pin@2||-20.5|0.5
Awire|net@8|||2700|pin@2||-20.5|0.5|pin@3||-20.5|12
Awire|net@9|||1800|pin@3||-20.5|12|pmos@1|g|-19|12
Awire|net@10|||0|nmos@2|g|-19|6|pin@4||-28|6
Awire|net@11|||2700|pin@4||-28|6|pin@5||-28|12
Awire|net@12|||1800|pin@5||-28|12|pmos@2|g|-26.5|12
Awire|net@13|||2700|pmos@1|d|-16|14|pwr@0||-16|17
Awire|net@14|||0|pmos@0|d|-8.5|14|pmos@1|d|-16|14
Awire|net@15|||0|pmos@1|d|-16|14|pmos@2|d|-23.5|14
Awire|net@16|||1800|pmos@2|s|-23.5|10|pmos@1|s|-16|10
Awire|net@17|||0|pmos@0|s|-8.5|10|pmos@1|s|-16|10
Awire|net@18|||900|pmos@1|s|-16|10|nmos@2|d|-16|8
Awire|net@19|||900|nmos@0|s|-16|-7|gnd@0||-16|-9
Awire|net@20|||2700|nmos@0|d|-16|-3|nmos@1|s|-16|-1.5
Awire|net@21|||2700|nmos@1|d|-16|2.5|nmos@2|s|-16|4
Ea||D5G2;|conn@2|y|I
Eb||D5G2;|conn@1|y|I
Ec||D5G2;|conn@0|y|I
Ey||D5G2;|conn@3|y|O
X
# Cell nor2;1{ic}
Cnor2;1{ic}||artwork|977189205000|1194494637051|E
NCircle|art@0||0|5|6|2|RRR||ART_degrees()F[0.0,3.1415927]
NOpened-Polygon|art@1||1|2|2||||trace()V[1/0,-1/0]
NOpened-Polygon|art@2||1|8|2||||trace()V[1/0,-1/0]
NCircle|art@3||5.5|5|1|1||
NCircle|art@4||2|5|6|6|RRR||ART_degrees()F[0.0,3.1415927]
NOpened-Polygon|art@5||0|4|2||||trace()V[-1/0,1/0]
NOpened-Polygon|art@6||0|6|2||||trace()V[-1/0,1/0]
NOpened-Polygon|art@7||6.5|5|1||||trace()V[0.5/0,-0.5/0]