From e1871bb19c439fe1c98db2d5f0f4f45897f609a5 Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 10:31:28 +0100 Subject: [PATCH 01/11] Add atsamd-hal-macros crate --- atsamd-hal-macros/Cargo.toml | 17 ++ atsamd-hal-macros/build.rs | 280 +++++++++++++++++++++++++ atsamd-hal-macros/devices.yaml | 138 +++++++++++++ atsamd-hal-macros/src/error.rs | 21 ++ atsamd-hal-macros/src/generation.rs | 96 +++++++++ atsamd-hal-macros/src/lib.rs | 307 ++++++++++++++++++++++++++++ atsamd-hal-macros/src/parsing.rs | 152 ++++++++++++++ 7 files changed, 1011 insertions(+) create mode 100644 atsamd-hal-macros/Cargo.toml create mode 100644 atsamd-hal-macros/build.rs create mode 100644 atsamd-hal-macros/devices.yaml create mode 100644 atsamd-hal-macros/src/error.rs create mode 100644 atsamd-hal-macros/src/generation.rs create mode 100644 atsamd-hal-macros/src/lib.rs create mode 100644 atsamd-hal-macros/src/parsing.rs diff --git a/atsamd-hal-macros/Cargo.toml b/atsamd-hal-macros/Cargo.toml new file mode 100644 index 00000000000..65170727afa --- /dev/null +++ b/atsamd-hal-macros/Cargo.toml @@ -0,0 +1,17 @@ +[package] +name = "atsamd-hal-macros" +version = "0.16.0" +edition = "2021" + +[lib] +proc-macro = true + +[dependencies] +litrs = "0.4.1" +phf = { version = "0.11.1", default-features = false } + +[build-dependencies] +phf = { version = "0.11.1", default-features = false } +phf_codegen = "0.11.1" +serde = { version = "1.0.195", features = ["derive"] } +serde_yaml = "0.9.30" diff --git a/atsamd-hal-macros/build.rs b/atsamd-hal-macros/build.rs new file mode 100644 index 00000000000..a258b8da0b7 --- /dev/null +++ b/atsamd-hal-macros/build.rs @@ -0,0 +1,280 @@ +use std::{ + collections::{BTreeMap, BTreeSet, HashMap}, + path::PathBuf, +}; + +pub type PinCollection = BTreeSet; + +#[derive(serde::Deserialize, Debug)] +#[serde(deny_unknown_fields)] +#[serde(rename_all = "kebab-case")] +struct Devices { + pin_groups: HashMap, + families: HashMap, +} + +#[derive(serde::Deserialize, Debug)] +#[serde(deny_unknown_fields)] +struct Family { + pins: HashMap, + peripherals: Vec, +} + +#[derive(Debug)] +struct Peripheral { + name: String, + variant: Option, + start: u32, + count: Option, + only: Option>, + except: Option>, +} + +impl<'de> serde::Deserialize<'de> for Peripheral { + fn deserialize(deserializer: D) -> Result + where + D: serde::Deserializer<'de>, + { + #[derive(serde::Deserialize, Debug)] + #[serde(deny_unknown_fields)] + struct PeripheralBody { + #[serde(default)] + variant: Option, + #[serde(default)] + only: Option>, + #[serde(default)] + except: Option>, + #[serde(default)] + count: Option, + #[serde(default)] + start: u32, + } + + struct Visitor; + + impl<'de> serde::de::Visitor<'de> for Visitor { + type Value = Peripheral; + + fn expecting(&self, formatter: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(formatter, "a string or a peripheral mapping") + } + + fn visit_str(self, v: &str) -> Result + where + E: serde::de::Error, + { + Ok(Peripheral { + name: v.to_string(), + variant: None, + count: None, + only: None, + except: None, + start: 0, + }) + } + + fn visit_string(self, v: String) -> Result + where + E: serde::de::Error, + { + Ok(Peripheral { + name: v, + variant: None, + count: None, + only: None, + except: None, + start: 0, + }) + } + + fn visit_map(self, mut map: A) -> Result + where + A: serde::de::MapAccess<'de>, + { + if let Some((name, body)) = map.next_entry::()? { + if map + .next_entry::()? + .is_none() + { + Ok(Peripheral { + name, + variant: body.variant, + only: body.only, + except: body.except, + count: body.count, + start: body.start, + }) + } else { + Err(serde::de::Error::invalid_length( + 2, + &"expected peripheral map to have a single element", + )) + } + } else { + Err(serde::de::Error::invalid_length( + 0, + &"expected peripheral map to have a single element", + )) + } + } + } + + deserializer.deserialize_any(Visitor) + } +} + +fn normalize_pins(pin_groups: &HashMap, pins: &mut PinCollection) -> bool { + let mut new = Vec::new(); + let mut changed = false; + loop { + pins.retain(|pin| { + if let Some(pins) = pin_groups.get(pin) { + new.extend(pins.iter().cloned()); + false + } else { + true + } + }); + if new.is_empty() { + break; + } + pins.extend(new.drain(..)); + changed = true; + } + changed +} + +fn main() -> std::io::Result<()> { + println!("cargo:rerun-if-changed=devices.yaml"); + println!("cargo:rerun-if-changed=build.rs"); + let out_dir: PathBuf = std::env::var("OUT_DIR").unwrap().into(); + let manifest_dir: PathBuf = std::env::var("CARGO_MANIFEST_DIR").unwrap().into(); + + let peripheral_mapping = load_peripheral_mapping(manifest_dir)?; + let all_devices = peripheral_mapping + .values() + .flat_map(|value| value.iter()) + .map(|device| device.as_str()) + .collect::>() + .into_iter() + .map(|s| format!("{s:?}")) + .collect::>() + .join(", "); + let map = generate_phf_map(&peripheral_mapping); + + let file = std::fs::File::create(out_dir.join("generated.rs"))?; + let mut file = std::io::BufWriter::new(file); + use std::io::Write; + write!( + file, + "static PERIPHERALS: phf::Map<&str, &[&str]> = {};", + map.build() + )?; + + write!(file, "static ALL_DEVICES: &[&str] = &[{all_devices}];",)?; + + Ok(()) +} + +fn generate_phf_map( + peripheral_mapping: &BTreeMap>, +) -> phf_codegen::Map<&str> { + let mut map = phf_codegen::Map::new(); + + for (peripheral, devices) in peripheral_mapping { + let mut value = String::from("&["); + for device in devices { + use std::fmt::Write; + write!(value, "{device:?},").unwrap(); + } + value.push(']'); + map.entry(peripheral.as_str(), &value); + } + map +} + +fn load_peripheral_mapping( + manifest_dir: PathBuf, +) -> Result>, std::io::Error> { + let mut devices: Devices = + serde_yaml::from_reader(std::fs::File::open(manifest_dir.join("devices.yaml"))?).unwrap(); + loop { + let mut changed = false; + for key in devices + .pin_groups + .keys() + .cloned() + .collect::>() + .into_iter() + { + let mut cur = std::mem::take(devices.pin_groups.get_mut(&key).unwrap()); + changed |= normalize_pins(&devices.pin_groups, &mut cur); + devices.pin_groups.insert(key, cur); + } + if !changed { + break; + } + } + let mut peripheral_mapping: BTreeMap> = BTreeMap::new(); + let mut peripheral_sub_mapping: BTreeMap> = BTreeMap::new(); + for (family_name, mut family) in devices.families { + for (device_name, pins) in family.pins.iter_mut() { + normalize_pins(&devices.pin_groups, pins); + for pin in pins.iter() { + peripheral_mapping + .entry(pin.clone()) + .or_default() + .insert(device_name.clone()); + let port_group = pin + .trim_end_matches(|c: char| c.is_ascii_digit()) + .strip_prefix('p') + .unwrap(); + peripheral_mapping + .entry(format!("pin-group-{port_group}",)) + .or_default() + .insert(device_name.clone()); + } + } + for peripheral in family.peripherals { + let variant = peripheral.variant.unwrap_or_else(|| family_name.clone()); + for i in 0..peripheral.count.unwrap_or(1) { + let name = if peripheral.count.is_some() { + format!("{}{}", peripheral.name, peripheral.start + i) + } else { + peripheral.name.clone() + }; + let combined_name = format!("{}-{}", name, variant); + let devices = family + .pins + .keys() + .filter(|key| { + peripheral + .only + .as_ref() + .map_or(true, |only| only.contains(key)) + && peripheral + .except + .as_ref() + .map_or(true, |except| !except.contains(key)) + }) + .cloned(); + peripheral_mapping + .entry(name) + .or_default() + .extend(devices.clone()); + peripheral_sub_mapping + .entry(combined_name) + .or_default() + .extend(devices); + } + } + } + + for (sub_peripheral_key, sub_peripheral) in peripheral_sub_mapping { + assert!(peripheral_mapping + .insert(sub_peripheral_key, sub_peripheral) + .is_none()); + } + + Ok(peripheral_mapping) +} diff --git a/atsamd-hal-macros/devices.yaml b/atsamd-hal-macros/devices.yaml new file mode 100644 index 00000000000..1fdbda4d5d8 --- /dev/null +++ b/atsamd-hal-macros/devices.yaml @@ -0,0 +1,138 @@ +pin-groups: + pins-14: ["pa02", "pa04", "pa05", "pa08", "pa09", "pa14", "pa15", "pa24", "pa25", "pa30", "pa31"] + pins-24: ["pins-14", "pa03", "pa06", "pa07", "pa10", "pa11", "pa16", "pa17", "pa22", "pa23"] + pins-32: ["pins-24", "pa18", "pa19"] + pins-32a: ["pins-32", "pa00", "pa01", "pa27"] + pins-32l: ["pins-32", "pb02", "pb03", "pb04", "pb05"] + pins-48: ["pins-32", "pa12", "pa13", "pa20", "pa21", "pa27", "pb02", "pb03", "pb08", "pb09", "pb10", "pb11"] + pins-48a: ["pins-48", "pa00", "pa01", "pb22", "pb23"] + pins-48l: ["pins-48", "pb00", "pb01", "pb04", "pb05"] + pins-64: ["pins-48a", "pins-48l", "pb06", "pb07", "pb12", "pb13", "pb14", "pb15", "pb16", "pb17", "pb30", "pb31"] + pins-100: ["pins-64", "pb18", "pb19", "pb20", "pb21", "pb24", "pb25", "pc00", "pc01", "pc02", "pc03", "pc05", "pc06", "pc07", "pc10", "pc11", "pc12", "pc13", "pc14", "pc15", "pc16", "pc17", "pc18", "pc19", "pc20", "pc21", "pc24", "pc25", "pc26", "pc27", "pc28"] + pins-128: ["pins-100", "pb26", "pb27", "pb28", "pb29", "pc04", "pc22", "pc23", "pc30", "pc31", "pd00", "pd01", "pd08", "pd09", "pd10", "pd11", "pd12", "pd20", "pd21"] + +families: + d11: + pins: + samd11c: ["pins-14", "pa28"] + samd11d: ["pins-24", "pa27", "pa28"] + peripherals: + - serial-numbers + - dsu + - clock + - gclk + - pm + - sysctrl + - wdt + - rtc + - dmac + - eic + - nvmctrl + - port + - evsys + - sercom: { count: 2, only: ["samd11c"] } + - sercom: { count: 3, only: ["samd11d"] } + - tc: { start: 1, count: 2 } + - tcc: { count: 1 } + - usb + - adc + - ac + - dac + - ptc + + d21: + pins: + samd21e: ["pins-32a", "pa28"] + samd21g: ["pins-48a", "pa28"] + samd21j: ["pins-64", "pa28"] + samd21el: ["pins-32l"] + samd21gl: ["pins-48l", "pa28"] + peripherals: + - serial-numbers + - dsu + - clock + - gclk + - pm + - sysctrl + - wdt + - rtc + - dmac + - eic + - nvmctrl + - port + - evsys + - sercom: { count: 4, only: ["samd21e", "samd21el"] } + - sercom: { count: 6, only: ["samd21g", "samd21j", "samd21gl"] } + - i2s: { only: ["samd21e", "samd21g", "samd21j"] } + - tc: { start: 3, count: 3, only: ["samd21e", "samd21g", "samd21el"] } + - tc: { start: 3, count: 5, only: ["samd21j", "samd21gl"] } + # TODO: Some of the devices actually has 4, figure out how to support that + - tcc: { count: 3 } + - usb: { only: ["samd21e", "samd21g", "samd21j"] } + - adc + - ac + - dac + - ptc + + d5x: + pins: + samd51g: ["pins-48a"] + samd51j: ["pins-64"] + samd51n: ["pins-100"] + samd51p: ["pins-128"] + same51g: ["pins-48a"] + same51j: ["pins-64"] + same51n: ["pins-100"] + same53j: ["pins-64"] + same53n: ["pins-100"] + same54n: ["pins-100"] + same54p: ["pins-128"] + peripherals: + - serial-numbers + - cmcc + - dsu + - clock + - gclk + - mclk + - rstc + - ramecc + - pm + - supc + - wdt + - rtc + - dmac + - eic + - gmac: { only: ["same53j", "same53n", "same54n", "same54p"] } + - nvmctrl + - icm + - pac + - oscctrl + - osc32kctrl + - freqm + - evsys + - port + - sercom: { count: 6, only: ["samd51g", "samd51j", "same51g", "same51j", "same53j"] } + - sercom: { count: 8, only: ["samd51n", "samd51p", "same51n", "same53n", "same54n", "same54p"] } + - qspi + - usb + - can: { count: 1, only: ["same51g"]} + - can: { count: 2, only: ["same51j", "same51n", "same54n", "same54p"] } + - sdhc: { count: 1, only: ["samd51g", "samd51j", "same51g", "same51n", "same51j", "same53j"] } + - sdhc: { count: 2, only: ["samd51n", "samd51p", "same53n", "same54n", "same54p"] } + - ccl + - aes + - pukcc + - pukcl + - trng + - adc + - ac + - dac + - tc: { count: 4, only: ["samd51g", "same51g"] } + - tc: { count: 6, only: ["samd51j", "same51j", "same53j"] } + - tc: { count: 8, only: ["same53n", "same54p", "same54n", "samd51p", "samd51n", "same51n"] } + - tcc: { count: 3, only: ["samd51g", "same51g"] } + - tcc: { count: 5, only: ["samd51j", "samd51n", "samd51p", "same51j", "same51n", "same53j", "same53n", "same54n", "same54p"] } + - ptc + - i2s: { except: ["samd51j"] } + - pcc + - pdec diff --git a/atsamd-hal-macros/src/error.rs b/atsamd-hal-macros/src/error.rs new file mode 100644 index 00000000000..df17e150a0b --- /dev/null +++ b/atsamd-hal-macros/src/error.rs @@ -0,0 +1,21 @@ +use proc_macro::TokenStream; + +pub enum Error { + UnknownPeripheral { peripheral: String }, + GenericParseError { expected: String }, +} + +impl Error { + pub fn to_compile_error(&self, name: &str) -> TokenStream { + let s = match self { + Error::UnknownPeripheral { peripheral } => { + format!("{name}: unknown peripheral {peripheral:?}") + } + Error::GenericParseError { expected } => { + format!("{name}: could not parse the argument, expected {expected}") + } + }; + let s = format!("compile_error!({s:?});"); + s.parse().unwrap() + } +} diff --git a/atsamd-hal-macros/src/generation.rs b/atsamd-hal-macros/src/generation.rs new file mode 100644 index 00000000000..f8eaaf94f49 --- /dev/null +++ b/atsamd-hal-macros/src/generation.rs @@ -0,0 +1,96 @@ +use std::collections::BTreeSet; + +use proc_macro::{Delimiter, Group, Ident, Literal, Punct, Spacing, Span, TokenStream, TokenTree}; + +use crate::{error::Error, parsing::HalExpr}; + +include!(concat!(env!("OUT_DIR"), "/generated.rs")); + +fn all_devices() -> BTreeSet<&'static str> { + ALL_DEVICES.iter().copied().collect() +} + +fn lookup_peripheral(peripheral: &str) -> Result<&'static [&'static str], Error> { + if let Some(cur_devices) = PERIPHERALS.get(peripheral) { + Ok(*cur_devices) + } else { + Err(Error::UnknownPeripheral { + peripheral: peripheral.to_string(), + }) + } +} + +fn cfg_token_tree<'a>(devices: impl IntoIterator) -> Group { + let cfg_args = cfg_args(devices); + let cfg_args = TokenTree::Group(Group::new( + Delimiter::Parenthesis, + cfg_args.into_iter().collect(), + )); + + Group::new( + Delimiter::Bracket, + [ + TokenTree::Ident(Ident::new("cfg", Span::call_site())), + cfg_args, + ] + .into_iter() + .collect(), + ) +} + +pub fn cfg_args<'a>(devices: impl IntoIterator) -> Vec { + let mut inner = Vec::new(); + for device in devices { + if !inner.is_empty() { + inner.push(TokenTree::Punct(Punct::new(',', Spacing::Alone))); + } + inner.push(TokenTree::Ident(Ident::new("feature", Span::call_site()))); + inner.push(TokenTree::Punct(Punct::new('=', Spacing::Alone))); + inner.push(TokenTree::Literal(Literal::string(device))); + } + let any_args = TokenTree::Group(Group::new( + Delimiter::Parenthesis, + inner.into_iter().collect(), + )); + vec![ + TokenTree::Ident(Ident::new("any", Span::call_site())), + any_args, + ] +} + +pub fn hal_expr_to_devices(expr: &HalExpr) -> Result, Error> { + match expr { + HalExpr::All(args) => { + let mut devices = all_devices(); + for arg in args { + devices = devices + .intersection(&hal_expr_to_devices(arg)?) + .copied() + .collect(); + } + Ok(devices) + } + HalExpr::Any(args) => { + let mut devices = BTreeSet::new(); + for arg in args { + devices.extend(hal_expr_to_devices(arg)?); + } + Ok(devices) + } + HalExpr::Peripheral(lit) => Ok(lookup_peripheral(lit)?.iter().copied().collect()), + } +} + +pub fn gen_cfgs(expr: &HalExpr) -> Result { + Ok(cfg_token_tree(hal_expr_to_devices(expr)?)) +} + +pub fn add_cfgs_to_input(cfgs: Group, input: TokenStream) -> TokenStream { + [ + TokenTree::Punct(Punct::new('#', Spacing::Alone)), + TokenTree::Group(cfgs), + ] + .into_iter() + .chain(input) + .collect::() +} diff --git a/atsamd-hal-macros/src/lib.rs b/atsamd-hal-macros/src/lib.rs new file mode 100644 index 00000000000..fca8f76ac55 --- /dev/null +++ b/atsamd-hal-macros/src/lib.rs @@ -0,0 +1,307 @@ +//! This crate contains proc-macros to be used by the `atsamd-hal` crate. It is +//! not intended to be used outside this crate, and no stability guarantees are +//! made. +//! +//! The main purpose of this crate is to separate the task of writing the code +//! to support peripherals of the atsamd families from the task of figuring out +//! which specific devices has those peripherals. +//! +//! The actual mapping of devices to peripherals is specified in the +//! `devices.yaml` file. In the `atsamd-hal` crate you then only need to care +//! about the peripherals themselves (and their different variants). +//! +//! To use the macros in this crate, you need to specify a **peripheral +//! expression**, which can be one of the following: +//! +//! - A peripheral from `devices.yaml` in the form of a string. Examples: +//! `"serial-numbers"` or `"sercom3"`. +//! - A peripheral from `devices.yaml` suffixed with the device family. +//! Examples: `"serial-numbers-d11"` or `"sercom3-d5x"` +//! - A pin from `devices.yaml`. Examples: `"pb22"`. +//! - An expression of the form `any([peripheral expression], ...)`. Example: +//! `any("pm-d11", "pm-d21", "rstc-d5x")`. +//! - An expression of the form `all([peripheral expression], ...)`. Example: +//! `all("tc4", "tc5")`. + +use proc_macro::{Delimiter, Group, Ident, Literal, Punct, Spacing, Span, TokenStream, TokenTree}; + +mod error; +mod generation; +mod parsing; + +use error::Error; +use generation::{add_cfgs_to_input, cfg_args, gen_cfgs, hal_expr_to_devices}; +use parsing::{eat_attribute, eat_eof, eat_group, eat_hal_expr, eat_operator, eat_string_literal}; + +/// Attribute macro which expands to a suitable `#[cfg(...)]` expression. +/// +/// It can be used like `#[hal_cfg([peripheral expression])]`. +/// +/// The macro will look up all devices that fulfill the expression and expand +/// the macro into a cfg attribute of the form `#[cfg(any(feature = "device1", +/// feature = "device2", ...)]`. +#[proc_macro_attribute] +pub fn hal_cfg(args: TokenStream, input: TokenStream) -> TokenStream { + hal_cfg_impl(args).map_or_else( + |e| e.to_compile_error("hal_cfg"), + |cfgs| add_cfgs_to_input(cfgs, input), + ) +} + +fn hal_cfg_impl(args: TokenStream) -> Result { + let mut args = args.into_iter().peekable(); + let expr = eat_hal_expr(&mut args)?; + if args.peek().is_some() { + eat_operator(",", &mut args)?; + } + eat_eof(&mut args)?; + let cfgs = gen_cfgs(&expr)?; + Ok(cfgs) +} + +/// Macro which expands to a `mod foo;` item with different paths for each +/// device. +/// +/// It can be used like this: +/// +/// ```ignore +/// #[hal_module( +/// any("nvmctrl-d11", "nvmctrl-d21") => "calibration/d11.rs", +/// "nvmctrl-d5x" => "calibration/d5x.rs", +/// )] +/// pub mod calibration {} + +/// #[hal_module("aes") +/// pub mod aes {} +/// ``` +/// +/// This will then expand to something of the form: +/// ```ignore +/// #[cfg(any(feature = "samd11c", ...))] +/// #[path = "calibration/d11.rs"] +/// pub mod calibration; +/// +/// #[cfg(any(feature = "samd51g", ...))] +/// #[path = "calibration/d5x.rs"] +/// pub mod calibration; +/// +/// #[cfg(any(feature = "samd51g", ...))] +/// pub mod aes; +/// ``` +/// +/// Ideally you would be to write `pub mod calibration;` instead of +/// `pub mod calibration {}`, but unfortunately non-inline modules are not +/// currently supposed in proc macros. See +/// [rust#54727](https://github.com/rust-lang/rust/issues/54727) for details. +#[proc_macro_attribute] +pub fn hal_module(args: TokenStream, input: TokenStream) -> TokenStream { + hal_module_impl(args, input).unwrap_or_else(|e| e.to_compile_error("hal_module")) +} + +fn hal_module_impl(args: TokenStream, input: TokenStream) -> Result { + let mut args = args.into_iter().peekable(); + let args = &mut args; + + let input = input + .into_iter() + .map(|token| { + // Replace `{}` with `;` + if let TokenTree::Group(g) = &token { + if g.delimiter() == Delimiter::Brace && g.stream().into_iter().count() == 0 { + return TokenTree::Punct(Punct::new(';', Spacing::Alone)); + } + } + token + }) + .collect::>(); + + let mut out = TokenStream::new(); + + while args.peek().is_some() { + let hal_expr = eat_hal_expr(args)?; + + out.extend([ + TokenTree::Punct(Punct::new('#', Spacing::Alone)), + TokenTree::Group(gen_cfgs(&hal_expr)?), + ]); + + if matches!(args.peek(), Some(TokenTree::Punct(p)) if p.as_char() == '=') { + eat_operator("=>", args)?; + let path = eat_string_literal(args)?; + out.extend([ + TokenTree::Punct(Punct::new('#', Spacing::Alone)), + TokenTree::Group(Group::new( + Delimiter::Bracket, + TokenStream::from_iter([ + TokenTree::Ident(Ident::new("path", Span::call_site())), + TokenTree::Punct(Punct::new('=', Spacing::Alone)), + TokenTree::Literal(Literal::string(&path)), + ]), + )), + ]); + } + + out.extend(input.iter().cloned()); + + if args.peek().is_some() { + eat_operator(",", args)?; + } + } + eat_eof(args)?; + + Ok(out) +} + +/// Helper macro to allow using `#[hal_cfg(..)]` macro in more places +/// +/// Normally the `#[cfg(..)]` macro is allowed in many more places than +/// proc-macros, such as directly on a statement. This mitigates that +/// restriction. +/// +/// It can be used like this: +/// +/// ```ignore +/// #[hal_macro_helper] +/// struct MyStruct { +/// #[hal_cfg("sercom0")] +/// my_field: String +/// } +/// ``` +/// +/// This works, because attributes are allowed on the outer item. +/// +/// The `#[hal_macro_helper]` will search through the item and replace all +/// instances of the `#[hal_cfg(..)]` attribute with the corresponding +/// `#[cfg(..)]` attribute instead. This way the inner attributes are +/// technically not interpreted as a proc-macro at all. +#[proc_macro_attribute] +pub fn hal_macro_helper(_args: TokenStream, input: TokenStream) -> TokenStream { + hal_macro_helper_impl(input).unwrap_or_else(|e| e.to_compile_error("hal_macro_helper")) +} + +fn hal_macro_helper_impl(input: TokenStream) -> Result { + let input = input.into_iter(); + let mut out = Vec::with_capacity(input.size_hint().0); + let mut last_was_pound = false; + + for mut arg in input { + let saved_last_was_pound = std::mem::replace(&mut last_was_pound, false); + match &mut arg { + TokenTree::Group(group) => { + if saved_last_was_pound { + replace_inner_macros(group)?; + } else { + let mut new_group = + Group::new(group.delimiter(), hal_macro_helper_impl(group.stream())?); + new_group.set_span(group.span()); + *group = new_group; + } + } + TokenTree::Punct(p) if p.as_char() == '#' && p.spacing() == Spacing::Alone => { + last_was_pound = true; + } + _ => (), + } + out.push(arg); + } + Ok(out.into_iter().collect()) +} + +fn replace_inner_macros(group: &mut Group) -> Result<(), Error> { + let mut tokens = group.stream().into_iter(); + let Some(TokenTree::Ident(func)) = tokens.next() else { + return Ok(()); + }; + + if func.to_string().as_str() != "hal_cfg" { + return Ok(()); + } + + let Some(TokenTree::Group(inner_group)) = tokens.next() else { + return Ok(()); + }; + + if inner_group.delimiter() != Delimiter::Parenthesis { + return Ok(()); + } + + if tokens.next().is_some() { + return Ok(()); + } + + let mut new_group = hal_cfg_impl(inner_group.stream())?; + new_group.set_span(group.span()); + *group = new_group; + + Ok(()) +} + +/// Helper macro to make conditional docs work nicer +/// +/// Can be used like this: +/// +/// ```ignore +/// #[hal_docs( +/// { +/// /// Example struct! +/// /// +/// /// It can do things! +/// } +/// "usb" => { +/// /// +/// /// It also supports usb on this device. +/// } +/// )] +/// pub struct ExampleStruct; +/// ``` +#[proc_macro_attribute] +pub fn hal_docs(args: TokenStream, input: TokenStream) -> TokenStream { + hal_docs_impl(args, input).unwrap_or_else(|e| e.to_compile_error("hal_docs")) +} + +fn hal_docs_impl(args: TokenStream, input: TokenStream) -> Result { + let mut args = args.into_iter().peekable(); + let args = &mut args; + + let mut out = TokenStream::new(); + + while args.peek().is_some() { + let mut attribute_formatter = None; + + if !matches!(args.peek(), Some(TokenTree::Group(_))) { + let expr = eat_hal_expr(args)?; + eat_operator("=>", args)?; + + let mut cfg_args = cfg_args(hal_expr_to_devices(&expr)?); + cfg_args.push(TokenTree::Punct(Punct::new(',', Spacing::Alone))); + attribute_formatter = Some(move |attribute_body: TokenStream| { + TokenStream::from_iter([ + TokenTree::Ident(Ident::new("cfg_attr", Span::call_site())), + TokenTree::Group(Group::new( + Delimiter::Parenthesis, + TokenStream::from_iter(cfg_args.iter().cloned().chain(attribute_body)), + )), + ]) + }); + } + + let group = eat_group(Delimiter::Brace, args)?; + let mut items = group.stream().into_iter().peekable(); + + while items.peek().is_some() { + let mut attribute = eat_attribute(&mut items)?; + if let Some(attribute_formatter) = &mut attribute_formatter { + attribute.inner_stream = attribute_formatter(attribute.inner_stream); + } + out.extend([ + attribute.pound, + TokenTree::Group(Group::new(Delimiter::Bracket, attribute.inner_stream)), + ]) + } + } + eat_eof(args)?; + + out.extend(input); + + Ok(out) +} diff --git a/atsamd-hal-macros/src/parsing.rs b/atsamd-hal-macros/src/parsing.rs new file mode 100644 index 00000000000..5b2da534d2d --- /dev/null +++ b/atsamd-hal-macros/src/parsing.rs @@ -0,0 +1,152 @@ +use std::borrow::Cow; + +use proc_macro::{Delimiter, Group, Spacing, TokenStream, TokenTree}; + +use crate::error::Error; + +pub fn eat_operator(s: &str, args: &mut impl Iterator) -> Result<(), Error> { + let mut chars = s.chars().peekable(); + + macro_rules! bail { + () => { + return Err(Error::GenericParseError { + expected: format!("operator {s:?}"), + }) + }; + } + + while let Some(c) = chars.next() { + let Some(TokenTree::Punct(punct)) = args.next() else { + bail!(); + }; + + if punct.as_char() != c { + bail!() + } + + match (chars.peek().is_some(), punct.spacing()) { + (true, Spacing::Alone) => bail!(), + (false, Spacing::Joint) => bail!(), + _ => (), + } + } + + Ok(()) +} + +pub fn eat_string_literal( + args: &mut impl Iterator, +) -> Result, Error> { + let Some(lit) = args.next() else { + return Err(Error::GenericParseError { + expected: "string literal".to_string(), + }); + }; + + Ok(litrs::StringLit::try_from(lit) + .map_err(|_| Error::GenericParseError { + expected: "string literal".to_string(), + })? + .into_value()) +} + +pub fn eat_group( + delimiter: Delimiter, + args: &mut impl Iterator, +) -> Result { + let err = || Error::GenericParseError { + expected: format!("group with delimiter {delimiter:?}"), + }; + + let Some(TokenTree::Group(group)) = args.next() else { + return Err(err()); + }; + + (group.delimiter() == delimiter) + .then_some(group) + .ok_or_else(err) +} + +pub struct Attribute { + pub pound: TokenTree, + pub inner_stream: TokenStream, +} + +pub fn eat_attribute(args: &mut impl Iterator) -> Result { + macro_rules! bail { + () => { + return Err(Error::GenericParseError { + expected: "attribute".to_string(), + }) + }; + } + + let Some(TokenTree::Punct(punct)) = args.next() else { + bail!(); + }; + + if punct.as_char() != '#' { + bail!(); + } + + let group = eat_group(Delimiter::Bracket, args)?; + + Ok(Attribute { + pound: TokenTree::Punct(punct), + inner_stream: group.stream(), + }) +} + +pub fn eat_eof(args: &mut impl Iterator) -> Result<(), Error> { + if args.next().is_none() { + Ok(()) + } else { + Err(Error::GenericParseError { + expected: "EOF".to_string(), + }) + } +} + +pub enum HalExpr { + All(Vec), + Any(Vec), + Peripheral(std::borrow::Cow<'static, str>), +} + +pub fn eat_hal_expr(expr: &mut impl Iterator) -> Result { + match expr.next() { + Some(TokenTree::Ident(ident)) => { + let variant: Option _> = match ident.to_string().as_str() { + "all" => Some(HalExpr::All), + "any" => Some(HalExpr::Any), + _ => None, + }; + if let Some(variant) = variant { + if let Some(TokenTree::Group(group)) = expr.next() { + if group.delimiter() == Delimiter::Parenthesis { + let mut inner = Vec::new(); + let mut args = group.stream().into_iter().peekable(); + while args.peek().is_some() { + inner.push(eat_hal_expr(&mut args)?); + if args.peek().is_none() { + break; + } + eat_operator(",", &mut args)?; + } + eat_eof(&mut args)?; + return Ok(variant(inner)); + } + } + } + } + Some(TokenTree::Literal(lit)) => { + if let Ok(string_lit) = litrs::StringLit::try_from(lit) { + return Ok(HalExpr::Peripheral(string_lit.into_value())); + } + } + _ => (), + } + Err(Error::GenericParseError { + expected: "a string literal or an any()/all() expression".to_string(), + }) +} From b85a115097f96bec037c89e89fea3f3bf7d40639 Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 10:41:45 +0100 Subject: [PATCH 02/11] Replace some cfg_attr docs with normal docstrings, since the outer-attribute style will not be supported by our proc-macro --- hal/src/dmac/channel/mod.rs | 24 +++++++-------- hal/src/sercom/i2c.rs | 4 +-- hal/src/sercom/mod.rs | 54 ++++++++++++++++----------------- hal/src/sercom/pad.rs | 20 +++++-------- hal/src/sercom/spi.rs | 59 +++++++++++++++---------------------- hal/src/sercom/uart.rs | 27 +++++++---------- 6 files changed, 80 insertions(+), 108 deletions(-) diff --git a/hal/src/dmac/channel/mod.rs b/hal/src/dmac/channel/mod.rs index cd555e5741d..285588acc4f 100644 --- a/hal/src/dmac/channel/mod.rs +++ b/hal/src/dmac/channel/mod.rs @@ -7,19 +7,17 @@ //! use by a [`Transfer`](super::transfer::Transfer). Initializing a channel //! requires setting a priority level, as well as enabling or disabling //! interrupt requests (only for the specific channel being initialized). -#![cfg_attr( - feature = "thumbv7", - doc = "# Burst Length and FIFO Threshold (SAMD51/SAME5x only) - -The transfer burst length can be configured through the -[`Channel::burst_length`] method. A burst is an atomic, -uninterruptible transfer which length corresponds to a number of beats. See -SAMD5x/E5x datasheet section 22.6.1.1 for more information. The FIFO -threshold can be configured through the -[`Channel::fifo_threshold`] method. This enables the channel -to wait for multiple Beats before sending a Burst. See SAMD5x/E5x datasheet -section 22.6.2.8 for more information." -)] +//! +//! # Burst Length and FIFO Threshold (SAMD51/SAME5x only) +//! +//! The transfer burst length can be configured through the +//! [`Channel::burst_length`] method. A burst is an atomic, +//! uninterruptible transfer which length corresponds to a number of beats. See +//! SAMD5x/E5x datasheet section 22.6.1.1 for more information. The FIFO +//! threshold can be configured through the +//! [`Channel::fifo_threshold`] method. This enables the channel +//! to wait for multiple Beats before sending a Burst. See SAMD5x/E5x datasheet +//! section 22.6.2.8 for more information. //! //! # Channel status //! diff --git a/hal/src/sercom/i2c.rs b/hal/src/sercom/i2c.rs index 64e9225132a..24c036b48aa 100644 --- a/hal/src/sercom/i2c.rs +++ b/hal/src/sercom/i2c.rs @@ -212,11 +212,11 @@ implements the DMAC [`Buffer`] trait. The provided [`send_with_dma`] and [`receive_with_dma`] build and begin a [`dmac::Transfer`], thus starting the I2C -in a non-blocking way. +in a non-blocking way. Note that the [`init_dma_transfer`] method should be called immediately before starting a DMA transfer with I2C. This will check that the bus is in a correct -state before starting the transfer, and providing a token type to pass to the +state before starting the transfer, and providing a token type to pass to the [`send_with_dma`] and [`receive_with_dma`] methods. Optionally, interrupts can be enabled on the provided diff --git a/hal/src/sercom/mod.rs b/hal/src/sercom/mod.rs index a1d2d0a04ae..cfeca08a18e 100644 --- a/hal/src/sercom/mod.rs +++ b/hal/src/sercom/mod.rs @@ -2,34 +2,32 @@ //! //! The SERCOM module is used to configure the SERCOM peripherals as USART, SPI //! or I2C interfaces. -#![cfg_attr( - feature = "thumbv7", - doc = " -# Undocumented features - -The ATSAMx5x chips contain certain features that aren't documented in the datasheet. -These features are implemented in the HAL based on experimentation with certain boards -which have verifiably demonstrated that those features work as intended. - -* [`UndocIoSet1`](pad::UndocIoSet1): Implement an undocumented `IoSet` for PA16, PA17, -PB22 & PB23 configured for [`Sercom1`]. The pygamer & feather_m4 use this combination, -but it is not listed as valid in the datasheet. - -* [`UndocIoSet2`](pad::UndocIoSet2): Implement an undocumented `IoSet` for PA00, PA01, -PB22 & PB23 configured for [`Sercom1`]. The itsybitsy_m4 uses this combination, but it is -not listed as valid in the datasheet. - -* [`PB02`] is I2C-capable according to metro_m4. As such, [`PB02`] -implements [`IsI2cPad`]. - -* [`PB03`] is I2C-capable according to metro_m4. As such, [`PB03`] -implements [`IsI2cPad`](pad::IsI2cPad). - -[`PB02`]: crate::gpio::pin::PB02 -[`PB03`]: crate::gpio::pin::PB03 -[`IsI2cPad`]: pad::IsI2cPad -" -)] +//! # Undocumented features +//! +//! The ATSAMx5x chips contain certain features that aren't documented in the +//! datasheet. These features are implemented in the HAL based on +//! experimentation with certain boards which have verifiably demonstrated that +//! those features work as intended. +//! +//! * [`UndocIoSet1`](pad::UndocIoSet1): Implement an undocumented `IoSet` for +//! PA16, PA17, +//! PB22 & PB23 configured for [`Sercom1`]. The pygamer & feather_m4 use this +//! combination, but it is not listed as valid in the datasheet. +//! +//! * [`UndocIoSet2`](pad::UndocIoSet2): Implement an undocumented `IoSet` for +//! PA00, PA01, +//! PB22 & PB23 configured for [`Sercom1`]. The itsybitsy_m4 uses this +//! combination, but it is not listed as valid in the datasheet. +//! +//! * [`PB02`] is I2C-capable according to metro_m4. As such, [`PB02`] +//! implements [`IsI2cPad`]. +//! +//! * [`PB03`] is I2C-capable according to metro_m4. As such, [`PB03`] +//! implements [`IsI2cPad`](pad::IsI2cPad). +//! +//! [`PB02`]: crate::gpio::pin::PB02 +//! [`PB03`]: crate::gpio::pin::PB03 +//! [`IsI2cPad`]: pad::IsI2cPad use core::ops::Deref; diff --git a/hal/src/sercom/pad.rs b/hal/src/sercom/pad.rs index feb29dd5df6..45589c71d97 100644 --- a/hal/src/sercom/pad.rs +++ b/hal/src/sercom/pad.rs @@ -25,19 +25,13 @@ //! [`AlternateD`]: crate::gpio::AlternateD //! [type class]: crate::typelevel#type-classes //! [type-level function]: crate::typelevel#type-level-functions -#![cfg_attr( - feature = "thumbv7", - doc = " -# IOSET\n -\n -SAMx5x chips do not allow arbitrary combinations of `PinId` for a given -SERCOM. Instead, all `PinId`s must belong to the same IOSET. This module -defines a [type-level enum], [`IoSet`], to enforce this restriction, and the -[`InIoSet`] [type class] is responsible for labeling each `IsPad` type with -its corresponding, valid `IoSet`\\(s).\n -\n -" -)] +//! # IOSET (SAMD51/SAME5x only) +//! +//! SAMx5x chips do not allow arbitrary combinations of `PinId` for a given +//! SERCOM. Instead, all `PinId`s must belong to the same IOSET. This module +//! defines a [type-level enum], [`IoSet`], to enforce this restriction, and the +//! [`InIoSet`] [type class] is responsible for labeling each `IsPad` type with +//! its corresponding, valid `IoSet`\(s). use paste::paste; use seq_macro::seq; diff --git a/hal/src/sercom/spi.rs b/hal/src/sercom/spi.rs index e48ad505d3b..e7d21c548f8 100644 --- a/hal/src/sercom/spi.rs +++ b/hal/src/sercom/spi.rs @@ -14,8 +14,7 @@ //! An SPI peripheral can use up to four [`Pin`]s as [`Sercom`] pads. However, //! only certain `Pin` combinations are acceptable. All `Pin`s must be mapped to //! the same `Sercom`, and for SAMx5x chips, they must also belong to the same -#![cfg_attr(feature = "thumbv6", doc = "`IoSet`.")] -#![cfg_attr(feature = "thumbv7", doc = "[`IoSet`].")] +//! `IoSet`. //! This HAL makes it impossible to use invalid `Pin` combinations, and the //! [`Pads`] struct is responsible for enforcing these constraints. //! @@ -50,28 +49,25 @@ //! [`Pin`]: crate::gpio::pin::Pin //! [`PinId`]: crate::gpio::pin::PinId //! [`PinMode`]: crate::gpio::pin::PinMode -#![cfg_attr( - not(feature = "samd11"), - doc = " -Alternatively, you can use the `PadsFromIds` alias to define a set of -`Pads` in terms of [`PinId`]s instead of [`Pin`]s. This is useful when you -don't have [`Pin`] aliases pre-defined. - -``` -use atsamd_hal::gpio::{PA08, PA09}; -use atsamd_hal::sercom::{Sercom0, spi}; -use atsamd_hal::typelevel::NoneT; - -// SAMx5x-specific imports -use atsamd_hal::sercom::pad::IoSet1; - -// SAMD21 version -type Pads = spi::PadsFromIds; -// SAMx5x version -type Pads = spi::PadsFromIds; -``` -" -)] +//! +//! +//! Alternatively, you can use the `PadsFromIds` alias to define a set of +//! `Pads` in terms of [`PinId`]s instead of [`Pin`]s. This is useful when you +//! don't have [`Pin`] aliases pre-defined. +//! +//! ``` +//! use atsamd_hal::gpio::{PA08, PA09}; +//! use atsamd_hal::sercom::{Sercom0, spi}; +//! use atsamd_hal::typelevel::NoneT; +//! +//! // SAMx5x-specific imports +//! use atsamd_hal::sercom::pad::IoSet1; +//! +//! // SAMD21 version +//! type Pads = spi::PadsFromIds; +//! // SAMx5x version +//! type Pads = spi::PadsFromIds; +//! ``` //! //! Instances of `Pads` are created using the builder pattern. Start by creating //! an empty set of `Pads` using [`Default`]. Then pass each respective `Pin` @@ -115,21 +111,12 @@ type Pads = spi::PadsFromIds; //! [`Pads`] type; an [`OpMode`], which defaults to [`Master`]; and a //! [`Size`] type that varies by chip. [`Size`] essentially acts as a trait //! alias. On SAMD11 and SAMD21 chips, it represents the -#![cfg_attr( - feature = "thumbv6", - doc = "[`CharSize`], which can either be [`EightBit`] or [`NineBit`]. " -)] -#![cfg_attr( - feature = "thumbv7", - doc = "`CharSize`, which can either be `EightBit` or `NineBit`. " -)] +//! `CharSize`, which can either be `EightBit` or `NineBit`. //! While on SAMx5x chips, it represents the transaction -#![cfg_attr(feature = "thumbv6", doc = "`Length`")] -#![cfg_attr(feature = "thumbv7", doc = "[`Length`]")] +//! `Length` //! in bytes, using type-level numbers provided by the [`typenum`] crate. Valid //! transaction lengths, from `U1` to `U255`, are re-exported in the -#![cfg_attr(feature = "thumbv6", doc = "`lengths`")] -#![cfg_attr(feature = "thumbv7", doc = "[`lengths`]")] +//! `lengths` //! sub-module. //! //! ``` diff --git a/hal/src/sercom/uart.rs b/hal/src/sercom/uart.rs index 77813190291..0f4dac6a9f4 100644 --- a/hal/src/sercom/uart.rs +++ b/hal/src/sercom/uart.rs @@ -34,22 +34,17 @@ //! type Tx = Pin; //! type Pads = uart::Pads; //! ``` -#![cfg_attr( - not(feature = "samd11"), - doc = " -Alternatively, you can use the [`PadsFromIds`] alias to define a set of -`Pads` in terms of [`PinId`]s instead of `Pin`s. This is useful when you -don't have [`Pin`] aliases pre-defined. - -``` -use atsamd_hal::gpio::{PA08, PA09}; -use atsamd_hal::sercom::{Sercom0, uart}; - -type Pads = uart::PadsFromIds; -``` - -" -)] +//! +//! Alternatively, you can use the [`PadsFromIds`] alias to define a set of +//! `Pads` in terms of [`PinId`]s instead of `Pin`s. This is useful when you +//! don't have [`Pin`] aliases pre-defined. +//! +//! ``` +//! use atsamd_hal::gpio::{PA08, PA09}; +//! use atsamd_hal::sercom::{Sercom0, uart}; +//! +//! type Pads = uart::PadsFromIds; +//! ``` //! //! Instances of [`Pads`] are created using the builder pattern. Start by //! creating an empty set of [`Pads`] using [`Default`]. Then pass each From a065246f96c2c25c97ed287f1e5353b1f601dd5e Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 13:38:58 +0100 Subject: [PATCH 03/11] Use the feature names in "define_pac!()" instead of the crate names --- hal/src/lib.rs | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/hal/src/lib.rs b/hal/src/lib.rs index 7a53ac6ef82..50ce5fb2158 100644 --- a/hal/src/lib.rs +++ b/hal/src/lib.rs @@ -28,22 +28,24 @@ macro_rules! define_pac { } define_pac!( - (atsamd11c, "atsamd11c"), - (atsamd11d, "atsamd11d"), - (atsamd21e, "atsamd21e"), - (atsamd21g, "atsamd21g"), - (atsamd21j, "atsamd21j"), - (atsamd51g, "atsamd51g"), - (atsamd51j, "atsamd51j"), - (atsamd51n, "atsamd51n"), - (atsamd51p, "atsamd51p"), - (atsame51g, "atsame51g"), - (atsame51j, "atsame51j"), - (atsame51n, "atsame51n"), - (atsame53j, "atsame53j"), - (atsame53n, "atsame53n"), - (atsame54n, "atsame54n"), - (atsame54p, "atsame54p") + (atsamd11c, "samd11c"), + (atsamd11d, "samd11d"), + (atsamd21e, "samd21e"), + (atsamd21g, "samd21g"), + (atsamd21j, "samd21j"), + (atsamd21e, "samd21el"), + (atsamd21g, "samd21gl"), + (atsamd51g, "samd51g"), + (atsamd51j, "samd51j"), + (atsamd51n, "samd51n"), + (atsamd51p, "samd51p"), + (atsame51g, "same51g"), + (atsame51j, "same51j"), + (atsame51n, "same51n"), + (atsame53j, "same53j"), + (atsame53n, "same53n"), + (atsame54n, "same54n"), + (atsame54p, "same54p") ); #[cfg(feature = "use_rtt")] From 2b27578eb5d348c7e79505261d38298de7a9bbdd Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 11:27:58 +0100 Subject: [PATCH 04/11] Split up the thumbv6m and thumbv7em directories by peripheral instead of by architecture --- hal/src/lib.rs | 13 +--- .../adc.rs => peripherals/adc/d11.rs} | 0 .../adc.rs => peripherals/adc/d5x.rs} | 0 .../aes.rs => peripherals/aes/mod.rs} | 0 .../aes/rustcrypto.rs | 0 .../aes/rustcrypto/decrypt.rs | 0 .../aes/rustcrypto/encrypt.rs | 0 .../calibration/d11.rs} | 0 .../calibration/d5x.rs} | 0 hal/src/{thumbv7em => peripherals}/can.rs | 0 .../clock.rs => peripherals/clock/d11.rs} | 0 .../clock.rs => peripherals/clock/d5x/mod.rs} | 0 .../clock => peripherals/clock/d5x}/v1.rs | 0 .../clock => peripherals/clock/d5x}/v2.rs | 0 .../clock => peripherals/clock/d5x}/v2/ahb.rs | 0 .../clock => peripherals/clock/d5x}/v2/apb.rs | 0 .../clock/d5x}/v2/dfll.rs | 0 .../clock/d5x}/v2/dpll.rs | 0 .../clock/d5x}/v2/gclk.rs | 0 .../clock/d5x}/v2/osculp32k.rs | 0 .../clock/d5x}/v2/pclk.rs | 0 .../clock/d5x}/v2/reset.rs | 0 .../clock/d5x}/v2/rtcosc.rs | 0 .../clock/d5x}/v2/types.rs | 0 .../clock/d5x}/v2/xosc.rs | 0 .../clock/d5x}/v2/xosc32k.rs | 0 hal/src/{thumbv7em => peripherals}/dsu.rs | 0 .../eic => peripherals/eic/d11}/mod.rs | 0 .../eic => peripherals/eic/d11}/pin.rs | 0 .../eic => peripherals/eic/d5x}/mod.rs | 0 .../eic => peripherals/eic/d5x}/pin.rs | 0 hal/src/{thumbv7em => peripherals}/icm.rs | 0 hal/src/peripherals/mod.rs | 76 +++++++++++++++++++ .../nvm.rs => peripherals/nvm/mod.rs} | 0 .../nvm/smart_eeprom.rs | 0 .../{thumbv7em => peripherals}/pukcc/c_abi.rs | 0 .../pukcc/curves.rs | 0 .../pukcc.rs => peripherals/pukcc/mod.rs} | 0 .../pwm.rs => peripherals/pwm/d11.rs} | 0 .../pwm.rs => peripherals/pwm/d5x.rs} | 0 hal/src/{thumbv7em => peripherals}/qspi.rs | 0 .../reset_cause/d11.rs} | 0 .../reset_cause/d5x.rs} | 0 .../serial_number/d11.rs} | 0 .../serial_number/d5x.rs} | 0 .../timer.rs => peripherals/timer/d11.rs} | 0 .../timer.rs => peripherals/timer/d5x.rs} | 0 hal/src/{thumbv7em => peripherals}/trng.rs | 0 .../usb => peripherals/usb/d11}/bus.rs | 0 .../usb => peripherals/usb/d11}/devicedesc.rs | 0 .../usb => peripherals/usb/d11}/mod.rs | 0 .../usb => peripherals/usb/d5x}/bus.rs | 0 .../usb => peripherals/usb/d5x}/devicedesc.rs | 0 .../usb => peripherals/usb/d5x}/mod.rs | 0 .../watchdog/d11.rs} | 0 .../watchdog/d5x.rs} | 0 hal/src/thumbv6m/mod.rs | 23 ------ hal/src/thumbv7em/mod.rs | 34 --------- 58 files changed, 78 insertions(+), 68 deletions(-) rename hal/src/{thumbv6m/adc.rs => peripherals/adc/d11.rs} (100%) rename hal/src/{thumbv7em/adc.rs => peripherals/adc/d5x.rs} (100%) rename hal/src/{thumbv7em/aes.rs => peripherals/aes/mod.rs} (100%) rename hal/src/{thumbv7em => peripherals}/aes/rustcrypto.rs (100%) rename hal/src/{thumbv7em => peripherals}/aes/rustcrypto/decrypt.rs (100%) rename hal/src/{thumbv7em => peripherals}/aes/rustcrypto/encrypt.rs (100%) rename hal/src/{thumbv6m/calibration.rs => peripherals/calibration/d11.rs} (100%) rename hal/src/{thumbv7em/calibration.rs => peripherals/calibration/d5x.rs} (100%) rename hal/src/{thumbv7em => peripherals}/can.rs (100%) rename hal/src/{thumbv6m/clock.rs => peripherals/clock/d11.rs} (100%) rename hal/src/{thumbv7em/clock.rs => peripherals/clock/d5x/mod.rs} (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v1.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/ahb.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/apb.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/dfll.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/dpll.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/gclk.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/osculp32k.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/pclk.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/reset.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/rtcosc.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/types.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/xosc.rs (100%) rename hal/src/{thumbv7em/clock => peripherals/clock/d5x}/v2/xosc32k.rs (100%) rename hal/src/{thumbv7em => peripherals}/dsu.rs (100%) rename hal/src/{thumbv6m/eic => peripherals/eic/d11}/mod.rs (100%) rename hal/src/{thumbv6m/eic => peripherals/eic/d11}/pin.rs (100%) rename hal/src/{thumbv7em/eic => peripherals/eic/d5x}/mod.rs (100%) rename hal/src/{thumbv7em/eic => peripherals/eic/d5x}/pin.rs (100%) rename hal/src/{thumbv7em => peripherals}/icm.rs (100%) create mode 100644 hal/src/peripherals/mod.rs rename hal/src/{thumbv7em/nvm.rs => peripherals/nvm/mod.rs} (100%) rename hal/src/{thumbv7em => peripherals}/nvm/smart_eeprom.rs (100%) rename hal/src/{thumbv7em => peripherals}/pukcc/c_abi.rs (100%) rename hal/src/{thumbv7em => peripherals}/pukcc/curves.rs (100%) rename hal/src/{thumbv7em/pukcc.rs => peripherals/pukcc/mod.rs} (100%) rename hal/src/{thumbv6m/pwm.rs => peripherals/pwm/d11.rs} (100%) rename hal/src/{thumbv7em/pwm.rs => peripherals/pwm/d5x.rs} (100%) rename hal/src/{thumbv7em => peripherals}/qspi.rs (100%) rename hal/src/{thumbv6m/reset_cause.rs => peripherals/reset_cause/d11.rs} (100%) rename hal/src/{thumbv7em/reset_cause.rs => peripherals/reset_cause/d5x.rs} (100%) rename hal/src/{thumbv6m/serial_number.rs => peripherals/serial_number/d11.rs} (100%) rename hal/src/{thumbv7em/serial_number.rs => peripherals/serial_number/d5x.rs} (100%) rename hal/src/{thumbv6m/timer.rs => peripherals/timer/d11.rs} (100%) rename hal/src/{thumbv7em/timer.rs => peripherals/timer/d5x.rs} (100%) rename hal/src/{thumbv7em => peripherals}/trng.rs (100%) rename hal/src/{thumbv6m/usb => peripherals/usb/d11}/bus.rs (100%) rename hal/src/{thumbv6m/usb => peripherals/usb/d11}/devicedesc.rs (100%) rename hal/src/{thumbv6m/usb => peripherals/usb/d11}/mod.rs (100%) rename hal/src/{thumbv7em/usb => peripherals/usb/d5x}/bus.rs (100%) rename hal/src/{thumbv7em/usb => peripherals/usb/d5x}/devicedesc.rs (100%) rename hal/src/{thumbv7em/usb => peripherals/usb/d5x}/mod.rs (100%) rename hal/src/{thumbv6m/watchdog.rs => peripherals/watchdog/d11.rs} (100%) rename hal/src/{thumbv7em/watchdog.rs => peripherals/watchdog/d5x.rs} (100%) delete mode 100644 hal/src/thumbv6m/mod.rs delete mode 100644 hal/src/thumbv7em/mod.rs diff --git a/hal/src/lib.rs b/hal/src/lib.rs index 50ce5fb2158..6a63c54f88b 100644 --- a/hal/src/lib.rs +++ b/hal/src/lib.rs @@ -90,19 +90,10 @@ pub mod dmac; #[cfg(all(feature = "usb", feature = "device", not(feature = "has-usb")))] compile_error!("The 'usb' feature is enabled, but this chip does not support USB"); -#[cfg(feature = "thumbv6")] #[doc(hidden)] -pub mod thumbv6m; -#[cfg(feature = "thumbv6")] +mod peripherals; #[doc(inline)] -pub use crate::thumbv6m::*; - -#[cfg(feature = "thumbv7")] -#[doc(hidden)] -pub mod thumbv7em; -#[cfg(feature = "thumbv7")] -#[doc(inline)] -pub use crate::thumbv7em::*; +pub use crate::peripherals::*; #[macro_use] mod bsp_peripherals_macro; diff --git a/hal/src/thumbv6m/adc.rs b/hal/src/peripherals/adc/d11.rs similarity index 100% rename from hal/src/thumbv6m/adc.rs rename to hal/src/peripherals/adc/d11.rs diff --git a/hal/src/thumbv7em/adc.rs b/hal/src/peripherals/adc/d5x.rs similarity index 100% rename from hal/src/thumbv7em/adc.rs rename to hal/src/peripherals/adc/d5x.rs diff --git a/hal/src/thumbv7em/aes.rs b/hal/src/peripherals/aes/mod.rs similarity index 100% rename from hal/src/thumbv7em/aes.rs rename to hal/src/peripherals/aes/mod.rs diff --git a/hal/src/thumbv7em/aes/rustcrypto.rs b/hal/src/peripherals/aes/rustcrypto.rs similarity index 100% rename from hal/src/thumbv7em/aes/rustcrypto.rs rename to hal/src/peripherals/aes/rustcrypto.rs diff --git a/hal/src/thumbv7em/aes/rustcrypto/decrypt.rs b/hal/src/peripherals/aes/rustcrypto/decrypt.rs similarity index 100% rename from hal/src/thumbv7em/aes/rustcrypto/decrypt.rs rename to hal/src/peripherals/aes/rustcrypto/decrypt.rs diff --git a/hal/src/thumbv7em/aes/rustcrypto/encrypt.rs b/hal/src/peripherals/aes/rustcrypto/encrypt.rs similarity index 100% rename from hal/src/thumbv7em/aes/rustcrypto/encrypt.rs rename to hal/src/peripherals/aes/rustcrypto/encrypt.rs diff --git a/hal/src/thumbv6m/calibration.rs b/hal/src/peripherals/calibration/d11.rs similarity index 100% rename from hal/src/thumbv6m/calibration.rs rename to hal/src/peripherals/calibration/d11.rs diff --git a/hal/src/thumbv7em/calibration.rs b/hal/src/peripherals/calibration/d5x.rs similarity index 100% rename from hal/src/thumbv7em/calibration.rs rename to hal/src/peripherals/calibration/d5x.rs diff --git a/hal/src/thumbv7em/can.rs b/hal/src/peripherals/can.rs similarity index 100% rename from hal/src/thumbv7em/can.rs rename to hal/src/peripherals/can.rs diff --git a/hal/src/thumbv6m/clock.rs b/hal/src/peripherals/clock/d11.rs similarity index 100% rename from hal/src/thumbv6m/clock.rs rename to hal/src/peripherals/clock/d11.rs diff --git a/hal/src/thumbv7em/clock.rs b/hal/src/peripherals/clock/d5x/mod.rs similarity index 100% rename from hal/src/thumbv7em/clock.rs rename to hal/src/peripherals/clock/d5x/mod.rs diff --git a/hal/src/thumbv7em/clock/v1.rs b/hal/src/peripherals/clock/d5x/v1.rs similarity index 100% rename from hal/src/thumbv7em/clock/v1.rs rename to hal/src/peripherals/clock/d5x/v1.rs diff --git a/hal/src/thumbv7em/clock/v2.rs b/hal/src/peripherals/clock/d5x/v2.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2.rs rename to hal/src/peripherals/clock/d5x/v2.rs diff --git a/hal/src/thumbv7em/clock/v2/ahb.rs b/hal/src/peripherals/clock/d5x/v2/ahb.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/ahb.rs rename to hal/src/peripherals/clock/d5x/v2/ahb.rs diff --git a/hal/src/thumbv7em/clock/v2/apb.rs b/hal/src/peripherals/clock/d5x/v2/apb.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/apb.rs rename to hal/src/peripherals/clock/d5x/v2/apb.rs diff --git a/hal/src/thumbv7em/clock/v2/dfll.rs b/hal/src/peripherals/clock/d5x/v2/dfll.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/dfll.rs rename to hal/src/peripherals/clock/d5x/v2/dfll.rs diff --git a/hal/src/thumbv7em/clock/v2/dpll.rs b/hal/src/peripherals/clock/d5x/v2/dpll.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/dpll.rs rename to hal/src/peripherals/clock/d5x/v2/dpll.rs diff --git a/hal/src/thumbv7em/clock/v2/gclk.rs b/hal/src/peripherals/clock/d5x/v2/gclk.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/gclk.rs rename to hal/src/peripherals/clock/d5x/v2/gclk.rs diff --git a/hal/src/thumbv7em/clock/v2/osculp32k.rs b/hal/src/peripherals/clock/d5x/v2/osculp32k.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/osculp32k.rs rename to hal/src/peripherals/clock/d5x/v2/osculp32k.rs diff --git a/hal/src/thumbv7em/clock/v2/pclk.rs b/hal/src/peripherals/clock/d5x/v2/pclk.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/pclk.rs rename to hal/src/peripherals/clock/d5x/v2/pclk.rs diff --git a/hal/src/thumbv7em/clock/v2/reset.rs b/hal/src/peripherals/clock/d5x/v2/reset.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/reset.rs rename to hal/src/peripherals/clock/d5x/v2/reset.rs diff --git a/hal/src/thumbv7em/clock/v2/rtcosc.rs b/hal/src/peripherals/clock/d5x/v2/rtcosc.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/rtcosc.rs rename to hal/src/peripherals/clock/d5x/v2/rtcosc.rs diff --git a/hal/src/thumbv7em/clock/v2/types.rs b/hal/src/peripherals/clock/d5x/v2/types.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/types.rs rename to hal/src/peripherals/clock/d5x/v2/types.rs diff --git a/hal/src/thumbv7em/clock/v2/xosc.rs b/hal/src/peripherals/clock/d5x/v2/xosc.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/xosc.rs rename to hal/src/peripherals/clock/d5x/v2/xosc.rs diff --git a/hal/src/thumbv7em/clock/v2/xosc32k.rs b/hal/src/peripherals/clock/d5x/v2/xosc32k.rs similarity index 100% rename from hal/src/thumbv7em/clock/v2/xosc32k.rs rename to hal/src/peripherals/clock/d5x/v2/xosc32k.rs diff --git a/hal/src/thumbv7em/dsu.rs b/hal/src/peripherals/dsu.rs similarity index 100% rename from hal/src/thumbv7em/dsu.rs rename to hal/src/peripherals/dsu.rs diff --git a/hal/src/thumbv6m/eic/mod.rs b/hal/src/peripherals/eic/d11/mod.rs similarity index 100% rename from hal/src/thumbv6m/eic/mod.rs rename to hal/src/peripherals/eic/d11/mod.rs diff --git a/hal/src/thumbv6m/eic/pin.rs b/hal/src/peripherals/eic/d11/pin.rs similarity index 100% rename from hal/src/thumbv6m/eic/pin.rs rename to hal/src/peripherals/eic/d11/pin.rs diff --git a/hal/src/thumbv7em/eic/mod.rs b/hal/src/peripherals/eic/d5x/mod.rs similarity index 100% rename from hal/src/thumbv7em/eic/mod.rs rename to hal/src/peripherals/eic/d5x/mod.rs diff --git a/hal/src/thumbv7em/eic/pin.rs b/hal/src/peripherals/eic/d5x/pin.rs similarity index 100% rename from hal/src/thumbv7em/eic/pin.rs rename to hal/src/peripherals/eic/d5x/pin.rs diff --git a/hal/src/thumbv7em/icm.rs b/hal/src/peripherals/icm.rs similarity index 100% rename from hal/src/thumbv7em/icm.rs rename to hal/src/peripherals/icm.rs diff --git a/hal/src/peripherals/mod.rs b/hal/src/peripherals/mod.rs new file mode 100644 index 00000000000..8ee8780d941 --- /dev/null +++ b/hal/src/peripherals/mod.rs @@ -0,0 +1,76 @@ +#[cfg(feature = "unproven")] +#[cfg_attr(feature = "thumbv6", path = "adc/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "adc/d5x.rs")] +pub mod adc; + +#[cfg_attr(feature = "thumbv6", path = "calibration/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "calibration/d5x.rs")] +pub mod calibration; + +#[cfg_attr(feature = "thumbv6", path = "timer/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "timer/d5x.rs")] +pub mod timer; + +#[cfg_attr(feature = "thumbv6", path = "eic/d11/mod.rs")] +#[cfg_attr(feature = "thumbv7", path = "eic/d5x/mod.rs")] +pub mod eic; + +#[cfg(all(feature = "usb", feature = "has-usb"))] +#[cfg_attr(feature = "thumbv6", path = "usb/d11/mod.rs")] +#[cfg_attr(feature = "thumbv7", path = "usb/d5x/mod.rs")] +pub mod usb; + +#[cfg(feature = "unproven")] +#[cfg_attr(feature = "thumbv6", path = "pwm/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "pwm/d5x.rs")] +pub mod pwm; + +#[cfg_attr(feature = "thumbv6", path = "clock/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "clock/d5x/mod.rs")] +pub mod clock; + +#[cfg(feature = "thumbv7")] +pub mod aes; + +#[cfg(feature = "thumbv7")] +pub mod dsu; + +#[cfg(feature = "thumbv7")] +pub mod pukcc; + +#[cfg(feature = "thumbv7")] +pub mod qspi; + +#[cfg(feature = "thumbv7")] +pub mod trng; + +#[cfg(feature = "unproven")] +#[cfg(feature = "thumbv7")] +pub mod icm; + +#[cfg(feature = "thumbv7")] +pub mod nvm; + +#[cfg(all( + any(feature = "has-can0", feature = "has-can1"), + feature = "can", + feature = "thumbv7" +))] +pub mod can; + +#[cfg(feature = "unproven")] +#[cfg_attr(feature = "thumbv6", path = "watchdog/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "watchdog/d5x.rs")] +pub mod watchdog; + +#[cfg_attr(feature = "thumbv6", path = "reset_cause/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "reset_cause/d5x.rs")] +mod reset_cause; + +pub use reset_cause::*; + +#[cfg_attr(feature = "thumbv6", path = "serial_number/d11.rs")] +#[cfg_attr(feature = "thumbv7", path = "serial_number/d5x.rs")] +mod serial_number; + +pub use serial_number::*; diff --git a/hal/src/thumbv7em/nvm.rs b/hal/src/peripherals/nvm/mod.rs similarity index 100% rename from hal/src/thumbv7em/nvm.rs rename to hal/src/peripherals/nvm/mod.rs diff --git a/hal/src/thumbv7em/nvm/smart_eeprom.rs b/hal/src/peripherals/nvm/smart_eeprom.rs similarity index 100% rename from hal/src/thumbv7em/nvm/smart_eeprom.rs rename to hal/src/peripherals/nvm/smart_eeprom.rs diff --git a/hal/src/thumbv7em/pukcc/c_abi.rs b/hal/src/peripherals/pukcc/c_abi.rs similarity index 100% rename from hal/src/thumbv7em/pukcc/c_abi.rs rename to hal/src/peripherals/pukcc/c_abi.rs diff --git a/hal/src/thumbv7em/pukcc/curves.rs b/hal/src/peripherals/pukcc/curves.rs similarity index 100% rename from hal/src/thumbv7em/pukcc/curves.rs rename to hal/src/peripherals/pukcc/curves.rs diff --git a/hal/src/thumbv7em/pukcc.rs b/hal/src/peripherals/pukcc/mod.rs similarity index 100% rename from hal/src/thumbv7em/pukcc.rs rename to hal/src/peripherals/pukcc/mod.rs diff --git a/hal/src/thumbv6m/pwm.rs b/hal/src/peripherals/pwm/d11.rs similarity index 100% rename from hal/src/thumbv6m/pwm.rs rename to hal/src/peripherals/pwm/d11.rs diff --git a/hal/src/thumbv7em/pwm.rs b/hal/src/peripherals/pwm/d5x.rs similarity index 100% rename from hal/src/thumbv7em/pwm.rs rename to hal/src/peripherals/pwm/d5x.rs diff --git a/hal/src/thumbv7em/qspi.rs b/hal/src/peripherals/qspi.rs similarity index 100% rename from hal/src/thumbv7em/qspi.rs rename to hal/src/peripherals/qspi.rs diff --git a/hal/src/thumbv6m/reset_cause.rs b/hal/src/peripherals/reset_cause/d11.rs similarity index 100% rename from hal/src/thumbv6m/reset_cause.rs rename to hal/src/peripherals/reset_cause/d11.rs diff --git a/hal/src/thumbv7em/reset_cause.rs b/hal/src/peripherals/reset_cause/d5x.rs similarity index 100% rename from hal/src/thumbv7em/reset_cause.rs rename to hal/src/peripherals/reset_cause/d5x.rs diff --git a/hal/src/thumbv6m/serial_number.rs b/hal/src/peripherals/serial_number/d11.rs similarity index 100% rename from hal/src/thumbv6m/serial_number.rs rename to hal/src/peripherals/serial_number/d11.rs diff --git a/hal/src/thumbv7em/serial_number.rs b/hal/src/peripherals/serial_number/d5x.rs similarity index 100% rename from hal/src/thumbv7em/serial_number.rs rename to hal/src/peripherals/serial_number/d5x.rs diff --git a/hal/src/thumbv6m/timer.rs b/hal/src/peripherals/timer/d11.rs similarity index 100% rename from hal/src/thumbv6m/timer.rs rename to hal/src/peripherals/timer/d11.rs diff --git a/hal/src/thumbv7em/timer.rs b/hal/src/peripherals/timer/d5x.rs similarity index 100% rename from hal/src/thumbv7em/timer.rs rename to hal/src/peripherals/timer/d5x.rs diff --git a/hal/src/thumbv7em/trng.rs b/hal/src/peripherals/trng.rs similarity index 100% rename from hal/src/thumbv7em/trng.rs rename to hal/src/peripherals/trng.rs diff --git a/hal/src/thumbv6m/usb/bus.rs b/hal/src/peripherals/usb/d11/bus.rs similarity index 100% rename from hal/src/thumbv6m/usb/bus.rs rename to hal/src/peripherals/usb/d11/bus.rs diff --git a/hal/src/thumbv6m/usb/devicedesc.rs b/hal/src/peripherals/usb/d11/devicedesc.rs similarity index 100% rename from hal/src/thumbv6m/usb/devicedesc.rs rename to hal/src/peripherals/usb/d11/devicedesc.rs diff --git a/hal/src/thumbv6m/usb/mod.rs b/hal/src/peripherals/usb/d11/mod.rs similarity index 100% rename from hal/src/thumbv6m/usb/mod.rs rename to hal/src/peripherals/usb/d11/mod.rs diff --git a/hal/src/thumbv7em/usb/bus.rs b/hal/src/peripherals/usb/d5x/bus.rs similarity index 100% rename from hal/src/thumbv7em/usb/bus.rs rename to hal/src/peripherals/usb/d5x/bus.rs diff --git a/hal/src/thumbv7em/usb/devicedesc.rs b/hal/src/peripherals/usb/d5x/devicedesc.rs similarity index 100% rename from hal/src/thumbv7em/usb/devicedesc.rs rename to hal/src/peripherals/usb/d5x/devicedesc.rs diff --git a/hal/src/thumbv7em/usb/mod.rs b/hal/src/peripherals/usb/d5x/mod.rs similarity index 100% rename from hal/src/thumbv7em/usb/mod.rs rename to hal/src/peripherals/usb/d5x/mod.rs diff --git a/hal/src/thumbv6m/watchdog.rs b/hal/src/peripherals/watchdog/d11.rs similarity index 100% rename from hal/src/thumbv6m/watchdog.rs rename to hal/src/peripherals/watchdog/d11.rs diff --git a/hal/src/thumbv7em/watchdog.rs b/hal/src/peripherals/watchdog/d5x.rs similarity index 100% rename from hal/src/thumbv7em/watchdog.rs rename to hal/src/peripherals/watchdog/d5x.rs diff --git a/hal/src/thumbv6m/mod.rs b/hal/src/thumbv6m/mod.rs deleted file mode 100644 index 075cab739ec..00000000000 --- a/hal/src/thumbv6m/mod.rs +++ /dev/null @@ -1,23 +0,0 @@ -pub mod eic; - -mod reset_cause; -pub use reset_cause::*; - -mod serial_number; -pub use serial_number::*; - -pub mod calibration; -pub mod clock; -pub mod timer; - -#[cfg(feature = "unproven")] -pub mod adc; - -#[cfg(feature = "unproven")] -pub mod pwm; - -#[cfg(feature = "unproven")] -pub mod watchdog; - -#[cfg(all(feature = "usb", feature = "has-usb"))] -pub mod usb; diff --git a/hal/src/thumbv7em/mod.rs b/hal/src/thumbv7em/mod.rs deleted file mode 100644 index b851479055d..00000000000 --- a/hal/src/thumbv7em/mod.rs +++ /dev/null @@ -1,34 +0,0 @@ -pub mod aes; -pub mod calibration; -#[cfg(all(any(feature = "has-can0", feature = "has-can1"), feature = "can"))] -pub mod can; -pub mod clock; -pub mod eic; -pub mod pukcc; -pub mod qspi; -pub mod timer; -pub mod trng; - -#[cfg(feature = "usb")] -pub mod usb; - -mod reset_cause; -pub use reset_cause::*; - -mod serial_number; -pub use serial_number::*; - -#[cfg(feature = "unproven")] -pub mod adc; - -#[cfg(feature = "unproven")] -pub mod pwm; - -#[cfg(feature = "unproven")] -pub mod watchdog; - -#[cfg(feature = "unproven")] -pub mod icm; - -pub mod dsu; -pub mod nvm; From cb942a919bcea427c77f9d59fef385102156caf8 Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 12:24:42 +0100 Subject: [PATCH 05/11] Replace most uses of `#[cfg()]` with `#[hal_cfg()]` --- hal/Cargo.toml | 1 + hal/src/dmac/channel/mod.rs | 18 +- hal/src/dmac/channel/reg.rs | 20 +- hal/src/dmac/dma_controller.rs | 12 +- hal/src/dmac/mod.rs | 20 +- hal/src/gpio/dynpin.rs | 28 ++- hal/src/gpio/pin.rs | 222 ++++++++--------- hal/src/gpio/reg.rs | 28 ++- hal/src/peripherals/adc/d11.rs | 93 +++---- hal/src/peripherals/adc/d5x.rs | 61 +++-- hal/src/peripherals/calibration/d11.rs | 13 +- hal/src/peripherals/can.rs | 15 +- hal/src/peripherals/clock/d11.rs | 19 +- hal/src/peripherals/clock/d5x/v1.rs | 23 +- hal/src/peripherals/clock/d5x/v2/ahb.rs | 11 +- hal/src/peripherals/clock/d5x/v2/apb.rs | 66 ++--- hal/src/peripherals/clock/d5x/v2/gclk.rs | 35 ++- hal/src/peripherals/clock/d5x/v2/pclk.rs | 42 ++-- hal/src/peripherals/clock/d5x/v2/types.rs | 50 ++-- hal/src/peripherals/eic/d11/pin.rs | 101 +++++--- hal/src/peripherals/eic/d5x/pin.rs | 161 ++++++++----- hal/src/peripherals/mod.rs | 109 +++++---- hal/src/peripherals/pwm/d11.rs | 47 ++-- hal/src/peripherals/pwm/d5x.rs | 254 ++++++++++--------- hal/src/peripherals/timer/d11.rs | 10 +- hal/src/peripherals/timer/d5x.rs | 6 +- hal/src/rtc.rs | 29 ++- hal/src/sercom/dma.rs | 32 ++- hal/src/sercom/i2c.rs | 12 +- hal/src/sercom/i2c/pads_thumbv6m.rs | 10 +- hal/src/sercom/mod.rs | 97 +++++--- hal/src/sercom/pad.rs | 37 ++- hal/src/sercom/pad/impl_pad_thumbv6m.rs | 6 +- hal/src/sercom/pad/impl_pad_thumbv7em.rs | 281 +++++++++++++++++----- hal/src/sercom/spi.rs | 129 +++++----- hal/src/sercom/spi/pads_thumbv6m.rs | 10 +- hal/src/sercom/spi/reg.rs | 23 +- hal/src/sercom/spi_future.rs | 20 +- hal/src/sercom/uart.rs | 16 +- hal/src/sercom/uart/config.rs | 6 +- hal/src/sercom/uart/pads_thumbv6m.rs | 10 +- hal/src/sercom/uart/reg.rs | 10 +- 42 files changed, 1328 insertions(+), 865 deletions(-) diff --git a/hal/Cargo.toml b/hal/Cargo.toml index cf26d7ef119..c204d553e7b 100644 --- a/hal/Cargo.toml +++ b/hal/Cargo.toml @@ -31,6 +31,7 @@ features = ["samd21g", "samd21g-rt", "unproven", "usb", "dma"] [dependencies] aes = "0.7.5" +atsamd-hal-macros = { version = "0.16.0", path = "../atsamd-hal-macros" } bitfield = "0.13" bitflags = "1.2.1" cipher = "0.3" diff --git a/hal/src/dmac/channel/mod.rs b/hal/src/dmac/channel/mod.rs index 285588acc4f..e2d94c216f9 100644 --- a/hal/src/dmac/channel/mod.rs +++ b/hal/src/dmac/channel/mod.rs @@ -31,6 +31,8 @@ //! `Uninitialized` state. You will be required to call [`Channel::init`] //! again before being able to use it with a `Transfer`. +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use super::dma_controller::{ChId, PriorityLevel, TriggerAction, TriggerSource}; use crate::typelevel::{Is, Sealed}; use core::marker::PhantomData; @@ -40,7 +42,7 @@ mod reg; use reg::RegisterBlock; -#[cfg(feature = "thumbv7")] +#[hal_cfg("dmac-d5x")] use super::dma_controller::{BurstLength, FifoThreshold}; //============================================================================== @@ -139,15 +141,16 @@ impl Channel { /// /// A `Channel` with a `Ready` status #[inline] + #[hal_macro_helper] pub fn init(mut self, lvl: PriorityLevel) -> Channel { // Software reset the channel for good measure self._reset_private(); - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("dmac-d11", "dmac-d21"))] // Setup priority level self.regs.chctrlb.modify(|_, w| w.lvl().bits(lvl as u8)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("dmac-d5x")] self.regs.chprilvl.modify(|_, w| w.prilvl().bits(lvl as u8)); Channel { @@ -218,7 +221,7 @@ impl Channel { /// Set the FIFO threshold length. The channel will wait until it has /// received the selected number of Beats before triggering the Burst /// transfer, reducing the DMA transfer latency. - #[cfg(feature = "thumbv7")] + #[hal_cfg("dmac-d5x")] #[inline] pub fn fifo_threshold(&mut self, threshold: FifoThreshold) { self.regs @@ -228,7 +231,7 @@ impl Channel { /// Set burst length for the channel, in number of beats. A burst transfer /// is an atomic, uninterruptible operation. - #[cfg(feature = "thumbv7")] + #[hal_cfg("dmac-d5x")] #[inline] pub fn burst_length(&mut self, burst_length: BurstLength) { self.regs @@ -242,19 +245,20 @@ impl Channel { /// /// A `Channel` with a `Busy` status. #[inline] + #[hal_macro_helper] pub(crate) fn start( mut self, trig_src: TriggerSource, trig_act: TriggerAction, ) -> Channel { // Configure the trigger source and trigger action - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("dmac-d11", "dmac-d21"))] self.regs.chctrlb.modify(|_, w| { w.trigsrc().variant(trig_src); w.trigact().variant(trig_act) }); - #[cfg(feature = "thumbv7")] + #[hal_cfg("dmac-d5x")] self.regs.chctrla.modify(|_, w| { w.trigsrc().variant(trig_src); w.trigact().variant(trig_act) diff --git a/hal/src/dmac/channel/reg.rs b/hal/src/dmac/channel/reg.rs index 5b8b0502e29..753c1e7107e 100644 --- a/hal/src/dmac/channel/reg.rs +++ b/hal/src/dmac/channel/reg.rs @@ -10,6 +10,8 @@ //! way. For SAMD51+, `with_chid` returns the register block which contains the //! registers owned by a specific channel. +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use super::super::dma_controller::ChId; use core::marker::PhantomData; use paste::paste; @@ -24,10 +26,10 @@ use crate::pac::{ Peripherals, DMAC, }; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("dmac-d11", "dmac-d21"))] use pac::dmac as channel_regs; -#[cfg(feature = "thumbv7")] +#[hal_cfg("dmac-d5x")] use pac::dmac::channel as channel_regs; use channel_regs::{ @@ -36,7 +38,7 @@ use channel_regs::{ }; use channel_regs::{CHCTRLA, CHCTRLB, CHINTENCLR, CHINTENSET, CHINTFLAG, CHSTATUS}; -#[cfg(feature = "thumbv7")] +#[hal_cfg("dmac-d5x")] use pac::dmac::{ channel::{chprilvl::CHPRILVL_SPEC, CHPRILVL}, CHANNEL, @@ -56,7 +58,7 @@ pub(super) trait Register { /// the CHID register, then access the channel control registers. /// If an interrupt were to change the CHID register and not reset it /// to the expected value, we would be faced with undefined behaviour. - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("dmac-d11", "dmac-d21"))] #[inline] fn with_chid R, R>(&mut self, fun: F) -> R { // SAFETY: This method is ONLY safe if the individual channels are GUARANTEED @@ -92,7 +94,7 @@ pub(super) trait Register { /// the registers are accessed in an interrupt-safe way, as the SAMD21 /// DMAC is a little funky. For the SAMD51/SAMEx, we simply take a reference /// to the correct channel number and run the closure on that. - #[cfg(feature = "thumbv7")] + #[hal_cfg("dmac-d5x")] #[inline] fn with_chid R, R>(&mut self, fun: F) -> R { // SAFETY: This method is ONLY safe if the individual channels are GUARANTEED @@ -266,7 +268,7 @@ reg_proxy!(chintenclr, register, rw); reg_proxy!(chintenset, register, rw); reg_proxy!(chintflag, register, rw); reg_proxy!(chstatus, register, r); -#[cfg(feature = "thumbv7")] +#[hal_cfg("dmac-d5x")] reg_proxy!(chprilvl, register, rw); reg_proxy!(intstatus, bit, r); @@ -278,6 +280,7 @@ reg_proxy!(swtrigctrl, bit, rw); /// within registers that should be readable/writable by specific /// [`Channel`]s are exposed. #[allow(dead_code)] +#[hal_macro_helper] pub(super) struct RegisterBlock { pub chctrla: ChctrlaProxy, pub chctrlb: ChctrlbProxy, @@ -289,11 +292,12 @@ pub(super) struct RegisterBlock { pub busych: BusychProxy, pub pendch: PendchProxy, pub swtrigctrl: SwtrigctrlProxy, - #[cfg(feature = "thumbv7")] + #[hal_cfg("dmac-d5x")] pub chprilvl: ChprilvlProxy, } impl RegisterBlock { + #[hal_macro_helper] pub(super) fn new(_id: PhantomData) -> Self { Self { chctrla: ChctrlaProxy::new(), @@ -306,7 +310,7 @@ impl RegisterBlock { busych: BusychProxy::new(), pendch: PendchProxy::new(), swtrigctrl: SwtrigctrlProxy::new(), - #[cfg(feature = "thumbv7")] + #[hal_cfg("dmac-d5x")] chprilvl: ChprilvlProxy::new(), } } diff --git a/hal/src/dmac/dma_controller.rs b/hal/src/dmac/dma_controller.rs index 6b573f894be..c3bd4fe67ab 100644 --- a/hal/src/dmac/dma_controller.rs +++ b/hal/src/dmac/dma_controller.rs @@ -19,16 +19,18 @@ //! Using the [`DmaController::free`] method will //! deinitialize the DMAC and return the underlying PAC object. +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use modular_bitfield::prelude::*; use seq_macro::seq; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("dmac-d11", "dmac-d21"))] pub use crate::pac::dmac::chctrlb::{ LVLSELECT_A as PriorityLevel, TRIGACTSELECT_A as TriggerAction, TRIGSRCSELECT_A as TriggerSource, }; -#[cfg(feature = "thumbv7")] +#[hal_cfg("dmac-d5x")] pub use crate::pac::dmac::channel::{ chctrla::{ BURSTLENSELECT_A as BurstLength, THRESHOLDSELECT_A as FifoThreshold, @@ -133,9 +135,10 @@ impl DmaController { /// priority levels are enabled unless subsequently disabled using the /// `level_x_enabled` methods. #[inline] + #[hal_macro_helper] pub fn init(mut dmac: DMAC, _pm: &mut PM) -> Self { // ----- Initialize clocking ----- // - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("dmac-d11", "dmac-d21"))] { // Enable clocking _pm.ahbmask.modify(|_, w| w.dmac_().set_bit()); @@ -226,12 +229,13 @@ impl DmaController { /// moved back into the [`Channels`] struct before being able to pass it /// into [`free`](DmaController::free). #[inline] + #[hal_macro_helper] pub fn free(mut self, _channels: Channels, _pm: &mut PM) -> DMAC { self.dmac.ctrl.modify(|_, w| w.dmaenable().clear_bit()); Self::swreset(&mut self.dmac); - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("dmac-d11", "dmac-d21"))] { // Disable the DMAC clocking _pm.apbbmask.modify(|_, w| w.dmac_().clear_bit()); diff --git a/hal/src/dmac/mod.rs b/hal/src/dmac/mod.rs index 43d2377f204..57333b1817b 100644 --- a/hal/src/dmac/mod.rs +++ b/hal/src/dmac/mod.rs @@ -251,6 +251,8 @@ // This is necessary until modular_bitfield fixes all their identity_op warnings #![allow(clippy::identity_op)] +use atsamd_hal_macros::hal_cfg; + use modular_bitfield::prelude::*; pub use channel::*; @@ -277,7 +279,8 @@ pub enum Error { /// Result for DMAC operations pub type Result = core::result::Result; -#[cfg(all(feature = "samd11", feature = "max-channels"))] +#[cfg(feature = "max-channels")] +#[hal_cfg("dmac-d11")] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { @@ -285,7 +288,8 @@ macro_rules! with_num_channels { }; } -#[cfg(all(feature = "samd21", feature = "max-channels"))] +#[cfg(feature = "max-channels")] +#[hal_cfg("dmac-d21")] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { @@ -293,7 +297,8 @@ macro_rules! with_num_channels { }; } -#[cfg(all(feature = "thumbv7", feature = "max-channels"))] +#[cfg(feature = "max-channels")] +#[hal_cfg("dmac-d5x")] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { @@ -301,7 +306,8 @@ macro_rules! with_num_channels { }; } -#[cfg(all(feature = "samd11", not(feature = "max-channels")))] +#[cfg(not(feature = "max-channels"))] +#[hal_cfg("dmac-d11")] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { @@ -309,7 +315,8 @@ macro_rules! with_num_channels { }; } -#[cfg(all(feature = "samd21", not(feature = "max-channels")))] +#[cfg(not(feature = "max-channels"))] +#[hal_cfg("dmac-d21")] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { @@ -317,7 +324,8 @@ macro_rules! with_num_channels { }; } -#[cfg(all(feature = "thumbv7", not(feature = "max-channels")))] +#[cfg(not(feature = "max-channels"))] +#[hal_cfg("dmac-d5x")] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { diff --git a/hal/src/gpio/dynpin.rs b/hal/src/gpio/dynpin.rs index e00a6eef21f..4c7af067774 100644 --- a/hal/src/gpio/dynpin.rs +++ b/hal/src/gpio/dynpin.rs @@ -59,6 +59,8 @@ #![allow(clippy::bool_comparison)] +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use core::convert::TryFrom; use paste::paste; @@ -106,6 +108,7 @@ pub enum DynOutput { } /// Value-level `enum` for alternate peripheral function configurations +#[hal_macro_helper] #[derive(PartialEq, Eq, Clone, Copy)] pub enum DynAlternate { B, @@ -114,19 +117,19 @@ pub enum DynAlternate { E, F, G, - #[cfg(any(feature = "samd21", feature = "thumbv7"))] + #[hal_cfg(any("port-d21", "port-d5x"))] H, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] I, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] J, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] K, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] L, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] M, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] N, } @@ -186,9 +189,9 @@ macro_rules! dyn_alternate { } dyn_alternate!(B, C, D, E, F, G); -#[cfg(any(feature = "samd21", feature = "thumbv7"))] +#[hal_cfg(any("port-d21", "port-d5x"))] dyn_alternate!(H); -#[cfg(feature = "thumbv7")] +#[hal_cfg("port-d5x")] dyn_alternate!(I, J, K, L, M, N); //============================================================================== @@ -197,13 +200,14 @@ dyn_alternate!(I, J, K, L, M, N); /// Value-level `enum` for pin groups #[derive(PartialEq, Clone, Copy)] +#[hal_macro_helper] pub enum DynGroup { A, - #[cfg(any(feature = "samd21", feature = "thumbv7"))] + #[hal_cfg("pin-group-b")] B, - #[cfg(feature = "pins-100")] + #[hal_cfg("pin-group-c")] C, - #[cfg(feature = "pins-128")] + #[hal_cfg("pin-group-d")] D, } diff --git a/hal/src/gpio/pin.rs b/hal/src/gpio/pin.rs index 2b74cc7a019..024874160b7 100644 --- a/hal/src/gpio/pin.rs +++ b/hal/src/gpio/pin.rs @@ -96,6 +96,8 @@ #![allow(clippy::zero_prefixed_literal)] #![allow(clippy::bool_comparison)] +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use core::convert::Infallible; use core::marker::PhantomData; use core::mem::transmute; @@ -342,10 +344,10 @@ macro_rules! alternate { alternate!(B, C, D, E, F, G); -#[cfg(any(feature = "samd21", feature = "thumbv7"))] +#[hal_cfg(any("port-d21", "port-d5x"))] alternate!(H); -#[cfg(feature = "thumbv7")] +#[hal_cfg("port-d5x")] alternate!(I, J, K, L, M, N); /// Type-level variant of [`PinMode`] for alternate peripheral functions @@ -732,6 +734,7 @@ macro_rules! impl_core_convert_from { }; } +#[hal_macro_helper] impl_core_convert_from!( FloatingDisabled, PullDownDisabled, @@ -750,19 +753,19 @@ impl_core_convert_from!( AlternateE, AlternateF, AlternateG, - #[cfg(any(feature = "samd21", feature = "thumbv7"))] + #[hal_cfg(any("port-d21", "port-d5x"))] AlternateH, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] AlternateI, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] AlternateJ, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] AlternateK, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] AlternateL, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] AlternateM, - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] AlternateN, ); @@ -1064,213 +1067,214 @@ macro_rules! declare_pins { }; } +#[hal_macro_helper] declare_pins!( A { - #[cfg(feature = "has-pa00")] + #[hal_cfg("pa00")] (PA00, 00), - #[cfg(feature = "has-pa01")] + #[hal_cfg("pa01")] (PA01, 01), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa02")] (PA02, 02), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa03")] (PA03, 03), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa04")] (PA04, 04), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa05")] (PA05, 05), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa06")] (PA06, 06), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa07")] (PA07, 07), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa08")] (PA08, 08), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa09")] (PA09, 09), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa10")] (PA10, 10), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa11")] (PA11, 11), - #[cfg(feature = "pins-48")] + #[hal_cfg("pa12")] (PA12, 12), - #[cfg(feature = "pins-48")] + #[hal_cfg("pa13")] (PA13, 13), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa14")] (PA14, 14), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa15")] (PA15, 15), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa16")] (PA16, 16), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa17")] (PA17, 17), - #[cfg(feature = "pins-32")] + #[hal_cfg("pa18")] (PA18, 18), - #[cfg(feature = "pins-32")] + #[hal_cfg("pa19")] (PA19, 19), - #[cfg(feature = "pins-48")] + #[hal_cfg("pa20")] (PA20, 20), - #[cfg(feature = "pins-48")] + #[hal_cfg("pa21")] (PA21, 21), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa22")] (PA22, 22), - #[cfg(feature = "pins-24")] + #[hal_cfg("pa23")] (PA23, 23), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa24")] (PA24, 24), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa25")] (PA25, 25), - #[cfg(feature = "has-pa27")] + #[hal_cfg("pa27")] (PA27, 27), - #[cfg(feature = "has-pa28")] + #[hal_cfg("pa28")] (PA28, 28), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa30")] (PA30, 30), - #[cfg(feature = "pins-14")] + #[hal_cfg("pa31")] (PA31, 31), } B { - #[cfg(feature = "has-pb00")] + #[hal_cfg("pb00")] (PB00, 00), - #[cfg(feature = "has-pb01")] + #[hal_cfg("pb01")] (PB01, 01), - #[cfg(feature = "has-pb02")] + #[hal_cfg("pb02")] (PB02, 02), - #[cfg(feature = "has-pb03")] + #[hal_cfg("pb03")] (PB03, 03), - #[cfg(feature = "has-pb04")] + #[hal_cfg("pb04")] (PB04, 04), - #[cfg(feature = "has-pb05")] + #[hal_cfg("pb05")] (PB05, 05), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb06")] (PB06, 06), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb07")] (PB07, 07), - #[cfg(feature = "pins-48")] + #[hal_cfg("pb08")] (PB08, 08), - #[cfg(feature = "pins-48")] + #[hal_cfg("pb09")] (PB09, 09), - #[cfg(feature = "pins-48")] + #[hal_cfg("pb10")] (PB10, 10), - #[cfg(feature = "pins-48")] + #[hal_cfg("pb11")] (PB11, 11), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] (PB12, 12), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] (PB13, 13), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] (PB14, 14), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] (PB15, 15), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] (PB16, 16), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] (PB17, 17), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb18")] (PB18, 18), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb19")] (PB19, 19), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb20")] (PB20, 20), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb21")] (PB21, 21), - #[cfg(feature = "has-pb22")] + #[hal_cfg("pb22")] (PB22, 22), - #[cfg(feature = "has-pb23")] + #[hal_cfg("pb23")] (PB23, 23), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb24")] (PB24, 24), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb25")] (PB25, 25), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb26")] (PB26, 26), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb27")] (PB27, 27), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb28")] (PB28, 28), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb29")] (PB29, 29), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb30")] (PB30, 30), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb31")] (PB31, 31), } C { - #[cfg(feature = "pins-100")] + #[hal_cfg("pc00")] (PC00, 00), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc01")] (PC01, 01), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc02")] (PC02, 02), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc03")] (PC03, 03), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc04")] (PC04, 04), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc05")] (PC05, 05), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc06")] (PC06, 06), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc07")] (PC07, 07), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc10")] (PC10, 10), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc11")] (PC11, 11), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc12")] (PC12, 12), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc13")] (PC13, 13), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc14")] (PC14, 14), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc15")] (PC15, 15), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc16")] (PC16, 16), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc17")] (PC17, 17), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc18")] (PC18, 18), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc19")] (PC19, 19), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc20")] (PC20, 20), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc21")] (PC21, 21), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc22")] (PC22, 22), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc23")] (PC23, 23), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc24")] (PC24, 24), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc25")] (PC25, 25), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc26")] (PC26, 26), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc27")] (PC27, 27), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc28")] (PC28, 28), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc30")] (PC30, 30), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc31")] (PC31, 31), } D { - #[cfg(feature = "pins-128")] + #[hal_cfg("pd00")] (PD00, 00), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd01")] (PD01, 01), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd08")] (PD08, 08), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd09")] (PD09, 09), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd10")] (PD10, 10), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd11")] (PD11, 11), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd12")] (PD12, 12), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd20")] (PD20, 20), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd21")] (PD21, 21), } ); diff --git a/hal/src/gpio/reg.rs b/hal/src/gpio/reg.rs index 899a7b88a00..842dbf52171 100644 --- a/hal/src/gpio/reg.rs +++ b/hal/src/gpio/reg.rs @@ -1,10 +1,12 @@ -#[cfg(feature = "thumbv6")] +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + +#[hal_cfg(any("port-d11", "port-d21"))] use crate::pac::port::{ CTRL, DIR, DIRCLR, DIRSET, DIRTGL, IN, OUT, OUTCLR, OUTSET, OUTTGL, PINCFG0_ as PINCFG, PMUX0_ as PMUX, WRCONFIG, }; -#[cfg(feature = "thumbv7")] +#[hal_cfg("port-d5x")] use crate::pac::port::group::{ CTRL, DIR, DIRCLR, DIRSET, DIRTGL, IN, OUT, OUTCLR, OUTSET, OUTTGL, PINCFG, PMUX, WRCONFIG, }; @@ -30,6 +32,7 @@ struct ModeFields { impl From for ModeFields { #[inline] + #[hal_macro_helper] fn from(mode: DynPinMode) -> Self { let mut fields = Self::default(); use DynPinMode::*; @@ -122,31 +125,31 @@ impl From for ModeFields { G => { fields.pmux = 6; } - #[cfg(any(feature = "samd21", feature = "thumbv7"))] + #[hal_cfg(any("port-d21", "port-d5x"))] H => { fields.pmux = 7; } - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] I => { fields.pmux = 8; } - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] J => { fields.pmux = 9; } - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] K => { fields.pmux = 10; } - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] L => { fields.pmux = 11; } - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] M => { fields.pmux = 12; } - #[cfg(feature = "thumbv7")] + #[hal_cfg("port-d5x")] N => { fields.pmux = 13; } @@ -228,14 +231,15 @@ pub(super) unsafe trait RegisterInterface { const GROUPS: *const GROUP = PORT::ptr() as *const _; #[inline] + #[hal_macro_helper] fn group(&self) -> &GROUP { let offset = match self.id().group { DynGroup::A => 0, - #[cfg(any(feature = "samd21", feature = "thumbv7"))] + #[hal_cfg("pin-group-b")] DynGroup::B => 1, - #[cfg(feature = "pins-100")] + #[hal_cfg("pin-group-c")] DynGroup::C => 2, - #[cfg(feature = "pins-128")] + #[hal_cfg("pin-group-d")] DynGroup::D => 3, }; // Safety: It is safe to create shared references to each PAC register diff --git a/hal/src/peripherals/adc/d11.rs b/hal/src/peripherals/adc/d11.rs index 3045cc0514c..9b95942da39 100644 --- a/hal/src/peripherals/adc/d11.rs +++ b/hal/src/peripherals/adc/d11.rs @@ -1,4 +1,6 @@ //! Analogue-to-Digital Conversion +use atsamd_hal_macros::hal_cfg; + use crate::clock::GenericClockController; use crate::ehal::adc::{Channel, OneShot}; use crate::gpio::*; @@ -165,10 +167,13 @@ where macro_rules! adc_pins { ( $( + $( #[$cfg:meta] )? $PinId:ident: $CHAN:literal ),+ + $(,)? ) => { $( + $( #[$cfg] )? impl Channel for Pin<$PinId, AlternateB> { type ID = u8; fn channel() -> u8 { $CHAN } @@ -177,64 +182,70 @@ macro_rules! adc_pins { } } -#[cfg(feature = "samd11")] +#[hal_cfg("adc-d11")] adc_pins! { + #[hal_cfg("pa02")] PA02: 0, + #[hal_cfg("pa03")] + PA03: 1, + #[hal_cfg("pa04")] PA04: 2, + #[hal_cfg("pa05")] PA05: 3, - PA14: 6, - PA15: 7 -} - -#[cfg(feature = "pins-d11d")] -adc_pins! { - PA03: 1, + #[hal_cfg("pa06")] PA06: 4, + #[hal_cfg("pa07")] PA07: 5, + #[hal_cfg("pa14")] + PA14: 6, + #[hal_cfg("pa15")] + PA15: 7, + #[hal_cfg("pa10")] PA10: 8, - PA11: 9 + #[hal_cfg("pa11")] + PA11: 9, } -#[cfg(feature = "samd21")] +#[hal_cfg("adc-d21")] adc_pins! { + #[hal_cfg("pa02")] PA02: 0, + #[hal_cfg("pa03")] PA03: 1, + #[hal_cfg("pb08")] + PB08: 2, + #[hal_cfg("pb09")] + PB09: 3, + #[hal_cfg("pa04")] PA04: 4, + #[hal_cfg("pa05")] PA05: 5, + #[hal_cfg("pa06")] PA06: 6, + #[hal_cfg("pa07")] PA07: 7, + #[hal_cfg("pb00")] + PB00: 8, + #[hal_cfg("pb01")] + PB01: 9, + #[hal_cfg("pb02")] + PB02: 10, + #[hal_cfg("pb03")] + PB03: 11, + #[hal_cfg("pb04")] + PB04: 12, + #[hal_cfg("pb05")] + PB05: 13, + #[hal_cfg("pb06")] + PB06: 14, + #[hal_cfg("pb07")] + PB07: 15, + #[hal_cfg("pa08")] PA08: 16, + #[hal_cfg("pa09")] PA09: 17, + #[hal_cfg("pa10")] PA10: 18, - PA11: 19 -} - -#[cfg(feature = "has-pb00")] -adc_pins! { PB00: 8 } - -#[cfg(feature = "has-pb01")] -adc_pins! { PB01: 9 } - -#[cfg(feature = "has-pb02")] -adc_pins! { PB02: 10 } - -#[cfg(feature = "has-pb03")] -adc_pins! { PB03: 11 } - -#[cfg(feature = "has-pb04")] -adc_pins! { PB04: 12 } - -#[cfg(feature = "has-pb05")] -adc_pins! { PB05: 13 } - -#[cfg(feature = "pins-48")] -adc_pins! { - PB08: 2, - PB09: 3 -} - -#[cfg(feature = "pins-64")] -adc_pins! { - PB06: 14, - PB07: 15 + #[hal_cfg("pa11")] + PA11: 19, } diff --git a/hal/src/peripherals/adc/d5x.rs b/hal/src/peripherals/adc/d5x.rs index e7d61b48e10..349ee5d128e 100644 --- a/hal/src/peripherals/adc/d5x.rs +++ b/hal/src/peripherals/adc/d5x.rs @@ -1,4 +1,6 @@ //! Analogue-to-Digital Conversion +use atsamd_hal_macros::hal_cfg; + use crate::clock::GenericClockController; #[rustfmt::skip] use crate::gpio::*; @@ -273,10 +275,13 @@ adc_hal! { macro_rules! adc_pins { ( $( - $PinId:ident: ($ADC:ident, $CHAN:literal), - )+ + $( #[$cfg:meta] )? + $PinId:ident: ($ADC:ident, $CHAN:literal) + ),+ + $(,)? ) => { $( + $( #[$cfg] )? impl Channel<$ADC> for Pin<$PinId, AlternateB> { type ID = u8; fn channel() -> u8 { $CHAN } @@ -286,49 +291,69 @@ macro_rules! adc_pins { } adc_pins! { + #[hal_cfg("pa02")] PA02: (ADC0, 0), + #[hal_cfg("pa03")] PA03: (ADC0, 1), + #[hal_cfg("pb08")] PB08: (ADC0, 2), + #[hal_cfg("pb09")] PB09: (ADC0, 3), + #[hal_cfg("pa04")] PA04: (ADC0, 4), + #[hal_cfg("pa05")] PA05: (ADC0, 5), + #[hal_cfg("pa06")] PA06: (ADC0, 6), + #[hal_cfg("pa07")] PA07: (ADC0, 7), + #[hal_cfg("pa08")] PA08: (ADC0, 8), + #[hal_cfg("pa09")] PA09: (ADC0, 9), + #[hal_cfg("pa10")] PA10: (ADC0, 10), + #[hal_cfg("pa11")] PA11: (ADC0, 11), + #[hal_cfg("pb00")] + PB00: (ADC0, 12), + #[hal_cfg("pb01")] + PB01: (ADC0, 13), + #[hal_cfg("pb02")] PB02: (ADC0, 14), + #[hal_cfg("pb03")] PB03: (ADC0, 15), + #[hal_cfg("pb08")] PB08: (ADC1, 0), + #[hal_cfg("pb09")] PB09: (ADC1, 1), + #[hal_cfg("pa08")] PA08: (ADC1, 2), + #[hal_cfg("pa09")] PA09: (ADC1, 3), -} - -#[cfg(feature = "pins-64")] -adc_pins! { - PB00: (ADC0, 12), - PB01: (ADC0, 13), + #[hal_cfg("pc02")] + PC02: (ADC1, 4), + #[hal_cfg("pc03")] + PC03: (ADC1, 5), + #[hal_cfg("pb04")] PB04: (ADC1, 6), + #[hal_cfg("pb05")] PB05: (ADC1, 7), + #[hal_cfg("pb06")] PB06: (ADC1, 8), + #[hal_cfg("pb07")] PB07: (ADC1, 9), -} - -#[cfg(feature = "pins-100")] -adc_pins! { - PC02: (ADC1, 4), - PC03: (ADC1, 5), + #[hal_cfg("pc00")] PC00: (ADC1, 10), + #[hal_cfg("pc01")] PC01: (ADC1, 11), -} - -#[cfg(feature = "pins-128")] -adc_pins! { + #[hal_cfg("pc30")] PC30: (ADC1, 12), + #[hal_cfg("pc31")] PC31: (ADC1, 13), + #[hal_cfg("pd00")] PD00: (ADC1, 14), + #[hal_cfg("pd01")] PD01: (ADC1, 15), } diff --git a/hal/src/peripherals/calibration/d11.rs b/hal/src/peripherals/calibration/d11.rs index fb4228206c4..ee855d7ef2b 100644 --- a/hal/src/peripherals/calibration/d11.rs +++ b/hal/src/peripherals/calibration/d11.rs @@ -2,6 +2,7 @@ // For samd11, see 9.5 NVM Software Calibration Area Mapping, page 24 // For samd21, see 10.3.2 NVM Software Calibration Area Mapping, page 46 +use atsamd_hal_macros::hal_cfg; use core::ptr; const ADDR: u32 = 0x806020u32; @@ -53,9 +54,13 @@ pub fn usb_transp_cal() -> u8 { } /// USB TRIM calibration value. Should be written to USB PADCAL register. +#[hal_cfg("nvmctrl-d11")] pub fn usb_trim_cal() -> u8 { - #[cfg(feature = "samd11")] - return cal_with_errata(4, 23, 7, 7, 5) as u8; - #[cfg(feature = "samd21")] - return cal_with_errata(4, 23, 7, 7, 3) as u8; + cal_with_errata(4, 23, 7, 7, 5) as u8 +} + +/// USB TRIM calibration value. Should be written to USB PADCAL register. +#[hal_cfg("nvmctrl-d21")] +pub fn usb_trim_cal() -> u8 { + cal_with_errata(4, 23, 7, 7, 3) as u8 } diff --git a/hal/src/peripherals/can.rs b/hal/src/peripherals/can.rs index 672a8897753..2eb7e8ebaeb 100644 --- a/hal/src/peripherals/can.rs +++ b/hal/src/peripherals/can.rs @@ -21,8 +21,9 @@ use crate::{ gpio::*, typelevel::{Decrement, Increment}, }; +use atsamd_hal_macros::hal_cfg; -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] use crate::clock::v2::types::Can1; use mcan_core::fugit::HertzU32; @@ -115,7 +116,7 @@ unsafe impl CanId for Can0 { const ADDRESS: *const () = crate::pac::CAN0::PTR as *const _; } -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] unsafe impl CanId for Can1 { const ADDRESS: *const () = crate::pac::CAN1::PTR as *const _; } @@ -128,7 +129,7 @@ impl OwnedPeripheral for crate::pac::CAN0 { type Represents = Can0; } -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] impl OwnedPeripheral for crate::pac::CAN1 { type Represents = Can1; } @@ -157,22 +158,22 @@ impl TxPin for Pin { type ValidFor = Can0; } -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] impl RxPin for Pin { type ValidFor = Can1; } -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] impl RxPin for Pin { type ValidFor = Can1; } -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] impl TxPin for Pin { type ValidFor = Can1; } -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] impl TxPin for Pin { type ValidFor = Can1; } diff --git a/hal/src/peripherals/clock/d11.rs b/hal/src/peripherals/clock/d11.rs index 93d21194611..425e63ad667 100644 --- a/hal/src/peripherals/clock/d11.rs +++ b/hal/src/peripherals/clock/d11.rs @@ -5,6 +5,8 @@ //! that the peripherals have been correctly configured. #![allow(clippy::from_over_into)] +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use fugit::RateExtU32; use crate::pac::gclk::clkctrl::GENSELECT_A::*; @@ -153,6 +155,7 @@ impl GenericClockController { Self::new_48mhz_from_32khz(gclk, pm, sysctrl, nvmctrl, true) } + #[hal_macro_helper] fn new_48mhz_from_32khz( gclk: GCLK, pm: &mut PM, @@ -163,7 +166,7 @@ impl GenericClockController { let mut state = State { gclk }; set_flash_to_half_auto_wait_state(nvmctrl); - #[cfg(feature = "samd21")] + #[hal_cfg("clock-d21")] set_flash_manual_write(nvmctrl); enable_gclk_apb(pm); if use_external_crystal { @@ -217,6 +220,7 @@ impl GenericClockController { /// Reset the clock controller, configure the system to run at 8Mhz from /// internal 8 MHz RC clock (no PLL) and reset various clock dividers. + #[hal_macro_helper] pub fn with_internal_8mhz( gclk: GCLK, pm: &mut PM, @@ -226,11 +230,11 @@ impl GenericClockController { let mut state = State { gclk }; // No wait states needed <= 24 MHz @ 3.3v (ref. 37.12 NVM characteristics) - #[cfg(feature = "samd21")] + #[hal_cfg("clock-d21")] set_flash_manual_write(nvmctrl); // Get rid of unused warning - #[cfg(not(feature = "samd21"))] + #[hal_cfg("clock-d11")] let _ = nvmctrl; enable_gclk_apb(pm); @@ -397,7 +401,7 @@ impl GenericClockController { } // samd11 -#[cfg(feature = "samd11")] +#[hal_cfg("clock-d11")] clock_generator!( (tcc0, Tcc0Clock, TCC0), (tc1_tc2, Tc1Tc2Clock, TC1_TC2), @@ -419,7 +423,7 @@ clock_generator!( (dac, DacClock, DAC), ); // samd21 -#[cfg(feature = "samd21")] +#[hal_cfg("clock-d21")] clock_generator!( (tcc0_tcc1, Tcc0Tcc1Clock, TCC0_TCC1), (tcc2_tc3, Tcc2Tc3Clock, TCC2_TC3), @@ -467,7 +471,7 @@ fn set_flash_to_half_auto_wait_state(nvmctrl: &mut NVMCTRL) { } /// Prevent automatic writes to flash by pointers to flash area -#[cfg(feature = "samd21")] +#[hal_cfg("clock-d21")] fn set_flash_manual_write(nvmctrl: &mut NVMCTRL) { nvmctrl.ctrlb.modify(|_, w| w.manw().set_bit()); } @@ -520,6 +524,7 @@ fn wait_for_dfllrdy(sysctrl: &mut SYSCTRL) { } /// Configure the dfll48m to operate at 48Mhz +#[hal_macro_helper] fn configure_and_enable_dfll48m(sysctrl: &mut SYSCTRL, use_external_crystal: bool) { // Turn it off while we configure it. // Note that we need to turn off on-demand mode and @@ -590,7 +595,7 @@ fn configure_and_enable_dfll48m(sysctrl: &mut SYSCTRL, use_external_crystal: boo // and finally enable it! sysctrl.dfllctrl.modify(|_, w| w.enable().set_bit()); - #[cfg(feature = "samd21")] + #[hal_cfg("clock-d21")] if use_external_crystal { // wait for lock while sysctrl.pclksr.read().dflllckc().bit_is_clear() diff --git a/hal/src/peripherals/clock/d5x/v1.rs b/hal/src/peripherals/clock/d5x/v1.rs index 859be06aebb..a1f60670cd7 100644 --- a/hal/src/peripherals/clock/d5x/v1.rs +++ b/hal/src/peripherals/clock/d5x/v1.rs @@ -7,6 +7,8 @@ //! configured. #![allow(clippy::from_over_into)] +use atsamd_hal_macros::hal_macro_helper; + use fugit::RateExtU32; use crate::clock::v2::pclk::{ids::*, Pclk, PclkSourceId}; @@ -422,16 +424,17 @@ impl GenericClockController { } } +#[hal_macro_helper] clock_generator!( (tc0_tc1, Tc0Tc1Clock, TC0_TC1, Tc0Tc1), (tcc0_tcc1, Tcc0Tcc1Clock, TCC0_TCC1, Tcc0Tcc1), (tc2_tc3, Tc2Tc3Clock, TC2_TC3, Tc2Tc3), (tcc2_tcc3, Tcc2Tcc3Clock, TCC2_TCC3, Tcc2Tcc3), - #[cfg(all(feature = "has-tc4", feature = "has-tc5"))] + #[hal_cfg(all("tc4", "tc5"))] (tc4_tc5, Tc4Tc5Clock, TC4_TC5, Tc4Tc5), - #[cfg(feature = "has-tcc4")] + #[hal_cfg("tcc4")] (tcc4, Tcc4Clock, TCC4, Tcc4), - #[cfg(all(feature = "has-tc6", feature = "has-tc7"))] + #[hal_cfg(all("tc6", "tc7"))] (tc6_tc7, Tc6Tc7Clock, TC6_TC7, Tc6Tc7), (sercom0_core, Sercom0CoreClock, SERCOM0_CORE, Sercom0), (sercom1_core, Sercom1CoreClock, SERCOM1_CORE, Sercom1), @@ -439,9 +442,9 @@ clock_generator!( (sercom3_core, Sercom3CoreClock, SERCOM3_CORE, Sercom3), (sercom4_core, Sercom4CoreClock, SERCOM4_CORE, Sercom4), (sercom5_core, Sercom5CoreClock, SERCOM5_CORE, Sercom5), - #[cfg(feature = "has-sercom6")] + #[hal_cfg("sercom6")] (sercom6_core, Sercom6CoreClock, SERCOM6_CORE, Sercom6), - #[cfg(feature = "has-sercom7")] + #[hal_cfg("sercom7")] (sercom7_core, Sercom7CoreClock, SERCOM7_CORE, Sercom7), (usb, UsbClock, USB, Usb), (adc0, Adc0Clock, ADC0, Adc0), @@ -461,20 +464,20 @@ clock_generator!( (evsys9, Evsys9Clock, EVSYS9, EvSys9), (evsys10, Evsys10Clock, EVSYS10, EvSys10), (evsys11, Evsys11Clock, EVSYS11, EvSys11), - #[cfg(feature = "has-can0")] + #[hal_cfg("can0")] (can0, Can0Clock, CAN0, Can0), - #[cfg(feature = "has-can1")] + #[hal_cfg("can1")] (can1, Can1Clock, CAN1, Can1), (pdec, PdecClock, PDEC, PDec), (ac, AcClock, AC, Ac), (ccl, CclClock, CCL, Ccl), (dac, DacClock, DAC, Dac), - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] (i2s0, I2S0Clock, I2S0, I2S0), - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] (i2s1, I2S1Clock, I2S1, I2S1), (sdhc0, Sdhc0Clock, SDHC0, Sdhc0), - #[cfg(feature = "has-sdhc1")] + #[hal_cfg("sdhc1")] (sdhc1, Sdhc1Clock, SDHC1, Sdhc1), (cm4_trace, Cm4TraceClock, CM4_TRACE, CM4Trace), ); diff --git a/hal/src/peripherals/clock/d5x/v2/ahb.rs b/hal/src/peripherals/clock/d5x/v2/ahb.rs index a614e321bdc..a6bcfc06495 100644 --- a/hal/src/peripherals/clock/d5x/v2/ahb.rs +++ b/hal/src/peripherals/clock/d5x/v2/ahb.rs @@ -122,6 +122,8 @@ //! [`Clocks`]: super::Clocks //! [`Buses`]: super::Buses +use atsamd_hal_macros::hal_macro_helper; + use core::marker::PhantomData; use bitflags; @@ -368,6 +370,7 @@ macro_rules! define_ahb_types { }; } +#[hal_macro_helper] define_ahb_types!( Hpb0 = 0, Hpb1 = 1, @@ -380,14 +383,14 @@ define_ahb_types!( Usb = 10, Pac = 12, Qspi = 13, - #[cfg(feature = "has-gmac")] + #[hal_cfg("gmac")] Gmac = 14, Sdhc0 = 15, - #[cfg(feature = "has-sdhc1")] + #[hal_cfg("sdhc1")] Sdhc1 = 16, - #[cfg(feature = "has-can0")] + #[hal_cfg("can0")] Can0 = 17, - #[cfg(feature = "has-can1")] + #[hal_cfg("can1")] Can1 = 18, Icm = 19, Pukcc = 20, diff --git a/hal/src/peripherals/clock/d5x/v2/apb.rs b/hal/src/peripherals/clock/d5x/v2/apb.rs index b8fb1d078f3..79ab24914b4 100644 --- a/hal/src/peripherals/clock/d5x/v2/apb.rs +++ b/hal/src/peripherals/clock/d5x/v2/apb.rs @@ -121,6 +121,7 @@ //! [`Clocks`]: super::Clocks //! [`Buses`]: super::Buses +use atsamd_hal_macros::hal_macro_helper; use core::marker::PhantomData; use bitflags; @@ -351,6 +352,7 @@ macro_rules! define_apb_types { }; } +#[hal_macro_helper] define_apb_types!( A { Pac = 0, @@ -385,14 +387,14 @@ define_apb_types!( RamEcc = 16, } C { - #[cfg(feature = "has-gmac")] + #[hal_cfg("gmac")] Gmac = 2, Tcc2 = 3, - #[cfg(feature = "has-tcc3")] + #[hal_cfg("tcc3")] Tcc3 = 4, - #[cfg(feature = "has-tc4")] + #[hal_cfg("tc4")] Tc4 = 5, - #[cfg(feature = "has-tc5")] + #[hal_cfg("tc5")] Tc5 = 6, PDec = 7, Ac = 8, @@ -405,20 +407,20 @@ define_apb_types!( D { Sercom4 = 0, Sercom5 = 1, - #[cfg(feature = "has-sercom6")] + #[hal_cfg("sercom6")] Sercom6 = 2, - #[cfg(feature = "has-sercom7")] + #[hal_cfg("sercom7")] Sercom7 = 3, - #[cfg(feature = "has-tcc4")] + #[hal_cfg("tcc4")] Tcc4 = 4, - #[cfg(feature = "has-tc6")] + #[hal_cfg("tc6")] Tc6 = 5, - #[cfg(feature = "has-tc7")] + #[hal_cfg("tc7")] Tc7 = 6, Adc0 = 7, Adc1 = 8, Dac = 9, - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] I2S = 10, Pcc = 11, } @@ -507,6 +509,7 @@ impl ApbClk { //============================================================================== /// Set of [`ApbToken`]s for APB clocks that are disabled at power-on reset +#[hal_macro_helper] pub struct ApbTokens { pub freq_m: ApbToken, pub sercom0: ApbToken, @@ -521,12 +524,12 @@ pub struct ApbTokens { pub tcc1: ApbToken, pub tc2: ApbToken, pub tc3: ApbToken, - #[cfg(feature = "has-tc4")] + #[hal_cfg("tc4")] pub tc4: ApbToken, pub tcc2: ApbToken, - #[cfg(feature = "has-tcc3")] + #[hal_cfg("tcc3")] pub tcc3: ApbToken, - #[cfg(feature = "has-tc5")] + #[hal_cfg("tc5")] pub tc5: ApbToken, pub p_dec: ApbToken, pub ac: ApbToken, @@ -536,20 +539,20 @@ pub struct ApbTokens { pub ccl: ApbToken, pub sercom4: ApbToken, pub sercom5: ApbToken, - #[cfg(feature = "has-sercom6")] + #[hal_cfg("sercom6")] pub sercom6: ApbToken, - #[cfg(feature = "has-sercom7")] + #[hal_cfg("sercom7")] pub sercom7: ApbToken, - #[cfg(feature = "has-tcc4")] + #[hal_cfg("tcc4")] pub tcc4: ApbToken, - #[cfg(feature = "has-tc6")] + #[hal_cfg("tc6")] pub tc6: ApbToken, - #[cfg(feature = "has-tc7")] + #[hal_cfg("tc7")] pub tc7: ApbToken, pub adc0: ApbToken, pub adc1: ApbToken, pub dac: ApbToken, - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] pub i2s: ApbToken, pub pcc: ApbToken, } @@ -561,6 +564,7 @@ impl ApbTokens { /// /// All invariants required by `ApbToken::new` must be upheld here as well. #[inline] + #[hal_macro_helper] pub(super) unsafe fn new() -> Self { Self { freq_m: ApbToken::new(), @@ -576,12 +580,12 @@ impl ApbTokens { tcc1: ApbToken::new(), tc2: ApbToken::new(), tc3: ApbToken::new(), - #[cfg(feature = "has-tc4")] + #[hal_cfg("tc4")] tc4: ApbToken::new(), tcc2: ApbToken::new(), - #[cfg(feature = "has-tcc3")] + #[hal_cfg("tcc3")] tcc3: ApbToken::new(), - #[cfg(feature = "has-tc5")] + #[hal_cfg("tc5")] tc5: ApbToken::new(), p_dec: ApbToken::new(), ac: ApbToken::new(), @@ -591,20 +595,20 @@ impl ApbTokens { ccl: ApbToken::new(), sercom4: ApbToken::new(), sercom5: ApbToken::new(), - #[cfg(feature = "has-sercom6")] + #[hal_cfg("sercom6")] sercom6: ApbToken::new(), - #[cfg(feature = "has-sercom7")] + #[hal_cfg("sercom7")] sercom7: ApbToken::new(), - #[cfg(feature = "has-tcc4")] + #[hal_cfg("tcc4")] tcc4: ApbToken::new(), - #[cfg(feature = "has-tc6")] + #[hal_cfg("tc6")] tc6: ApbToken::new(), - #[cfg(feature = "has-tc7")] + #[hal_cfg("tc7")] tc7: ApbToken::new(), adc0: ApbToken::new(), adc1: ApbToken::new(), dac: ApbToken::new(), - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] i2s: ApbToken::new(), pcc: ApbToken::new(), } @@ -616,6 +620,7 @@ impl ApbTokens { //============================================================================== /// Set of [`ApbClk`]s for APB clocks that are enabled at power-on reset +#[hal_macro_helper] pub struct ApbClks { pub pac: ApbClk, pub pm: ApbClk, @@ -632,7 +637,7 @@ pub struct ApbClks { pub nvm_ctrl: ApbClk, pub port: ApbClk, pub ram_ecc: ApbClk, - #[cfg(feature = "has-gmac")] + #[hal_cfg("gmac")] pub gmac: ApbClk, pub qspi: ApbClk, } @@ -644,6 +649,7 @@ impl ApbClks { /// /// All invariants required by `ApbToken::new` must be upheld here as well. #[inline] + #[hal_macro_helper] pub(super) unsafe fn new() -> Self { ApbClks { pac: ApbClk::new(ApbToken::new()), @@ -661,7 +667,7 @@ impl ApbClks { nvm_ctrl: ApbClk::new(ApbToken::new()), port: ApbClk::new(ApbToken::new()), ram_ecc: ApbClk::new(ApbToken::new()), - #[cfg(feature = "has-gmac")] + #[hal_cfg("gmac")] gmac: ApbClk::new(ApbToken::new()), qspi: ApbClk::new(ApbToken::new()), } diff --git a/hal/src/peripherals/clock/d5x/v2/gclk.rs b/hal/src/peripherals/clock/d5x/v2/gclk.rs index 71b14bbdb6f..4d37047b89c 100644 --- a/hal/src/peripherals/clock/d5x/v2/gclk.rs +++ b/hal/src/peripherals/clock/d5x/v2/gclk.rs @@ -755,42 +755,53 @@ pub trait GclkIo: PinId { // These implementations are much easier to read with `#[rustfmt::skip]` #[rustfmt::skip] mod gclkio_impl { + use atsamd_hal_macros::hal_cfg; use super::*; + #[hal_cfg("pa10")] impl GclkIo for gpio::PA10 { type GclkId = Gclk4Id; } + #[hal_cfg("pa11")] impl GclkIo for gpio::PA11 { type GclkId = Gclk5Id; } + #[hal_cfg("pa14")] impl GclkIo for gpio::PA14 { type GclkId = Gclk0Id; } + #[hal_cfg("pa15")] impl GclkIo for gpio::PA15 { type GclkId = Gclk1Id; } + #[hal_cfg("pa16")] impl GclkIo for gpio::PA16 { type GclkId = Gclk2Id; } + #[hal_cfg("pa17")] impl GclkIo for gpio::PA17 { type GclkId = Gclk3Id; } + #[hal_cfg("pa27")] impl GclkIo for gpio::PA27 { type GclkId = Gclk1Id; } + #[hal_cfg("pa30")] impl GclkIo for gpio::PA30 { type GclkId = Gclk0Id; } + #[hal_cfg("pb10")] impl GclkIo for gpio::PB10 { type GclkId = Gclk4Id; } + #[hal_cfg("pb11")] impl GclkIo for gpio::PB11 { type GclkId = Gclk5Id; } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] impl GclkIo for gpio::PB12 { type GclkId = Gclk6Id; } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] impl GclkIo for gpio::PB13 { type GclkId = Gclk7Id; } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] impl GclkIo for gpio::PB14 { type GclkId = Gclk0Id; } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] impl GclkIo for gpio::PB15 { type GclkId = Gclk1Id; } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] impl GclkIo for gpio::PB16 { type GclkId = Gclk2Id; } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] impl GclkIo for gpio::PB17 { type GclkId = Gclk3Id; } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb18")] impl GclkIo for gpio::PB18 { type GclkId = Gclk4Id; } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb19")] impl GclkIo for gpio::PB19 { type GclkId = Gclk5Id; } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb20")] impl GclkIo for gpio::PB20 { type GclkId = Gclk6Id; } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb21")] impl GclkIo for gpio::PB21 { type GclkId = Gclk7Id; } - #[cfg(feature = "has-pb22")] + #[hal_cfg("pb22")] impl GclkIo for gpio::PB22 { type GclkId = Gclk0Id; } - #[cfg(feature = "has-pb23")] + #[hal_cfg("pb23")] impl GclkIo for gpio::PB23 { type GclkId = Gclk1Id; } } diff --git a/hal/src/peripherals/clock/d5x/v2/pclk.rs b/hal/src/peripherals/clock/d5x/v2/pclk.rs index 313b8120e34..8ee7c16baba 100644 --- a/hal/src/peripherals/clock/d5x/v2/pclk.rs +++ b/hal/src/peripherals/clock/d5x/v2/pclk.rs @@ -62,6 +62,8 @@ //! [`clock::v2::types`]: super::types //! [`Sercom`]: crate::sercom::Sercom +use atsamd_hal_macros::hal_macro_helper; + use core::marker::PhantomData; use paste::paste; @@ -152,12 +154,13 @@ impl PclkToken

{ /// use atsamd_hal::clock::v2::pclk::ids::*; /// ``` pub mod ids { + use atsamd_hal_macros::hal_cfg; pub use crate::sercom::{Sercom0, Sercom1, Sercom2, Sercom3, Sercom4, Sercom5}; - #[cfg(feature = "has-sercom6")] + #[hal_cfg("sercom6")] pub use crate::sercom::Sercom6; - #[cfg(feature = "has-sercom7")] + #[hal_cfg("sercom7")] pub use crate::sercom::Sercom7; pub use super::super::dfll::DfllId; @@ -169,19 +172,19 @@ pub mod ids { SlowClk, Tc0Tc1, Tc2Tc3, Tcc0Tcc1, Tcc2Tcc3, Usb, }; - #[cfg(feature = "has-can0")] + #[hal_cfg("can0")] pub use super::super::types::Can0; - #[cfg(feature = "has-can1")] + #[hal_cfg("can1")] pub use super::super::types::Can1; - #[cfg(feature = "has-sdhc1")] + #[hal_cfg("sdhc1")] pub use super::super::types::Sdhc1; - #[cfg(all(feature = "has-tc4", feature = "has-tc5"))] + #[hal_cfg(all("tc4", "tc5"))] pub use super::super::types::Tc4Tc5; - #[cfg(all(feature = "has-tc6", feature = "has-tc7"))] + #[hal_cfg(all("tc6", "tc7"))] pub use super::super::types::Tc6Tc7; - #[cfg(feature = "has-tcc4")] + #[hal_cfg("tcc4")] pub use super::super::types::Tcc4; - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] pub use super::super::types::{I2S0, I2S1}; } @@ -221,6 +224,7 @@ use ids::*; /// /// with_pclk_types_ids!(some_macro!(first, second)); /// ``` +#[hal_macro_helper] macro_rules! with_pclk_types_ids { ( $some_macro:ident ! ( $( $args:tt )* ) ) => { $some_macro!( @@ -252,35 +256,35 @@ macro_rules! with_pclk_types_ids { (Sercom3 = 24, sercom3) (Tcc0Tcc1 = 25, tcc0_tcc1) (Tc2Tc3 = 26, tc2_tc3) - #[cfg(feature = "has-can0")] + #[hal_cfg("can0")] (Can0 = 27, can0) - #[cfg(feature = "has-can1")] + #[hal_cfg("can1")] (Can1 = 28, can1) (Tcc2Tcc3 = 29, tcc2_tcc3) - #[cfg(all(feature = "has-tc4", feature = "has-tc5"))] + #[hal_cfg(all("tc4", "tc5"))] (Tc4Tc5 = 30, tc4_tc5) (PDec = 31, pdec) (Ac = 32, ac) (Ccl = 33, ccl) (Sercom4 = 34, sercom4) (Sercom5 = 35, sercom5) - #[cfg(feature = "has-sercom6")] + #[hal_cfg("sercom6")] (Sercom6 = 36, sercom6) - #[cfg(feature = "has-sercom7")] + #[hal_cfg("sercom7")] (Sercom7 = 37, sercom7) - #[cfg(feature = "has-tcc4")] + #[hal_cfg("tcc4")] (Tcc4 = 38, tcc4) - #[cfg(all(feature = "has-tc6", feature = "has-tc7"))] + #[hal_cfg(all("tc6", "tc7"))] (Tc6Tc7 = 39, tc6_tc7) (Adc0 = 40, adc0) (Adc1 = 41, adc1) (Dac = 42, dac) - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] (I2S0 = 43, i2s0) - #[cfg(feature = "has-i2s")] + #[hal_cfg("i2s")] (I2S1 = 44, i2s1) (Sdhc0 = 45, sdhc0) - #[cfg(feature = "has-sdhc1")] + #[hal_cfg("sdhc1")] (Sdhc1 = 46, sdhc1) (CM4Trace = 47, cm4_trace) ); diff --git a/hal/src/peripherals/clock/d5x/v2/types.rs b/hal/src/peripherals/clock/d5x/v2/types.rs index 00174c46534..88bfc43ee22 100644 --- a/hal/src/peripherals/clock/d5x/v2/types.rs +++ b/hal/src/peripherals/clock/d5x/v2/types.rs @@ -17,17 +17,33 @@ //! [`Sercom0`]: crate::sercom::Sercom0 //! [`Sercom1`]: crate::sercom::Sercom1 -use paste::paste; -use seq_macro::seq; +use atsamd_hal_macros::hal_cfg; use crate::typelevel::Sealed; -seq!(N in 0..=7 { - paste! { - #[cfg(feature = "has-" sercom~N)] - pub use crate::sercom::Sercom~N; - } -}); +#[hal_cfg("sercom0")] +pub use crate::sercom::Sercom0; + +#[hal_cfg("sercom1")] +pub use crate::sercom::Sercom1; + +#[hal_cfg("sercom2")] +pub use crate::sercom::Sercom2; + +#[hal_cfg("sercom3")] +pub use crate::sercom::Sercom3; + +#[hal_cfg("sercom4")] +pub use crate::sercom::Sercom4; + +#[hal_cfg("sercom5")] +pub use crate::sercom::Sercom5; + +#[hal_cfg("sercom6")] +pub use crate::sercom::Sercom6; + +#[hal_cfg("sercom7")] +pub use crate::sercom::Sercom7; macro_rules! create_types { ( @@ -50,9 +66,9 @@ macro_rules! create_types { create_types!(Ac); create_types!(Adc0, Adc1); create_types!(Aes); -#[cfg(feature = "has-can0")] +#[hal_cfg("can0")] create_types!(Can0); -#[cfg(feature = "has-can1")] +#[hal_cfg("can1")] create_types!(Can1); create_types!(Ccl); create_types!(Cmcc); @@ -69,13 +85,13 @@ create_types!(FreqM); create_types!(FreqMMeasure); create_types!(FreqMReference); create_types!(Gclk); -#[cfg(feature = "has-gmac")] +#[hal_cfg("gmac")] create_types!(Gmac); create_types!(Hpb0, Hpb1, Hpb2, Hpb3); create_types!(Icm); create_types!(Mclk); create_types!(NvmCtrl, NvmCtrlSmeeProm, NvmCtrlCache); -#[cfg(feature = "has-i2s")] +#[hal_cfg("i2s")] create_types!(I2S, I2S0, I2S1); create_types!(OscCtrl); create_types!(Osc32kCtrl); @@ -90,21 +106,21 @@ create_types!(RamEcc); create_types!(RstC); create_types!(Rtc); create_types!(Sdhc0); -#[cfg(feature = "has-sdhc1")] +#[hal_cfg("sdhc1")] create_types!(Sdhc1); create_types!(SlowClk); create_types!(SupC); create_types!(Tc0Tc1, Tc0, Tc1); create_types!(Tc2Tc3, Tc2, Tc3); -#[cfg(all(feature = "has-tc4", feature = "has-tc5"))] +#[hal_cfg(all("tc4", "tc5"))] create_types!(Tc4Tc5, Tc4, Tc5); -#[cfg(all(feature = "has-tc6", feature = "has-tc7"))] +#[hal_cfg(all("tc6", "tc7"))] create_types!(Tc6Tc7, Tc6, Tc7); create_types!(Tcc0Tcc1, Tcc0, Tcc1); create_types!(Tcc2Tcc3, Tcc2); -#[cfg(feature = "has-tcc3")] +#[hal_cfg("tcc3")] create_types!(Tcc3); -#[cfg(feature = "has-tcc4")] +#[hal_cfg("tcc4")] create_types!(Tcc4); create_types!(Trng); create_types!(Usb); diff --git a/hal/src/peripherals/eic/d11/pin.rs b/hal/src/peripherals/eic/d11/pin.rs index e069bee1b62..55686b395b3 100644 --- a/hal/src/peripherals/eic/d11/pin.rs +++ b/hal/src/peripherals/eic/d11/pin.rs @@ -4,6 +4,7 @@ use crate::gpio::{ self, pin::*, AnyPin, FloatingInterrupt, PinMode, PullDownInterrupt, PullUpInterrupt, }; use crate::pac; +use atsamd_hal_macros::hal_cfg; use super::EIC; @@ -211,173 +212,203 @@ crate::paste::item! { // SAMD11 -#[cfg(feature = "samd11")] +#[hal_cfg("eic-d11")] mod impls { use super::*; ei!(ExtInt[1] { + #[hal_cfg("pa15")] PA15, }); ei!(ExtInt[2] { + #[hal_cfg("pa02")] PA02, }); ei!(ExtInt[3] { + #[hal_cfg("pa31")] PA31, }); ei!(ExtInt[4] { + #[hal_cfg("pa04")] PA04, + #[hal_cfg("pa24")] PA24, }); ei!(ExtInt[5] { + #[hal_cfg("pa05")] PA05, + #[hal_cfg("pa25")] PA25, }); ei!(ExtInt[6] { + #[hal_cfg("pa08")] PA08, }); ei!(ExtInt[7] { + #[hal_cfg("pa09")] PA09, }); } // SAMD21 -#[cfg(feature = "samd21")] +#[hal_cfg("eic-d21")] mod impls { use super::*; ei!(ExtInt[0] { - #[cfg(feature = "has-pa00")] + #[hal_cfg("pa00")] PA00, + #[hal_cfg("pa16")] PA16, - #[cfg(feature = "has-pb00")] + #[hal_cfg("pb00")] PB00, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] PB16, }); ei!(ExtInt[1] { - #[cfg(feature = "has-pa01")] + #[hal_cfg("pa01")] PA01, + #[hal_cfg("pa17")] PA17, - #[cfg(feature = "has-pb01")] + #[hal_cfg("pb01")] PB01, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] PB17, }); ei!(ExtInt[2] { + #[hal_cfg("pa02")] PA02, + #[hal_cfg("pa18")] PA18, - #[cfg(feature = "has-pb02")] + #[hal_cfg("pb02")] PB02, }); ei!(ExtInt[3] { + #[hal_cfg("pa03")] PA03, + #[hal_cfg("pa19")] PA19, - #[cfg(feature = "has-pb03")] + #[hal_cfg("pb03")] PB03, }); ei!(ExtInt[4] { + #[hal_cfg("pa04")] PA04, - #[cfg(feature = "pins-48")] + #[hal_cfg("pa20")] PA20, - #[cfg(feature = "has-pb04")] + #[hal_cfg("pb04")] PB04, }); ei!(ExtInt[5] { + #[hal_cfg("pa05")] PA05, - #[cfg(feature = "pins-48")] + #[hal_cfg("pa21")] PA21, - #[cfg(feature = "has-pb05")] + #[hal_cfg("pb05")] PB05, }); ei!(ExtInt[6] { + #[hal_cfg("pa06")] PA06, + #[hal_cfg("pa22")] PA22, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb06")] PB06, - #[cfg(feature = "has-pb22")] + #[hal_cfg("pb22")] PB22, }); ei!(ExtInt[7] { + #[hal_cfg("pa07")] PA07, + #[hal_cfg("pa23")] PA23, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb07")] PB07, - #[cfg(feature = "has-pb23")] + #[hal_cfg("pb23")] PB23, }); ei!(ExtInt[8] { - #[cfg(feature = "has-pa28")] + #[hal_cfg("pa28")] PA28, - #[cfg(feature = "pins-48")] + #[hal_cfg("pb08")] PB08, }); ei!(ExtInt[9] { + #[hal_cfg("pa09")] PA09, - #[cfg(feature = "pins-48")] + #[hal_cfg("pb09")] PB09, }); ei!(ExtInt[10] { + #[hal_cfg("pa10")] PA10, + #[hal_cfg("pa30")] PA30, - #[cfg(feature = "pins-48")] + #[hal_cfg("pb10")] PB10, }); ei!(ExtInt[11] { - PA11, - PA31, - #[cfg(feature = "pins-48")] - PB11, + #[hal_cfg("pa11")] + PA11, + #[hal_cfg("pa31")] + PA31, + #[hal_cfg("pb11")] + PB11, }); ei!(ExtInt[12] { - #[cfg(feature = "pins-48")] + #[hal_cfg("pa12")] PA12, + #[hal_cfg("pa24")] PA24, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] PB12, }); ei!(ExtInt[13] { - #[cfg(feature = "pins-48")] + #[hal_cfg("pa13")] PA13, + #[hal_cfg("pa25")] PA25, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] PB13, }); ei!(ExtInt[14] { + #[hal_cfg("pa14")] PA14, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] PB14, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb30")] PB30, }); ei!(ExtInt[15] { + #[hal_cfg("pa15")] PA15, - #[cfg(feature = "has-pa27")] + #[hal_cfg("pa27")] PA27, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] PB15, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb31")] PB31, }); } diff --git a/hal/src/peripherals/eic/d5x/pin.rs b/hal/src/peripherals/eic/d5x/pin.rs index a2a5c2df594..6eadaf44131 100644 --- a/hal/src/peripherals/eic/d5x/pin.rs +++ b/hal/src/peripherals/eic/d5x/pin.rs @@ -4,6 +4,7 @@ use crate::gpio::{ self, pin::*, AnyPin, FloatingInterrupt, PinMode, PullDownInterrupt, PullUpInterrupt, }; use crate::pac; +use atsamd_hal_macros::hal_cfg; /// The EicPin trait makes it more ergonomic to convert a gpio pin into an EIC /// pin. You should not implement this trait for yourself; only the @@ -205,209 +206,245 @@ crate::paste::item! { } ei!(ExtInt[0] { + #[hal_cfg("pa00")] PA00, + #[hal_cfg("pa16")] PA16, - #[cfg(feature = "has-pb00")] + #[hal_cfg("pb00")] PB00, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] PB16, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc00")] PC00, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc16")] PC16, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd00")] PD00, }); ei!(ExtInt[1] { + #[hal_cfg("pa01")] PA01, + #[hal_cfg("pa17")] PA17, - #[cfg(feature = "has-pb01")] + #[hal_cfg("pb01")] PB01, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] PB17, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc01")] PC01, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc17")] PC17, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd01")] PD01, }); ei!(ExtInt[2] { + #[hal_cfg("pa02")] PA02, + #[hal_cfg("pa18")] PA18, + #[hal_cfg("pb02")] PB02, - #[cfg(feature = "pins-100")] + #[hal_cfg("pb18")] PB18, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc02")] PC02, - #[cfg(feature = "pins-128")] + #[hal_cfg("pc18")] PC18, }); ei!(ExtInt[3] { + #[hal_cfg("pa03")] PA03, + #[hal_cfg("pa19")] PA19, + #[hal_cfg("pb03")] PB03, - #[cfg(feature = "pins-100")] + #[hal_cfg("pb19")] PB19, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc03")] PC03, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc19")] PC19, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd08")] PD08, }); ei!(ExtInt[4] { + #[hal_cfg("pa04")] PA04, + #[hal_cfg("pa20")] PA20, - #[cfg(feature = "has-pb04")] + #[hal_cfg("pb04")] PB04, - #[cfg(feature = "pins-100")] + #[hal_cfg("pb20")] PB20, - #[cfg(feature = "pins-128")] + #[hal_cfg("pc04")] PC04, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc20")] PC20, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd09")] PD09, }); ei!(ExtInt[5] { + #[hal_cfg("pa05")] PA05, + #[hal_cfg("pa21")] PA21, - #[cfg(feature = "has-pb05")] + #[hal_cfg("pb05")] PB05, - #[cfg(feature = "pins-100")] + #[hal_cfg("pb21")] PB21, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc05")] PC05, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc21")] PC21, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd10")] PD10, }); ei!(ExtInt[6] { + #[hal_cfg("pa06")] PA06, + #[hal_cfg("pa22")] PA22, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb06")] PB06, + #[hal_cfg("pb22")] PB22, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc06")] PC06, - #[cfg(feature = "pins-128")] + #[hal_cfg("pc22")] PC22, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd11")] PD11, }); ei!(ExtInt[7] { + #[hal_cfg("pa07")] PA07, + #[hal_cfg("pa23")] PA23, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb07")] PB07, + #[hal_cfg("pb23")] PB23, - #[cfg(feature = "pins-128")] + #[hal_cfg("pc23")] PC23, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd12")] PD12, }); ei!(ExtInt[8] { + #[hal_cfg("pa24")] PA24, + #[hal_cfg("pb08")] PB08, - #[cfg(feature = "pins-100")] + #[hal_cfg("pb24")] PB24, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc24")] PC24, }); ei!(ExtInt[9] { + #[hal_cfg("pa09")] PA09, + #[hal_cfg("pa25")] PA25, + #[hal_cfg("pb09")] PB09, - #[cfg(feature = "pins-100")] + #[hal_cfg("pb25")] PB25, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc07")] PC07, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc25")] PC25, }); ei!(ExtInt[10] { + #[hal_cfg("pa10")] PA10, + #[hal_cfg("pb10")] PB10, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc10")] PC10, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc26")] PC26, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd20")] PD20, }); ei!(ExtInt[11] { + #[hal_cfg("pa11")] PA11, + #[hal_cfg("pa27")] PA27, + #[hal_cfg("pb11")] PB11, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc11")] PC11, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc27")] PC27, - #[cfg(feature = "pins-128")] + #[hal_cfg("pd21")] PD21, }); ei!(ExtInt[12] { + #[hal_cfg("pa12")] PA12, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] PB12, - #[cfg(feature = "pins-128")] + #[hal_cfg("pb26")] PB26, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc12")] PC12, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc28")] PC28, }); ei!(ExtInt[13] { + #[hal_cfg("pa13")] PA13, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] PB13, - #[cfg(feature = "pins-128")] + #[hal_cfg("pb27")] PB27, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc13")] PC13, }); ei!(ExtInt[14] { + #[hal_cfg("pa14")] PA14, + #[hal_cfg("pa30")] PA30, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] PB14, - #[cfg(feature = "pins-128")] + #[hal_cfg("pb28")] PB28, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb30")] PB30, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc14")] PC14, - #[cfg(feature = "pins-128")] + #[hal_cfg("pc30")] PC30, }); ei!(ExtInt[15] { + #[hal_cfg("pa15")] PA15, + #[hal_cfg("pa31")] PA31, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] PB15, - #[cfg(feature = "pins-128")] + #[hal_cfg("pb29")] PB29, - #[cfg(feature = "pins-64")] + #[hal_cfg("pb31")] PB31, - #[cfg(feature = "pins-100")] + #[hal_cfg("pc15")] PC15, - #[cfg(feature = "pins-128")] + #[hal_cfg("pc31")] PC31, }); diff --git a/hal/src/peripherals/mod.rs b/hal/src/peripherals/mod.rs index 8ee8780d941..08bc37adfff 100644 --- a/hal/src/peripherals/mod.rs +++ b/hal/src/peripherals/mod.rs @@ -1,62 +1,75 @@ -#[cfg(feature = "unproven")] -#[cfg_attr(feature = "thumbv6", path = "adc/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "adc/d5x.rs")] -pub mod adc; - -#[cfg_attr(feature = "thumbv6", path = "calibration/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "calibration/d5x.rs")] -pub mod calibration; - -#[cfg_attr(feature = "thumbv6", path = "timer/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "timer/d5x.rs")] -pub mod timer; - -#[cfg_attr(feature = "thumbv6", path = "eic/d11/mod.rs")] -#[cfg_attr(feature = "thumbv7", path = "eic/d5x/mod.rs")] -pub mod eic; +use atsamd_hal_macros::{hal_cfg, hal_module}; -#[cfg(all(feature = "usb", feature = "has-usb"))] -#[cfg_attr(feature = "thumbv6", path = "usb/d11/mod.rs")] -#[cfg_attr(feature = "thumbv7", path = "usb/d5x/mod.rs")] -pub mod usb; +#[cfg(feature = "unproven")] +#[hal_module( + any("adc-d11", "adc-d21") => "adc/d11.rs", + "adc-d5x" => "adc/d5x.rs", +)] +pub mod adc {} + +#[hal_module( + any("nvmctrl-d11", "nvmctrl-d21") => "calibration/d11.rs", + "nvmctrl-d5x" => "calibration/d5x.rs", +)] +pub mod calibration {} + +#[hal_module( + any("clock-d11", "clock-d21") => "timer/d11.rs", + "clock-d5x" => "timer/d5x.rs", +)] +pub mod timer {} + +#[hal_module( + any("eic-d11", "eic-d21") => "eic/d11/mod.rs", + "eic-d5x" => "eic/d5x/mod.rs", +)] +pub mod eic {} + +#[cfg(feature = "usb")] +#[hal_module( + any("usb-d11", "usb-d21") => "usb/d11/mod.rs", + "usb-d5x" => "usb/d5x/mod.rs", +)] +pub mod usb {} #[cfg(feature = "unproven")] -#[cfg_attr(feature = "thumbv6", path = "pwm/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "pwm/d5x.rs")] -pub mod pwm; +#[hal_module( + any("clock-d11", "clock-d21") => "pwm/d11.rs", + "clock-d5x" => "pwm/d5x.rs", +)] +pub mod pwm {} -#[cfg_attr(feature = "thumbv6", path = "clock/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "clock/d5x/mod.rs")] -pub mod clock; +#[hal_module( + any("clock-d11", "clock-d21") => "clock/d11.rs", + "clock-d5x" => "clock/d5x/mod.rs", +)] +pub mod clock {} -#[cfg(feature = "thumbv7")] -pub mod aes; +#[hal_module("aes")] +pub mod aes {} -#[cfg(feature = "thumbv7")] -pub mod dsu; +#[hal_module("dsu-d5x")] +pub mod dsu {} -#[cfg(feature = "thumbv7")] -pub mod pukcc; +#[hal_module("pukcc")] +pub mod pukcc {} -#[cfg(feature = "thumbv7")] -pub mod qspi; +#[hal_module("qspi")] +pub mod qspi {} -#[cfg(feature = "thumbv7")] -pub mod trng; +#[hal_module("trng")] +pub mod trng {} #[cfg(feature = "unproven")] -#[cfg(feature = "thumbv7")] -pub mod icm; - -#[cfg(feature = "thumbv7")] -pub mod nvm; - -#[cfg(all( - any(feature = "has-can0", feature = "has-can1"), - feature = "can", - feature = "thumbv7" -))] -pub mod can; +#[hal_module("icm")] +pub mod icm {} + +#[hal_module("nvmctrl-d5x")] +pub mod nvm {} + +#[cfg(feature = "can")] +#[hal_module(any("can0", "can1"))] +pub mod can {} #[cfg(feature = "unproven")] #[cfg_attr(feature = "thumbv6", path = "watchdog/d11.rs")] diff --git a/hal/src/peripherals/pwm/d11.rs b/hal/src/peripherals/pwm/d11.rs index 04125d650e3..1d6be00d923 100644 --- a/hal/src/peripherals/pwm/d11.rs +++ b/hal/src/peripherals/pwm/d11.rs @@ -1,5 +1,4 @@ -use paste::paste; -use seq_macro::seq; +use atsamd_hal_macros::hal_cfg; use crate::clock; use crate::ehal::{Pwm, PwmPin}; @@ -7,20 +6,6 @@ use crate::pac::PM; use crate::time::Hertz; use crate::timer_params::TimerParams; -seq!(N in 1..=7 { - paste! { - #[cfg(feature = "has-" tc~N)] - use crate::pac::TC~N; - } -}); - -seq!(N in 0..=2 { - paste! { - #[cfg(feature = "has-" tcc~N)] - use crate::pac::TCC~N; - } -}); - // Timer/Counter (TCx) macro_rules! pwm { @@ -31,14 +16,14 @@ pub struct $TYPE { /// The frequency of the attached clock, not the period of the pwm. /// Used to calculate the period of the pwm. clock_freq: Hertz, - tc: $TC, + tc: crate::pac::$TC, } impl $TYPE { pub fn new( clock: &clock::$clock, freq: Hertz, - tc: $TC, + tc: crate::pac::$TC, pm: &mut PM, ) -> Self { let count = tc.count16(); @@ -134,20 +119,20 @@ impl PwmPin for $TYPE { )+}} -#[cfg(feature = "has-tc1")] +#[hal_cfg("tc1")] pwm! { Pwm1: (TC1, Tc1Tc2Clock, apbcmask, tc1_, Pwm1Wrapper) } -#[cfg(feature = "has-tc2")] +#[hal_cfg("tc2")] pwm! { Pwm2: (TC2, Tc1Tc2Clock, apbcmask, tc2_, Pwm2Wrapper) } -#[cfg(feature = "has-tc3")] +#[hal_cfg("tc3")] pwm! { Pwm3: (TC3, Tcc2Tc3Clock, apbcmask, tc3_, Pwm3Wrapper) } -#[cfg(feature = "has-tc4")] +#[hal_cfg("tc4")] pwm! { Pwm4: (TC4, Tc4Tc5Clock, apbcmask, tc4_, Pwm4Wrapper) } -#[cfg(feature = "has-tc5")] +#[hal_cfg("tc5")] pwm! { Pwm5: (TC5, Tc4Tc5Clock, apbcmask, tc5_, Pwm5Wrapper) } -#[cfg(feature = "has-tc6")] +#[hal_cfg("tc6")] pwm! { Pwm6: (TC6, Tc6Tc7Clock, apbcmask, tc6_, Pwm6Wrapper) } -#[cfg(feature = "has-tc7")] +#[hal_cfg("tc7")] pwm! { Pwm7: (TC7, Tc6Tc7Clock, apbcmask, tc7_, Pwm7Wrapper) } // Timer/Counter for Control Applications (TCCx) @@ -168,14 +153,14 @@ pub struct $TYPE { /// The frequency of the attached clock, not the period of the pwm. /// Used to calculate the period of the pwm. clock_freq: Hertz, - tcc: $TCC, + tcc: crate::pac::$TCC, } impl $TYPE { pub fn new> ( clock: &clock::$clock, freq: F, - tcc: $TCC, + tcc: crate::pac::$TCC, pm: &mut PM, ) -> Self { let freq = freq.into(); @@ -277,11 +262,11 @@ impl Pwm for $TYPE { )+}} -#[cfg(all(feature = "samd11", feature = "has-tcc0"))] +#[hal_cfg("tcc0-d11")] pwm_tcc! { Pwm0: (TCC0, Tcc0Clock, apbcmask, tcc0_, Pwm0Wrapper) } -#[cfg(all(feature = "samd21", feature = "has-tcc0"))] +#[hal_cfg("tcc0-d21")] pwm_tcc! { Pwm0: (TCC0, Tcc0Tcc1Clock, apbcmask, tcc0_, Pwm0Wrapper) } -#[cfg(feature = "has-tcc1")] +#[hal_cfg("tcc1")] pwm_tcc! { Pwm1: (TCC1, Tcc0Tcc1Clock, apbcmask, tcc1_, Pwm1Wrapper) } -#[cfg(feature = "has-tcc1")] +#[hal_cfg("tcc1")] pwm_tcc! { Pwm2: (TCC2, Tcc2Tc3Clock, apbcmask, tcc2_, Pwm2Wrapper) } diff --git a/hal/src/peripherals/pwm/d5x.rs b/hal/src/peripherals/pwm/d5x.rs index b6fafd595e3..98b24edc32b 100644 --- a/hal/src/peripherals/pwm/d5x.rs +++ b/hal/src/peripherals/pwm/d5x.rs @@ -1,7 +1,6 @@ #![allow(non_snake_case)] -use paste::paste; -use seq_macro::seq; +use atsamd_hal_macros::hal_cfg; use crate::clock; use crate::ehal::{Pwm, PwmPin}; @@ -11,20 +10,6 @@ use crate::pac::MCLK; use crate::time::Hertz; use crate::timer_params::TimerParams; -seq!(N in 0..=7 { - paste! { - #[cfg(feature = "has-" tc~N)] - use crate::pac::TC~N; - } -}); - -seq!(N in 0..=4 { - paste! { - #[cfg(feature = "has-" tcc~N)] - use crate::pac::TCC~N; - } -}); - // Timer/Counter (TCx) /// This is a major syntax hack. @@ -69,67 +54,79 @@ macro_rules! impl_tc_pinout { }; } -#[cfg(feature = "has-tc0")] +#[hal_cfg("tc0")] impl_tc_pinout!(TC0Pinout: [ + #[hal_cfg("pa05")] (Pa5, PA05), + #[hal_cfg("pa09")] (Pa9, PA09), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb31")] (Pb31, PB31) ]); -#[cfg(feature = "has-tc1")] +#[hal_cfg("tc1")] impl_tc_pinout!(TC1Pinout: [ + #[hal_cfg("pa07")] (Pa7, PA07), + #[hal_cfg("pa11")] (Pa11, PA11) ]); -#[cfg(feature = "has-tc2")] +#[hal_cfg("tc2")] impl_tc_pinout!(TC2Pinout: [ - #[cfg(feature = "has-pa01")] + #[hal_cfg("pa01")] (Pa1, PA01), + #[hal_cfg("pa13")] (Pa13, PA13), + #[hal_cfg("pa17")] (Pa17, PA17) ]); -#[cfg(feature = "has-tc3")] +#[hal_cfg("tc3")] impl_tc_pinout!(TC3Pinout: [ + #[hal_cfg("pa15")] (Pa15, PA15), + #[hal_cfg("pa19")] (Pa19, PA19) ]); -#[cfg(feature = "has-tc4")] +#[hal_cfg("tc4")] impl_tc_pinout!(TC4Pinout: [ + #[hal_cfg("pa23")] (Pa23, PA23), - #[cfg(feature = "pins-48")] + #[hal_cfg("pb09")] (Pb9, PB09), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] (Pb13, PB13) ]); -#[cfg(feature = "has-tc5")] +#[hal_cfg("tc5")] impl_tc_pinout!(TC5Pinout: [ + #[hal_cfg("pa25")] (Pa25, PA25), + #[hal_cfg("pb11")] (Pb11, PB11), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] (Pb15, PB15) ]); -#[cfg(feature = "has-tc6")] +#[hal_cfg("tc6")] impl_tc_pinout!(TC6Pinout: [ - #[cfg(feature = "has-pb03")] + #[hal_cfg("pb03")] (Pb3, PB03), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] (Pb17, PB17), - #[cfg(feature = "pins-64")] + #[hal_cfg("pa31")] (Pa31, PA31) ]); -#[cfg(feature = "has-tc7")] +#[hal_cfg("tc7")] impl_tc_pinout!(TC7Pinout: [ + #[hal_cfg("pa21")] (Pa21, PA21), - #[cfg(feature = "has-pb23")] + #[hal_cfg("pb23")] (Pb23, PB23), - #[cfg(feature = "has-pb01")] + #[hal_cfg("pb01")] (Pb1, PB01) ]); @@ -141,7 +138,7 @@ pub struct $TYPE { /// The frequency of the attached clock, not the period of the pwm. /// Used to calculate the period of the pwm. clock_freq: Hertz, - tc: $TC, + tc: crate::pac::$TC, #[allow(dead_code)] pinout: $pinout, } @@ -150,7 +147,7 @@ impl $TYPE { pub fn new( clock: &clock::$clock, freq: Hertz, - tc: $TC, + tc: crate::pac::$TC, pinout: $pinout, mclk: &mut MCLK, ) -> Self { @@ -253,21 +250,21 @@ impl PwmPin for $TYPE { )+}} -#[cfg(feature = "has-tc0")] +#[hal_cfg("tc0")] pwm! { Pwm0: (TC0, TC0Pinout, Tc0Tc1Clock, apbamask, tc0_, Pwm0Wrapper) } -#[cfg(feature = "has-tc1")] +#[hal_cfg("tc1")] pwm! { Pwm1: (TC1, TC1Pinout, Tc0Tc1Clock, apbamask, tc1_, Pwm1Wrapper) } -#[cfg(feature = "has-tc2")] +#[hal_cfg("tc2")] pwm! { Pwm2: (TC2, TC2Pinout, Tc2Tc3Clock, apbbmask, tc2_, Pwm2Wrapper) } -#[cfg(feature = "has-tc3")] +#[hal_cfg("tc3")] pwm! { Pwm3: (TC3, TC3Pinout, Tc2Tc3Clock, apbbmask, tc3_, Pwm3Wrapper) } -#[cfg(feature = "has-tc4")] +#[hal_cfg("tc4")] pwm! { Pwm4: (TC4, TC4Pinout, Tc4Tc5Clock, apbcmask, tc4_, Pwm4Wrapper) } -#[cfg(feature = "has-tc5")] +#[hal_cfg("tc5")] pwm! { Pwm5: (TC5, TC5Pinout, Tc4Tc5Clock, apbcmask, tc5_, Pwm5Wrapper) } -#[cfg(feature = "has-tc6")] +#[hal_cfg("tc6")] pwm! { Pwm6: (TC6, TC6Pinout, Tc6Tc7Clock, apbdmask, tc6_, Pwm6Wrapper) } -#[cfg(feature = "has-tc7")] +#[hal_cfg("tc7")] pwm! { Pwm7: (TC7, TC7Pinout, Tc6Tc7Clock, apbdmask, tc7_, Pwm7Wrapper) } // Timer/Counter for Control Applications (TCCx) @@ -326,168 +323,207 @@ macro_rules! impl_tcc_pinout { }; } -#[cfg(feature = "has-tcc0")] +#[hal_cfg("tcc0")] impl_tcc_pinout!(TCC0Pinout: [ + #[hal_cfg("pa08")] (Pa8, PA08, AlternateF), + #[hal_cfg("pa09")] (Pa9, PA09, AlternateF), + #[hal_cfg("pa10")] (Pa10, PA10, AlternateF), + #[hal_cfg("pa11")] (Pa11, PA11, AlternateF), + #[hal_cfg("pa12")] (Pa12, PA12, AlternateF), + #[hal_cfg("pa13")] (Pa13, PA13, AlternateF), + #[hal_cfg("pa16")] (Pa16, PA16, AlternateG), + #[hal_cfg("pa17")] (Pa17, PA17, AlternateG), + #[hal_cfg("pa18")] (Pa18, PA18, AlternateG), + #[hal_cfg("pa19")] (Pa19, PA19, AlternateG), + #[hal_cfg("pa20")] (Pa20, PA20, AlternateG), + #[hal_cfg("pa21")] (Pa21, PA21, AlternateG), + #[hal_cfg("pa22")] (Pa22, PA22, AlternateG), + #[hal_cfg("pa23")] (Pa23, PA23, AlternateG), + #[hal_cfg("pb10")] (Pb10, PB10, AlternateF), + #[hal_cfg("pb11")] (Pb11, PB11, AlternateF), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] (Pb12, PB12, AlternateG), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] (Pb13, PB13, AlternateG), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] (Pb14, PB14, AlternateG), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] (Pb15, PB15, AlternateG), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] (Pb16, PB16, AlternateG), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] (Pb17, PB17, AlternateG), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb30")] (Pb30, PB30, AlternateG), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb31")] (Pb31, PB31, AlternateG), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc10")] (Pc10, PC10, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc11")] (Pc11, PC11, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc12")] (Pc12, PC12, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc13")] (Pc13, PC13, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc14")] (Pc14, PC14, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc15")] (Pc15, PC15, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc16")] (Pc16, PC16, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc17")] (Pc17, PC17, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc18")] (Pc18, PC18, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc19")] (Pc19, PC19, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc20")] (Pc20, PC20, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc21")] (Pc21, PC21, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc04")] (Pc4, PC04, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc22")] (Pc22, PC22, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pc23")] (Pc23, PC23, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd08")] (Pd8, PD08, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd09")] (Pd9, PD09, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd10")] (Pd10, PD10, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd11")] (Pd11, PD11, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd12")] (Pd12, PD12, AlternateF) ]); -#[cfg(feature = "has-tcc1")] +#[hal_cfg("tcc1")] impl_tcc_pinout!(TCC1Pinout: [ + #[hal_cfg("pa08")] (Pa8, PA08, AlternateG), + #[hal_cfg("pa09")] (Pa9, PA09, AlternateG), + #[hal_cfg("pa10")] (Pa10, PA10, AlternateG), + #[hal_cfg("pa11")] (Pa11, PA11, AlternateG), + #[hal_cfg("pa12")] (Pa12, PA12, AlternateG), + #[hal_cfg("pa13")] (Pa13, PA13, AlternateG), + #[hal_cfg("pa14")] (Pa14, PA14, AlternateG), + #[hal_cfg("pa15")] (Pa15, PA15, AlternateG), + #[hal_cfg("pa16")] (Pa16, PA16, AlternateF), + #[hal_cfg("pa17")] (Pa17, PA17, AlternateF), + #[hal_cfg("pa18")] (Pa18, PA18, AlternateF), + #[hal_cfg("pa19")] (Pa19, PA19, AlternateF), + #[hal_cfg("pa20")] (Pa20, PA20, AlternateF), + #[hal_cfg("pa21")] (Pa21, PA21, AlternateF), + #[hal_cfg("pa22")] (Pa22, PA22, AlternateF), + #[hal_cfg("pa23")] (Pa23, PA23, AlternateF), + #[hal_cfg("pb10")] (Pb10, PB10, AlternateG), + #[hal_cfg("pb11")] (Pb11, PB11, AlternateG), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb18")] (Pb18, PB18, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb19")] (Pb19, PB19, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb20")] (Pb20, PB20, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pb21")] (Pb21, PB21, AlternateF), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc10")] (Pc10, PC10, AlternateG), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc11")] (Pc11, PC11, AlternateG), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc12")] (Pc12, PC12, AlternateG), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc13")] (Pc13, PC13, AlternateG), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc14")] (Pc14, PC14, AlternateG), - #[cfg(feature = "pins-100")] + #[hal_cfg("pc15")] (Pc15, PC15, AlternateG), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb26")] (Pb26, PB26, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb27")] (Pb27, PB27, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb28")] (Pb28, PB28, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pb29")] (Pb29, PB29, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd20")] (Pd20, PD20, AlternateF), - #[cfg(feature = "pins-128")] + #[hal_cfg("pd21")] (Pd21, PD21, AlternateF) ]); -#[cfg(feature = "has-tcc2")] +#[hal_cfg("tcc2")] impl_tcc_pinout!(TCC2Pinout: [ + #[hal_cfg("pa14")] (Pa14, PA14, AlternateF), + #[hal_cfg("pa15")] (Pa15, PA15, AlternateF), + #[hal_cfg("pa24")] (Pa24, PA24, AlternateF), + #[hal_cfg("pa30")] (Pa30, PA30, AlternateF), + #[hal_cfg("pa31")] (Pa31, PA31, AlternateF), - #[cfg(feature = "has-pb02")] + #[hal_cfg("pb02")] (Pb2, PB02, AlternateF) ]); -#[cfg(feature = "has-tcc3")] +#[hal_cfg("tcc3")] impl_tcc_pinout!(TCC3Pinout: [ - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] (Pb12, PB12, AlternateF), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] (Pb13, PB13, AlternateF), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] (Pb16, PB16, AlternateF), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] (Pb17, PB17, AlternateF) ]); -#[cfg(feature = "has-tcc4")] +#[hal_cfg("tcc4")] impl_tcc_pinout!(TCC4Pinout: [ - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] (Pb14, PB14, AlternateF), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] (Pb15, PB15, AlternateF), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb30")] (Pb30, PB30, AlternateF), - #[cfg(feature = "pins-64")] + #[hal_cfg("pb31")] (Pb31, PB31, AlternateF) ]); @@ -499,7 +535,7 @@ pub struct $TYPE { /// The frequency of the attached clock, not the period of the pwm. /// Used to calculate the period of the pwm. clock_freq: Hertz, - tcc: $TCC, + tcc: crate::pac::$TCC, #[allow(dead_code)] pinout: $pinout, } @@ -508,7 +544,7 @@ impl $TYPE { pub fn new( clock: &clock::$clock, freq: Hertz, - tcc: $TCC, + tcc: crate::pac::$TCC, pinout: $pinout, mclk: &mut MCLK, ) -> Self { @@ -614,13 +650,13 @@ impl Pwm for $TYPE { }; } -#[cfg(feature = "has-tcc0")] +#[hal_cfg("tcc0")] pwm_tcc! { Tcc0Pwm: (TCC0, TCC0Pinout, Tcc0Tcc1Clock, apbbmask, tcc0_, TccPwm0Wrapper) } -#[cfg(feature = "has-tcc1")] +#[hal_cfg("tcc1")] pwm_tcc! { Tcc1Pwm: (TCC1, TCC1Pinout, Tcc0Tcc1Clock, apbbmask, tcc1_, TccPwm1Wrapper) } -#[cfg(feature = "has-tcc2")] +#[hal_cfg("tcc2")] pwm_tcc! { Tcc2Pwm: (TCC2, TCC2Pinout, Tcc2Tcc3Clock, apbcmask, tcc2_, TccPwm2Wrapper) } -#[cfg(feature = "has-tcc3")] +#[hal_cfg("tcc3")] pwm_tcc! { Tcc3Pwm: (TCC3, TCC3Pinout, Tcc2Tcc3Clock, apbcmask, tcc3_, TccPwm3Wrapper) } -#[cfg(feature = "has-tcc4")] +#[hal_cfg("tcc4")] pwm_tcc! { Tcc4Pwm: (TCC4, TCC4Pinout, Tcc4Clock, apbdmask, tcc4_, TccPwm4Wrapper) } diff --git a/hal/src/peripherals/timer/d11.rs b/hal/src/peripherals/timer/d11.rs index 47889dcb6f3..e31ab1c3c15 100644 --- a/hal/src/peripherals/timer/d11.rs +++ b/hal/src/peripherals/timer/d11.rs @@ -1,9 +1,11 @@ //! Working with timer counter hardware +use atsamd_hal_macros::hal_cfg; + use crate::ehal::timer::{CountDown, Periodic}; use crate::pac::PM; -#[cfg(feature = "samd11")] +#[hal_cfg("tc1-d11")] use crate::pac::{tc1::COUNT16, TC1}; -#[cfg(feature = "samd21")] +#[hal_cfg("tc3-d21")] use crate::pac::{tc3::COUNT16, TC3, TC4, TC5}; use crate::timer_params::TimerParams; @@ -169,12 +171,12 @@ impl TimerCounter<$TC> } // samd11 -#[cfg(feature = "samd11")] +#[hal_cfg("tc1-d11")] tc! { TimerCounter1: (TC1, tc1_, Tc1Tc2Clock), } // samd21 -#[cfg(feature = "samd21")] +#[hal_cfg("tc3-d21")] tc! { TimerCounter3: (TC3, tc3_, Tcc2Tc3Clock), TimerCounter4: (TC4, tc4_, Tc4Tc5Clock), diff --git a/hal/src/peripherals/timer/d5x.rs b/hal/src/peripherals/timer/d5x.rs index f4c03bc9a2d..b841f2ee1e1 100644 --- a/hal/src/peripherals/timer/d5x.rs +++ b/hal/src/peripherals/timer/d5x.rs @@ -1,8 +1,10 @@ //! Working with timer counter hardware +use atsamd_hal_macros::hal_cfg; + use crate::ehal::timer::{CountDown, Periodic}; use crate::pac::tc0::COUNT16; use crate::pac::{MCLK, TC2, TC3}; -#[cfg(all(feature = "has-tc4", feature = "has-tc5"))] +#[hal_cfg(all("tc4", "tc5"))] use crate::pac::{TC4, TC5}; use crate::timer_params::TimerParams; use crate::timer_traits::InterruptDrivenTimer; @@ -173,7 +175,7 @@ tc! { TimerCounter3: (TC3, tc3_, Tc2Tc3Clock, apbbmask), } -#[cfg(all(feature = "has-tc4", feature = "has-tc5"))] +#[hal_cfg(all("tc4", "tc5"))] tc! { TimerCounter4: (TC4, tc4_, Tc4Tc5Clock, apbcmask), TimerCounter5: (TC5, tc5_, Tc4Tc5Clock, apbcmask), diff --git a/hal/src/rtc.rs b/hal/src/rtc.rs index 06e5f28e5df..6596fd8dfbf 100644 --- a/hal/src/rtc.rs +++ b/hal/src/rtc.rs @@ -1,4 +1,6 @@ //! Real-time clock/counter +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use crate::ehal::timer::{CountDown, Periodic}; use crate::pac::rtc::{MODE0, MODE2}; use crate::pac::RTC; @@ -21,14 +23,14 @@ pub type Duration = fugit::Duration; use rtic_monotonic::Monotonic; // SAMx5x imports -#[cfg(feature = "thumbv7")] +#[hal_cfg("rtc-d5x")] use crate::pac::{ rtc::mode0::ctrla::PRESCALERSELECT_A, rtc::mode0::CTRLA as MODE0_CTRLA, rtc::mode2::CTRLA as MODE2_CTRLA, MCLK as PM, }; // SAMD11/SAMD21 imports -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("rtc-d11", "rtc-d21"))] use crate::pac::{ rtc::mode0::ctrl::PRESCALERSELECT_A, rtc::mode0::CTRL as MODE0_CTRLA, rtc::mode2::CTRL as MODE2_CTRLA, PM, @@ -98,6 +100,7 @@ pub struct Rtc { _mode: PhantomData, } +#[hal_macro_helper] impl Rtc { // --- Helper Functions for M0 vs M4 targets #[inline] @@ -112,25 +115,25 @@ impl Rtc { #[inline] fn mode0_ctrla(&self) -> &MODE0_CTRLA { - #[cfg(feature = "thumbv7")] + #[hal_cfg("rtc-d5x")] return &self.mode0().ctrla; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("rtc-d11", "rtc-d21"))] return &self.mode0().ctrl; } #[inline] fn mode2_ctrla(&self) -> &MODE2_CTRLA { - #[cfg(feature = "thumbv7")] + #[hal_cfg("rtc-d5x")] return &self.mode2().ctrla; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("rtc-d11", "rtc-d21"))] return &self.mode2().ctrl; } #[inline] fn sync(&self) { - #[cfg(feature = "thumbv7")] + #[hal_cfg("rtc-d5x")] while self.mode2().syncbusy.read().bits() != 0 {} - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("rtc-d11", "rtc-d21"))] while self.mode2().status.read().syncbusy().bit_is_set() {} } @@ -174,7 +177,7 @@ impl Rtc { self.sync(); // enable clock sync on SAMx5x - #[cfg(feature = "thumbv7")] + #[hal_cfg("rtc-d5x")] { self.mode2_ctrla().modify(|_, w| { w.clocksync().set_bit() // synchronize the CLOCK register @@ -208,7 +211,7 @@ impl Rtc { }); // enable clock sync on SAMx5x - #[cfg(feature = "thumbv7")] + #[hal_cfg("rtc-d5x")] { self.mode2_ctrla().modify(|_, w| { w.clocksync().set_bit() // synchronize the CLOCK register @@ -247,9 +250,10 @@ impl Rtc { /// Returns the internal counter value. #[inline] + #[hal_macro_helper] pub fn count32(&self) -> u32 { // synchronize this read on SAMD11/21. SAMx5x is automatically synchronized - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("rtc-d11", "rtc-d21"))] { self.mode0().readreq.modify(|_, w| w.rcont().set_bit()); self.sync(); @@ -309,9 +313,10 @@ impl Rtc { } /// Returns the current clock/calendar value. + #[hal_macro_helper] pub fn current_time(&self) -> Datetime { // synchronize this read on SAMD11/21. SAMx5x is automatically synchronized - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("rtc-d11", "rtc-d21"))] { self.mode2().readreq.modify(|_, w| w.rcont().set_bit()); self.sync(); diff --git a/hal/src/sercom/dma.rs b/hal/src/sercom/dma.rs index 070ef41be13..b4ee63bc3d3 100644 --- a/hal/src/sercom/dma.rs +++ b/hal/src/sercom/dma.rs @@ -3,6 +3,8 @@ //! See the [`mod@uart`], [`mod@i2c`] and [`mod@spi`] modules for the //! corresponding DMA transfer implementations. +use atsamd_hal_macros::hal_macro_helper; + use crate::{ dmac::{ self, @@ -77,6 +79,7 @@ impl I2c { /// /// It is recommended that you check for errors after the transfer is /// complete by calling [`read_status`](I2c::read_status). + #[hal_macro_helper] pub fn receive_with_dma( self, address: u8, @@ -97,10 +100,10 @@ impl I2c { .as_mut() .enable_interrupts(InterruptFlags::new().with_tcmpl(true)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] let trigger_action = TriggerAction::BURST; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -125,6 +128,7 @@ impl I2c { /// It is recommended that you check for errors after the transfer is /// complete by calling [`read_status`](I2c::read_status). #[inline] + #[hal_macro_helper] pub fn send_with_dma( self, address: u8, @@ -145,10 +149,10 @@ impl I2c { .as_mut() .enable_interrupts(InterruptFlags::new().with_tcmpl(true)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] let trigger_action = TriggerAction::BURST; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -206,6 +210,7 @@ where /// Transform an [`Uart`] into a DMA [`Transfer`]) and /// start receiving into the provided buffer. #[inline] + #[hal_macro_helper] pub fn receive_with_dma( self, buf: B, @@ -221,10 +226,10 @@ where .as_mut() .enable_interrupts(InterruptFlags::new().with_tcmpl(true)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] let trigger_action = TriggerAction::BURST; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -244,6 +249,7 @@ where /// Transform an [`Uart`] into a DMA [`Transfer`]) and /// start sending the provided buffer. #[inline] + #[hal_macro_helper] pub fn send_with_dma( self, buf: B, @@ -259,10 +265,10 @@ where .as_mut() .enable_interrupts(InterruptFlags::new().with_tcmpl(true)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] let trigger_action = TriggerAction::BURST; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -312,6 +318,7 @@ where /// Transform an [`Spi`] into a DMA [`Transfer`]) and /// start a send transaction. #[inline] + #[hal_macro_helper] pub fn send_with_dma( self, buf: B, @@ -327,10 +334,10 @@ where .as_mut() .enable_interrupts(InterruptFlags::new().with_tcmpl(true)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] let trigger_action = TriggerAction::BURST; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -350,6 +357,7 @@ where /// Transform an [`Spi`] into a DMA [`Transfer`]) and /// start a receive transaction. #[inline] + #[hal_macro_helper] pub fn receive_with_dma( self, buf: B, @@ -365,10 +373,10 @@ where .as_mut() .enable_interrupts(InterruptFlags::new().with_tcmpl(true)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] let trigger_action = TriggerAction::BURST; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check diff --git a/hal/src/sercom/i2c.rs b/hal/src/sercom/i2c.rs index 24c036b48aa..c45acdd3d72 100644 --- a/hal/src/sercom/i2c.rs +++ b/hal/src/sercom/i2c.rs @@ -255,13 +255,13 @@ fn i2c_send_with_dma>(i2c: I2c, c " )] -#[cfg(feature = "thumbv6")] -#[path = "i2c/pads_thumbv6m.rs"] -mod pads; +use atsamd_hal_macros::hal_module; -#[cfg(feature = "thumbv7")] -#[path = "i2c/pads_thumbv7em.rs"] -mod pads; +#[hal_module( + any("sercom0-d11", "sercom0-d21") => "i2c/pads_thumbv6m.rs", + "sercom0-d5x" => "i2c/pads_thumbv7em.rs", +)] +mod pads {} pub use pads::*; diff --git a/hal/src/sercom/i2c/pads_thumbv6m.rs b/hal/src/sercom/i2c/pads_thumbv6m.rs index 7bd11070c3a..76019fa414c 100644 --- a/hal/src/sercom/i2c/pads_thumbv6m.rs +++ b/hal/src/sercom/i2c/pads_thumbv6m.rs @@ -3,6 +3,8 @@ //! See the [i2c module](super) documentation for more details on declaring and //! instantiating a [`Pads`] type. +use atsamd_hal_macros::hal_cfg; + use crate::{gpio::AnyPin, sercom::*, typelevel::Sealed}; use core::marker::PhantomData; @@ -21,7 +23,7 @@ where scl: SCL, } -#[cfg(feature = "samd11")] +#[hal_cfg("sercom0-d11")] impl PadsFromIds where S: Sercom, @@ -42,7 +44,7 @@ where } } -#[cfg(not(feature = "samd11"))] +#[hal_cfg("sercom0-d21")] impl PadsFromIds where S: Sercom, @@ -107,7 +109,7 @@ where /// /// [`Pin`]: crate::gpio::Pin /// [`PinId`]: crate::gpio::PinId -#[cfg(feature = "samd11")] +#[hal_cfg("sercom0-d11")] pub type PadsFromIds = Pads, Pad>; /// Define a set of [`Pads`] using [`PinId`]s instead of [`Pin`]s @@ -136,7 +138,7 @@ pub type PadsFromIds = Pads, Pad /// /// [`Pin`]: crate::gpio::Pin /// [`PinId`]: crate::gpio::PinId -#[cfg(feature = "samd21")] +#[hal_cfg("sercom0-d21")] pub type PadsFromIds = Pads, Pad>; //============================================================================= diff --git a/hal/src/sercom/mod.rs b/hal/src/sercom/mod.rs index cfeca08a18e..49e3efd4b74 100644 --- a/hal/src/sercom/mod.rs +++ b/hal/src/sercom/mod.rs @@ -29,17 +29,16 @@ //! [`PB03`]: crate::gpio::pin::PB03 //! [`IsI2cPad`]: pad::IsI2cPad -use core::ops::Deref; +use atsamd_hal_macros::hal_cfg; -use paste::paste; -use seq_macro::seq; +use core::ops::Deref; use crate::pac; use pac::sercom0; -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] use pac::MCLK as APB_CLK_CTRL; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] use pac::PM as APB_CLK_CTRL; #[cfg(feature = "dma")] @@ -77,39 +76,65 @@ pub trait Sercom: Sealed + Deref { } macro_rules! sercom { - ( $apbmask:ident: ($start:literal, $end:literal) ) => { - seq!(N in $start..=$end { - paste! { - #[cfg(feature = "has-" sercom~N)] - use pac::SERCOM~N; - /// Type alias for the corresponding SERCOM instance - #[cfg(feature = "has-" sercom~N)] - pub type Sercom~N = SERCOM~N; - #[cfg(feature = "has-" sercom~N)] - impl Sealed for Sercom~N {} - #[cfg(feature = "has-" sercom~N)] - impl Sercom for Sercom~N { - const NUM: usize = N; - #[cfg(feature = "dma")] - const DMA_RX_TRIGGER: TriggerSource = TriggerSource::[]; - #[cfg(feature = "dma")] - const DMA_TX_TRIGGER: TriggerSource = TriggerSource::[]; - #[inline] - fn enable_apb_clock(&mut self, ctrl: &APB_CLK_CTRL) { - ctrl.$apbmask.modify(|_, w| w.[]().set_bit()); - } - } + ( $apbmask:ident, $N:expr, $alias:ident, $pac_type:ident, $pac_rx:ident, $pac_tx:ident, $pac_modify:ident) => { + use pac::$pac_type; + /// Type alias for the corresponding SERCOM instance + pub type $alias = $pac_type; + impl Sealed for $alias {} + impl Sercom for $alias { + const NUM: usize = $N; + #[cfg(feature = "dma")] + const DMA_RX_TRIGGER: TriggerSource = TriggerSource::$pac_rx; + #[cfg(feature = "dma")] + const DMA_TX_TRIGGER: TriggerSource = TriggerSource::$pac_tx; + #[inline] + fn enable_apb_clock(&mut self, ctrl: &APB_CLK_CTRL) { + ctrl.$apbmask.modify(|_, w| w.$pac_modify().set_bit()); } - }); + } }; } -#[cfg(feature = "thumbv6")] -sercom!(apbcmask: (0, 5)); +// d11 and d21 families +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] +sercom!(apbcmask, 0, Sercom0, SERCOM0, SERCOM0_RX, SERCOM0_TX, sercom0_); + +#[hal_cfg(any("sercom1-d11", "sercom1-d21"))] +sercom!(apbcmask, 1, Sercom1, SERCOM1, SERCOM1_RX, SERCOM1_TX, sercom1_); + +#[hal_cfg(any("sercom2-d11", "sercom2-d21"))] +sercom!(apbcmask, 2, Sercom2, SERCOM2, SERCOM2_RX, SERCOM2_TX, sercom2_); + +#[hal_cfg("sercom3-d21")] +sercom!(apbcmask, 3, Sercom3, SERCOM3, SERCOM3_RX, SERCOM3_TX, sercom3_); + +#[hal_cfg("sercom4-d21")] +sercom!(apbcmask, 4, Sercom4, SERCOM4, SERCOM4_RX, SERCOM4_TX, sercom4_); + +#[hal_cfg("sercom5-d21")] +sercom!(apbcmask, 5, Sercom5, SERCOM5, SERCOM5_RX, SERCOM5_TX, sercom5_); + +// d5x family +#[hal_cfg("sercom0-d5x")] +sercom!(apbamask, 0, Sercom0, SERCOM0, SERCOM0_RX, SERCOM0_TX, sercom0_); + +#[hal_cfg("sercom1-d5x")] +sercom!(apbamask, 1, Sercom1, SERCOM1, SERCOM1_RX, SERCOM1_TX, sercom1_); + +#[hal_cfg("sercom2-d5x")] +sercom!(apbbmask, 2, Sercom2, SERCOM2, SERCOM2_RX, SERCOM2_TX, sercom2_); + +#[hal_cfg("sercom3-d5x")] +sercom!(apbbmask, 3, Sercom3, SERCOM3, SERCOM3_RX, SERCOM3_TX, sercom3_); + +#[hal_cfg("sercom4-d5x")] +sercom!(apbdmask, 4, Sercom4, SERCOM4, SERCOM4_RX, SERCOM4_TX, sercom4_); + +#[hal_cfg("sercom5-d5x")] +sercom!(apbdmask, 5, Sercom5, SERCOM5, SERCOM5_RX, SERCOM5_TX, sercom5_); + +#[hal_cfg("sercom6-d5x")] +sercom!(apbdmask, 6, Sercom6, SERCOM6, SERCOM6_RX, SERCOM6_TX, sercom6_); -#[cfg(feature = "thumbv7")] -sercom!(apbamask: (0, 1)); -#[cfg(feature = "thumbv7")] -sercom!(apbbmask: (2, 3)); -#[cfg(feature = "thumbv7")] -sercom!(apbdmask: (4, 7)); +#[hal_cfg("sercom7-d5x")] +sercom!(apbdmask, 7, Sercom7, SERCOM7, SERCOM7_RX, SERCOM7_TX, sercom7_); diff --git a/hal/src/sercom/pad.rs b/hal/src/sercom/pad.rs index 45589c71d97..bd56d4101a2 100644 --- a/hal/src/sercom/pad.rs +++ b/hal/src/sercom/pad.rs @@ -33,22 +33,21 @@ //! [`InIoSet`] [type class] is responsible for labeling each `IsPad` type with //! its corresponding, valid `IoSet`\(s). +use atsamd_hal_macros::{hal_cfg, hal_module}; use paste::paste; use seq_macro::seq; use super::Sercom; -#[cfg(not(feature = "samd11"))] +#[hal_cfg(any("sercom0-d21", "sercom0-d5x"))] use crate::gpio::OptionalPinId; use crate::gpio::{AnyPin, OptionalPin, Pin, PinId, PinMode}; use crate::typelevel::{NoneT, Sealed}; -#[cfg(feature = "thumbv6")] -#[path = "pad/impl_pad_thumbv6m.rs"] -mod impl_pad; - -#[cfg(feature = "thumbv7")] -#[path = "pad/impl_pad_thumbv7em.rs"] -mod impl_pad; +#[hal_module( + any("sercom0-d11", "sercom0-d21") => "pad/impl_pad_thumbv6m.rs", + "sercom0-d5x" => "pad/impl_pad_thumbv7em.rs", +)] +mod impl_pad {} //============================================================================== // PadNum @@ -167,7 +166,7 @@ impl SomePad for P {} /// See the documentation on [type-level functions] for more details. /// /// [type-level functions]: crate::typelevel#type-level-functions -#[cfg(feature = "samd11")] +#[hal_cfg("sercom0-d11")] pub trait GetPad where S: Sercom, @@ -191,7 +190,7 @@ where /// See the documentation on [type-level functions] for more details. /// /// [type-level functions]: crate::typelevel#type-level-functions -#[cfg(not(feature = "samd11"))] +#[hal_cfg(any("sercom0-d21", "sercom0-d5x"))] pub trait GetPad where S: Sercom, @@ -207,22 +206,22 @@ where /// Type alias using [`GetPad`] to recover the [`PinMode`] for a given SERCOM /// pad -#[cfg(feature = "samd11")] +#[hal_cfg("sercom0-d11")] pub type PadMode = >::PinMode; /// Type alias using [`GetPad`] to recover the [`PinMode`] for a given SERCOM /// pad -#[cfg(not(feature = "samd11"))] +#[hal_cfg(any("sercom0-d21", "sercom0-d5x"))] pub type PadMode = >::PinMode; /// Type alias to recover a [`Pin`] configured as a SERCOM pad in the correct /// [`PadMode`] -#[cfg(feature = "samd11")] +#[hal_cfg("sercom0-d11")] pub type Pad = Pin>; /// Type alias to recover a [`Pin`] configured as a SERCOM pad in the correct /// [`PadMode`] -#[cfg(not(feature = "samd11"))] +#[hal_cfg(any("sercom0-d21", "sercom0-d5x"))] pub type Pad = Pin>; //============================================================================== @@ -238,19 +237,19 @@ pub type Pad = Pin>; /// `Option`. /// /// [type-level functions]: crate::typelevel#type-level-functions -#[cfg(not(feature = "samd11"))] +#[hal_cfg(any("sercom0-d21", "sercom0-d5x"))] pub trait GetOptionalPad: OptionalPinId { type PadNum: OptionalPadNum; type Pad: OptionalPad; } -#[cfg(not(feature = "samd11"))] +#[hal_cfg(any("sercom0-d21", "sercom0-d5x"))] impl GetOptionalPad for NoneT { type PadNum = NoneT; type Pad = NoneT; } -#[cfg(not(feature = "samd11"))] +#[hal_cfg(any("sercom0-d21", "sercom0-d5x"))] impl GetOptionalPad for I where S: Sercom, @@ -265,7 +264,7 @@ where // IoSet //============================================================================== -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] mod ioset { use super::*; @@ -357,5 +356,5 @@ mod ioset { } } -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] pub use ioset::*; diff --git a/hal/src/sercom/pad/impl_pad_thumbv6m.rs b/hal/src/sercom/pad/impl_pad_thumbv6m.rs index 8be71d1b457..a212a1113c1 100644 --- a/hal/src/sercom/pad/impl_pad_thumbv6m.rs +++ b/hal/src/sercom/pad/impl_pad_thumbv6m.rs @@ -1,5 +1,7 @@ //! Implementations of the [`IsPad`], [`IsI2cPad`], [`GetPad`] traits +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use crate::gpio::*; use crate::sercom::*; @@ -37,12 +39,12 @@ macro_rules! pad_info { $Sercom:ident, $PadNum:ident ) => { - #[cfg(feature = "samd11")] + #[hal_cfg("sercom0-d11")] impl GetPad<$Sercom, $PadNum> for $PinId { type PinMode = Alternate<$Cfg>; } - #[cfg(feature = "samd21")] + #[hal_cfg("sercom0-d21")] impl GetPad<$Sercom> for $PinId { type PadNum = $PadNum; type PinMode = Alternate<$Cfg>; diff --git a/hal/src/sercom/pad/impl_pad_thumbv7em.rs b/hal/src/sercom/pad/impl_pad_thumbv7em.rs index 389abdee7b1..fda518a148b 100644 --- a/hal/src/sercom/pad/impl_pad_thumbv7em.rs +++ b/hal/src/sercom/pad/impl_pad_thumbv7em.rs @@ -55,28 +55,30 @@ macro_rules! pad_info { macro_rules! pad_table { ( - #[$cfg:meta] + #[$id_cfg:meta] $PinId:ident { $( + $( #[$sercom_cfg:meta] )? $Cfg:ident: ( $Sercom:ident, $PadNum:ident, $( $IoSet:ident ),+ ) $( + $I2C:ident )?, )+ } ) => { $( - #[$cfg] + #[$id_cfg] + $( #[$sercom_cfg] )? pad_info!( $PinId, $Cfg, $Sercom, $PadNum, $( $IoSet ),+ $( + $I2C )?); )+ }; ( $PinId:ident { $( - $( #[$cfg:meta] )? + $( #[$sercom_cfg:meta] )? $Cfg:ident: ( $Sercom:ident, $PadNum:ident, $( $IoSet:ident ),+ ) $( + $I2C:ident )?, )+ } ) => { $( - $( #[$cfg] )? + $( #[$sercom_cfg] )? pad_info!( $PinId, $Cfg, $Sercom, $PadNum, $( $IoSet ),+ $( + $I2C )?); )+ }; @@ -105,358 +107,523 @@ macro_rules! pad_table { }; } -// Because we presume to be #[cfg(feature = "thumbv7")], we can also presume a -// minimum of #[cfg(feature = "pins-48a")], which cuts down on the number of -// required features below. pad_table!( + #[hal_cfg("pa00")] PA00 { + #[hal_cfg("sercom1")] D: (Sercom1, Pad0, IoSet4), } + #[hal_cfg("pa01")] PA01 { + #[hal_cfg("sercom1")] D: (Sercom1, Pad1, IoSet4), } + #[hal_cfg("pa04")] PA04 { + #[hal_cfg("sercom0")] D: (Sercom0, Pad0, IoSet3), } + #[hal_cfg("pa05")] PA05 { + #[hal_cfg("sercom0")] D: (Sercom0, Pad1, IoSet3), } + #[hal_cfg("pa06")] PA06 { + #[hal_cfg("sercom0")] D: (Sercom0, Pad2, IoSet3), } + #[hal_cfg("pa07")] PA07 { + #[hal_cfg("sercom0")] D: (Sercom0, Pad3, IoSet3), } + #[hal_cfg("pa08")] PA08 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad0, IoSet1) + I2C, + #[hal_cfg("sercom2")] D: (Sercom2, Pad1, IoSet3) + I2C, } + #[hal_cfg("pa09")] PA09 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad1, IoSet1) + I2C, + #[hal_cfg("sercom2")] D: (Sercom2, Pad0, IoSet3) + I2C, } + #[hal_cfg("pa10")] PA10 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad2, IoSet1), + #[hal_cfg("sercom2")] D: (Sercom2, Pad2, IoSet3), } + #[hal_cfg("pa11")] PA11 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad3, IoSet1), + #[hal_cfg("sercom2")] D: (Sercom2, Pad3, IoSet3), } + #[hal_cfg("pa12")] PA12 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad0, IoSet1) + I2C, + #[hal_cfg("sercom4")] D: (Sercom4, Pad1, IoSet3) + I2C, } + #[hal_cfg("pa13")] PA13 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad1, IoSet1) + I2C, + #[hal_cfg("sercom4")] D: (Sercom4, Pad0, IoSet3) + I2C, } + #[hal_cfg("pa14")] PA14 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad2, IoSet1), + #[hal_cfg("sercom4")] D: (Sercom4, Pad2, IoSet3), } + #[hal_cfg("pa15")] PA15 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad3, IoSet1), + #[hal_cfg("sercom4")] D: (Sercom4, Pad3, IoSet3), } + #[hal_cfg("pa16")] PA16 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad0, IoSet1) + I2C, + #[hal_cfg("sercom3")] D: (Sercom3, Pad1, IoSet3) + I2C, } + #[hal_cfg("pa17")] PA17 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad1, IoSet1) + I2C, + #[hal_cfg("sercom3")] D: (Sercom3, Pad0, IoSet3) + I2C, } + #[hal_cfg("pa18")] PA18 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad2, IoSet1), + #[hal_cfg("sercom3")] D: (Sercom3, Pad2, IoSet3), } + #[hal_cfg("pa19")] PA19 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad3, IoSet1), + #[hal_cfg("sercom3")] D: (Sercom3, Pad3, IoSet3), } + #[hal_cfg("pa20")] PA20 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad2, IoSet2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad2, IoSet2), } + #[hal_cfg("pa21")] PA21 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad3, IoSet2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad3, IoSet2), } + #[hal_cfg("pa22")] PA22 { + #[hal_cfg("sercom3")] C: (Sercom3, Pad0, IoSet1) + I2C, + #[hal_cfg("sercom5")] D: (Sercom5, Pad1, IoSet2, IoSet3, IoSet4) + I2C, } + #[hal_cfg("pa23")] PA23 { + #[hal_cfg("sercom3")] C: (Sercom3, Pad1, IoSet1) + I2C, + #[hal_cfg("sercom5")] D: (Sercom5, Pad0, IoSet2, IoSet3, IoSet4) + I2C, } + #[hal_cfg("pa24")] PA24 { + #[hal_cfg("sercom3")] C: (Sercom3, Pad2, IoSet1), + #[hal_cfg("sercom5")] D: (Sercom5, Pad2, IoSet3), } + #[hal_cfg("pa25")] PA25 { + #[hal_cfg("sercom3")] C: (Sercom3, Pad3, IoSet1), + #[hal_cfg("sercom5")] D: (Sercom5, Pad3, IoSet3), } + #[hal_cfg("pa30")] PA30 { - #[cfg(feature = "has-sercom7")] + // Pin table in 6.1 does not mention function C, but sercom table in 6.2.8.1 does + #[hal_cfg("sercom7")] C: (Sercom7, Pad2, IoSet5), + #[hal_cfg("sercom1")] D: (Sercom1, Pad2, IoSet4), } + #[hal_cfg("pa31")] PA31 { - #[cfg(feature = "has-sercom7")] + // Pin table in 6.1 does not mention function C, but sercom table in 6.2.8.1 does + #[hal_cfg("sercom7")] C: (Sercom7, Pad3, IoSet5), + #[hal_cfg("sercom1")] D: (Sercom1, Pad3, IoSet4), } - #[cfg(feature = "has-pb00")] + #[hal_cfg("pb00")] PB00 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad2, IoSet5, IoSet6), } - #[cfg(feature = "has-pb01")] + #[hal_cfg("pb01")] PB01 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad3, IoSet5, IoSet6), } + #[hal_cfg("pb02")] PB02 { // According to Metro M4, PB02 is I2C-capable. This disagrees with datasheet table 6-8. + #[hal_cfg("sercom5")] D: (Sercom5, Pad0, IoSet6) + I2C, } + #[hal_cfg("pb03")] PB03 { // According to Metro M4, PB03 is I2C-capable. This disagrees with datasheet table 6-8. + #[hal_cfg("sercom5")] D: (Sercom5, Pad1, IoSet6) + I2C, } + #[hal_cfg("pb08")] PB08 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad0, IoSet2), } + #[hal_cfg("pb09")] PB09 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad1, IoSet2), } + #[hal_cfg("pb10")] PB10 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad2, IoSet2), } + #[hal_cfg("pb11")] PB11 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad3, IoSet2), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] PB12 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad0, IoSet1), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] PB13 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad1, IoSet1), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] PB14 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad2, IoSet1), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] PB15 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad3, IoSet1), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] PB16 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad0, IoSet1), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] PB17 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad1, IoSet1), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb18")] PB18 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad2, IoSet1), + #[hal_cfg("sercom7")] D: (Sercom7, Pad2, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb19")] PB19 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad3, IoSet1), + #[hal_cfg("sercom7")] D: (Sercom7, Pad3, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb20")] PB20 { // According to Grand Central M4, PB20 is I2C-capable. This disagrees with datasheet // table 6-8. + #[hal_cfg("sercom3")] C: (Sercom3, Pad0, IoSet2) + I2C, + #[hal_cfg("sercom7")] D: (Sercom7, Pad1, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb21")] PB21 { // According to Grand Central M4, PB21 is I2C-capable. This disagrees with datasheet // table 6-8. + #[hal_cfg("sercom3")] C: (Sercom3, Pad1, IoSet2) + I2C, + #[hal_cfg("sercom7")] D: (Sercom7, Pad0, IoSet4), } + #[hal_cfg("pb22")] PB22 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad2, IoSet3), + #[hal_cfg("sercom5")] D: (Sercom5, Pad2, IoSet4), } + #[hal_cfg("pb23")] PB23 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad3, IoSet3), + #[hal_cfg("sercom5")] D: (Sercom5, Pad3, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb24")] PB24 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad0, IoSet2), + #[hal_cfg("sercom2")] D: (Sercom2, Pad1, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pb25")] PB25 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad1, IoSet2), + #[hal_cfg("sercom2")] D: (Sercom2, Pad0, IoSet4), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pb26")] PB26 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad0, IoSet2), + #[hal_cfg("sercom4")] D: (Sercom4, Pad1, IoSet4), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pb27")] PB27 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad1, IoSet2), + #[hal_cfg("sercom4")] D: (Sercom4, Pad0, IoSet4), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pb28")] PB28 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad2, IoSet2), + #[hal_cfg("sercom4")] D: (Sercom4, Pad2, IoSet4), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pb29")] PB29 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad3, IoSet2), + #[hal_cfg("sercom4")] D: (Sercom4, Pad3, IoSet4), } + #[hal_cfg("pb30")] PB30 { - #[cfg(feature = "has-sercom7")] + // Pin table in 6.1 does not mention function C, but sercom table in 6.2.8.1 does + #[hal_cfg("sercom7")] C: (Sercom7, Pad0, IoSet5), - #[cfg(feature = "pins-64")] + #[hal_cfg("sercom5")] D: (Sercom5, Pad1, IoSet5), } + #[hal_cfg("pb31")] PB31 { - #[cfg(feature = "has-sercom7")] + // Pin table in 6.1 does not mention function C, but sercom table in 6.2.8.1 does + #[hal_cfg("sercom7")] C: (Sercom7, Pad1, IoSet5), - #[cfg(feature = "pins-64")] + #[hal_cfg("sercom5")] D: (Sercom5, Pad0, IoSet5), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pc04")] PC04 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad0, IoSet2), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc05")] PC05 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad1, IoSet2), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc06")] PC06 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad2, IoSet2), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc07")] PC07 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad3, IoSet2), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc10")] PC10 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad2, IoSet5), + #[hal_cfg("sercom7")] D: (Sercom7, Pad2, IoSet3), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc11")] PC11 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad3, IoSet5), + #[hal_cfg("sercom7")] D: (Sercom7, Pad3, IoSet3), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc12")] PC12 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad0, IoSet1, IoSet3), + #[hal_cfg("sercom6")] D: (Sercom6, Pad1, IoSet4, IoSet5), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc13")] PC13 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad1, IoSet1, IoSet3), + #[hal_cfg("sercom6")] D: (Sercom6, Pad0, IoSet4, IoSet5), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc14")] PC14 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad2, IoSet1), + #[hal_cfg("sercom6")] D: (Sercom6, Pad2, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc15")] PC15 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad3, IoSet1), + #[hal_cfg("sercom6")] D: (Sercom6, Pad3, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc16")] PC16 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad0, IoSet1), + #[hal_cfg("sercom0")] D: (Sercom0, Pad1, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc17")] PC17 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad1, IoSet1), + #[hal_cfg("sercom0")] D: (Sercom0, Pad0, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc18")] PC18 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad2, IoSet1), + #[hal_cfg("sercom0")] D: (Sercom0, Pad2, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc19")] PC19 { + #[hal_cfg("sercom6")] C: (Sercom6, Pad3, IoSet1), + #[hal_cfg("sercom0")] D: (Sercom0, Pad3, IoSet4), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pc22")] PC22 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad0, IoSet2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad1, IoSet4), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pc23")] PC23 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad1, IoSet2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad0, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc24")] PC24 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad2, IoSet2), + #[hal_cfg("sercom2")] D: (Sercom2, Pad2, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc25")] PC25 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad3, IoSet2), + #[hal_cfg("sercom2")] D: (Sercom2, Pad3, IoSet4), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc27")] PC27 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad0, IoSet3), } - #[cfg(feature = "pins-100")] + #[hal_cfg("pc28")] PC28 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad1, IoSet3), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pd08")] PD08 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad0, IoSet2) + I2C, + #[hal_cfg("sercom6")] D: (Sercom6, Pad1, IoSet3) + I2C, } - #[cfg(feature = "pins-128")] + #[hal_cfg("pd09")] PD09 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad1, IoSet2) + I2C, + #[hal_cfg("sercom6")] D: (Sercom6, Pad0, IoSet3) + I2C, } - #[cfg(feature = "pins-128")] + #[hal_cfg("pd10")] PD10 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad2, IoSet2), + #[hal_cfg("sercom6")] D: (Sercom6, Pad2, IoSet3), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pd11")] PD11 { + #[hal_cfg("sercom7")] C: (Sercom7, Pad3, IoSet2), + #[hal_cfg("sercom6")] D: (Sercom6, Pad3, IoSet3), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pd20")] PD20 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad2, IoSet2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad2, IoSet4), } - #[cfg(feature = "pins-128")] + #[hal_cfg("pd21")] PD21 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad3, IoSet2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad3, IoSet4), } ); diff --git a/hal/src/sercom/spi.rs b/hal/src/sercom/spi.rs index e7d21c548f8..0e3aa46f897 100644 --- a/hal/src/sercom/spi.rs +++ b/hal/src/sercom/spi.rs @@ -299,6 +299,8 @@ let (chan0, _, spi, _) = dma_transfer.wait(); " )] +use atsamd_hal_macros::{hal_cfg, hal_docs, hal_macro_helper, hal_module}; + use core::convert::TryFrom; use core::marker::PhantomData; @@ -317,46 +319,40 @@ use reg::Registers; // Chip-specific imports //============================================================================= -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] use crate::pac::sercom0::spi::ctrla::MODESELECT_A; -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] use crate::pac::sercom0::spim::ctrla::MODESELECT_A; -#[cfg(feature = "thumbv6")] -#[path = "spi/pads_thumbv6m.rs"] -mod pads; - -#[cfg(feature = "thumbv7")] -#[path = "spi/pads_thumbv7em.rs"] -mod pads; +#[hal_module( + any("sercom0-d11", "sercom0-d21") => "spi/pads_thumbv6m.rs", + "sercom0-d5x" => "spi/pads_thumbv7em.rs", +)] +pub mod pads {} pub use pads::*; -#[cfg(feature = "thumbv6")] -#[path = "spi/char_size.rs"] -mod size; - -#[cfg(feature = "thumbv7")] -#[path = "spi/length.rs"] -mod size; +#[hal_module( + any("sercom0-d11", "sercom0-d21") => "spi/char_size.rs", + "sercom0-d5x" => "spi/length.rs", +)] +pub mod size {} pub use size::*; /// Valid transaction [`Length`]s from the [`typenum`] crate -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] pub mod lengths { seq_macro::seq!(N in 1..=255 { pub use typenum::U~N; }); } -#[cfg(feature = "thumbv6")] -#[path = "spi/impl_ehal_thumbv6m.rs"] -pub mod impl_ehal; - -#[cfg(feature = "thumbv7")] -#[path = "spi/impl_ehal_thumbv7em.rs"] -pub mod impl_ehal; +#[hal_module( + any("sercom0-d11", "sercom0-d21") => "spi/impl_ehal_thumbv6m.rs", + "sercom0-d5x" => "spi/impl_ehal_thumbv7em.rs", +)] +pub mod impl_ehal {} //============================================================================= // BitOrder @@ -500,37 +496,37 @@ impl MasterMode for MasterHWSS {} //============================================================================= /// Type alias for the width of the `DATA` register -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] pub type DataWidth = u16; /// Type alias for the width of the `DATA` register -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] pub type DataWidth = u32; /// Trait alias whose definition varies by chip /// /// On SAMD11 and SAMD21 chips, this represents the [`CharSize`]. -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] pub trait Size: CharSize {} -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] impl Size for C {} /// Type alias for the default [`Size`] type, which varies by chip -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] pub type DefaultSize = EightBit; /// Trait alias whose definition varies by chip /// /// On SAMx5x chips, this represents the transaction [`Length`]. -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] pub trait Size: Length {} -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] impl Size for L {} /// Type alias for the default [`Size`] type, which varies by chip -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] pub type DefaultSize = typenum::U1; //============================================================================== @@ -541,11 +537,11 @@ pub type DefaultSize = typenum::U1; /// read or write of the `DATA` register pub trait AtomicSize: Size {} -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] impl AtomicSize for C {} -#[cfg(feature = "thumbv7")] -seq!(N in 1..=4 { +#[hal_cfg("sercom0-d5x")] +seq_macro::seq!(N in 1..=4 { impl AtomicSize for lengths::U~N {} }); @@ -638,14 +634,15 @@ where impl Config

{ /// Create a new [`Config`] in the default configuration. #[inline] + #[hal_macro_helper] fn default(sercom: P::Sercom, pads: P, freq: impl Into) -> Self { let mut regs = Registers { sercom }; regs.reset(); regs.set_op_mode(Master::MODE, Master::MSSEN); regs.set_dipo_dopo(P::DIPO_DOPO); - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] regs.set_char_size(EightBit::BITS); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] regs.set_length(1); Self { regs, @@ -656,22 +653,38 @@ impl Config

{ } } - /// Create a new [`Config`] in the default configuration - /// - /// This function will enable the corresponding APB clock, reset the - /// [`Sercom`] peripheral, and return a [`Config`] in the default - /// configuration. The default [`OpMode`] is [`Master`], while the default - /// [`Size`] is an - #[cfg_attr(feature = "thumbv6", doc = "[`EightBit`] [`CharSize`]")] - #[cfg_attr(feature = "thumbv7", doc = "`EightBit` `CharSize`")] - /// for SAMD11 and SAMD21 chips or a - #[cfg_attr(feature = "thumbv6", doc = "`Length` of `U1`")] - #[cfg_attr(feature = "thumbv7", doc = "[`Length`] of `U1`")] - /// for SAMx5x chips. Note that [`Config`] takes ownership of both the - /// PAC [`Sercom`] struct as well as the [`Pads`]. - /// - /// Users must configure GCLK manually. The `freq` parameter represents the - /// GCLK frequency for this [`Sercom`] instance. + #[hal_docs( + { + /// Create a new [`Config`] in the default configuration + /// + /// This function will enable the corresponding APB clock, reset the + /// [`Sercom`] peripheral, and return a [`Config`] in the default + /// configuration. The default [`OpMode`] is [`Master`], while the default + /// [`Size`] is an + } + any("sercom0-d11", "sercom0-d21") => { + /// [`EightBit`] [`CharSize`] + } + "sercom0-d5x" => { + /// `EightBit` `CharSize` + } + { + /// for SAMD11 and SAMD21 chips or a + } + any("sercom0-d11", "sercom0-d21") => { + /// `Length` of `U1` + } + "sercom0-d5x" => { + /// [`Length`] of `U1` + } + { + /// for SAMx5x chips. Note that [`Config`] takes ownership of both the + /// PAC [`Sercom`] struct as well as the [`Pads`]. + /// + /// Users must configure GCLK manually. The `freq` parameter represents the + /// GCLK frequency for this [`Sercom`] instance. + } + )] #[inline] pub fn new( apb_clk_ctrl: &APB_CLK_CTRL, @@ -747,7 +760,7 @@ where } /// Change the [`CharSize`] using the builder pattern - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] #[inline] pub fn char_size(mut self) -> Config { self.regs.set_char_size(C2::BITS); @@ -760,7 +773,7 @@ where /// [`DynLength`] and then use the [`dyn_length`] method. /// /// [`dyn_length`]: Config::dyn_length - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] #[inline] pub fn length(mut self) -> Config { self.regs.set_length(L2::U8); @@ -954,7 +967,7 @@ where } } -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] impl Config where P: ValidPads, @@ -1155,7 +1168,7 @@ where /// [`Length`], you **must** wait for a TXC flag before changing to a new /// [`Length`]. #[inline] - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] pub fn length(self) -> Spi, A> where Config: ValidConfig, @@ -1261,7 +1274,7 @@ where } } -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] impl Spi, A> where P: ValidPads, diff --git a/hal/src/sercom/spi/pads_thumbv6m.rs b/hal/src/sercom/spi/pads_thumbv6m.rs index 3db30a72770..8192e4663e3 100644 --- a/hal/src/sercom/spi/pads_thumbv6m.rs +++ b/hal/src/sercom/spi/pads_thumbv6m.rs @@ -3,9 +3,11 @@ //! See the [spi module](super) documentation for more details on declaring and //! instantiating a [`Pads`] type. +use atsamd_hal_macros::hal_cfg; + use core::marker::PhantomData; -#[cfg(feature = "samd21")] +#[hal_cfg("sercom0-d21")] use crate::gpio::AnyPin; use crate::sercom::*; use crate::typelevel::{NoneT, Sealed}; @@ -212,7 +214,7 @@ where } } -#[cfg(feature = "samd11")] +#[hal_cfg("sercom0-d11")] impl Pads where S: Sercom, @@ -284,7 +286,7 @@ where } } -#[cfg(feature = "samd21")] +#[hal_cfg("sercom0-d21")] impl Pads where S: Sercom, @@ -404,7 +406,7 @@ where /// [`Pin`]: crate::gpio::Pin /// [`PinId`]: crate::gpio::PinId /// [`OptionalPinId`]: crate::gpio::OptionalPinId -#[cfg(feature = "samd21")] +#[hal_cfg("sercom0-d21")] pub type PadsFromIds = Pads< S, >::Pad, diff --git a/hal/src/sercom/spi/reg.rs b/hal/src/sercom/spi/reg.rs index 52e43a73eed..373f9c74a23 100644 --- a/hal/src/sercom/spi/reg.rs +++ b/hal/src/sercom/spi/reg.rs @@ -1,15 +1,17 @@ +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + use core::convert::TryInto; use embedded_hal::spi; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] use crate::pac::sercom0::SPI; -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] use crate::pac::sercom0::SPIM; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] use crate::pac::sercom0::spi::ctrla::MODESELECT_A; -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] use crate::pac::sercom0::spim::ctrla::MODESELECT_A; use crate::sercom::Sercom; @@ -36,13 +38,13 @@ pub(super) struct Registers { unsafe impl Sync for Registers {} impl Registers { - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] #[inline] pub fn spi(&self) -> &SPI { self.sercom.spi() } - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] #[inline] pub fn spi(&self) -> &SPIM { self.sercom.spim() @@ -78,10 +80,11 @@ impl Registers { /// in each SPI transaction. Due to a hardware bug, ICSPACE must be at least /// one. See the silicon errata for more details. #[inline] + #[hal_macro_helper] pub fn set_op_mode(&mut self, mode: MODESELECT_A, mssen: bool) { self.spi().ctrla.modify(|_, w| w.mode().variant(mode)); self.spi().ctrlb.modify(|_, w| w.mssen().bit(mssen)); - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] self.spi().ctrlc.write(|w| unsafe { w.data32b().data_trans_32bit(); w.icspace().bits(1) @@ -90,14 +93,14 @@ impl Registers { } /// Return the current transaction length - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] #[inline] pub fn get_length(&self) -> u8 { self.spi().length.read().len().bits() } /// Set the transaction length - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] #[inline] pub fn set_length(&mut self, length: u8) { let length = if length == 0 { 1 } else { length }; @@ -109,7 +112,7 @@ impl Registers { } /// Set the character size - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] #[inline] pub fn set_char_size(&mut self, bits: u8) { self.spi() diff --git a/hal/src/sercom/spi_future.rs b/hal/src/sercom/spi_future.rs index c19a1dfc004..b7158f6ae94 100644 --- a/hal/src/sercom/spi_future.rs +++ b/hal/src/sercom/spi_future.rs @@ -172,6 +172,8 @@ //! [`Poll`]: core::task::Poll //! [RTIC]: https://rtic.rs/ +use atsamd_hal_macros::hal_cfg; + use core::convert::Infallible; use core::task::Poll; @@ -182,7 +184,7 @@ use crate::typelevel::NoneT; use super::spi::{AnySpi, Error, Flags}; -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] use { super::spi::{ Capability, Config, DynLength, OpMode, Spi, StaticLength, ValidConfig, ValidPads, @@ -190,13 +192,13 @@ use { typenum::Unsigned, }; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] use core::mem::size_of; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] type Data = u16; -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] type Data = u32; //============================================================================= @@ -206,13 +208,13 @@ type Data = u32; /// Trait used to verify the [`SpiFuture`] buffer length #[allow(clippy::len_without_is_empty)] pub trait CheckBufLen: AnySpi { - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] /// [`Spi`] transaction length /// /// This value is zero for an [`Spi`] with [`DynLength`] const LEN: usize = ::USIZE; - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] /// [`Spi`] transaction length /// /// [`Spi`]: super::spi::Spi @@ -267,10 +269,10 @@ pub trait CheckBufLen: AnySpi { } } -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] impl CheckBufLen for S {} -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] impl CheckBufLen for Spi, A> where Config: ValidConfig, @@ -281,7 +283,7 @@ where { } -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] impl CheckBufLen for Spi, A> where Config: ValidConfig, diff --git a/hal/src/sercom/uart.rs b/hal/src/sercom/uart.rs index 0f4dac6a9f4..d1cc67d436b 100644 --- a/hal/src/sercom/uart.rs +++ b/hal/src/sercom/uart.rs @@ -382,13 +382,13 @@ let (chan1, rx, rx_buffer) = rx_dma.wait(); " )] -#[cfg(feature = "thumbv6")] -#[path = "uart/pads_thumbv6m.rs"] -mod pads; +use atsamd_hal_macros::{hal_cfg, hal_module}; -#[cfg(feature = "thumbv7")] -#[path = "uart/pads_thumbv7em.rs"] -mod pads; +#[hal_module( + any("sercom0-d11", "sercom0-d21") => "uart/pads_thumbv6m.rs", + "sercom0-d5x" => "uart/pads_thumbv7em.rs", +)] +mod pads {} pub use pads::*; @@ -411,11 +411,11 @@ use core::{convert::TryInto, marker::PhantomData}; use num_traits::AsPrimitive; /// Size of the SERCOM's `DATA` register -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] pub type DataReg = u16; /// Size of the SERCOM's `DATA` register -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] pub type DataReg = u32; //============================================================================= diff --git a/hal/src/sercom/uart/config.rs b/hal/src/sercom/uart/config.rs index af5816eade6..207a67ace92 100644 --- a/hal/src/sercom/uart/config.rs +++ b/hal/src/sercom/uart/config.rs @@ -1,5 +1,7 @@ //! UART [`Config`] definition and implementation\ +use atsamd_hal_macros::hal_cfg; + use super::{ BaudMode, BitOrder, Capability, CharSize, CharSizeEnum, DataReg, DynCharSize, EightBit, FixedCharSize, Parity, Registers, StopBits, Uart, ValidConfig, ValidPads, @@ -50,12 +52,12 @@ where /// Clock type needed to create a new [`Config`]. [`PM`](pac::PM) for thumbv6m /// targets. -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] pub type Clock = pac::PM; /// Clock type needed to create a new [`Config`]. [`MCLK`](pac::MCLK) for /// thumbv7em targets. -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] pub type Clock = pac::MCLK; impl Config

{ diff --git a/hal/src/sercom/uart/pads_thumbv6m.rs b/hal/src/sercom/uart/pads_thumbv6m.rs index d946f005ffa..0c85cd70e40 100644 --- a/hal/src/sercom/uart/pads_thumbv6m.rs +++ b/hal/src/sercom/uart/pads_thumbv6m.rs @@ -1,5 +1,7 @@ //! UART pad definitions for thumbv6m targets +use atsamd_hal_macros::hal_cfg; + use super::{AnyConfig, Capability, CharSize, Config, Duplex, Rx, Tx}; use crate::{ sercom::*, @@ -7,7 +9,7 @@ use crate::{ }; use core::marker::PhantomData; -#[cfg(not(feature = "samd11"))] +#[hal_cfg("sercom0-d21")] use crate::gpio::AnyPin; //============================================================================= @@ -209,7 +211,7 @@ where } } -#[cfg(feature = "samd11")] +#[hal_cfg("sercom0-d11")] impl Pads where S: Sercom, @@ -267,7 +269,7 @@ where } } -#[cfg(feature = "samd21")] +#[hal_cfg("sercom0-d21")] impl Pads where S: Sercom, @@ -370,7 +372,7 @@ where /// [`PinId`]: crate::gpio::PinId /// [`OptionalPinId`]: crate::gpio::OptionalPinId -#[cfg(feature = "samd21")] +#[hal_cfg("sercom0-d21")] pub type PadsFromIds = Pads< S, >::Pad, diff --git a/hal/src/sercom/uart/reg.rs b/hal/src/sercom/uart/reg.rs index 2b5eda3f457..1f4fe8119b2 100644 --- a/hal/src/sercom/uart/reg.rs +++ b/hal/src/sercom/uart/reg.rs @@ -1,14 +1,16 @@ //! Register-level access to UART configuration +use atsamd_hal_macros::hal_cfg; + use super::{BaudMode, BitOrder, CharSizeEnum, Flags, Oversampling, Parity, Status, StopBits}; use crate::pac; use crate::sercom::*; -#[cfg(feature = "thumbv6")] +#[hal_cfg(any("sercom0-d11", "sercom0-d21"))] use pac::sercom0::usart::ctrla::MODESELECT_A; -#[cfg(feature = "thumbv7")] +#[hal_cfg("sercom0-d5x")] use pac::sercom0::usart_int::ctrla::MODESELECT_A; use crate::time::Hertz; @@ -29,7 +31,7 @@ impl Registers { } /// Helper function to access the underlying `USART` from the given `SERCOM` - #[cfg(feature = "thumbv6")] + #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] #[inline] fn usart(&self) -> &pac::sercom0::USART { self.sercom.usart() @@ -37,7 +39,7 @@ impl Registers { /// Helper function to access the underlying `USART_INT` from the given /// `SERCOM` - #[cfg(feature = "thumbv7")] + #[hal_cfg("sercom0-d5x")] #[inline] fn usart(&self) -> &pac::sercom0::USART_INT { self.sercom.usart_int() From bd64204eb19e15d055c7142aa30517c60991a98c Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 14:44:03 +0100 Subject: [PATCH 06/11] Merge the reset_cause, serial_number and watchdog modules --- hal/src/peripherals/mod.rs | 17 +++-- .../{reset_cause/d5x.rs => reset_cause.rs} | 15 ++++ hal/src/peripherals/reset_cause/d11.rs | 30 -------- .../d11.rs => serial_number.rs} | 19 ++++- hal/src/peripherals/serial_number/d5x.rs | 46 ------------- .../{watchdog/d11.rs => watchdog.rs} | 40 ++++++++--- hal/src/peripherals/watchdog/d5x.rs | 69 ------------------- 7 files changed, 72 insertions(+), 164 deletions(-) rename hal/src/peripherals/{reset_cause/d5x.rs => reset_cause.rs} (64%) delete mode 100644 hal/src/peripherals/reset_cause/d11.rs rename hal/src/peripherals/{serial_number/d11.rs => serial_number.rs} (72%) delete mode 100644 hal/src/peripherals/serial_number/d5x.rs rename hal/src/peripherals/{watchdog/d11.rs => watchdog.rs} (52%) delete mode 100644 hal/src/peripherals/watchdog/d5x.rs diff --git a/hal/src/peripherals/mod.rs b/hal/src/peripherals/mod.rs index 08bc37adfff..f7e06075617 100644 --- a/hal/src/peripherals/mod.rs +++ b/hal/src/peripherals/mod.rs @@ -72,18 +72,17 @@ pub mod nvm {} pub mod can {} #[cfg(feature = "unproven")] -#[cfg_attr(feature = "thumbv6", path = "watchdog/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "watchdog/d5x.rs")] -pub mod watchdog; +#[hal_module("wdt")] +pub mod watchdog {} -#[cfg_attr(feature = "thumbv6", path = "reset_cause/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "reset_cause/d5x.rs")] -mod reset_cause; +#[hal_module(any("pm-d11", "pm-d21", "rstc-d5x"))] +mod reset_cause {} +#[hal_cfg(any("pm-d11", "pm-d21", "rstc-d5x"))] pub use reset_cause::*; -#[cfg_attr(feature = "thumbv6", path = "serial_number/d11.rs")] -#[cfg_attr(feature = "thumbv7", path = "serial_number/d5x.rs")] -mod serial_number; +#[hal_module("serial-numbers")] +mod serial_number {} +#[hal_cfg("serial-numbers")] pub use serial_number::*; diff --git a/hal/src/peripherals/reset_cause/d5x.rs b/hal/src/peripherals/reset_cause.rs similarity index 64% rename from hal/src/peripherals/reset_cause/d5x.rs rename to hal/src/peripherals/reset_cause.rs index 334b1975d28..5d0f52f4fc0 100644 --- a/hal/src/peripherals/reset_cause/d5x.rs +++ b/hal/src/peripherals/reset_cause.rs @@ -1,27 +1,35 @@ +use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; + /// ResetCause represents the reason the MCU was reset. +#[hal_macro_helper] #[derive(Debug, Clone, Copy)] pub enum ResetCause { Unknown, POR, BOD12, BOD33, + #[hal_cfg("rstc-d5x")] NVM, External, Watchdog, System, + #[hal_cfg("rstc-d5x")] Backup, } impl From for ResetCause { + #[hal_macro_helper] fn from(rcause_val: u8) -> ResetCause { match rcause_val { 1 => Self::POR, 2 => Self::BOD12, 4 => Self::BOD33, + #[hal_cfg("rstc-d5x")] 8 => Self::NVM, 16 => Self::External, 32 => Self::Watchdog, 64 => Self::System, + #[hal_cfg("rstc-d5x")] 128 => Self::Backup, _ => Self::Unknown, } @@ -29,6 +37,13 @@ impl From for ResetCause { } /// Returns the cause of the last reset. +#[hal_cfg(any("pm-d11", "pm-d21"))] +pub fn reset_cause(pm: &crate::pac::PM) -> ResetCause { + ResetCause::from(pm.rcause.read().bits()) +} + +/// Returns the cause of the last reset. +#[hal_cfg("rstc-d5x")] pub fn reset_cause(rstc: &crate::pac::RSTC) -> ResetCause { ResetCause::from(rstc.rcause.read().bits()) } diff --git a/hal/src/peripherals/reset_cause/d11.rs b/hal/src/peripherals/reset_cause/d11.rs deleted file mode 100644 index 9a5684a58e5..00000000000 --- a/hal/src/peripherals/reset_cause/d11.rs +++ /dev/null @@ -1,30 +0,0 @@ -/// ResetCause represents the reason the MCU was reset. -#[derive(Debug, Clone, Copy)] -pub enum ResetCause { - Unknown, - POR, - BOD12, - BOD33, - External, - Watchdog, - System, -} - -impl From for ResetCause { - fn from(rcause_val: u8) -> ResetCause { - match rcause_val { - 1 => Self::POR, - 2 => Self::BOD12, - 4 => Self::BOD33, - 16 => Self::External, - 32 => Self::Watchdog, - 64 => Self::System, - _ => Self::Unknown, - } - } -} - -/// Returns the cause of the last reset. -pub fn reset_cause(pm: &crate::pac::PM) -> ResetCause { - ResetCause::from(pm.rcause.read().bits()) -} diff --git a/hal/src/peripherals/serial_number/d11.rs b/hal/src/peripherals/serial_number.rs similarity index 72% rename from hal/src/peripherals/serial_number/d11.rs rename to hal/src/peripherals/serial_number.rs index ced2bfa20b4..436809d0f5d 100644 --- a/hal/src/peripherals/serial_number/d11.rs +++ b/hal/src/peripherals/serial_number.rs @@ -1,14 +1,29 @@ //! Serial number -// See 9.6 Memories --> Serial Number, page 24 for samd11 -// See 10.3.3 Memories --> Serial Number, page 45 for samd21 +use atsamd_hal_macros::hal_cfg; use core::ptr; +// See 9.6 Memories --> Serial Number, page 24 for samd11 +// See 10.3.3 Memories --> Serial Number, page 45 for samd21 +#[hal_cfg(any("serial-numbers-d11", "serial-numbers-d21"))] const SN_1: u32 = 0x0080A00C; +#[hal_cfg(any("serial-numbers-d11", "serial-numbers-d21"))] const SN_2: u32 = 0x0080A040; +#[hal_cfg(any("serial-numbers-d11", "serial-numbers-d21"))] const SN_3: u32 = 0x0080A044; +#[hal_cfg(any("serial-numbers-d11", "serial-numbers-d21"))] const SN_4: u32 = 0x0080A048; +// See 9.6 Memories --> Serial Number, page 60 +#[hal_cfg("serial-numbers-d5x")] +const SN_1: u32 = 0x008061FC; +#[hal_cfg("serial-numbers-d5x")] +const SN_2: u32 = 0x00806010; +#[hal_cfg("serial-numbers-d5x")] +const SN_3: u32 = 0x00806014; +#[hal_cfg("serial-numbers-d5x")] +const SN_4: u32 = 0x00806018; + /// Returns the serial number of the chip as 4 32-bit integers. The serial /// number is only guaranteed to be unique if all 128 bits are used. pub fn split_serial_number() -> (u32, u32, u32, u32) { diff --git a/hal/src/peripherals/serial_number/d5x.rs b/hal/src/peripherals/serial_number/d5x.rs deleted file mode 100644 index 28636564003..00000000000 --- a/hal/src/peripherals/serial_number/d5x.rs +++ /dev/null @@ -1,46 +0,0 @@ -//! Serial number -// See 9.6 Memories --> Serial Number, page 60 - -use core::ptr; - -const SN_1: u32 = 0x008061FC; -const SN_2: u32 = 0x00806010; -const SN_3: u32 = 0x00806014; -const SN_4: u32 = 0x00806018; - -/// Returns the serial number of the chip as 4 32-bit integers. The serial -/// number is only guaranteed to be unique if all 128 bits are used. -pub fn split_serial_number() -> (u32, u32, u32, u32) { - unsafe { - ( - ptr::read(SN_1 as *const u32), - ptr::read(SN_2 as *const u32), - ptr::read(SN_3 as *const u32), - ptr::read(SN_4 as *const u32), - ) - } -} - -/// Returns the serial number of the chip as an array of bytes. The serial -/// number is only guaranteed to be unique if all 16 bytes are used. -pub fn serial_number() -> [u8; 16] { - let sn = split_serial_number(); - [ - ((sn.0 >> 24) & 0xff) as u8, - ((sn.0 >> 16) & 0xff) as u8, - ((sn.0 >> 8) & 0xff) as u8, - (sn.0 & 0xff) as u8, - ((sn.1 >> 24) & 0xff) as u8, - ((sn.1 >> 16) & 0xff) as u8, - ((sn.1 >> 8) & 0xff) as u8, - (sn.1 & 0xff) as u8, - ((sn.2 >> 24) & 0xff) as u8, - ((sn.2 >> 16) & 0xff) as u8, - ((sn.2 >> 8) & 0xff) as u8, - (sn.2 & 0xff) as u8, - ((sn.3 >> 24) & 0xff) as u8, - ((sn.3 >> 16) & 0xff) as u8, - ((sn.3 >> 8) & 0xff) as u8, - (sn.3 & 0xff) as u8, - ] -} diff --git a/hal/src/peripherals/watchdog/d11.rs b/hal/src/peripherals/watchdog.rs similarity index 52% rename from hal/src/peripherals/watchdog/d11.rs rename to hal/src/peripherals/watchdog.rs index 41a77ecdf60..9fbba9ac648 100644 --- a/hal/src/peripherals/watchdog/d11.rs +++ b/hal/src/peripherals/watchdog.rs @@ -1,5 +1,6 @@ use crate::ehal::watchdog; use crate::pac::WDT; +use atsamd_hal_macros::hal_macro_helper; /// WatchdogTimeout enumerates usable values for configuring /// the timeout of the watchdog peripheral. @@ -40,11 +41,22 @@ impl watchdog::Watchdog for Watchdog { /// Disables a running watchdog timer so the processor won't be reset. impl watchdog::WatchdogDisable for Watchdog { + #[hal_macro_helper] fn disable(&mut self) { - // Disable the watchdog timer. - self.wdt.ctrl.write(|w| w.enable().clear_bit()); - // Wait for watchdog timer to be disabled. - while self.wdt.status.read().syncbusy().bit_is_set() {} + #[hal_cfg(any("wdt-d11", "wdt-d21"))] + { + // Disable the watchdog timer. + self.wdt.ctrl.write(|w| w.enable().clear_bit()); + // Wait for watchdog timer to be disabled. + while self.wdt.status.read().syncbusy().bit_is_set() {} + } + #[hal_cfg("wdt-d5x")] + { + // Disable the watchdog timer. + self.wdt.ctrla.write(|w| w.enable().clear_bit()); + // Wait for watchdog timer to be disabled. + while self.wdt.syncbusy.read().enable().bit_is_set() {} + } } } @@ -53,6 +65,7 @@ impl watchdog::WatchdogEnable for Watchdog { /// Enables a watchdog timer to reset the processor if software is frozen /// or stalled. + #[hal_macro_helper] fn start(&mut self, period: T) where T: Into, @@ -61,9 +74,20 @@ impl watchdog::WatchdogEnable for Watchdog { self.wdt .config .write(|w| unsafe { w.per().bits(period.into()) }); - // Enable the watchdog timer. - self.wdt.ctrl.write(|w| w.enable().set_bit()); - // Wait for watchdog timer to be enabled. - while self.wdt.status.read().syncbusy().bit_is_set() {} + #[hal_cfg(any("wdt-d11", "wdt-d21"))] + { + // Enable the watchdog timer. + self.wdt.ctrl.write(|w| w.enable().set_bit()); + // Wait for watchdog timer to be enabled. + while self.wdt.status.read().syncbusy().bit_is_set() {} + } + + #[hal_cfg("wdt-d5x")] + { + // Enable the watchdog timer. + self.wdt.ctrla.write(|w| w.enable().set_bit()); + // Wait for watchdog timer to be enabled. + while self.wdt.syncbusy.read().enable().bit_is_set() {} + } } } diff --git a/hal/src/peripherals/watchdog/d5x.rs b/hal/src/peripherals/watchdog/d5x.rs deleted file mode 100644 index a4faa1a5f04..00000000000 --- a/hal/src/peripherals/watchdog/d5x.rs +++ /dev/null @@ -1,69 +0,0 @@ -use crate::ehal::watchdog; -use crate::pac::WDT; - -/// WatchdogTimeout enumerates usable values for configuring -/// the timeout of the watchdog peripheral. -#[repr(u8)] -#[derive(Copy, Clone, Eq, PartialEq, Debug)] -pub enum WatchdogTimeout { - Cycles8 = 0, - Cycles16, - Cycles32, - Cycles64, - Cycles128, - Cycles256, - Cycles512, - Cycles1K, - Cycles2K, - Cycles4K, - Cycles8K, - Cycles16K, -} - -pub struct Watchdog { - wdt: WDT, -} - -impl Watchdog { - pub fn new(wdt: WDT) -> Self { - Self { wdt } - } -} - -impl watchdog::Watchdog for Watchdog { - /// Feeds an existing watchdog to ensure the processor isn't reset. - /// Sometimes commonly referred to as "kicking" or "refreshing". - fn feed(&mut self) { - self.wdt.clear.write(|w| unsafe { w.clear().bits(0xA5) }); - } -} - -/// Disables a running watchdog timer so the processor won't be reset. -impl watchdog::WatchdogDisable for Watchdog { - fn disable(&mut self) { - // Disable the watchdog timer. - self.wdt.ctrla.write(|w| w.enable().clear_bit()); - // Wait for watchdog timer to be disabled. - while self.wdt.syncbusy.read().enable().bit_is_set() {} - } -} - -impl watchdog::WatchdogEnable for Watchdog { - type Time = u8; - - /// Enables a watchdog timer to reset the processor if software is frozen - /// or stalled. - fn start(&mut self, period: T) - where - T: Into, - { - // Write the timeout configuration. - self.wdt - .config - .write(|w| unsafe { w.per().bits(period.into()) }); - // Enable the watchdog timer. - self.wdt.ctrla.write(|w| w.enable().set_bit()); - // Wait for watchdog timer to be enabled. - while self.wdt.syncbusy.read().enable().bit_is_set() {} - } -} From 5fd70b41c07315471718d50dfde06ace4588cfe6 Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 14:26:50 +0100 Subject: [PATCH 07/11] Split up the sercom pad table for d11/d21 --- hal/src/sercom/pad/impl_pad_thumbv6m.rs | 324 ++++++++++++++++++------ 1 file changed, 245 insertions(+), 79 deletions(-) diff --git a/hal/src/sercom/pad/impl_pad_thumbv6m.rs b/hal/src/sercom/pad/impl_pad_thumbv6m.rs index a212a1113c1..72e162a6223 100644 --- a/hal/src/sercom/pad/impl_pad_thumbv6m.rs +++ b/hal/src/sercom/pad/impl_pad_thumbv6m.rs @@ -60,15 +60,17 @@ macro_rules! pad_info { // Feature gates can be placed on individual configurations or on the entire pin macro_rules! pad_table { ( - #[$cfg:meta] + #[$id_cfg:meta] $PinId:ident { $( + $( #[$sercom_cfg:meta] )? $Cfg:ident: ( $Sercom:ident, $PadNum:ident ) $( + $I2C:ident )?, )+ } ) => { $( - #[$cfg] + #[$id_cfg] + $( #[$sercom_cfg] )? pad_info!( $PinId, $Cfg, $Sercom, $PadNum $( + $I2C )? ); )+ }; @@ -76,13 +78,13 @@ macro_rules! pad_table { ( $PinId:ident { $( - $( #[$cfg:meta] )? + $( #[$sercom_cfg:meta] )? $Cfg:ident: ( $Sercom:ident, $PadNum:ident ) $( + $I2C:ident )?, )+ } ) => { $( - $( #[$cfg] )? + $( #[$sercom_cfg] )? pad_info!( $PinId, $Cfg, $Sercom, $PadNum $( + $I2C )? ); )+ }; @@ -112,230 +114,394 @@ macro_rules! pad_table { }; } -// Because we presume to be #[cfg(feature = "thumbv6")], we can also presume a -// minimum of #[cfg(feature = "pins-14")], which cuts down on the number of -// required features below. +#[hal_macro_helper] +#[hal_cfg("sercom0-d11")] pad_table!( - #[cfg(feature = "has-pa00")] + #[hal_cfg("pa04")] + PA04 { + #[hal_cfg("sercom0")] + C: (Sercom0, Pad2), + #[hal_cfg("sercom0")] + D: (Sercom0, Pad0), + } + #[hal_cfg("pa05")] + PA05 { + #[hal_cfg("sercom0")] + C: (Sercom0, Pad3), + #[hal_cfg("sercom0")] + D: (Sercom0, Pad1), + } + #[hal_cfg("pa06")] + PA06 { + #[hal_cfg("sercom0")] + C: (Sercom0, Pad0), + #[hal_cfg("sercom0")] + D: (Sercom0, Pad2), + } + #[hal_cfg("pa07")] + PA07 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad1), + #[hal_cfg("sercom0")] + D: (Sercom0, Pad3), + } + #[hal_cfg("pa08")] + PA08 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad2), + #[hal_cfg("sercom0")] + D: (Sercom0, Pad2), + } + #[hal_cfg("pa09")] + PA09 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad3), + #[hal_cfg("sercom0")] + D: (Sercom0, Pad3), + } + #[hal_cfg("pa10")] + PA10 { + #[hal_cfg("sercom0")] + C: (Sercom0, Pad2), + #[hal_cfg("sercom2")] + D: (Sercom2, Pad2), + } + #[hal_cfg("pa11")] + PA11 { + #[hal_cfg("sercom0")] + C: (Sercom0, Pad3), + #[hal_cfg("sercom2")] + D: (Sercom2, Pad3), + } + #[hal_cfg("pa14")] + PA14 { + #[hal_cfg("sercom0")] + C: (Sercom0, Pad0) + I2C, + #[hal_cfg("sercom2")] + D: (Sercom2, Pad0) + I2C, + } + #[hal_cfg("pa15")] + PA15 { + #[hal_cfg("sercom0")] + C: (Sercom0, Pad1) + I2C, + #[hal_cfg("sercom2")] + D: (Sercom2, Pad1) + I2C, + } + #[hal_cfg("pa16")] + PA16 { + #[hal_cfg("sercom2")] + C: (Sercom1, Pad2), + #[hal_cfg("sercom2")] + D: (Sercom2, Pad2), + } + #[hal_cfg("pa17")] + PA17 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad3), + #[hal_cfg("sercom2")] + D: (Sercom2, Pad3), + } + #[hal_cfg("pa22")] + PA22 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad0) + I2C, + #[hal_cfg("sercom2")] + D: (Sercom2, Pad0) + I2C, + } + #[hal_cfg("pa23")] + PA23 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad1) + I2C, + #[hal_cfg("sercom2")] + D: (Sercom2, Pad1) + I2C, + } + #[hal_cfg("pa24")] + PA24 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad2), + #[hal_cfg("sercom2")] + D: (Sercom2, Pad2), + } + #[hal_cfg("pa25")] + PA25 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad3), + #[hal_cfg("sercom2")] + D: (Sercom2, Pad3), + } + #[hal_cfg("pa30")] + PA30 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad0), + #[hal_cfg("sercom1")] + D: (Sercom1, Pad2), + } + #[hal_cfg("pa31")] + PA31 { + #[hal_cfg("sercom1")] + C: (Sercom1, Pad1), + #[hal_cfg("sercom1")] + D: (Sercom1, Pad3), + } +); + +#[hal_macro_helper] +#[hal_cfg("sercom0-d21")] +pad_table!( + #[hal_cfg("pa00")] PA00 { + #[hal_cfg("sercom1")] D: (Sercom1, Pad0), } - #[cfg(feature = "has-pa01")] + #[hal_cfg("pa01")] PA01 { + #[hal_cfg("sercom1")] D: (Sercom1, Pad1), } + #[hal_cfg("pa04")] PA04 { - #[cfg(feature = "samd11")] - C: (Sercom0, Pad2), + #[hal_cfg("sercom0")] D: (Sercom0, Pad0), } + #[hal_cfg("pa05")] PA05 { - #[cfg(feature = "samd11")] - C: (Sercom0, Pad3), + #[hal_cfg("sercom0")] D: (Sercom0, Pad1), } - #[cfg(feature = "samd21")] + #[hal_cfg("pa06")] PA06 { + #[hal_cfg("sercom0")] D: (Sercom0, Pad2), } - #[cfg(feature = "samd21")] + #[hal_cfg("pa07")] PA07 { + #[hal_cfg("sercom0")] D: (Sercom0, Pad3), } + #[hal_cfg("pa08")] PA08 { - #[cfg(feature = "samd11")] - C: (Sercom1, Pad2), - #[cfg(feature = "samd11")] - D: (Sercom0, Pad2), - #[cfg(feature = "samd21")] + #[hal_cfg("sercom0")] C: (Sercom0, Pad0) + I2C, - #[cfg(feature = "samd21")] + #[hal_cfg("sercom2")] D: (Sercom2, Pad0) + I2C, } + #[hal_cfg("pa09")] PA09 { - #[cfg(feature = "samd11")] - C: (Sercom1, Pad3), - #[cfg(feature = "samd11")] - D: (Sercom0, Pad3), - #[cfg(feature = "samd21")] + #[hal_cfg("sercom0")] C: (Sercom0, Pad1) + I2C, - #[cfg(feature = "samd21")] + #[hal_cfg("sercom2")] D: (Sercom2, Pad1) + I2C, } - #[cfg(feature = "samd21")] + #[hal_cfg("pa10")] PA10 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad2), + #[hal_cfg("sercom2")] D: (Sercom2, Pad2), } - #[cfg(feature = "samd21")] + #[hal_cfg("pa11")] PA11 { + #[hal_cfg("sercom0")] C: (Sercom0, Pad3), + #[hal_cfg("sercom2")] D: (Sercom2, Pad3), } - #[cfg(feature = "pins-48")] + #[hal_cfg("pa12")] PA12 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad0) + I2C, + #[hal_cfg("sercom4")] D: (Sercom4, Pad0) + I2C, } - #[cfg(feature = "pins-48")] + #[hal_cfg("pa13")] PA13 { + #[hal_cfg("sercom2")] C: (Sercom2, Pad1) + I2C, + #[hal_cfg("sercom4")] D: (Sercom4, Pad1) + I2C, } + #[hal_cfg("pa14")] PA14 { - #[cfg(feature = "samd11")] - C: (Sercom0, Pad0) + I2C, - #[cfg(feature = "samd21")] + #[hal_cfg("sercom2")] C: (Sercom2, Pad2), - #[cfg(feature = "has-sercom4")] + #[hal_cfg("sercom4")] D: (Sercom4, Pad2), } + #[hal_cfg("pa15")] PA15 { - #[cfg(feature = "samd11")] - C: (Sercom0, Pad1) + I2C, - #[cfg(feature = "samd21")] + #[hal_cfg("sercom2")] C: (Sercom2, Pad3), - #[cfg(feature = "has-sercom4")] + #[hal_cfg("sercom4")] D: (Sercom4, Pad3), } - #[cfg(feature = "samd21")] + #[hal_cfg("pa16")] PA16 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad0) + I2C, + #[hal_cfg("sercom3")] D: (Sercom3, Pad0) + I2C, } - #[cfg(feature = "samd21")] + #[hal_cfg("pa17")] PA17 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad1) + I2C, + #[hal_cfg("sercom3")] D: (Sercom3, Pad1) + I2C, } - #[cfg(feature = "samd21")] + #[hal_cfg("pa18")] PA18 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad2), } - #[cfg(feature = "samd21")] + #[hal_cfg("pa19")] PA19 { + #[hal_cfg("sercom1")] C: (Sercom1, Pad3), + #[hal_cfg("sercom3")] D: (Sercom3, Pad3), } - #[cfg(feature = "pins-48")] + #[hal_cfg("pa20")] PA20 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad2), + #[hal_cfg("sercom3")] D: (Sercom3, Pad2), } - #[cfg(feature = "pins-48")] + #[hal_cfg("pa21")] PA21 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad3), + #[hal_cfg("sercom3")] D: (Sercom3, Pad3), } + #[hal_cfg("pa22")] PA22 { - #[cfg(feature = "samd21")] + #[hal_cfg("sercom3")] C: (Sercom3, Pad0) + I2C, - #[cfg(feature = "has-sercom5")] + #[hal_cfg("sercom5")] D: (Sercom5, Pad0) + I2C, } + #[hal_cfg("pa23")] PA23 { - #[cfg(feature = "samd21")] + #[hal_cfg("sercom3")] C: (Sercom3, Pad1) + I2C, - #[cfg(feature = "has-sercom5")] + #[hal_cfg("sercom5")] D: (Sercom5, Pad1) + I2C, } + #[hal_cfg("pa24")] PA24 { - #[cfg(feature = "samd11")] - C: (Sercom1, Pad2), - #[cfg(feature = "samd21")] + #[hal_cfg("sercom3")] C: (Sercom3, Pad2), - #[cfg(feature = "has-sercom5")] + #[hal_cfg("sercom5")] D: (Sercom5, Pad2), } + #[hal_cfg("pa25")] PA25 { - #[cfg(feature = "samd11")] - C: (Sercom1, Pad3), - #[cfg(feature = "samd21")] + #[hal_cfg("sercom3")] C: (Sercom3, Pad3), - #[cfg(feature = "has-sercom5")] + #[hal_cfg("sercom5")] D: (Sercom5, Pad3), } + #[hal_cfg("pa30")] PA30 { - #[cfg(feature = "samd11")] - C: (Sercom1, Pad0), + #[hal_cfg("sercom1")] D: (Sercom1, Pad2), } + #[hal_cfg("pa31")] PA31 { - #[cfg(feature = "samd11")] - C: (Sercom1, Pad1), + #[hal_cfg("sercom1")] D: (Sercom1, Pad3), } - #[cfg(feature = "has-pb00")] + #[hal_cfg("pb00")] PB00 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad2), } - #[cfg(feature = "has-pb01")] + #[hal_cfg("pb01")] PB01 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad3), } - #[cfg(feature = "has-sercom5")] + #[hal_cfg("pb02")] PB02 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad0), } - #[cfg(feature = "has-sercom5")] + #[hal_cfg("pb03")] PB03 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad1), } - #[cfg(feature = "pins-48")] + #[hal_cfg("pb08")] PB08 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad0), } - #[cfg(feature = "pins-48")] + #[hal_cfg("pb09")] PB09 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad1), } - #[cfg(feature = "pins-48")] + #[hal_cfg("pb10")] PB10 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad2), } - #[cfg(feature = "pins-48")] + #[hal_cfg("pb11")] PB11 { + #[hal_cfg("sercom4")] D: (Sercom4, Pad3), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb12")] PB12 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad0) + I2C, } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb13")] PB13 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad1) + I2C, } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb14")] PB14 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad2), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb15")] PB15 { + #[hal_cfg("sercom4")] C: (Sercom4, Pad3), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb16")] PB16 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad0) + I2C, } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb17")] PB17 { + #[hal_cfg("sercom5")] C: (Sercom5, Pad1) + I2C, } - #[cfg(feature = "has-pb22")] + #[hal_cfg("pb22")] PB22 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad2), } - #[cfg(feature = "has-pb23")] + #[hal_cfg("pb23")] PB23 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad3), } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb30")] PB30 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad0) + I2C, } - #[cfg(feature = "pins-64")] + #[hal_cfg("pb31")] PB31 { + #[hal_cfg("sercom5")] D: (Sercom5, Pad1) + I2C, } ); From c341c40424255468dce68b0597d37a1fec72990e Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 14:58:19 +0100 Subject: [PATCH 08/11] Get rid of unused cargo features --- boards/edgebadge/Cargo.toml | 2 +- boards/feather_m4/Cargo.toml | 2 +- boards/grand_central_m4/Cargo.toml | 2 +- boards/itsybitsy_m4/Cargo.toml | 2 +- boards/matrix_portal_m4/Cargo.toml | 2 +- boards/metro_m4/Cargo.toml | 2 +- boards/pygamer/Cargo.toml | 2 +- boards/pyportal/Cargo.toml | 2 +- boards/trellis_m4/Cargo.toml | 2 +- hal/Cargo.toml | 209 +++-------------------------- hal/src/lib.rs | 16 --- 11 files changed, 27 insertions(+), 216 deletions(-) diff --git a/boards/edgebadge/Cargo.toml b/boards/edgebadge/Cargo.toml index 44e3361e5ab..6efbabbd03a 100644 --- a/boards/edgebadge/Cargo.toml +++ b/boards/edgebadge/Cargo.toml @@ -43,7 +43,7 @@ tinybmp = "0.5.0" [features] # ask the HAL to enable atsamd51j support -default = ["rt", "atsamd-hal/samd51j", "atsamd-hal/samd51", "unproven"] +default = ["rt", "atsamd-hal/samd51j", "unproven"] rt = ["cortex-m-rt", "atsamd-hal/samd51j-rt"] unproven = ["atsamd-hal/unproven"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/feather_m4/Cargo.toml b/boards/feather_m4/Cargo.toml index dc5aba55737..b8f7fbede7f 100644 --- a/boards/feather_m4/Cargo.toml +++ b/boards/feather_m4/Cargo.toml @@ -43,7 +43,7 @@ heapless = "0.7" [features] # ask the HAL to enable atsamd51j support -default = ["rt", "atsamd-hal/samd51j", "atsamd-hal/samd51"] +default = ["rt", "atsamd-hal/samd51j"] rt = ["cortex-m-rt", "atsamd-hal/samd51j-rt"] unproven = ["atsamd-hal/unproven"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/grand_central_m4/Cargo.toml b/boards/grand_central_m4/Cargo.toml index 49feba3ee9f..83b9ce2f234 100644 --- a/boards/grand_central_m4/Cargo.toml +++ b/boards/grand_central_m4/Cargo.toml @@ -35,7 +35,7 @@ panic-semihosting = "0.5" smart-leds = "0.3" [features] -default = ["rt", "atsamd-hal/samd51p", "atsamd-hal/samd51", "atsamd-hal/unproven"] +default = ["rt", "atsamd-hal/samd51p", "atsamd-hal/unproven"] rt = ["cortex-m-rt", "atsamd-hal/samd51p-rt"] unproven = ["atsamd-hal/unproven"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/itsybitsy_m4/Cargo.toml b/boards/itsybitsy_m4/Cargo.toml index 26aef725d53..1f992894d1c 100644 --- a/boards/itsybitsy_m4/Cargo.toml +++ b/boards/itsybitsy_m4/Cargo.toml @@ -38,7 +38,7 @@ panic-semihosting = "0.6" [features] # ask the HAL to enable atsamd51g support -default = ["rt", "atsamd-hal/samd51g", "atsamd-hal/samd51", "atsamd-hal/unproven"] +default = ["rt", "atsamd-hal/samd51g", "atsamd-hal/unproven"] rt = ["cortex-m-rt", "atsamd-hal/samd51g-rt"] unproven = ["atsamd-hal/unproven"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/matrix_portal_m4/Cargo.toml b/boards/matrix_portal_m4/Cargo.toml index 02761339462..b31b6eb1bc5 100644 --- a/boards/matrix_portal_m4/Cargo.toml +++ b/boards/matrix_portal_m4/Cargo.toml @@ -35,7 +35,7 @@ panic-halt = "0.2" [features] # ask the HAL to enable atsamd51j support -default = ["rt", "atsamd-hal/samd51j", "atsamd-hal/samd51"] +default = ["rt", "atsamd-hal/samd51j"] rt = ["cortex-m-rt", "atsamd-hal/samd51j-rt"] unproven = ["atsamd-hal/unproven"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/metro_m4/Cargo.toml b/boards/metro_m4/Cargo.toml index d58ad28efb6..2722c9a728b 100644 --- a/boards/metro_m4/Cargo.toml +++ b/boards/metro_m4/Cargo.toml @@ -47,7 +47,7 @@ version = "0.3" [features] # ask the HAL to enable atsamd51j support -default = ["rt", "atsamd-hal/samd51j", "atsamd-hal/samd51"] +default = ["rt", "atsamd-hal/samd51j"] rt = ["cortex-m-rt", "atsamd-hal/samd51j-rt"] unproven = ["atsamd-hal/unproven"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/pygamer/Cargo.toml b/boards/pygamer/Cargo.toml index d4b406e4614..684f16b9748 100644 --- a/boards/pygamer/Cargo.toml +++ b/boards/pygamer/Cargo.toml @@ -51,7 +51,7 @@ tinybmp = "0.3.1" [features] # ask the HAL to enable atsamd51j support -default = ["rt", "atsamd-hal/samd51j", "atsamd-hal/samd51", "unproven"] +default = ["rt", "atsamd-hal/samd51j", "unproven"] rt = ["cortex-m-rt", "atsamd-hal/samd51j-rt"] unproven = ["atsamd-hal/unproven"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/pyportal/Cargo.toml b/boards/pyportal/Cargo.toml index aa4ba229774..8361b948ef2 100644 --- a/boards/pyportal/Cargo.toml +++ b/boards/pyportal/Cargo.toml @@ -47,7 +47,7 @@ version = "~0.3" [features] # ask the HAL to enable atsamd51j support -default = ["rt", "atsamd-hal/samd51j", "atsamd-hal/samd51", "unproven"] +default = ["rt", "atsamd-hal/samd51j", "unproven"] unproven = ["atsamd-hal/unproven"] rt = ["cortex-m-rt", "atsamd-hal/samd51j-rt"] usb = ["atsamd-hal/usb", "usb-device"] diff --git a/boards/trellis_m4/Cargo.toml b/boards/trellis_m4/Cargo.toml index fb428a437cc..4555d5ead66 100644 --- a/boards/trellis_m4/Cargo.toml +++ b/boards/trellis_m4/Cargo.toml @@ -43,7 +43,7 @@ version = "0.3" [features] # ask the HAL to enable atsamd51g support -default = ["rt", "atsamd-hal/samd51g", "atsamd-hal/samd51"] +default = ["rt", "atsamd-hal/samd51g"] rt = ["cortex-m-rt", "atsamd-hal/samd51g-rt"] unproven = ["atsamd-hal/unproven"] keypad-unproven = ["keypad", "unproven"] diff --git a/hal/Cargo.toml b/hal/Cargo.toml index c204d553e7b..f7f2efebb56 100644 --- a/hal/Cargo.toml +++ b/hal/Cargo.toml @@ -108,30 +108,30 @@ atsame54p = {version = "0.13.0", path = "../pac/atsame54p", optional = true} # to change. But all implied features are considered implementation details and # subject to change without notice. -samd11c = ["samd11", "atsamd11c", "periph-d11c", "pins-d11c"] -samd11d = ["samd11", "atsamd11d", "periph-d11d", "pins-d11d"] +samd11c = ["device", "dep:atsamd11c"] +samd11d = ["device", "dep:atsamd11d"] -samd21e = ["samd21", "atsamd21e", "periph-d21e", "pins-d21e"] -samd21g = ["samd21", "atsamd21g", "periph-d21g", "pins-d21g"] -samd21j = ["samd21", "atsamd21j", "periph-d21j", "pins-d21j"] +samd21e = ["device", "dep:atsamd21e"] +samd21g = ["device", "dep:atsamd21g"] +samd21j = ["device", "dep:atsamd21j"] -samd21el = ["samd21", "atsamd21e", "periph-d21el", "pins-d21el"] -samd21gl = ["samd21", "atsamd21g", "periph-d21gl", "pins-d21gl"] +samd21el = ["device", "dep:atsamd21e"] +samd21gl = ["device", "dep:atsamd21g"] -samd51g = ["samd51", "atsamd51g", "periph-d51g", "pins-d51g"] -samd51j = ["samd51", "atsamd51j", "periph-d51j", "pins-d51j"] -samd51n = ["samd51", "atsamd51n", "periph-d51n", "pins-d51n"] -samd51p = ["samd51", "atsamd51p", "periph-d51p", "pins-d51p"] +samd51g = ["device", "dep:atsamd51g"] +samd51j = ["device", "dep:atsamd51j"] +samd51n = ["device", "dep:atsamd51n"] +samd51p = ["device", "dep:atsamd51p"] -same51g = ["same51", "atsame51g", "periph-e51g", "pins-e51g"] -same51j = ["same51", "atsame51j", "periph-e51j", "pins-e51j"] -same51n = ["same51", "atsame51n", "periph-e51n", "pins-e51n"] +same51g = ["device", "dep:atsame51g"] +same51j = ["device", "dep:atsame51j"] +same51n = ["device", "dep:atsame51n"] -same53j = ["same53", "atsame53j", "periph-e53j", "pins-e53j"] -same53n = ["same53", "atsame53n", "periph-e53n", "pins-e53n"] +same53j = ["device", "dep:atsame53j"] +same53n = ["device", "dep:atsame53n"] -same54n = ["same54", "atsame54n", "periph-e54n", "pins-e54n"] -same54p = ["same54", "atsame54p", "periph-e54p", "pins-e54p"] +same54n = ["device", "dep:atsame54n"] +same54p = ["device", "dep:atsame54p"] #------------------------------------------------------------------------------- # RT features @@ -196,179 +196,6 @@ use_rtt = ["jlink_rtt"] # change without notice. Users should not specify any of these features # manually. -#------------------------------------------------------------------------------- -# Chip -#------------------------------------------------------------------------------- - # The `device` feature tells the HAL that a device has been selected from the # feature list. It exists mostly to provide better error messages. device = [] - -# The `library` feature exists to allow building the HAL without specifying a -# device. It should be mutually exclusive with the `device` feature. -library = [] - -# Define a feature for each instruction set -thumbv6 = ["device"] -thumbv7 = ["device"] - -# Map each series of chips to its instruction set -samd11 = ["thumbv6"] -samd21 = ["thumbv6"] -samd51 = ["thumbv7"] -same51 = ["thumbv7"] -same53 = ["thumbv7"] -same54 = ["thumbv7"] - -#------------------------------------------------------------------------------- -# Pins -#------------------------------------------------------------------------------- - -# Define features for specific pins -# -# Cargo features are purely additive. This mostly works well for GPIO pins, -# because the pins in a larger package are typically a strict super set of the -# pins in a smaller package. However, there are a few exceptions to this rule. -# For these pins, we create dedicated features. -has-pa00 = [] -has-pa01 = [] -has-pa27 = [] -has-pa28 = [] -has-pb00 = [] -has-pb01 = [] -has-pb02 = [] -has-pb03 = [] -has-pb04 = [] -has-pb05 = [] -has-pb22 = [] -has-pb23 = [] - -# Define features for various sets of pins, each corresponding to a particular -# device package -pins-14 = [] -pins-24 = ["pins-14"] -pins-32 = ["pins-24"] -pins-32a = ["pins-32", "has-pa00", "has-pa01", "has-pa27"] -pins-32l = ["pins-32", "has-pb02", "has-pb03", "has-pb04", "has-pb05"] -pins-48 = ["pins-32", "has-pa27", "has-pb02", "has-pb03"] -pins-48a = ["pins-48", "has-pa00", "has-pa01", "has-pb22", "has-pb23"] -pins-48l = ["pins-48", "has-pb00", "has-pb01", "has-pb04", "has-pb05"] -pins-64 = ["pins-48a", "pins-48l"] - -pins-100 = ["pins-64"] -pins-128 = ["pins-100"] - -# Map each variant to its corresponding set of pins -pins-d11c = ["pins-14", "has-pa28"] -pins-d11d = ["pins-24", "has-pa28", "has-pa27"] - -pins-d21e = ["pins-32a", "has-pa28"] -pins-d21g = ["pins-48a", "has-pa28"] -pins-d21j = ["pins-64", "has-pa28"] - -pins-d21el = ["pins-32l"] -pins-d21gl = ["pins-48l", "has-pa28"] - -pins-d51g = ["pins-48a"] -pins-d51j = ["pins-64"] -pins-d51n = ["pins-100"] -pins-d51p = ["pins-128"] - -pins-e51g = ["pins-48a"] -pins-e51j = ["pins-64"] -pins-e51n = ["pins-100"] - -pins-e53j = ["pins-64"] -pins-e53n = ["pins-100"] - -pins-e54n = ["pins-100"] -pins-e54p = ["pins-128"] - -#------------------------------------------------------------------------------- -# Peripherals -#------------------------------------------------------------------------------- - -# Define a feature for each optional peripheral -has-can0 = [] -has-can1 = [] -has-ethernet = [] -has-gmac = [] -has-i2s = [] -has-sdhc1 = [] -has-sercom0 = [] -has-sercom1 = [] -has-sercom2 = [] -has-sercom3 = [] -has-sercom4 = [] -has-sercom5 = [] -has-sercom6 = [] -has-sercom7 = [] -has-tc0 = [] -has-tc1 = [] -has-tc2 = [] -has-tc3 = [] -has-tc4 = [] -has-tc5 = [] -has-tc6 = [] -has-tc7 = [] -has-tcc0 = [] -has-tcc1 = [] -has-tcc2 = [] -has-tcc3 = [] -has-usb = [] - -# Map each variant to its collection of peripherals -periph-d11c = ["has-sercom0", "has-sercom1", "has-tc1", "has-tc2", "has-tcc0"] -periph-d11d = ["periph-d11c", "has-sercom2"] - -periph-d21 = [ - "has-i2s", - "has-sercom0", - "has-sercom1", - "has-sercom2", - "has-sercom3", - "has-tc3", - "has-tc4", - "has-tc5", - "has-tcc0", - "has-tcc1", - "has-tcc2", -] - -periph-d21e = ["periph-d21", "has-usb"] -periph-d21g = ["periph-d21e", "has-sercom4", "has-sercom5"] -periph-d21j = ["periph-d21g", "has-tc6", "has-tc7"] - -periph-d21el = ["periph-d21"] -periph-d21gl = ["periph-d21el", "has-sercom4", "has-sercom5"] - -periph-d51 = [ - "has-sercom0", - "has-sercom1", - "has-sercom2", - "has-sercom3", - "has-sercom4", - "has-sercom5", - "has-tc0", - "has-tc1", - "has-tc2", - "has-tc3", - "has-tcc0", - "has-tcc1", - "has-usb", -] - -periph-d51g = ["periph-d51"] -periph-d51j = ["periph-d51g", "has-i2s", "has-tcc2", "has-tcc3", "has-tc4", "has-tc5"] -periph-d51n = ["periph-d51j", "has-tc6", "has-tc7", "has-sdhc1", "has-sercom6", "has-sercom7"] -periph-d51p = ["periph-d51n"] - -periph-e51g = ["periph-d51g", "has-can0"] -periph-e51j = ["periph-d51j", "has-can0", "has-can1"] -periph-e51n = ["periph-d51j", "has-can0", "has-can1", "has-tc6", "has-tc7", "has-sercom6", "has-sercom7"] - -periph-e53j = ["periph-d51j", "has-ethernet"] -periph-e53n = ["periph-d51n", "has-ethernet"] - -periph-e54n = ["periph-d51n", "has-ethernet", "has-can0", "has-can1"] -periph-e54p = ["periph-d51p", "has-ethernet", "has-can0", "has-can1"] diff --git a/hal/src/lib.rs b/hal/src/lib.rs index 6a63c54f88b..9cc0c53c0b2 100644 --- a/hal/src/lib.rs +++ b/hal/src/lib.rs @@ -5,19 +5,6 @@ pub use fugit; pub use paste; pub mod typelevel; -#[cfg(not(any(feature = "library", feature = "device")))] -compile_error!( - "The HAL is usually built for a specific target device, selected using a \ - feature. If atsamd-hal is being built as a library, bypass this check by \ - specifying the `library` feature" -); - -#[cfg(all(feature = "library", feature = "device"))] -compile_error!("Cannot combine `library` and `device` features"); - -#[cfg(all(feature = "library", feature = "dma"))] -compile_error!("Cannot combine `library` and `dma` features"); - macro_rules! define_pac { ( $( ($pac:ident, $feat:literal)),+ ) => { $( @@ -87,9 +74,6 @@ pub mod timer_traits; #[cfg(feature = "dma")] pub mod dmac; -#[cfg(all(feature = "usb", feature = "device", not(feature = "has-usb")))] -compile_error!("The 'usb' feature is enabled, but this chip does not support USB"); - #[doc(hidden)] mod peripherals; #[doc(inline)] From a6670a15b1c92191e6c79f03ac962e4237b9ff90 Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 10:30:40 +0100 Subject: [PATCH 09/11] Update CHANGELOG --- hal/CHANGELOG.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hal/CHANGELOG.md b/hal/CHANGELOG.md index c0b1db29a7f..0e051eca256 100644 --- a/hal/CHANGELOG.md +++ b/hal/CHANGELOG.md @@ -9,7 +9,8 @@ - Update README.md - moves some content to wiki - Remove pin `pa28` from the `d21el` target (#717) - Fix a pwm configuration for the `tc4` on `D5x` targets (#720) -- Update to usb-device 0.3.1 +- Update to usb-device 0.3.1 (#718) +- Internal re-organization to support more devices (#728) # v0.16.0 From 5597ddab610db398878fcfc71bbeaa256f649e11 Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 18:31:50 +0100 Subject: [PATCH 10/11] Fix nightly clippy --- hal/src/dmac/channel/mod.rs | 6 ++++++ hal/src/dmac/dma_controller.rs | 12 ++++++++++++ hal/src/dmac/mod.rs | 6 ++++++ hal/src/gpio/dynpin.rs | 2 -- hal/src/rtc.rs | 2 -- hal/src/sercom/i2c/config.rs | 2 +- hal/src/sercom/i2c/flags.rs | 6 ++++++ hal/src/sercom/i2c/reg.rs | 2 +- hal/src/sercom/spi.rs | 3 +-- hal/src/sercom/spi/reg.rs | 2 -- hal/src/sercom/uart.rs | 4 ++-- hal/src/sercom/uart/config.rs | 2 +- hal/src/sercom/uart/flags.rs | 1 - hal/src/sercom/uart/reg.rs | 2 +- 14 files changed, 37 insertions(+), 15 deletions(-) diff --git a/hal/src/dmac/channel/mod.rs b/hal/src/dmac/channel/mod.rs index e2d94c216f9..4d1f6e73401 100644 --- a/hal/src/dmac/channel/mod.rs +++ b/hal/src/dmac/channel/mod.rs @@ -358,6 +358,12 @@ pub enum CallbackStatus { TransferSuspended, } +impl Default for InterruptFlags { + fn default() -> Self { + Self::new() + } +} + /// Interrupt sources available to a DMA channel #[bitfield] #[repr(u8)] diff --git a/hal/src/dmac/dma_controller.rs b/hal/src/dmac/dma_controller.rs index c3bd4fe67ab..90e78c9be23 100644 --- a/hal/src/dmac/dma_controller.rs +++ b/hal/src/dmac/dma_controller.rs @@ -81,6 +81,12 @@ pub struct DmaController { dmac: DMAC, } +impl Default for PriorityLevelMask { + fn default() -> Self { + Self::new() + } +} + /// Mask representing which priority levels should be enabled/disabled #[bitfield] #[repr(u16)] @@ -103,6 +109,12 @@ pub struct PriorityLevelMask { _reserved: B4, } +impl Default for RoundRobinMask { + fn default() -> Self { + Self::new() + } +} + /// Mask representing which priority levels should be configured as round-robin #[bitfield] #[repr(u32)] diff --git a/hal/src/dmac/mod.rs b/hal/src/dmac/mod.rs index 57333b1817b..e5c539bd767 100644 --- a/hal/src/dmac/mod.rs +++ b/hal/src/dmac/mod.rs @@ -343,6 +343,12 @@ macro_rules! get { pub const NUM_CHANNELS: usize = with_num_channels!(get); // ----- DMAC SRAM registers ----- // +impl Default for BlockTransferControl { + fn default() -> Self { + Self::new() + } +} + /// Bitfield representing the BTCTRL SRAM DMAC register #[bitfield] #[derive(Clone, Copy)] diff --git a/hal/src/gpio/dynpin.rs b/hal/src/gpio/dynpin.rs index 4c7af067774..88ee4876294 100644 --- a/hal/src/gpio/dynpin.rs +++ b/hal/src/gpio/dynpin.rs @@ -61,8 +61,6 @@ use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; -use core::convert::TryFrom; - use paste::paste; use crate::ehal::digital::v2::OutputPin; diff --git a/hal/src/rtc.rs b/hal/src/rtc.rs index 6596fd8dfbf..35937e6d244 100644 --- a/hal/src/rtc.rs +++ b/hal/src/rtc.rs @@ -13,8 +13,6 @@ use void::Void; #[cfg(feature = "sdmmc")] use embedded_sdmmc::{TimeSource, Timestamp}; -#[cfg(feature = "rtic")] -use fugit; #[cfg(feature = "rtic")] pub type Instant = fugit::Instant; #[cfg(feature = "rtic")] diff --git a/hal/src/sercom/i2c/config.rs b/hal/src/sercom/i2c/config.rs index d04adba2bd8..16626612d53 100644 --- a/hal/src/sercom/i2c/config.rs +++ b/hal/src/sercom/i2c/config.rs @@ -3,7 +3,7 @@ use super::{I2c, InactiveTimeout, PadSet, Registers}; use crate::{ pac::sercom0::i2cm::ctrla::MODESELECT_A, - sercom::*, + sercom::{Sercom, APB_CLK_CTRL}, time::Hertz, typelevel::{Is, Sealed}, }; diff --git a/hal/src/sercom/i2c/flags.rs b/hal/src/sercom/i2c/flags.rs index 4ee40561afb..2ec9dff38f0 100644 --- a/hal/src/sercom/i2c/flags.rs +++ b/hal/src/sercom/i2c/flags.rs @@ -30,6 +30,12 @@ pub enum BusState { Busy = 0x03, } +impl Default for Status { + fn default() -> Self { + Self::new() + } +} + /// Status flags for I2C transactions /// /// The available status flags are `BUSERR`, `ARBLOST`, `RXNACK`, diff --git a/hal/src/sercom/i2c/reg.rs b/hal/src/sercom/i2c/reg.rs index d8f59cc64b1..7044c6a5008 100644 --- a/hal/src/sercom/i2c/reg.rs +++ b/hal/src/sercom/i2c/reg.rs @@ -4,7 +4,7 @@ use super::flags::{BusState, Error}; use super::InactiveTimeout; use super::{Flags, Status}; use crate::pac; -use crate::sercom::*; +use crate::sercom::Sercom; use crate::time::Hertz; const MASTER_ACT_READ: u8 = 2; diff --git a/hal/src/sercom/spi.rs b/hal/src/sercom/spi.rs index 0e3aa46f897..2a479a04480 100644 --- a/hal/src/sercom/spi.rs +++ b/hal/src/sercom/spi.rs @@ -301,14 +301,13 @@ let (chan0, _, spi, _) = dma_transfer.wait(); use atsamd_hal_macros::{hal_cfg, hal_docs, hal_macro_helper, hal_module}; -use core::convert::TryFrom; use core::marker::PhantomData; use bitflags::bitflags; use embedded_hal::spi; pub use embedded_hal::spi::{Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; -use crate::sercom::*; +use crate::sercom::{pad::SomePad, Sercom, APB_CLK_CTRL}; use crate::time::Hertz; use crate::typelevel::{Is, NoneT, Sealed}; diff --git a/hal/src/sercom/spi/reg.rs b/hal/src/sercom/spi/reg.rs index 373f9c74a23..d5cd15a6ca6 100644 --- a/hal/src/sercom/spi/reg.rs +++ b/hal/src/sercom/spi/reg.rs @@ -1,7 +1,5 @@ use atsamd_hal_macros::{hal_cfg, hal_macro_helper}; -use core::convert::TryInto; - use embedded_hal::spi; #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] diff --git a/hal/src/sercom/uart.rs b/hal/src/sercom/uart.rs index d1cc67d436b..bbcb9dcabe0 100644 --- a/hal/src/sercom/uart.rs +++ b/hal/src/sercom/uart.rs @@ -406,8 +406,8 @@ pub use config::*; pub mod impl_ehal; -use crate::{sercom::*, typelevel::Sealed}; -use core::{convert::TryInto, marker::PhantomData}; +use crate::{sercom::pad::SomePad, typelevel::Sealed}; +use core::marker::PhantomData; use num_traits::AsPrimitive; /// Size of the SERCOM's `DATA` register diff --git a/hal/src/sercom/uart/config.rs b/hal/src/sercom/uart/config.rs index 207a67ace92..fa399d7670c 100644 --- a/hal/src/sercom/uart/config.rs +++ b/hal/src/sercom/uart/config.rs @@ -8,7 +8,7 @@ use super::{ }; use crate::{ pac, - sercom::*, + sercom::Sercom, time::Hertz, typelevel::{Is, Sealed}, }; diff --git a/hal/src/sercom/uart/flags.rs b/hal/src/sercom/uart/flags.rs index dc6de64c590..3d1c4d57211 100644 --- a/hal/src/sercom/uart/flags.rs +++ b/hal/src/sercom/uart/flags.rs @@ -1,7 +1,6 @@ //! Flag definitions use bitflags::bitflags; -use core::convert::TryFrom; //============================================================================= // Interrupt flags diff --git a/hal/src/sercom/uart/reg.rs b/hal/src/sercom/uart/reg.rs index 1f4fe8119b2..913cb146517 100644 --- a/hal/src/sercom/uart/reg.rs +++ b/hal/src/sercom/uart/reg.rs @@ -5,7 +5,7 @@ use atsamd_hal_macros::hal_cfg; use super::{BaudMode, BitOrder, CharSizeEnum, Flags, Oversampling, Parity, Status, StopBits}; use crate::pac; -use crate::sercom::*; +use crate::sercom::Sercom; #[hal_cfg(any("sercom0-d11", "sercom0-d21"))] use pac::sercom0::usart::ctrla::MODESELECT_A; From d1e134dc9e095fb7c17752104a9db38d9fc409a9 Mon Sep 17 00:00:00 2001 From: Tethys Svensson Date: Tue, 5 Mar 2024 17:49:23 +0100 Subject: [PATCH 11/11] Fix to make samd21gl compile --- atsamd-hal-macros/devices.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/atsamd-hal-macros/devices.yaml b/atsamd-hal-macros/devices.yaml index 1fdbda4d5d8..fd7ce6b22c7 100644 --- a/atsamd-hal-macros/devices.yaml +++ b/atsamd-hal-macros/devices.yaml @@ -64,9 +64,10 @@ families: - sercom: { count: 4, only: ["samd21e", "samd21el"] } - sercom: { count: 6, only: ["samd21g", "samd21j", "samd21gl"] } - i2s: { only: ["samd21e", "samd21g", "samd21j"] } - - tc: { start: 3, count: 3, only: ["samd21e", "samd21g", "samd21el"] } - - tc: { start: 3, count: 5, only: ["samd21j", "samd21gl"] } - # TODO: Some of the devices actually has 4, figure out how to support that + # TODO: The datasheet says that the samd21gl devices actually has 5 TCs, but that does not compile + - tc: { start: 3, count: 3, only: ["samd21e", "samd21g", "samd21el", "samd21gl"] } + - tc: { start: 3, count: 5, only: ["samd21j"] } + # TODO: Some of the devices actually has 4 TCCs, figure out how to support that - tcc: { count: 3 } - usb: { only: ["samd21e", "samd21g", "samd21j"] } - adc