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si4468.c
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si4468.c
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/*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* The software is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "ch.h"
#include "hal.h"
#include "nanovna.h"
#include <math.h>
#include "si4432.h"
#include "spi.h"
#pragma GCC push_options
#pragma GCC optimize ("Os")
//#define __USE_FRR_FOR_RSSI__
// Define for use hardware SPI mode
#define USE_HARDWARE_SPI_MODE
// 10MHz clock
#define SI4432_10MHZ 10000000U
// !!!! FROM ili9341.c for disable it !!!!
//#define LCD_CS_HIGH palSetPad(GPIOB, GPIOB_LCD_CS)
// Not use delays for CS
#if 1
#define SI_CS_DELAY
#define PE_CS_DELAY
#define ADF_CS_DELAY
#else
#define SI_CS_DELAY {__asm("NOP");__asm("NOP");__asm("NOP");__asm("NOP");}
#define PE_CS_DELAY {__asm("NOP");__asm("NOP");__asm("NOP");__asm("NOP");}
#define ADF_CS_DELAY {__asm("NOP");__asm("NOP");__asm("NOP");__asm("NOP");}
#endif
#define SI_CS_LOW {palClearLine(LINE_RX_SEL);SI_CS_DELAY;}
#define SI_CS_HIGH {SI_CS_DELAY;palSetLine(LINE_RX_SEL);}
#define SI_SDN_LOW palClearLine(LINE_RX_SDN);
#define SI_SDN_HIGH palSetLine(LINE_RX_SDN);
// Hardware or software SPI use
#ifdef USE_HARDWARE_SPI_MODE
#define SI4432_SPI SPI1
// Check device SPI clock speed
#if STM32_PCLK2 > 48000000 // 48 or 72M MCU
// On 72M MCU STM32_PCLK2 = 72M, SPI = 72M/4 = 18M
//#define SI4432_SPI_SPEED SPI_BR_DIV4
#define SI4432_SPI_SPEED SPI_BR_DIV8
#else
// On 48M MCU STM32_PCLK2 = 48M, SPI = 48M/2 = 24M
//#define SI4432_SPI_SPEED SPI_BR_DIV2
#define SI4432_SPI_SPEED SPI_BR_DIV4
#endif
//#define ADF_SPI_SPEED SPI_BR_DIV64
//#define ADF_SPI_SPEED SPI_BR_DIV32
#define ADF_SPI_SPEED SPI_BR_DIV2
#define PE4302_HW_SHIFT true
#define PE_SPI_SPEED SPI_BR_DIV8
#define PE_SW_DELAY 2
static uint32_t old_spi_settings;
#else
static uint32_t new_port_moder;
#endif
static uint32_t old_port_moder;
#define SPI1_CLK_HIGH palSetPad(GPIOB, GPIOB_SPI_SCLK)
#define SPI1_CLK_LOW palClearPad(GPIOB, GPIOB_SPI_SCLK)
#define SPI1_SDI_HIGH palSetPad(GPIOB, GPIOB_SPI_MOSI)
#define SPI1_SDI_LOW palClearPad(GPIOB, GPIOB_SPI_MOSI)
#define SPI1_RESET palClearPort(GPIOB, (1<<GPIOB_SPI_SCLK)|(1<<GPIOB_SPI_MOSI))
#define SPI1_SDO ((palReadPort(GPIOB)>>GPIOB_SPI_MISO)&1)
#define SPI1_portSDO (palReadPort(GPIOB)&(1<<GPIOB_SPI_MISO))
#ifdef __PE4302__
#define CS_PE_HIGH {PE_CS_DELAY;palSetLine(LINE_PE_SEL);}
#define CS_PE_LOW {PE_CS_DELAY;palClearLine(LINE_PE_SEL);}
#endif
//#define MAXLOG 1024
//unsigned char SI4432_logging[MAXLOG];
//volatile int log_index = 0;
//#define SI4432_log(X) { if (log_index < MAXLOG) SI4432_logging[log_index++] = X; }
#define SI4432_log(X)
void start_SI4432_SPI_mode(void){
#ifdef USE_HARDWARE_SPI_MODE
old_spi_settings = SI4432_SPI->CR1;
SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED);
#else
// Init legs mode for software bitbang
old_port_moder = GPIOB->MODER;
new_port_moder = old_port_moder & ~(PIN_MODE_ANALOG(GPIOB_SPI_SCLK)|PIN_MODE_ANALOG(GPIOB_SPI_MISO)|PIN_MODE_ANALOG(GPIOB_SPI_MOSI));
new_port_moder|= PIN_MODE_OUTPUT(GPIOB_SPI_SCLK)|PIN_MODE_INPUT(GPIOB_SPI_MISO)|PIN_MODE_OUTPUT(GPIOB_SPI_MOSI);
GPIOB->MODER = new_port_moder;
// Pull down SPI
SPI1_SDI_LOW;
SPI1_CLK_LOW;
#endif
}
void stop_SI4432_SPI_mode(void){
#ifdef USE_HARDWARE_SPI_MODE
SI4432_SPI->CR1 = old_spi_settings;
#else
// Restore hardware SPI
GPIOB->MODER = old_port_moder;
#endif
}
void start_PE4312_SPI_mode(void){
// Init legs mode for software bitbang
old_spi_settings = SI4432_SPI->CR1;
old_port_moder = GPIOB->MODER;
uint32_t new_port_moder = old_port_moder & ~(PIN_MODE_ANALOG(GPIOB_SPI_SCLK)|PIN_MODE_ANALOG(GPIOB_SPI_MISO)|PIN_MODE_ANALOG(GPIOB_SPI_MOSI));
new_port_moder|= PIN_MODE_OUTPUT(GPIOB_SPI_SCLK)|PIN_MODE_INPUT(GPIOB_SPI_MISO)|PIN_MODE_OUTPUT(GPIOB_SPI_MOSI);
GPIOB->MODER = new_port_moder;
// Pull down SPI
SPI1_SDI_LOW;
SPI1_CLK_LOW;
}
void stop_PE4312_SPI_mode(void){
// Restore hardware SPI
GPIOB->MODER = old_port_moder;
SI4432_SPI->CR1 = old_spi_settings;
}
#if 0
static void software_shiftOut(uint8_t val)
{
SI4432_log(SI4432_Sel);
SI4432_log(val);
uint8_t i = 0;
do {
if (val & 0x80)
SPI1_SDI_HIGH;
my_microsecond_delay(PE_SW_DELAY);
SPI1_CLK_HIGH;
my_microsecond_delay(PE_SW_DELAY);
SPI1_RESET;
val<<=1;
}while((++i) & 0x07);
}
#endif
static void shiftOut(uint8_t val)
{
#ifdef USE_HARDWARE_SPI_MODE
while (SPI_TX_IS_NOT_EMPTY(SI4432_SPI));
SPI_WRITE_8BIT(SI4432_SPI, val);
while (SPI_IS_BUSY(SI4432_SPI)) // drop rx and wait tx
(void)SPI_READ_8BIT(SI4432_SPI);
#else
SI4432_log(SI4432_Sel);
SI4432_log(val);
uint8_t i = 0;
do {
SPI1_SDI_HIGH;
SPI1_CLK_HIGH;
SPI1_RESET;
val<<=1;
}while((++i) & 0x07);
#endif
}
static uint8_t shiftIn(void)
{
#ifdef USE_HARDWARE_SPI_MODE
// while (SPI_TX_IS_NOT_EMPTY(SI4432_SPI));
SPI_WRITE_8BIT(SI4432_SPI, 0xFF);
while (SPI_RX_IS_EMPTY(SI4432_SPI)) ; // drop rx and wait tx
return SPI_READ_8BIT(SI4432_SPI);
#else
uint32_t value = 0;
uint8_t i = 0;
do {
value<<=1;
SPI1_CLK_HIGH;
value|=SPI1_portSDO;
SPI1_CLK_LOW;
}while((++i) & 0x07);
return value>>GPIOB_SPI_MISO;
#endif
}
uint32_t SI4432_step_delay = 1500;
uint32_t SI4432_offset_delay = 1500;
#define MINIMUM_WAIT_FOR_RSSI 280
//------------PE4302 -----------------------------------------------
#ifdef __PE4302__
void PE4302_init(void) {
CS_PE_LOW;
}
static unsigned char old_attenuation = 255;
bool PE4302_Write_Byte(unsigned char DATA )
{
// if (old_attenuation == DATA) /// Must always have same execution time
// return false;
old_attenuation = DATA;
#ifdef __ARW621__
DATA = DATA << 1;
#endif
#if PE4302_HW_SHIFT
set_SPI_mode(SPI_MODE_SI);
if (SI4432_SPI_SPEED != PE_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, PE_SPI_SPEED);
SPI_WRITE_8BIT(SI4432_SPI, DATA);
while (SPI_IS_BUSY(SI4432_SPI));
#else // Run PE4312 in SW mode to avoid disturbances
set_SPI_mode(SPI_MODE_PE);
software_shiftOut(DATA);
#endif
CS_PE_HIGH;
my_microsecond_delay(PE_SW_DELAY);
CS_PE_LOW;
my_microsecond_delay(PE_SW_DELAY);
#if PE4302_HW_SHIFT
if (SI4432_SPI_SPEED != PE_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED);
#endif
return true;
}
#endif
//------------------------------- ADF4351 -------------------------------------
//#define SI5351_INITIAL_FREQ 3206896551
//#define SI5351_INITIAL_FREQ 15000000000ULL
#define NO_SHIFT_MUL 30
#define NO_SHIFT_DIV 30
#ifdef __SI5351__
#include "si5351.h"
static int shifted = 0;
//static int old_shifted = -1;
#define SHIFT_MUL 31
#define SHIFT_DIV 29
//#define SI5351_INITIAL_FREQ 3000000000ULL
void ADF4350_shift_ref(int f) {
if (f == shifted)
return;
shifted = f;
if (si5351_available && shifted)
si5351_set_int_mul_div(0, SHIFT_MUL, SHIFT_DIV, 0);
else
si5351_set_int_mul_div(0, NO_SHIFT_MUL, NO_SHIFT_DIV, 0);
ADF4351_recalculate_PFDRFout();
}
#else
int si5351_available = false;
#endif
#define __NEW_ADF4351__
#ifdef __NEW_ADF4351__
bool ADF4351_frequency_changed = false;
uint16_t R = 1;
int old_R = 0;
uint16_t N = 1;
uint16_t frac = 0;
uint16_t modulus = 32;
uint16_t out_div = 0;
uint16_t mux = 0;
uint16_t csr = 1; // cycle slip reduction, if enabled cp must be lowest value
uint16_t bscm = 1; // Band select clock mode
// uint32_t reg_0 = 0;
uint32_t reg_1 = 0;
uint32_t reg_2 = 0;
uint32_t reg_3 = 0;
uint32_t reg_4 = 0;
uint32_t reg_5 = 0;
uint16_t id = 0;
uint8_t rfPower = 0b00;
static freq_t prev_actual_freq = 0;
bool pdwn = false;
uint16_t powerDown = 0;
static const uint8_t auxPower = 0b00;
// band select divider. 1 to 255.
volatile uint16_t bsDivider = 100; // For set internal logic clock (24M / 192 = 125k) max 125k
// charge pump current, 0 to 15.
static uint8_t cpCurrent = 0; // Must be zero when using either CSR or Fast Lock
// CLKDIV divider (for fastlock and phase resync). 0 to 4095.
volatile uint16_t fastlockDivider = 6; // Not used when in CSR mode
static const uint16_t phase = 1;
enum {
CLKDIVMODE_OFF = 0b00,
CLKDIVMODE_FASTLOCK = 0b01,
CLKDIVMODE_RESYNC = 0b10
} clkDivMode = CLKDIVMODE_FASTLOCK;
static const enum {
LD_LOW = 0b00,
LD_LOCK_DETECT = 0b01,
LD_HIGH = 0b11
} ld_pin = LD_LOCK_DETECT; // Used for led output
bool refDouble = false;
static const bool refDiv2 = false;
static const bool rfEnable = true;
static bool auxEnable = false;
static const bool feedbackFromDivided = true;
static const bool LDF = false; // for fractional mode
static const bool LDP = true; // 6 ns
static const bool LDS = true;
static enum {
LD_LOW_NOISE = 0b00,
LD_LOW_SPUR1 = 0b10,
LD_LOW_SPUR2 = 0b11
} noiseMode = LD_LOW_NOISE;
/*
static const enum {
p_4_div_5 = 0, // min integer 23, max freq = 3.0GHz
p_8_div_9 = 1 // min integer 75, max freq = 4.4GHz
} prescaler = p_8_div_9;
*/
static const enum {
CPt_NORMAL = 0b00, // Work, use default
CPt_LONG_RESET = 0b01, // Work
CPt_FORCE_SOURCE = 0b10,
CPt_FORCE_SINK = 0b11,
} CP_Test = CPt_NORMAL;
const enum {
CPm_DISABLE = 0b00, // Default
CPm_10pct = 0b01,
CPm_20pct = 0b10,
CPm_30pct = 0b11, // ! Show best linearity result
} CP_Mode = CPm_DISABLE;
#define CS_ADF0_HIGH {palSetLine(LINE_LO_SEL);ADF_CS_DELAY;}
#define CS_ADF0_LOW {palClearLine(LINE_LO_SEL);ADF_CS_DELAY;}
bool ADF4351_dirty = false;
void ADF4351_WriteRegister32(int channel, const uint32_t value)
{
(void) channel;
// Select chip
CS_ADF0_LOW;
// Send 32 bit register
#if 1
SPI_WRITE_8BIT(SI4432_SPI, (value >> 24));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 16));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 8));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 0));
ADF4351_dirty = true;
// while (SPI_IS_BUSY(SI4432_SPI)); // drop rx and wait tx
#else
shiftOut((value >> 24) & 0xFF);
shiftOut((value >> 16) & 0xFF);
shiftOut((value >> 8) & 0xFF);
shiftOut((value >> 0) & 0xFF);
#endif
// unselect
// CS_ADF0_HIGH;
}
void ADF4351_Latch(void)
{
if (ADF4351_dirty == false)
return;
while (SPI_IS_BUSY(SI4432_SPI)); // drop rx and wait tx
CS_ADF0_HIGH;
}
void sendConfig(void) {
if (SI4432_SPI_SPEED != ADF_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, ADF_SPI_SPEED);
if (max2871) {
// pdwn = false; //Power down is no longer active.
uint32_t reg;
const bool fractional = false;
const uint32_t phase = 1; // Recommended
// const bool LDS = (SI5351_INITIAL_FREQ > 3200000000ULL ? true: false);
// reg 5
// LD pin register 5
reg = (ld_pin<<22) | 0b101;
if (reg!=reg_5) {ADF4351_WriteRegister32(id, reg); reg_5 = reg;}
// reg 4
// bs devider fb rf divider bs divider VCO down mtld aux sel aux en aux pwr rf en rf pwr register 4
reg = (bsDivider>>7) << 24 | (feedbackFromDivided<<23) | (out_div<<20) | ((bsDivider&0x7f)<<12) | (powerDown<<11) | (0<<10) | (0<<9) | (auxEnable<<8) | (auxPower<<6) | (rfEnable<<5) | (rfPower<<3) | 0b100;
if (reg!=reg_4) {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_4 = reg;}
// reg 3
// bscm | csr mutedel clkdiv mode clkdiv register 3
reg = (bscm<<23) | (csr<<18) | (0<<17) | (clkDivMode<<15) | (fastlockDivider<<3) | 0b011;
if (reg!=reg_3) {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_3 = reg;}
// reg 2 cp three reset
// LD speed noise mode muxout ref dbr ref div2 R DB CP current LDF LDP PD pol powerdown state counter register 2
reg = (LDS<<31) | (noiseMode<<29) | (mux<<26) | (refDouble<<25) | (refDiv2 << 24) | (R<<14) | (0<<13) | (cpCurrent<<9) | (LDF<<8) | (LDP<<7) | (1<<6) | (pdwn<<5) | (0<<4) | (0<<3) | 0b010;
if (reg!=reg_2) {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_2 = reg;}
// reg 1
// CP mode CP test phase frac modulus
reg = (CP_Mode<<29) | (CP_Test<<27) | (phase<<15) | (modulus<<3) | 0b001;
if (reg!=reg_1) {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_1 = reg;}
// reg 0 (need always send for apply some reg 1 - 5 settings
reg = (fractional<<31) | (N<<15) | (frac<<3) | 0b000;
/*if (reg!=reg_0)*/ {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg);/* reg_0 = reg;*/}
ADF4351_Latch();
} else {
// pdwn = false; //Power down is no longer active.
uint32_t reg;
#ifdef BOARD_DOUBLE_REF_MODE
uint32_t prescaler = (N > 75) ? 1 : 0;
#else
uint32_t prescaler = 1;
#endif
// reg 5
// LD pin register 5
reg = (ld_pin<<22) | (0b11<<19)| 0b101;
if (reg!=reg_5) {ADF4351_WriteRegister32(id, reg); reg_5 = reg;}
// reg 4
// fb rf divider bs divider VCO down mtld aux sel aux en aux pwr rf en rf pwr register 4
reg = (feedbackFromDivided<<23) | (out_div<<20) | (bsDivider<<12) | (0<<11) | (0<<10) | (0<<9) | (auxEnable<<8) | (auxPower<<6) | (rfEnable<<5) | (rfPower<<3) | 0b100;
if (reg!=reg_4) { ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_4 = reg;}
// reg 3
// csr clkdiv mode clkdiv register 3
reg = (csr<<18) | (clkDivMode<<15) | (fastlockDivider<<3) | 0b011;
if (reg!=reg_3) {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_3 = reg;}
// reg 2 cp three reset
// noise mode muxout ref dbr ref div2 R DB CP current LDF LDP PD pol powerdown state counter register 2
reg = (noiseMode<<29) | (mux<<26) | (refDouble<<25) | (refDiv2 << 24) | (R<<14) | (0<<13) | (cpCurrent<<9) | (LDF<<8) | (LDP<<7) | (1<<6) | (pdwn<<5) | (0<<4) | (0<<3) | 0b010;
if (reg!=reg_2) {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_2 = reg;}
// reg 1
// prescaler phase frac modulus
reg = (prescaler<<27) | (phase<<15) | (modulus<<3) | 0b001;
if (reg!=reg_1) {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg); reg_1 = reg;}
// reg 0 (need always send for apply some reg 1 - 5 settings
reg = (N<<15) | (frac<<3) | 0b000;
/*if (reg!=reg_0)*/ {ADF4351_Latch(); ADF4351_WriteRegister32(id, reg);/* reg_0 = reg;*/}
ADF4351_Latch();
}
if (SI4432_SPI_SPEED != ADF_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED);
}
void sendPowerdown(bool p) {
if(pdwn == p)
return;
pdwn = p;
uint32_t reg = (noiseMode<<29) | (0b001<<26) | (refDouble<<25) | (refDiv2 << 24) | (R<<14) | (cpCurrent<<9) | (0<<8) | (0<<7) | (1<<6) | (pdwn<<5) | 0b010;
if (reg!=reg_2) {ADF4351_WriteRegister32(id, reg); reg_2 = reg;ADF4351_Latch(); }
}
static uint32_t adf4350_get_O(uint64_t freqHz) {
if(max2871) {
if(freqHz > 3000000000) return 0; // 1
else if(freqHz > 1500000000) return 1; // 2
else if(freqHz > 750000000) return 2; // 4
else if(freqHz > 375000000) return 3; // 8
else if(freqHz > 187500000) return 4; // 16
else if(freqHz > 137500000) return 5; // 32
else if(freqHz > 68750000) return 6; // 64
else/*if(freqHz > 34375000)*/return 7; //128
}else{
if(freqHz > 2200000000) return 0; // 1
else if(freqHz > 1100000000) return 1; // 2
else if(freqHz > 550000000) return 2; // 4
else if(freqHz > 275000000) return 3; // 8
else/*if(freqHz > 137500000)*/return 4; // 16
}
}
freq_t xtal;
uint64_t ADF4351_set_frequency(int channel, uint64_t freqHz) {
(void) channel;
// RFout = xtalFreqHz × (N + FRAC/MOD) = xtalFreqHz × (N * MOD + FRAC) / MOD
// step = xtalFreqHz / MOD; !!!! should get integer result, also this result should divided by 16
// for 24M step = 24M / 4000 = 6k and 6k/16 = 375
// Nx = RFout / step
// N * 4000 + frac = Nx
// N = Nx / 4000
// frac = Nx % 4000
#if 1
out_div = adf4350_get_O(freqHz);
#ifdef __SI5351__
// if (shifted != old_shifted || xtal == 0)
{
// old_shifted = shifted;
if (shifted)
xtal = (config.setting_frequency_30mhz * SHIFT_MUL) / SHIFT_DIV;
else
{
#endif
xtal = config.setting_frequency_30mhz; // * NO_SHIFT_MUL)/ NO_SHIFT_DIV;
#ifdef __SI5351__
}
}
#endif
if (refDouble) {
xtal<<=1;
}
if (R > 1)
xtal /= R;
#if 1
uint32_t modulus_x2 = modulus<<1;
uint32_t INTA_F = (((freqHz << out_div) * (uint64_t)(modulus_x2*FREQ_MULTIPLIER))/ xtal) + 1;
N = INTA_F / modulus_x2;
frac = (INTA_F - N * modulus_x2)>>1;
if (frac >= modulus) {
frac -= modulus;
N++;
}
freq_t actual_freq = (((uint64_t)xtal *(uint64_t)(N * modulus +frac)) >> out_div) / (modulus*FREQ_MULTIPLIER);
#else
uint32_t _N = ((freqHz<<out_div) * (uint64_t)modulus) / xtal;
N = _N / modulus;
frac = _N % modulus;
#endif
#else
uint32_t MOD = ADF4350_modulo;
if (MOD == 0)
MOD = 60;
uint32_t MOD_X2 = MOD<<1;
uint32_t INTA_F = ((freq * (uint64_t)output_divider) * (uint64_t)MOD_X2/ PFDR) + 1;
uint32_t INTA = INTA_F / MOD_X2;
uint32_t FRAC = (INTA_F - INTA * MOD_X2)>>1;
if (FRAC >= MOD) {
FRAC -= MOD;
INTA++;
}
freq_t actual_freq = ((uint64_t)xtal *(N * modulus +frac))/ (1<<out_div) / modulus;
#endif
if (prev_actual_freq == actual_freq)
return prev_actual_freq;
prev_actual_freq = actual_freq;
ADF4351_frequency_changed = true;
sendConfig();
return actual_freq;
}
void ADF4351_force_refresh(void) {
prev_actual_freq = 0;
// reg_0 = 0;
reg_1 = 0;
reg_2 = 0;
reg_3 = 0;
reg_4 = 0;
}
void ADF4351_modulo(int m)
{
modulus = m;
}
uint16_t ADF4351_get_modulo(void)
{
return modulus;
}
void ADF4351_spur_mode(int S)
{
noiseMode = S;
}
void ADF4351_R_counter(int new_R)
{
if (new_R == old_R)
return;
old_R = new_R;
refDouble = false;
if (new_R < 0) {
refDouble = true;
new_R = -new_R;
}
if (new_R<1)
return;
R = new_R;
clear_frequency_cache(); // When R changes the possible frequencies will change
}
void ADF4351_mux(int m)
{
mux = m;
sendConfig();
}
void ADF4351_csr(int c)
{
csr = (c & 0x1);
sendConfig();
}
void ADF4351_fastlock(int c)
{
clkDivMode = (c & 0x3);
sendConfig();
}
void ADF4351_CP(int p)
{
if (cpCurrent == p)
return;
cpCurrent = p;
sendConfig();
}
uint16_t ADF4351_get_CP(void)
{
return cpCurrent;
}
void ADF4351_drive(int p)
{
if (rfPower == p)
return;
rfPower = p;
sendConfig();
my_microsecond_delay(1000);
}
#if 0
void ADF4351_aux_drive(int p)
{
if ( auxPower == p)
return;
auxPower = p;
sendConfig();
}
#endif
void ADF4351_enable_aux_out(int s)
{
if ( auxEnable == s)
return;
auxEnable = s;
sendConfig();
}
void ADF4351_enable(int s)
{
if ( powerDown == !s)
return;
powerDown = !s;
sendConfig();
osalThreadSleepMilliseconds(10);
}
void ADF4351_enable_out(int s)
{
if ( pdwn == !s)
return;
powerDown = !s;
pdwn = !s;
sendConfig();
osalThreadSleepMilliseconds(10);
}
void ADF4351_recalculate_PFDRFout(void) {
int local_r = old_R;
old_R = -1;
ADF4351_R_counter(local_r);
sendConfig();
}
void ADF4351_Setup(void)
{
CS_ADF0_HIGH;
#ifdef __SI5351__
si5351_available = si5351_init();
if (si5351_available) {
si5351_set_frequency(0, (config.setting_frequency_30mhz * NO_SHIFT_MUL)/ NO_SHIFT_DIV /100, 0);
si5351_set_int_mul_div(0, NO_SHIFT_MUL, NO_SHIFT_DIV, 0);
}
si5351_available = false; // Don't use shifting
#endif
cpCurrent = 0;
if (max2871) {
// refDouble = true;
} else {
ADF4351_csr(1); //Cycle slip enabled
ADF4351_fastlock(1); // Fastlock enabled
cpCurrent = 0;
}
// R = 1;
ADF4351_set_frequency(0,3000000000);
ADF4351_mux(0); // Tristate
}
#else
#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
#define bitSet(value, bit) ((value) |= (1UL << (bit)))
#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
#define bitWrite(value, bit, bitvalue) ((bitvalue) ? bitSet(value, bit) : bitClear(value, bit))
#define maskedWrite(reg, bit, mask, value) (reg) &= ~(((uint32_t)mask) << (bit)); (reg) |= ((((uint32_t) (value)) & ((uint32_t)mask)) << (bit));
#define CS_ADF0_HIGH {palSetLine(LINE_LO_SEL);ADF_CS_DELAY;}
#define CS_ADF1_HIGH {ADF_CS_DELAY;palSetLine(LINE_LO_SEL);}
#define CS_ADF0_LOW {palClearLine(LINE_LO_SEL);ADF_CS_DELAY;}
#define CS_ADF1_LOW {ADF_CS_DELAY;palClearLine(LINE_LO_SEL);}
#define CS_ADF_LOW(ch) {palClearLine(ch);ADF_CS_DELAY;}
#define CS_ADF_HIGH(ch) {ADF_CS_DELAY;palSetLine(ch);}
uint32_t registers[6] = {0xC88000, 0x8008011, 0x1800C642, 0x48963,0xA5003C , 0x580005} ; //10 MHz ref
uint32_t old_registers[6];
int debug = 0;
ioline_t ADF4351_LE[2] = { LINE_LO_SEL, LINE_LO_SEL};
//int ADF4351_Mux = 7;
bool ADF4351_frequency_changed = false;
//#define DEBUG(X) // Serial.print( X )
//#define DEBUGLN(X) Serial.println( X )
//#define DEBUGFLN(X,Y) Serial.println( X,Y )
//#define DEBUGF(X,Y) Serial.print( X,Y )
#define DEBUG(X)
#define DEBUGLN(X)
#define XTAL 300000000
uint64_t PFDRFout[6] = {XTAL,XTAL,XTAL,10000000,10000000,10000000}; //Reference freq in MHz
int64_t
ADF4350_modulo = 0, // Linked to spur table!!!!!
target_freq;
int old_R = 0;
void ADF4351_Setup(void)
{
// palSetPadMode(GPIOA, 1, PAL_MODE_OUTPUT_PUSHPULL );
// palSetPadMode(GPIOA, 2, PAL_MODE_OUTPUT_PUSHPULL );
local_setting_frequency_30mhz_x100 = config.setting_frequency_30mhz;
#ifdef __SI5351__
si5351_available = si5351_init();
if (si5351_available)
si5351_set_frequency(0, 30000000, 0);
si5351_available = false; // Don't use shifting
#endif
// SPI3_CLK_HIGH;
// SPI3_SDI_HIGH;
CS_ADF0_HIGH;
// CS_ADF1_HIGH;
// bitSet (registers[2], 17); // R set to 8
// bitClear (registers[2], 14); // R set to 8
// while(1) {
//
ADF4351_R_counter(1);
ADF4351_CP(0);
ADF4351_fastlock(1); // Fastlock enabled
ADF4351_csr(1); //Cycle slip enabled
ADF4351_set_frequency(0,200000000);
ADF4351_mux(0); // Tristate
// ADF4351_mux(6); // Show lock on led
}
void ADF4351_WriteRegister32(int channel, const uint32_t value)
{
// Select chip
CS_ADF_LOW(ADF4351_LE[channel]);
// Send 32 bit register
#if 1
SPI_WRITE_8BIT(SI4432_SPI, (value >> 24));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 16));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 8));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 0));
while (SPI_IS_BUSY(SI4432_SPI)); // drop rx and wait tx
#else
shiftOut((value >> 24) & 0xFF);
shiftOut((value >> 16) & 0xFF);
shiftOut((value >> 8) & 0xFF);
shiftOut((value >> 0) & 0xFF);
#endif
// unselect
CS_ADF_HIGH(ADF4351_LE[channel]);
}
void ADF4351_Set(int channel)
{
#if 0
for (int i = 5; i >= 0; i--) {
if (registers[i] != old_registers[i])
goto update;
}
return;
update:
#endif
set_SPI_mode(SPI_MODE_SI);
if (SI4432_SPI_SPEED != ADF_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, ADF_SPI_SPEED);
for (int i = 5; i >= 0; i--) {
#if 0
if (i == 0 || registers[i] != old_registers[i])
#endif
ADF4351_WriteRegister32(channel, registers[i]);
old_registers[i] = registers[i];
}
if (SI4432_SPI_SPEED != ADF_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED);
}
static freq_t prev_actual_freq = 0;
void ADF4351_force_refresh(void) {
prev_actual_freq = 0;
for (int i = 5; i >= 0; i--)
old_registers[i] = 0;
}
void ADF4351_modulo(int m)
{
ADF4350_modulo = m;
// ADF4351_set_frequency(0, (uint64_t)prev_actual_freq);
}
uint64_t ADF4351_set_frequency(int channel, uint64_t freq) // freq / 10Hz
{
uint64_t actual_freq = ADF4351_prepare_frequency(channel,freq);
if (actual_freq != prev_actual_freq) {
ADF4351_frequency_changed = true;
ADF4351_Set(channel);
prev_actual_freq = actual_freq;
}
return actual_freq;
}
void ADF4351_spur_mode(int S)
{
bitWrite(registers[2], 29, S & 1);
bitWrite(registers[2], 30, S & 2);
ADF4351_Set(0);
}
void ADF4351_R_counter(int R)
{
if (R == old_R)
return;
old_R = R;
int dbl = false;
if (R < 0) {
dbl = true;
R = -R;
}
if (R<1)
return;
bitWrite(registers[2], 25, dbl); // Reference doubler
for (int channel=0; channel < 6; channel++) {
PFDRFout[channel] = (local_setting_frequency_30mhz_x100 * (dbl?2:1)) / R;
}
maskedWrite(registers[2],14, 0x3FF, R);
// ADF4351_Set(0); // Let next frequency set do the writing
// ADF4351_force_refresh();
clear_frequency_cache(); // When R changes the possible frequencies will change
}
void ADF4351_recalculate_PFDRFout(void){
int local_r = old_R;
old_R = -1;
local_setting_frequency_30mhz_x100 = config.setting_frequency_30mhz;
ADF4351_R_counter(local_r);
}
void ADF4351_mux(int R)
{
maskedWrite(registers[2],26, 0x7, R);
// registers[2] &= ~(((uint32_t) 0x7) << 26);
// registers[2] |= (((uint32_t)R & 0x07) << 26);
ADF4351_Set(0);
}
void ADF4351_csr(int c)
{
maskedWrite(registers[3],18, 0x1, c);
// registers[3] &= ~(((uint32_t) 0x1) << 18);
// registers[3] |= (((uint32_t)c & 0x01) << 18);
ADF4351_Set(0);
}
void ADF4351_fastlock(int c)
{
maskedWrite(registers[3],15, 0x3, c);
// registers[3] &= ~(((uint32_t) 0x3) << 15);
// registers[3] |= (((uint32_t)c & 0x03) << 15);
ADF4351_Set(0);
}
void ADF4351_CP(int p)
{
maskedWrite(registers[2],9, 0xF, p);
// registers[2] &= ~(((uint32_t)0xF) << 9);
// registers[2] |= (((uint32_t) p) << 9);
ADF4351_Set(0);
}
void ADF4351_drive(int p)
{
if (((registers[4] >> 3) & 0x03 ) == (p & 0x03))
return;
maskedWrite(registers[4],3, 0x3, p);
// p &= 0x03;
// registers[4] &= ~(((uint32_t)0x3) << 3);
// registers[4] |= (((uint32_t) p) << 3);
ADF4351_Set(0);
my_microsecond_delay(1000);
}
void ADF4351_aux_drive(int p)
{
if (((registers[4] >> 6) & 0x03 ) == (p & 0x03))
return;
maskedWrite(registers[4],6, 0x3, p);
// p &= 0x03;
// registers[4] &= ~(((uint32_t)0x3) << 6);
// registers[4] |= (((uint32_t) p) << 6);
ADF4351_Set(0);
}
#if 0
static uint32_t gcd(uint32_t x, uint32_t y)
{
uint32_t z;
while (y != 0) {