From cc21b5e20b7f8009dfca7795baf79770aa356911 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Thu, 9 Feb 2023 23:19:18 +0000 Subject: [PATCH] [CHERI-RISC-V] Default to emitting compressed CHERI instructions Both hardware implementations and QEMU have supported these for a long time, so it makes sense for the compiler to default to emitting them if the "C" extension is enabled. This retains the flags that were used to enable the instructions but turns them into an opt-out flag instead. Once the exact impact of compressed CHERI instructions has been evaluated, these command line options and the SubtargetFeature can be removed. See https://github.com/CTSRD-CHERI/llvm-project/issues/681 --- clang/include/clang/Driver/Options.td | 6 ++++-- clang/test/Driver/riscv-default-features.c | 15 +++++++++------ clang/test/Driver/riscv-features.c | 12 +++++++----- llvm/lib/Object/ELFObjectFile.cpp | 1 - llvm/lib/Target/RISCV/RISCV.td | 8 ++++---- llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 +- llvm/test/CodeGen/RISCV/cheri/compress.ll | 16 ++++++++-------- .../RISCV/cheri/rv32cxcheri-cap-mode-invalid.s | 14 +++++++------- .../cheri/rv32cxcheri-cap-mode-only-valid.s | 6 +++--- .../MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s | 12 ++++++------ .../RISCV/cheri/rv64cxcheri-cap-mode-invalid.s | 12 ++++++------ .../cheri/rv64cxcheri-cap-mode-only-valid.s | 6 +++--- 12 files changed, 58 insertions(+), 52 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 017620ad554a..8022173880a4 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -3389,10 +3389,12 @@ def mcmodel_EQ_medany : Flag<["-"], "mcmodel=medany">, Group; def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group, HelpText<"Enable use of experimental RISC-V extensions.">; -def mxcheri_rvc : Flag<["-"], "mxcheri-rvc">, Group, +// TODO: Remove these options (https://github.com/CTSRD-CHERI/llvm-project/issues/681) +def mxcheri_rvc : Flag<["-"], "mxcheri-rvc">, Group, HelpText<"Enable using compressed CHERI instructions">; -def mno_xcheri_rvc : Flag<["-"], "mno-xcheri-rvc">, Group, +def mxcheri_norvc : Flag<["-"], "mxcheri-norvc">, Group, HelpText<"Disable using compressed CHERI instructions">; +def mno_xcheri_rvc : Flag<["-"], "mno-xcheri-rvc">, Alias; def munaligned_access : Flag<["-"], "munaligned-access">, Group, HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64 only)">; diff --git a/clang/test/Driver/riscv-default-features.c b/clang/test/Driver/riscv-default-features.c index f0de2ae0c4a5..64c8ad4a7344 100644 --- a/clang/test/Driver/riscv-default-features.c +++ b/clang/test/Driver/riscv-default-features.c @@ -3,10 +3,13 @@ // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI // RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI -// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-RVC -// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-RVC // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mno-xcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-NORVC // RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mno-xcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-NORVC +// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mxcheri-norvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-NORVC +// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mxcheri-norvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-NORVC +// Ignored flag to enabled xcheri-rvc: +// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-RVC +// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-RVC // RV32: "target-features"="+a,+c,+m,+relax,-save-restore" // RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore" @@ -14,10 +17,10 @@ // RV32-XCHERI: "target-features"="+relax,+xcheri,-save-restore" // RV64-XCHERI: "target-features"="+64bit,+relax,+xcheri,-save-restore" -// RV32-XCHERI-RVC: "target-features"="+relax,+xcheri,+xcheri-rvc,-save-restore" -// RV64-XCHERI-RVC: "target-features"="+64bit,+relax,+xcheri,+xcheri-rvc,-save-restore" -// RV32-XCHERI-NORVC: "target-features"="+relax,+xcheri,-save-restore,-xcheri-rvc" -// RV64-XCHERI-NORVC: "target-features"="+64bit,+relax,+xcheri,-save-restore,-xcheri-rvc" +// RV32-XCHERI-RVC: "target-features"="+relax,+xcheri,-save-restore" +// RV64-XCHERI-RVC: "target-features"="+64bit,+relax,+xcheri,-save-restore" +// RV32-XCHERI-NORVC: "target-features"="+relax,+xcheri,+xcheri-norvc,-save-restore" +// RV64-XCHERI-NORVC: "target-features"="+64bit,+relax,+xcheri,+xcheri-norvc,-save-restore" // Dummy function int foo(){ diff --git a/clang/test/Driver/riscv-features.c b/clang/test/Driver/riscv-features.c index 0e248254f1f5..7b4b37d4a6c1 100644 --- a/clang/test/Driver/riscv-features.c +++ b/clang/test/Driver/riscv-features.c @@ -21,13 +21,15 @@ // DEFAULT: "-target-feature" "-save-restore" // DEFAULT-NOT: "-target-feature" "+save-restore" -// RUN: %clang -target riscv32 -### %s -march=rv32ixcheri 2>&1 | FileCheck %s --check-prefixes=XCHERI,XCHERI-NORVC -// RUN: %clang -target riscv64 -### %s -march=rv64ixcheri 2>&1 | FileCheck %s --check-prefixes=XCHERI,XCHERI-NORVC -// RUN: %clang -target riscv32-unknown-elf -### %s -march=rv64ixcheri -mxcheri-rvc 2>&1 | FileCheck %s --check-prefixes=XCHERI,XCHERI-RVC +// RUN: %clang -target riscv32 -### %s -march=rv32ixcheri 2>&1 | FileCheck %s --check-prefixes=XCHERI +// RUN: %clang -target riscv64 -### %s -march=rv64ixcheri 2>&1 | FileCheck %s --check-prefixes=XCHERI +// RUN: %clang -target riscv32-unknown-elf -### %s -march=rv64ixcheri -mxcheri-rvc 2>&1 | FileCheck %s --check-prefixes=XCHERI +// RUN: %clang -target riscv32-unknown-elf -### %s -march=rv64ixcheri -mxcheri-norvc 2>&1 | FileCheck %s --check-prefixes=XCHERI,XCHERI-NORVC // RUN: %clang -target riscv32-unknown-elf -### %s -march=rv64ixcheri -mno-xcheri-rvc 2>&1 | FileCheck %s --check-prefixes=XCHERI,XCHERI-NORVC // XCHERI: "-target-feature" "+xcheri" -// XCHERI-RVC: "-target-feature" "+xcheri-rvc" -// XCHERI-NORVC: "-target-feature" "-xcheri-rvc" +// XCHERI-NOT: "{{[+|-]}}xcheri- +// XCHERI-NORVC: "-target-feature" "+xcheri-norvc" +// XCHERI-NOT: "{{[+|-]}}xcheri- // RUN: %clang -target riscv32-linux -### %s -fsyntax-only 2>&1 \ // RUN: | FileCheck %s -check-prefix=DEFAULT-LINUX diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index 29182c63be57..3b21e9e830fa 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -306,7 +306,6 @@ SubtargetFeatures ELFObjectFileBase::getRISCVFeatures() const { if (PlatformFlags & ELF::EF_RISCV_CAP_MODE) { Features.AddFeature("xcheri"); - Features.AddFeature("xcheri-rvc"); Features.AddFeature("cap-mode"); } diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index d6d4fc14ada8..d52acfc338d9 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -375,11 +375,11 @@ def FeatureCheri def HasCheri : Predicate<"Subtarget->hasCheri()">, AssemblerPredicate<(all_of FeatureCheri), "CHERI Extension">; -def FeatureCheriRVC - : SubtargetFeature<"xcheri-rvc", "EnableCheriRVCInstrs", "true", - "Enable CHERI RVC Instructions.">; +def FeatureCheriNoRVC + : SubtargetFeature<"xcheri-norvc", "EnableCheriRVCInstrs", "false", + "Disable CHERI RVC Instructions.">; def HasCheriRVC : Predicate<"Subtarget->enableCheriRVCInstrs()">, - AssemblerPredicate<(all_of FeatureCheriRVC), + AssemblerPredicate<(all_of (not FeatureCheriNoRVC)), "CHERI RVC Instructions">; def FeatureCapMode diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 5feaf2834646..1e70327e31cc 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -103,7 +103,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool IsCapMode = false; bool EnableLinkerRelax = false; bool EnableRVCHintInstrs = true; - bool EnableCheriRVCInstrs = false; + bool EnableCheriRVCInstrs = true; bool EnableSaveRestore = false; unsigned XLen = 32; ExtZvl ZvlLen = ExtZvl::NotSet; diff --git a/llvm/test/CodeGen/RISCV/cheri/compress.ll b/llvm/test/CodeGen/RISCV/cheri/compress.ll index d259b4f0b8c2..0dd310fc6662 100644 --- a/llvm/test/CodeGen/RISCV/cheri/compress.ll +++ b/llvm/test/CodeGen/RISCV/cheri/compress.ll @@ -4,23 +4,23 @@ ; ; RUN: cat %s > %t.tgtattr ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr -; RUN: %riscv32_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode,+xcheri-rvc -filetype=obj < %t.tgtattr \ -; RUN: | llvm-objdump -d -M no-aliases --syms - | FileCheck %s -; RUN: %riscv64_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode,+xcheri-rvc -filetype=obj < %t.tgtattr \ +; RUN: %riscv32_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode -filetype=obj < %t.tgtattr \ ; RUN: | llvm-objdump -d -M no-aliases --syms - | FileCheck %s ; RUN: %riscv64_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode -filetype=obj < %t.tgtattr \ +; RUN: | llvm-objdump -d -M no-aliases --syms - | FileCheck %s +; RUN: %riscv64_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode,+xcheri-norvc -filetype=obj < %t.tgtattr \ ; RUN: | llvm-objdump -d -M no-aliases --syms - | FileCheck %s --check-prefix=NORVC ; RUN: cat %s > %t.fnattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+cap-mode,+xcheri-rvc" }' >> %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+cap-mode" }' >> %t.fnattr ; RUN: %riscv32_cheri_purecap_llc -filetype=obj < %t.fnattr \ -; RUN: | llvm-objdump -d --mattr=+c,+xcheri-rvc -M no-aliases --syms - | FileCheck %s +; RUN: | llvm-objdump -d --mattr=+c -M no-aliases --syms - | FileCheck %s ; RUN: %riscv64_cheri_purecap_llc -filetype=obj < %t.fnattr \ -; RUN: | llvm-objdump -d --mattr=+c,+xcheri-rvc -M no-aliases --syms - | FileCheck %s +; RUN: | llvm-objdump -d --mattr=+c -M no-aliases --syms - | FileCheck %s ; RUN: cat %s > %t.fnattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+cap-mode" }' >> %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+cap-mode,+xcheri-norvc" }' >> %t.fnattr ; RUN: %riscv64_cheri_purecap_llc -filetype=obj < %t.fnattr \ -; RUN: | llvm-objdump -d --mattr=+c,+xcheri-rvc -M no-aliases --syms - | FileCheck %s --check-prefix=NORVC +; RUN: | llvm-objdump -d --mattr=+c -M no-aliases --syms - | FileCheck %s --check-prefix=NORVC ; Basic check that we can use CHERI compressed instructions diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s index 8c679985e07b..64e9f6825252 100644 --- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s +++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s @@ -1,8 +1,8 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-RV32-C --implicit-check-not="error:" # RUN: not llvm-mc -triple riscv32 -mattr=+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-RV32-NO-C --implicit-check-not="error:" -# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ +# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64-C --implicit-check-not="error:" # RUN: not llvm-mc -triple riscv64 -mattr=+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64-NO-C --implicit-check-not="error:" @@ -10,23 +10,23 @@ ## C.JAL is only defined for RV32C: c.cjal 2046 # CHECK-RV64-C: :[[#@LINE-1]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} -# CHECK-RV32-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions){{$}} -# CHECK-RV64-NO-C: :[[#@LINE-3]]:1: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} +# CHECK-RV32-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-RV64-NO-C: :[[#@LINE-3]]:1: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} ## C.CSD needs RV64C: c.csd a5, 124(ca3) # CHECK-RV32: :[[#@LINE-1]]:11: error: invalid operand for instruction # CHECK-RV64-C: :[[#@LINE-2]]:11: error: immediate must be a multiple of 8 bytes in the range [0, 248] -# TODO-RV64-NO-C: :[[#@LINE-3]]:11: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions){{$}} +# TODO-RV64-NO-C: :[[#@LINE-3]]:11: error: instruction requires the following: 'C' (Compressed Instructions){{$}} # CHECK-RV64-NO-C: :[[#@LINE-4]]:11: error: invalid operand for instruction ## misaligned immediate: c.csw a5, 1(ca3) # CHECK-RV32-C: :[[#@LINE-1]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124] -# TODO-RV32-NO-C: :[[#@LINE-2]]:11: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions){{$}} +# TODO-RV32-NO-C: :[[#@LINE-2]]:11: error: instruction requires the following: 'C' (Compressed Instructions){{$}} # CHECK-RV32-NO-C: :[[#@LINE-3]]:11: error: invalid operand for instruction # CHECK-RV64-C: :[[#@LINE-4]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124] -# TODO-RV64-NO-C: :[[#@LINE-5]]:11: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions){{$}} +# TODO-RV64-NO-C: :[[#@LINE-5]]:11: error: instruction requires the following: 'C' (Compressed Instructions){{$}} # CHECK-RV64-NO-C: :[[#@LINE-6]]:11: error: invalid operand for instruction # Bad operands: diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s index 08f4fd32e47b..d01d6403ca20 100644 --- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode < %s \ -# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+cap-mode < %s \ +# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s index c5519aeaa6bf..be147c486930 100644 --- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ # RUN: | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode < %s \ -# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+cap-mode < %s \ +# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode < %s \ -# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+cap-mode < %s \ +# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ # RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(csp) diff --git a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s index debb64470c8e..16b6f957e254 100644 --- a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s +++ b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s @@ -1,15 +1,15 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ +# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ # RUN: | FileCheck %s --check-prefixes=CHECK-RV64 --implicit-check-not="error:" # RUN: not llvm-mc -triple riscv64 -mattr=+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK-RV64-NO-C --implicit-check-not="error:" -# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK-RV32 --implicit-check-not="error:" ## Invalid immediates ## FIXME: ideally this should report an immediate value error rather than only valid for RV64! c.clccsp cra, 40(csp) # CHECK-RV64: :[[#@LINE-1]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} -# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} +# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} c.csccsp cra, 1024(csp) # CHECK-RV32: :[[#@LINE-1]]:15: error: immediate must be a multiple of 8 bytes in the range [0, 504] @@ -20,12 +20,12 @@ c.csccsp cra, 1024(csp) ## FIXME: ideally this should report an immediate value error rather than only valid for RV64! c.clc ca2, 8(ca0) # CHECK-RV64: :[[#@LINE-1]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} -# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} +# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} ## FIXME: ideally this should report an immediate value error rather than only valid for RV64! c.csc ca5, 24(ca3) # CHECK-RV64: :[[#@LINE-1]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} -# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} +# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} c.cldcsp ra, 7(csp) # CHECK-RV64: :[[#@LINE-1]]:14: error: immediate must be a multiple of 8 bytes in the range [0, 504] @@ -54,4 +54,4 @@ c.csd a5, 4(ca3) ## C.JAL is only defined for RV32C: c.cjal 2046 # CHECK-RV64: :[[#@LINE-1]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} -# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: CHERI RVC Instructions, 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} +# CHECK-RV64-NO-C: :[[#@LINE-2]]:1: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s index 300def992c7e..964156f365bc 100644 --- a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+xcheri-rvc,+cap-mode < %s \ -# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+xcheri-rvc,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+cap-mode < %s \ +# RUN: | llvm-objdump -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s