diff --git a/.gitmodules b/.gitmodules
index a024164..b4a6be1 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,6 +13,10 @@
path = build-scripts
url = https://gitlab.com/BU-EDF/fw-bits/build-scripts.git
branch = develop
+[submodule "configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater"]
+ path = configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater
+ url = https://github.com/apollo-lhc/FPGA_heater.git
[submodule "configs/IT-DTC_p1_VU13p-1/it-dtc-fw"]
path = configs/IT-DTC_p1_VU13p-1/it-dtc-fw
url = https://gitlab.com/apollo-lhc/it-dtc/it-dtc-fw.git
+
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater
new file mode 160000
index 0000000..04e423d
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater
@@ -0,0 +1 @@
+Subproject commit 04e423df18e8b1b51fa7c2cf0b388d37a04460e8
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/Generate_svf.tcl b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/Generate_svf.tcl
new file mode 100644
index 0000000..c7a7fbf
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/Generate_svf.tcl
@@ -0,0 +1,32 @@
+#this has to be called from inside an open session
+source ${apollo_root_path}/configs/${build_name}/settings.tcl
+
+set SVF_TARGET [format "svf_top%06u" [expr {round(1000000 *rand())}]]
+
+
+
+#derived from walkthrough https://blog.xjtag.com/2016/07/creating-svf-files-using-xilinx-vivado/
+open_hw
+if { [string length [get_hw_targets -quiet -regexp .*/${SVF_TARGET}] ] } {
+ delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]
+}
+create_hw_target ${SVF_TARGET}
+close_hw_target
+open_hw_target [get_hw_targets -regexp .*/${SVF_TARGET}]
+
+
+#1st in chain, no need to add another FPGA to the chain
+#create_hw_device -part xcku15p-ffva1760-2-e
+
+#add the virtex to the chain
+set DEVICE [create_hw_device -part ${FPGA_part}]
+set_property PROGRAM.FILE ${apollo_root_path}/bit/top_${build_name}.bit $DEVICE
+set_param xicom.config_chunk_size 0
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+
+program_hw_devices -force -svf_file ${apollo_root_path}/bit/top_${build_name}.svf ${DEVICE}
+
+write_cfgmem -force -loadbit "up 0 ${apollo_root_path}/bit/top_${build_name}.bit" -format mcs -size 128 -file "${apollo_root_path}/bit/top_${build_name}.mcs"
+
+delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/config.yaml b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/config.yaml
new file mode 100644
index 0000000..d3a9d47
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/config.yaml
@@ -0,0 +1,101 @@
+AXI_CONTROL_SETS:
+ AXI_MASTER_CTRL:
+ axi_interconnect: "${::AXI_INTERCONNECT_NAME}"
+ axi_clk: "${::AXI_MASTER_CLK}"
+ axi_rstn: "${::AXI_MASTER_RSTN}"
+ axi_freq: "${::AXI_MASTER_CLK_FREQ}"
+
+
+AXI_SLAVES:
+ F1_IO:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB1002000"
+ range: "4K"
+ remote_slave: "1"
+ XML: "address_table/modules/CM_IO.xml"
+ UHAL_BASE: 0x81000000
+ HDL:
+ out_name: "IO"
+ map_template: "axi_generic/template_map_withbram.vhd"
+ F1_SYS_MGMT:
+ TCL_CALL:
+ command: AXI_IP_SYS_MGMT
+ enable_i2c_pins: 1
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB1001000"
+ range: "4K"
+ remote_slave: "1"
+ XML: "address_table/modules/VIRTEX_SYS_MGMT.xml"
+ UHAL_BASE: 0x80000000
+
+ F1_CM_FW_INFO:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB1003000"
+ range: "4K"
+ remote_slave: "1"
+ XML: "address_table/modules/FW_INFO.xml"
+ UHAL_BASE: 0x82000000
+ HDL:
+ out_name: "CM_FW_INFO"
+ map_template: "axi_generic/template_map.vhd"
+
+
+ F1_IPBUS:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ type: "AXI4"
+ addr:
+ offset: "0xB0000000"
+ range: "16M"
+ data_width: "64"
+ remote_slave: "1"
+ XML: "address_table/modules/IPBUS.xml"
+ UHAL_BASE: 0x85000000
+
+ F1_C2C_INTF:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB1010000"
+ range: "64K"
+ remote_slave: "1"
+ XML: "address_table/modules/C2C_INTFS.xml"
+ UHAL_BASE: 0x86000000
+ HDL:
+ out_name: "C2C_INTF"
+ map_template: "axi_generic/template_map_withbram.vhd"
+ SUB_SLAVES:
+ CM1_PB_UART:
+ TCL_CALL:
+ command: "AXI_IP_UART"
+ addr:
+ offset: "0xB1008000"
+ range: "4K"
+ irq_port: "F1_C2CB/axi_c2c_s2m_intr_in"
+ baud_rate: "115200"
+ axi_control: "${::AXI_MASTER_CTRL}"
+ manual_load_dtsi: "1"
+ remote_slave: "1"
+ dt_data: "compatible = \"xlnx,axi-uartlite-2.0\", \"xlnx,xps-uartlite-1.00.a\";current-speed = <115200>;device_type = \"serial\";interrupt-names = \"interrupt\";interrupt-parent = <&IRQ0_INTR_CTRL>;interrupts = <4 0>;port-number = <101>;xlnx,baudrate = <0x1c200>;xlnx,data-bits = <0x8>;xlnx,odd-parity = <0x0>;xlnx,s-axi-aclk-freq-hz-d = \"49.9995\";xlnx,use-parity = <0x0>;
+ "
+
+CORES:
+ onboardclk:
+ TCL_CALL:
+ command: BuildClockWizard
+ in_clk_type: Differential_clock_capable_pin
+ in_clk_freq_MHZ: 200
+ out_clks:
+ 1: 200
+ 2: 50
+
+
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/files.tcl b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/files.tcl
new file mode 100644
index 0000000..0ef59f9
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/files.tcl
@@ -0,0 +1,60 @@
+set bd_path proj
+
+array set bd_files [list {c2cSlave} {configs/${build_name}/createC2CSlaveInterconnect.tcl} \
+ ]
+
+set vhdl_files "\
+ configs/${build_name}/src/top.vhd \
+ configs/${build_name}/FPGA_heater/heater.vhd \
+ configs/${build_name}/FPGA_heater/lut_oscillator.vhd \
+ configs/${build_name}/src/ibert_ultrascale_gty_l.vhd \
+ configs/${build_name}/src/ibert_ultrascale_gty_r.vhd \
+ configs/${build_name}/src/VIRTEX_TCDS_map.vhd \
+ configs/${build_name}/src/VIRTEX_TCDS_PKG.vhd \
+ configs/${build_name}/src/TCDS.vhd \
+ src/misc/DC_data_CDC.vhd \
+ src/misc/pacd.vhd \
+ src/misc/types.vhd \
+ src/misc/capture_CDC.vhd \
+ src/misc/counter.vhd \
+ src/misc/counter_CDC.vhd \
+ regmap_helper/axiReg/axiRegWidthPkg_32.vhd \
+ regmap_helper/axiReg/axiRegPkg_d64.vhd \
+ regmap_helper/axiReg/axiRegPkg.vhd \
+ regmap_helper/axiReg/axiReg.vhd \
+ regmap_helper/axiReg/bramPortPkg.vhd \
+ regmap_helper/axiReg/axiRegBlocking.vhd \
+ src/C2C_INTF/C2C_Intf.vhd \
+ src/C2C_INTF/CM_phy_lane_control.vhd \
+ src/RGB_PWM.vhd \
+ src/LED_PWM.vhd \
+ src/misc/rate_counter.vhd \
+ src/CM_FW_info/CM_FW_info.vhd \
+ ${autogen_path}/IO/IO_PKG.vhd \
+ ${autogen_path}/IO/IO_map.vhd \
+ ${autogen_path}/C2C_INTF/C2C_INTF_map.vhd \
+ ${autogen_path}/C2C_INTF/C2C_INTF_PKG.vhd \
+ ${autogen_path}/CM_FW_INFO/CM_FW_INFO_PKG.vhd \
+ ${autogen_path}/CM_FW_INFO/CM_FW_INFO_map.vhd \
+ src/C2C_INTF/picoblaze/picoblaze/kcpsm6.vhd \
+ src/C2C_INTF/picoblaze/uart_rx6.vhd \
+ src/C2C_INTF/picoblaze/uart_tx6.vhd \
+ src/C2C_INTF/picoblaze/uC.vhd \
+ src/C2C_INTF/picoblaze/picoblaze/cli.vhd \
+ "
+set xdc_files "\
+ configs/${build_name}/src/top_pins.xdc \
+ configs/${build_name}/src/top_timing.xdc \
+ configs/${build_name}/src/top_heaters.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_l.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_l_clockgroups.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_r.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_r_clockgroups.xdc \
+ "
+
+set xci_files "\
+ cores/AXI_BRAM/AXI_BRAM.xci \
+ cores/DP_BRAM/DP_BRAM.xci \
+ configs/${build_name}/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci \
+ configs/${build_name}/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci \
+ "
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/settings.tcl b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/settings.tcl
new file mode 100644
index 0000000..4717d6f
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/settings.tcl
@@ -0,0 +1,19 @@
+
+#set the FPGA part number
+set FPGA_part xcvu13p-flga2577-1-e
+
+##for c2c
+set C2C F1_C2C
+set C2C_PHY ${C2C}_PHY
+set C2CB F1_C2CB
+set C2CB_PHY ${C2CB}_PHY
+
+#create remote device tree entries, 64 bit
+global REMOTE_C2C_64
+set REMOTE_C2C_64 1
+
+
+set top top
+
+set outputDir ./
+
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_PKG.vhd b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_PKG.vhd
new file mode 100644
index 0000000..059c5dc
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_PKG.vhd
@@ -0,0 +1,105 @@
+--This file was auto-generated.
+--Modifications might be lost.
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+package VIRTEX_TCDS_CTRL is
+ type VIRTEX_TCDS_CLOCKING_MON_t is record
+ COUNTS_REFCLK0 : std_logic_vector(31 downto 0);
+ COUNTS_TXOUTCLK : std_logic_vector(31 downto 0);
+ POWER_GOOD : std_logic;
+ QPLL0_FBCLKLOST : std_logic;
+ QPLL0_LOCK : std_logic;
+ QPLL0_REFCLKLOST : std_logic;
+ RX_CDR_STABLE : std_logic;
+ end record VIRTEX_TCDS_CLOCKING_MON_t;
+
+ type VIRTEX_TCDS_RESETS_MON_t is record
+ RX_PMA_RESET_DONE : std_logic;
+ RX_RESET_DONE : std_logic;
+ TX_PMA_RESET_DONE : std_logic;
+ TX_RESET_DONE : std_logic;
+ end record VIRTEX_TCDS_RESETS_MON_t;
+
+ type VIRTEX_TCDS_RESETS_CTRL_t is record
+ RESET_ALL : std_logic;
+ RX_DATAPATH : std_logic;
+ RX_PLL_DATAPATH : std_logic;
+ TX_DATAPATH : std_logic;
+ TX_PLL_DATAPATH : std_logic;
+ end record VIRTEX_TCDS_RESETS_CTRL_t;
+
+ type VIRTEX_TCDS_RX_MON_t is record
+ BAD_CHAR : std_logic_vector( 3 downto 0);
+ DISP_ERROR : std_logic_vector( 3 downto 0);
+ PMA_RESET_DONE : std_logic;
+ end record VIRTEX_TCDS_RX_MON_t;
+
+ type VIRTEX_TCDS_RX_CTRL_t is record
+ PRBS_RESET : std_logic;
+ PRBS_SEL : std_logic_vector( 3 downto 0);
+ USER_CLK_READY : std_logic;
+ end record VIRTEX_TCDS_RX_CTRL_t;
+
+ type VIRTEX_TCDS_TX_MON_t is record
+ PMA_RESET_DONE : std_logic;
+ PWR_GOOD : std_logic;
+ end record VIRTEX_TCDS_TX_MON_t;
+
+ type VIRTEX_TCDS_TX_CTRL_t is record
+ INHIBIT : std_logic;
+ PRBS_FORCE_ERROR : std_logic;
+ PRBS_SEL : std_logic_vector( 3 downto 0);
+ USER_CLK_READY : std_logic;
+ end record VIRTEX_TCDS_TX_CTRL_t;
+
+ type VIRTEX_TCDS_EYESCAN_CTRL_t is record
+ RESET : std_logic;
+ TRIGGER : std_logic;
+ end record VIRTEX_TCDS_EYESCAN_CTRL_t;
+
+ type VIRTEX_TCDS_DEBUG_MON_t is record
+ CAPTURE_D : std_logic_vector(31 downto 0);
+ CAPTURE_K : std_logic_vector( 3 downto 0);
+ end record VIRTEX_TCDS_DEBUG_MON_t;
+
+ type VIRTEX_TCDS_DEBUG_CTRL_t is record
+ CAPTURE : std_logic;
+ FIXED_SEND_D : std_logic_vector(31 downto 0);
+ FIXED_SEND_K : std_logic_vector( 3 downto 0);
+ MODE : std_logic_vector( 3 downto 0);
+ end record VIRTEX_TCDS_DEBUG_CTRL_t;
+
+ type VIRTEX_TCDS_Heater_MON_t is record
+ Output : std_logic_vector(31 downto 0);
+ end record VIRTEX_TCDS_Heater_MON_t;
+
+ type VIRTEX_TCDS_Heater_CTRL_t is record
+ Adjust : std_logic_vector(31 downto 0);
+ Enable : std_logic;
+ SelectHeater : std_logic_vector(31 downto 0);
+ end record VIRTEX_TCDS_Heater_CTRL_t;
+
+ type VIRTEX_TCDS_MON_t is record
+ CLOCKING : VIRTEX_TCDS_CLOCKING_MON_t;
+ DEBUG : VIRTEX_TCDS_DEBUG_MON_t;
+ Heater : VIRTEX_TCDS_Heater_MON_t;
+ RESETS : VIRTEX_TCDS_RESETS_MON_t;
+ RX : VIRTEX_TCDS_RX_MON_t;
+ TX : VIRTEX_TCDS_TX_MON_t;
+ end record VIRTEX_TCDS_MON_t;
+
+ type VIRTEX_TCDS_CTRL_t is record
+ DEBUG : VIRTEX_TCDS_DEBUG_CTRL_t;
+ EYESCAN : VIRTEX_TCDS_EYESCAN_CTRL_t;
+ Heater : VIRTEX_TCDS_Heater_CTRL_t;
+ LOOPBACK : std_logic_vector( 2 downto 0);
+ RESETS : VIRTEX_TCDS_RESETS_CTRL_t;
+ RX : VIRTEX_TCDS_RX_CTRL_t;
+ TX : VIRTEX_TCDS_TX_CTRL_t;
+ end record VIRTEX_TCDS_CTRL_t;
+
+
+
+end package VIRTEX_TCDS_CTRL;
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_map.vhd b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_map.vhd
new file mode 100644
index 0000000..15dab45
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_map.vhd
@@ -0,0 +1,209 @@
+--This file was auto-generated.
+--Modifications might be lost.
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.AXIRegPkg.all;
+use work.types.all;
+use work.VIRTEX_TCDS_Ctrl.all;
+entity VIRTEX_TCDS_interface is
+ port (
+ clk_axi : in std_logic;
+ reset_axi_n : in std_logic;
+ slave_readMOSI : in AXIReadMOSI;
+ slave_readMISO : out AXIReadMISO := DefaultAXIReadMISO;
+ slave_writeMOSI : in AXIWriteMOSI;
+ slave_writeMISO : out AXIWriteMISO := DefaultAXIWriteMISO;
+ Mon : in VIRTEX_TCDS_Mon_t;
+ Ctrl : out VIRTEX_TCDS_Ctrl_t
+ );
+end entity VIRTEX_TCDS_interface;
+architecture behavioral of VIRTEX_TCDS_interface is
+ signal localAddress : slv_32_t;
+ signal localRdData : slv_32_t;
+ signal localRdData_latch : slv_32_t;
+ signal localWrData : slv_32_t;
+ signal localWrEn : std_logic;
+ signal localRdReq : std_logic;
+ signal localRdAck : std_logic;
+
+
+ signal reg_data : slv32_array_t(integer range 0 to 83);
+ constant Default_reg_data : slv32_array_t(integer range 0 to 83) := (others => x"00000000");
+begin -- architecture behavioral
+
+ -------------------------------------------------------------------------------
+ -- AXI
+ -------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------
+ AXIRegBridge : entity work.axiLiteReg
+ port map (
+ clk_axi => clk_axi,
+ reset_axi_n => reset_axi_n,
+ readMOSI => slave_readMOSI,
+ readMISO => slave_readMISO,
+ writeMOSI => slave_writeMOSI,
+ writeMISO => slave_writeMISO,
+ address => localAddress,
+ rd_data => localRdData_latch,
+ wr_data => localWrData,
+ write_en => localWrEn,
+ read_req => localRdReq,
+ read_ack => localRdAck);
+
+ latch_reads: process (clk_axi) is
+ begin -- process latch_reads
+ if clk_axi'event and clk_axi = '1' then -- rising clock edge
+ if localRdReq = '1' then
+ localRdData_latch <= localRdData;
+ end if;
+ end if;
+ end process latch_reads;
+ reads: process (localRdReq,localAddress,reg_data) is
+ begin -- process reads
+ localRdAck <= '0';
+ localRdData <= x"00000000";
+ if localRdReq = '1' then
+ localRdAck <= '1';
+ case to_integer(unsigned(localAddress(6 downto 0))) is
+ when 0 => --0x0
+ localRdData( 1) <= Mon.CLOCKING.POWER_GOOD; --
+ localRdData( 9) <= Mon.CLOCKING.RX_CDR_STABLE; --
+ when 1 => --0x1
+ localRdData(31 downto 0) <= Mon.CLOCKING.COUNTS_TXOUTCLK; --
+ when 2 => --0x2
+ localRdData(31 downto 0) <= Mon.CLOCKING.COUNTS_REFCLK0; --
+ when 3 => --0x3
+ localRdData( 0) <= Mon.CLOCKING.QPLL0_LOCK; --
+ localRdData( 1) <= Mon.CLOCKING.QPLL0_FBCLKLOST; --
+ localRdData( 2) <= Mon.CLOCKING.QPLL0_REFCLKLOST; --
+ when 68 => --0x44
+ localRdData(31 downto 0) <= Mon.DEBUG.CAPTURE_D; --
+ when 5 => --0x5
+ localRdData( 0) <= reg_data( 5)( 0); --
+ localRdData( 4) <= reg_data( 5)( 4); --
+ localRdData( 5) <= reg_data( 5)( 5); --
+ localRdData( 8) <= reg_data( 5)( 8); --
+ localRdData( 9) <= reg_data( 5)( 9); --
+ when 6 => --0x6
+ localRdData( 6) <= Mon.RESETS.TX_RESET_DONE; --
+ localRdData( 7) <= Mon.RESETS.TX_PMA_RESET_DONE; --
+ localRdData(10) <= Mon.RESETS.RX_RESET_DONE; --
+ localRdData(11) <= Mon.RESETS.RX_PMA_RESET_DONE; --
+ when 32 => --0x20
+ localRdData( 1) <= Mon.TX.PMA_RESET_DONE; --
+ localRdData( 4) <= Mon.TX.PWR_GOOD; --
+ when 8 => --0x8
+ localRdData( 2 downto 0) <= reg_data( 8)( 2 downto 0); --
+ when 80 => --0x50
+ localRdData( 0) <= reg_data(80)( 0); --
+ when 71 => --0x47
+ localRdData( 3 downto 0) <= reg_data(71)( 3 downto 0); --
+ when 66 => --0x42
+ localRdData( 3 downto 0) <= reg_data(66)( 3 downto 0); --
+ when 16 => --0x10
+ localRdData( 1) <= Mon.RX.PMA_RESET_DONE; --
+ localRdData( 7 downto 4) <= Mon.RX.BAD_CHAR; --
+ localRdData(11 downto 8) <= Mon.RX.DISP_ERROR; --
+ when 17 => --0x11
+ localRdData( 3 downto 0) <= reg_data(17)( 3 downto 0); --
+ localRdData( 5) <= reg_data(17)( 5); --
+ when 82 => --0x52
+ localRdData(31 downto 0) <= reg_data(82)(31 downto 0); --
+ when 83 => --0x53
+ localRdData(31 downto 0) <= Mon.Heater.Output; --
+ when 49 => --0x31
+ localRdData( 0) <= reg_data(49)( 0); --
+ when 81 => --0x51
+ localRdData(31 downto 0) <= reg_data(81)(31 downto 0); --
+ when 33 => --0x21
+ localRdData( 3 downto 0) <= reg_data(33)( 3 downto 0); --
+ localRdData( 5) <= reg_data(33)( 5); --
+ localRdData( 6) <= reg_data(33)( 6); --
+ when 70 => --0x46
+ localRdData(31 downto 0) <= reg_data(70)(31 downto 0); --
+ when 69 => --0x45
+ localRdData( 3 downto 0) <= Mon.DEBUG.CAPTURE_K; --
+ when others =>
+ localRdData <= x"00000000";
+ end case;
+ end if;
+ end process reads;
+
+
+
+ -- Register mapping to ctrl structures
+ Ctrl.RESETS.RESET_ALL <= reg_data( 5)( 0);
+ Ctrl.RESETS.TX_PLL_DATAPATH <= reg_data( 5)( 4);
+ Ctrl.RESETS.TX_DATAPATH <= reg_data( 5)( 5);
+ Ctrl.RESETS.RX_PLL_DATAPATH <= reg_data( 5)( 8);
+ Ctrl.RESETS.RX_DATAPATH <= reg_data( 5)( 9);
+ Ctrl.LOOPBACK <= reg_data( 8)( 2 downto 0);
+ Ctrl.RX.PRBS_SEL <= reg_data(17)( 3 downto 0);
+ Ctrl.RX.USER_CLK_READY <= reg_data(17)( 5);
+ Ctrl.TX.PRBS_SEL <= reg_data(33)( 3 downto 0);
+ Ctrl.TX.INHIBIT <= reg_data(33)( 5);
+ Ctrl.TX.USER_CLK_READY <= reg_data(33)( 6);
+ Ctrl.EYESCAN.RESET <= reg_data(49)( 0);
+ Ctrl.DEBUG.MODE <= reg_data(66)( 3 downto 0);
+ Ctrl.DEBUG.FIXED_SEND_D <= reg_data(70)(31 downto 0);
+ Ctrl.DEBUG.FIXED_SEND_K <= reg_data(71)( 3 downto 0);
+ Ctrl.Heater.Enable <= reg_data(80)( 0);
+ Ctrl.Heater.Adjust <= reg_data(81)(31 downto 0);
+ Ctrl.Heater.SelectHeater <= reg_data(82)(31 downto 0);
+
+
+
+ reg_writes: process (clk_axi, reset_axi_n) is
+ begin -- process reg_writes
+ if reset_axi_n = '0' then -- asynchronous reset (active low)
+ reg_data <= default_reg_data;
+ elsif clk_axi'event and clk_axi = '1' then -- rising clock edge
+ Ctrl.RX.PRBS_RESET <= '0';
+ Ctrl.TX.PRBS_FORCE_ERROR <= '0';
+ Ctrl.EYESCAN.TRIGGER <= '0';
+ Ctrl.DEBUG.CAPTURE <= '0';
+
+ if localWrEn = '1' then
+ case to_integer(unsigned(localAddress(6 downto 0))) is
+ when 64 => --0x40
+ Ctrl.DEBUG.CAPTURE <= localWrData( 0);
+ when 33 => --0x21
+ Ctrl.TX.PRBS_FORCE_ERROR <= localWrData( 4);
+ reg_data(33)( 3 downto 0) <= localWrData( 3 downto 0); --
+ reg_data(33)( 5) <= localWrData( 5); --
+ reg_data(33)( 6) <= localWrData( 6); --
+ when 66 => --0x42
+ reg_data(66)( 3 downto 0) <= localWrData( 3 downto 0); --
+ when 5 => --0x5
+ reg_data( 5)( 0) <= localWrData( 0); --
+ reg_data( 5)( 4) <= localWrData( 4); --
+ reg_data( 5)( 5) <= localWrData( 5); --
+ reg_data( 5)( 8) <= localWrData( 8); --
+ reg_data( 5)( 9) <= localWrData( 9); --
+ when 70 => --0x46
+ reg_data(70)(31 downto 0) <= localWrData(31 downto 0); --
+ when 49 => --0x31
+ reg_data(49)( 0) <= localWrData( 0); --
+ Ctrl.EYESCAN.TRIGGER <= localWrData( 4);
+ when 8 => --0x8
+ reg_data( 8)( 2 downto 0) <= localWrData( 2 downto 0); --
+ when 71 => --0x47
+ reg_data(71)( 3 downto 0) <= localWrData( 3 downto 0); --
+ when 80 => --0x50
+ reg_data(80)( 0) <= localWrData( 0); --
+ when 17 => --0x11
+ Ctrl.RX.PRBS_RESET <= localWrData( 4);
+ reg_data(17)( 3 downto 0) <= localWrData( 3 downto 0); --
+ reg_data(17)( 5) <= localWrData( 5); --
+ when 82 => --0x52
+ reg_data(82)(31 downto 0) <= localWrData(31 downto 0); --
+ when 81 => --0x51
+ reg_data(81)(31 downto 0) <= localWrData(31 downto 0); --
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process reg_writes;
+
+end architecture behavioral;
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci
new file mode 100644
index 0000000..ee4cc04
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci
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diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci
new file mode 100644
index 0000000..c97822c
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci
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diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.vhd b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.vhd
new file mode 100644
index 0000000..33856b2
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.vhd
@@ -0,0 +1,498 @@
+
+--// file: ibert_ultrascale_gty_0.v
+--//////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2012.3
+--// \ \ Application : IBERT Ultrascale
+--// / / Filename : example_ibert_ultrascale_gty_0
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--// Module example_ibert_ultrascale_gty_0
+--// Generated by Xilinx IBERT_Ultrascale
+--//////////////////////////////////////////////////////////////////////////////
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.numeric_std.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity ibert_ultrascale_gty_l is
+ generic
+ (
+ C_NUM_GTY_QUADS : integer := 13;
+ C_GTY_REFCLKS_USED : integer :=6
+ );
+ port
+ (
+ gty_refclk0p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ gty_refclk0n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ -- gty_sysclk_i : in std_logic;
+ --gty_sysclkp_i : in std_logic;
+ --gty_sysclkn_i : in std_logic;
+ gty_rxn_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_rxp_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txn_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txp_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0)
+ );
+end entity ibert_ultrascale_gty_l;
+
+architecture proc of ibert_ultrascale_gty_l is
+-- //
+-- // Ibert refclk internal signals
+-- //
+
+ signal gty_qrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_refclk0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_refclk1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_sysclk_i: std_logic;
+begin
+
+
+ --
+ -- Sysclock IBUFDS instantiation
+ --
+ --u_ibufgds : IBUFGDS
+ -- generic map (
+ -- DIFF_TERM => true
+ -- ) port map (
+ -- I => gty_sysclkp_i,
+ -- IB => gty_sysclkn_i,
+ -- O => gty_sysclk_i
+ -- );
+
+ u_gty_sysclk_internal : BUFG_GT
+ port map (
+ I => gty_odiv2_0_i(1),
+ O => gty_sysclk_i,
+ CE => '1',
+ CEMASK => '0',
+ CLR => '0',
+ CLRMASK => '0',
+ DIV => "000"
+ );
+
+
+ --
+ -- Refclk IBUFDS instantiations
+ --
+
+
+ u_buf_q2_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(0),
+ ODIV2 => gty_odiv2_0_i(0),
+ CEB => '0',
+ I => gty_refclk0p_i(0),
+ IB => gty_refclk0n_i(0)
+ );
+
+
+ u_buf_q4_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(1),
+ ODIV2 => gty_odiv2_0_i(1),
+ CEB => '0',
+ I => gty_refclk0p_i(1),
+ IB => gty_refclk0n_i(1)
+ );
+
+ --u_buf_q2_clk1 :IBUFDS_GTE4
+ -- port map(
+ -- O => gty_refclk1_i(0),
+ -- ODIV2 => gty_odiv2_1_i(0),
+ -- CEB => '0',
+ -- I => gty_refclk1p_i(0),
+ -- IB => gty_refclk1n_i(0)
+ -- );
+
+ u_buf_q6_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(2),
+ ODIV2 => gty_odiv2_0_i(2),
+ CEB => '0',
+ I => gty_refclk0p_i(2),
+ IB => gty_refclk0n_i(2)
+ );
+
+ u_buf_q9_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(3),
+ ODIV2 => gty_odiv2_0_i(3),
+ CEB => '0',
+ I => gty_refclk0p_i(3),
+ IB => gty_refclk0n_i(3)
+ );
+
+
+ u_buf_q10_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(4),
+ ODIV2 => gty_odiv2_0_i(4),
+ CEB => '0',
+ I => gty_refclk0p_i(4),
+ IB => gty_refclk0n_i(4)
+ );
+
+ u_buf_q13_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(5),
+ ODIV2 => gty_odiv2_0_i(5),
+ CEB => '0',
+ I => gty_refclk0p_i(5),
+ IB => gty_refclk0n_i(5)
+ );
+
+
+ --
+ -- Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
+ --
+-- gty_qrefclk0_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk1_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qnorthrefclk0_i(0) <= '0';
+-- gty_qnorthrefclk1_i(0) <= '0';
+-- gty_qsouthrefclk0_i(0) <= '0';
+-- gty_qsouthrefclk1_i(0) <= '0';
+----GTYE4_COMMON clock connection
+-- gty_qrefclk00_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk10_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qrefclk01_i(0) <= '0';
+-- gty_qrefclk11_i(0) <= '0';
+-- gty_qnorthrefclk00_i(0) <= '0';
+-- gty_qnorthrefclk10_i(0) <= '0';
+-- gty_qnorthrefclk01_i(0) <= '0';
+-- gty_qnorthrefclk11_i(0) <= '0';
+-- gty_qsouthrefclk00_i(0) <= '0';
+-- gty_qsouthrefclk10_i(0) <= '0';
+-- gty_qsouthrefclk01_i(0) <= '0';
+-- gty_qsouthrefclk11_i(0) <= '0';
+--
+--
+
+ gty_qrefclk0_i(0) <= '0';
+ gty_qrefclk1_i(0) <= '0';
+ gty_qnorthrefclk0_i(0) <= '0';
+ gty_qnorthrefclk1_i(0) <= '0';
+ gty_qsouthrefclk0_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk1_i(0) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(0) <= '0';
+ gty_qrefclk10_i(0) <= '0';
+ gty_qrefclk01_i(0) <= '0';
+ gty_qrefclk11_i(0) <= '0';
+ gty_qnorthrefclk00_i(0) <= '0';
+ gty_qnorthrefclk10_i(0) <= '0';
+ gty_qnorthrefclk01_i(0) <= '0';
+ gty_qnorthrefclk11_i(0) <= '0';
+ gty_qsouthrefclk00_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk10_i(0) <= '0';
+ gty_qsouthrefclk01_i(0) <= '0';
+ gty_qsouthrefclk11_i(0) <= '0';
+
+
+ gty_qrefclk0_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk1_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(1) <= '0';
+ gty_qnorthrefclk1_i(1) <= '0';
+ gty_qsouthrefclk0_i(1) <= '0';
+ gty_qsouthrefclk1_i(1) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk10_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(1) <= '0';
+ gty_qrefclk11_i(1) <= '0';
+ gty_qnorthrefclk00_i(1) <= '0';
+ gty_qnorthrefclk10_i(1) <= '0';
+ gty_qnorthrefclk01_i(1) <= '0';
+ gty_qnorthrefclk11_i(1) <= '0';
+ gty_qsouthrefclk00_i(1) <= '0';
+ gty_qsouthrefclk10_i(1) <= '0';
+ gty_qsouthrefclk01_i(1) <= '0';
+ gty_qsouthrefclk11_i(1) <= '0';
+
+
+ gty_qrefclk0_i(2) <= '0';
+ gty_qrefclk1_i(2) <= '0';
+ gty_qnorthrefclk0_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk1_i(2) <= '0';
+ gty_qsouthrefclk0_i(2) <= '0';
+ gty_qsouthrefclk1_i(2) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(2) <= '0';
+ gty_qrefclk10_i(2) <= '0';
+ gty_qrefclk01_i(2) <= '0';
+ gty_qrefclk11_i(2) <= '0';
+ gty_qnorthrefclk00_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk10_i(2) <= '0';
+ gty_qnorthrefclk01_i(2) <= '0';
+ gty_qnorthrefclk11_i(2) <= '0';
+ gty_qsouthrefclk00_i(2) <= '0';
+ gty_qsouthrefclk10_i(2) <= '0';
+ gty_qsouthrefclk01_i(2) <= '0';
+ gty_qsouthrefclk11_i(2) <= '0';
+
+
+ gty_qrefclk0_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk1_i(3) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(3) <= '0';
+ gty_qnorthrefclk1_i(3) <= '0';
+ gty_qsouthrefclk0_i(3) <= '0';
+ gty_qsouthrefclk1_i(3) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk10_i(3) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(3) <= '0';
+ gty_qrefclk11_i(3) <= '0';
+ gty_qnorthrefclk00_i(3) <= '0';
+ gty_qnorthrefclk10_i(3) <= '0';
+ gty_qnorthrefclk01_i(3) <= '0';
+ gty_qnorthrefclk11_i(3) <= '0';
+ gty_qsouthrefclk00_i(3) <= '0';
+ gty_qsouthrefclk10_i(3) <= '0';
+ gty_qsouthrefclk01_i(3) <= '0';
+ gty_qsouthrefclk11_i(3) <= '0';
+
+ gty_qrefclk0_i(4) <= '0';
+ gty_qrefclk1_i(4) <= '0';
+ gty_qnorthrefclk0_i(4) <= '0';
+ gty_qnorthrefclk1_i(4) <= '0';
+ gty_qsouthrefclk0_i(4) <= gty_refclk0_i(2);
+ gty_qsouthrefclk1_i(4) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(4) <= '0';
+ gty_qrefclk10_i(4) <= '0';
+ gty_qrefclk01_i(4) <= '0';
+ gty_qrefclk11_i(4) <= '0';
+ gty_qnorthrefclk00_i(4) <= '0';
+ gty_qnorthrefclk10_i(4) <= '0';
+ gty_qnorthrefclk01_i(4) <= '0';
+ gty_qnorthrefclk11_i(4) <= '0';
+ gty_qsouthrefclk00_i(4) <= gty_refclk0_i(2);
+ gty_qsouthrefclk10_i(4) <= '0';
+ gty_qsouthrefclk01_i(4) <= '0';
+ gty_qsouthrefclk11_i(4) <= '0';
+
+
+ gty_qrefclk0_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk1_i(5) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(5) <= '0';
+ gty_qnorthrefclk1_i(5) <= '0';
+ gty_qsouthrefclk0_i(5) <= '0';
+ gty_qsouthrefclk1_i(5) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk10_i(5) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(5) <= '0';
+ gty_qrefclk11_i(5) <= '0';
+ gty_qnorthrefclk00_i(5) <= '0';
+ gty_qnorthrefclk10_i(5) <= '0';
+ gty_qnorthrefclk01_i(5) <= '0';
+ gty_qnorthrefclk11_i(5) <= '0';
+ gty_qsouthrefclk00_i(5) <= '0';
+ gty_qsouthrefclk10_i(5) <= '0';
+ gty_qsouthrefclk01_i(5) <= '0';
+ gty_qsouthrefclk11_i(5) <= '0';
+
+
+ gty_qrefclk0_i(6) <= '0';
+ gty_qrefclk1_i(6) <= '0';
+ gty_qnorthrefclk0_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk1_i(6) <= '0';
+ gty_qsouthrefclk0_i(6) <= '0';
+ gty_qsouthrefclk1_i(6) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(6) <= '0';
+ gty_qrefclk10_i(6) <= '0';
+ gty_qrefclk01_i(6) <= '0';
+ gty_qrefclk11_i(6) <= '0';
+ gty_qnorthrefclk00_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk10_i(6) <= '0';
+ gty_qnorthrefclk01_i(6) <= '0';
+ gty_qnorthrefclk11_i(6) <= '0';
+ gty_qsouthrefclk00_i(6) <= '0';
+ gty_qsouthrefclk10_i(6) <= '0';
+ gty_qsouthrefclk01_i(6) <= '0';
+ gty_qsouthrefclk11_i(6) <= '0';
+
+ gty_qrefclk0_i(7) <= '0';
+ gty_qrefclk1_i(7) <= '0';
+ gty_qnorthrefclk0_i(7) <= '0';
+ gty_qnorthrefclk1_i(7) <= '0';
+ gty_qsouthrefclk0_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk1_i(7) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(7) <= '0';
+ gty_qrefclk10_i(7) <= '0';
+ gty_qrefclk01_i(7) <= '0';
+ gty_qrefclk11_i(7) <= '0';
+ gty_qnorthrefclk00_i(7) <= '0';
+ gty_qnorthrefclk10_i(7) <= '0';
+ gty_qnorthrefclk01_i(7) <= '0';
+ gty_qnorthrefclk11_i(7) <= '0';
+ gty_qsouthrefclk00_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk10_i(7) <= '0';
+ gty_qsouthrefclk01_i(7) <= '0';
+ gty_qsouthrefclk11_i(7) <= '0';
+
+ gty_qrefclk0_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk1_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qnorthrefclk0_i(8) <= '0';
+ gty_qnorthrefclk1_i(8) <= '0';
+ gty_qsouthrefclk0_i(8) <= '0';
+ gty_qsouthrefclk1_i(8) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk10_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qrefclk01_i(8) <= '0';
+ gty_qrefclk11_i(8) <= '0';
+ gty_qnorthrefclk00_i(8) <= '0';
+ gty_qnorthrefclk10_i(8) <= '0';
+ gty_qnorthrefclk01_i(8) <= '0';
+ gty_qnorthrefclk11_i(8) <= '0';
+ gty_qsouthrefclk00_i(8) <= '0';
+ gty_qsouthrefclk10_i(8) <= '0';
+ gty_qsouthrefclk01_i(8) <= '0';
+ gty_qsouthrefclk11_i(8) <= '0';
+
+
+ gty_qrefclk0_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk1_i(9) <= '0';
+ gty_qnorthrefclk0_i(9) <= '0';
+ gty_qnorthrefclk1_i(9) <= '0';
+ gty_qsouthrefclk0_i(9) <= '0';
+ gty_qsouthrefclk1_i(9) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk10_i(9) <= '0';
+ gty_qrefclk01_i(9) <= '0';
+ gty_qrefclk11_i(9) <= '0';
+ gty_qnorthrefclk00_i(9) <= '0';
+ gty_qnorthrefclk10_i(9) <= '0';
+ gty_qnorthrefclk01_i(9) <= '0';
+ gty_qnorthrefclk11_i(9) <= '0';
+ gty_qsouthrefclk00_i(9) <= '0';
+ gty_qsouthrefclk10_i(9) <= '0';
+ gty_qsouthrefclk01_i(9) <= '0';
+ gty_qsouthrefclk11_i(9) <= '0';
+
+
+ gty_qrefclk0_i(10) <= '0';
+ gty_qrefclk1_i(10) <= '0';
+ gty_qnorthrefclk0_i(10) <= '0';
+ gty_qnorthrefclk1_i(10) <= '0';
+ gty_qsouthrefclk0_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk1_i(10) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(10) <= '0';
+ gty_qrefclk10_i(10) <= '0';
+ gty_qrefclk01_i(10) <= '0';
+ gty_qrefclk11_i(10) <= '0';
+ gty_qnorthrefclk00_i(10) <= '0';
+ gty_qnorthrefclk10_i(10) <= '0';
+ gty_qnorthrefclk01_i(10) <= '0';
+ gty_qnorthrefclk11_i(10) <= '0';
+ gty_qsouthrefclk00_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk10_i(10) <= '0';
+ gty_qsouthrefclk01_i(10) <= '0';
+ gty_qsouthrefclk11_i(10) <= '0';
+
+
+ gty_qrefclk0_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk1_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qnorthrefclk0_i(11) <= '0';
+ gty_qnorthrefclk1_i(11) <= '0';
+ gty_qsouthrefclk0_i(11) <= '0';
+ gty_qsouthrefclk1_i(11) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk10_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qrefclk01_i(11) <= '0';
+ gty_qrefclk11_i(11) <= '0';
+ gty_qnorthrefclk00_i(11) <= '0';
+ gty_qnorthrefclk10_i(11) <= '0';
+ gty_qnorthrefclk01_i(11) <= '0';
+ gty_qnorthrefclk11_i(11) <= '0';
+ gty_qsouthrefclk00_i(11) <= '0';
+ gty_qsouthrefclk10_i(11) <= '0';
+ gty_qsouthrefclk01_i(11) <= '0';
+ gty_qsouthrefclk11_i(11) <= '0';
+
+
+ gty_qrefclk0_i(12) <= '0';
+ gty_qrefclk1_i(12) <= '0';
+ gty_qnorthrefclk0_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk1_i(12) <= '0';
+ gty_qsouthrefclk0_i(12) <= '0';
+ gty_qsouthrefclk1_i(12) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(12) <= '0';
+ gty_qrefclk10_i(12) <= '0';
+ gty_qrefclk01_i(12) <= '0';
+ gty_qrefclk11_i(12) <= '0';
+ gty_qnorthrefclk00_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk10_i(12) <= '0';
+ gty_qnorthrefclk01_i(12) <= '0';
+ gty_qnorthrefclk11_i(12) <= '0';
+ gty_qsouthrefclk00_i(12) <= '0';
+ gty_qsouthrefclk10_i(12) <= '0';
+ gty_qsouthrefclk01_i(12) <= '0';
+ gty_qsouthrefclk11_i(12) <= '0';
+ --
+ -- IBERT core instantiation
+ --
+ u_ibert_gty_core : entity work.ibert_ultrascale_gty_core_l
+ port map (
+ txn_o => gty_txn_o,
+ txp_o => gty_txp_o,
+ rxn_i => gty_rxn_i,
+ rxp_i => gty_rxp_i,
+ clk => gty_sysclk_i,
+ gtrefclk0_i => gty_qrefclk0_i,
+ gtrefclk1_i => gty_qrefclk1_i,
+ gtnorthrefclk0_i => gty_qnorthrefclk0_i,
+ gtnorthrefclk1_i => gty_qnorthrefclk1_i,
+ gtsouthrefclk0_i => gty_qsouthrefclk0_i,
+ gtsouthrefclk1_i => gty_qsouthrefclk1_i,
+ gtrefclk00_i => gty_qrefclk00_i,
+ gtrefclk10_i => gty_qrefclk10_i,
+ gtrefclk01_i => gty_qrefclk01_i,
+ gtrefclk11_i => gty_qrefclk11_i,
+ gtnorthrefclk00_i => gty_qnorthrefclk00_i,
+ gtnorthrefclk10_i => gty_qnorthrefclk10_i,
+ gtnorthrefclk01_i => gty_qnorthrefclk01_i,
+ gtnorthrefclk11_i => gty_qnorthrefclk11_i,
+ gtsouthrefclk00_i => gty_qsouthrefclk00_i,
+ gtsouthrefclk10_i => gty_qsouthrefclk10_i,
+ gtsouthrefclk01_i => gty_qsouthrefclk01_i,
+ gtsouthrefclk11_i => gty_qsouthrefclk11_i
+ );
+
+end proc;
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.xdc b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.xdc
new file mode 100644
index 0000000..92004d2
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.xdc
@@ -0,0 +1,70 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2012.3
+## \ \ Application : IBERT Ultrascale
+## / / Filename : example_ibert_ultrascale_gty_0.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+##
+## Icon Constraints
+##
+
+set_property C_CLK_INPUT_FREQ_HZ 50000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets AXI_CLK]
+
+##
+##gtrefclk lock constraints
+##
+## set_property PACKAGE_PIN AY39 [get_ports gty_refclk0p_i[0]]
+## set_property PACKAGE_PIN AY40 [get_ports gty_refclk0n_i[0]]
+## set_property PACKAGE_PIN AW41 [get_ports gty_refclk1p_i[0]]
+## set_property PACKAGE_PIN AW42 [get_ports gty_refclk1n_i[0]]
+## set_property PACKAGE_PIN AT39 [get_ports gty_refclk0p_i[1]]
+## set_property PACKAGE_PIN AT40 [get_ports gty_refclk0n_i[1]]
+## set_property PACKAGE_PIN AR41 [get_ports gty_refclk1p_i[1]]
+## set_property PACKAGE_PIN AR42 [get_ports gty_refclk1n_i[1]]
+## set_property PACKAGE_PIN AM39 [get_ports gty_refclk0p_i[2]]
+## set_property PACKAGE_PIN AM40 [get_ports gty_refclk0n_i[2]]
+## set_property PACKAGE_PIN AL41 [get_ports gty_refclk1p_i[2]]
+## set_property PACKAGE_PIN AL42 [get_ports gty_refclk1n_i[2]]
+## set_property PACKAGE_PIN AA41 [get_ports gty_refclk0p_i[3]]
+## set_property PACKAGE_PIN AA42 [get_ports gty_refclk0n_i[3]]
+## set_property PACKAGE_PIN Y39 [get_ports gty_refclk1p_i[3]]
+## set_property PACKAGE_PIN Y40 [get_ports gty_refclk1n_i[3]]
+## set_property PACKAGE_PIN W41 [get_ports gty_refclk0p_i[4]]
+## set_property PACKAGE_PIN W42 [get_ports gty_refclk0n_i[4]]
+## set_property PACKAGE_PIN V39 [get_ports gty_refclk1p_i[4]]
+## set_property PACKAGE_PIN V40 [get_ports gty_refclk1n_i[4]]
+## set_property PACKAGE_PIN N41 [get_ports gty_refclk0p_i[5]]
+## set_property PACKAGE_PIN N42 [get_ports gty_refclk0n_i[5]]
+## set_property PACKAGE_PIN M39 [get_ports gty_refclk1p_i[5]]
+## set_property PACKAGE_PIN M40 [get_ports gty_refclk1n_i[5]]
+##
+## Refclk constraints
+##
+#create_clock -name gtrefclk0_2 -period 3.104 [get_ports p_lf_r0_ad]
+create_clock -name gtrefclk0_2 -period 3.1030303 [get_ports p_lf_r0_ad]
+set_clock_groups -group [get_clocks gtrefclk0_2 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_4 -period 3.1030303 [get_ports p_lf_r0_af]
+set_clock_groups -group [get_clocks gtrefclk0_4 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_6 -period 3.1030303 [get_ports p_lf_r0_r]
+set_clock_groups -group [get_clocks gtrefclk0_6 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_9 -period 3.1030303 [get_ports p_lf_r0_u]
+set_clock_groups -group [get_clocks gtrefclk0_9 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_10 -period 3.1030303 [get_ports p_lf_r0_v]
+set_clock_groups -group [get_clocks gtrefclk0_10 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_13 -period 3.1030303 [get_ports p_lf_r0_y]
+set_clock_groups -group [get_clocks gtrefclk0_13 -include_generated_clocks] -asynchronous
+
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l_clockgroups.xdc b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l_clockgroups.xdc
new file mode 100644
index 0000000..aa0ef57
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l_clockgroups.xdc
@@ -0,0 +1,175 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2017.1
+## \ \ Application : IBERT Ultrascale
+## / / Filename : ibert_ultrascale_gty_ip_example.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+## TX/RX out clock clock constraints
+##
+# GT X0Y4
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y5
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y6
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y7
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y8
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y9
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y10
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y11
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y12
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y13
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y14
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y15
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y16
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y17
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y18
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y19
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y20
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y21
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y22
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y23
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y24
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y25
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y26
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y27
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y28
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y29
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y30
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y31
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y32
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y33
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y34
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y35
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y36
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y37
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y38
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y39
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y40
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y41
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y42
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y43
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y48
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y49
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y50
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y51
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y52
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y53
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y54
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y55
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y56
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y57
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y58
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y59
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.vhd b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.vhd
new file mode 100644
index 0000000..1945307
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.vhd
@@ -0,0 +1,498 @@
+
+--// file: ibert_ultrascale_gty_0.v
+--//////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2012.3
+--// \ \ Application : IBERT Ultrascale
+--// / / Filename : example_ibert_ultrascale_gty_0
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--// Module example_ibert_ultrascale_gty_0
+--// Generated by Xilinx IBERT_Ultrascale
+--//////////////////////////////////////////////////////////////////////////////
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.numeric_std.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity ibert_ultrascale_gty_r is
+ generic
+ (
+ C_NUM_GTY_QUADS : integer := 13;
+ C_GTY_REFCLKS_USED : integer :=6
+ );
+ port
+ (
+ gty_refclk0p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ gty_refclk0n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ -- gty_sysclk_i : in std_logic;
+ --gty_sysclkp_i : in std_logic;
+ --gty_sysclkn_i : in std_logic;
+ gty_rxn_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_rxp_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txn_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txp_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0)
+ );
+end entity ibert_ultrascale_gty_r;
+
+architecture proc of ibert_ultrascale_gty_r is
+-- //
+-- // Ibert refclk internal signals
+-- //
+
+ signal gty_qrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_refclk0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_refclk1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_sysclk_i: std_logic;
+begin
+
+
+ --
+ -- Sysclock IBUFDS instantiation
+ --
+ --u_ibufgds : IBUFGDS
+ -- generic map (
+ -- DIFF_TERM => true
+ -- ) port map (
+ -- I => gty_sysclkp_i,
+ -- IB => gty_sysclkn_i,
+ -- O => gty_sysclk_i
+ -- );
+
+ u_gty_sysclk_internal : BUFG_GT
+ port map (
+ I => gty_odiv2_0_i(4),
+ O => gty_sysclk_i,
+ CE => '1',
+ CEMASK => '0',
+ CLR => '0',
+ CLRMASK => '0',
+ DIV => "000"
+ );
+
+
+ --
+ -- Refclk IBUFDS instantiations
+ --
+
+
+ u_buf_q2_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(0),
+ ODIV2 => gty_odiv2_0_i(0),
+ CEB => '0',
+ I => gty_refclk0p_i(0),
+ IB => gty_refclk0n_i(0)
+ );
+
+
+ u_buf_q4_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(1),
+ ODIV2 => gty_odiv2_0_i(1),
+ CEB => '0',
+ I => gty_refclk0p_i(1),
+ IB => gty_refclk0n_i(1)
+ );
+
+ --u_buf_q2_clk1 :IBUFDS_GTE4
+ -- port map(
+ -- O => gty_refclk1_i(0),
+ -- ODIV2 => gty_odiv2_1_i(0),
+ -- CEB => '0',
+ -- I => gty_refclk1p_i(0),
+ -- IB => gty_refclk1n_i(0)
+ -- );
+
+ u_buf_q6_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(2),
+ ODIV2 => gty_odiv2_0_i(2),
+ CEB => '0',
+ I => gty_refclk0p_i(2),
+ IB => gty_refclk0n_i(2)
+ );
+
+ u_buf_q9_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(3),
+ ODIV2 => gty_odiv2_0_i(3),
+ CEB => '0',
+ I => gty_refclk0p_i(3),
+ IB => gty_refclk0n_i(3)
+ );
+
+
+ u_buf_q10_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(4),
+ ODIV2 => gty_odiv2_0_i(4),
+ CEB => '0',
+ I => gty_refclk0p_i(4),
+ IB => gty_refclk0n_i(4)
+ );
+
+ u_buf_q13_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(5),
+ ODIV2 => gty_odiv2_0_i(5),
+ CEB => '0',
+ I => gty_refclk0p_i(5),
+ IB => gty_refclk0n_i(5)
+ );
+
+
+ --
+ -- Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
+ --
+-- gty_qrefclk0_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk1_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qnorthrefclk0_i(0) <= '0';
+-- gty_qnorthrefclk1_i(0) <= '0';
+-- gty_qsouthrefclk0_i(0) <= '0';
+-- gty_qsouthrefclk1_i(0) <= '0';
+----GTYE4_COMMON clock connection
+-- gty_qrefclk00_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk10_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qrefclk01_i(0) <= '0';
+-- gty_qrefclk11_i(0) <= '0';
+-- gty_qnorthrefclk00_i(0) <= '0';
+-- gty_qnorthrefclk10_i(0) <= '0';
+-- gty_qnorthrefclk01_i(0) <= '0';
+-- gty_qnorthrefclk11_i(0) <= '0';
+-- gty_qsouthrefclk00_i(0) <= '0';
+-- gty_qsouthrefclk10_i(0) <= '0';
+-- gty_qsouthrefclk01_i(0) <= '0';
+-- gty_qsouthrefclk11_i(0) <= '0';
+--
+--
+
+ gty_qrefclk0_i(0) <= '0';
+ gty_qrefclk1_i(0) <= '0';
+ gty_qnorthrefclk0_i(0) <= '0';
+ gty_qnorthrefclk1_i(0) <= '0';
+ gty_qsouthrefclk0_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk1_i(0) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(0) <= '0';
+ gty_qrefclk10_i(0) <= '0';
+ gty_qrefclk01_i(0) <= '0';
+ gty_qrefclk11_i(0) <= '0';
+ gty_qnorthrefclk00_i(0) <= '0';
+ gty_qnorthrefclk10_i(0) <= '0';
+ gty_qnorthrefclk01_i(0) <= '0';
+ gty_qnorthrefclk11_i(0) <= '0';
+ gty_qsouthrefclk00_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk10_i(0) <= '0';
+ gty_qsouthrefclk01_i(0) <= '0';
+ gty_qsouthrefclk11_i(0) <= '0';
+
+
+ gty_qrefclk0_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk1_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(1) <= '0';
+ gty_qnorthrefclk1_i(1) <= '0';
+ gty_qsouthrefclk0_i(1) <= '0';
+ gty_qsouthrefclk1_i(1) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk10_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(1) <= '0';
+ gty_qrefclk11_i(1) <= '0';
+ gty_qnorthrefclk00_i(1) <= '0';
+ gty_qnorthrefclk10_i(1) <= '0';
+ gty_qnorthrefclk01_i(1) <= '0';
+ gty_qnorthrefclk11_i(1) <= '0';
+ gty_qsouthrefclk00_i(1) <= '0';
+ gty_qsouthrefclk10_i(1) <= '0';
+ gty_qsouthrefclk01_i(1) <= '0';
+ gty_qsouthrefclk11_i(1) <= '0';
+
+
+ gty_qrefclk0_i(2) <= '0';
+ gty_qrefclk1_i(2) <= '0';
+ gty_qnorthrefclk0_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk1_i(2) <= '0';
+ gty_qsouthrefclk0_i(2) <= '0';
+ gty_qsouthrefclk1_i(2) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(2) <= '0';
+ gty_qrefclk10_i(2) <= '0';
+ gty_qrefclk01_i(2) <= '0';
+ gty_qrefclk11_i(2) <= '0';
+ gty_qnorthrefclk00_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk10_i(2) <= '0';
+ gty_qnorthrefclk01_i(2) <= '0';
+ gty_qnorthrefclk11_i(2) <= '0';
+ gty_qsouthrefclk00_i(2) <= '0';
+ gty_qsouthrefclk10_i(2) <= '0';
+ gty_qsouthrefclk01_i(2) <= '0';
+ gty_qsouthrefclk11_i(2) <= '0';
+
+
+ gty_qrefclk0_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk1_i(3) <= '0';
+ gty_qnorthrefclk0_i(3) <= '0';
+ gty_qnorthrefclk1_i(3) <= '0';
+ gty_qsouthrefclk0_i(3) <= '0';
+ gty_qsouthrefclk1_i(3) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk10_i(3) <= '0';
+ gty_qrefclk01_i(3) <= '0';
+ gty_qrefclk11_i(3) <= '0';
+ gty_qnorthrefclk00_i(3) <= '0';
+ gty_qnorthrefclk10_i(3) <= '0';
+ gty_qnorthrefclk01_i(3) <= '0';
+ gty_qnorthrefclk11_i(3) <= '0';
+ gty_qsouthrefclk00_i(3) <= '0';
+ gty_qsouthrefclk10_i(3) <= '0';
+ gty_qsouthrefclk01_i(3) <= '0';
+ gty_qsouthrefclk11_i(3) <= '0';
+
+ gty_qrefclk0_i(4) <= '0';
+ gty_qrefclk1_i(4) <= '0';
+ gty_qnorthrefclk0_i(4) <= gty_refclk0_i(1);
+ gty_qnorthrefclk1_i(4) <= '0';
+ gty_qsouthrefclk0_i(4) <= '0';
+ gty_qsouthrefclk1_i(4) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(4) <= '0';
+ gty_qrefclk10_i(4) <= '0';
+ gty_qrefclk01_i(4) <= '0';
+ gty_qrefclk11_i(4) <= '0';
+ gty_qnorthrefclk00_i(4) <= gty_refclk0_i(1);
+ gty_qnorthrefclk10_i(4) <= '0';
+ gty_qnorthrefclk01_i(4) <= '0';
+ gty_qnorthrefclk11_i(4) <= '0';
+ gty_qsouthrefclk00_i(4) <= '0';
+ gty_qsouthrefclk10_i(4) <= '0';
+ gty_qsouthrefclk01_i(4) <= '0';
+ gty_qsouthrefclk11_i(4) <= '0';
+
+
+ gty_qrefclk0_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk1_i(5) <= '0';
+ gty_qnorthrefclk0_i(5) <= '0';
+ gty_qnorthrefclk1_i(5) <= '0';
+ gty_qsouthrefclk0_i(5) <= '0';
+ gty_qsouthrefclk1_i(5) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk10_i(5) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(5) <= '0';
+ gty_qrefclk11_i(5) <= '0';
+ gty_qnorthrefclk00_i(5) <= '0';
+ gty_qnorthrefclk10_i(5) <= '0';
+ gty_qnorthrefclk01_i(5) <= '0';
+ gty_qnorthrefclk11_i(5) <= '0';
+ gty_qsouthrefclk00_i(5) <= '0';
+ gty_qsouthrefclk10_i(5) <= '0';
+ gty_qsouthrefclk01_i(5) <= '0';
+ gty_qsouthrefclk11_i(5) <= '0';
+
+
+ gty_qrefclk0_i(6) <= '0';
+ gty_qrefclk1_i(6) <= '0';
+ gty_qnorthrefclk0_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk1_i(6) <= '0';
+ gty_qsouthrefclk0_i(6) <= '0';
+ gty_qsouthrefclk1_i(6) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(6) <= '0';
+ gty_qrefclk10_i(6) <= '0';
+ gty_qrefclk01_i(6) <= '0';
+ gty_qrefclk11_i(6) <= '0';
+ gty_qnorthrefclk00_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk10_i(6) <= '0';
+ gty_qnorthrefclk01_i(6) <= '0';
+ gty_qnorthrefclk11_i(6) <= '0';
+ gty_qsouthrefclk00_i(6) <= '0';
+ gty_qsouthrefclk10_i(6) <= '0';
+ gty_qsouthrefclk01_i(6) <= '0';
+ gty_qsouthrefclk11_i(6) <= '0';
+
+ gty_qrefclk0_i(7) <= '0';
+ gty_qrefclk1_i(7) <= '0';
+ gty_qnorthrefclk0_i(7) <= '0';
+ gty_qnorthrefclk1_i(7) <= '0';
+ gty_qsouthrefclk0_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk1_i(7) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(7) <= '0';
+ gty_qrefclk10_i(7) <= '0';
+ gty_qrefclk01_i(7) <= '0';
+ gty_qrefclk11_i(7) <= '0';
+ gty_qnorthrefclk00_i(7) <= '0';
+ gty_qnorthrefclk10_i(7) <= '0';
+ gty_qnorthrefclk01_i(7) <= '0';
+ gty_qnorthrefclk11_i(7) <= '0';
+ gty_qsouthrefclk00_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk10_i(7) <= '0';
+ gty_qsouthrefclk01_i(7) <= '0';
+ gty_qsouthrefclk11_i(7) <= '0';
+
+ gty_qrefclk0_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk1_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qnorthrefclk0_i(8) <= '0';
+ gty_qnorthrefclk1_i(8) <= '0';
+ gty_qsouthrefclk0_i(8) <= '0';
+ gty_qsouthrefclk1_i(8) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk10_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qrefclk01_i(8) <= '0';
+ gty_qrefclk11_i(8) <= '0';
+ gty_qnorthrefclk00_i(8) <= '0';
+ gty_qnorthrefclk10_i(8) <= '0';
+ gty_qnorthrefclk01_i(8) <= '0';
+ gty_qnorthrefclk11_i(8) <= '0';
+ gty_qsouthrefclk00_i(8) <= '0';
+ gty_qsouthrefclk10_i(8) <= '0';
+ gty_qsouthrefclk01_i(8) <= '0';
+ gty_qsouthrefclk11_i(8) <= '0';
+
+
+ gty_qrefclk0_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk1_i(9) <= '0';
+ gty_qnorthrefclk0_i(9) <= '0';
+ gty_qnorthrefclk1_i(9) <= '0';
+ gty_qsouthrefclk0_i(9) <= '0';
+ gty_qsouthrefclk1_i(9) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk10_i(9) <= '0';
+ gty_qrefclk01_i(9) <= '0';
+ gty_qrefclk11_i(9) <= '0';
+ gty_qnorthrefclk00_i(9) <= '0';
+ gty_qnorthrefclk10_i(9) <= '0';
+ gty_qnorthrefclk01_i(9) <= '0';
+ gty_qnorthrefclk11_i(9) <= '0';
+ gty_qsouthrefclk00_i(9) <= '0';
+ gty_qsouthrefclk10_i(9) <= '0';
+ gty_qsouthrefclk01_i(9) <= '0';
+ gty_qsouthrefclk11_i(9) <= '0';
+
+
+ gty_qrefclk0_i(10) <= '0';
+ gty_qrefclk1_i(10) <= '0';
+ gty_qnorthrefclk0_i(10) <= '0';
+ gty_qnorthrefclk1_i(10) <= '0';
+ gty_qsouthrefclk0_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk1_i(10) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(10) <= '0';
+ gty_qrefclk10_i(10) <= '0';
+ gty_qrefclk01_i(10) <= '0';
+ gty_qrefclk11_i(10) <= '0';
+ gty_qnorthrefclk00_i(10) <= '0';
+ gty_qnorthrefclk10_i(10) <= '0';
+ gty_qnorthrefclk01_i(10) <= '0';
+ gty_qnorthrefclk11_i(10) <= '0';
+ gty_qsouthrefclk00_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk10_i(10) <= '0';
+ gty_qsouthrefclk01_i(10) <= '0';
+ gty_qsouthrefclk11_i(10) <= '0';
+
+
+ gty_qrefclk0_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk1_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qnorthrefclk0_i(11) <= '0';
+ gty_qnorthrefclk1_i(11) <= '0';
+ gty_qsouthrefclk0_i(11) <= '0';
+ gty_qsouthrefclk1_i(11) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk10_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qrefclk01_i(11) <= '0';
+ gty_qrefclk11_i(11) <= '0';
+ gty_qnorthrefclk00_i(11) <= '0';
+ gty_qnorthrefclk10_i(11) <= '0';
+ gty_qnorthrefclk01_i(11) <= '0';
+ gty_qnorthrefclk11_i(11) <= '0';
+ gty_qsouthrefclk00_i(11) <= '0';
+ gty_qsouthrefclk10_i(11) <= '0';
+ gty_qsouthrefclk01_i(11) <= '0';
+ gty_qsouthrefclk11_i(11) <= '0';
+
+
+ gty_qrefclk0_i(12) <= '0';
+ gty_qrefclk1_i(12) <= '0';
+ gty_qnorthrefclk0_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk1_i(12) <= '0';
+ gty_qsouthrefclk0_i(12) <= '0';
+ gty_qsouthrefclk1_i(12) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(12) <= '0';
+ gty_qrefclk10_i(12) <= '0';
+ gty_qrefclk01_i(12) <= '0';
+ gty_qrefclk11_i(12) <= '0';
+ gty_qnorthrefclk00_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk10_i(12) <= '0';
+ gty_qnorthrefclk01_i(12) <= '0';
+ gty_qnorthrefclk11_i(12) <= '0';
+ gty_qsouthrefclk00_i(12) <= '0';
+ gty_qsouthrefclk10_i(12) <= '0';
+ gty_qsouthrefclk01_i(12) <= '0';
+ gty_qsouthrefclk11_i(12) <= '0';
+ --
+ -- IBERT core instantiation
+ --
+ u_ibert_gty_core_1 : entity work.ibert_ultrascale_gty_core_r
+ port map (
+ txn_o => gty_txn_o,
+ txp_o => gty_txp_o,
+ rxn_i => gty_rxn_i,
+ rxp_i => gty_rxp_i,
+ clk => gty_sysclk_i,
+ gtrefclk0_i => gty_qrefclk0_i,
+ gtrefclk1_i => gty_qrefclk1_i,
+ gtnorthrefclk0_i => gty_qnorthrefclk0_i,
+ gtnorthrefclk1_i => gty_qnorthrefclk1_i,
+ gtsouthrefclk0_i => gty_qsouthrefclk0_i,
+ gtsouthrefclk1_i => gty_qsouthrefclk1_i,
+ gtrefclk00_i => gty_qrefclk00_i,
+ gtrefclk10_i => gty_qrefclk10_i,
+ gtrefclk01_i => gty_qrefclk01_i,
+ gtrefclk11_i => gty_qrefclk11_i,
+ gtnorthrefclk00_i => gty_qnorthrefclk00_i,
+ gtnorthrefclk10_i => gty_qnorthrefclk10_i,
+ gtnorthrefclk01_i => gty_qnorthrefclk01_i,
+ gtnorthrefclk11_i => gty_qnorthrefclk11_i,
+ gtsouthrefclk00_i => gty_qsouthrefclk00_i,
+ gtsouthrefclk10_i => gty_qsouthrefclk10_i,
+ gtsouthrefclk01_i => gty_qsouthrefclk01_i,
+ gtsouthrefclk11_i => gty_qsouthrefclk11_i
+ );
+
+end proc;
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.xdc b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.xdc
new file mode 100644
index 0000000..e91a4a4
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.xdc
@@ -0,0 +1,70 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2012.3
+## \ \ Application : IBERT Ultrascale
+## / / Filename : example_ibert_ultrascale_gty_0.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+##
+## Icon Constraints
+##
+
+## set_property C_CLK_INPUT_FREQ_HZ 50000000 [get_debug_cores dbg_hub]
+## set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+## set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+## connect_debug_port dbg_hub/clk [get_nets AXI_CLK]
+
+##
+##gtrefclk lock constraints
+##
+## set_property PACKAGE_PIN AY39 [get_ports gty_refclk0p_i[0]]
+## set_property PACKAGE_PIN AY40 [get_ports gty_refclk0n_i[0]]
+## set_property PACKAGE_PIN AW41 [get_ports gty_refclk1p_i[0]]
+## set_property PACKAGE_PIN AW42 [get_ports gty_refclk1n_i[0]]
+## set_property PACKAGE_PIN AT39 [get_ports gty_refclk0p_i[1]]
+## set_property PACKAGE_PIN AT40 [get_ports gty_refclk0n_i[1]]
+## set_property PACKAGE_PIN AR41 [get_ports gty_refclk1p_i[1]]
+## set_property PACKAGE_PIN AR42 [get_ports gty_refclk1n_i[1]]
+## set_property PACKAGE_PIN AM39 [get_ports gty_refclk0p_i[2]]
+## set_property PACKAGE_PIN AM40 [get_ports gty_refclk0n_i[2]]
+## set_property PACKAGE_PIN AL41 [get_ports gty_refclk1p_i[2]]
+## set_property PACKAGE_PIN AL42 [get_ports gty_refclk1n_i[2]]
+## set_property PACKAGE_PIN AA41 [get_ports gty_refclk0p_i[3]]
+## set_property PACKAGE_PIN AA42 [get_ports gty_refclk0n_i[3]]
+## set_property PACKAGE_PIN Y39 [get_ports gty_refclk1p_i[3]]
+## set_property PACKAGE_PIN Y40 [get_ports gty_refclk1n_i[3]]
+## set_property PACKAGE_PIN W41 [get_ports gty_refclk0p_i[4]]
+## set_property PACKAGE_PIN W42 [get_ports gty_refclk0n_i[4]]
+## set_property PACKAGE_PIN V39 [get_ports gty_refclk1p_i[4]]
+## set_property PACKAGE_PIN V40 [get_ports gty_refclk1n_i[4]]
+## set_property PACKAGE_PIN N41 [get_ports gty_refclk0p_i[5]]
+## set_property PACKAGE_PIN N42 [get_ports gty_refclk0n_i[5]]
+## set_property PACKAGE_PIN M39 [get_ports gty_refclk1p_i[5]]
+## set_property PACKAGE_PIN M40 [get_ports gty_refclk1n_i[5]]
+##
+## Refclk constraints
+##
+#create_clock -name gtrefclk0_2 -period 3.104 [get_ports p_lf_r0_ad]
+create_clock -name gtrefclk0_1 -period 3.1030303 [get_ports p_rt_r0_n]
+set_clock_groups -group [get_clocks gtrefclk0_1 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_3 -period 3.1030303 [get_ports p_rt_r0_b]
+set_clock_groups -group [get_clocks gtrefclk0_3 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_5 -period 3.1030303 [get_ports p_rt_r0_e]
+set_clock_groups -group [get_clocks gtrefclk0_5 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_7 -period 3.1030303 [get_ports p_rt_r0_f]
+set_clock_groups -group [get_clocks gtrefclk0_7 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_11 -period 3.1030303 [get_ports p_rt_r0_g]
+set_clock_groups -group [get_clocks gtrefclk0_11 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_12 -period 3.1030303 [get_ports p_rt_r0_i]
+set_clock_groups -group [get_clocks gtrefclk0_12 -include_generated_clocks] -asynchronous
+
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r_clockgroups.xdc b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r_clockgroups.xdc
new file mode 100644
index 0000000..765eddd
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r_clockgroups.xdc
@@ -0,0 +1,175 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2017.1
+## \ \ Application : IBERT Ultrascale
+## / / Filename : ibert_ultrascale_gty_ip_example.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+## TX/RX out clock clock constraints
+##
+# GT X0Y4
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y5
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y6
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y7
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y8
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y9
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y10
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y11
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y12
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y13
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y14
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y15
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y16
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y17
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y18
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y19
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y20
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y21
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y22
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y23
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y24
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y25
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y26
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y27
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y28
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y29
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y30
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y31
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y32
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y33
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y34
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y35
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y36
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y37
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y38
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y39
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y40
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y41
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y42
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y43
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y48
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y49
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y50
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y51
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y52
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y53
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y54
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y55
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y56
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y57
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y58
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y59
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top.vhd b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top.vhd
new file mode 100644
index 0000000..9612cad
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top.vhd
@@ -0,0 +1,838 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_misc.all;
+
+use work.axiRegPkg.all;
+use work.axiRegPkg_d64.all;
+use work.types.all;
+use work.IO_Ctrl.all;
+use work.C2C_INTF_CTRL.all;
+use work.AXISlaveAddrPkg.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity top is
+ port (
+ -- clocks
+ p_clk_200 : in std_logic;
+ n_clk_200 : in std_logic; -- 200 MHz system clock
+
+ -- A copy of the RefClk#0 used by the 12-channel FireFlys on the left side of the FPGA.
+ --This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_lf_x12_r0_clk : in std_logic;
+ -- n_lf_x12_r0_clk : in std_logic;
+
+ -- -- A copy of the RefClk#0 used by the 4-channel FireFlys on the left side of the FPGA.
+ -- -- This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_lf_x4_r0_clk : in std_logic;
+ -- n_lf_x4_r0_clk : in std_logic;
+
+ ---- A copy of the RefClk#0 used by the 12-channel FireFlys on the right side of the FPGA.
+ ---- This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_rt_x12_r0_clk : in std_logic;
+ -- n_rt_x12_r0_clk : in std_logic;
+
+ ---- A copy of the RefClk#0 used by the 4-channel FireFlys on the right side of the FPGA.
+ ---- This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_rt_x4_r0_clk : in std_logic;
+ -- n_rt_x4_r0_clk : in std_logic;
+
+ --'input' "fpga_identity" to differentiate FPGA#1 from FPGA#2.
+ -- The signal will be HI in FPGA#1 and LO in FPGA#2.
+-- fpga_identity : in std_logic;
+
+ -- 'output' "led": 3 bits to light a tri-color LED
+ -- These use different pins on F1 vs. F2. The pins are unused on the "other" FPGA,
+ -- so each color for both FPGAs can be driven at the same time
+ led_f1_red : out std_logic;
+ led_f1_green : out std_logic;
+ led_f1_blue : out std_logic;
+ --led_f2_red : out std_logic;
+ --led_f2_green : out std_logic;
+ --led_f2_blue : out std_logic;
+
+ -- 'input' "mcu_to_f": 1 bit trom the MCU
+ -- 'output' "f_to_mcu": 1 bit to the MCU
+ -- There is no currently defined use for these.
+ --mcu_to_f : in std_logic;
+ --f_to_mcu : out std_logic;
+
+ -- 'output' "c2c_ok": 1 bit to the MCU
+ -- The FPGA should set this output HI when the chip-2-chip link is working.
+ c2c_ok : out std_logic;
+
+ -- If the Zynq on the SM is the TCDS endpoint, then both FPGAs only use port #0 for TCDS
+ -- signals and the two FPGAs are programmed identically.
+ --
+ -- If FPGA#1 is the TCDS endpoint, then:
+ -- 1) TCDS signals from the ATCA backplane connect to port#0 on FPGA#1
+ -- 2) TCDS information is sent from FPGA#1 to FPGA#2 on port #3
+ -- 3) TCDS information is sent from FPGA#1 to the Zynq on the SM on port #2.
+ --
+ -- RefClk#0 for quad AB comes from REFCLK SYNTHESIZER R1A which can be driven by:
+ -- a) synth oscillator
+ -- b) HQ_CLK from the SM
+ -- b1) 320 MHz if FPGA#1 is the TCDS endpoint
+ -- b2) 40 MHz if the SM is the TCDS endpoint
+ -- c) Optional front panel connector for an external LVDS clock
+ -- quad AB
+ -- p_lf_r0_ab : in std_logic;
+ -- n_lf_r0_ab : in std_logic;
+ ----
+ ---- RefClk#1 comes from REFCLK SYNTHESIZER R1B which can be driven by:
+ ---- a) synth oscillator
+ ---- b) an output from EXTERNAL REFCLK SYNTH R1A
+ ---- c) the 40 MHz TCDS RECOVERED CLOCK from FPGA #1
+ ---- RefClk#1 is only connected on FPGA#1, and is only used when FPGA#1 is the TCDS endpoint.
+ ---- quad AB
+ -- p_lf_r1_ab : in std_logic;
+ -- n_lf_r1_ab : in std_logic;
+ ---- quad L
+ -- p_lf_r1_l : in std_logic;
+ -- n_lf_r1_l : in std_logic;
+
+ --
+ -- Port #0 is the main TCDS path. Both FPGAs use it when the Zynq on the SM is the
+ -- TCDS endpoint. Only FPGA#1 uses it when FPGA#1 is the TCDS endpoint.
+ -- Port #0 receive (schematic name is "con*_tcds_in")
+ -- p_tcds_in : in std_logic;
+ -- n_tcds_in : in std_logic;
+
+ ---- Port #0 transmit (schematic name is "con*_tcds_out")
+ -- p_tcds_out : out std_logic;
+ -- n_tcds_out : out std_logic;
+ ----
+ ---- Port #2 is used to send TCDS signals between FPGA#1 and the Zynq when
+ ---- FPGA#1 is the TCDS endpoint. Port #2 is not used when the Zynq on the SM is the
+ ---- TCDS endpoint. Port #2 is not connected to anything on FPGA#2.
+ ---- quad AB
+ -- p_tcds_from_zynq_a : in std_logic;
+ -- n_tcds_from_zynq_a : in std_logic;
+ -- p_tcds_to_zynq_a : out std_logic;
+ -- n_tcds_to_zynq_a : out std_logic;
+
+ ---- quad L
+ -- p_tcds_from_zynq_b : in std_logic;
+ -- n_tcds_from_zynq_b : in std_logic;
+ -- p_tcds_to_zynq_b : out std_logic;
+ -- n_tcds_to_zynq_b : out std_logic;
+
+ ----
+ ---- Port #3 is cross-connected between the two FPGAs. It is only used when FPGA#1
+ ---- is the TCDS endpoint.
+ ---- quad AB
+ -- p_tcds_cross_recv_a : in std_logic;
+ -- n_tcds_cross_recv_a : in std_logic;
+ -- p_tcds_cross_xmit_a : out std_logic;
+ -- n_tcds_cross_xmit_a : out std_logic;
+
+ ---- quad L
+ -- p_tcds_cross_recv_b : in std_logic;
+ -- n_tcds_cross_recv_b : in std_logic;
+ -- p_tcds_cross_xmit_b : out std_logic;
+ -- n_tcds_cross_xmit_b : out std_logic;
+
+ ----
+ ---- Recovered 40 MHz TCDS clock output to feed REFCLK SYNTHESIZER R1B.
+ ---- This is only connected on FPGA#1, and is only used when FPGA#1 is the
+ ---- TCDS endpoint. On FPGA#2, these signals are not connected, but are reserved.
+ -- p_tcds_recov_clk : out std_logic;
+ -- n_tcds_recov_clk : out std_logic;
+
+ ----
+ ---- 40 MHz TCDS clock connected to FPGA logic. This is used in the FPGA for two
+ ---- purposes. The first is to generate high-speed processing clocks by multiplying
+ ---- in an MMCM. The second is to synchronize processing to the 40 MHz LHC bunch crossing.
+ -- p_tcds40_clk : in std_logic;
+ -- n_tcds40_clk : in std_logic;
+
+
+ ---- Spare input signals from the "other" FPGA.
+ ---- These cross-connect to the spare output signals on the other FPGA
+ ---- 'in_spare[2]' is connected to global glock-capable input pins
+ -- p_in_spare : in std_logic_vector(2 downto 0);
+ -- n_in_spare : in std_logic_vector(2 downto 0);
+ ---- Spare output signals to the "other" FPGA.
+ ---- These cross-connect to the spare input signals on the other FPGA
+ -- p_out_spare : out std_logic_vector(2 downto 0);
+ -- n_out_spare : out std_logic_vector(2 downto 0);
+
+ ---- HDMI-style test connector on the front panel
+ ---- 5 differential and 2 single-ended
+ ---- 'test_conn_0' connects to global clock-capable input pins
+ ---- THE DIRECTIONS ARE SET UP FOR TESTING. CHANGE THEM FOR REAL APPLICATIONS.
+ -- p_test_conn_0 : in std_logic;
+ -- n_test_conn_0 : in std_logic;
+ -- p_test_conn_1 : in std_logic;
+ -- n_test_conn_1 : in std_logic;
+ -- p_test_conn_2 : in std_logic;
+ -- n_test_conn_2 : in std_logic;
+ -- p_test_conn_3 : in std_logic;
+ -- n_test_conn_3 : in std_logic;
+ -- p_test_conn_4 : in std_logic;
+ -- n_test_conn_4 : in std_logic;
+ -- test_conn_5 : out std_logic;
+ -- test_conn_6 : out std_logic;
+
+ -- Spare pins to 1mm x 1mm headers on the bottom of the board
+ -- They could be used in an emergency as I/Os, or for debugging
+ -- hdr[1] and hdr[2] are on global clock-capable pins
+ --input hdr1, hdr2,
+ --input hdr3, hdr4, hdr5, hdr6,
+ --output reg hdr7, hdr8, hdr9, hdr10,
+
+ -- C2C primary (#1) and secondary (#2) links to the Zynq on the SM
+ p_rt_r0_l : in std_logic;
+ n_rt_r0_l : in std_logic;
+ p_mgt_sm_to_f : in std_logic_vector(2 downto 1);
+ n_mgt_sm_to_f : in std_logic_vector(2 downto 1);
+ p_mgt_f_to_sm : out std_logic_vector(2 downto 1);
+ n_mgt_f_to_sm : out std_logic_vector(2 downto 1);
+
+ --n_mgt_z2v : in std_logic_vector(1 downto 1);
+ --p_mgt_z2v : in std_logic_vector(1 downto 1);
+ --n_mgt_v2z : out std_logic_vector(1 downto 1);
+ --p_mgt_v2z : out std_logic_vector(1 downto 1);
+
+ -- Connect FF1, 12 lane, quad AC,AD,AE
+ -- p_lt_r0_ad : in std_logic;
+ -- n_lt_r0_ad : in std_logic;
+ -- n_ff1_recv : in std_logic_vector(11 downto 0);
+ -- p_ff1_recv : in std_logic_vector(11 downto 0);
+ -- n_ff1_xmit : out std_logic_vector(11 downto 0);
+ -- p_ff1_xmit : out std_logic_vector(11 downto 0);
+
+ ---- Connect FF4, 4 lane, quad AF
+ -- p_lf_r0_af : in std_logic;
+ -- n_lf_r0_af : in std_logic;
+ -- n_ff4_recv : in std_logic_vector(3 downto 0);
+ -- p_ff4_recv : in std_logic_vector(3 downto 0);
+ -- n_ff4_xmit : out std_logic_vector(3 downto 0);
+ -- p_ff4_xmit : out std_logic_vector(3 downto 0);
+
+ -- -- Connect FF4, 4 lane, quad U
+ -- p_lf_r0_u : in std_logic;
+ -- n_lf_r0_u : in std_logic;
+ -- n_ff6_recv : in std_logic_vector(3 downto 0);
+ -- p_ff6_recv : in std_logic_vector(3 downto 0);
+ -- n_ff6_xmit : out std_logic_vector(3 downto 0);
+ -- p_ff6_xmit : out std_logic_vector(3 downto 0);
+
+ -- I2C pins
+ -- The "sysmon" port can be accessed before the FPGA is configured.
+ -- The "generic" port requires a configured FPGA with an I2C module. The information
+ -- that can be accessed on the generic port is user-defined.
+ --i2c_scl_f_generic : inout std_logic;
+ --i2c_sda_f_generic : inout std_logic;
+ i2c_scl_f_sysmon : inout std_logic;
+ i2c_sda_f_sysmon : inout std_logic
+ );
+ end entity top;
+
+ architecture structure of top is
+ signal clk_200_raw : std_logic;
+ signal clk_200 : std_logic;
+ signal clk_50 : std_logic;
+ signal reset : std_logic;
+ signal locked_clk200 : std_logic;
+
+ signal led_blue_local : slv_8_t;
+ signal led_red_local : slv_8_t;
+ signal led_green_local : slv_8_t;
+
+ constant localAXISlaves : integer := 4;
+ signal local_AXI_ReadMOSI : AXIReadMOSI_array_t(0 to localAXISlaves-1) := (others => DefaultAXIReadMOSI);
+ signal local_AXI_ReadMISO : AXIReadMISO_array_t(0 to localAXISlaves-1) := (others => DefaultAXIReadMISO);
+ signal local_AXI_WriteMOSI : AXIWriteMOSI_array_t(0 to localAXISlaves-1) := (others => DefaultAXIWriteMOSI);
+ signal local_AXI_WriteMISO : AXIWriteMISO_array_t(0 to localAXISlaves-1) := (others => DefaultAXIWriteMISO);
+
+ signal AXI_CLK : std_logic;
+ signal AXI_RST_N : std_logic;
+ signal AXI_RESET : std_logic;
+
+ signal ext_AXI_ReadMOSI : AXIReadMOSI_d64 := DefaultAXIReadMOSI_d64;
+ signal ext_AXI_ReadMISO : AXIReadMISO_d64 := DefaultAXIReadMISO_d64;
+ signal ext_AXI_WriteMOSI : AXIWriteMOSI_d64 := DefaultAXIWriteMOSI_d64;
+ signal ext_AXI_WriteMISO : AXIWriteMISO_d64 := DefaultAXIWriteMISO_d64;
+
+ signal C2C_Mon : C2C_INTF_MON_t;
+ signal C2C_Ctrl : C2C_INTF_Ctrl_t;
+
+ signal clk_F1_C2C_PHY_user : STD_logic_vector(1 downto 1);
+ signal BRAM_write : std_logic;
+ signal BRAM_addr : std_logic_vector(10 downto 0);
+ signal BRAM_WR_data : std_logic_vector(31 downto 0);
+ signal BRAM_RD_data : std_logic_vector(31 downto 0);
+
+ signal bram_rst_a : std_logic;
+ signal bram_clk_a : std_logic;
+ signal bram_en_a : std_logic;
+ signal bram_we_a : std_logic_vector(7 downto 0);
+ signal bram_addr_a : std_logic_vector(8 downto 0);
+ signal bram_wrdata_a : std_logic_vector(63 downto 0);
+ signal bram_rddata_a : std_logic_vector(63 downto 0);
+
+
+ signal AXI_BRAM_EN : std_logic;
+ signal AXI_BRAM_we : std_logic_vector(7 downto 0);
+ signal AXI_BRAM_addr :std_logic_vector(12 downto 0);
+ signal AXI_BRAM_DATA_IN : std_logic_vector(63 downto 0);
+ signal AXI_BRAM_DATA_OUT : std_logic_vector(63 downto 0);
+
+ signal pB_UART_tx : std_logic;
+ signal pB_UART_rx : std_logic;
+
+
+begin
+ -- connect 200 MHz to a clock wizard that outputs 200 MHz, 100 MHz, and 50 MHz
+ Local_Clocking_1: entity work.onboardclk
+ port map (
+ clk_200Mhz => clk_200,
+ clk_50Mhz => clk_50,
+ reset => '0',
+ locked => locked_clk200,
+ clk_in1_p => p_clk_200,
+ clk_in1_n => n_clk_200);
+ AXI_CLK <= clk_50;
+
+-- add differential clock buffers to all the incoming clocks
+--wire lf_x12_r0_clk;
+--IBUFDS lf_x12_r0_clk_buf(.O(lf_x12_r0_clk), .I(p_lf_x12_r0_clk), .IB(n_lf_x12_r0_clk) );
+--wire lf_x4_r0_clk;
+--IBUFDS lf_x4_r0_clk_buf(.O(lf_x4_r0_clk), .I(p_lf_x4_r0_clk), .IB(n_lf_x4_r0_clk) );
+--wire rt_x12_r0_clk;
+--IBUFDS rt_x12_r0_clk_buf(.O(rt_x12_r0_clk), .I(p_rt_x12_r0_clk), .IB(n_rt_x12_r0_clk) );
+--wire rt_x4_r0_clk;
+--IBUFDS rt_x4_r0_clk_buf(.O(rt_x4_r0_clk), .I(p_rt_x4_r0_clk), .IB(n_rt_x4_r0_clk) );
+--wire tcds40_clk; -- 40 MHz LHC clock
+--IBUFDS tcds40_clk_buf(.O(tcds40_clk), .I(p_tcds40_clk), .IB(n_tcds40_clk) );
+
+-- add differential output buffer to TCDS recovered clock
+--wire tcds_recov_clk;
+--OBUFDS(.I(tcds_recov_clk), .O(p_tcds_recov_clk), .OB(n_tcds_recov_clk));
+---- dummy connection to tcds_recov_clk
+--assign tcds_recov_clk = tcds40_clk;
+
+-- add a free running counter to divide the clock
+--reg [27:0] divider;
+--always @(posedge clk_200) begin
+-- divider[27:0] <= divider[27:0] + 1;
+--end
+
+--assign led_f1_red = divider[27];
+--assign led_f1_green = divider[26];
+--assign led_f1_blue = divider[25];
+--assign led_f2_red = divider[27];
+--assign led_f2_green = divider[26];
+--assign led_f2_blue = divider[25];
+
+---- create 3 differential buffers for spare inputs
+--genvar chan;
+--wire [2:0] in_spare;
+--generate
+-- for (chan=0; chan < 3; chan=chan+1)
+-- begin: gen_in_spare_buf
+-- IBUFDS in_spare_buf(.O(in_spare[chan]), .I(p_in_spare[chan]), .IB(n_in_spare[chan]) );
+-- end
+--endgenerate
+
+---- create 3 differential buffers for spare outputs
+--reg [2:0] out_spare;
+--generate
+-- for (chan=0; chan < 3; chan=chan+1)
+-- begin: gen_out_spare_buf
+-- OBUFDS out_spare_buf(.I(out_spare[chan]), .O(p_out_spare[chan]), .OB(n_out_spare[chan]) );
+-- end
+--endgenerate
+
+-- loop the spare in to the spare out
+--always @(posedge clk_200) begin
+-- out_spare[2:0] <= in_spare[2:0];
+--end
+
+---- create differential buffers to loop the test_conn signals
+--wire test_conn_clk;
+--IBUFDS test_conn_clk_buf(.O(test_conn_clk), .I(p_test_conn_0), .IB(n_test_conn_0) );
+--wire test_conn_3, test_conn_4;
+--IBUFDS test_conn_4_buf(.O(test_conn_4), .I(p_test_conn_4), .IB(n_test_conn_4));
+--IBUFDS test_conn_3_buf(.O(test_conn_3), .I(p_test_conn_3), .IB(n_test_conn_3));
+--reg test_conn_out_2, test_conn_out_1;
+--OBUFDS test_conn_out_2_buf(.I(test_conn_out_2), .O(p_test_conn_2), .OB(n_test_conn_2));
+--OBUFDS test_conn_out_1_buf(.I(test_conn_out_1), .O(p_test_conn_1), .OB(n_test_conn_1));
+
+---- loop test_conn 'in' to 'out' using 'clk'
+--always @(posedge test_conn_clk) begin
+-- test_conn_out_2 <= test_conn_4;
+-- test_conn_out_1 <= test_conn_3;
+-- test_conn_5 <= test_conn_6;
+--end
+
+---- create differential buffers to loop the 'hdr' signals
+--wire hdr_clk;
+--IBUFDS hdr_clk_buf(.O(hdr_clk), .I(hdr1), .IB(hdr2) );
+
+---- loop hdr 'in' to 'out' using 'clk'
+--always @(posedge hdr_clk) begin
+-- hdr7 <= hdr3;
+-- hdr8 <= hdr4;
+-- hdr9 <= hdr5;
+-- hdr10 <= hdr6;
+--end
+
+---- create tri-state buffers for generic I2C scl and sda
+--wire i2c_scl_generic_out, i2c_scl_generic_tri, i2c_scl_generic_in;
+--generic_scl: IOBUF
+-- port map (
+-- clk_200 => clk_200,
+-- I => i2c_scl_generic_out,
+-- T => i2c_scl_generic_tri,
+-- O => i2c_scl_generic_in,
+-- IO => i2c_scl_f_generic
+-- );
+--wire i2c_sda_generic_out, i2c_sda_generic_tri, i2c_sda_generic_in;
+--IOBUF generic_sda(.I(i2c_sda_generic_out),.T(i2c_sda_generic_tri), .O(i2c_sda_generic_in), .IO(i2c_sda_f_generic));
+
+--wire i2c_scl_sysmon_out, i2c_scl_sysmon_tri, i2c_scl_sysmon_in;
+--IOBUF sysmon_scl(.I(i2c_scl_sysmon_out),.T(i2c_scl_sysmon_tri), .O(i2c_scl_sysmon_in), .IO(i2c_scl_f_sysmon));
+--wire i2c_sda_sysmon_out, i2c_sda_sysmon_tri, i2c_sda_sysmon_in;
+--IOBUF sysmon_sda(.I(i2c_sda_sysmon_out),.T(i2c_sda_sysmon_tri), .O(i2c_sda_sysmon_in), .IO(i2c_sda_f_sysmon));
+
+---- create dummy logic to use remaining inputs and outputs
+--always @(posedge clk_200) begin
+-- f_to_mcu <= mcu_to_f & fpga_identity;
+--end
+
+-- Connect the c2c block
+--top_block_wrapper top_block_wrapper1 (
+-- .c2c_refclk_n(n_rt_r0_l),
+-- .c2c_refclk_p(p_rt_r0_l),
+-- .c2c_rxn(n_mgt_sm_to_f_1),
+-- .c2c_rxp(p_mgt_sm_to_f_1),
+-- .c2c_txn(n_mgt_f_to_sm_1),
+-- .c2c_txp(p_mgt_f_to_sm_1),
+-- .c2c2_rxn(n_mgt_sm_to_f_2),
+-- .c2c2_rxp(p_mgt_sm_to_f_2),
+-- .c2c2_txn(n_mgt_f_to_sm_2),
+-- .c2c2_txp(p_mgt_f_to_sm_2),
+-- .clk_100(clk_100),
+-- .c2c_ok(c2c_ok),
+-- .scl_i(i2c_scl_generic_in),
+-- .scl_o(i2c_scl_generic_out),
+-- .scl_t(i2c_scl_generic_tri),
+-- .sda_i(i2c_sda_generic_in),
+-- .sda_o(i2c_sda_generic_out),
+-- .sda_t(i2c_sda_generic_tri)
+--);
+
+-- add a ffx4 block to use 1 quad (quad AF = FF4)
+--BD_FFx4 FFx4_AF (
+-- .init_clk(clk_50),
+-- .refclk_n(n_lf_r0_af),
+-- .refclk_p(p_lf_r0_af),
+-- .rx_n({n_ff4_recv[0],n_ff4_recv[1],n_ff4_recv[2],n_ff4_recv[3]}),
+-- .rx_p({p_ff4_recv[0],p_ff4_recv[1],p_ff4_recv[2],p_ff4_recv[3]}),
+-- .tx_n({n_ff4_xmit[0],n_ff4_xmit[1],n_ff4_xmit[2],n_ff4_xmit[3]}),
+-- .tx_p({p_ff4_xmit[0],p_ff4_xmit[1],p_ff4_xmit[2],p_ff4_xmit[3]})
+--);
+
+---- add a ffx4 block to use 1 quad (quad U = FF6)
+--FFx4_U FFx4_U (
+-- .init_clk(clk_200),
+-- .refclk_n(n_lf_r0_u),
+-- .refclk_p(p_lf_r0_u),
+-- .rx_n({n_ff6_recv[0],n_ff6_recv[1],n_ff6_recv[2],n_ff6_recv[3]}),
+-- .rx_p({p_ff6_recv[0],p_ff6_recv[1],p_ff6_recv[2],p_ff6_recv[3]}),
+-- .tx_n({n_ff6_xmit[0],n_ff6_xmit[1],n_ff6_xmit[2],n_ff6_xmit[3]}),
+-- .tx_p({p_ff6_xmit[0],p_ff6_xmit[1],p_ff6_xmit[2],p_ff6_xmit[3]})
+--);
+
+-- add a ffx12 block to use 3 quads (quad AC,AD,AE = FF1)
+--BD_FFx12 FFx12_AD (
+-- .init_clk(clk_50),
+-- .refclk_n(n_lf_r0_ad),
+-- .refclk_p(p_lf_r0_ad),
+-- .rx_n({n_ff1_recv[11],n_ff1_recv[10],n_ff1_recv[9],n_ff1_recv[8],n_ff1_recv[7],n_ff1_recv[6],n_ff1_recv[5],n_ff1_recv[4],n_ff1_recv[3],n_ff1_recv[2],n_ff1_recv[1],n_ff1_recv[0]}),
+-- .rx_p({p_ff1_recv[11],p_ff1_recv[10],p_ff1_recv[9],p_ff1_recv[8],p_ff1_recv[7],p_ff1_recv[6],p_ff1_recv[5],p_ff1_recv[4],p_ff1_recv[3],p_ff1_recv[2],p_ff1_recv[1],p_ff1_recv[0]}),
+-- .tx_n({n_ff1_xmit[11],n_ff1_xmit[10],n_ff1_xmit[9],n_ff1_xmit[8],n_ff1_xmit[7],n_ff1_xmit[6],n_ff1_xmit[5],n_ff1_xmit[4],n_ff1_xmit[3],n_ff1_xmit[2],n_ff1_xmit[1],n_ff1_xmit[0]}),
+-- .tx_p({p_ff1_xmit[11],p_ff1_xmit[10],p_ff1_xmit[9],p_ff1_xmit[8],p_ff1_xmit[7],p_ff1_xmit[6],p_ff1_xmit[5],p_ff1_xmit[4],p_ff1_xmit[3],p_ff1_xmit[2],p_ff1_xmit[1],p_ff1_xmit[0]})
+--);
+
+ c2csslave_wrapper_1: entity work.c2cslave_wrapper
+ port map (
+ AXI_CLK => AXI_CLK,
+ AXI_RST_N(0) => AXI_RST_N,
+ CM1_PB_UART_rxd => pB_UART_tx,
+ CM1_PB_UART_txd => pB_UART_rx,
+ F1_C2C_phy_Rx_rxn => n_mgt_sm_to_f(1 downto 1),
+ F1_C2C_phy_Rx_rxp => p_mgt_sm_to_f(1 downto 1),
+ F1_C2C_phy_Tx_txn => n_mgt_f_to_sm(1 downto 1),
+ F1_C2C_phy_Tx_txp => p_mgt_f_to_sm(1 downto 1),
+ F1_C2CB_phy_Rx_rxn => n_mgt_sm_to_f(2 downto 2),
+ F1_C2CB_phy_Rx_rxp => p_mgt_sm_to_f(2 downto 2),
+ F1_C2CB_phy_Tx_txn => n_mgt_f_to_sm(2 downto 2),
+ F1_C2CB_phy_Tx_txp => p_mgt_f_to_sm(2 downto 2),
+ F1_C2C_phy_refclk_clk_n => n_rt_r0_l,
+ F1_C2C_phy_refclk_clk_p => p_rt_r0_l,
+ clk50Mhz => clk_50,
+
+ F1_IO_araddr => local_AXI_ReadMOSI(0).address,
+ F1_IO_arprot => local_AXI_ReadMOSI(0).protection_type,
+ F1_IO_arready => local_AXI_ReadMISO(0).ready_for_address,
+ F1_IO_arvalid => local_AXI_ReadMOSI(0).address_valid,
+ F1_IO_awaddr => local_AXI_WriteMOSI(0).address,
+ F1_IO_awprot => local_AXI_WriteMOSI(0).protection_type,
+ F1_IO_awready => local_AXI_WriteMISO(0).ready_for_address,
+ F1_IO_awvalid => local_AXI_WriteMOSI(0).address_valid,
+ F1_IO_bready => local_AXI_WriteMOSI(0).ready_for_response,
+ F1_IO_bresp => local_AXI_WriteMISO(0).response,
+ F1_IO_bvalid => local_AXI_WriteMISO(0).response_valid,
+ F1_IO_rdata => local_AXI_ReadMISO(0).data,
+ F1_IO_rready => local_AXI_ReadMOSI(0).ready_for_data,
+ F1_IO_rresp => local_AXI_ReadMISO(0).response,
+ F1_IO_rvalid => local_AXI_ReadMISO(0).data_valid,
+ F1_IO_wdata => local_AXI_WriteMOSI(0).data,
+ F1_IO_wready => local_AXI_WriteMISO(0).ready_for_data,
+ F1_IO_wstrb => local_AXI_WriteMOSI(0).data_write_strobe,
+ F1_IO_wvalid => local_AXI_WriteMOSI(0).data_valid,
+
+
+ F1_C2C_INTF_araddr => local_AXI_ReadMOSI(2).address,
+ F1_C2C_INTF_arprot => local_AXI_ReadMOSI(2).protection_type,
+ F1_C2C_INTF_arready => local_AXI_ReadMISO(2).ready_for_address,
+ F1_C2C_INTF_arvalid => local_AXI_ReadMOSI(2).address_valid,
+ F1_C2C_INTF_awaddr => local_AXI_WriteMOSI(2).address,
+ F1_C2C_INTF_awprot => local_AXI_WriteMOSI(2).protection_type,
+ F1_C2C_INTF_awready => local_AXI_WriteMISO(2).ready_for_address,
+ F1_C2C_INTF_awvalid => local_AXI_WriteMOSI(2).address_valid,
+ F1_C2C_INTF_bready => local_AXI_WriteMOSI(2).ready_for_response,
+ F1_C2C_INTF_bresp => local_AXI_WriteMISO(2).response,
+ F1_C2C_INTF_bvalid => local_AXI_WriteMISO(2).response_valid,
+ F1_C2C_INTF_rdata => local_AXI_ReadMISO(2).data,
+ F1_C2C_INTF_rready => local_AXI_ReadMOSI(2).ready_for_data,
+ F1_C2C_INTF_rresp => local_AXI_ReadMISO(2).response,
+ F1_C2C_INTF_rvalid => local_AXI_ReadMISO(2).data_valid,
+ F1_C2C_INTF_wdata => local_AXI_WriteMOSI(2).data,
+ F1_C2C_INTF_wready => local_AXI_WriteMISO(2).ready_for_data,
+ F1_C2C_INTF_wstrb => local_AXI_WriteMOSI(2).data_write_strobe,
+ F1_C2C_INTF_wvalid => local_AXI_WriteMOSI(2).data_valid,
+
+
+ F1_CM_FW_INFO_araddr => local_AXI_ReadMOSI(1).address,
+ F1_CM_FW_INFO_arprot => local_AXI_ReadMOSI(1).protection_type,
+ F1_CM_FW_INFO_arready => local_AXI_ReadMISO(1).ready_for_address,
+ F1_CM_FW_INFO_arvalid => local_AXI_ReadMOSI(1).address_valid,
+ F1_CM_FW_INFO_awaddr => local_AXI_WriteMOSI(1).address,
+ F1_CM_FW_INFO_awprot => local_AXI_WriteMOSI(1).protection_type,
+ F1_CM_FW_INFO_awready => local_AXI_WriteMISO(1).ready_for_address,
+ F1_CM_FW_INFO_awvalid => local_AXI_WriteMOSI(1).address_valid,
+ F1_CM_FW_INFO_bready => local_AXI_WriteMOSI(1).ready_for_response,
+ F1_CM_FW_INFO_bresp => local_AXI_WriteMISO(1).response,
+ F1_CM_FW_INFO_bvalid => local_AXI_WriteMISO(1).response_valid,
+ F1_CM_FW_INFO_rdata => local_AXI_ReadMISO(1).data,
+ F1_CM_FW_INFO_rready => local_AXI_ReadMOSI(1).ready_for_data,
+ F1_CM_FW_INFO_rresp => local_AXI_ReadMISO(1).response,
+ F1_CM_FW_INFO_rvalid => local_AXI_ReadMISO(1).data_valid,
+ F1_CM_FW_INFO_wdata => local_AXI_WriteMOSI(1).data,
+ F1_CM_FW_INFO_wready => local_AXI_WriteMISO(1).ready_for_data,
+ F1_CM_FW_INFO_wstrb => local_AXI_WriteMOSI(1).data_write_strobe,
+ F1_CM_FW_INFO_wvalid => local_AXI_WriteMOSI(1).data_valid,
+
+
+ F1_IPBUS_araddr => ext_AXI_ReadMOSI.address,
+ F1_IPBUS_arburst => ext_AXI_ReadMOSI.burst_type,
+ F1_IPBUS_arcache => ext_AXI_ReadMOSI.cache_type,
+ F1_IPBUS_arlen => ext_AXI_ReadMOSI.burst_length,
+ F1_IPBUS_arlock(0) => ext_AXI_ReadMOSI.lock_type,
+ F1_IPBUS_arprot => ext_AXI_ReadMOSI.protection_type,
+ F1_IPBUS_arqos => ext_AXI_ReadMOSI.qos,
+ F1_IPBUS_arready(0) => ext_AXI_ReadMISO.ready_for_address,
+ F1_IPBUS_arregion => ext_AXI_ReadMOSI.region,
+ F1_IPBUS_arsize => ext_AXI_ReadMOSI.burst_size,
+ F1_IPBUS_arvalid(0) => ext_AXI_ReadMOSI.address_valid,
+ F1_IPBUS_awaddr => ext_AXI_WriteMOSI.address,
+ F1_IPBUS_awburst => ext_AXI_WriteMOSI.burst_type,
+ F1_IPBUS_awcache => ext_AXI_WriteMOSI.cache_type,
+ F1_IPBUS_awlen => ext_AXI_WriteMOSI.burst_length,
+ F1_IPBUS_awlock(0) => ext_AXI_WriteMOSI.lock_type,
+ F1_IPBUS_awprot => ext_AXI_WriteMOSI.protection_type,
+ F1_IPBUS_awqos => ext_AXI_WriteMOSI.qos,
+ F1_IPBUS_awready(0) => ext_AXI_WriteMISO.ready_for_address,
+ F1_IPBUS_awregion => ext_AXI_WriteMOSI.region,
+ F1_IPBUS_awsize => ext_AXI_WriteMOSI.burst_size,
+ F1_IPBUS_awvalid(0) => ext_AXI_WriteMOSI.address_valid,
+ F1_IPBUS_bready(0) => ext_AXI_WriteMOSI.ready_for_response,
+ F1_IPBUS_bresp => ext_AXI_WriteMISO.response,
+ F1_IPBUS_bvalid(0) => ext_AXI_WriteMISO.response_valid,
+ F1_IPBUS_rdata => ext_AXI_ReadMISO.data,
+ F1_IPBUS_rlast(0) => ext_AXI_ReadMISO.last,
+ F1_IPBUS_rready(0) => ext_AXI_ReadMOSI.ready_for_data,
+ F1_IPBUS_rresp => ext_AXI_ReadMISO.response,
+ F1_IPBUS_rvalid(0) => ext_AXI_ReadMISO.data_valid,
+ F1_IPBUS_wdata => ext_AXI_WriteMOSI.data,
+ F1_IPBUS_wlast(0) => ext_AXI_WriteMOSI.last,
+ F1_IPBUS_wready(0) => ext_AXI_WriteMISO.ready_for_data,
+ F1_IPBUS_wstrb => ext_AXI_WriteMOSI.data_write_strobe,
+ F1_IPBUS_wvalid(0) => ext_AXI_WriteMOSI.data_valid,
+ reset_n => locked_clk200,--reset,
+
+ F1_C2C_PHY_DEBUG_cplllock(0) => C2C_Mon.C2C(1).DEBUG.CPLL_LOCK,
+ F1_C2C_PHY_DEBUG_dmonitorout => C2C_Mon.C2C(1).DEBUG.DMONITOR,
+ F1_C2C_PHY_DEBUG_eyescandataerror(0) => C2C_Mon.C2C(1).DEBUG.EYESCAN_DATA_ERROR,
+
+ F1_C2C_PHY_DEBUG_eyescanreset(0) => C2C_Ctrl.C2C(1).DEBUG.EYESCAN_RESET,
+ F1_C2C_PHY_DEBUG_eyescantrigger(0) => C2C_Ctrl.C2C(1).DEBUG.EYESCAN_TRIGGER,
+ F1_C2C_PHY_DEBUG_pcsrsvdin => C2C_Ctrl.C2C(1).DEBUG.PCS_RSV_DIN,
+ F1_C2C_PHY_DEBUG_qplllock(0) => C2C_Mon.C2C(1).DEBUG.QPLL_LOCK,
+ F1_C2C_PHY_DEBUG_rxbufreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.BUF_RESET,
+ F1_C2C_PHY_DEBUG_rxbufstatus => C2C_Mon.C2C(1).DEBUG.RX.BUF_STATUS,
+ F1_C2C_PHY_DEBUG_rxcdrhold(0) => C2C_Ctrl.C2C(1).DEBUG.RX.CDR_HOLD,
+ F1_C2C_PHY_DEBUG_rxdfelpmreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.DFE_LPM_RESET,
+ F1_C2C_PHY_DEBUG_rxlpmen(0) => C2C_Ctrl.C2C(1).DEBUG.RX.LPM_EN,
+ F1_C2C_PHY_DEBUG_rxpcsreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PCS_RESET,
+ F1_C2C_PHY_DEBUG_rxpmareset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PMA_RESET,
+ F1_C2C_PHY_DEBUG_rxpmaresetdone(0) => C2C_Mon.C2C(1).DEBUG.RX.PMA_RESET_DONE,
+ F1_C2C_PHY_DEBUG_rxprbscntreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PRBS_CNT_RST,
+ F1_C2C_PHY_DEBUG_rxprbserr(0) => C2C_Mon.C2C(1).DEBUG.RX.PRBS_ERR,
+ F1_C2C_PHY_DEBUG_rxprbssel => C2C_Ctrl.C2C(1).DEBUG.RX.PRBS_SEL,
+ F1_C2C_PHY_DEBUG_rxrate => C2C_Ctrl.C2C(1).DEBUG.RX.RATE,
+ F1_C2C_PHY_DEBUG_rxresetdone(0) => C2C_Mon.C2C(1).DEBUG.RX.RESET_DONE,
+ F1_C2C_PHY_DEBUG_txbufstatus => C2C_Mon.C2C(1).DEBUG.TX.BUF_STATUS,
+ F1_C2C_PHY_DEBUG_txdiffctrl => C2C_Ctrl.C2C(1).DEBUG.TX.DIFF_CTRL,
+ F1_C2C_PHY_DEBUG_txinhibit(0) => C2C_Ctrl.C2C(1).DEBUG.TX.INHIBIT,
+ F1_C2C_PHY_DEBUG_txpcsreset(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PCS_RESET,
+ F1_C2C_PHY_DEBUG_txpmareset(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PMA_RESET,
+ F1_C2C_PHY_DEBUG_txpolarity(0) => C2C_Ctrl.C2C(1).DEBUG.TX.POLARITY,
+ F1_C2C_PHY_DEBUG_txpostcursor => C2C_Ctrl.C2C(1).DEBUG.TX.POST_CURSOR,
+ F1_C2C_PHY_DEBUG_txprbsforceerr(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PRBS_FORCE_ERR,
+ F1_C2C_PHY_DEBUG_txprbssel => C2C_Ctrl.C2C(1).DEBUG.TX.PRBS_SEL,
+ F1_C2C_PHY_DEBUG_txprecursor => C2C_Ctrl.C2C(1).DEBUG.TX.PRE_CURSOR,
+ F1_C2C_PHY_DEBUG_txresetdone(0) => C2C_MON.C2C(1).DEBUG.TX.RESET_DONE,
+
+ F1_C2C_PHY_channel_up => C2C_Mon.C2C(1).STATUS.CHANNEL_UP,
+ F1_C2C_PHY_gt_pll_lock => C2C_MON.C2C(1).STATUS.PHY_GT_PLL_LOCK,
+ F1_C2C_PHY_hard_err => C2C_Mon.C2C(1).STATUS.PHY_HARD_ERR,
+ F1_C2C_PHY_lane_up => C2C_Mon.C2C(1).STATUS.PHY_LANE_UP(0 downto 0),
+ F1_C2C_PHY_mmcm_not_locked_out => C2C_Mon.C2C(1).STATUS.PHY_MMCM_LOL,
+ F1_C2C_PHY_soft_err => C2C_Mon.C2C(1).STATUS.PHY_SOFT_ERR,
+
+ F1_C2C_aurora_do_cc => C2C_Mon.C2C(1).STATUS.DO_CC,
+ F1_C2C_aurora_pma_init_in => C2C_Ctrl.C2C(1).STATUS.INITIALIZE,
+ F1_C2C_axi_c2c_config_error_out => C2C_Mon.C2C(1).STATUS.CONFIG_ERROR,
+ F1_C2C_axi_c2c_link_status_out => C2C_MON.C2C(1).STATUS.LINK_GOOD,
+ F1_C2C_axi_c2c_multi_bit_error_out => C2C_MON.C2C(1).STATUS.MB_ERROR,
+ F1_C2C_phy_power_down => '0',
+ F1_C2C_PHY_clk => clk_F1_C2C_PHY_user(1),
+ F1_C2C_PHY_DRP_daddr => C2C_Ctrl.C2C(1).DRP.address,
+ F1_C2C_PHY_DRP_den => C2C_Ctrl.C2C(1).DRP.enable,
+ F1_C2C_PHY_DRP_di => C2C_Ctrl.C2C(1).DRP.wr_data,
+ F1_C2C_PHY_DRP_do => C2C_MON.C2C(1).DRP.rd_data,
+ F1_C2C_PHY_DRP_drdy => C2C_MON.C2C(1).DRP.rd_data_valid,
+ F1_C2C_PHY_DRP_dwe => C2C_Ctrl.C2C(1).DRP.wr_enable,
+
+ F1_C2CB_PHY_DEBUG_cplllock(0) => C2C_Mon.C2C(2).DEBUG.CPLL_LOCK,
+ F1_C2CB_PHY_DEBUG_dmonitorout => C2C_Mon.C2C(2).DEBUG.DMONITOR,
+ F1_C2CB_PHY_DEBUG_eyescandataerror(0) => C2C_Mon.C2C(2).DEBUG.EYESCAN_DATA_ERROR,
+
+ F1_C2CB_PHY_DEBUG_eyescanreset(0) => C2C_Ctrl.C2C(2).DEBUG.EYESCAN_RESET,
+ F1_C2CB_PHY_DEBUG_eyescantrigger(0) => C2C_Ctrl.C2C(2).DEBUG.EYESCAN_TRIGGER,
+ F1_C2CB_PHY_DEBUG_pcsrsvdin => C2C_Ctrl.C2C(2).DEBUG.PCS_RSV_DIN,
+ F1_C2CB_PHY_DEBUG_qplllock(0) => C2C_Mon.C2C(2).DEBUG.QPLL_LOCK,
+ F1_C2CB_PHY_DEBUG_rxbufreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.BUF_RESET,
+ F1_C2CB_PHY_DEBUG_rxbufstatus => C2C_Mon.C2C(2).DEBUG.RX.BUF_STATUS,
+ F1_C2CB_PHY_DEBUG_rxcdrhold(0) => C2C_Ctrl.C2C(2).DEBUG.RX.CDR_HOLD,
+ F1_C2CB_PHY_DEBUG_rxdfelpmreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.DFE_LPM_RESET,
+ F1_C2CB_PHY_DEBUG_rxlpmen(0) => C2C_Ctrl.C2C(2).DEBUG.RX.LPM_EN,
+ F1_C2CB_PHY_DEBUG_rxpcsreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PCS_RESET,
+ F1_C2CB_PHY_DEBUG_rxpmareset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PMA_RESET,
+ F1_C2CB_PHY_DEBUG_rxpmaresetdone(0) => C2C_Mon.C2C(2).DEBUG.RX.PMA_RESET_DONE,
+ F1_C2CB_PHY_DEBUG_rxprbscntreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PRBS_CNT_RST,
+ F1_C2CB_PHY_DEBUG_rxprbserr(0) => C2C_Mon.C2C(2).DEBUG.RX.PRBS_ERR,
+ F1_C2CB_PHY_DEBUG_rxprbssel => C2C_Ctrl.C2C(2).DEBUG.RX.PRBS_SEL,
+ F1_C2CB_PHY_DEBUG_rxrate => C2C_Ctrl.C2C(2).DEBUG.RX.RATE,
+ F1_C2CB_PHY_DEBUG_rxresetdone(0) => C2C_Mon.C2C(2).DEBUG.RX.RESET_DONE,
+ F1_C2CB_PHY_DEBUG_txbufstatus => C2C_Mon.C2C(2).DEBUG.TX.BUF_STATUS,
+ F1_C2CB_PHY_DEBUG_txdiffctrl => C2C_Ctrl.C2C(2).DEBUG.TX.DIFF_CTRL,
+ F1_C2CB_PHY_DEBUG_txinhibit(0) => C2C_Ctrl.C2C(2).DEBUG.TX.INHIBIT,
+ F1_C2CB_PHY_DEBUG_txpcsreset(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PCS_RESET,
+ F1_C2CB_PHY_DEBUG_txpmareset(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PMA_RESET,
+ F1_C2CB_PHY_DEBUG_txpolarity(0) => C2C_Ctrl.C2C(2).DEBUG.TX.POLARITY,
+ F1_C2CB_PHY_DEBUG_txpostcursor => C2C_Ctrl.C2C(2).DEBUG.TX.POST_CURSOR,
+ F1_C2CB_PHY_DEBUG_txprbsforceerr(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PRBS_FORCE_ERR,
+ F1_C2CB_PHY_DEBUG_txprbssel => C2C_Ctrl.C2C(2).DEBUG.TX.PRBS_SEL,
+ F1_C2CB_PHY_DEBUG_txprecursor => C2C_Ctrl.C2C(2).DEBUG.TX.PRE_CURSOR,
+ F1_C2CB_PHY_DEBUG_txresetdone(0) => C2C_MON.C2C(2).DEBUG.TX.RESET_DONE,
+
+ F1_C2CB_PHY_channel_up => C2C_Mon.C2C(2).STATUS.CHANNEL_UP,
+ F1_C2CB_PHY_gt_pll_lock => C2C_MON.C2C(2).STATUS.PHY_GT_PLL_LOCK,
+ F1_C2CB_PHY_hard_err => C2C_Mon.C2C(2).STATUS.PHY_HARD_ERR,
+ F1_C2CB_PHY_lane_up => C2C_Mon.C2C(2).STATUS.PHY_LANE_UP(0 downto 0),
+-- F1_C2CB_PHY_mmcm_not_locked => C2C_Mon.C2C(2).STATUS.PHY_MMCM_LOL,
+ F1_C2CB_PHY_soft_err => C2C_Mon.C2C(2).STATUS.PHY_SOFT_ERR,
+
+ F1_C2CB_aurora_do_cc => C2C_Mon.C2C(2).STATUS.DO_CC,
+ F1_C2CB_aurora_pma_init_in => C2C_Ctrl.C2C(2).STATUS.INITIALIZE,
+ F1_C2CB_axi_c2c_config_error_out => C2C_Mon.C2C(2).STATUS.CONFIG_ERROR,
+ F1_C2CB_axi_c2c_link_status_out => C2C_MON.C2C(2).STATUS.LINK_GOOD,
+ F1_C2CB_axi_c2c_multi_bit_error_out => C2C_MON.C2C(2).STATUS.MB_ERROR,
+ F1_C2CB_phy_power_down => '0',
+-- F1_C2CB_PHY_user_clk_out => clk_F1_C2CB_PHY_user,
+ F1_C2CB_PHY_DRP_daddr => C2C_Ctrl.C2C(2).DRP.address,
+ F1_C2CB_PHY_DRP_den => C2C_Ctrl.C2C(2).DRP.enable,
+ F1_C2CB_PHY_DRP_di => C2C_Ctrl.C2C(2).DRP.wr_data,
+ F1_C2CB_PHY_DRP_do => C2C_MON.C2C(2).DRP.rd_data,
+ F1_C2CB_PHY_DRP_drdy => C2C_MON.C2C(2).DRP.rd_data_valid,
+ F1_C2CB_PHY_DRP_dwe => C2C_Ctrl.C2C(2).DRP.wr_enable,
+
+ F1_SYS_MGMT_sda =>i2c_sda_f_sysmon,
+ F1_SYS_MGMT_scl =>i2c_scl_f_sysmon
+);
+
+ c2c_ok <= C2C_Mon.C2C(1).STATUS.LINK_GOOD;
+
+ RGB_pwm_1: entity work.RGB_pwm
+ generic map (
+ CLKFREQ => 200000000,
+ RGBFREQ => 1000)
+ port map (
+ clk => clk_200,
+ redcount => led_red_local,
+ greencount => led_green_local,
+ bluecount => led_blue_local,
+ LEDred => led_f1_red,
+ LEDgreen => led_f1_green,
+ LEDblue => led_f1_blue);
+
+ rate_counter_1: entity work.rate_counter
+ generic map (
+ CLK_A_1_SECOND => 2000000)
+ port map (
+ clk_A => clk_200,
+ clk_B => clk_F1_C2C_PHY_user(1),
+ reset_A_async => AXI_RESET,
+ event_b => '1',
+ rate => C2C_Mon.C2C(1).USER_FREQ);
+ C2C_Mon.C2C(2).USER_FREQ <= C2C_Mon.C2C(1).USER_FREQ;
+
+
+ F1_IO_interface_1: entity work.IO_map
+ generic map(
+ ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F1_IO)
+ )
+ port map (
+ clk_axi => AXI_CLK,
+ reset_axi_n => AXI_RST_N,
+ slave_readMOSI => local_AXI_readMOSI(0),
+ slave_readMISO => local_AXI_readMISO(0),
+ slave_writeMOSI => local_AXI_writeMOSI(0),
+ slave_writeMISO => local_AXI_writeMISO(0),
+ Mon.CLK_200_LOCKED => locked_clk200,
+ Mon.BRAM.RD_DATA => BRAM_RD_DATA,
+ Ctrl.RGB.R => led_red_local,
+ Ctrl.RGB.G => led_green_local,
+ Ctrl.RGB.B => led_blue_local,
+ Ctrl.BRAM.WRITE => BRAM_WRITE,
+ Ctrl.BRAM.ADDR(10 downto 0) => BRAM_ADDR,
+ Ctrl.BRAM.ADDR(14 downto 11) => open,
+ Ctrl.BRAM.WR_DATA => BRAM_WR_DATA
+ );
+
+ CM_F1_info_1: entity work.CM_FW_info
+ generic map (
+ ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F1_CM_FW_INFO)
+ )
+ port map (
+ clk_axi => AXI_CLK,
+ reset_axi_n => AXI_RST_N,
+ readMOSI => local_AXI_ReadMOSI(1),
+ readMISO => local_AXI_ReadMISO(1),
+ writeMOSI => local_AXI_WriteMOSI(1),
+ writeMISO => local_AXI_WriteMISO(1));
+
+ C2C_INTF_1: entity work.C2C_INTF
+ generic map (
+ ERROR_WAIT_TIME => 90000000,
+ ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F1_C2C_INTF)
+ )
+ port map (
+ clk_axi => AXI_CLK,
+ reset_axi_n => AXI_RST_N,
+ readMOSI => local_AXI_readMOSI(2),
+ readMISO => local_AXI_readMISO(2),
+ writeMOSI => local_AXI_writeMOSI(2),
+ writeMISO => local_AXI_writeMISO(2),
+ clk_C2C(1) => clk_F1_C2C_PHY_user(1),
+ clk_C2C(2) => clk_F1_C2C_PHY_user(1),
+ UART_Rx => pb_UART_Rx,
+ UART_Tx => pb_UART_Tx,
+ Mon => C2C_Mon,
+ Ctrl => C2C_Ctrl);
+
+
+ AXI_RESET <= not AXI_RST_N;
+
+ AXI_BRAM_1: entity work.AXI_BRAM
+ port map (
+ s_axi_aclk => AXI_CLK,
+ s_axi_aresetn => AXI_RST_N,
+ s_axi_araddr => ext_AXI_ReadMOSI.address(12 downto 0),
+ s_axi_arburst => ext_AXI_ReadMOSI.burst_type,
+ s_axi_arcache => ext_AXI_ReadMOSI.cache_type,
+ s_axi_arlen => ext_AXI_ReadMOSI.burst_length,
+ s_axi_arlock => ext_AXI_ReadMOSI.lock_type,
+ s_axi_arprot => ext_AXI_ReadMOSI.protection_type,
+-- s_axi_arqos => ext_AXI_ReadMOSI.qos,
+ s_axi_arready => ext_AXI_ReadMISO.ready_for_address,
+-- s_axi_arregion => ext_AXI_ReadMOSI.region,
+ s_axi_arsize => ext_AXI_ReadMOSI.burst_size,
+ s_axi_arvalid => ext_AXI_ReadMOSI.address_valid,
+ s_axi_awaddr => ext_AXI_WriteMOSI.address(12 downto 0),
+ s_axi_awburst => ext_AXI_WriteMOSI.burst_type,
+ s_axi_awcache => ext_AXI_WriteMOSI.cache_type,
+ s_axi_awlen => ext_AXI_WriteMOSI.burst_length,
+ s_axi_awlock => ext_AXI_WriteMOSI.lock_type,
+ s_axi_awprot => ext_AXI_WriteMOSI.protection_type,
+-- s_axi_awqos => ext_AXI_WriteMOSI.qos,
+ s_axi_awready => ext_AXI_WriteMISO.ready_for_address,
+-- s_axi_awregion => ext_AXI_WriteMOSI.region,
+ s_axi_awsize => ext_AXI_WriteMOSI.burst_size,
+ s_axi_awvalid => ext_AXI_WriteMOSI.address_valid,
+ s_axi_bready => ext_AXI_WriteMOSI.ready_for_response,
+ s_axi_bresp => ext_AXI_WriteMISO.response,
+ s_axi_bvalid => ext_AXI_WriteMISO.response_valid,
+ s_axi_rdata => ext_AXI_ReadMISO.data,
+ s_axi_rlast => ext_AXI_ReadMISO.last,
+ s_axi_rready => ext_AXI_ReadMOSI.ready_for_data,
+ s_axi_rresp => ext_AXI_ReadMISO.response,
+ s_axi_rvalid => ext_AXI_ReadMISO.data_valid,
+ s_axi_wdata => ext_AXI_WriteMOSI.data,
+ s_axi_wlast => ext_AXI_WriteMOSI.last,
+ s_axi_wready => ext_AXI_WriteMISO.ready_for_data,
+ s_axi_wstrb => ext_AXI_WriteMOSI.data_write_strobe,
+ s_axi_wvalid => ext_AXI_WriteMOSI.data_valid,
+ bram_rst_a => open,
+ bram_clk_a => AXI_CLK,
+ bram_en_a => AXI_BRAM_en,
+ bram_we_a => AXI_BRAM_we,
+ bram_addr_a => AXI_BRAM_addr,
+ bram_wrdata_a => AXI_BRAM_DATA_IN,
+ bram_rddata_a => AXI_BRAM_DATA_OUT);
+
+ DP_BRAM_1: entity work.DP_BRAM
+ port map (
+ clka => AXI_CLK,
+ ena => AXI_BRAM_EN,
+ wea => AXI_BRAM_we,
+ addra => AXI_BRAM_addr(11 downto 2),
+ dina => AXI_BRAM_DATA_IN,
+ douta => AXI_BRAM_DATA_OUT,
+ clkb => AXI_CLK,
+ enb => '1',
+ web => (others => BRAM_WRITE),
+ addrb => BRAM_ADDR,
+ dinb => BRAM_WR_DATA,
+ doutb => BRAM_RD_DATA);
+
+end architecture structure;
+
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top_pins.xdc b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top_pins.xdc
new file mode 100644
index 0000000..fbe9f58
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top_pins.xdc
@@ -0,0 +1,1167 @@
+# pin constraint file for the Apollo 6089-119 board.
+# VU13P (or VU9P) in A2577 package
+#
+# This board has two A2577 FPGA sites. One is the "primary" site, and the other is the
+# "secondary" site. This pin constraint file is usable for both sites. There are some wiring
+# differences on the circuit board. Any differences will be noted.
+#
+# The schematic prefixes of 'f1_' or 'f2_ are dropped from names. They appear on the
+# the schematics to differentiate signals, like 'f1_led_red' vs. 'f2_led_red'. In
+# the Vivado code, they are just 'led_red' for either of the two FPGA sites.
+#
+# The schematic prefixes of 'bc' and 'ac' are dropped from names. They appear
+# on the schematics to differentiate on which side of a coupling capacitor the
+# signal appears.
+#
+# Differential pair names start with 'p_' or 'n_'.
+#
+# Except for clock inputs, signals that can be bused together use bracketed,
+# numbered suffixes.
+
+#-------------------------------------------------
+# Important! Do not remove this constraint!
+# This property ensures that all unused pins are set to high impedance.
+# If the constraint is removed, all unused pins have to be set to HiZ in the top level file.
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
+#-------------------------------------------------
+
+#-------------------------------------------------
+# Important! Do not remove this constraint!
+# Refer to UG580 "SYSMON User Guide" for "Over Temperature Automatic Shutdown"
+# shutdown on over-temperature
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]
+#-------------------------------------------------
+
+#-------------------------------------------------
+# Set internal reference voltages to 0.90 on banks with I/O signals.
+# This is required for the HSTL and DIFF_HSTL I/O standards (if used)
+# ADD VU9P BANKS IF THAT IS THE FPGA BEING USED
+#VU13P SLR#0
+#set_property INTERNAL_VREF 0.90 [get_iobanks 61]
+set_property INTERNAL_VREF 0.90 [get_iobanks 62]
+#set_property INTERNAL_VREF 0.90 [get_iobanks 63]
+#VU13P SLR#1
+set_property INTERNAL_VREF 0.90 [get_iobanks 65]
+set_property INTERNAL_VREF 0.90 [get_iobanks 66]
+#VU13P SLR#2
+set_property INTERNAL_VREF 0.90 [get_iobanks 70]
+set_property INTERNAL_VREF 0.90 [get_iobanks 71]
+#VU13P SLR#3
+set_property INTERNAL_VREF 0.90 [get_iobanks 73]
+set_property INTERNAL_VREF 0.90 [get_iobanks 74]
+set_property INTERNAL_VREF 0.90 [get_iobanks 75]
+
+#-------------------------------------------------
+
+#-------------------------------------------------
+# 200 MHz system clock on bank 66
+# This is SLR#1 on both VU13P and VU9P
+
+# 'input' clk_200: 200 MHz clock (schematic name is "ac_f*_xtal_200")
+set_property IOSTANDARD LVDS [get_ports *_clk_200]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *_clk_200]
+set_property PACKAGE_PIN AT17 [get_ports p_clk_200 ]
+set_property PACKAGE_PIN AU16 [get_ports n_clk_200 ]
+#-------------------------------------------------
+
+#-------------------------------------------------
+# other clock inputs
+
+# A copy of the RefClk#0 used by the 12-channel FireFlys on the left side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *lf_x12_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *lf_x12_r0_clk]
+set_property PACKAGE_PIN P33 [get_ports p_lf_x12_r0_clk]
+set_property PACKAGE_PIN P34 [get_ports n_lf_x12_r0_clk]
+
+# A copy of the RefClk#0 used by the 4-channel FireFlys on the left side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *lf_x4_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *lf_x4_r0_clk]
+set_property PACKAGE_PIN N32 [get_ports p_lf_x4_r0_clk]
+set_property PACKAGE_PIN M32 [get_ports n_lf_x4_r0_clk]
+
+# A copy of the RefClk#0 used by the 12-channel FireFlys on the right side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *rt_x12_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *rt_x12_r0_clk]
+set_property PACKAGE_PIN R18 [get_ports p_rt_x12_r0_clk]
+set_property PACKAGE_PIN R17 [get_ports n_rt_x12_r0_clk]
+
+# A copy of the RefClk#0 used by the 4-channel FireFlys on the right side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *rt_x4_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *rt_x4_r0_clk]
+set_property PACKAGE_PIN N19 [get_ports p_rt_x4_r0_clk]
+set_property PACKAGE_PIN N18 [get_ports n_rt_x4_r0_clk]
+#-------------------------------------------------
+
+#-----------------------------------------------
+# 'input' "fpga_identity" to differentiate FPGA#1 from FPGA#2.
+# The signal will be HI in FPGA#1 and LO in FPGA#2.
+set_property IOSTANDARD LVCMOS18 [get_ports fpga_identity]
+set_property PACKAGE_PIN B29 [get_ports fpga_identity]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# 'output' "led": 3 bits to light a tri-color LED
+# These use different pins on F1 vs. F2. The pins are unused on the "other" FPGA,
+# so each color for both FPGAs can be driven at the same time
+set_property IOSTANDARD LVCMOS18 [get_ports led_*]
+set_property PACKAGE_PIN A30 [get_ports led_f1_blue]
+set_property PACKAGE_PIN A29 [get_ports led_f1_green]
+set_property PACKAGE_PIN A28 [get_ports led_f1_red]
+
+set_property PACKAGE_PIN BL27 [get_ports led_f2_blue]
+set_property PACKAGE_PIN BL28 [get_ports led_f2_green]
+set_property PACKAGE_PIN BL30 [get_ports led_f2_red]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# 'input' "mcu_to_f": 1 bit trom the MCU
+# 'output' "f_to_mcu": 1 bit to the MCU
+# There is no currently defined use for these.
+set_property IOSTANDARD LVCMOS18 [get_ports mcu_to_f]
+set_property IOSTANDARD LVCMOS18 [get_ports f_to_mcu]
+set_property PACKAGE_PIN L33 [get_ports mcu_to_f]
+set_property PACKAGE_PIN M36 [get_ports f_to_mcu]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# 'output' "c2c_ok": 1 bit to the MCU
+# The FPGA should set this output HI when the chip-2-chip link is working.
+set_property IOSTANDARD LVCMOS18 [get_ports c2c_ok]
+set_property PACKAGE_PIN L35 [get_ports c2c_ok]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# I2C pins
+# The "sysmon" port can be accessed before the FPGA is configured.
+# The "generic" port requires a configured FPGA with an I2C module. The information
+# that can be accessed on the generic port is user-defined.
+set_property IOSTANDARD LVCMOS18 [get_ports i2c_s*]
+set_property PACKAGE_PIN BB16 [get_ports i2c_scl_f_sysmon]
+set_property PACKAGE_PIN BC16 [get_ports i2c_sda_f_sysmon]
+set_property PACKAGE_PIN V36 [get_ports i2c_scl_f_generic]
+set_property PACKAGE_PIN J32 [get_ports i2c_sda_f_generic]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# TCDS signals to/from the service blade and to/from the "other" FPGA
+#
+# There is an asymmetry between FPGA#1 (the "primary") and FPGA#2 (the "secondary").
+# The TCDS endpoint can be either the Zynq on the SM, or FPGA#1 on the CM.
+#
+# The primary ones are connected to GTY quad AB (120 on VU13P, 119 on VU9P).
+# If, for some reason, the primary quad can't be modified and FPGA#1 is the TCDS
+# endpoint, then TCDS signals to the Zynq and FPGA#2 can be connected
+# via GTY quad L (220 on VU13P, ??? on VU9P).
+#
+# If the Zynq on the SM is the TCDS endpoint, then both FPGAs only use port #0 for TCDS
+# signals and the two FPGAs are programmed identically.
+#
+# If FPGA#1 is the TCDS endpoint, then:
+# 1) TCDS signals from the ATCA backplane connect to port#0 on FPGA#1
+# 2) TCDS information is sent from FPGA#1 to FPGA#2 on port #3
+# 3) TCDS information is sent from FPGA#1 to the Zynq on the SM on port #2.
+
+# RefClk#0 for quad AB comes from REFCLK SYNTHESIZER R1A which can be driven by:
+# a) synth oscillator
+# b) HQ_CLK from the SM
+# b1) 320 MHz if FPGA#1 is the TCDS endpoint
+# b2) 40 MHz if the SM is the TCDS endpoint
+# c) Optional front panel connector for an external LVDS clock
+# quad AB
+set_property PACKAGE_PIN BD39 [get_ports p_lf_r0_ab]
+set_property PACKAGE_PIN BD40 [get_ports n_lf_r0_ab]
+
+# RefClk#1 comes from REFCLK SYNTHESIZER R1B which can be driven by:
+# a) synth oscillator
+# b) an output from EXTERNAL REFCLK SYNTH R1A
+# c) the 40 MHz TCDS RECOVERED CLOCK from FPGA #1
+# RefClk#1 is only connected on FPGA#1, and is only used when FPGA#1 is the TCDS endpoint.
+# quad AB
+set_property PACKAGE_PIN BC41 [get_ports p_lf_r1_ab]
+set_property PACKAGE_PIN BC42 [get_ports n_lf_r1_ab]
+# quad L
+set_property PACKAGE_PIN BC11 [get_ports p_lf_r1_l]
+set_property PACKAGE_PIN BC10 [get_ports n_lf_r1_l]
+
+# Port #0 is the main TCDS path. Both FPGAs use it when the Zynq on the SM is the
+# TCDS endpoint. Only FPGA#1 uses it when FPGA#1 is the TCDS endpoint.
+# Port #0 receive (schematic name is "con*_tcds_in")
+set_property PACKAGE_PIN BG32 [get_ports p_tcds_in]
+set_property PACKAGE_PIN BG33 [get_ports n_tcds_in]
+# Port #0 transmit (schematic name is "con*_tcds_out")
+set_property PACKAGE_PIN BH39 [get_ports p_tcds_out]
+set_property PACKAGE_PIN BH40 [get_ports n_tcds_out]
+
+# Port #2 is used to send TCDS signals between FPGA#1 and the Zynq when
+# FPGA#1 is the TCDS endpoint. Port #2 is not used when the Zynq on the SM is the
+# TCDS endpoint. Port #2 is not connected to anything on FPGA#2.
+# Port #2 receive (schematic name is "tcds_from_zynq")
+# quad AB
+set_property PACKAGE_PIN BJ32 [get_ports p_tcds_from_zynq_a]
+set_property PACKAGE_PIN BJ33 [get_ports n_tcds_from_zynq_a]
+# quad L
+set_property PACKAGE_PIN BJ20 [get_ports p_tcds_from_zynq_b]
+set_property PACKAGE_PIN BJ19 [get_ports n_tcds_from_zynq_b]
+# quad AB
+# Port #2 transmit (schematic name is "tcds_to_zynq")
+# quad AB
+set_property PACKAGE_PIN BJ37 [get_ports p_tcds_to_zynq_a]
+set_property PACKAGE_PIN BJ38 [get_ports n_tcds_to_zynq_a]
+# quad L
+set_property PACKAGE_PIN BJ15 [get_ports p_tcds_to_zynq_b]
+set_property PACKAGE_PIN BJ14 [get_ports n_tcds_to_zynq_b]
+
+# Port #3 is cross-connected between the two FPGAs. It is only used when FPGA#1
+# is the TCDS endpoint.
+# Port #3 receive
+# quad AB
+set_property PACKAGE_PIN BH34 [get_ports p_tcds_cross_recv_a]
+set_property PACKAGE_PIN BH35 [get_ports n_tcds_cross_recv_a]
+# quad L
+set_property PACKAGE_PIN BH18 [get_ports p_tcds_cross_recv_b]
+set_property PACKAGE_PIN BH17 [get_ports n_tcds_cross_recv_b]
+#Port #3 transmit
+# quad AB
+set_property PACKAGE_PIN BG37 [get_ports p_tcds_cross_xmit_a]
+set_property PACKAGE_PIN BG38 [get_ports n_tcds_cross_xmit_a]
+# quad L
+set_property PACKAGE_PIN BG15 [get_ports p_tcds_cross_xmit_b]
+set_property PACKAGE_PIN BG14 [get_ports n_tcds_cross_xmit_b]
+
+# Recovered 40 MHz TCDS clock output to feed REFCLK SYNTHESIZER R1B.
+# This is only connected on FPGA#1, and is only used when FPGA#1 is the
+# TCDS endpoint. On FPGA#2, these signals are not connected, but are reserved.
+set_property IOSTANDARD LVDS [get_ports *_tcds_recov_clk]
+set_property PACKAGE_PIN BJ26 [get_ports p_tcds_recov_clk]
+set_property PACKAGE_PIN BK26 [get_ports n_tcds_recov_clk]
+
+# 40 MHz TCDS clock connected to FPGA logic. This is used in the FPGA for two
+# purposes. The first is to generate high-speed processing clocks by multiplying
+# in an MMCM. The second is to synchronize processing to the 40 MHz LHC bunch crossing.
+set_property IOSTANDARD LVDS [get_ports *_tcds40_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *_tcds40_clk]
+set_property PACKAGE_PIN AR17 [get_ports p_tcds40_clk ]
+set_property PACKAGE_PIN AR16 [get_ports n_tcds40_clk ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# AXI C2C signals
+# GTY transceiver reference clocks for AXI C2C link to SM.
+# Quad L (VU13P=220, VU9P=219)
+# RefClk#1 on BC11/BC10 is used for TCDS.
+set_property PACKAGE_PIN BD13 [get_ports p_rt_r0_l]
+set_property PACKAGE_PIN BD12 [get_ports n_rt_r0_l]
+
+# GTY AXI C2C links to the SM
+# 'input' "SM_TO_F": links from the Zynq on the SM
+# 'output' "F_TO_SM": links to the Zynq on the SM
+# Quad L (VU13P=220, VU9P=219)
+# Port #0 receive
+set_property PACKAGE_PIN BG20 [get_ports {p_mgt_sm_to_f[1]} ]
+set_property PACKAGE_PIN BG19 [get_ports {n_mgt_sm_to_f[1]} ]
+# Port #0 transmit
+set_property PACKAGE_PIN BH13 [get_ports {p_mgt_f_to_sm[1]} ]
+set_property PACKAGE_PIN BH12 [get_ports {n_mgt_f_to_sm[1]} ]
+# Port #1 receive
+set_property PACKAGE_PIN BF18 [get_ports {p_mgt_sm_to_f[2]} ]
+set_property PACKAGE_PIN BF17 [get_ports {n_mgt_sm_to_f[2]} ]
+# Port #1 transmit
+set_property PACKAGE_PIN BF13 [get_ports {p_mgt_f_to_sm[2]} ]
+set_property PACKAGE_PIN BF12 [get_ports {n_mgt_f_to_sm[2]} ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 12-lane FireFLy #1
+# Quad AD (VU13P=122, VU9P=121)
+# Use the same clocks for adjacent quads AC and AE (VU13P=121/122/123, VU9P=120/121/122)
+set_property PACKAGE_PIN AY39 [get_ports p_lf_r0_ad]
+set_property PACKAGE_PIN AY40 [get_ports n_lf_r0_ad]
+set_property PACKAGE_PIN AW41 [get_ports p_lf_r1_ad]
+set_property PACKAGE_PIN AW42 [get_ports n_lf_r1_ad]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 12-lane FireFLy #2
+# Quad R (VU13P=126, VU9P=125)
+# Use the same clocks for adjacent quads Q and S (VU13P=125/126/127, VU9P=124/125/126)
+set_property PACKAGE_PIN AM39 [get_ports p_lf_r0_r]
+set_property PACKAGE_PIN AM40 [get_ports n_lf_r0_r]
+set_property PACKAGE_PIN AL41 [get_ports p_lf_r1_r]
+set_property PACKAGE_PIN AL42 [get_ports n_lf_r1_r]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 12-lane FireFLy #3
+# Quad Y (VU13P=133, VU9P=132)
+# Use the same clocks for adjacent quads X and Z (VU13P=132/133/134, VU9P=131/132/133)
+set_property PACKAGE_PIN N41 [get_ports p_lf_r0_y]
+set_property PACKAGE_PIN N42 [get_ports n_lf_r0_y]
+set_property PACKAGE_PIN M39 [get_ports p_lf_r1_y]
+set_property PACKAGE_PIN M40 [get_ports n_lf_r1_y]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 4-lane FireFLy #4
+# Quad AF (VU13P=124, VU9P=123)
+# This clock is not shared with any adjacent quads.
+set_property PACKAGE_PIN AT39 [get_ports p_lf_r0_af]
+set_property PACKAGE_PIN AT40 [get_ports n_lf_r0_af]
+set_property PACKAGE_PIN AR41 [get_ports p_lf_r1_af]
+set_property PACKAGE_PIN AR42 [get_ports n_lf_r1_af]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 4-lane FireFLy #5,6,7
+# Quad U (VU13P=129, VU9P=128)
+# Use the same clocks for adjacent quads T and V (VU13P=128/129/130, VU9P=127/128)
+# FireFly #7 is in a different SLR on the VU9P, so an additional clock is needed
+# for quad V (129) on the VU9P package.
+set_property PACKAGE_PIN AA41 [get_ports p_lf_r0_u]
+set_property PACKAGE_PIN AA42 [get_ports n_lf_r0_u]
+set_property PACKAGE_PIN Y39 [get_ports p_lf_r1_u]
+set_property PACKAGE_PIN Y40 [get_ports n_lf_r1_u]
+# RefClk#1 on quad V is not connected.
+# Quad V (VU13P=130, VU9P=129)
+set_property PACKAGE_PIN W41 [get_ports p_lf_r0_v]
+set_property PACKAGE_PIN W42 [get_ports n_lf_r0_v]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 12-lane FireFly#3
+# Quad N (VU13P=222, VU9P=221)
+# Use the same clocks for adjacent quads M and O (VU13P=221/222/223, VU9P=220/221/222)
+set_property PACKAGE_PIN AY13 [get_ports p_rt_r0_n]
+set_property PACKAGE_PIN AY12 [get_ports n_rt_r0_n]
+set_property PACKAGE_PIN AW11 [get_ports p_rt_r1_n]
+set_property PACKAGE_PIN AW10 [get_ports n_rt_r1_n]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 4-lane FireFly#5,6,7
+# Quad B (VU13P=226, VU9P=225)
+# Use the same clocks for adjacent quads A and C (VU13P=225/226/227, VU9P=224/225/226)
+set_property PACKAGE_PIN AM13 [get_ports p_rt_r0_b ]
+set_property PACKAGE_PIN AM12 [get_ports n_rt_r0_b]
+set_property PACKAGE_PIN AL11 [get_ports p_rt_r1_b]
+set_property PACKAGE_PIN AL10 [get_ports n_rt_r1_b]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 12-lane FireFly#2
+# Quad E (VU13P=229, VU9P=228)
+# Use the same clocks for adjacent quads D and F (VU13P=228/229/230, VU9P=227/228)
+# FireFly #2 is split between different SLRs on the VU9P, so an additional clock is needed
+# for quad F (229) on the VU9P package. However, there are not enough sources for RefClk#1,
+# so if Quad F on the VU9P package needs a RefClk#1, it will have to use the clock
+# from the adjacent quad G.
+set_property PACKAGE_PIN AA11 [get_ports p_rt_r0_e]
+set_property PACKAGE_PIN AA10 [get_ports n_rt_r0_e]
+set_property PACKAGE_PIN Y13 [get_ports p_rt_r1_e]
+set_property PACKAGE_PIN Y12 [get_ports n_rt_r1_e]
+# Quad F (VU13P=230, VU9P=229)
+set_property PACKAGE_PIN W10 [get_ports n_rt_r0_f]
+set_property PACKAGE_PIN W11 [get_ports p_rt_r0_f]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 4-lane FireFly#4
+# Quad G (VU13P=231, VU9P=230)
+# This quad is not used on FPGA#2.
+# It is used on FPGA#1 to connect to quad P on FPGA#2
+set_property PACKAGE_PIN U11 [get_ports p_rt_r0_g]
+set_property PACKAGE_PIN U10 [get_ports n_rt_r0_g]
+set_property PACKAGE_PIN T13 [get_ports p_rt_r1_g]
+set_property PACKAGE_PIN T12 [get_ports n_rt_r1_g]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# Quad P (VU13P=224, VU9P=223)
+# This quad is not used on FPGA#1.
+# It is used on FPGA#2 to connect to quad G on FPGA#1
+set_property PACKAGE_PIN AT13 [get_ports p_rt_r0_p]
+set_property PACKAGE_PIN AT12 [get_ports n_rt_r0_p]
+set_property PACKAGE_PIN AR11 [get_ports p_rt_r1_p]
+set_property PACKAGE_PIN AR10 [get_ports n_rt_r1_p]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 12-lane FireFly#1
+# Quad I (VU13P=233, VU9P=232)
+# Use the same clocks for adjacent quads H and J (VU13P=232/233/234, VU9P=231/232/233)
+set_property PACKAGE_PIN N11 [get_ports p_rt_r0_i]
+set_property PACKAGE_PIN N10 [get_ports n_rt_r0_i]
+set_property PACKAGE_PIN M13 [get_ports p_rt_r1_i]
+set_property PACKAGE_PIN M12 [get_ports n_rt_r1_i]
+#-----------------------------------------------
+
+
+
+#-----------------------------------------------
+# firefly#1 receivers
+# Uses quads AC, AD, AE (VU13P=121/122/123, VU9P=120/121/122)
+# Clocked from quad AD (VU13P=122, VU9P=121)
+set_property PACKAGE_PIN BK34 [get_ports { p_ff1_recv[0] } ]
+set_property PACKAGE_PIN BK35 [get_ports { n_ff1_recv[0] } ]
+set_property PACKAGE_PIN BL32 [get_ports { p_ff1_recv[1] } ]
+set_property PACKAGE_PIN BL33 [get_ports { n_ff1_recv[1] } ]
+set_property PACKAGE_PIN BC50 [get_ports { p_ff1_recv[10] } ]
+set_property PACKAGE_PIN BC51 [get_ports { n_ff1_recv[10] } ]
+set_property PACKAGE_PIN BB48 [get_ports { p_ff1_recv[11] } ]
+set_property PACKAGE_PIN BB49 [get_ports { n_ff1_recv[11] } ]
+set_property PACKAGE_PIN BL46 [get_ports { p_ff1_recv[2] } ]
+set_property PACKAGE_PIN BL47 [get_ports { n_ff1_recv[2] } ]
+set_property PACKAGE_PIN BJ46 [get_ports { p_ff1_recv[3] } ]
+set_property PACKAGE_PIN BJ47 [get_ports { n_ff1_recv[3] } ]
+set_property PACKAGE_PIN BH48 [get_ports { p_ff1_recv[4] } ]
+set_property PACKAGE_PIN BH49 [get_ports { n_ff1_recv[4] } ]
+set_property PACKAGE_PIN BG50 [get_ports { p_ff1_recv[5] } ]
+set_property PACKAGE_PIN BG51 [get_ports { n_ff1_recv[5] } ]
+set_property PACKAGE_PIN BG46 [get_ports { p_ff1_recv[6] } ]
+set_property PACKAGE_PIN BG47 [get_ports { n_ff1_recv[6] } ]
+set_property PACKAGE_PIN BF48 [get_ports { p_ff1_recv[7] } ]
+set_property PACKAGE_PIN BF49 [get_ports { n_ff1_recv[7] } ]
+set_property PACKAGE_PIN BE50 [get_ports { p_ff1_recv[8] } ]
+set_property PACKAGE_PIN BE51 [get_ports { n_ff1_recv[8] } ]
+set_property PACKAGE_PIN BD48 [get_ports { p_ff1_recv[9] } ]
+set_property PACKAGE_PIN BD49 [get_ports { n_ff1_recv[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#1 transmitters
+# Uses quads AC, AD, AE (VU13P=121/122/123, VU9P=120/121/122)
+# Clocked from quad AD (VU13P=122, VU9P=121)
+set_property PACKAGE_PIN BL37 [get_ports { p_ff1_xmit[0] } ]
+set_property PACKAGE_PIN BL38 [get_ports { n_ff1_xmit[0] } ]
+set_property PACKAGE_PIN BK39 [get_ports { p_ff1_xmit[1] } ]
+set_property PACKAGE_PIN BK40 [get_ports { n_ff1_xmit[1] } ]
+set_property PACKAGE_PIN BC45 [get_ports { p_ff1_xmit[10] } ]
+set_property PACKAGE_PIN BC46 [get_ports { n_ff1_xmit[10] } ]
+set_property PACKAGE_PIN BB43 [get_ports { p_ff1_xmit[11] } ]
+set_property PACKAGE_PIN BB44 [get_ports { n_ff1_xmit[11] } ]
+set_property PACKAGE_PIN BL41 [get_ports { p_ff1_xmit[2] } ]
+set_property PACKAGE_PIN BL42 [get_ports { n_ff1_xmit[2] } ]
+set_property PACKAGE_PIN BK43 [get_ports { p_ff1_xmit[3] } ]
+set_property PACKAGE_PIN BK44 [get_ports { n_ff1_xmit[3] } ]
+set_property PACKAGE_PIN BG41 [get_ports { p_ff1_xmit[4] } ]
+set_property PACKAGE_PIN BG42 [get_ports { n_ff1_xmit[4] } ]
+set_property PACKAGE_PIN BJ41 [get_ports { p_ff1_xmit[5] } ]
+set_property PACKAGE_PIN BJ42 [get_ports { n_ff1_xmit[5] } ]
+set_property PACKAGE_PIN BH43 [get_ports { p_ff1_xmit[6] } ]
+set_property PACKAGE_PIN BH44 [get_ports { n_ff1_xmit[6] } ]
+set_property PACKAGE_PIN BF43 [get_ports { p_ff1_xmit[7] } ]
+set_property PACKAGE_PIN BF44 [get_ports { n_ff1_xmit[7] } ]
+set_property PACKAGE_PIN BE45 [get_ports { p_ff1_xmit[8] } ]
+set_property PACKAGE_PIN BE46 [get_ports { n_ff1_xmit[8] } ]
+set_property PACKAGE_PIN BD43 [get_ports { p_ff1_xmit[9] } ]
+set_property PACKAGE_PIN BD44 [get_ports { n_ff1_xmit[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#2 receivers
+# Uses quads Q, R, S (VU13P=125/126/127, VU9P=124/125/126)
+# Clocked from quad R (VU13P=126, VU9P=125)
+set_property PACKAGE_PIN AU50 [get_ports { p_ff2_recv[0] } ]
+set_property PACKAGE_PIN AU51 [get_ports { n_ff2_recv[0] } ]
+set_property PACKAGE_PIN AT48 [get_ports { p_ff2_recv[1] } ]
+set_property PACKAGE_PIN AT49 [get_ports { n_ff2_recv[1] } ]
+set_property PACKAGE_PIN AG50 [get_ports { p_ff2_recv[10] } ]
+set_property PACKAGE_PIN AG51 [get_ports { n_ff2_recv[10] } ]
+set_property PACKAGE_PIN AF48 [get_ports { p_ff2_recv[11] } ]
+set_property PACKAGE_PIN AF49 [get_ports { n_ff2_recv[11] } ]
+set_property PACKAGE_PIN AR50 [get_ports { p_ff2_recv[2] } ]
+set_property PACKAGE_PIN AR51 [get_ports { n_ff2_recv[2] } ]
+set_property PACKAGE_PIN AP48 [get_ports { p_ff2_recv[3] } ]
+set_property PACKAGE_PIN AP49 [get_ports { n_ff2_recv[3] } ]
+set_property PACKAGE_PIN AN50 [get_ports { p_ff2_recv[4] } ]
+set_property PACKAGE_PIN AN51 [get_ports { n_ff2_recv[4] } ]
+set_property PACKAGE_PIN AM48 [get_ports { p_ff2_recv[5] } ]
+set_property PACKAGE_PIN AM49 [get_ports { n_ff2_recv[5] } ]
+set_property PACKAGE_PIN AL50 [get_ports { p_ff2_recv[6] } ]
+set_property PACKAGE_PIN AL51 [get_ports { n_ff2_recv[6] } ]
+set_property PACKAGE_PIN AK48 [get_ports { p_ff2_recv[7] } ]
+set_property PACKAGE_PIN AK49 [get_ports { n_ff2_recv[7] } ]
+set_property PACKAGE_PIN AJ50 [get_ports { p_ff2_recv[8] } ]
+set_property PACKAGE_PIN AJ51 [get_ports { n_ff2_recv[8] } ]
+set_property PACKAGE_PIN AH48 [get_ports { p_ff2_recv[9] } ]
+set_property PACKAGE_PIN AH49 [get_ports { n_ff2_recv[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#2 transmitters
+# Uses quads Q, R, S (VU13P=125/126/127, VU9P=124/125/126)
+# Clocked from quad R (VU13P=126, VU9P=125)
+set_property PACKAGE_PIN AU45 [get_ports { p_ff2_xmit[0] } ]
+set_property PACKAGE_PIN AU46 [get_ports { n_ff2_xmit[0] } ]
+set_property PACKAGE_PIN AT43 [get_ports { p_ff2_xmit[1] } ]
+set_property PACKAGE_PIN AT44 [get_ports { n_ff2_xmit[1] } ]
+set_property PACKAGE_PIN AG45 [get_ports { p_ff2_xmit[10] } ]
+set_property PACKAGE_PIN AG46 [get_ports { n_ff2_xmit[10] } ]
+set_property PACKAGE_PIN AF43 [get_ports { p_ff2_xmit[11] } ]
+set_property PACKAGE_PIN AF44 [get_ports { n_ff2_xmit[11] } ]
+set_property PACKAGE_PIN AR45 [get_ports { p_ff2_xmit[2] } ]
+set_property PACKAGE_PIN AR46 [get_ports { n_ff2_xmit[2] } ]
+set_property PACKAGE_PIN AP43 [get_ports { p_ff2_xmit[3] } ]
+set_property PACKAGE_PIN AP44 [get_ports { n_ff2_xmit[3] } ]
+set_property PACKAGE_PIN AN45 [get_ports { p_ff2_xmit[4] } ]
+set_property PACKAGE_PIN AN46 [get_ports { n_ff2_xmit[4] } ]
+set_property PACKAGE_PIN AM43 [get_ports { p_ff2_xmit[5] } ]
+set_property PACKAGE_PIN AM44 [get_ports { n_ff2_xmit[5] } ]
+set_property PACKAGE_PIN AL45 [get_ports { p_ff2_xmit[6] } ]
+set_property PACKAGE_PIN AL46 [get_ports { n_ff2_xmit[6] } ]
+set_property PACKAGE_PIN AK43 [get_ports { p_ff2_xmit[7] } ]
+set_property PACKAGE_PIN AK44 [get_ports { n_ff2_xmit[7] } ]
+set_property PACKAGE_PIN AJ45 [get_ports { p_ff2_xmit[8] } ]
+set_property PACKAGE_PIN AJ46 [get_ports { n_ff2_xmit[8] } ]
+set_property PACKAGE_PIN AH43 [get_ports { p_ff2_xmit[9] } ]
+set_property PACKAGE_PIN AH44 [get_ports { n_ff2_xmit[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#3 receivers
+# Uses quads X, Y, Z (VU13P=132/133/134, VU9P=131/132/133)
+# Clocked from quad Y (VU13P=133, VU9P=132)
+set_property PACKAGE_PIN J50 [get_ports { p_ff3_recv[0] } ]
+set_property PACKAGE_PIN J51 [get_ports { n_ff3_recv[0] } ]
+set_property PACKAGE_PIN H48 [get_ports { p_ff3_recv[1] } ]
+set_property PACKAGE_PIN H49 [get_ports { n_ff3_recv[1] } ]
+set_property PACKAGE_PIN B34 [get_ports { p_ff3_recv[10] } ]
+set_property PACKAGE_PIN B35 [get_ports { n_ff3_recv[10] } ]
+set_property PACKAGE_PIN C32 [get_ports { p_ff3_recv[11] } ]
+set_property PACKAGE_PIN C33 [get_ports { n_ff3_recv[11] } ]
+set_property PACKAGE_PIN G50 [get_ports { p_ff3_recv[2] } ]
+set_property PACKAGE_PIN G51 [get_ports { n_ff3_recv[2] } ]
+set_property PACKAGE_PIN F48 [get_ports { p_ff3_recv[3] } ]
+set_property PACKAGE_PIN F49 [get_ports { n_ff3_recv[3] } ]
+set_property PACKAGE_PIN E50 [get_ports { p_ff3_recv[4] } ]
+set_property PACKAGE_PIN E51 [get_ports { n_ff3_recv[4] } ]
+set_property PACKAGE_PIN D48 [get_ports { p_ff3_recv[5] } ]
+set_property PACKAGE_PIN D49 [get_ports { n_ff3_recv[5] } ]
+set_property PACKAGE_PIN E46 [get_ports { p_ff3_recv[6] } ]
+set_property PACKAGE_PIN E47 [get_ports { n_ff3_recv[6] } ]
+set_property PACKAGE_PIN C46 [get_ports { p_ff3_recv[7] } ]
+set_property PACKAGE_PIN C47 [get_ports { n_ff3_recv[7] } ]
+set_property PACKAGE_PIN A46 [get_ports { p_ff3_recv[8] } ]
+set_property PACKAGE_PIN A47 [get_ports { n_ff3_recv[8] } ]
+set_property PACKAGE_PIN A32 [get_ports { p_ff3_recv[9] } ]
+set_property PACKAGE_PIN A33 [get_ports { n_ff3_recv[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#3 transmitters
+# Uses quads X, Y, Z (VU13P=132/133/134, VU9P=131/132/133)
+# Clocked from quad Y (VU13P=133, VU9P=132)
+set_property PACKAGE_PIN J45 [get_ports { p_ff3_xmit[0] } ]
+set_property PACKAGE_PIN J46 [get_ports { n_ff3_xmit[0] } ]
+set_property PACKAGE_PIN H43 [get_ports { p_ff3_xmit[1] } ]
+set_property PACKAGE_PIN H44 [get_ports { n_ff3_xmit[1] } ]
+set_property PACKAGE_PIN A37 [get_ports { p_ff3_xmit[10] } ]
+set_property PACKAGE_PIN A38 [get_ports { n_ff3_xmit[10] } ]
+set_property PACKAGE_PIN C37 [get_ports { p_ff3_xmit[11] } ]
+set_property PACKAGE_PIN C38 [get_ports { n_ff3_xmit[11] } ]
+set_property PACKAGE_PIN G45 [get_ports { p_ff3_xmit[2] } ]
+set_property PACKAGE_PIN G46 [get_ports { n_ff3_xmit[2] } ]
+set_property PACKAGE_PIN F43 [get_ports { p_ff3_xmit[3] } ]
+set_property PACKAGE_PIN F44 [get_ports { n_ff3_xmit[3] } ]
+set_property PACKAGE_PIN D43 [get_ports { p_ff3_xmit[4] } ]
+set_property PACKAGE_PIN D44 [get_ports { n_ff3_xmit[4] } ]
+set_property PACKAGE_PIN B43 [get_ports { p_ff3_xmit[5] } ]
+set_property PACKAGE_PIN B44 [get_ports { n_ff3_xmit[5] } ]
+set_property PACKAGE_PIN C41 [get_ports { p_ff3_xmit[6] } ]
+set_property PACKAGE_PIN C42 [get_ports { n_ff3_xmit[6] } ]
+set_property PACKAGE_PIN E41 [get_ports { p_ff3_xmit[7] } ]
+set_property PACKAGE_PIN E42 [get_ports { n_ff3_xmit[7] } ]
+set_property PACKAGE_PIN A41 [get_ports { p_ff3_xmit[8] } ]
+set_property PACKAGE_PIN A42 [get_ports { n_ff3_xmit[8] } ]
+set_property PACKAGE_PIN B39 [get_ports { p_ff3_xmit[9] } ]
+set_property PACKAGE_PIN B40 [get_ports { n_ff3_xmit[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#4 receivers
+# Uses quad AF (VU13P=124, VU9P=123)
+# Clocked from quad AF (VU13P=124, VU9P=123)
+set_property PACKAGE_PIN BA50 [get_ports { p_ff4_recv[0] } ]
+set_property PACKAGE_PIN BA51 [get_ports { n_ff4_recv[0] } ]
+set_property PACKAGE_PIN AY48 [get_ports { p_ff4_recv[1] } ]
+set_property PACKAGE_PIN AY49 [get_ports { n_ff4_recv[1] } ]
+set_property PACKAGE_PIN AW50 [get_ports { p_ff4_recv[2] } ]
+set_property PACKAGE_PIN AW51 [get_ports { n_ff4_recv[2] } ]
+set_property PACKAGE_PIN AV48 [get_ports { p_ff4_recv[3] } ]
+set_property PACKAGE_PIN AV49 [get_ports { n_ff4_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#4 transmitters
+# Uses quad AF (VU13P=124, VU9P=123)
+# Clocked from quad AF (VU13P=124, VU9P=123)
+set_property PACKAGE_PIN BA45 [get_ports { p_ff4_xmit[0] } ]
+set_property PACKAGE_PIN BA46 [get_ports { n_ff4_xmit[0] } ]
+set_property PACKAGE_PIN AY43 [get_ports { p_ff4_xmit[1] } ]
+set_property PACKAGE_PIN AY44 [get_ports { n_ff4_xmit[1] } ]
+set_property PACKAGE_PIN AW45 [get_ports { p_ff4_xmit[2] } ]
+set_property PACKAGE_PIN AW46 [get_ports { n_ff4_xmit[2] } ]
+set_property PACKAGE_PIN AV43 [get_ports { p_ff4_xmit[3] } ]
+set_property PACKAGE_PIN AV44 [get_ports { n_ff4_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#5 receivers
+# Uses quad T (VU13P=128, VU9P=127)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AE50 [get_ports { p_ff5_recv[0] } ]
+set_property PACKAGE_PIN AE51 [get_ports { n_ff5_recv[0] } ]
+set_property PACKAGE_PIN AD48 [get_ports { p_ff5_recv[1] } ]
+set_property PACKAGE_PIN AD49 [get_ports { n_ff5_recv[1] } ]
+set_property PACKAGE_PIN AC50 [get_ports { p_ff5_recv[2] } ]
+set_property PACKAGE_PIN AC51 [get_ports { n_ff5_recv[2] } ]
+set_property PACKAGE_PIN AB48 [get_ports { p_ff5_recv[3] } ]
+set_property PACKAGE_PIN AB49 [get_ports { n_ff5_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#5 transmitters
+# Uses quad T (VU13P=128, VU9P=127)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AE45 [get_ports { p_ff5_xmit[0] } ]
+set_property PACKAGE_PIN AE46 [get_ports { n_ff5_xmit[0] } ]
+set_property PACKAGE_PIN AD43 [get_ports { p_ff5_xmit[1] } ]
+set_property PACKAGE_PIN AD44 [get_ports { n_ff5_xmit[1] } ]
+set_property PACKAGE_PIN AC45 [get_ports { p_ff5_xmit[2] } ]
+set_property PACKAGE_PIN AC46 [get_ports { n_ff5_xmit[2] } ]
+set_property PACKAGE_PIN AB43 [get_ports { p_ff5_xmit[3] } ]
+set_property PACKAGE_PIN AB44 [get_ports { n_ff5_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#6 receivers
+# Uses quad U (VU13P=129, VU9P=128)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AA50 [get_ports { p_ff6_recv[0] } ]
+set_property PACKAGE_PIN AA51 [get_ports { n_ff6_recv[0] } ]
+set_property PACKAGE_PIN Y48 [get_ports { p_ff6_recv[1] } ]
+set_property PACKAGE_PIN Y49 [get_ports { n_ff6_recv[1] } ]
+set_property PACKAGE_PIN W50 [get_ports { p_ff6_recv[2] } ]
+set_property PACKAGE_PIN W51 [get_ports { n_ff6_recv[2] } ]
+set_property PACKAGE_PIN V48 [get_ports { p_ff6_recv[3] } ]
+set_property PACKAGE_PIN V49 [get_ports { n_ff6_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#6 transmitters
+# Uses quad U (VU13P=129, VU9P=128)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AA45 [get_ports { p_ff6_xmit[0] } ]
+set_property PACKAGE_PIN AA46 [get_ports { n_ff6_xmit[0] } ]
+set_property PACKAGE_PIN Y43 [get_ports { p_ff6_xmit[1] } ]
+set_property PACKAGE_PIN Y44 [get_ports { n_ff6_xmit[1] } ]
+set_property PACKAGE_PIN W45 [get_ports { p_ff6_xmit[2] } ]
+set_property PACKAGE_PIN W46 [get_ports { n_ff6_xmit[2] } ]
+set_property PACKAGE_PIN V43 [get_ports { p_ff6_xmit[3] } ]
+set_property PACKAGE_PIN V44 [get_ports { n_ff6_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#7 receivers
+# Uses quad V (VU13P=130, VU9P=129)
+# In the VU9P, this is in a different SLR than FireFly#5,6
+# Clocked from quad U on VU13P (VU13P=129)
+# Clocked from quad V on VU9P (VU9P=129)
+set_property PACKAGE_PIN U50 [get_ports { p_ff7_recv[0] } ]
+set_property PACKAGE_PIN U51 [get_ports { n_ff7_recv[0] } ]
+set_property PACKAGE_PIN T48 [get_ports { p_ff7_recv[1] } ]
+set_property PACKAGE_PIN T49 [get_ports { n_ff7_recv[1] } ]
+set_property PACKAGE_PIN R50 [get_ports { p_ff7_recv[2] } ]
+set_property PACKAGE_PIN R51 [get_ports { n_ff7_recv[2] } ]
+set_property PACKAGE_PIN P48 [get_ports { p_ff7_recv[3] } ]
+set_property PACKAGE_PIN P49 [get_ports { n_ff7_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#7 transmitters
+# Uses quad V (VU13P=130, VU9P=129)
+# In the VU9P, this is in a different SLR than FireFly#5,6
+# Clocked from quad U on VU13P (VU13P=129)
+# Clocked from quad V on VU9P (VU9P=129)
+set_property PACKAGE_PIN U45 [get_ports { p_ff7_xmit[0] } ]
+set_property PACKAGE_PIN U46 [get_ports { n_ff7_xmit[0] } ]
+set_property PACKAGE_PIN T43 [get_ports { p_ff7_xmit[1] } ]
+set_property PACKAGE_PIN T44 [get_ports { n_ff7_xmit[1] } ]
+set_property PACKAGE_PIN R45 [get_ports { p_ff7_xmit[2] } ]
+set_property PACKAGE_PIN R46 [get_ports { n_ff7_xmit[2] } ]
+set_property PACKAGE_PIN P43 [get_ports { p_ff7_xmit[3] } ]
+set_property PACKAGE_PIN P44 [get_ports { n_ff7_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad A connects to FPGA#2 quad F
+# FPGA#1 quad F connects to FPGA#2 quad A
+# Quad A (VU13P=225, VU9P=224)
+# Quad F (VU13P=230, VU9P=229)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad A will also
+# connect to the secondary 4-lane FireFly#7
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad F will also
+# connect to the secondary 12-lane FireFly#2
+# FPGA#1 and FPGA#2 quad A are clocked from quad B (VU13P=226, VU9P=225)
+# FPGA#1 and FPGA#2 quad F is clocked from quad F (VU13P=230, VU9P=229)
+#
+# Quad A receivers
+set_property PACKAGE_PIN AU2 [get_ports { p_a_recv[0] } ]
+set_property PACKAGE_PIN AU1 [get_ports { n_a_recv[0] } ]
+set_property PACKAGE_PIN AT4 [get_ports { p_a_recv[1] } ]
+set_property PACKAGE_PIN AT3 [get_ports { n_a_recv[1] } ]
+set_property PACKAGE_PIN AR2 [get_ports { p_a_recv[2] } ]
+set_property PACKAGE_PIN AR1 [get_ports { n_a_recv[2] } ]
+set_property PACKAGE_PIN AP4 [get_ports { p_a_recv[3] } ]
+set_property PACKAGE_PIN AP3 [get_ports { n_a_recv[3] } ]
+
+# Quad A transmitters
+set_property PACKAGE_PIN AU7 [get_ports { p_a_xmit[0] } ]
+set_property PACKAGE_PIN AU6 [get_ports { n_a_xmit[0] } ]
+set_property PACKAGE_PIN AT9 [get_ports { p_a_xmit[1] } ]
+set_property PACKAGE_PIN AT8 [get_ports { n_a_xmit[1] } ]
+set_property PACKAGE_PIN AR7 [get_ports { p_a_xmit[2] } ]
+set_property PACKAGE_PIN AR6 [get_ports { n_a_xmit[2] } ]
+set_property PACKAGE_PIN AP9 [get_ports { p_a_xmit[3] } ]
+set_property PACKAGE_PIN AP8 [get_ports { n_a_xmit[3] } ]
+
+# Quad F receivers
+set_property PACKAGE_PIN U2 [get_ports { p_f_recv[0] } ]
+set_property PACKAGE_PIN U1 [get_ports { n_f_recv[0] } ]
+set_property PACKAGE_PIN T4 [get_ports { p_f_recv[1] } ]
+set_property PACKAGE_PIN T3 [get_ports { n_f_recv[1] } ]
+set_property PACKAGE_PIN R2 [get_ports { p_f_recv[2] } ]
+set_property PACKAGE_PIN R1 [get_ports { n_f_recv[2] } ]
+set_property PACKAGE_PIN P4 [get_ports { p_f_recv[3] } ]
+set_property PACKAGE_PIN P3 [get_ports { n_f_recv[3] } ]
+
+#Quad F transmitters
+set_property PACKAGE_PIN U7 [get_ports { p_f_xmit[0] } ]
+set_property PACKAGE_PIN U6 [get_ports { n_f_xmit[0] } ]
+set_property PACKAGE_PIN T9 [get_ports { p_f_xmit[1] } ]
+set_property PACKAGE_PIN T8 [get_ports { n_f_xmit[1] } ]
+set_property PACKAGE_PIN R7 [get_ports { p_f_xmit[2] } ]
+set_property PACKAGE_PIN R6 [get_ports { n_f_xmit[2] } ]
+set_property PACKAGE_PIN P9 [get_ports { p_f_xmit[3] } ]
+set_property PACKAGE_PIN P8 [get_ports { n_f_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad B connects to FPGA#2 quad E
+# FPGA#1 quad E connects to FPGA#2 quad B
+# Quad B (VU13P=226, VU9P=225)
+# Quad E (VU13P=229, VU9P=228)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad B will also
+# connect to the secondary 4-lane FireFly#6
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad E will also
+# connect to the secondary 12-lane FireFly#2
+# FPGA#1 and FPGA#2 quad B are clocked from quad B (VU13P=226, VU9P=225)
+# FPGA#1 and FPGA#2 quad E is clocked from quad E (VU13P=229, VU9P=228)
+#
+# Quad B receivers
+set_property PACKAGE_PIN AN2 [get_ports { p_b_recv[0] } ]
+set_property PACKAGE_PIN AN1 [get_ports { n_b_recv[0] } ]
+set_property PACKAGE_PIN AM4 [get_ports { p_b_recv[1] } ]
+set_property PACKAGE_PIN AM3 [get_ports { n_b_recv[1] } ]
+set_property PACKAGE_PIN AL2 [get_ports { p_b_recv[2] } ]
+set_property PACKAGE_PIN AL1 [get_ports { n_b_recv[2] } ]
+set_property PACKAGE_PIN AK4 [get_ports { p_b_recv[3] } ]
+set_property PACKAGE_PIN AK3 [get_ports { n_b_recv[3] } ]
+
+# Quad B transmitters
+set_property PACKAGE_PIN AN7 [get_ports { p_b_xmit[0] } ]
+set_property PACKAGE_PIN AN6 [get_ports { n_b_xmit[0] } ]
+set_property PACKAGE_PIN AM9 [get_ports { p_b_xmit[1] } ]
+set_property PACKAGE_PIN AM8 [get_ports { n_b_xmit[1] } ]
+set_property PACKAGE_PIN AL7 [get_ports { p_b_xmit[2] } ]
+set_property PACKAGE_PIN AL6 [get_ports { n_b_xmit[2] } ]
+set_property PACKAGE_PIN AK9 [get_ports { p_b_xmit[3] } ]
+set_property PACKAGE_PIN AK8 [get_ports { n_b_xmit[3] } ]
+
+# Quad E receivers
+set_property PACKAGE_PIN AA2 [get_ports { p_e_recv[0] } ]
+set_property PACKAGE_PIN AA1 [get_ports { n_e_recv[0] } ]
+set_property PACKAGE_PIN Y4 [get_ports { p_e_recv[1] } ]
+set_property PACKAGE_PIN Y3 [get_ports { n_e_recv[1] } ]
+set_property PACKAGE_PIN W2 [get_ports { p_e_recv[2] } ]
+set_property PACKAGE_PIN W1 [get_ports { n_e_recv[2] } ]
+set_property PACKAGE_PIN V4 [get_ports { p_e_recv[3] } ]
+set_property PACKAGE_PIN V3 [get_ports { n_e_recv[3] } ]
+
+# Quad E transmitters
+set_property PACKAGE_PIN AA7 [get_ports { p_e_xmit[0] } ]
+set_property PACKAGE_PIN AA6 [get_ports { n_e_xmit[0] } ]
+set_property PACKAGE_PIN Y9 [get_ports { p_e_xmit[1] } ]
+set_property PACKAGE_PIN Y8 [get_ports { n_e_xmit[1] } ]
+set_property PACKAGE_PIN W7 [get_ports { p_e_xmit[2] } ]
+set_property PACKAGE_PIN W6 [get_ports { n_e_xmit[2] } ]
+set_property PACKAGE_PIN V9 [get_ports { p_e_xmit[3] } ]
+set_property PACKAGE_PIN V8 [get_ports { n_e_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad C connects to FPGA#2 quad D
+# FPGA#1 quad D connects to FPGA#2 quad C
+# Quad C (VU13P=227, VU9P=226)
+# Quad D (VU13P=228, VU9P=227)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad C will also
+# connect to the secondary 4-lane FireFly#5
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad D will also
+# connect to the secondary 12-lane FireFly#2
+# FPGA#1 and FPGA#2 quad C are clocked from quad B (VU13P=226, VU9P=225)
+# FPGA#1 and FPGA#2 quad D are clocked from quad E (VU13P=229, VU9P=228)
+#
+# Quad C receivers
+set_property PACKAGE_PIN AJ2 [get_ports { p_c_recv[0] } ]
+set_property PACKAGE_PIN AJ1 [get_ports { n_c_recv[0] } ]
+set_property PACKAGE_PIN AH4 [get_ports { p_c_recv[1] } ]
+set_property PACKAGE_PIN AH3 [get_ports { n_c_recv[1] } ]
+set_property PACKAGE_PIN AG2 [get_ports { p_c_recv[2] } ]
+set_property PACKAGE_PIN AG1 [get_ports { n_c_recv[2] } ]
+set_property PACKAGE_PIN AF4 [get_ports { p_c_recv[3] } ]
+set_property PACKAGE_PIN AF3 [get_ports { n_c_recv[3] } ]
+
+# Quad C transmitters
+set_property PACKAGE_PIN AJ7 [get_ports { p_c_xmit[0] } ]
+set_property PACKAGE_PIN AJ6 [get_ports { n_c_xmit[0] } ]
+set_property PACKAGE_PIN AH9 [get_ports { p_c_xmit[1] } ]
+set_property PACKAGE_PIN AH8 [get_ports { n_c_xmit[1] } ]
+set_property PACKAGE_PIN AG7 [get_ports { p_c_xmit[2] } ]
+set_property PACKAGE_PIN AG6 [get_ports { n_c_xmit[2] } ]
+set_property PACKAGE_PIN AF9 [get_ports { p_c_xmit[3] } ]
+set_property PACKAGE_PIN AF8 [get_ports { n_c_xmit[3] } ]
+
+# Quad D receivers
+set_property PACKAGE_PIN AE2 [get_ports { p_d_recv[0] } ]
+set_property PACKAGE_PIN AE1 [get_ports { n_d_recv[0] } ]
+set_property PACKAGE_PIN AD4 [get_ports { p_d_recv[1] } ]
+set_property PACKAGE_PIN AD3 [get_ports { n_d_recv[1] } ]
+set_property PACKAGE_PIN AC2 [get_ports { p_d_recv[2] } ]
+set_property PACKAGE_PIN AC1 [get_ports { n_d_recv[2] } ]
+set_property PACKAGE_PIN AB4 [get_ports { p_d_recv[3] } ]
+set_property PACKAGE_PIN AB3 [get_ports { n_d_recv[3] } ]
+
+# Quad D transmitters
+set_property PACKAGE_PIN AE7 [get_ports { p_d_xmit[0] } ]
+set_property PACKAGE_PIN AE6 [get_ports { n_d_xmit[0] } ]
+set_property PACKAGE_PIN AD9 [get_ports { p_d_xmit[1] } ]
+set_property PACKAGE_PIN AD8 [get_ports { n_d_xmit[1] } ]
+set_property PACKAGE_PIN AC7 [get_ports { p_d_xmit[2] } ]
+set_property PACKAGE_PIN AC6 [get_ports { n_d_xmit[2] } ]
+set_property PACKAGE_PIN AB9 [get_ports { p_d_xmit[3] } ]
+set_property PACKAGE_PIN AB8 [get_ports { n_d_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad G connects to FPGA#2 quad P
+# FPGA#1 quad P and FPGA#2 quad G are not used
+# Quad G (VU13P=231, VU9P=230)
+# Quad P (VU13P=224, VU9P=223)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad G will also
+# connect to the secondary 4-lane FireFly#4
+# FPGA#1 quad G clocked from quad G (VU13P=231, VU9P=230)
+# FPGA#2 quad P is clocked from quad P (VU13P=224, VU9P=223)
+#
+# Quad G receivers
+set_property PACKAGE_PIN N2 [get_ports { p_g_recv[0] } ]
+set_property PACKAGE_PIN N1 [get_ports { n_g_recv[0] } ]
+set_property PACKAGE_PIN M4 [get_ports { p_g_recv[1] } ]
+set_property PACKAGE_PIN M3 [get_ports { n_g_recv[1] } ]
+set_property PACKAGE_PIN L2 [get_ports { p_g_recv[2] } ]
+set_property PACKAGE_PIN L1 [get_ports { n_g_recv[2] } ]
+set_property PACKAGE_PIN K4 [get_ports { p_g_recv[3] } ]
+set_property PACKAGE_PIN K3 [get_ports { n_g_recv[3] } ]
+
+# Quad G transmitters
+set_property PACKAGE_PIN N7 [get_ports { p_g_xmit[0] } ]
+set_property PACKAGE_PIN N6 [get_ports { n_g_xmit[0] } ]
+set_property PACKAGE_PIN M9 [get_ports { p_g_xmit[1] } ]
+set_property PACKAGE_PIN M8 [get_ports { n_g_xmit[1] } ]
+set_property PACKAGE_PIN L7 [get_ports { p_g_xmit[2] } ]
+set_property PACKAGE_PIN L6 [get_ports { n_g_xmit[2] } ]
+set_property PACKAGE_PIN K9 [get_ports { p_g_xmit[3] } ]
+set_property PACKAGE_PIN K8 [get_ports { n_g_xmit[3] } ]
+
+# Quad P receivers
+set_property PACKAGE_PIN BA2 [get_ports { p_p_recv[0] } ]
+set_property PACKAGE_PIN BA1 [get_ports { n_p_recv[0] } ]
+set_property PACKAGE_PIN AY4 [get_ports { p_p_recv[1] } ]
+set_property PACKAGE_PIN AY3 [get_ports { n_p_recv[1] } ]
+set_property PACKAGE_PIN AW2 [get_ports { p_p_recv[2] } ]
+set_property PACKAGE_PIN AW1 [get_ports { n_p_recv[2] } ]
+set_property PACKAGE_PIN AV4 [get_ports { p_p_recv[3] } ]
+set_property PACKAGE_PIN AV3 [get_ports { n_p_recv[3] } ]
+
+# Quad P transmitters
+set_property PACKAGE_PIN BA7 [get_ports { p_p_xmit[0] } ]
+set_property PACKAGE_PIN BA6 [get_ports { n_p_xmit[0] } ]
+set_property PACKAGE_PIN AY9 [get_ports { p_p_xmit[1] } ]
+set_property PACKAGE_PIN AY8 [get_ports { n_p_xmit[1] } ]
+set_property PACKAGE_PIN AW7 [get_ports { p_p_xmit[2] } ]
+set_property PACKAGE_PIN AW6 [get_ports { n_p_xmit[2] } ]
+set_property PACKAGE_PIN AV9 [get_ports { p_p_xmit[3] } ]
+set_property PACKAGE_PIN AV8 [get_ports { n_p_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad H connects to FPGA#2 quad O
+# FPGA#1 quad O connects to FPGA#2 quad H
+# Quad H (VU13P=232, VU9P=231)
+# Quad O (VU13P=223, VU9P=222)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad H will also
+# connect to the secondary 12-lane FireFly#1
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad O will also
+# connect to the secondary 12-lane FireFly#3
+# FPGA#1 and FPGA#2 quad H are clocked from quad I (VU13P=233, VU9P=232)
+# FPGA#1 and FPGA#2 quad O are clocked from quad N (VU13P=222, VU9P=221)
+#
+# Quad H receivers
+set_property PACKAGE_PIN J2 [get_ports { p_h_recv[0] } ]
+set_property PACKAGE_PIN J1 [get_ports { n_h_recv[0] } ]
+set_property PACKAGE_PIN H4 [get_ports { p_h_recv[1] } ]
+set_property PACKAGE_PIN H3 [get_ports { n_h_recv[1] } ]
+set_property PACKAGE_PIN G2 [get_ports { p_h_recv[2] } ]
+set_property PACKAGE_PIN G1 [get_ports { n_h_recv[2] } ]
+set_property PACKAGE_PIN F4 [get_ports { p_h_recv[3] } ]
+set_property PACKAGE_PIN F3 [get_ports { n_h_recv[3] } ]
+
+# Quad H transmitters
+set_property PACKAGE_PIN J7 [get_ports { p_h_xmit[0] } ]
+set_property PACKAGE_PIN J6 [get_ports { n_h_xmit[0] } ]
+set_property PACKAGE_PIN H9 [get_ports { p_h_xmit[1] } ]
+set_property PACKAGE_PIN H8 [get_ports { n_h_xmit[1] } ]
+set_property PACKAGE_PIN G7 [get_ports { p_h_xmit[2] } ]
+set_property PACKAGE_PIN G6 [get_ports { n_h_xmit[2] } ]
+set_property PACKAGE_PIN F9 [get_ports { p_h_xmit[3] } ]
+set_property PACKAGE_PIN F8 [get_ports { n_h_xmit[3] } ]
+
+# Quad O receivers
+set_property PACKAGE_PIN BE2 [get_ports { p_o_recv[0] } ]
+set_property PACKAGE_PIN BE1 [get_ports { n_o_recv[0] } ]
+set_property PACKAGE_PIN BD4 [get_ports { p_o_recv[1] } ]
+set_property PACKAGE_PIN BD3 [get_ports { n_o_recv[1] } ]
+set_property PACKAGE_PIN BC2 [get_ports { p_o_recv[2] } ]
+set_property PACKAGE_PIN BC1 [get_ports { n_o_recv[2] } ]
+set_property PACKAGE_PIN BB4 [get_ports { p_o_recv[3] } ]
+set_property PACKAGE_PIN BB3 [get_ports { n_o_recv[3] } ]
+
+# Quad O transmitters
+set_property PACKAGE_PIN BE7 [get_ports { p_o_xmit[0] } ]
+set_property PACKAGE_PIN BE6 [get_ports { n_o_xmit[0] } ]
+set_property PACKAGE_PIN BD9 [get_ports { p_o_xmit[1] } ]
+set_property PACKAGE_PIN BD8 [get_ports { n_o_xmit[1] } ]
+set_property PACKAGE_PIN BC7 [get_ports { p_o_xmit[2] } ]
+set_property PACKAGE_PIN BC6 [get_ports { n_o_xmit[2] } ]
+set_property PACKAGE_PIN BB9 [get_ports { p_o_xmit[3] } ]
+set_property PACKAGE_PIN BB8 [get_ports { n_o_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad I connects to FPGA#2 quad N
+# FPGA#1 quad N connects to FPGA#2 quad I
+# Quad I (VU13P=233, VU9P=232)
+# Quad N (VU13P=222, VU9P=221)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad I will also
+# connect to the secondary 12-lane FireFly#1
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad N will also
+# connect to the secondary 12-lane FireFly#3
+# FPGA#1 and FPGA#2 quad I are clocked from quad I (VU13P=233, VU9P=232)
+# FPGA#1 and FPGA#2 quad N are clocked from quad N (VU13P=222, VU9P=221)
+#
+# Quad I receivers
+set_property PACKAGE_PIN E2 [get_ports { p_i_recv[0] } ]
+set_property PACKAGE_PIN E1 [get_ports { n_i_recv[0] } ]
+set_property PACKAGE_PIN D4 [get_ports { p_i_recv[1] } ]
+set_property PACKAGE_PIN D3 [get_ports { n_i_recv[1] } ]
+set_property PACKAGE_PIN E6 [get_ports { p_i_recv[2] } ]
+set_property PACKAGE_PIN E5 [get_ports { n_i_recv[2] } ]
+set_property PACKAGE_PIN C6 [get_ports { p_i_recv[3] } ]
+set_property PACKAGE_PIN C5 [get_ports { n_i_recv[3] } ]
+
+# Quad I transmitters
+set_property PACKAGE_PIN D9 [get_ports { p_i_xmit[0] } ]
+set_property PACKAGE_PIN D8 [get_ports { n_i_xmit[0] } ]
+set_property PACKAGE_PIN B9 [get_ports { p_i_xmit[1] } ]
+set_property PACKAGE_PIN B8 [get_ports { n_i_xmit[1] } ]
+set_property PACKAGE_PIN C11 [get_ports { p_i_xmit[2] } ]
+set_property PACKAGE_PIN C10 [get_ports { n_i_xmit[2] } ]
+set_property PACKAGE_PIN E11 [get_ports { p_i_xmit[3] } ]
+set_property PACKAGE_PIN E10 [get_ports { n_i_xmit[3] } ]
+
+# Quad N receivers
+set_property PACKAGE_PIN BH4 [get_ports { p_n_recv[0] } ]
+set_property PACKAGE_PIN BH3 [get_ports { n_n_recv[0] } ]
+set_property PACKAGE_PIN BG2 [get_ports { p_n_recv[1] } ]
+set_property PACKAGE_PIN BG1 [get_ports { n_n_recv[1] } ]
+set_property PACKAGE_PIN BG6 [get_ports { p_n_recv[2] } ]
+set_property PACKAGE_PIN BG5 [get_ports { n_n_recv[2] } ]
+set_property PACKAGE_PIN BF4 [get_ports { p_n_recv[3] } ]
+set_property PACKAGE_PIN BF3 [get_ports { n_n_recv[3] } ]
+
+# Quad N transmitters
+set_property PACKAGE_PIN BG11 [get_ports { p_n_xmit[0] } ]
+set_property PACKAGE_PIN BG10 [get_ports { n_n_xmit[0] } ]
+set_property PACKAGE_PIN BJ11 [get_ports { p_n_xmit[1] } ]
+set_property PACKAGE_PIN BJ10 [get_ports { n_n_xmit[1] } ]
+set_property PACKAGE_PIN BH9 [get_ports { p_n_xmit[2] } ]
+set_property PACKAGE_PIN BH8 [get_ports { n_n_xmit[2] } ]
+set_property PACKAGE_PIN BF9 [get_ports { p_n_xmit[3] } ]
+set_property PACKAGE_PIN BF8 [get_ports { n_n_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad J connects to FPGA#2 quad M
+# FPGA#1 quad M connects to FPGA#2 quad J
+# Quad J (VU13P=234, VU9P=233)
+# Quad M (VU13P=221, VU9P=220)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad J will also
+# connect to the secondary 12-lane FireFly#1
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad M will also
+# connect to the secondary 12-lane FireFly#3
+# FPGA#1 and FPGA#2 quad J are clocked from quad I (VU13P=233, VU9P=232)
+# FPGA#1 and FPGA#2 quad M are clocked from quad N (VU13P=222, VU9P=221)
+#
+# Quad J receivers
+set_property PACKAGE_PIN A6 [get_ports { p_j_recv[0] } ]
+set_property PACKAGE_PIN A5 [get_ports { n_j_recv[0] } ]
+set_property PACKAGE_PIN A20 [get_ports { p_j_recv[1] } ]
+set_property PACKAGE_PIN A19 [get_ports { n_j_recv[1] } ]
+set_property PACKAGE_PIN B18 [get_ports { p_j_recv[2] } ]
+set_property PACKAGE_PIN B17 [get_ports { n_j_recv[2] } ]
+set_property PACKAGE_PIN C20 [get_ports { p_j_recv[3] } ]
+set_property PACKAGE_PIN C19 [get_ports { n_j_recv[3] } ]
+
+# Quad J transmitters
+set_property PACKAGE_PIN A11 [get_ports { p_j_xmit[0] } ]
+set_property PACKAGE_PIN A10 [get_ports { n_j_xmit[0] } ]
+set_property PACKAGE_PIN B13 [get_ports { p_j_xmit[1] } ]
+set_property PACKAGE_PIN B12 [get_ports { n_j_xmit[1] } ]
+set_property PACKAGE_PIN A15 [get_ports { p_j_xmit[2] } ]
+set_property PACKAGE_PIN A14 [get_ports { n_j_xmit[2] } ]
+set_property PACKAGE_PIN C15 [get_ports { p_j_xmit[3] } ]
+set_property PACKAGE_PIN C14 [get_ports { n_j_xmit[3] } ]
+
+# Quad M receivers
+set_property PACKAGE_PIN BK18 [get_ports { p_m_recv[0] } ]
+set_property PACKAGE_PIN BK17 [get_ports { n_m_recv[0] } ]
+set_property PACKAGE_PIN BL20 [get_ports { p_m_recv[1] } ]
+set_property PACKAGE_PIN BL19 [get_ports { n_m_recv[1] } ]
+set_property PACKAGE_PIN BL6 [get_ports { p_m_recv[2] } ]
+set_property PACKAGE_PIN BL5 [get_ports { n_m_recv[2] } ]
+set_property PACKAGE_PIN BJ6 [get_ports { p_m_recv[3] } ]
+set_property PACKAGE_PIN BJ5 [get_ports { n_m_recv[3] } ]
+
+# Quad M transmitters
+set_property PACKAGE_PIN BL15 [get_ports { p_m_xmit[0] } ]
+set_property PACKAGE_PIN BL14 [get_ports { n_m_xmit[0] } ]
+set_property PACKAGE_PIN BK13 [get_ports { p_m_xmit[1] } ]
+set_property PACKAGE_PIN BK12 [get_ports { n_m_xmit[1] } ]
+set_property PACKAGE_PIN BL11 [get_ports { p_m_xmit[2] } ]
+set_property PACKAGE_PIN BL10 [get_ports { n_m_xmit[2] } ]
+set_property PACKAGE_PIN BK9 [get_ports { p_m_xmit[3] } ]
+set_property PACKAGE_PIN BK8 [get_ports { n_m_xmit[3] } ]
+#-----------------------------------------------
+
+
+#-----------------------------------------------
+# Front panel HDMI-sytle test connector
+# 'test_conn_0' connects to global clock-capable input pins
+set_property IOSTANDARD LVDS [get_ports p_test_conn*]
+set_property IOSTANDARD LVDS [get_ports n_test_conn*]
+# Enable the DIFF_TERM_ADV property for any ports used as inputs
+#set_property DIFF_TERM_ADV TERM_100 [get_ports p_test_conn*]
+#set_property DIFF_TERM_ADV TERM_100 [get_ports n_test_conn*]
+set_property PACKAGE_PIN BD28 [get_ports p_test_conn_0 ]
+set_property PACKAGE_PIN BE28 [get_ports n_test_conn_0 ]
+set_property PACKAGE_PIN AW31 [get_ports p_test_conn_1 ]
+set_property PACKAGE_PIN AY31 [get_ports n_test_conn_1 ]
+set_property PACKAGE_PIN AV29 [get_ports p_test_conn_2 ]
+set_property PACKAGE_PIN AW29 [get_ports n_test_conn_2 ]
+set_property PACKAGE_PIN AU31 [get_ports p_test_conn_3 ]
+set_property PACKAGE_PIN AV31 [get_ports n_test_conn_3 ]
+set_property PACKAGE_PIN AY30 [get_ports p_test_conn_4 ]
+set_property PACKAGE_PIN BA30 [get_ports n_test_conn_4 ]
+
+set_property IOSTANDARD LVCMOS18 [get_ports test_conn_5]
+set_property IOSTANDARD LVCMOS18 [get_ports test_conn_6]
+set_property PACKAGE_PIN BA29 [get_ports test_conn_5 ]
+set_property PACKAGE_PIN BA28 [get_ports test_conn_6 ]
+#-----------------------------------------------
+
+
+#-----------------------------------------------
+# Spare input signals from the "other" FPGA.
+# These cross-connect to the spare output signals on the other FPGA
+# 'in_spare[2]' is connected to global glock-capable input pins
+set_property IOSTANDARD LVDS [get_ports *_in_spare*]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *_in_spare*]
+set_property PACKAGE_PIN E30 [get_ports { p_in_spare[0] } ]
+set_property PACKAGE_PIN D30 [get_ports { n_in_spare[0] } ]
+set_property PACKAGE_PIN D28 [get_ports { p_in_spare[1] } ]
+set_property PACKAGE_PIN D29 [get_ports { n_in_spare[1] } ]
+set_property PACKAGE_PIN C29 [get_ports { p_in_spare[2] } ]
+set_property PACKAGE_PIN C30 [get_ports { n_in_spare[2] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# Spare output signals to the "other" FPGA.
+# These cross-connect to the spare input signals on the other FPGA
+set_property IOSTANDARD LVDS [get_ports *_out_spare*]
+set_property PACKAGE_PIN BG29 [get_ports { p_out_spare[0] } ]
+set_property PACKAGE_PIN BH29 [get_ports { n_out_spare[0] } ]
+set_property PACKAGE_PIN BF29 [get_ports { p_out_spare[1] } ]
+set_property PACKAGE_PIN BG30 [get_ports { n_out_spare[1] } ]
+set_property PACKAGE_PIN BG26 [get_ports { p_out_spare[2] } ]
+set_property PACKAGE_PIN BG27 [get_ports { n_out_spare[2] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# Spare pins to 1mm x 1mm headers on the bottom of the board
+# They could be used in an emergency as I/Os, or for debugging
+# hdr1 and hdr2 are on global clock-capable pins
+set_property IOSTANDARD LVDS [get_ports hdr1]
+set_property IOSTANDARD LVDS [get_ports hdr2]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr3]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr4]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr5]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr6]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr7]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr8]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr9]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr10]
+set_property PACKAGE_PIN L28 [get_ports hdr1 ]
+set_property PACKAGE_PIN L29 [get_ports hdr2 ]
+set_property PACKAGE_PIN C26 [get_ports hdr3 ]
+set_property PACKAGE_PIN B26 [get_ports hdr4 ]
+set_property PACKAGE_PIN A25 [get_ports hdr5 ]
+set_property PACKAGE_PIN B25 [get_ports hdr6 ]
+set_property PACKAGE_PIN A24 [get_ports hdr7 ]
+set_property PACKAGE_PIN B24 [get_ports hdr8 ]
+set_property PACKAGE_PIN A23 [get_ports hdr9 ]
+set_property PACKAGE_PIN A22 [get_ports hdr10 ]
+
+#-----------------------------------------------
+
diff --git a/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top_timing.xdc b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top_timing.xdc
new file mode 100644
index 0000000..a3b699b
--- /dev/null
+++ b/configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/top_timing.xdc
@@ -0,0 +1,5 @@
+# 200 MHz oscillator
+create_clock -period 5.000 -waveform {0.000 2.5000} [get_nets clk_200]
+
+# 40 MHz extracted clock
+create_clock -period 25.000 -waveform {0.000 12.5000} [get_nets amc13_clk_40]
\ No newline at end of file
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater
new file mode 120000
index 0000000..2b11982
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater
@@ -0,0 +1 @@
+../Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater/
\ No newline at end of file
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/Generate_svf.tcl b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/Generate_svf.tcl
new file mode 100644
index 0000000..85e3bb7
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/Generate_svf.tcl
@@ -0,0 +1,32 @@
+#this has to be called from inside an open session
+source ${apollo_root_path}/configs/${build_name}/settings.tcl
+
+set SVF_TARGET [format "svf_top%06u" [expr {round(1000000 *rand())}]]
+
+
+
+#derived from walkthrough https://blog.xjtag.com/2016/07/creating-svf-files-using-xilinx-vivado/
+open_hw
+if { [string length [get_hw_targets -quiet -regexp .*/${SVF_TARGET}] ] } {
+ delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]
+}
+create_hw_target ${SVF_TARGET}
+close_hw_target
+open_hw_target [get_hw_targets -regexp .*/${SVF_TARGET}]
+
+
+#add the other FPGA to the chain
+create_hw_device -part xcvu13p-flga2577-1-e
+
+#add the virtex to the chain
+set DEVICE [create_hw_device -part ${FPGA_part}]
+set_property PROGRAM.FILE ${apollo_root_path}/bit/top_${build_name}.bit $DEVICE
+set_param xicom.config_chunk_size 0
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+
+program_hw_devices -force -svf_file ${apollo_root_path}/bit/top_${build_name}.svf ${DEVICE}
+
+write_cfgmem -force -loadbit "up 0 ${apollo_root_path}/bit/top_${build_name}.bit" -format mcs -size 128 -file "${apollo_root_path}/bit/top_${build_name}.mcs"
+
+delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/config.yaml b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/config.yaml
new file mode 100644
index 0000000..6cd62e8
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/config.yaml
@@ -0,0 +1,101 @@
+AXI_CONTROL_SETS:
+ AXI_MASTER_CTRL:
+ axi_interconnect: "${::AXI_INTERCONNECT_NAME}"
+ axi_clk: "${::AXI_MASTER_CLK}"
+ axi_rstn: "${::AXI_MASTER_RSTN}"
+ axi_freq: "${::AXI_MASTER_CLK_FREQ}"
+
+
+AXI_SLAVES:
+ F2_IO:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB3002000"
+ range: "4K"
+ remote_slave: "1"
+ XML: "address_table/modules/CM_IO.xml"
+ UHAL_BASE: 0xc1000000
+ HDL:
+ out_name: "IO"
+ map_template: "axi_generic/template_map_withbram.vhd"
+ F2_SYS_MGMT:
+ TCL_CALL:
+ command: AXI_IP_SYS_MGMT
+ enable_i2c_pins: 1
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB3001000"
+ range: "4K"
+ remote_slave: "1"
+ XML: "address_table/modules/VIRTEX_SYS_MGMT.xml"
+ UHAL_BASE: 0xc0000000
+
+ F2_CM_FW_INFO:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB3003000"
+ range: "4K"
+ remote_slave: "1"
+ XML: "address_table/modules/FW_INFO.xml"
+ UHAL_BASE: 0xc2000000
+ HDL:
+ out_name: "CM_FW_INFO"
+ map_template: "axi_generic/template_map.vhd"
+
+
+ F2_IPBUS:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ type: "AXI4"
+ addr:
+ offset: "0xB2000000"
+ range: "16M"
+ data_width: "64"
+ remote_slave: "1"
+ XML: "address_table/modules/IPBUS.xml"
+ UHAL_BASE: 0xc5000000
+
+ F2_C2C_INTF:
+ TCL_CALL:
+ command: AXI_PL_DEV_CONNECT
+ axi_control: "${::AXI_MASTER_CTRL}"
+ addr:
+ offset: "0xB3010000"
+ range: "64K"
+ remote_slave: "1"
+ XML: "address_table/modules/C2C_INTFS.xml"
+ UHAL_BASE: 0xc6000000
+ HDL:
+ out_name: "C2C_INTF"
+ map_template: "axi_generic/template_map_withbram.vhd"
+ SUB_SLAVES:
+ CM1_PB_UART:
+ TCL_CALL:
+ command: "AXI_IP_UART"
+ addr:
+ offset: "0xB3008000"
+ range: "4K"
+ irq_port: "F2_C2CB/axi_c2c_s2m_intr_in"
+ baud_rate: "115200"
+ axi_control: "${::AXI_MASTER_CTRL}"
+ manual_load_dtsi: "1"
+ remote_slave: "1"
+ dt_data: "compatible = \"xlnx,axi-uartlite-2.0\", \"xlnx,xps-uartlite-1.00.a\";current-speed = <115200>;device_type = \"serial\";interrupt-names = \"interrupt\";interrupt-parent = <&IRQ0_INTR_CTRL>;interrupts = <4 0>;port-number = <101>;xlnx,baudrate = <0x1c200>;xlnx,data-bits = <0x8>;xlnx,odd-parity = <0x0>;xlnx,s-axi-aclk-freq-hz-d = \"49.9995\";xlnx,use-parity = <0x0>;
+ "
+
+CORES:
+ onboardclk:
+ TCL_CALL:
+ command: BuildClockWizard
+ in_clk_type: Differential_clock_capable_pin
+ in_clk_freq_MHZ: 200
+ out_clks:
+ 1: 200
+ 2: 50
+
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/createC2CSlaveInterconnect.tcl b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/createC2CSlaveInterconnect.tcl
new file mode 100644
index 0000000..efe816d
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/createC2CSlaveInterconnect.tcl
@@ -0,0 +1,119 @@
+source ${apollo_root_path}/bd/axi_helpers.tcl
+source ${apollo_root_path}/bd/Xilinx_AXI_slaves.tcl
+source ${apollo_root_path}/bd/Xilinx_Cores.tcl
+
+#create a block design called "c2cSlave"
+#directory and name must be the same
+set bd_design_name "c2cSlave"
+create_bd_design -dir ./ ${bd_design_name}
+
+set EXT_CLK clk50Mhz
+set EXT_RESET reset_n
+set EXT_CLK_FREQ 50000000
+
+set AXI_MASTER_CLK AXI_CLK
+set AXI_MASTER_RSTN AXI_RST_N
+set AXI_MASTER_CLK_FREQ 50000000
+
+set AXI_INTERCONNECT_NAME slave_interconnect
+
+
+
+#================================================================================
+# Setup external clock and reset
+#================================================================================
+create_bd_port -dir I -type clk $EXT_CLK
+set_property CONFIG.FREQ_HZ ${EXT_CLK_FREQ} [get_bd_ports ${EXT_CLK}]
+create_bd_port -dir I -type rst $EXT_RESET
+
+
+
+#================================================================================
+# Create an AXI interconnect
+#================================================================================
+puts "Building AXI C2C slave interconnect"
+
+#create AXI clock & reset ports
+create_bd_port -dir I -type clk $AXI_MASTER_CLK
+set_property CONFIG.FREQ_HZ ${AXI_MASTER_CLK_FREQ} [get_bd_ports ${AXI_MASTER_CLK}]
+create_bd_port -dir O -type rst $AXI_MASTER_RSTN
+
+#create the reset logic
+set SYS_RESETER sys_reseter
+create_bd_cell -type ip -vlnv [get_ipdefs -filter {NAME == proc_sys_reset}] $SYS_RESETER
+#connect external reset
+connect_bd_net [get_bd_ports $EXT_RESET] [get_bd_pins $SYS_RESETER/ext_reset_in]
+#connect clock
+connect_bd_net [get_bd_ports $AXI_MASTER_CLK] [get_bd_pins $SYS_RESETER/slowest_sync_clk]
+
+
+set SYS_RESETER_AXI_RSTN $SYS_RESETER/interconnect_aresetn
+#create the reset to sys reseter and slave interconnect
+connect_bd_net [get_bd_ports $AXI_MASTER_RSTN] [get_bd_pins $SYS_RESETER_AXI_RSTN]
+
+AXI_C2C_MASTER [dict create device_name ${C2C} \
+ axi_control [dict create axi_clk $AXI_MASTER_CLK \
+ axi_rstn $AXI_MASTER_RSTN\
+ axi_freq $AXI_MASTER_CLK_FREQ] \
+ primary_serdes 1 \
+ init_clk $EXT_CLK \
+ refclk_freq 200 \
+ c2c_master false \
+ speed 5 \
+ ]
+if { [info exists C2CB] } {
+ AXI_C2C_MASTER [dict create device_name ${C2CB} \
+ axi_control [dict create axi_clk $AXI_MASTER_CLK \
+ axi_rstn $AXI_MASTER_RSTN\
+ axi_freq $AXI_MASTER_CLK_FREQ] \
+ primary_serdes ${C2C}_PHY \
+ init_clk $EXT_CLK \
+ refclk_freq 200 \
+ c2c_master false \
+ speed 5 \
+ ]
+}
+
+
+#================================================================================
+# Create JTAG AXI Master
+#================================================================================
+set JTAG_AXI_MASTER JTAG_AXI_Master
+BUILD_JTAG_AXI_MASTER [dict create device_name ${JTAG_AXI_MASTER} axi_clk ${AXI_MASTER_CLK} axi_rstn ${AXI_MASTER_RSTN}]
+
+#================================================================================
+# Connect C2C master port to interconnect slave port
+#================================================================================
+set mAXI [list ${C2C}/m_axi ${C2CB}/m_axi_lite ${JTAG_AXI_MASTER}/M_AXI]
+set mCLK [list ${AXI_MASTER_CLK} ${AXI_MASTER_CLK} ${AXI_MASTER_CLK} ]
+set mRST [list ${AXI_MASTER_RSTN} ${AXI_MASTER_RSTN} ${AXI_MASTER_RSTN}]
+[BUILD_AXI_INTERCONNECT $AXI_INTERCONNECT_NAME ${AXI_MASTER_CLK} $AXI_MASTER_RSTN $mAXI $mCLK $mRST]
+
+
+
+#================================================================================
+# Configure and add AXI slaves
+#================================================================================
+source -quiet ${apollo_root_path}/bd/add_slaves_from_yaml.tcl
+yaml_to_bd "${apollo_root_path}/configs/${build_name}/config.yaml"
+
+GENERATE_AXI_ADDR_MAP_C "${apollo_root_path}/configs/${build_name}/autogen/AXI_slave_addrs.h"
+GENERATE_AXI_ADDR_MAP_VHDL "${apollo_root_path}/configs/${build_name}/autogen/AXI_slave_pkg.vhd"
+read_vhdl "${apollo_root_path}/configs/${build_name}/autogen/AXI_slave_pkg.vhd"
+
+#=================================================
+# Configure SYS MGMT to have all SLRs enabled
+#=================================================
+
+set_property -dict [list CONFIG.CHANNEL_ENABLE_VUSER0_SLAVE0_SSIT {true} CONFIG.CHANNEL_ENABLE_VUSER0_SLAVE1_SSIT {true} CONFIG.CHANNEL_ENABLE_VUSER0_SLAVE2_SSIT {true} CONFIG.Enable_Slave0 {true} CONFIG.Enable_Slave1 {true} CONFIG.Enable_Slave2 {true}] [get_bd_cells F2_SYS_MGMT]
+
+#========================================
+# Finish up
+#========================================
+validate_bd_design
+
+make_wrapper -files [get_files ${bd_design_name}.bd] -top -import -force
+save_bd_design
+
+close_bd_design ${bd_design_name}
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/files.tcl b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/files.tcl
new file mode 100644
index 0000000..609be19
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/files.tcl
@@ -0,0 +1,60 @@
+set bd_path proj
+
+array set bd_files [list {c2cSlave} {configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/createC2CSlaveInterconnect.tcl} \
+ ]
+
+set vhdl_files "\
+ configs/${build_name}/src/top.vhd \
+ configs/${build_name}/FPGA_heater/heater.vhd \
+ configs/${build_name}/FPGA_heater/lut_oscilator.vhd \
+ configs/${build_name}/src/ibert_ultrascale_gty_l.vhd \
+ configs/${build_name}/src/ibert_ultrascale_gty_r.vhd \
+ configs/${build_name}/src/HEATER_map.vhd \
+ configs/${build_name}/src/HEATER_PKG.vhd \
+ configs/${build_name}/src/heater_control.vhd \
+ src/misc/DC_data_CDC.vhd \
+ src/misc/pacd.vhd \
+ src/misc/types.vhd \
+ src/misc/capture_CDC.vhd \
+ src/misc/counter.vhd \
+ src/misc/counter_CDC.vhd \
+ regmap_helper/axiReg/axiRegWidthPkg_32.vhd \
+ regmap_helper/axiReg/axiRegPkg_d64.vhd \
+ regmap_helper/axiReg/axiRegPkg.vhd \
+ regmap_helper/axiReg/axiReg.vhd \
+ regmap_helper/axiReg/bramPortPkg.vhd \
+ regmap_helper/axiReg/axiRegBlocking.vhd \
+ src/C2C_INTF/C2C_Intf.vhd \
+ src/C2C_INTF/CM_phy_lane_control.vhd \
+ src/RGB_PWM.vhd \
+ src/LED_PWM.vhd \
+ src/misc/rate_counter.vhd \
+ src/CM_FW_info/CM_FW_info.vhd \
+ ${autogen_path}/IO/IO_PKG.vhd \
+ ${autogen_path}/IO/IO_map.vhd \
+ ${autogen_path}/C2C_INTF/C2C_INTF_map.vhd \
+ ${autogen_path}/C2C_INTF/C2C_INTF_PKG.vhd \
+ ${autogen_path}/CM_FW_INFO/CM_FW_INFO_PKG.vhd \
+ ${autogen_path}/CM_FW_INFO/CM_FW_INFO_map.vhd \
+ src/C2C_INTF/picoblaze/picoblaze/kcpsm6.vhd \
+ src/C2C_INTF/picoblaze/uart_rx6.vhd \
+ src/C2C_INTF/picoblaze/uart_tx6.vhd \
+ src/C2C_INTF/picoblaze/uC.vhd \
+ src/C2C_INTF/picoblaze/picoblaze/cli.vhd \
+ "
+set xdc_files "\
+ configs/${build_name}/src/top_pins.xdc \
+ configs/${build_name}/src/top_timing.xdc \
+ configs/${build_name}/src/top_heaters.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_l.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_l_clockgroups.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_r.xdc \
+ configs/${build_name}/src/ibert_ultrascale_gty_r_clockgroups.xdc \
+ "
+
+set xci_files "\
+ cores/AXI_BRAM/AXI_BRAM.xci \
+ cores/DP_BRAM/DP_BRAM.xci \
+ configs/${build_name}/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci \
+ configs/${build_name}/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci \
+ "
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/settings.tcl b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/settings.tcl
new file mode 100644
index 0000000..472058a
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/settings.tcl
@@ -0,0 +1,19 @@
+
+#set the FPGA part number
+set FPGA_part xcvu13p-flga2577-1-e
+
+##for c2c
+set C2C F2_C2C
+set C2C_PHY ${C2C}_PHY
+set C2CB F2_C2CB
+set C2CB_PHY ${C2CB}_PHY
+
+#create remote device tree entries, set them to 64 bit
+global REMOTE_C2C_64
+set REMOTE_C2C_64 1
+
+
+set top top
+
+set outputDir ./
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/HEATER_PKG.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/HEATER_PKG.vhd
new file mode 100644
index 0000000..6928f1c
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/HEATER_PKG.vhd
@@ -0,0 +1,105 @@
+--This file was auto-generated.
+--Modifications might be lost.
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+package HEATER_CTRL is
+ type VIRTEX_CLOCKING_MON_t is record
+ COUNTS_REFCLK0 : std_logic_vector(31 downto 0);
+ COUNTS_TXOUTCLK : std_logic_vector(31 downto 0);
+ POWER_GOOD : std_logic;
+ QPLL0_FBCLKLOST : std_logic;
+ QPLL0_LOCK : std_logic;
+ QPLL0_REFCLKLOST : std_logic;
+ RX_CDR_STABLE : std_logic;
+ end record VIRTEX_CLOCKING_MON_t;
+
+ type VIRTEX_RESETS_MON_t is record
+ RX_PMA_RESET_DONE : std_logic;
+ RX_RESET_DONE : std_logic;
+ TX_PMA_RESET_DONE : std_logic;
+ TX_RESET_DONE : std_logic;
+ end record VIRTEX_RESETS_MON_t;
+
+ type VIRTEX_RESETS_CTRL_t is record
+ RESET_ALL : std_logic;
+ RX_DATAPATH : std_logic;
+ RX_PLL_DATAPATH : std_logic;
+ TX_DATAPATH : std_logic;
+ TX_PLL_DATAPATH : std_logic;
+ end record VIRTEX_RESETS_CTRL_t;
+
+ type VIRTEX_RX_MON_t is record
+ BAD_CHAR : std_logic_vector( 3 downto 0);
+ DISP_ERROR : std_logic_vector( 3 downto 0);
+ PMA_RESET_DONE : std_logic;
+ end record VIRTEX_RX_MON_t;
+
+ type VIRTEX_RX_CTRL_t is record
+ PRBS_RESET : std_logic;
+ PRBS_SEL : std_logic_vector( 3 downto 0);
+ USER_CLK_READY : std_logic;
+ end record VIRTEX_RX_CTRL_t;
+
+ type VIRTEX_TX_MON_t is record
+ PMA_RESET_DONE : std_logic;
+ PWR_GOOD : std_logic;
+ end record VIRTEX_TX_MON_t;
+
+ type VIRTEX_TX_CTRL_t is record
+ INHIBIT : std_logic;
+ PRBS_FORCE_ERROR : std_logic;
+ PRBS_SEL : std_logic_vector( 3 downto 0);
+ USER_CLK_READY : std_logic;
+ end record VIRTEX_TX_CTRL_t;
+
+ type VIRTEX_EYESCAN_CTRL_t is record
+ RESET : std_logic;
+ TRIGGER : std_logic;
+ end record VIRTEX_EYESCAN_CTRL_t;
+
+ type VIRTEX_DEBUG_MON_t is record
+ CAPTURE_D : std_logic_vector(31 downto 0);
+ CAPTURE_K : std_logic_vector( 3 downto 0);
+ end record VIRTEX_DEBUG_MON_t;
+
+ type VIRTEX_DEBUG_CTRL_t is record
+ CAPTURE : std_logic;
+ FIXED_SEND_D : std_logic_vector(31 downto 0);
+ FIXED_SEND_K : std_logic_vector( 3 downto 0);
+ MODE : std_logic_vector( 3 downto 0);
+ end record VIRTEX_DEBUG_CTRL_t;
+
+ type VIRTEX_Heater_MON_t is record
+ Output : std_logic_vector(31 downto 0);
+ end record VIRTEX_Heater_MON_t;
+
+ type VIRTEX_Heater_CTRL_t is record
+ Adjust : std_logic_vector(31 downto 0);
+ Enable : std_logic;
+ SelectHeater : std_logic_vector(31 downto 0);
+ end record VIRTEX_Heater_CTRL_t;
+
+ type VIRTEX_MON_t is record
+ CLOCKING : VIRTEX_CLOCKING_MON_t;
+ DEBUG : VIRTEX_DEBUG_MON_t;
+ Heater : VIRTEX_Heater_MON_t;
+ RESETS : VIRTEX_RESETS_MON_t;
+ RX : VIRTEX_RX_MON_t;
+ TX : VIRTEX_TX_MON_t;
+ end record VIRTEX_MON_t;
+
+ type VIRTEX_CTRL_t is record
+ DEBUG : VIRTEX_DEBUG_CTRL_t;
+ EYESCAN : VIRTEX_EYESCAN_CTRL_t;
+ Heater : VIRTEX_Heater_CTRL_t;
+ LOOPBACK : std_logic_vector( 2 downto 0);
+ RESETS : VIRTEX_RESETS_CTRL_t;
+ RX : VIRTEX_RX_CTRL_t;
+ TX : VIRTEX_TX_CTRL_t;
+ end record VIRTEX_CTRL_t;
+
+
+
+end package HEATER_CTRL;
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/HEATER_map.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/HEATER_map.vhd
new file mode 100644
index 0000000..7aa6a1b
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/HEATER_map.vhd
@@ -0,0 +1,209 @@
+--This file was auto-generated.
+--Modifications might be lost.
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.AXIRegPkg.all;
+use work.types.all;
+use work.HEATER_Ctrl.all;
+entity heater_interface is
+ port (
+ clk_axi : in std_logic;
+ reset_axi_n : in std_logic;
+ slave_readMOSI : in AXIReadMOSI;
+ slave_readMISO : out AXIReadMISO := DefaultAXIReadMISO;
+ slave_writeMOSI : in AXIWriteMOSI;
+ slave_writeMISO : out AXIWriteMISO := DefaultAXIWriteMISO;
+ Mon : in VIRTEX_Mon_t;
+ Ctrl : out VIRTEX_Ctrl_t
+ );
+end entity heater_interface;
+architecture behavioral of heater_interface is
+ signal localAddress : slv_32_t;
+ signal localRdData : slv_32_t;
+ signal localRdData_latch : slv_32_t;
+ signal localWrData : slv_32_t;
+ signal localWrEn : std_logic;
+ signal localRdReq : std_logic;
+ signal localRdAck : std_logic;
+
+
+ signal reg_data : slv32_array_t(integer range 0 to 83);
+ constant Default_reg_data : slv32_array_t(integer range 0 to 83) := (others => x"00000000");
+begin -- architecture behavioral
+
+ -------------------------------------------------------------------------------
+ -- AXI
+ -------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------
+ AXIRegBridge : entity work.axiLiteReg
+ port map (
+ clk_axi => clk_axi,
+ reset_axi_n => reset_axi_n,
+ readMOSI => slave_readMOSI,
+ readMISO => slave_readMISO,
+ writeMOSI => slave_writeMOSI,
+ writeMISO => slave_writeMISO,
+ address => localAddress,
+ rd_data => localRdData_latch,
+ wr_data => localWrData,
+ write_en => localWrEn,
+ read_req => localRdReq,
+ read_ack => localRdAck);
+
+ latch_reads: process (clk_axi) is
+ begin -- process latch_reads
+ if clk_axi'event and clk_axi = '1' then -- rising clock edge
+ if localRdReq = '1' then
+ localRdData_latch <= localRdData;
+ end if;
+ end if;
+ end process latch_reads;
+ reads: process (localRdReq,localAddress,reg_data) is
+ begin -- process reads
+ localRdAck <= '0';
+ localRdData <= x"00000000";
+ if localRdReq = '1' then
+ localRdAck <= '1';
+ case to_integer(unsigned(localAddress(6 downto 0))) is
+ when 0 => --0x0
+ localRdData( 1) <= Mon.CLOCKING.POWER_GOOD; --
+ localRdData( 9) <= Mon.CLOCKING.RX_CDR_STABLE; --
+ when 1 => --0x1
+ localRdData(31 downto 0) <= Mon.CLOCKING.COUNTS_TXOUTCLK; --
+ when 2 => --0x2
+ localRdData(31 downto 0) <= Mon.CLOCKING.COUNTS_REFCLK0; --
+ when 3 => --0x3
+ localRdData( 0) <= Mon.CLOCKING.QPLL0_LOCK; --
+ localRdData( 1) <= Mon.CLOCKING.QPLL0_FBCLKLOST; --
+ localRdData( 2) <= Mon.CLOCKING.QPLL0_REFCLKLOST; --
+ when 68 => --0x44
+ localRdData(31 downto 0) <= Mon.DEBUG.CAPTURE_D; --
+ when 5 => --0x5
+ localRdData( 0) <= reg_data( 5)( 0); --
+ localRdData( 4) <= reg_data( 5)( 4); --
+ localRdData( 5) <= reg_data( 5)( 5); --
+ localRdData( 8) <= reg_data( 5)( 8); --
+ localRdData( 9) <= reg_data( 5)( 9); --
+ when 6 => --0x6
+ localRdData( 6) <= Mon.RESETS.TX_RESET_DONE; --
+ localRdData( 7) <= Mon.RESETS.TX_PMA_RESET_DONE; --
+ localRdData(10) <= Mon.RESETS.RX_RESET_DONE; --
+ localRdData(11) <= Mon.RESETS.RX_PMA_RESET_DONE; --
+ when 32 => --0x20
+ localRdData( 1) <= Mon.TX.PMA_RESET_DONE; --
+ localRdData( 4) <= Mon.TX.PWR_GOOD; --
+ when 8 => --0x8
+ localRdData( 2 downto 0) <= reg_data( 8)( 2 downto 0); --
+ when 80 => --0x50
+ localRdData( 0) <= reg_data(80)( 0); --
+ when 71 => --0x47
+ localRdData( 3 downto 0) <= reg_data(71)( 3 downto 0); --
+ when 66 => --0x42
+ localRdData( 3 downto 0) <= reg_data(66)( 3 downto 0); --
+ when 16 => --0x10
+ localRdData( 1) <= Mon.RX.PMA_RESET_DONE; --
+ localRdData( 7 downto 4) <= Mon.RX.BAD_CHAR; --
+ localRdData(11 downto 8) <= Mon.RX.DISP_ERROR; --
+ when 17 => --0x11
+ localRdData( 3 downto 0) <= reg_data(17)( 3 downto 0); --
+ localRdData( 5) <= reg_data(17)( 5); --
+ when 82 => --0x52
+ localRdData(31 downto 0) <= reg_data(82)(31 downto 0); --
+ when 83 => --0x53
+ localRdData(31 downto 0) <= Mon.Heater.Output; --
+ when 49 => --0x31
+ localRdData( 0) <= reg_data(49)( 0); --
+ when 81 => --0x51
+ localRdData(31 downto 0) <= reg_data(81)(31 downto 0); --
+ when 33 => --0x21
+ localRdData( 3 downto 0) <= reg_data(33)( 3 downto 0); --
+ localRdData( 5) <= reg_data(33)( 5); --
+ localRdData( 6) <= reg_data(33)( 6); --
+ when 70 => --0x46
+ localRdData(31 downto 0) <= reg_data(70)(31 downto 0); --
+ when 69 => --0x45
+ localRdData( 3 downto 0) <= Mon.DEBUG.CAPTURE_K; --
+ when others =>
+ localRdData <= x"00000000";
+ end case;
+ end if;
+ end process reads;
+
+
+
+ -- Register mapping to ctrl structures
+ Ctrl.RESETS.RESET_ALL <= reg_data( 5)( 0);
+ Ctrl.RESETS.TX_PLL_DATAPATH <= reg_data( 5)( 4);
+ Ctrl.RESETS.TX_DATAPATH <= reg_data( 5)( 5);
+ Ctrl.RESETS.RX_PLL_DATAPATH <= reg_data( 5)( 8);
+ Ctrl.RESETS.RX_DATAPATH <= reg_data( 5)( 9);
+ Ctrl.LOOPBACK <= reg_data( 8)( 2 downto 0);
+ Ctrl.RX.PRBS_SEL <= reg_data(17)( 3 downto 0);
+ Ctrl.RX.USER_CLK_READY <= reg_data(17)( 5);
+ Ctrl.TX.PRBS_SEL <= reg_data(33)( 3 downto 0);
+ Ctrl.TX.INHIBIT <= reg_data(33)( 5);
+ Ctrl.TX.USER_CLK_READY <= reg_data(33)( 6);
+ Ctrl.EYESCAN.RESET <= reg_data(49)( 0);
+ Ctrl.DEBUG.MODE <= reg_data(66)( 3 downto 0);
+ Ctrl.DEBUG.FIXED_SEND_D <= reg_data(70)(31 downto 0);
+ Ctrl.DEBUG.FIXED_SEND_K <= reg_data(71)( 3 downto 0);
+ Ctrl.Heater.Enable <= reg_data(80)( 0);
+ Ctrl.Heater.Adjust <= reg_data(81)(31 downto 0);
+ Ctrl.Heater.SelectHeater <= reg_data(82)(31 downto 0);
+
+
+
+ reg_writes: process (clk_axi, reset_axi_n) is
+ begin -- process reg_writes
+ if reset_axi_n = '0' then -- asynchronous reset (active low)
+ reg_data <= default_reg_data;
+ elsif clk_axi'event and clk_axi = '1' then -- rising clock edge
+ Ctrl.RX.PRBS_RESET <= '0';
+ Ctrl.TX.PRBS_FORCE_ERROR <= '0';
+ Ctrl.EYESCAN.TRIGGER <= '0';
+ Ctrl.DEBUG.CAPTURE <= '0';
+
+ if localWrEn = '1' then
+ case to_integer(unsigned(localAddress(6 downto 0))) is
+ when 64 => --0x40
+ Ctrl.DEBUG.CAPTURE <= localWrData( 0);
+ when 33 => --0x21
+ Ctrl.TX.PRBS_FORCE_ERROR <= localWrData( 4);
+ reg_data(33)( 3 downto 0) <= localWrData( 3 downto 0); --
+ reg_data(33)( 5) <= localWrData( 5); --
+ reg_data(33)( 6) <= localWrData( 6); --
+ when 66 => --0x42
+ reg_data(66)( 3 downto 0) <= localWrData( 3 downto 0); --
+ when 5 => --0x5
+ reg_data( 5)( 0) <= localWrData( 0); --
+ reg_data( 5)( 4) <= localWrData( 4); --
+ reg_data( 5)( 5) <= localWrData( 5); --
+ reg_data( 5)( 8) <= localWrData( 8); --
+ reg_data( 5)( 9) <= localWrData( 9); --
+ when 70 => --0x46
+ reg_data(70)(31 downto 0) <= localWrData(31 downto 0); --
+ when 49 => --0x31
+ reg_data(49)( 0) <= localWrData( 0); --
+ Ctrl.EYESCAN.TRIGGER <= localWrData( 4);
+ when 8 => --0x8
+ reg_data( 8)( 2 downto 0) <= localWrData( 2 downto 0); --
+ when 71 => --0x47
+ reg_data(71)( 3 downto 0) <= localWrData( 3 downto 0); --
+ when 80 => --0x50
+ reg_data(80)( 0) <= localWrData( 0); --
+ when 17 => --0x11
+ Ctrl.RX.PRBS_RESET <= localWrData( 4);
+ reg_data(17)( 3 downto 0) <= localWrData( 3 downto 0); --
+ reg_data(17)( 5) <= localWrData( 5); --
+ when 82 => --0x52
+ reg_data(82)(31 downto 0) <= localWrData(31 downto 0); --
+ when 81 => --0x51
+ reg_data(81)(31 downto 0) <= localWrData(31 downto 0); --
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process reg_writes;
+
+end architecture behavioral;
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_PKG.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_PKG.vhd
new file mode 100644
index 0000000..059c5dc
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_PKG.vhd
@@ -0,0 +1,105 @@
+--This file was auto-generated.
+--Modifications might be lost.
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+package VIRTEX_TCDS_CTRL is
+ type VIRTEX_TCDS_CLOCKING_MON_t is record
+ COUNTS_REFCLK0 : std_logic_vector(31 downto 0);
+ COUNTS_TXOUTCLK : std_logic_vector(31 downto 0);
+ POWER_GOOD : std_logic;
+ QPLL0_FBCLKLOST : std_logic;
+ QPLL0_LOCK : std_logic;
+ QPLL0_REFCLKLOST : std_logic;
+ RX_CDR_STABLE : std_logic;
+ end record VIRTEX_TCDS_CLOCKING_MON_t;
+
+ type VIRTEX_TCDS_RESETS_MON_t is record
+ RX_PMA_RESET_DONE : std_logic;
+ RX_RESET_DONE : std_logic;
+ TX_PMA_RESET_DONE : std_logic;
+ TX_RESET_DONE : std_logic;
+ end record VIRTEX_TCDS_RESETS_MON_t;
+
+ type VIRTEX_TCDS_RESETS_CTRL_t is record
+ RESET_ALL : std_logic;
+ RX_DATAPATH : std_logic;
+ RX_PLL_DATAPATH : std_logic;
+ TX_DATAPATH : std_logic;
+ TX_PLL_DATAPATH : std_logic;
+ end record VIRTEX_TCDS_RESETS_CTRL_t;
+
+ type VIRTEX_TCDS_RX_MON_t is record
+ BAD_CHAR : std_logic_vector( 3 downto 0);
+ DISP_ERROR : std_logic_vector( 3 downto 0);
+ PMA_RESET_DONE : std_logic;
+ end record VIRTEX_TCDS_RX_MON_t;
+
+ type VIRTEX_TCDS_RX_CTRL_t is record
+ PRBS_RESET : std_logic;
+ PRBS_SEL : std_logic_vector( 3 downto 0);
+ USER_CLK_READY : std_logic;
+ end record VIRTEX_TCDS_RX_CTRL_t;
+
+ type VIRTEX_TCDS_TX_MON_t is record
+ PMA_RESET_DONE : std_logic;
+ PWR_GOOD : std_logic;
+ end record VIRTEX_TCDS_TX_MON_t;
+
+ type VIRTEX_TCDS_TX_CTRL_t is record
+ INHIBIT : std_logic;
+ PRBS_FORCE_ERROR : std_logic;
+ PRBS_SEL : std_logic_vector( 3 downto 0);
+ USER_CLK_READY : std_logic;
+ end record VIRTEX_TCDS_TX_CTRL_t;
+
+ type VIRTEX_TCDS_EYESCAN_CTRL_t is record
+ RESET : std_logic;
+ TRIGGER : std_logic;
+ end record VIRTEX_TCDS_EYESCAN_CTRL_t;
+
+ type VIRTEX_TCDS_DEBUG_MON_t is record
+ CAPTURE_D : std_logic_vector(31 downto 0);
+ CAPTURE_K : std_logic_vector( 3 downto 0);
+ end record VIRTEX_TCDS_DEBUG_MON_t;
+
+ type VIRTEX_TCDS_DEBUG_CTRL_t is record
+ CAPTURE : std_logic;
+ FIXED_SEND_D : std_logic_vector(31 downto 0);
+ FIXED_SEND_K : std_logic_vector( 3 downto 0);
+ MODE : std_logic_vector( 3 downto 0);
+ end record VIRTEX_TCDS_DEBUG_CTRL_t;
+
+ type VIRTEX_TCDS_Heater_MON_t is record
+ Output : std_logic_vector(31 downto 0);
+ end record VIRTEX_TCDS_Heater_MON_t;
+
+ type VIRTEX_TCDS_Heater_CTRL_t is record
+ Adjust : std_logic_vector(31 downto 0);
+ Enable : std_logic;
+ SelectHeater : std_logic_vector(31 downto 0);
+ end record VIRTEX_TCDS_Heater_CTRL_t;
+
+ type VIRTEX_TCDS_MON_t is record
+ CLOCKING : VIRTEX_TCDS_CLOCKING_MON_t;
+ DEBUG : VIRTEX_TCDS_DEBUG_MON_t;
+ Heater : VIRTEX_TCDS_Heater_MON_t;
+ RESETS : VIRTEX_TCDS_RESETS_MON_t;
+ RX : VIRTEX_TCDS_RX_MON_t;
+ TX : VIRTEX_TCDS_TX_MON_t;
+ end record VIRTEX_TCDS_MON_t;
+
+ type VIRTEX_TCDS_CTRL_t is record
+ DEBUG : VIRTEX_TCDS_DEBUG_CTRL_t;
+ EYESCAN : VIRTEX_TCDS_EYESCAN_CTRL_t;
+ Heater : VIRTEX_TCDS_Heater_CTRL_t;
+ LOOPBACK : std_logic_vector( 2 downto 0);
+ RESETS : VIRTEX_TCDS_RESETS_CTRL_t;
+ RX : VIRTEX_TCDS_RX_CTRL_t;
+ TX : VIRTEX_TCDS_TX_CTRL_t;
+ end record VIRTEX_TCDS_CTRL_t;
+
+
+
+end package VIRTEX_TCDS_CTRL;
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_map.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_map.vhd
new file mode 100644
index 0000000..15dab45
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_map.vhd
@@ -0,0 +1,209 @@
+--This file was auto-generated.
+--Modifications might be lost.
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.AXIRegPkg.all;
+use work.types.all;
+use work.VIRTEX_TCDS_Ctrl.all;
+entity VIRTEX_TCDS_interface is
+ port (
+ clk_axi : in std_logic;
+ reset_axi_n : in std_logic;
+ slave_readMOSI : in AXIReadMOSI;
+ slave_readMISO : out AXIReadMISO := DefaultAXIReadMISO;
+ slave_writeMOSI : in AXIWriteMOSI;
+ slave_writeMISO : out AXIWriteMISO := DefaultAXIWriteMISO;
+ Mon : in VIRTEX_TCDS_Mon_t;
+ Ctrl : out VIRTEX_TCDS_Ctrl_t
+ );
+end entity VIRTEX_TCDS_interface;
+architecture behavioral of VIRTEX_TCDS_interface is
+ signal localAddress : slv_32_t;
+ signal localRdData : slv_32_t;
+ signal localRdData_latch : slv_32_t;
+ signal localWrData : slv_32_t;
+ signal localWrEn : std_logic;
+ signal localRdReq : std_logic;
+ signal localRdAck : std_logic;
+
+
+ signal reg_data : slv32_array_t(integer range 0 to 83);
+ constant Default_reg_data : slv32_array_t(integer range 0 to 83) := (others => x"00000000");
+begin -- architecture behavioral
+
+ -------------------------------------------------------------------------------
+ -- AXI
+ -------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------
+ AXIRegBridge : entity work.axiLiteReg
+ port map (
+ clk_axi => clk_axi,
+ reset_axi_n => reset_axi_n,
+ readMOSI => slave_readMOSI,
+ readMISO => slave_readMISO,
+ writeMOSI => slave_writeMOSI,
+ writeMISO => slave_writeMISO,
+ address => localAddress,
+ rd_data => localRdData_latch,
+ wr_data => localWrData,
+ write_en => localWrEn,
+ read_req => localRdReq,
+ read_ack => localRdAck);
+
+ latch_reads: process (clk_axi) is
+ begin -- process latch_reads
+ if clk_axi'event and clk_axi = '1' then -- rising clock edge
+ if localRdReq = '1' then
+ localRdData_latch <= localRdData;
+ end if;
+ end if;
+ end process latch_reads;
+ reads: process (localRdReq,localAddress,reg_data) is
+ begin -- process reads
+ localRdAck <= '0';
+ localRdData <= x"00000000";
+ if localRdReq = '1' then
+ localRdAck <= '1';
+ case to_integer(unsigned(localAddress(6 downto 0))) is
+ when 0 => --0x0
+ localRdData( 1) <= Mon.CLOCKING.POWER_GOOD; --
+ localRdData( 9) <= Mon.CLOCKING.RX_CDR_STABLE; --
+ when 1 => --0x1
+ localRdData(31 downto 0) <= Mon.CLOCKING.COUNTS_TXOUTCLK; --
+ when 2 => --0x2
+ localRdData(31 downto 0) <= Mon.CLOCKING.COUNTS_REFCLK0; --
+ when 3 => --0x3
+ localRdData( 0) <= Mon.CLOCKING.QPLL0_LOCK; --
+ localRdData( 1) <= Mon.CLOCKING.QPLL0_FBCLKLOST; --
+ localRdData( 2) <= Mon.CLOCKING.QPLL0_REFCLKLOST; --
+ when 68 => --0x44
+ localRdData(31 downto 0) <= Mon.DEBUG.CAPTURE_D; --
+ when 5 => --0x5
+ localRdData( 0) <= reg_data( 5)( 0); --
+ localRdData( 4) <= reg_data( 5)( 4); --
+ localRdData( 5) <= reg_data( 5)( 5); --
+ localRdData( 8) <= reg_data( 5)( 8); --
+ localRdData( 9) <= reg_data( 5)( 9); --
+ when 6 => --0x6
+ localRdData( 6) <= Mon.RESETS.TX_RESET_DONE; --
+ localRdData( 7) <= Mon.RESETS.TX_PMA_RESET_DONE; --
+ localRdData(10) <= Mon.RESETS.RX_RESET_DONE; --
+ localRdData(11) <= Mon.RESETS.RX_PMA_RESET_DONE; --
+ when 32 => --0x20
+ localRdData( 1) <= Mon.TX.PMA_RESET_DONE; --
+ localRdData( 4) <= Mon.TX.PWR_GOOD; --
+ when 8 => --0x8
+ localRdData( 2 downto 0) <= reg_data( 8)( 2 downto 0); --
+ when 80 => --0x50
+ localRdData( 0) <= reg_data(80)( 0); --
+ when 71 => --0x47
+ localRdData( 3 downto 0) <= reg_data(71)( 3 downto 0); --
+ when 66 => --0x42
+ localRdData( 3 downto 0) <= reg_data(66)( 3 downto 0); --
+ when 16 => --0x10
+ localRdData( 1) <= Mon.RX.PMA_RESET_DONE; --
+ localRdData( 7 downto 4) <= Mon.RX.BAD_CHAR; --
+ localRdData(11 downto 8) <= Mon.RX.DISP_ERROR; --
+ when 17 => --0x11
+ localRdData( 3 downto 0) <= reg_data(17)( 3 downto 0); --
+ localRdData( 5) <= reg_data(17)( 5); --
+ when 82 => --0x52
+ localRdData(31 downto 0) <= reg_data(82)(31 downto 0); --
+ when 83 => --0x53
+ localRdData(31 downto 0) <= Mon.Heater.Output; --
+ when 49 => --0x31
+ localRdData( 0) <= reg_data(49)( 0); --
+ when 81 => --0x51
+ localRdData(31 downto 0) <= reg_data(81)(31 downto 0); --
+ when 33 => --0x21
+ localRdData( 3 downto 0) <= reg_data(33)( 3 downto 0); --
+ localRdData( 5) <= reg_data(33)( 5); --
+ localRdData( 6) <= reg_data(33)( 6); --
+ when 70 => --0x46
+ localRdData(31 downto 0) <= reg_data(70)(31 downto 0); --
+ when 69 => --0x45
+ localRdData( 3 downto 0) <= Mon.DEBUG.CAPTURE_K; --
+ when others =>
+ localRdData <= x"00000000";
+ end case;
+ end if;
+ end process reads;
+
+
+
+ -- Register mapping to ctrl structures
+ Ctrl.RESETS.RESET_ALL <= reg_data( 5)( 0);
+ Ctrl.RESETS.TX_PLL_DATAPATH <= reg_data( 5)( 4);
+ Ctrl.RESETS.TX_DATAPATH <= reg_data( 5)( 5);
+ Ctrl.RESETS.RX_PLL_DATAPATH <= reg_data( 5)( 8);
+ Ctrl.RESETS.RX_DATAPATH <= reg_data( 5)( 9);
+ Ctrl.LOOPBACK <= reg_data( 8)( 2 downto 0);
+ Ctrl.RX.PRBS_SEL <= reg_data(17)( 3 downto 0);
+ Ctrl.RX.USER_CLK_READY <= reg_data(17)( 5);
+ Ctrl.TX.PRBS_SEL <= reg_data(33)( 3 downto 0);
+ Ctrl.TX.INHIBIT <= reg_data(33)( 5);
+ Ctrl.TX.USER_CLK_READY <= reg_data(33)( 6);
+ Ctrl.EYESCAN.RESET <= reg_data(49)( 0);
+ Ctrl.DEBUG.MODE <= reg_data(66)( 3 downto 0);
+ Ctrl.DEBUG.FIXED_SEND_D <= reg_data(70)(31 downto 0);
+ Ctrl.DEBUG.FIXED_SEND_K <= reg_data(71)( 3 downto 0);
+ Ctrl.Heater.Enable <= reg_data(80)( 0);
+ Ctrl.Heater.Adjust <= reg_data(81)(31 downto 0);
+ Ctrl.Heater.SelectHeater <= reg_data(82)(31 downto 0);
+
+
+
+ reg_writes: process (clk_axi, reset_axi_n) is
+ begin -- process reg_writes
+ if reset_axi_n = '0' then -- asynchronous reset (active low)
+ reg_data <= default_reg_data;
+ elsif clk_axi'event and clk_axi = '1' then -- rising clock edge
+ Ctrl.RX.PRBS_RESET <= '0';
+ Ctrl.TX.PRBS_FORCE_ERROR <= '0';
+ Ctrl.EYESCAN.TRIGGER <= '0';
+ Ctrl.DEBUG.CAPTURE <= '0';
+
+ if localWrEn = '1' then
+ case to_integer(unsigned(localAddress(6 downto 0))) is
+ when 64 => --0x40
+ Ctrl.DEBUG.CAPTURE <= localWrData( 0);
+ when 33 => --0x21
+ Ctrl.TX.PRBS_FORCE_ERROR <= localWrData( 4);
+ reg_data(33)( 3 downto 0) <= localWrData( 3 downto 0); --
+ reg_data(33)( 5) <= localWrData( 5); --
+ reg_data(33)( 6) <= localWrData( 6); --
+ when 66 => --0x42
+ reg_data(66)( 3 downto 0) <= localWrData( 3 downto 0); --
+ when 5 => --0x5
+ reg_data( 5)( 0) <= localWrData( 0); --
+ reg_data( 5)( 4) <= localWrData( 4); --
+ reg_data( 5)( 5) <= localWrData( 5); --
+ reg_data( 5)( 8) <= localWrData( 8); --
+ reg_data( 5)( 9) <= localWrData( 9); --
+ when 70 => --0x46
+ reg_data(70)(31 downto 0) <= localWrData(31 downto 0); --
+ when 49 => --0x31
+ reg_data(49)( 0) <= localWrData( 0); --
+ Ctrl.EYESCAN.TRIGGER <= localWrData( 4);
+ when 8 => --0x8
+ reg_data( 8)( 2 downto 0) <= localWrData( 2 downto 0); --
+ when 71 => --0x47
+ reg_data(71)( 3 downto 0) <= localWrData( 3 downto 0); --
+ when 80 => --0x50
+ reg_data(80)( 0) <= localWrData( 0); --
+ when 17 => --0x11
+ Ctrl.RX.PRBS_RESET <= localWrData( 4);
+ reg_data(17)( 3 downto 0) <= localWrData( 3 downto 0); --
+ reg_data(17)( 5) <= localWrData( 5); --
+ when 82 => --0x52
+ reg_data(82)(31 downto 0) <= localWrData(31 downto 0); --
+ when 81 => --0x51
+ reg_data(81)(31 downto 0) <= localWrData(31 downto 0); --
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process reg_writes;
+
+end architecture behavioral;
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/heater_control.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/heater_control.vhd
new file mode 100644
index 0000000..a8d9c5e
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/heater_control.vhd
@@ -0,0 +1,128 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.axiRegPkg.all;
+use work.HEATER_Ctrl.all;
+use work.types.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity heater_control is
+ port (
+ clk_axi : in std_logic; --50 MHz
+ clk_200 : in std_logic;
+ reset_axi_n : in std_logic;
+ readMOSI : in AXIreadMOSI;
+ readMISO : out AXIreadMISO;
+ writeMOSI : in AXIwriteMOSI;
+ writeMISO : out AXIwriteMISO;
+ heater_output : out slv32_array_t(31 downto 0));
+
+end entity heater_control;
+
+architecture behavioral of heater_control is
+ signal heater_output_pl : slv32_array_t(31 downto 0);
+ signal heater_enable : std_logic;
+ signal heater_adjust : std_logic_vector(31 downto 0);
+ signal heater_select : std_logic_vector(31 downto 0);
+ signal reset : std_logic;
+
+ signal Mon : VIRTEX_Mon_t;
+ signal Ctrl : VIRTEX_Ctrl_t;
+
+begin -- architecture TCDS
+ reset <= not reset_axi_n;
+
+ gen_heater_1: for i in 0 to 7 generate
+ heater_1: entity work.heater
+ generic map (
+ C_SLV_DWIDTH => 32,
+ C_NUM_LUTS => 4096--8192--32768--131072--65536
+ ) port map (
+ clk => clk_200,
+ reset => reset,
+ enable_heater => heater_enable,
+ adjust_heaters => heater_adjust,
+ read_which_heater => heater_select,
+ heater_output => heater_output_pl(i)
+ );
+ end generate gen_heater_1;
+
+ gen_heater_2: for i in 8 to 15 generate
+ heater_2: entity work.heater
+ generic map (
+ C_SLV_DWIDTH => 32,
+ C_NUM_LUTS => 4096--8192--32768--131072--65536
+ ) port map (
+ clk => clk_200,
+ reset => reset,
+ enable_heater => heater_enable,
+ adjust_heaters => heater_adjust,
+ read_which_heater => heater_select,
+ heater_output => heater_output_pl(i)
+ );
+ end generate gen_heater_2;
+
+ gen_heater_3: for i in 16 to 23 generate
+ heater_3: entity work.heater
+ generic map (
+ C_SLV_DWIDTH => 32,
+ C_NUM_LUTS => 4096--8192--32768--131072--65536
+ ) port map (
+ clk => clk_200,
+ reset => reset,
+ enable_heater => heater_enable,
+ adjust_heaters => heater_adjust,
+ read_which_heater => heater_select,
+ heater_output => heater_output_pl(i)
+ );
+ end generate gen_heater_3;
+
+ gen_heater_4: for i in 24 to 31 generate
+ heater_4: entity work.heater
+ generic map (
+ C_SLV_DWIDTH => 32,
+ C_NUM_LUTS => 4096--8192--32768--131072--65536
+ ) port map (
+ clk => clk_200,
+ reset => reset,
+ enable_heater => heater_enable,
+ adjust_heaters => heater_adjust,
+ read_which_heater => heater_select,
+ heater_output => heater_output_pl(i)
+ );
+ end generate gen_heater_4;
+
+ data_proc: process (clk_200, reset) is
+ begin -- process data_proc
+ if rising_edge(clk_200) then
+ if (reset = '1') then
+ heater_enable <= '0';
+ heater_adjust <= (others=>'0');
+ heater_output <= (others => (others => '0'));
+ heater_select <= (others => '0');
+ else
+ heater_enable <= Ctrl.Heater.Enable;
+ heater_adjust <= Ctrl.Heater.Adjust;
+ heater_output <= heater_output_pl;
+ heater_select <= Ctrl.Heater.SelectHeater;
+ end if;
+ end if;
+ end process data_proc;
+
+
+
+ heater_interface_1: entity work.heater_interface
+ port map (
+ clk_axi => clk_axi,
+ reset_axi_n => reset_axi_n,
+ slave_readMOSI => readMOSI,
+ slave_readMISO => readMISO,
+ slave_writeMOSI => writeMOSI,
+ slave_writeMISO => writeMISO,
+ Mon => Mon,
+ Ctrl => Ctrl);
+
+end architecture behavioral;
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci
new file mode 100644
index 0000000..ee4cc04
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci
@@ -0,0 +1,1258 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ ibert_ultrascale_gty_core_l
+
+
+ 0
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diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci
new file mode 100644
index 0000000..c97822c
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci
@@ -0,0 +1,1244 @@
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+ 0
+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ General_ES
+ 1
+ 322.265625
+ UNASSIGNED
+ UNASSIGNED
+ DIFF_SSTL15
+ 0
+ 0
+ 1
+ 0
+ QUAD230_0
+ 4
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ 250
+ "11"
+ "11"
+ "11"
+ "11"
+ "11"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "11"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "11"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "11"
+ "11"
+ "11"
+ "11"
+ "11"
+ "11"
+ "10"
+ "10"
+ "10"
+ "10"
+ "10"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
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+ "00"
+ "10"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "00"
+ "10"
+ "10"
+ "10"
+ "10"
+ "10"
+ "10"
+ 25.78125
+ 25.78125
+ 25.78125
+ 25.78125
+ 25.78125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 25.78125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 25.78125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 3.125
+ 25.78125
+ 25.78125
+ 25.78125
+ 25.78125
+ 25.78125
+ 25.78125
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ xcvu13p
+ virtexuplus
+ 0
+ 10
+ -1
+ 0
+ "1"
+ "1"
+ false
+ true
+ 1
+ Custom_1
+ Custom_2
+ Custom_3
+ 1
+ 80
+ 80
+ 80
+ 25.78125
+ 5
+ 5
+ QPLL0
+ QPLL0
+ QPLL0
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ None
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ None
+ Custom_1_/_25.78125_Gbps
+ Custom_1_/_25.78125_Gbps
+ None
+ Custom_1_/_25.78125_Gbps
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ 13
+ 0
+ 0
+ 322.265625
+ 100
+ 100
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ MGTREFCLK0_222
+ MGTREFCLK0_222
+ MGTREFCLK0_222
+ None
+ MGTREFCLK0_224
+ MGTREFCLK0_224
+ MGTREFCLK0_226
+ MGTREFCLK0_226
+ MGTREFCLK0_229
+ MGTREFCLK0_229
+ MGTREFCLK0_230
+ None
+ MGTREFCLK0_233
+ MGTREFCLK0_233
+ None
+ MGTREFCLK0_233
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ None
+ 105.00
+ QUAD221_0
+ "1"
+ UNASSIGNED
+ UNASSIGNED
+ LVCMOS25
+ 322.265625
+ UNASSIGNED
+ UNASSIGNED
+ DIFF_SSTL15
+ 0
+ 0
+ QUAD230_0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ibert_ultrascale_gty_core_r
+ 20
+ 20
+ 20
+ AC
+ AC
+ AC
+ AUTO
+ AUTO
+ AUTO
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ PROGRAMMABLE
+ PROGRAMMABLE
+ PROGRAMMABLE
+ 800
+ 800
+ 800
+ virtexuplus
+
+
+ xcvu13p
+ flga2577
+ VHDL
+
+ MIXED
+ -1
+
+ E
+ TRUE
+ TRUE
+ IP_Flow
+ 5
+ TRUE
+ ../../../../top.gen/sources_1/ip/ibert_ultrascale_gty_core_r_1
+
+ .
+ 2020.2.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.vhd
new file mode 100644
index 0000000..33856b2
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.vhd
@@ -0,0 +1,498 @@
+
+--// file: ibert_ultrascale_gty_0.v
+--//////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2012.3
+--// \ \ Application : IBERT Ultrascale
+--// / / Filename : example_ibert_ultrascale_gty_0
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--// Module example_ibert_ultrascale_gty_0
+--// Generated by Xilinx IBERT_Ultrascale
+--//////////////////////////////////////////////////////////////////////////////
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.numeric_std.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity ibert_ultrascale_gty_l is
+ generic
+ (
+ C_NUM_GTY_QUADS : integer := 13;
+ C_GTY_REFCLKS_USED : integer :=6
+ );
+ port
+ (
+ gty_refclk0p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ gty_refclk0n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ -- gty_sysclk_i : in std_logic;
+ --gty_sysclkp_i : in std_logic;
+ --gty_sysclkn_i : in std_logic;
+ gty_rxn_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_rxp_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txn_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txp_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0)
+ );
+end entity ibert_ultrascale_gty_l;
+
+architecture proc of ibert_ultrascale_gty_l is
+-- //
+-- // Ibert refclk internal signals
+-- //
+
+ signal gty_qrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_refclk0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_refclk1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_sysclk_i: std_logic;
+begin
+
+
+ --
+ -- Sysclock IBUFDS instantiation
+ --
+ --u_ibufgds : IBUFGDS
+ -- generic map (
+ -- DIFF_TERM => true
+ -- ) port map (
+ -- I => gty_sysclkp_i,
+ -- IB => gty_sysclkn_i,
+ -- O => gty_sysclk_i
+ -- );
+
+ u_gty_sysclk_internal : BUFG_GT
+ port map (
+ I => gty_odiv2_0_i(1),
+ O => gty_sysclk_i,
+ CE => '1',
+ CEMASK => '0',
+ CLR => '0',
+ CLRMASK => '0',
+ DIV => "000"
+ );
+
+
+ --
+ -- Refclk IBUFDS instantiations
+ --
+
+
+ u_buf_q2_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(0),
+ ODIV2 => gty_odiv2_0_i(0),
+ CEB => '0',
+ I => gty_refclk0p_i(0),
+ IB => gty_refclk0n_i(0)
+ );
+
+
+ u_buf_q4_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(1),
+ ODIV2 => gty_odiv2_0_i(1),
+ CEB => '0',
+ I => gty_refclk0p_i(1),
+ IB => gty_refclk0n_i(1)
+ );
+
+ --u_buf_q2_clk1 :IBUFDS_GTE4
+ -- port map(
+ -- O => gty_refclk1_i(0),
+ -- ODIV2 => gty_odiv2_1_i(0),
+ -- CEB => '0',
+ -- I => gty_refclk1p_i(0),
+ -- IB => gty_refclk1n_i(0)
+ -- );
+
+ u_buf_q6_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(2),
+ ODIV2 => gty_odiv2_0_i(2),
+ CEB => '0',
+ I => gty_refclk0p_i(2),
+ IB => gty_refclk0n_i(2)
+ );
+
+ u_buf_q9_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(3),
+ ODIV2 => gty_odiv2_0_i(3),
+ CEB => '0',
+ I => gty_refclk0p_i(3),
+ IB => gty_refclk0n_i(3)
+ );
+
+
+ u_buf_q10_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(4),
+ ODIV2 => gty_odiv2_0_i(4),
+ CEB => '0',
+ I => gty_refclk0p_i(4),
+ IB => gty_refclk0n_i(4)
+ );
+
+ u_buf_q13_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(5),
+ ODIV2 => gty_odiv2_0_i(5),
+ CEB => '0',
+ I => gty_refclk0p_i(5),
+ IB => gty_refclk0n_i(5)
+ );
+
+
+ --
+ -- Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
+ --
+-- gty_qrefclk0_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk1_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qnorthrefclk0_i(0) <= '0';
+-- gty_qnorthrefclk1_i(0) <= '0';
+-- gty_qsouthrefclk0_i(0) <= '0';
+-- gty_qsouthrefclk1_i(0) <= '0';
+----GTYE4_COMMON clock connection
+-- gty_qrefclk00_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk10_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qrefclk01_i(0) <= '0';
+-- gty_qrefclk11_i(0) <= '0';
+-- gty_qnorthrefclk00_i(0) <= '0';
+-- gty_qnorthrefclk10_i(0) <= '0';
+-- gty_qnorthrefclk01_i(0) <= '0';
+-- gty_qnorthrefclk11_i(0) <= '0';
+-- gty_qsouthrefclk00_i(0) <= '0';
+-- gty_qsouthrefclk10_i(0) <= '0';
+-- gty_qsouthrefclk01_i(0) <= '0';
+-- gty_qsouthrefclk11_i(0) <= '0';
+--
+--
+
+ gty_qrefclk0_i(0) <= '0';
+ gty_qrefclk1_i(0) <= '0';
+ gty_qnorthrefclk0_i(0) <= '0';
+ gty_qnorthrefclk1_i(0) <= '0';
+ gty_qsouthrefclk0_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk1_i(0) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(0) <= '0';
+ gty_qrefclk10_i(0) <= '0';
+ gty_qrefclk01_i(0) <= '0';
+ gty_qrefclk11_i(0) <= '0';
+ gty_qnorthrefclk00_i(0) <= '0';
+ gty_qnorthrefclk10_i(0) <= '0';
+ gty_qnorthrefclk01_i(0) <= '0';
+ gty_qnorthrefclk11_i(0) <= '0';
+ gty_qsouthrefclk00_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk10_i(0) <= '0';
+ gty_qsouthrefclk01_i(0) <= '0';
+ gty_qsouthrefclk11_i(0) <= '0';
+
+
+ gty_qrefclk0_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk1_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(1) <= '0';
+ gty_qnorthrefclk1_i(1) <= '0';
+ gty_qsouthrefclk0_i(1) <= '0';
+ gty_qsouthrefclk1_i(1) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk10_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(1) <= '0';
+ gty_qrefclk11_i(1) <= '0';
+ gty_qnorthrefclk00_i(1) <= '0';
+ gty_qnorthrefclk10_i(1) <= '0';
+ gty_qnorthrefclk01_i(1) <= '0';
+ gty_qnorthrefclk11_i(1) <= '0';
+ gty_qsouthrefclk00_i(1) <= '0';
+ gty_qsouthrefclk10_i(1) <= '0';
+ gty_qsouthrefclk01_i(1) <= '0';
+ gty_qsouthrefclk11_i(1) <= '0';
+
+
+ gty_qrefclk0_i(2) <= '0';
+ gty_qrefclk1_i(2) <= '0';
+ gty_qnorthrefclk0_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk1_i(2) <= '0';
+ gty_qsouthrefclk0_i(2) <= '0';
+ gty_qsouthrefclk1_i(2) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(2) <= '0';
+ gty_qrefclk10_i(2) <= '0';
+ gty_qrefclk01_i(2) <= '0';
+ gty_qrefclk11_i(2) <= '0';
+ gty_qnorthrefclk00_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk10_i(2) <= '0';
+ gty_qnorthrefclk01_i(2) <= '0';
+ gty_qnorthrefclk11_i(2) <= '0';
+ gty_qsouthrefclk00_i(2) <= '0';
+ gty_qsouthrefclk10_i(2) <= '0';
+ gty_qsouthrefclk01_i(2) <= '0';
+ gty_qsouthrefclk11_i(2) <= '0';
+
+
+ gty_qrefclk0_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk1_i(3) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(3) <= '0';
+ gty_qnorthrefclk1_i(3) <= '0';
+ gty_qsouthrefclk0_i(3) <= '0';
+ gty_qsouthrefclk1_i(3) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk10_i(3) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(3) <= '0';
+ gty_qrefclk11_i(3) <= '0';
+ gty_qnorthrefclk00_i(3) <= '0';
+ gty_qnorthrefclk10_i(3) <= '0';
+ gty_qnorthrefclk01_i(3) <= '0';
+ gty_qnorthrefclk11_i(3) <= '0';
+ gty_qsouthrefclk00_i(3) <= '0';
+ gty_qsouthrefclk10_i(3) <= '0';
+ gty_qsouthrefclk01_i(3) <= '0';
+ gty_qsouthrefclk11_i(3) <= '0';
+
+ gty_qrefclk0_i(4) <= '0';
+ gty_qrefclk1_i(4) <= '0';
+ gty_qnorthrefclk0_i(4) <= '0';
+ gty_qnorthrefclk1_i(4) <= '0';
+ gty_qsouthrefclk0_i(4) <= gty_refclk0_i(2);
+ gty_qsouthrefclk1_i(4) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(4) <= '0';
+ gty_qrefclk10_i(4) <= '0';
+ gty_qrefclk01_i(4) <= '0';
+ gty_qrefclk11_i(4) <= '0';
+ gty_qnorthrefclk00_i(4) <= '0';
+ gty_qnorthrefclk10_i(4) <= '0';
+ gty_qnorthrefclk01_i(4) <= '0';
+ gty_qnorthrefclk11_i(4) <= '0';
+ gty_qsouthrefclk00_i(4) <= gty_refclk0_i(2);
+ gty_qsouthrefclk10_i(4) <= '0';
+ gty_qsouthrefclk01_i(4) <= '0';
+ gty_qsouthrefclk11_i(4) <= '0';
+
+
+ gty_qrefclk0_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk1_i(5) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(5) <= '0';
+ gty_qnorthrefclk1_i(5) <= '0';
+ gty_qsouthrefclk0_i(5) <= '0';
+ gty_qsouthrefclk1_i(5) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk10_i(5) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(5) <= '0';
+ gty_qrefclk11_i(5) <= '0';
+ gty_qnorthrefclk00_i(5) <= '0';
+ gty_qnorthrefclk10_i(5) <= '0';
+ gty_qnorthrefclk01_i(5) <= '0';
+ gty_qnorthrefclk11_i(5) <= '0';
+ gty_qsouthrefclk00_i(5) <= '0';
+ gty_qsouthrefclk10_i(5) <= '0';
+ gty_qsouthrefclk01_i(5) <= '0';
+ gty_qsouthrefclk11_i(5) <= '0';
+
+
+ gty_qrefclk0_i(6) <= '0';
+ gty_qrefclk1_i(6) <= '0';
+ gty_qnorthrefclk0_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk1_i(6) <= '0';
+ gty_qsouthrefclk0_i(6) <= '0';
+ gty_qsouthrefclk1_i(6) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(6) <= '0';
+ gty_qrefclk10_i(6) <= '0';
+ gty_qrefclk01_i(6) <= '0';
+ gty_qrefclk11_i(6) <= '0';
+ gty_qnorthrefclk00_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk10_i(6) <= '0';
+ gty_qnorthrefclk01_i(6) <= '0';
+ gty_qnorthrefclk11_i(6) <= '0';
+ gty_qsouthrefclk00_i(6) <= '0';
+ gty_qsouthrefclk10_i(6) <= '0';
+ gty_qsouthrefclk01_i(6) <= '0';
+ gty_qsouthrefclk11_i(6) <= '0';
+
+ gty_qrefclk0_i(7) <= '0';
+ gty_qrefclk1_i(7) <= '0';
+ gty_qnorthrefclk0_i(7) <= '0';
+ gty_qnorthrefclk1_i(7) <= '0';
+ gty_qsouthrefclk0_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk1_i(7) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(7) <= '0';
+ gty_qrefclk10_i(7) <= '0';
+ gty_qrefclk01_i(7) <= '0';
+ gty_qrefclk11_i(7) <= '0';
+ gty_qnorthrefclk00_i(7) <= '0';
+ gty_qnorthrefclk10_i(7) <= '0';
+ gty_qnorthrefclk01_i(7) <= '0';
+ gty_qnorthrefclk11_i(7) <= '0';
+ gty_qsouthrefclk00_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk10_i(7) <= '0';
+ gty_qsouthrefclk01_i(7) <= '0';
+ gty_qsouthrefclk11_i(7) <= '0';
+
+ gty_qrefclk0_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk1_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qnorthrefclk0_i(8) <= '0';
+ gty_qnorthrefclk1_i(8) <= '0';
+ gty_qsouthrefclk0_i(8) <= '0';
+ gty_qsouthrefclk1_i(8) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk10_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qrefclk01_i(8) <= '0';
+ gty_qrefclk11_i(8) <= '0';
+ gty_qnorthrefclk00_i(8) <= '0';
+ gty_qnorthrefclk10_i(8) <= '0';
+ gty_qnorthrefclk01_i(8) <= '0';
+ gty_qnorthrefclk11_i(8) <= '0';
+ gty_qsouthrefclk00_i(8) <= '0';
+ gty_qsouthrefclk10_i(8) <= '0';
+ gty_qsouthrefclk01_i(8) <= '0';
+ gty_qsouthrefclk11_i(8) <= '0';
+
+
+ gty_qrefclk0_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk1_i(9) <= '0';
+ gty_qnorthrefclk0_i(9) <= '0';
+ gty_qnorthrefclk1_i(9) <= '0';
+ gty_qsouthrefclk0_i(9) <= '0';
+ gty_qsouthrefclk1_i(9) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk10_i(9) <= '0';
+ gty_qrefclk01_i(9) <= '0';
+ gty_qrefclk11_i(9) <= '0';
+ gty_qnorthrefclk00_i(9) <= '0';
+ gty_qnorthrefclk10_i(9) <= '0';
+ gty_qnorthrefclk01_i(9) <= '0';
+ gty_qnorthrefclk11_i(9) <= '0';
+ gty_qsouthrefclk00_i(9) <= '0';
+ gty_qsouthrefclk10_i(9) <= '0';
+ gty_qsouthrefclk01_i(9) <= '0';
+ gty_qsouthrefclk11_i(9) <= '0';
+
+
+ gty_qrefclk0_i(10) <= '0';
+ gty_qrefclk1_i(10) <= '0';
+ gty_qnorthrefclk0_i(10) <= '0';
+ gty_qnorthrefclk1_i(10) <= '0';
+ gty_qsouthrefclk0_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk1_i(10) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(10) <= '0';
+ gty_qrefclk10_i(10) <= '0';
+ gty_qrefclk01_i(10) <= '0';
+ gty_qrefclk11_i(10) <= '0';
+ gty_qnorthrefclk00_i(10) <= '0';
+ gty_qnorthrefclk10_i(10) <= '0';
+ gty_qnorthrefclk01_i(10) <= '0';
+ gty_qnorthrefclk11_i(10) <= '0';
+ gty_qsouthrefclk00_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk10_i(10) <= '0';
+ gty_qsouthrefclk01_i(10) <= '0';
+ gty_qsouthrefclk11_i(10) <= '0';
+
+
+ gty_qrefclk0_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk1_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qnorthrefclk0_i(11) <= '0';
+ gty_qnorthrefclk1_i(11) <= '0';
+ gty_qsouthrefclk0_i(11) <= '0';
+ gty_qsouthrefclk1_i(11) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk10_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qrefclk01_i(11) <= '0';
+ gty_qrefclk11_i(11) <= '0';
+ gty_qnorthrefclk00_i(11) <= '0';
+ gty_qnorthrefclk10_i(11) <= '0';
+ gty_qnorthrefclk01_i(11) <= '0';
+ gty_qnorthrefclk11_i(11) <= '0';
+ gty_qsouthrefclk00_i(11) <= '0';
+ gty_qsouthrefclk10_i(11) <= '0';
+ gty_qsouthrefclk01_i(11) <= '0';
+ gty_qsouthrefclk11_i(11) <= '0';
+
+
+ gty_qrefclk0_i(12) <= '0';
+ gty_qrefclk1_i(12) <= '0';
+ gty_qnorthrefclk0_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk1_i(12) <= '0';
+ gty_qsouthrefclk0_i(12) <= '0';
+ gty_qsouthrefclk1_i(12) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(12) <= '0';
+ gty_qrefclk10_i(12) <= '0';
+ gty_qrefclk01_i(12) <= '0';
+ gty_qrefclk11_i(12) <= '0';
+ gty_qnorthrefclk00_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk10_i(12) <= '0';
+ gty_qnorthrefclk01_i(12) <= '0';
+ gty_qnorthrefclk11_i(12) <= '0';
+ gty_qsouthrefclk00_i(12) <= '0';
+ gty_qsouthrefclk10_i(12) <= '0';
+ gty_qsouthrefclk01_i(12) <= '0';
+ gty_qsouthrefclk11_i(12) <= '0';
+ --
+ -- IBERT core instantiation
+ --
+ u_ibert_gty_core : entity work.ibert_ultrascale_gty_core_l
+ port map (
+ txn_o => gty_txn_o,
+ txp_o => gty_txp_o,
+ rxn_i => gty_rxn_i,
+ rxp_i => gty_rxp_i,
+ clk => gty_sysclk_i,
+ gtrefclk0_i => gty_qrefclk0_i,
+ gtrefclk1_i => gty_qrefclk1_i,
+ gtnorthrefclk0_i => gty_qnorthrefclk0_i,
+ gtnorthrefclk1_i => gty_qnorthrefclk1_i,
+ gtsouthrefclk0_i => gty_qsouthrefclk0_i,
+ gtsouthrefclk1_i => gty_qsouthrefclk1_i,
+ gtrefclk00_i => gty_qrefclk00_i,
+ gtrefclk10_i => gty_qrefclk10_i,
+ gtrefclk01_i => gty_qrefclk01_i,
+ gtrefclk11_i => gty_qrefclk11_i,
+ gtnorthrefclk00_i => gty_qnorthrefclk00_i,
+ gtnorthrefclk10_i => gty_qnorthrefclk10_i,
+ gtnorthrefclk01_i => gty_qnorthrefclk01_i,
+ gtnorthrefclk11_i => gty_qnorthrefclk11_i,
+ gtsouthrefclk00_i => gty_qsouthrefclk00_i,
+ gtsouthrefclk10_i => gty_qsouthrefclk10_i,
+ gtsouthrefclk01_i => gty_qsouthrefclk01_i,
+ gtsouthrefclk11_i => gty_qsouthrefclk11_i
+ );
+
+end proc;
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.xdc b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.xdc
new file mode 100644
index 0000000..92004d2
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l.xdc
@@ -0,0 +1,70 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2012.3
+## \ \ Application : IBERT Ultrascale
+## / / Filename : example_ibert_ultrascale_gty_0.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+##
+## Icon Constraints
+##
+
+set_property C_CLK_INPUT_FREQ_HZ 50000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets AXI_CLK]
+
+##
+##gtrefclk lock constraints
+##
+## set_property PACKAGE_PIN AY39 [get_ports gty_refclk0p_i[0]]
+## set_property PACKAGE_PIN AY40 [get_ports gty_refclk0n_i[0]]
+## set_property PACKAGE_PIN AW41 [get_ports gty_refclk1p_i[0]]
+## set_property PACKAGE_PIN AW42 [get_ports gty_refclk1n_i[0]]
+## set_property PACKAGE_PIN AT39 [get_ports gty_refclk0p_i[1]]
+## set_property PACKAGE_PIN AT40 [get_ports gty_refclk0n_i[1]]
+## set_property PACKAGE_PIN AR41 [get_ports gty_refclk1p_i[1]]
+## set_property PACKAGE_PIN AR42 [get_ports gty_refclk1n_i[1]]
+## set_property PACKAGE_PIN AM39 [get_ports gty_refclk0p_i[2]]
+## set_property PACKAGE_PIN AM40 [get_ports gty_refclk0n_i[2]]
+## set_property PACKAGE_PIN AL41 [get_ports gty_refclk1p_i[2]]
+## set_property PACKAGE_PIN AL42 [get_ports gty_refclk1n_i[2]]
+## set_property PACKAGE_PIN AA41 [get_ports gty_refclk0p_i[3]]
+## set_property PACKAGE_PIN AA42 [get_ports gty_refclk0n_i[3]]
+## set_property PACKAGE_PIN Y39 [get_ports gty_refclk1p_i[3]]
+## set_property PACKAGE_PIN Y40 [get_ports gty_refclk1n_i[3]]
+## set_property PACKAGE_PIN W41 [get_ports gty_refclk0p_i[4]]
+## set_property PACKAGE_PIN W42 [get_ports gty_refclk0n_i[4]]
+## set_property PACKAGE_PIN V39 [get_ports gty_refclk1p_i[4]]
+## set_property PACKAGE_PIN V40 [get_ports gty_refclk1n_i[4]]
+## set_property PACKAGE_PIN N41 [get_ports gty_refclk0p_i[5]]
+## set_property PACKAGE_PIN N42 [get_ports gty_refclk0n_i[5]]
+## set_property PACKAGE_PIN M39 [get_ports gty_refclk1p_i[5]]
+## set_property PACKAGE_PIN M40 [get_ports gty_refclk1n_i[5]]
+##
+## Refclk constraints
+##
+#create_clock -name gtrefclk0_2 -period 3.104 [get_ports p_lf_r0_ad]
+create_clock -name gtrefclk0_2 -period 3.1030303 [get_ports p_lf_r0_ad]
+set_clock_groups -group [get_clocks gtrefclk0_2 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_4 -period 3.1030303 [get_ports p_lf_r0_af]
+set_clock_groups -group [get_clocks gtrefclk0_4 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_6 -period 3.1030303 [get_ports p_lf_r0_r]
+set_clock_groups -group [get_clocks gtrefclk0_6 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_9 -period 3.1030303 [get_ports p_lf_r0_u]
+set_clock_groups -group [get_clocks gtrefclk0_9 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_10 -period 3.1030303 [get_ports p_lf_r0_v]
+set_clock_groups -group [get_clocks gtrefclk0_10 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_13 -period 3.1030303 [get_ports p_lf_r0_y]
+set_clock_groups -group [get_clocks gtrefclk0_13 -include_generated_clocks] -asynchronous
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l_clockgroups.xdc b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l_clockgroups.xdc
new file mode 100644
index 0000000..aa0ef57
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_l_clockgroups.xdc
@@ -0,0 +1,175 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2017.1
+## \ \ Application : IBERT Ultrascale
+## / / Filename : ibert_ultrascale_gty_ip_example.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+## TX/RX out clock clock constraints
+##
+# GT X0Y4
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y5
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y6
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y7
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y8
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y9
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y10
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y11
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y12
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y13
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y14
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y15
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y16
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y17
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y18
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y19
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y20
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y21
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y22
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y23
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y24
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y25
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y26
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y27
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y28
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y29
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y30
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y31
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y32
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y33
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y34
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y35
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y36
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y37
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y38
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y39
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y40
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y41
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y42
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y43
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y48
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y49
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y50
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y51
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y52
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y53
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y54
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y55
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y56
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y57
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y58
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y59
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_L/u_ibert_gty_core/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.vhd
new file mode 100644
index 0000000..1945307
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.vhd
@@ -0,0 +1,498 @@
+
+--// file: ibert_ultrascale_gty_0.v
+--//////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2012.3
+--// \ \ Application : IBERT Ultrascale
+--// / / Filename : example_ibert_ultrascale_gty_0
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--// Module example_ibert_ultrascale_gty_0
+--// Generated by Xilinx IBERT_Ultrascale
+--//////////////////////////////////////////////////////////////////////////////
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.numeric_std.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity ibert_ultrascale_gty_r is
+ generic
+ (
+ C_NUM_GTY_QUADS : integer := 13;
+ C_GTY_REFCLKS_USED : integer :=6
+ );
+ port
+ (
+ gty_refclk0p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ gty_refclk0n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1p_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+-- gty_refclk1n_i : in std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ -- gty_sysclk_i : in std_logic;
+ --gty_sysclkp_i : in std_logic;
+ --gty_sysclkn_i : in std_logic;
+ gty_rxn_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_rxp_i : in std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txn_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0);
+ gty_txp_o : out std_logic_vector(4*C_NUM_GTY_QUADS-1 downto 0)
+ );
+end entity ibert_ultrascale_gty_r;
+
+architecture proc of ibert_ultrascale_gty_r is
+-- //
+-- // Ibert refclk internal signals
+-- //
+
+ signal gty_qrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk0_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk1_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qnorthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk00_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk10_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk01_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_qsouthrefclk11_i :std_logic_vector(C_NUM_GTY_QUADS-1 downto 0);
+ signal gty_refclk0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_refclk1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_0_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_odiv2_1_i :std_logic_vector(C_GTY_REFCLKS_USED-1 downto 0);
+ signal gty_sysclk_i: std_logic;
+begin
+
+
+ --
+ -- Sysclock IBUFDS instantiation
+ --
+ --u_ibufgds : IBUFGDS
+ -- generic map (
+ -- DIFF_TERM => true
+ -- ) port map (
+ -- I => gty_sysclkp_i,
+ -- IB => gty_sysclkn_i,
+ -- O => gty_sysclk_i
+ -- );
+
+ u_gty_sysclk_internal : BUFG_GT
+ port map (
+ I => gty_odiv2_0_i(4),
+ O => gty_sysclk_i,
+ CE => '1',
+ CEMASK => '0',
+ CLR => '0',
+ CLRMASK => '0',
+ DIV => "000"
+ );
+
+
+ --
+ -- Refclk IBUFDS instantiations
+ --
+
+
+ u_buf_q2_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(0),
+ ODIV2 => gty_odiv2_0_i(0),
+ CEB => '0',
+ I => gty_refclk0p_i(0),
+ IB => gty_refclk0n_i(0)
+ );
+
+
+ u_buf_q4_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(1),
+ ODIV2 => gty_odiv2_0_i(1),
+ CEB => '0',
+ I => gty_refclk0p_i(1),
+ IB => gty_refclk0n_i(1)
+ );
+
+ --u_buf_q2_clk1 :IBUFDS_GTE4
+ -- port map(
+ -- O => gty_refclk1_i(0),
+ -- ODIV2 => gty_odiv2_1_i(0),
+ -- CEB => '0',
+ -- I => gty_refclk1p_i(0),
+ -- IB => gty_refclk1n_i(0)
+ -- );
+
+ u_buf_q6_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(2),
+ ODIV2 => gty_odiv2_0_i(2),
+ CEB => '0',
+ I => gty_refclk0p_i(2),
+ IB => gty_refclk0n_i(2)
+ );
+
+ u_buf_q9_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(3),
+ ODIV2 => gty_odiv2_0_i(3),
+ CEB => '0',
+ I => gty_refclk0p_i(3),
+ IB => gty_refclk0n_i(3)
+ );
+
+
+ u_buf_q10_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(4),
+ ODIV2 => gty_odiv2_0_i(4),
+ CEB => '0',
+ I => gty_refclk0p_i(4),
+ IB => gty_refclk0n_i(4)
+ );
+
+ u_buf_q13_clk0 :IBUFDS_GTE4
+ port map(
+ O => gty_refclk0_i(5),
+ ODIV2 => gty_odiv2_0_i(5),
+ CEB => '0',
+ I => gty_refclk0p_i(5),
+ IB => gty_refclk0n_i(5)
+ );
+
+
+ --
+ -- Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
+ --
+-- gty_qrefclk0_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk1_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qnorthrefclk0_i(0) <= '0';
+-- gty_qnorthrefclk1_i(0) <= '0';
+-- gty_qsouthrefclk0_i(0) <= '0';
+-- gty_qsouthrefclk1_i(0) <= '0';
+----GTYE4_COMMON clock connection
+-- gty_qrefclk00_i(0) <= gty_refclk0_i(0);
+-- gty_qrefclk10_i(0) <= '0'; --gty_refclk1_i(0);
+-- gty_qrefclk01_i(0) <= '0';
+-- gty_qrefclk11_i(0) <= '0';
+-- gty_qnorthrefclk00_i(0) <= '0';
+-- gty_qnorthrefclk10_i(0) <= '0';
+-- gty_qnorthrefclk01_i(0) <= '0';
+-- gty_qnorthrefclk11_i(0) <= '0';
+-- gty_qsouthrefclk00_i(0) <= '0';
+-- gty_qsouthrefclk10_i(0) <= '0';
+-- gty_qsouthrefclk01_i(0) <= '0';
+-- gty_qsouthrefclk11_i(0) <= '0';
+--
+--
+
+ gty_qrefclk0_i(0) <= '0';
+ gty_qrefclk1_i(0) <= '0';
+ gty_qnorthrefclk0_i(0) <= '0';
+ gty_qnorthrefclk1_i(0) <= '0';
+ gty_qsouthrefclk0_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk1_i(0) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(0) <= '0';
+ gty_qrefclk10_i(0) <= '0';
+ gty_qrefclk01_i(0) <= '0';
+ gty_qrefclk11_i(0) <= '0';
+ gty_qnorthrefclk00_i(0) <= '0';
+ gty_qnorthrefclk10_i(0) <= '0';
+ gty_qnorthrefclk01_i(0) <= '0';
+ gty_qnorthrefclk11_i(0) <= '0';
+ gty_qsouthrefclk00_i(0) <= gty_refclk0_i(0);
+ gty_qsouthrefclk10_i(0) <= '0';
+ gty_qsouthrefclk01_i(0) <= '0';
+ gty_qsouthrefclk11_i(0) <= '0';
+
+
+ gty_qrefclk0_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk1_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qnorthrefclk0_i(1) <= '0';
+ gty_qnorthrefclk1_i(1) <= '0';
+ gty_qsouthrefclk0_i(1) <= '0';
+ gty_qsouthrefclk1_i(1) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(1) <= gty_refclk0_i(0);
+ gty_qrefclk10_i(1) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(1) <= '0';
+ gty_qrefclk11_i(1) <= '0';
+ gty_qnorthrefclk00_i(1) <= '0';
+ gty_qnorthrefclk10_i(1) <= '0';
+ gty_qnorthrefclk01_i(1) <= '0';
+ gty_qnorthrefclk11_i(1) <= '0';
+ gty_qsouthrefclk00_i(1) <= '0';
+ gty_qsouthrefclk10_i(1) <= '0';
+ gty_qsouthrefclk01_i(1) <= '0';
+ gty_qsouthrefclk11_i(1) <= '0';
+
+
+ gty_qrefclk0_i(2) <= '0';
+ gty_qrefclk1_i(2) <= '0';
+ gty_qnorthrefclk0_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk1_i(2) <= '0';
+ gty_qsouthrefclk0_i(2) <= '0';
+ gty_qsouthrefclk1_i(2) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(2) <= '0';
+ gty_qrefclk10_i(2) <= '0';
+ gty_qrefclk01_i(2) <= '0';
+ gty_qrefclk11_i(2) <= '0';
+ gty_qnorthrefclk00_i(2) <= gty_refclk0_i(0);
+ gty_qnorthrefclk10_i(2) <= '0';
+ gty_qnorthrefclk01_i(2) <= '0';
+ gty_qnorthrefclk11_i(2) <= '0';
+ gty_qsouthrefclk00_i(2) <= '0';
+ gty_qsouthrefclk10_i(2) <= '0';
+ gty_qsouthrefclk01_i(2) <= '0';
+ gty_qsouthrefclk11_i(2) <= '0';
+
+
+ gty_qrefclk0_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk1_i(3) <= '0';
+ gty_qnorthrefclk0_i(3) <= '0';
+ gty_qnorthrefclk1_i(3) <= '0';
+ gty_qsouthrefclk0_i(3) <= '0';
+ gty_qsouthrefclk1_i(3) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(3) <= gty_refclk0_i(1);
+ gty_qrefclk10_i(3) <= '0';
+ gty_qrefclk01_i(3) <= '0';
+ gty_qrefclk11_i(3) <= '0';
+ gty_qnorthrefclk00_i(3) <= '0';
+ gty_qnorthrefclk10_i(3) <= '0';
+ gty_qnorthrefclk01_i(3) <= '0';
+ gty_qnorthrefclk11_i(3) <= '0';
+ gty_qsouthrefclk00_i(3) <= '0';
+ gty_qsouthrefclk10_i(3) <= '0';
+ gty_qsouthrefclk01_i(3) <= '0';
+ gty_qsouthrefclk11_i(3) <= '0';
+
+ gty_qrefclk0_i(4) <= '0';
+ gty_qrefclk1_i(4) <= '0';
+ gty_qnorthrefclk0_i(4) <= gty_refclk0_i(1);
+ gty_qnorthrefclk1_i(4) <= '0';
+ gty_qsouthrefclk0_i(4) <= '0';
+ gty_qsouthrefclk1_i(4) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(4) <= '0';
+ gty_qrefclk10_i(4) <= '0';
+ gty_qrefclk01_i(4) <= '0';
+ gty_qrefclk11_i(4) <= '0';
+ gty_qnorthrefclk00_i(4) <= gty_refclk0_i(1);
+ gty_qnorthrefclk10_i(4) <= '0';
+ gty_qnorthrefclk01_i(4) <= '0';
+ gty_qnorthrefclk11_i(4) <= '0';
+ gty_qsouthrefclk00_i(4) <= '0';
+ gty_qsouthrefclk10_i(4) <= '0';
+ gty_qsouthrefclk01_i(4) <= '0';
+ gty_qsouthrefclk11_i(4) <= '0';
+
+
+ gty_qrefclk0_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk1_i(5) <= '0';
+ gty_qnorthrefclk0_i(5) <= '0';
+ gty_qnorthrefclk1_i(5) <= '0';
+ gty_qsouthrefclk0_i(5) <= '0';
+ gty_qsouthrefclk1_i(5) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(5) <= gty_refclk0_i(2);
+ gty_qrefclk10_i(5) <= '0'; --gty_refclk1_i(0);
+ gty_qrefclk01_i(5) <= '0';
+ gty_qrefclk11_i(5) <= '0';
+ gty_qnorthrefclk00_i(5) <= '0';
+ gty_qnorthrefclk10_i(5) <= '0';
+ gty_qnorthrefclk01_i(5) <= '0';
+ gty_qnorthrefclk11_i(5) <= '0';
+ gty_qsouthrefclk00_i(5) <= '0';
+ gty_qsouthrefclk10_i(5) <= '0';
+ gty_qsouthrefclk01_i(5) <= '0';
+ gty_qsouthrefclk11_i(5) <= '0';
+
+
+ gty_qrefclk0_i(6) <= '0';
+ gty_qrefclk1_i(6) <= '0';
+ gty_qnorthrefclk0_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk1_i(6) <= '0';
+ gty_qsouthrefclk0_i(6) <= '0';
+ gty_qsouthrefclk1_i(6) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(6) <= '0';
+ gty_qrefclk10_i(6) <= '0';
+ gty_qrefclk01_i(6) <= '0';
+ gty_qrefclk11_i(6) <= '0';
+ gty_qnorthrefclk00_i(6) <= gty_refclk0_i(2);
+ gty_qnorthrefclk10_i(6) <= '0';
+ gty_qnorthrefclk01_i(6) <= '0';
+ gty_qnorthrefclk11_i(6) <= '0';
+ gty_qsouthrefclk00_i(6) <= '0';
+ gty_qsouthrefclk10_i(6) <= '0';
+ gty_qsouthrefclk01_i(6) <= '0';
+ gty_qsouthrefclk11_i(6) <= '0';
+
+ gty_qrefclk0_i(7) <= '0';
+ gty_qrefclk1_i(7) <= '0';
+ gty_qnorthrefclk0_i(7) <= '0';
+ gty_qnorthrefclk1_i(7) <= '0';
+ gty_qsouthrefclk0_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk1_i(7) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(7) <= '0';
+ gty_qrefclk10_i(7) <= '0';
+ gty_qrefclk01_i(7) <= '0';
+ gty_qrefclk11_i(7) <= '0';
+ gty_qnorthrefclk00_i(7) <= '0';
+ gty_qnorthrefclk10_i(7) <= '0';
+ gty_qnorthrefclk01_i(7) <= '0';
+ gty_qnorthrefclk11_i(7) <= '0';
+ gty_qsouthrefclk00_i(7) <= gty_refclk0_i(3);
+ gty_qsouthrefclk10_i(7) <= '0';
+ gty_qsouthrefclk01_i(7) <= '0';
+ gty_qsouthrefclk11_i(7) <= '0';
+
+ gty_qrefclk0_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk1_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qnorthrefclk0_i(8) <= '0';
+ gty_qnorthrefclk1_i(8) <= '0';
+ gty_qsouthrefclk0_i(8) <= '0';
+ gty_qsouthrefclk1_i(8) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(8) <= gty_refclk0_i(3);
+ gty_qrefclk10_i(8) <= '0'; --gty_refclk1_i(1);
+ gty_qrefclk01_i(8) <= '0';
+ gty_qrefclk11_i(8) <= '0';
+ gty_qnorthrefclk00_i(8) <= '0';
+ gty_qnorthrefclk10_i(8) <= '0';
+ gty_qnorthrefclk01_i(8) <= '0';
+ gty_qnorthrefclk11_i(8) <= '0';
+ gty_qsouthrefclk00_i(8) <= '0';
+ gty_qsouthrefclk10_i(8) <= '0';
+ gty_qsouthrefclk01_i(8) <= '0';
+ gty_qsouthrefclk11_i(8) <= '0';
+
+
+ gty_qrefclk0_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk1_i(9) <= '0';
+ gty_qnorthrefclk0_i(9) <= '0';
+ gty_qnorthrefclk1_i(9) <= '0';
+ gty_qsouthrefclk0_i(9) <= '0';
+ gty_qsouthrefclk1_i(9) <= '0';
+--GTYE4_COMMON clock connection
+ gty_qrefclk00_i(9) <= gty_refclk0_i(4);
+ gty_qrefclk10_i(9) <= '0';
+ gty_qrefclk01_i(9) <= '0';
+ gty_qrefclk11_i(9) <= '0';
+ gty_qnorthrefclk00_i(9) <= '0';
+ gty_qnorthrefclk10_i(9) <= '0';
+ gty_qnorthrefclk01_i(9) <= '0';
+ gty_qnorthrefclk11_i(9) <= '0';
+ gty_qsouthrefclk00_i(9) <= '0';
+ gty_qsouthrefclk10_i(9) <= '0';
+ gty_qsouthrefclk01_i(9) <= '0';
+ gty_qsouthrefclk11_i(9) <= '0';
+
+
+ gty_qrefclk0_i(10) <= '0';
+ gty_qrefclk1_i(10) <= '0';
+ gty_qnorthrefclk0_i(10) <= '0';
+ gty_qnorthrefclk1_i(10) <= '0';
+ gty_qsouthrefclk0_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk1_i(10) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(10) <= '0';
+ gty_qrefclk10_i(10) <= '0';
+ gty_qrefclk01_i(10) <= '0';
+ gty_qrefclk11_i(10) <= '0';
+ gty_qnorthrefclk00_i(10) <= '0';
+ gty_qnorthrefclk10_i(10) <= '0';
+ gty_qnorthrefclk01_i(10) <= '0';
+ gty_qnorthrefclk11_i(10) <= '0';
+ gty_qsouthrefclk00_i(10) <= gty_refclk0_i(5);
+ gty_qsouthrefclk10_i(10) <= '0';
+ gty_qsouthrefclk01_i(10) <= '0';
+ gty_qsouthrefclk11_i(10) <= '0';
+
+
+ gty_qrefclk0_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk1_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qnorthrefclk0_i(11) <= '0';
+ gty_qnorthrefclk1_i(11) <= '0';
+ gty_qsouthrefclk0_i(11) <= '0';
+ gty_qsouthrefclk1_i(11) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(11) <= gty_refclk0_i(5);
+ gty_qrefclk10_i(11) <= '0'; --gty_refclk1_i(11);
+ gty_qrefclk01_i(11) <= '0';
+ gty_qrefclk11_i(11) <= '0';
+ gty_qnorthrefclk00_i(11) <= '0';
+ gty_qnorthrefclk10_i(11) <= '0';
+ gty_qnorthrefclk01_i(11) <= '0';
+ gty_qnorthrefclk11_i(11) <= '0';
+ gty_qsouthrefclk00_i(11) <= '0';
+ gty_qsouthrefclk10_i(11) <= '0';
+ gty_qsouthrefclk01_i(11) <= '0';
+ gty_qsouthrefclk11_i(11) <= '0';
+
+
+ gty_qrefclk0_i(12) <= '0';
+ gty_qrefclk1_i(12) <= '0';
+ gty_qnorthrefclk0_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk1_i(12) <= '0';
+ gty_qsouthrefclk0_i(12) <= '0';
+ gty_qsouthrefclk1_i(12) <= '0';
+ --GTYE4_COMMON clock connection
+ gty_qrefclk00_i(12) <= '0';
+ gty_qrefclk10_i(12) <= '0';
+ gty_qrefclk01_i(12) <= '0';
+ gty_qrefclk11_i(12) <= '0';
+ gty_qnorthrefclk00_i(12) <= gty_refclk0_i(5);
+ gty_qnorthrefclk10_i(12) <= '0';
+ gty_qnorthrefclk01_i(12) <= '0';
+ gty_qnorthrefclk11_i(12) <= '0';
+ gty_qsouthrefclk00_i(12) <= '0';
+ gty_qsouthrefclk10_i(12) <= '0';
+ gty_qsouthrefclk01_i(12) <= '0';
+ gty_qsouthrefclk11_i(12) <= '0';
+ --
+ -- IBERT core instantiation
+ --
+ u_ibert_gty_core_1 : entity work.ibert_ultrascale_gty_core_r
+ port map (
+ txn_o => gty_txn_o,
+ txp_o => gty_txp_o,
+ rxn_i => gty_rxn_i,
+ rxp_i => gty_rxp_i,
+ clk => gty_sysclk_i,
+ gtrefclk0_i => gty_qrefclk0_i,
+ gtrefclk1_i => gty_qrefclk1_i,
+ gtnorthrefclk0_i => gty_qnorthrefclk0_i,
+ gtnorthrefclk1_i => gty_qnorthrefclk1_i,
+ gtsouthrefclk0_i => gty_qsouthrefclk0_i,
+ gtsouthrefclk1_i => gty_qsouthrefclk1_i,
+ gtrefclk00_i => gty_qrefclk00_i,
+ gtrefclk10_i => gty_qrefclk10_i,
+ gtrefclk01_i => gty_qrefclk01_i,
+ gtrefclk11_i => gty_qrefclk11_i,
+ gtnorthrefclk00_i => gty_qnorthrefclk00_i,
+ gtnorthrefclk10_i => gty_qnorthrefclk10_i,
+ gtnorthrefclk01_i => gty_qnorthrefclk01_i,
+ gtnorthrefclk11_i => gty_qnorthrefclk11_i,
+ gtsouthrefclk00_i => gty_qsouthrefclk00_i,
+ gtsouthrefclk10_i => gty_qsouthrefclk10_i,
+ gtsouthrefclk01_i => gty_qsouthrefclk01_i,
+ gtsouthrefclk11_i => gty_qsouthrefclk11_i
+ );
+
+end proc;
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.xdc b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.xdc
new file mode 100644
index 0000000..e91a4a4
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r.xdc
@@ -0,0 +1,70 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2012.3
+## \ \ Application : IBERT Ultrascale
+## / / Filename : example_ibert_ultrascale_gty_0.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+##
+## Icon Constraints
+##
+
+## set_property C_CLK_INPUT_FREQ_HZ 50000000 [get_debug_cores dbg_hub]
+## set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+## set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+## connect_debug_port dbg_hub/clk [get_nets AXI_CLK]
+
+##
+##gtrefclk lock constraints
+##
+## set_property PACKAGE_PIN AY39 [get_ports gty_refclk0p_i[0]]
+## set_property PACKAGE_PIN AY40 [get_ports gty_refclk0n_i[0]]
+## set_property PACKAGE_PIN AW41 [get_ports gty_refclk1p_i[0]]
+## set_property PACKAGE_PIN AW42 [get_ports gty_refclk1n_i[0]]
+## set_property PACKAGE_PIN AT39 [get_ports gty_refclk0p_i[1]]
+## set_property PACKAGE_PIN AT40 [get_ports gty_refclk0n_i[1]]
+## set_property PACKAGE_PIN AR41 [get_ports gty_refclk1p_i[1]]
+## set_property PACKAGE_PIN AR42 [get_ports gty_refclk1n_i[1]]
+## set_property PACKAGE_PIN AM39 [get_ports gty_refclk0p_i[2]]
+## set_property PACKAGE_PIN AM40 [get_ports gty_refclk0n_i[2]]
+## set_property PACKAGE_PIN AL41 [get_ports gty_refclk1p_i[2]]
+## set_property PACKAGE_PIN AL42 [get_ports gty_refclk1n_i[2]]
+## set_property PACKAGE_PIN AA41 [get_ports gty_refclk0p_i[3]]
+## set_property PACKAGE_PIN AA42 [get_ports gty_refclk0n_i[3]]
+## set_property PACKAGE_PIN Y39 [get_ports gty_refclk1p_i[3]]
+## set_property PACKAGE_PIN Y40 [get_ports gty_refclk1n_i[3]]
+## set_property PACKAGE_PIN W41 [get_ports gty_refclk0p_i[4]]
+## set_property PACKAGE_PIN W42 [get_ports gty_refclk0n_i[4]]
+## set_property PACKAGE_PIN V39 [get_ports gty_refclk1p_i[4]]
+## set_property PACKAGE_PIN V40 [get_ports gty_refclk1n_i[4]]
+## set_property PACKAGE_PIN N41 [get_ports gty_refclk0p_i[5]]
+## set_property PACKAGE_PIN N42 [get_ports gty_refclk0n_i[5]]
+## set_property PACKAGE_PIN M39 [get_ports gty_refclk1p_i[5]]
+## set_property PACKAGE_PIN M40 [get_ports gty_refclk1n_i[5]]
+##
+## Refclk constraints
+##
+#create_clock -name gtrefclk0_2 -period 3.104 [get_ports p_lf_r0_ad]
+create_clock -name gtrefclk0_1 -period 3.1030303 [get_ports p_rt_r0_n]
+set_clock_groups -group [get_clocks gtrefclk0_1 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_3 -period 3.1030303 [get_ports p_rt_r0_b]
+set_clock_groups -group [get_clocks gtrefclk0_3 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_5 -period 3.1030303 [get_ports p_rt_r0_e]
+set_clock_groups -group [get_clocks gtrefclk0_5 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_7 -period 3.1030303 [get_ports p_rt_r0_f]
+set_clock_groups -group [get_clocks gtrefclk0_7 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_11 -period 3.1030303 [get_ports p_rt_r0_g]
+set_clock_groups -group [get_clocks gtrefclk0_11 -include_generated_clocks] -asynchronous
+create_clock -name gtrefclk0_12 -period 3.1030303 [get_ports p_rt_r0_i]
+set_clock_groups -group [get_clocks gtrefclk0_12 -include_generated_clocks] -asynchronous
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r_clockgroups.xdc b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r_clockgroups.xdc
new file mode 100644
index 0000000..765eddd
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/ibert_ultrascale_gty_r_clockgroups.xdc
@@ -0,0 +1,175 @@
+
+# file: ibert_ultrascale_gty_0.xdc
+####################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 2017.1
+## \ \ Application : IBERT Ultrascale
+## / / Filename : ibert_ultrascale_gty_ip_example.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+##
+## Generated by Xilinx IBERT Ultrascale
+##**************************************************************************
+## TX/RX out clock clock constraints
+##
+# GT X0Y4
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y5
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y6
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y7
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y8
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y9
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y10
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y11
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[1].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y12
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y13
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y14
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y15
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[2].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y16
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y17
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y18
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y19
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[3].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y20
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y21
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y22
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y23
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[4].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y24
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y25
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y26
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y27
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[5].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y28
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y29
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y30
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y31
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[6].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y32
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y33
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y34
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y35
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[7].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y36
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y37
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y38
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y39
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[8].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y40
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y41
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y42
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y43
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[9].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y48
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y49
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y50
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y51
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[10].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y52
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y53
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y54
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y55
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[11].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y56
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[0].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y57
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[1].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y58
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[2].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
+# GT X0Y59
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/RXOUTCLK}] -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {IBERT_R/u_ibert_gty_core_1/inst/QUAD[12].u_q/CH[3].u_ch/u_gtye4_channel/TXOUTCLK}] -include_generated_clocks]
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top.vhd b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top.vhd
new file mode 100644
index 0000000..eeb3953
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top.vhd
@@ -0,0 +1,1525 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_misc.all;
+
+use work.axiRegPkg.all;
+use work.axiRegPkg_d64.all;
+use work.types.all;
+
+use work.IO_Ctrl.all;
+use work.C2C_INTF_CTRL.all;
+use work.AXISlaveAddrPkg.all;
+
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity top is
+ port (
+ -- clocks
+ p_clk_200 : in std_logic;
+ n_clk_200 : in std_logic; -- 200 MHz system clock
+
+ -- A copy of the RefClk#0 used by the 12-channel FireFlys on the left side of the FPGA.
+ --This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_lf_x12_r0_clk : in std_logic;
+ -- n_lf_x12_r0_clk : in std_logic;
+
+ -- -- A copy of the RefClk#0 used by the 4-channel FireFlys on the left side of the FPGA.
+ -- -- This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_lf_x4_r0_clk : in std_logic;
+ -- n_lf_x4_r0_clk : in std_logic;
+
+ ---- A copy of the RefClk#0 used by the 12-channel FireFlys on the right side of the FPGA.
+ ---- This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_rt_x12_r0_clk : in std_logic;
+ -- n_rt_x12_r0_clk : in std_logic;
+
+ ---- A copy of the RefClk#0 used by the 4-channel FireFlys on the right side of the FPGA.
+ ---- This can be the output of either refclk synthesizer R0A or R0B.
+ -- p_rt_x4_r0_clk : in std_logic;
+ -- n_rt_x4_r0_clk : in std_logic;
+
+ --'input' "fpga_identity" to differentiate FPGA#1 from FPGA#2.
+ -- The signal will be HI in FPGA#1 and LO in FPGA#2.
+-- fpga_identity : in std_logic;
+
+ -- 'output' "led": 3 bits to light a tri-color LED
+ -- These use different pins on F1 vs. F2. The pins are unused on the "other" FPGA,
+ -- so each color for both FPGAs can be driven at the same time
+ --led_f1_red : out std_logic;
+ --led_f1_green : out std_logic;
+ --led_f1_blue : out std_logic;
+ led_f2_red : out std_logic;
+ led_f2_green : out std_logic;
+ led_f2_blue : out std_logic;
+
+ -- 'input' "mcu_to_f": 1 bit trom the MCU
+ -- 'output' "f_to_mcu": 1 bit to the MCU
+ -- There is no currently defined use for these.
+ --mcu_to_f : in std_logic;
+ --f_to_mcu : out std_logic;
+
+ -- 'output' "c2c_ok": 1 bit to the MCU
+ -- The FPGA should set this output HI when the chip-2-chip link is working.
+ c2c_ok : out std_logic;
+
+ -- If the Zynq on the SM is the TCDS endpoint, then both FPGAs only use port #0 for TCDS
+ -- signals and the two FPGAs are programmed identically.
+ --
+ -- If FPGA#1 is the TCDS endpoint, then:
+ -- 1) TCDS signals from the ATCA backplane connect to port#0 on FPGA#1
+ -- 2) TCDS information is sent from FPGA#1 to FPGA#2 on port #3
+ -- 3) TCDS information is sent from FPGA#1 to the Zynq on the SM on port #2.
+ --
+ -- RefClk#0 for quad AB comes from REFCLK SYNTHESIZER R1A which can be driven by:
+ -- a) synth oscillator
+ -- b) HQ_CLK from the SM
+ -- b1) 320 MHz if FPGA#1 is the TCDS endpoint
+ -- b2) 40 MHz if the SM is the TCDS endpoint
+ -- c) Optional front panel connector for an external LVDS clock
+ -- quad AB
+ -- p_lf_r0_ab : in std_logic;
+ -- n_lf_r0_ab : in std_logic;
+ ----
+ ---- RefClk#1 comes from REFCLK SYNTHESIZER R1B which can be driven by:
+ ---- a) synth oscillator
+ ---- b) an output from EXTERNAL REFCLK SYNTH R1A
+ ---- c) the 40 MHz TCDS RECOVERED CLOCK from FPGA #1
+ ---- RefClk#1 is only connected on FPGA#1, and is only used when FPGA#1 is the TCDS endpoint.
+ ---- quad AB
+ -- p_lf_r1_ab : in std_logic;
+ -- n_lf_r1_ab : in std_logic;
+ ---- quad L
+ -- p_lf_r1_l : in std_logic;
+ -- n_lf_r1_l : in std_logic;
+
+ --
+ -- Port #0 is the main TCDS path. Both FPGAs use it when the Zynq on the SM is the
+ -- TCDS endpoint. Only FPGA#1 uses it when FPGA#1 is the TCDS endpoint.
+ -- Port #0 receive (schematic name is "con*_tcds_in")
+ -- p_tcds_in : in std_logic;
+ -- n_tcds_in : in std_logic;
+
+ ---- Port #0 transmit (schematic name is "con*_tcds_out")
+ -- p_tcds_out : out std_logic;
+ -- n_tcds_out : out std_logic;
+ ----
+ ---- Port #2 is used to send TCDS signals between FPGA#1 and the Zynq when
+ ---- FPGA#1 is the TCDS endpoint. Port #2 is not used when the Zynq on the SM is the
+ ---- TCDS endpoint. Port #2 is not connected to anything on FPGA#2.
+ ---- quad AB
+ -- p_tcds_from_zynq_a : in std_logic;
+ -- n_tcds_from_zynq_a : in std_logic;
+ -- p_tcds_to_zynq_a : out std_logic;
+ -- n_tcds_to_zynq_a : out std_logic;
+
+ ---- quad L
+ -- p_tcds_from_zynq_b : in std_logic;
+ -- n_tcds_from_zynq_b : in std_logic;
+ -- p_tcds_to_zynq_b : out std_logic;
+ -- n_tcds_to_zynq_b : out std_logic;
+
+ ----
+ ---- Port #3 is cross-connected between the two FPGAs. It is only used when FPGA#1
+ ---- is the TCDS endpoint.
+ ---- quad AB
+ -- p_tcds_cross_recv_a : in std_logic;
+ -- n_tcds_cross_recv_a : in std_logic;
+ -- p_tcds_cross_xmit_a : out std_logic;
+ -- n_tcds_cross_xmit_a : out std_logic;
+
+ ---- quad L
+ -- p_tcds_cross_recv_b : in std_logic;
+ -- n_tcds_cross_recv_b : in std_logic;
+ -- p_tcds_cross_xmit_b : out std_logic;
+ -- n_tcds_cross_xmit_b : out std_logic;
+
+ ----
+ ---- Recovered 40 MHz TCDS clock output to feed REFCLK SYNTHESIZER R1B.
+ ---- This is only connected on FPGA#1, and is only used when FPGA#1 is the
+ ---- TCDS endpoint. On FPGA#2, these signals are not connected, but are reserved.
+ -- p_tcds_recov_clk : out std_logic;
+ -- n_tcds_recov_clk : out std_logic;
+
+ ----
+ ---- 40 MHz TCDS clock connected to FPGA logic. This is used in the FPGA for two
+ ---- purposes. The first is to generate high-speed processing clocks by multiplying
+ ---- in an MMCM. The second is to synchronize processing to the 40 MHz LHC bunch crossing.
+ -- p_tcds40_clk : in std_logic;
+ -- n_tcds40_clk : in std_logic;
+
+
+ ---- Spare input signals from the "other" FPGA.
+ ---- These cross-connect to the spare output signals on the other FPGA
+ ---- 'in_spare[2]' is connected to global glock-capable input pins
+ -- p_in_spare : in std_logic_vector(2 downto 0);
+ -- n_in_spare : in std_logic_vector(2 downto 0);
+ ---- Spare output signals to the "other" FPGA.
+ ---- These cross-connect to the spare input signals on the other FPGA
+ -- p_out_spare : out std_logic_vector(2 downto 0);
+ -- n_out_spare : out std_logic_vector(2 downto 0);
+
+ ---- HDMI-style test connector on the front panel
+ ---- 5 differential and 2 single-ended
+ ---- 'test_conn_0' connects to global clock-capable input pins
+ ---- THE DIRECTIONS ARE SET UP FOR TESTING. CHANGE THEM FOR REAL APPLICATIONS.
+ -- p_test_conn_0 : in std_logic;
+ -- n_test_conn_0 : in std_logic;
+ -- p_test_conn_1 : in std_logic;
+ -- n_test_conn_1 : in std_logic;
+ -- p_test_conn_2 : in std_logic;
+ -- n_test_conn_2 : in std_logic;
+ -- p_test_conn_3 : in std_logic;
+ -- n_test_conn_3 : in std_logic;
+ -- p_test_conn_4 : in std_logic;
+ -- n_test_conn_4 : in std_logic;
+ -- test_conn_5 : out std_logic;
+ -- test_conn_6 : out std_logic;
+
+ -- Spare pins to 1mm x 1mm headers on the bottom of the board
+ -- They could be used in an emergency as I/Os, or for debugging
+ -- hdr[1] and hdr[2] are on global clock-capable pins
+ --input hdr1, hdr2,
+ --input hdr3, hdr4, hdr5, hdr6,
+ --output reg hdr7, hdr8, hdr9, hdr10,
+
+ -- C2C primary (#1) and secondary (#2) links to the Zynq on the SM
+ p_rt_r0_l : in std_logic;
+ n_rt_r0_l : in std_logic;
+ p_mgt_sm_to_f : in std_logic_vector(2 downto 1);
+ n_mgt_sm_to_f : in std_logic_vector(2 downto 1);
+ p_mgt_f_to_sm : out std_logic_vector(2 downto 1);
+ n_mgt_f_to_sm : out std_logic_vector(2 downto 1);
+
+ --n_mgt_z2v : in std_logic_vector(1 downto 1);
+ --p_mgt_z2v : in std_logic_vector(1 downto 1);
+ --n_mgt_v2z : out std_logic_vector(1 downto 1);
+ --p_mgt_v2z : out std_logic_vector(1 downto 1);
+
+ -- Connect FF1, 12 lane, quad AC,AD,AE
+ p_lf_r0_ad : in std_logic;
+ n_lf_r0_ad : in std_logic;
+ n_ff1_recv : in std_logic_vector(11 downto 0);
+ p_ff1_recv : in std_logic_vector(11 downto 0);
+ n_ff1_xmit : out std_logic_vector(11 downto 0);
+ p_ff1_xmit : out std_logic_vector(11 downto 0);
+
+ -- Connect FF4, 4 lane, quad AF
+ p_lf_r0_af : in std_logic;
+ n_lf_r0_af : in std_logic;
+ n_ff4_recv : in std_logic_vector(3 downto 0);
+ p_ff4_recv : in std_logic_vector(3 downto 0);
+ n_ff4_xmit : out std_logic_vector(3 downto 0);
+ p_ff4_xmit : out std_logic_vector(3 downto 0);
+
+ -- Connect FF2, 12 lane, quad Q,R,S
+ p_lf_r0_r : in std_logic;
+ n_lf_r0_r : in std_logic;
+ n_ff2_recv : in std_logic_vector(11 downto 0);
+ p_ff2_recv : in std_logic_vector(11 downto 0);
+ n_ff2_xmit : out std_logic_vector(11 downto 0);
+ p_ff2_xmit : out std_logic_vector(11 downto 0);
+
+ -- Connect FF5, 4 lane, quad T
+ n_ff5_recv : in std_logic_vector(3 downto 0);
+ p_ff5_recv : in std_logic_vector(3 downto 0);
+ n_ff5_xmit : out std_logic_vector(3 downto 0);
+ p_ff5_xmit : out std_logic_vector(3 downto 0);
+
+ -- Connect FF6, 4 lane, quad U
+ p_lf_r0_u : in std_logic;
+ n_lf_r0_u : in std_logic;
+ n_ff6_recv : in std_logic_vector(3 downto 0);
+ p_ff6_recv : in std_logic_vector(3 downto 0);
+ n_ff6_xmit : out std_logic_vector(3 downto 0);
+ p_ff6_xmit : out std_logic_vector(3 downto 0);
+
+ -- Connect FF7, 4 lane, quad V
+ p_lf_r0_v : in std_logic;
+ n_lf_r0_v : in std_logic;
+ n_ff7_recv : in std_logic_vector(3 downto 0);
+ p_ff7_recv : in std_logic_vector(3 downto 0);
+ n_ff7_xmit : out std_logic_vector(3 downto 0);
+ p_ff7_xmit : out std_logic_vector(3 downto 0);
+
+ -- Connect FF3, 12 lane, quad X,Y,Z
+ p_lf_r0_y : in std_logic;
+ n_lf_r0_y : in std_logic;
+ n_ff3_recv : in std_logic_vector(11 downto 0);
+ p_ff3_recv : in std_logic_vector(11 downto 0);
+ n_ff3_xmit : out std_logic_vector(11 downto 0);
+ p_ff3_xmit : out std_logic_vector(11 downto 0);
+
+
+ -- quad M
+ n_m_recv : in std_logic_vector(3 downto 0);
+ p_m_recv : in std_logic_vector(3 downto 0);
+ n_m_xmit : out std_logic_vector(3 downto 0);
+ p_m_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad N
+ p_rt_r0_n : in std_logic;
+ n_rt_r0_n : in std_logic;
+ n_n_recv : in std_logic_vector(3 downto 0);
+ p_n_recv : in std_logic_vector(3 downto 0);
+ n_n_xmit : out std_logic_vector(3 downto 0);
+ p_n_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad O
+ n_o_recv : in std_logic_vector(3 downto 0);
+ p_o_recv : in std_logic_vector(3 downto 0);
+ n_o_xmit : out std_logic_vector(3 downto 0);
+ p_o_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad P
+ p_rt_r0_p : in std_logic;
+ n_rt_r0_p : in std_logic;
+ n_p_recv : in std_logic_vector(3 downto 0);
+ p_p_recv : in std_logic_vector(3 downto 0);
+ n_p_xmit : out std_logic_vector(3 downto 0);
+ p_p_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad A
+ n_a_recv : in std_logic_vector(3 downto 0);
+ p_a_recv : in std_logic_vector(3 downto 0);
+ n_a_xmit : out std_logic_vector(3 downto 0);
+ p_a_xmit : out std_logic_vector(3 downto 0);
+
+-- quad B
+ p_rt_r0_b : in std_logic;
+ n_rt_r0_b : in std_logic;
+ n_b_recv : in std_logic_vector(3 downto 0);
+ p_b_recv : in std_logic_vector(3 downto 0);
+ n_b_xmit : out std_logic_vector(3 downto 0);
+ p_b_xmit : out std_logic_vector(3 downto 0);
+
+-- quad C
+ n_c_recv : in std_logic_vector(3 downto 0);
+ p_c_recv : in std_logic_vector(3 downto 0);
+ n_c_xmit : out std_logic_vector(3 downto 0);
+ p_c_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad D
+ n_d_recv : in std_logic_vector(3 downto 0);
+ p_d_recv : in std_logic_vector(3 downto 0);
+ n_d_xmit : out std_logic_vector(3 downto 0);
+ p_d_xmit : out std_logic_vector(3 downto 0);
+
+-- quad E
+ p_rt_r0_e : in std_logic;
+ n_rt_r0_e : in std_logic;
+ n_e_recv : in std_logic_vector(3 downto 0);
+ p_e_recv : in std_logic_vector(3 downto 0);
+ n_e_xmit : out std_logic_vector(3 downto 0);
+ p_e_xmit : out std_logic_vector(3 downto 0);
+
+-- quad F
+ p_rt_r0_f : in std_logic;
+ n_rt_r0_f : in std_logic;
+ n_f_recv : in std_logic_vector(3 downto 0);
+ p_f_recv : in std_logic_vector(3 downto 0);
+ n_f_xmit : out std_logic_vector(3 downto 0);
+ p_f_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad H
+ n_h_recv : in std_logic_vector(3 downto 0);
+ p_h_recv : in std_logic_vector(3 downto 0);
+ n_h_xmit : out std_logic_vector(3 downto 0);
+ p_h_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad I
+ p_rt_r0_i : in std_logic;
+ n_rt_r0_i : in std_logic;
+ n_i_recv : in std_logic_vector(3 downto 0);
+ p_i_recv : in std_logic_vector(3 downto 0);
+ n_i_xmit : out std_logic_vector(3 downto 0);
+ p_i_xmit : out std_logic_vector(3 downto 0);
+
+ -- quad J
+ n_j_recv : in std_logic_vector(3 downto 0);
+ p_j_recv : in std_logic_vector(3 downto 0);
+ n_j_xmit : out std_logic_vector(3 downto 0);
+ p_j_xmit : out std_logic_vector(3 downto 0);
+
+
+ -- I2C pins
+ -- The "sysmon" port can be accessed before the FPGA is configured.
+ -- The "generic" port requires a configured FPGA with an I2C module. The information
+ -- that can be accessed on the generic port is user-defined.
+ --i2c_scl_f_generic : inout std_logic;
+ --i2c_sda_f_generic : inout std_logic;
+ i2c_scl_f_sysmon : inout std_logic;
+ i2c_sda_f_sysmon : inout std_logic
+ );
+ end entity top;
+
+ architecture structure of top is
+ signal clk_200_raw : std_logic;
+ signal clk_200 : std_logic;
+ signal clk_50 : std_logic;
+ signal reset : std_logic;
+ signal locked_clk200 : std_logic;
+
+ signal led_blue_local : slv_8_t;
+ signal led_red_local : slv_8_t;
+ signal led_green_local : slv_8_t;
+
+ constant localAXISlaves : integer := 4;
+ signal local_AXI_ReadMOSI : AXIReadMOSI_array_t(0 to localAXISlaves-1) := (others => DefaultAXIReadMOSI);
+ signal local_AXI_ReadMISO : AXIReadMISO_array_t(0 to localAXISlaves-1) := (others => DefaultAXIReadMISO);
+ signal local_AXI_WriteMOSI : AXIWriteMOSI_array_t(0 to localAXISlaves-1) := (others => DefaultAXIWriteMOSI);
+ signal local_AXI_WriteMISO : AXIWriteMISO_array_t(0 to localAXISlaves-1) := (others => DefaultAXIWriteMISO);
+
+ signal AXI_CLK : std_logic;
+ signal AXI_RST_N : std_logic;
+ signal AXI_RESET : std_logic;
+
+ signal ext_AXI_ReadMOSI : AXIReadMOSI_d64 := DefaultAXIReadMOSI_d64;
+ signal ext_AXI_ReadMISO : AXIReadMISO_d64 := DefaultAXIReadMISO_d64;
+ signal ext_AXI_WriteMOSI : AXIWriteMOSI_d64 := DefaultAXIWriteMOSI_d64;
+ signal ext_AXI_WriteMISO : AXIWriteMISO_d64 := DefaultAXIWriteMISO_d64;
+
+ signal C2C_Mon : C2C_INTF_MON_t;
+ signal C2C_Ctrl : C2C_INTF_Ctrl_t;
+
+ signal clk_F2_C2C_PHY_user : STD_logic_vector(1 downto 1);
+ signal BRAM_write : std_logic;
+ signal BRAM_addr : std_logic_vector(10 downto 0);
+ signal BRAM_WR_data : std_logic_vector(31 downto 0);
+ signal BRAM_RD_data : std_logic_vector(31 downto 0);
+
+ signal bram_rst_a : std_logic;
+ signal bram_clk_a : std_logic;
+ signal bram_en_a : std_logic;
+ signal bram_we_a : std_logic_vector(7 downto 0);
+ signal bram_addr_a : std_logic_vector(8 downto 0);
+ signal bram_wrdata_a : std_logic_vector(63 downto 0);
+ signal bram_rddata_a : std_logic_vector(63 downto 0);
+
+ signal AXI_BRAM_EN : std_logic;
+ signal AXI_BRAM_we : std_logic_vector(7 downto 0);
+ signal AXI_BRAM_addr :std_logic_vector(12 downto 0);
+ signal AXI_BRAM_DATA_IN : std_logic_vector(63 downto 0);
+ signal AXI_BRAM_DATA_OUT : std_logic_vector(63 downto 0);
+
+ signal pB_UART_tx : std_logic;
+ signal pB_UART_rx : std_logic;
+
+ signal myreg1_test_vector : std_logic_vector(31 downto 0);
+ signal heater_output : slv32_array_t(31 downto 0);
+
+ function and_reduce_array(a : slv32_array_t(31 downto 0)) return std_logic_vector is
+ variable ret : std_logic_vector(31 downto 0) := (others => '0');
+ begin
+ for i in a'range loop
+ ret := ret and a(i);
+ end loop;
+ return ret;
+ end function and_reduce_array;
+
+begin
+ -- connect 200 MHz to a clock wizard that outputs 200 MHz, 100 MHz, and 50 MHz
+ Local_Clocking_1: entity work.onboardclk
+ port map (
+ clk_200Mhz => clk_200,
+ clk_50Mhz => clk_50,
+ reset => '0',
+ locked => locked_clk200,
+ clk_in1_p => p_clk_200,
+ clk_in1_n => n_clk_200);
+ AXI_CLK <= clk_50;
+
+
+
+-- add differential clock buffers to all the incoming clocks
+--wire lf_x12_r0_clk;
+--IBUFDS lf_x12_r0_clk_buf(.O(lf_x12_r0_clk), .I(p_lf_x12_r0_clk), .IB(n_lf_x12_r0_clk) );
+--wire lf_x4_r0_clk;
+--IBUFDS lf_x4_r0_clk_buf(.O(lf_x4_r0_clk), .I(p_lf_x4_r0_clk), .IB(n_lf_x4_r0_clk) );
+--wire rt_x12_r0_clk;
+--IBUFDS rt_x12_r0_clk_buf(.O(rt_x12_r0_clk), .I(p_rt_x12_r0_clk), .IB(n_rt_x12_r0_clk) );
+--wire rt_x4_r0_clk;
+--IBUFDS rt_x4_r0_clk_buf(.O(rt_x4_r0_clk), .I(p_rt_x4_r0_clk), .IB(n_rt_x4_r0_clk) );
+--wire tcds40_clk; -- 40 MHz LHC clock
+--IBUFDS tcds40_clk_buf(.O(tcds40_clk), .I(p_tcds40_clk), .IB(n_tcds40_clk) );
+
+-- add differential output buffer to TCDS recovered clock
+--wire tcds_recov_clk;
+--OBUFDS(.I(tcds_recov_clk), .O(p_tcds_recov_clk), .OB(n_tcds_recov_clk));
+---- dummy connection to tcds_recov_clk
+--assign tcds_recov_clk = tcds40_clk;
+
+-- add a free running counter to divide the clock
+--reg [27:0] divider;
+--always @(posedge clk_200) begin
+-- divider[27:0] <= divider[27:0] + 1;
+--end
+
+--assign led_f1_red = divider[27];
+--assign led_f1_green = divider[26];
+--assign led_f1_blue = divider[25];
+--assign led_f2_red = divider[27];
+--assign led_f2_green = divider[26];
+--assign led_f2_blue = divider[25];
+
+---- create 3 differential buffers for spare inputs
+--genvar chan;
+--wire [2:0] in_spare;
+--generate
+-- for (chan=0; chan < 3; chan=chan+1)
+-- begin: gen_in_spare_buf
+-- IBUFDS in_spare_buf(.O(in_spare[chan]), .I(p_in_spare[chan]), .IB(n_in_spare[chan]) );
+-- end
+--endgenerate
+
+---- create 3 differential buffers for spare outputs
+--reg [2:0] out_spare;
+--generate
+-- for (chan=0; chan < 3; chan=chan+1)
+-- begin: gen_out_spare_buf
+-- OBUFDS out_spare_buf(.I(out_spare[chan]), .O(p_out_spare[chan]), .OB(n_out_spare[chan]) );
+-- end
+--endgenerate
+
+-- loop the spare in to the spare out
+--always @(posedge clk_200) begin
+-- out_spare[2:0] <= in_spare[2:0];
+--end
+
+---- create differential buffers to loop the test_conn signals
+--wire test_conn_clk;
+--IBUFDS test_conn_clk_buf(.O(test_conn_clk), .I(p_test_conn_0), .IB(n_test_conn_0) );
+--wire test_conn_3, test_conn_4;
+--IBUFDS test_conn_4_buf(.O(test_conn_4), .I(p_test_conn_4), .IB(n_test_conn_4));
+--IBUFDS test_conn_3_buf(.O(test_conn_3), .I(p_test_conn_3), .IB(n_test_conn_3));
+--reg test_conn_out_2, test_conn_out_1;
+--OBUFDS test_conn_out_2_buf(.I(test_conn_out_2), .O(p_test_conn_2), .OB(n_test_conn_2));
+--OBUFDS test_conn_out_1_buf(.I(test_conn_out_1), .O(p_test_conn_1), .OB(n_test_conn_1));
+
+---- loop test_conn 'in' to 'out' using 'clk'
+--always @(posedge test_conn_clk) begin
+-- test_conn_out_2 <= test_conn_4;
+-- test_conn_out_1 <= test_conn_3;
+-- test_conn_5 <= test_conn_6;
+--end
+
+---- create differential buffers to loop the 'hdr' signals
+--wire hdr_clk;
+--IBUFDS hdr_clk_buf(.O(hdr_clk), .I(hdr1), .IB(hdr2) );
+
+---- loop hdr 'in' to 'out' using 'clk'
+--always @(posedge hdr_clk) begin
+-- hdr7 <= hdr3;
+-- hdr8 <= hdr4;
+-- hdr9 <= hdr5;
+-- hdr10 <= hdr6;
+--end
+
+---- create tri-state buffers for generic I2C scl and sda
+--wire i2c_scl_generic_out, i2c_scl_generic_tri, i2c_scl_generic_in;
+--generic_scl: IOBUF
+-- port map (
+-- clk_200 => clk_200,
+-- I => i2c_scl_generic_out,
+-- T => i2c_scl_generic_tri,
+-- O => i2c_scl_generic_in,
+-- IO => i2c_scl_f_generic
+-- );
+--wire i2c_sda_generic_out, i2c_sda_generic_tri, i2c_sda_generic_in;
+--IOBUF generic_sda(.I(i2c_sda_generic_out),.T(i2c_sda_generic_tri), .O(i2c_sda_generic_in), .IO(i2c_sda_f_generic));
+
+--wire i2c_scl_sysmon_out, i2c_scl_sysmon_tri, i2c_scl_sysmon_in;
+--IOBUF sysmon_scl(.I(i2c_scl_sysmon_out),.T(i2c_scl_sysmon_tri), .O(i2c_scl_sysmon_in), .IO(i2c_scl_f_sysmon));
+--wire i2c_sda_sysmon_out, i2c_sda_sysmon_tri, i2c_sda_sysmon_in;
+--IOBUF sysmon_sda(.I(i2c_sda_sysmon_out),.T(i2c_sda_sysmon_tri), .O(i2c_sda_sysmon_in), .IO(i2c_sda_f_sysmon));
+
+---- create dummy logic to use remaining inputs and outputs
+--always @(posedge clk_200) begin
+-- f_to_mcu <= mcu_to_f & fpga_identity;
+--end
+
+-- add a ffx4 block to use 1 quad (quad AF = FF4)
+--BD_FFx4 FFx4_AF (
+-- .init_clk(clk_50),
+-- .refclk_n(n_lf_r0_af),
+-- .refclk_p(p_lf_r0_af),
+-- .rx_n({n_ff4_recv[0],n_ff4_recv[1],n_ff4_recv[2],n_ff4_recv[3]}),
+-- .rx_p({p_ff4_recv[0],p_ff4_recv[1],p_ff4_recv[2],p_ff4_recv[3]}),
+-- .tx_n({n_ff4_xmit[0],n_ff4_xmit[1],n_ff4_xmit[2],n_ff4_xmit[3]}),
+-- .tx_p({p_ff4_xmit[0],p_ff4_xmit[1],p_ff4_xmit[2],p_ff4_xmit[3]})
+--);
+
+---- add a ffx4 block to use 1 quad (quad U = FF6)
+--FFx4_U FFx4_U (
+-- .init_clk(clk_200),
+-- .refclk_n(n_lf_r0_u),
+-- .refclk_p(p_lf_r0_u),
+-- .rx_n({n_ff6_recv[0],n_ff6_recv[1],n_ff6_recv[2],n_ff6_recv[3]}),
+-- .rx_p({p_ff6_recv[0],p_ff6_recv[1],p_ff6_recv[2],p_ff6_recv[3]}),
+-- .tx_n({n_ff6_xmit[0],n_ff6_xmit[1],n_ff6_xmit[2],n_ff6_xmit[3]}),
+-- .tx_p({p_ff6_xmit[0],p_ff6_xmit[1],p_ff6_xmit[2],p_ff6_xmit[3]})
+--);
+
+-- add a ffx12 block to use 3 quads (quad AC,AD,AE = FF1)
+--BD_FFx12 FFx12_AD (
+-- .init_clk(clk_50),
+-- .refclk_n(n_lf_r0_ad),
+-- .refclk_p(p_lf_r0_ad),
+-- .rx_n({n_ff1_recv[11],n_ff1_recv[10],n_ff1_recv[9],n_ff1_recv[8],n_ff1_recv[7],n_ff1_recv[6],n_ff1_recv[5],n_ff1_recv[4],n_ff1_recv[3],n_ff1_recv[2],n_ff1_recv[1],n_ff1_recv[0]}),
+-- .rx_p({p_ff1_recv[11],p_ff1_recv[10],p_ff1_recv[9],p_ff1_recv[8],p_ff1_recv[7],p_ff1_recv[6],p_ff1_recv[5],p_ff1_recv[4],p_ff1_recv[3],p_ff1_recv[2],p_ff1_recv[1],p_ff1_recv[0]}),
+-- .tx_n({n_ff1_xmit[11],n_ff1_xmit[10],n_ff1_xmit[9],n_ff1_xmit[8],n_ff1_xmit[7],n_ff1_xmit[6],n_ff1_xmit[5],n_ff1_xmit[4],n_ff1_xmit[3],n_ff1_xmit[2],n_ff1_xmit[1],n_ff1_xmit[0]}),
+-- .tx_p({p_ff1_xmit[11],p_ff1_xmit[10],p_ff1_xmit[9],p_ff1_xmit[8],p_ff1_xmit[7],p_ff1_xmit[6],p_ff1_xmit[5],p_ff1_xmit[4],p_ff1_xmit[3],p_ff1_xmit[2],p_ff1_xmit[1],p_ff1_xmit[0]})
+--);
+
+ c2csslave_wrapper_1: entity work.c2cslave_wrapper
+ port map (
+ AXI_CLK => AXI_CLK,
+ AXI_RST_N(0) => AXI_RST_N,
+ CM1_PB_UART_rxd => pB_UART_tx,
+ CM1_PB_UART_txd => pB_UART_rx,
+ F2_C2C_phy_Rx_rxn => n_mgt_sm_to_f(1 downto 1),
+ F2_C2C_phy_Rx_rxp => p_mgt_sm_to_f(1 downto 1),
+ F2_C2C_phy_Tx_txn => n_mgt_f_to_sm(1 downto 1),
+ F2_C2C_phy_Tx_txp => p_mgt_f_to_sm(1 downto 1),
+ F2_C2CB_phy_Rx_rxn => n_mgt_sm_to_f(2 downto 2),
+ F2_C2CB_phy_Rx_rxp => p_mgt_sm_to_f(2 downto 2),
+ F2_C2CB_phy_Tx_txn => n_mgt_f_to_sm(2 downto 2),
+ F2_C2CB_phy_Tx_txp => p_mgt_f_to_sm(2 downto 2),
+ F2_C2C_phy_refclk_clk_n => n_rt_r0_l,
+ F2_C2C_phy_refclk_clk_p => p_rt_r0_l,
+ clk50Mhz => clk_50,
+
+ F2_IO_araddr => local_AXI_ReadMOSI(0).address,
+ F2_IO_arprot => local_AXI_ReadMOSI(0).protection_type,
+ F2_IO_arready => local_AXI_ReadMISO(0).ready_for_address,
+ F2_IO_arvalid => local_AXI_ReadMOSI(0).address_valid,
+ F2_IO_awaddr => local_AXI_WriteMOSI(0).address,
+ F2_IO_awprot => local_AXI_WriteMOSI(0).protection_type,
+ F2_IO_awready => local_AXI_WriteMISO(0).ready_for_address,
+ F2_IO_awvalid => local_AXI_WriteMOSI(0).address_valid,
+ F2_IO_bready => local_AXI_WriteMOSI(0).ready_for_response,
+ F2_IO_bresp => local_AXI_WriteMISO(0).response,
+ F2_IO_bvalid => local_AXI_WriteMISO(0).response_valid,
+ F2_IO_rdata => local_AXI_ReadMISO(0).data,
+ F2_IO_rready => local_AXI_ReadMOSI(0).ready_for_data,
+ F2_IO_rresp => local_AXI_ReadMISO(0).response,
+ F2_IO_rvalid => local_AXI_ReadMISO(0).data_valid,
+ F2_IO_wdata => local_AXI_WriteMOSI(0).data,
+ F2_IO_wready => local_AXI_WriteMISO(0).ready_for_data,
+ F2_IO_wstrb => local_AXI_WriteMOSI(0).data_write_strobe,
+ F2_IO_wvalid => local_AXI_WriteMOSI(0).data_valid,
+
+
+ F2_C2C_INTF_araddr => local_AXI_ReadMOSI(2).address,
+ F2_C2C_INTF_arprot => local_AXI_ReadMOSI(2).protection_type,
+ F2_C2C_INTF_arready => local_AXI_ReadMISO(2).ready_for_address,
+ F2_C2C_INTF_arvalid => local_AXI_ReadMOSI(2).address_valid,
+ F2_C2C_INTF_awaddr => local_AXI_WriteMOSI(2).address,
+ F2_C2C_INTF_awprot => local_AXI_WriteMOSI(2).protection_type,
+ F2_C2C_INTF_awready => local_AXI_WriteMISO(2).ready_for_address,
+ F2_C2C_INTF_awvalid => local_AXI_WriteMOSI(2).address_valid,
+ F2_C2C_INTF_bready => local_AXI_WriteMOSI(2).ready_for_response,
+ F2_C2C_INTF_bresp => local_AXI_WriteMISO(2).response,
+ F2_C2C_INTF_bvalid => local_AXI_WriteMISO(2).response_valid,
+ F2_C2C_INTF_rdata => local_AXI_ReadMISO(2).data,
+ F2_C2C_INTF_rready => local_AXI_ReadMOSI(2).ready_for_data,
+ F2_C2C_INTF_rresp => local_AXI_ReadMISO(2).response,
+ F2_C2C_INTF_rvalid => local_AXI_ReadMISO(2).data_valid,
+ F2_C2C_INTF_wdata => local_AXI_WriteMOSI(2).data,
+ F2_C2C_INTF_wready => local_AXI_WriteMISO(2).ready_for_data,
+ F2_C2C_INTF_wstrb => local_AXI_WriteMOSI(2).data_write_strobe,
+ F2_C2C_INTF_wvalid => local_AXI_WriteMOSI(2).data_valid,
+
+
+ F2_CM_FW_INFO_araddr => local_AXI_ReadMOSI(1).address,
+ F2_CM_FW_INFO_arprot => local_AXI_ReadMOSI(1).protection_type,
+ F2_CM_FW_INFO_arready => local_AXI_ReadMISO(1).ready_for_address,
+ F2_CM_FW_INFO_arvalid => local_AXI_ReadMOSI(1).address_valid,
+ F2_CM_FW_INFO_awaddr => local_AXI_WriteMOSI(1).address,
+ F2_CM_FW_INFO_awprot => local_AXI_WriteMOSI(1).protection_type,
+ F2_CM_FW_INFO_awready => local_AXI_WriteMISO(1).ready_for_address,
+ F2_CM_FW_INFO_awvalid => local_AXI_WriteMOSI(1).address_valid,
+ F2_CM_FW_INFO_bready => local_AXI_WriteMOSI(1).ready_for_response,
+ F2_CM_FW_INFO_bresp => local_AXI_WriteMISO(1).response,
+ F2_CM_FW_INFO_bvalid => local_AXI_WriteMISO(1).response_valid,
+ F2_CM_FW_INFO_rdata => local_AXI_ReadMISO(1).data,
+ F2_CM_FW_INFO_rready => local_AXI_ReadMOSI(1).ready_for_data,
+ F2_CM_FW_INFO_rresp => local_AXI_ReadMISO(1).response,
+ F2_CM_FW_INFO_rvalid => local_AXI_ReadMISO(1).data_valid,
+ F2_CM_FW_INFO_wdata => local_AXI_WriteMOSI(1).data,
+ F2_CM_FW_INFO_wready => local_AXI_WriteMISO(1).ready_for_data,
+ F2_CM_FW_INFO_wstrb => local_AXI_WriteMOSI(1).data_write_strobe,
+ F2_CM_FW_INFO_wvalid => local_AXI_WriteMOSI(1).data_valid,
+
+
+ F2_IPBUS_araddr => ext_AXI_ReadMOSI.address,
+ F2_IPBUS_arburst => ext_AXI_ReadMOSI.burst_type,
+ F2_IPBUS_arcache => ext_AXI_ReadMOSI.cache_type,
+ F2_IPBUS_arlen => ext_AXI_ReadMOSI.burst_length,
+ F2_IPBUS_arlock(0) => ext_AXI_ReadMOSI.lock_type,
+ F2_IPBUS_arprot => ext_AXI_ReadMOSI.protection_type,
+ F2_IPBUS_arqos => ext_AXI_ReadMOSI.qos,
+ F2_IPBUS_arready(0) => ext_AXI_ReadMISO.ready_for_address,
+ F2_IPBUS_arregion => ext_AXI_ReadMOSI.region,
+ F2_IPBUS_arsize => ext_AXI_ReadMOSI.burst_size,
+ F2_IPBUS_arvalid(0) => ext_AXI_ReadMOSI.address_valid,
+ F2_IPBUS_awaddr => ext_AXI_WriteMOSI.address,
+ F2_IPBUS_awburst => ext_AXI_WriteMOSI.burst_type,
+ F2_IPBUS_awcache => ext_AXI_WriteMOSI.cache_type,
+ F2_IPBUS_awlen => ext_AXI_WriteMOSI.burst_length,
+ F2_IPBUS_awlock(0) => ext_AXI_WriteMOSI.lock_type,
+ F2_IPBUS_awprot => ext_AXI_WriteMOSI.protection_type,
+ F2_IPBUS_awqos => ext_AXI_WriteMOSI.qos,
+ F2_IPBUS_awready(0) => ext_AXI_WriteMISO.ready_for_address,
+ F2_IPBUS_awregion => ext_AXI_WriteMOSI.region,
+ F2_IPBUS_awsize => ext_AXI_WriteMOSI.burst_size,
+ F2_IPBUS_awvalid(0) => ext_AXI_WriteMOSI.address_valid,
+ F2_IPBUS_bready(0) => ext_AXI_WriteMOSI.ready_for_response,
+ F2_IPBUS_bresp => ext_AXI_WriteMISO.response,
+ F2_IPBUS_bvalid(0) => ext_AXI_WriteMISO.response_valid,
+ F2_IPBUS_rdata => ext_AXI_ReadMISO.data,
+ F2_IPBUS_rlast(0) => ext_AXI_ReadMISO.last,
+ F2_IPBUS_rready(0) => ext_AXI_ReadMOSI.ready_for_data,
+ F2_IPBUS_rresp => ext_AXI_ReadMISO.response,
+ F2_IPBUS_rvalid(0) => ext_AXI_ReadMISO.data_valid,
+ F2_IPBUS_wdata => ext_AXI_WriteMOSI.data,
+ F2_IPBUS_wlast(0) => ext_AXI_WriteMOSI.last,
+ F2_IPBUS_wready(0) => ext_AXI_WriteMISO.ready_for_data,
+ F2_IPBUS_wstrb => ext_AXI_WriteMOSI.data_write_strobe,
+ F2_IPBUS_wvalid(0) => ext_AXI_WriteMOSI.data_valid,
+ reset_n => locked_clk200,--reset,
+
+ F2_C2C_PHY_DEBUG_cplllock(0) => C2C_Mon.C2C(1).DEBUG.CPLL_LOCK,
+ F2_C2C_PHY_DEBUG_dmonitorout => C2C_Mon.C2C(1).DEBUG.DMONITOR,
+ F2_C2C_PHY_DEBUG_eyescandataerror(0) => C2C_Mon.C2C(1).DEBUG.EYESCAN_DATA_ERROR,
+
+ F2_C2C_PHY_DEBUG_eyescanreset(0) => C2C_Ctrl.C2C(1).DEBUG.EYESCAN_RESET,
+ F2_C2C_PHY_DEBUG_eyescantrigger(0) => C2C_Ctrl.C2C(1).DEBUG.EYESCAN_TRIGGER,
+ F2_C2C_PHY_DEBUG_pcsrsvdin => C2C_Ctrl.C2C(1).DEBUG.PCS_RSV_DIN,
+ F2_C2C_PHY_DEBUG_qplllock(0) => C2C_Mon.C2C(1).DEBUG.QPLL_LOCK,
+ F2_C2C_PHY_DEBUG_rxbufreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.BUF_RESET,
+ F2_C2C_PHY_DEBUG_rxbufstatus => C2C_Mon.C2C(1).DEBUG.RX.BUF_STATUS,
+ F2_C2C_PHY_DEBUG_rxcdrhold(0) => C2C_Ctrl.C2C(1).DEBUG.RX.CDR_HOLD,
+ F2_C2C_PHY_DEBUG_rxdfelpmreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.DFE_LPM_RESET,
+ F2_C2C_PHY_DEBUG_rxlpmen(0) => C2C_Ctrl.C2C(1).DEBUG.RX.LPM_EN,
+ F2_C2C_PHY_DEBUG_rxpcsreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PCS_RESET,
+ F2_C2C_PHY_DEBUG_rxpmareset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PMA_RESET,
+ F2_C2C_PHY_DEBUG_rxpmaresetdone(0) => C2C_Mon.C2C(1).DEBUG.RX.PMA_RESET_DONE,
+ F2_C2C_PHY_DEBUG_rxprbscntreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PRBS_CNT_RST,
+ F2_C2C_PHY_DEBUG_rxprbserr(0) => C2C_Mon.C2C(1).DEBUG.RX.PRBS_ERR,
+ F2_C2C_PHY_DEBUG_rxprbssel => C2C_Ctrl.C2C(1).DEBUG.RX.PRBS_SEL,
+ F2_C2C_PHY_DEBUG_rxrate => C2C_Ctrl.C2C(1).DEBUG.RX.RATE,
+ F2_C2C_PHY_DEBUG_rxresetdone(0) => C2C_Mon.C2C(1).DEBUG.RX.RESET_DONE,
+ F2_C2C_PHY_DEBUG_txbufstatus => C2C_Mon.C2C(1).DEBUG.TX.BUF_STATUS,
+ F2_C2C_PHY_DEBUG_txdiffctrl => C2C_Ctrl.C2C(1).DEBUG.TX.DIFF_CTRL,
+ F2_C2C_PHY_DEBUG_txinhibit(0) => C2C_Ctrl.C2C(1).DEBUG.TX.INHIBIT,
+ F2_C2C_PHY_DEBUG_txpcsreset(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PCS_RESET,
+ F2_C2C_PHY_DEBUG_txpmareset(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PMA_RESET,
+ F2_C2C_PHY_DEBUG_txpolarity(0) => C2C_Ctrl.C2C(1).DEBUG.TX.POLARITY,
+ F2_C2C_PHY_DEBUG_txpostcursor => C2C_Ctrl.C2C(1).DEBUG.TX.POST_CURSOR,
+ F2_C2C_PHY_DEBUG_txprbsforceerr(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PRBS_FORCE_ERR,
+ F2_C2C_PHY_DEBUG_txprbssel => C2C_Ctrl.C2C(1).DEBUG.TX.PRBS_SEL,
+ F2_C2C_PHY_DEBUG_txprecursor => C2C_Ctrl.C2C(1).DEBUG.TX.PRE_CURSOR,
+ F2_C2C_PHY_DEBUG_txresetdone(0) => C2C_MON.C2C(1).DEBUG.TX.RESET_DONE,
+
+ F2_C2C_PHY_channel_up => C2C_Mon.C2C(1).STATUS.CHANNEL_UP,
+ F2_C2C_PHY_gt_pll_lock => C2C_MON.C2C(1).STATUS.PHY_GT_PLL_LOCK,
+ F2_C2C_PHY_hard_err => C2C_Mon.C2C(1).STATUS.PHY_HARD_ERR,
+ F2_C2C_PHY_lane_up => C2C_Mon.C2C(1).STATUS.PHY_LANE_UP(0 downto 0),
+ F2_C2C_PHY_mmcm_not_locked_out => C2C_Mon.C2C(1).STATUS.PHY_MMCM_LOL,
+ F2_C2C_PHY_soft_err => C2C_Mon.C2C(1).STATUS.PHY_SOFT_ERR,
+
+ F2_C2C_aurora_do_cc => C2C_Mon.C2C(1).STATUS.DO_CC,
+ F2_C2C_aurora_pma_init_in => C2C_Ctrl.C2C(1).STATUS.INITIALIZE,
+ F2_C2C_axi_c2c_config_error_out => C2C_Mon.C2C(1).STATUS.CONFIG_ERROR,
+ F2_C2C_axi_c2c_link_status_out => C2C_MON.C2C(1).STATUS.LINK_GOOD,
+ F2_C2C_axi_c2c_multi_bit_error_out => C2C_MON.C2C(1).STATUS.MB_ERROR,
+ F2_C2C_phy_power_down => '0',
+ F2_C2C_PHY_clk => clk_F2_C2C_PHY_user(1),
+ F2_C2C_PHY_DRP_daddr => C2C_Ctrl.C2C(1).DRP.address,
+ F2_C2C_PHY_DRP_den => C2C_Ctrl.C2C(1).DRP.enable,
+ F2_C2C_PHY_DRP_di => C2C_Ctrl.C2C(1).DRP.wr_data,
+ F2_C2C_PHY_DRP_do => C2C_MON.C2C(1).DRP.rd_data,
+ F2_C2C_PHY_DRP_drdy => C2C_MON.C2C(1).DRP.rd_data_valid,
+ F2_C2C_PHY_DRP_dwe => C2C_Ctrl.C2C(1).DRP.wr_enable,
+
+ F2_C2CB_PHY_DEBUG_cplllock(0) => C2C_Mon.C2C(2).DEBUG.CPLL_LOCK,
+ F2_C2CB_PHY_DEBUG_dmonitorout => C2C_Mon.C2C(2).DEBUG.DMONITOR,
+ F2_C2CB_PHY_DEBUG_eyescandataerror(0) => C2C_Mon.C2C(2).DEBUG.EYESCAN_DATA_ERROR,
+
+ F2_C2CB_PHY_DEBUG_eyescanreset(0) => C2C_Ctrl.C2C(2).DEBUG.EYESCAN_RESET,
+ F2_C2CB_PHY_DEBUG_eyescantrigger(0) => C2C_Ctrl.C2C(2).DEBUG.EYESCAN_TRIGGER,
+ F2_C2CB_PHY_DEBUG_pcsrsvdin => C2C_Ctrl.C2C(2).DEBUG.PCS_RSV_DIN,
+ F2_C2CB_PHY_DEBUG_qplllock(0) => C2C_Mon.C2C(2).DEBUG.QPLL_LOCK,
+ F2_C2CB_PHY_DEBUG_rxbufreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.BUF_RESET,
+ F2_C2CB_PHY_DEBUG_rxbufstatus => C2C_Mon.C2C(2).DEBUG.RX.BUF_STATUS,
+ F2_C2CB_PHY_DEBUG_rxcdrhold(0) => C2C_Ctrl.C2C(2).DEBUG.RX.CDR_HOLD,
+ F2_C2CB_PHY_DEBUG_rxdfelpmreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.DFE_LPM_RESET,
+ F2_C2CB_PHY_DEBUG_rxlpmen(0) => C2C_Ctrl.C2C(2).DEBUG.RX.LPM_EN,
+ F2_C2CB_PHY_DEBUG_rxpcsreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PCS_RESET,
+ F2_C2CB_PHY_DEBUG_rxpmareset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PMA_RESET,
+ F2_C2CB_PHY_DEBUG_rxpmaresetdone(0) => C2C_Mon.C2C(2).DEBUG.RX.PMA_RESET_DONE,
+ F2_C2CB_PHY_DEBUG_rxprbscntreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PRBS_CNT_RST,
+ F2_C2CB_PHY_DEBUG_rxprbserr(0) => C2C_Mon.C2C(2).DEBUG.RX.PRBS_ERR,
+ F2_C2CB_PHY_DEBUG_rxprbssel => C2C_Ctrl.C2C(2).DEBUG.RX.PRBS_SEL,
+ F2_C2CB_PHY_DEBUG_rxrate => C2C_Ctrl.C2C(2).DEBUG.RX.RATE,
+ F2_C2CB_PHY_DEBUG_rxresetdone(0) => C2C_Mon.C2C(2).DEBUG.RX.RESET_DONE,
+ F2_C2CB_PHY_DEBUG_txbufstatus => C2C_Mon.C2C(2).DEBUG.TX.BUF_STATUS,
+ F2_C2CB_PHY_DEBUG_txdiffctrl => C2C_Ctrl.C2C(2).DEBUG.TX.DIFF_CTRL,
+ F2_C2CB_PHY_DEBUG_txinhibit(0) => C2C_Ctrl.C2C(2).DEBUG.TX.INHIBIT,
+ F2_C2CB_PHY_DEBUG_txpcsreset(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PCS_RESET,
+ F2_C2CB_PHY_DEBUG_txpmareset(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PMA_RESET,
+ F2_C2CB_PHY_DEBUG_txpolarity(0) => C2C_Ctrl.C2C(2).DEBUG.TX.POLARITY,
+ F2_C2CB_PHY_DEBUG_txpostcursor => C2C_Ctrl.C2C(2).DEBUG.TX.POST_CURSOR,
+ F2_C2CB_PHY_DEBUG_txprbsforceerr(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PRBS_FORCE_ERR,
+ F2_C2CB_PHY_DEBUG_txprbssel => C2C_Ctrl.C2C(2).DEBUG.TX.PRBS_SEL,
+ F2_C2CB_PHY_DEBUG_txprecursor => C2C_Ctrl.C2C(2).DEBUG.TX.PRE_CURSOR,
+ F2_C2CB_PHY_DEBUG_txresetdone(0) => C2C_MON.C2C(2).DEBUG.TX.RESET_DONE,
+
+ F2_C2CB_PHY_channel_up => C2C_Mon.C2C(2).STATUS.CHANNEL_UP,
+ F2_C2CB_PHY_gt_pll_lock => C2C_MON.C2C(2).STATUS.PHY_GT_PLL_LOCK,
+ F2_C2CB_PHY_hard_err => C2C_Mon.C2C(2).STATUS.PHY_HARD_ERR,
+ F2_C2CB_PHY_lane_up => C2C_Mon.C2C(2).STATUS.PHY_LANE_UP(0 downto 0),
+ -- F2_C2CB_PHY_mmcm_not_locked => C2C_Mon.C2C(2).STATUS.PHY_MMCM_LOL,
+ F2_C2CB_PHY_soft_err => C2C_Mon.C2C(2).STATUS.PHY_SOFT_ERR,
+
+ F2_C2CB_aurora_do_cc => C2C_Mon.C2C(2).STATUS.DO_CC,
+ F2_C2CB_aurora_pma_init_in => C2C_Ctrl.C2C(2).STATUS.INITIALIZE,
+ F2_C2CB_axi_c2c_config_error_out => C2C_Mon.C2C(2).STATUS.CONFIG_ERROR,
+ F2_C2CB_axi_c2c_link_status_out => C2C_MON.C2C(2).STATUS.LINK_GOOD,
+ F2_C2CB_axi_c2c_multi_bit_error_out => C2C_MON.C2C(2).STATUS.MB_ERROR,
+ F2_C2CB_phy_power_down => '0',
+ -- F2_C2CB_PHY_user_clk_out => clk_F2_C2CB_PHY_user,
+ F2_C2CB_PHY_DRP_daddr => C2C_Ctrl.C2C(2).DRP.address,
+ F2_C2CB_PHY_DRP_den => C2C_Ctrl.C2C(2).DRP.enable,
+ F2_C2CB_PHY_DRP_di => C2C_Ctrl.C2C(2).DRP.wr_data,
+ F2_C2CB_PHY_DRP_do => C2C_MON.C2C(2).DRP.rd_data,
+ F2_C2CB_PHY_DRP_drdy => C2C_MON.C2C(2).DRP.rd_data_valid,
+ F2_C2CB_PHY_DRP_dwe => C2C_Ctrl.C2C(2).DRP.wr_enable,
+
+ F2_SYS_MGMT_sda =>i2c_sda_f_sysmon,
+ F2_SYS_MGMT_scl =>i2c_scl_f_sysmon
+
+);
+
+ c2c_ok <= C2C_Mon.C2C(1).STATUS.LINK_GOOD;
+
+ RGB_pwm_1: entity work.RGB_pwm
+ generic map (
+ CLKFREQ => 200000000,
+ RGBFREQ => 1000)
+ port map (
+ clk => clk_200,
+ --redcount => led_red_local,
+ --greencount => led_green_local,
+ --bluecount => led_blue_local,
+ redcount => myreg1_test_vector( 7 downto 0),
+ greencount => myreg1_test_vector(15 downto 8),
+ bluecount => myreg1_test_vector(23 downto 16),
+
+ LEDred => led_f2_red,
+ LEDgreen => led_f2_green,
+ LEDblue => led_f2_blue);
+
+ myreg1_test_vector <= and_reduce_array(heater_output);
+
+ rate_counter_1: entity work.rate_counter
+ generic map (
+ CLK_A_1_SECOND => 2000000)
+ port map (
+ clk_A => clk_200,
+ clk_B => clk_F2_C2C_PHY_user(1),
+ reset_A_async => AXI_RESET,
+ event_b => '1',
+ rate => C2C_Mon.C2C(1).USER_FREQ);
+ C2C_Mon.C2C(2).USER_FREQ <= C2C_Mon.C2C(1).USER_FREQ;
+
+
+ F1_IO_interface_1: entity work.IO_map
+ generic map(
+ ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F2_IO)
+ )
+ port map (
+ clk_axi => AXI_CLK,
+ reset_axi_n => AXI_RST_N,
+ slave_readMOSI => local_AXI_readMOSI(0),
+ slave_readMISO => local_AXI_readMISO(0),
+ slave_writeMOSI => local_AXI_writeMOSI(0),
+ slave_writeMISO => local_AXI_writeMISO(0),
+ Mon.CLK_200_LOCKED => locked_clk200,
+ Mon.BRAM.RD_DATA => BRAM_RD_DATA,
+ Ctrl.RGB.R => led_red_local,
+ Ctrl.RGB.G => led_green_local,
+ Ctrl.RGB.B => led_blue_local,
+ Ctrl.BRAM.WRITE => BRAM_WRITE,
+ Ctrl.BRAM.ADDR(10 downto 0) => BRAM_ADDR,
+ Ctrl.BRAM.ADDR(14 downto 11) => open,
+ Ctrl.BRAM.WR_DATA => BRAM_WR_DATA
+ );
+
+ --CM_F1_info_1: entity work.CM_FW_info
+ -- generic map (
+ -- ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F2_CM_FW_INFO)
+ -- )
+ -- port map (
+ -- clk_axi => AXI_CLK,
+ -- reset_axi_n => AXI_RST_N,
+ -- readMOSI => local_AXI_ReadMOSI(1),
+ -- readMISO => local_AXI_ReadMISO(1),
+ -- writeMOSI => local_AXI_WriteMOSI(1),
+ -- writeMISO => local_AXI_WriteMISO(1));
+
+ C2C_INTF_1: entity work.C2C_INTF
+ generic map (
+ ERROR_WAIT_TIME => 90000000,
+ ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F2_C2C_INTF)
+ )
+ port map (
+ clk_axi => AXI_CLK,
+ reset_axi_n => AXI_RST_N,
+ readMOSI => local_AXI_readMOSI(2),
+ readMISO => local_AXI_readMISO(2),
+ writeMOSI => local_AXI_writeMOSI(2),
+ writeMISO => local_AXI_writeMISO(2),
+ clk_C2C(1) => clk_F2_C2C_PHY_user(1),
+ clk_C2C(2) => clk_F2_C2C_PHY_user(1),
+ UART_Rx => pb_UART_Rx,
+ UART_Tx => pb_UART_Tx,
+ Mon => C2C_Mon,
+ Ctrl => C2C_Ctrl);
+
+
+ AXI_RESET <= not AXI_RST_N;
+
+ AXI_BRAM_1: entity work.AXI_BRAM
+ port map (
+ s_axi_aclk => AXI_CLK,
+ s_axi_aresetn => AXI_RST_N,
+ s_axi_araddr => ext_AXI_ReadMOSI.address(12 downto 0),
+ s_axi_arburst => ext_AXI_ReadMOSI.burst_type,
+ s_axi_arcache => ext_AXI_ReadMOSI.cache_type,
+ s_axi_arlen => ext_AXI_ReadMOSI.burst_length,
+ s_axi_arlock => ext_AXI_ReadMOSI.lock_type,
+ s_axi_arprot => ext_AXI_ReadMOSI.protection_type,
+ -- s_axi_arqos => ext_AXI_ReadMOSI.qos,
+ s_axi_arready => ext_AXI_ReadMISO.ready_for_address,
+ -- s_axi_arregion => ext_AXI_ReadMOSI.region,
+ s_axi_arsize => ext_AXI_ReadMOSI.burst_size,
+ s_axi_arvalid => ext_AXI_ReadMOSI.address_valid,
+ s_axi_awaddr => ext_AXI_WriteMOSI.address(12 downto 0),
+ s_axi_awburst => ext_AXI_WriteMOSI.burst_type,
+ s_axi_awcache => ext_AXI_WriteMOSI.cache_type,
+ s_axi_awlen => ext_AXI_WriteMOSI.burst_length,
+ s_axi_awlock => ext_AXI_WriteMOSI.lock_type,
+ s_axi_awprot => ext_AXI_WriteMOSI.protection_type,
+ -- s_axi_awqos => ext_AXI_WriteMOSI.qos,
+ s_axi_awready => ext_AXI_WriteMISO.ready_for_address,
+ -- s_axi_awregion => ext_AXI_WriteMOSI.region,
+ s_axi_awsize => ext_AXI_WriteMOSI.burst_size,
+ s_axi_awvalid => ext_AXI_WriteMOSI.address_valid,
+ s_axi_bready => ext_AXI_WriteMOSI.ready_for_response,
+ s_axi_bresp => ext_AXI_WriteMISO.response,
+ s_axi_bvalid => ext_AXI_WriteMISO.response_valid,
+ s_axi_rdata => ext_AXI_ReadMISO.data,
+ s_axi_rlast => ext_AXI_ReadMISO.last,
+ s_axi_rready => ext_AXI_ReadMOSI.ready_for_data,
+ s_axi_rresp => ext_AXI_ReadMISO.response,
+ s_axi_rvalid => ext_AXI_ReadMISO.data_valid,
+ s_axi_wdata => ext_AXI_WriteMOSI.data,
+ s_axi_wlast => ext_AXI_WriteMOSI.last,
+ s_axi_wready => ext_AXI_WriteMISO.ready_for_data,
+ s_axi_wstrb => ext_AXI_WriteMOSI.data_write_strobe,
+ s_axi_wvalid => ext_AXI_WriteMOSI.data_valid,
+ bram_rst_a => open,
+ bram_clk_a => AXI_CLK,
+ bram_en_a => AXI_BRAM_en,
+ bram_we_a => AXI_BRAM_we,
+ bram_addr_a => AXI_BRAM_addr,
+ bram_wrdata_a => AXI_BRAM_DATA_IN,
+ bram_rddata_a => AXI_BRAM_DATA_OUT);
+
+ DP_BRAM_1: entity work.DP_BRAM
+ port map (
+ clka => AXI_CLK,
+ ena => AXI_BRAM_EN,
+ wea => AXI_BRAM_we,
+ addra => AXI_BRAM_addr(11 downto 2),
+ dina => AXI_BRAM_DATA_IN,
+ douta => AXI_BRAM_DATA_OUT,
+ clkb => AXI_CLK,
+ enb => '1',
+ web => (others => BRAM_WRITE),
+ addrb => BRAM_ADDR,
+ dinb => BRAM_WR_DATA,
+ doutb => BRAM_RD_DATA);
+
+
+
+ heater_control_1: entity work.heater_control
+ port map (
+ clk_axi => AXI_CLK,
+ clk_200 => clk_200,
+ reset_axi_n => AXI_RST_N,
+ readMOSI => local_AXI_readMOSI(1),
+ readMISO => local_AXI_readMISO(1),
+ writeMOSI => local_AXI_writeMOSI(1),
+ writeMISO => local_AXI_writeMISO(1),
+ heater_output => heater_output);
+
+
+ IBERT_L: entity work.ibert_ultrascale_gty_l
+ port map (
+-- gty_sysclkp_i => p_clk_200a,
+-- gty_sysclkn_i => n_clk_200a,
+ -- quad 121 - 123 (AC-AE)
+ gty_rxn_i(0) => n_ff1_recv(0),
+ gty_rxn_i(1) => n_ff1_recv(1),
+ gty_rxn_i(2) => n_ff1_recv(2),
+ gty_rxn_i(3) => n_ff1_recv(3),
+ gty_rxn_i(4) => n_ff1_recv(4),
+ gty_rxn_i(5) => n_ff1_recv(5),
+ gty_rxn_i(6) => n_ff1_recv(6),
+ gty_rxn_i(7) => n_ff1_recv(7),
+ gty_rxn_i(8) => n_ff1_recv(8),
+ gty_rxn_i(9) => n_ff1_recv(9),
+ gty_rxn_i(10) => n_ff1_recv(10),
+ gty_rxn_i(11) => n_ff1_recv(11),
+
+ -- quad 124
+ gty_rxn_i(12) => n_ff4_recv(0),
+ gty_rxn_i(13) => n_ff4_recv(1),
+ gty_rxn_i(14) => n_ff4_recv(2),
+ gty_rxn_i(15) => n_ff4_recv(3),
+
+ -- quad 125 - 127 (Q-S)
+ gty_rxn_i(16) => n_ff2_recv(0),
+ gty_rxn_i(17) => n_ff2_recv(1),
+ gty_rxn_i(18) => n_ff2_recv(2),
+ gty_rxn_i(19) => n_ff2_recv(3),
+ gty_rxn_i(20) => n_ff2_recv(4),
+ gty_rxn_i(21) => n_ff2_recv(5),
+ gty_rxn_i(22) => n_ff2_recv(6),
+ gty_rxn_i(23) => n_ff2_recv(7),
+ gty_rxn_i(24) => n_ff2_recv(8),
+ gty_rxn_i(25) => n_ff2_recv(9),
+ gty_rxn_i(26) => n_ff2_recv(10),
+ gty_rxn_i(27) => n_ff2_recv(11),
+
+ -- quad 128
+ gty_rxn_i(28) => n_ff5_recv(0),
+ gty_rxn_i(29) => n_ff5_recv(1),
+ gty_rxn_i(30) => n_ff5_recv(2),
+ gty_rxn_i(31) => n_ff5_recv(3),
+ -- quad 129
+ gty_rxn_i(32) => n_ff6_recv(0),
+ gty_rxn_i(33) => n_ff6_recv(1),
+ gty_rxn_i(34) => n_ff6_recv(2),
+ gty_rxn_i(35) => n_ff6_recv(3),
+ -- quad 130
+ gty_rxn_i(36) => n_ff7_recv(0),
+ gty_rxn_i(37) => n_ff7_recv(1),
+ gty_rxn_i(38) => n_ff7_recv(2),
+ gty_rxn_i(39) => n_ff7_recv(3),
+
+ -- quad 132-133 (X-Z)
+ gty_rxn_i(40) => n_ff3_recv(0),
+ gty_rxn_i(41) => n_ff3_recv(1),
+ gty_rxn_i(42) => n_ff3_recv(2),
+ gty_rxn_i(43) => n_ff3_recv(3),
+ gty_rxn_i(44) => n_ff3_recv(4),
+ gty_rxn_i(45) => n_ff3_recv(5),
+ gty_rxn_i(46) => n_ff3_recv(6),
+ gty_rxn_i(47) => n_ff3_recv(7),
+ gty_rxn_i(48) => n_ff3_recv(8),
+ gty_rxn_i(49) => n_ff3_recv(9),
+ gty_rxn_i(50) => n_ff3_recv(10),
+ gty_rxn_i(51) => n_ff3_recv(11),
+
+ -- quad 121 - 123 (AC-AE)
+ gty_rxp_i(0) => p_ff1_recv(0),
+ gty_rxp_i(1) => p_ff1_recv(1),
+ gty_rxp_i(2) => p_ff1_recv(2),
+ gty_rxp_i(3) => p_ff1_recv(3),
+ gty_rxp_i(4) => p_ff1_recv(4),
+ gty_rxp_i(5) => p_ff1_recv(5),
+ gty_rxp_i(6) => p_ff1_recv(6),
+ gty_rxp_i(7) => p_ff1_recv(7),
+ gty_rxp_i(8) => p_ff1_recv(8),
+ gty_rxp_i(9) => p_ff1_recv(9),
+ gty_rxp_i(10) => p_ff1_recv(10),
+ gty_rxp_i(11) => p_ff1_recv(11),
+
+ -- quad 124
+ gty_rxp_i(12) => p_ff4_recv(0),
+ gty_rxp_i(13) => p_ff4_recv(1),
+ gty_rxp_i(14) => p_ff4_recv(2),
+ gty_rxp_i(15) => p_ff4_recv(3),
+
+ -- quad 125 - 127 (Q-S)
+ gty_rxp_i(16) => p_ff2_recv(0),
+ gty_rxp_i(17) => p_ff2_recv(1),
+ gty_rxp_i(18) => p_ff2_recv(2),
+ gty_rxp_i(19) => p_ff2_recv(3),
+ gty_rxp_i(20) => p_ff2_recv(4),
+ gty_rxp_i(21) => p_ff2_recv(5),
+ gty_rxp_i(22) => p_ff2_recv(6),
+ gty_rxp_i(23) => p_ff2_recv(7),
+ gty_rxp_i(24) => p_ff2_recv(8),
+ gty_rxp_i(25) => p_ff2_recv(9),
+ gty_rxp_i(26) => p_ff2_recv(10),
+ gty_rxp_i(27) => p_ff2_recv(11),
+
+ -- quad 128
+ gty_rxp_i(28) => p_ff5_recv(0),
+ gty_rxp_i(29) => p_ff5_recv(1),
+ gty_rxp_i(30) => p_ff5_recv(2),
+ gty_rxp_i(31) => p_ff5_recv(3),
+ -- quad 129
+ gty_rxp_i(32) => p_ff6_recv(0),
+ gty_rxp_i(33) => p_ff6_recv(1),
+ gty_rxp_i(34) => p_ff6_recv(2),
+ gty_rxp_i(35) => p_ff6_recv(3),
+ -- quad 130
+ gty_rxp_i(36) => p_ff7_recv(0),
+ gty_rxp_i(37) => p_ff7_recv(1),
+ gty_rxp_i(38) => p_ff7_recv(2),
+ gty_rxp_i(39) => p_ff7_recv(3),
+
+ -- quad 132-133 (X-Z)
+ gty_rxp_i(40) => p_ff3_recv(0),
+ gty_rxp_i(41) => p_ff3_recv(1),
+ gty_rxp_i(42) => p_ff3_recv(2),
+ gty_rxp_i(43) => p_ff3_recv(3),
+ gty_rxp_i(44) => p_ff3_recv(4),
+ gty_rxp_i(45) => p_ff3_recv(5),
+ gty_rxp_i(46) => p_ff3_recv(6),
+ gty_rxp_i(47) => p_ff3_recv(7),
+ gty_rxp_i(48) => p_ff3_recv(8),
+ gty_rxp_i(49) => p_ff3_recv(9),
+ gty_rxp_i(50) => p_ff3_recv(10),
+ gty_rxp_i(51) => p_ff3_recv(11),
+
+
+ gty_refclk0p_i(0) => p_lf_r0_ad,
+ gty_refclk0p_i(1) => p_lf_r0_af,
+ gty_refclk0p_i(2) => p_lf_r0_r,
+ gty_refclk0p_i(3) => p_lf_r0_u,
+ gty_refclk0p_i(4) => p_lf_r0_v,
+ gty_refclk0p_i(5) => p_lf_r0_y,
+
+ gty_refclk0n_i(0) => n_lf_r0_ad,
+ gty_refclk0n_i(1) => n_lf_r0_af,
+ gty_refclk0n_i(2) => n_lf_r0_r,
+ gty_refclk0n_i(3) => n_lf_r0_u,
+ gty_refclk0n_i(4) => n_lf_r0_v,
+ gty_refclk0n_i(5) => n_lf_r0_y,
+
+ -- quad 121 - 123 (AC-AE)
+ gty_txn_o(0) => n_ff1_xmit(0),
+ gty_txn_o(1) => n_ff1_xmit(1),
+ gty_txn_o(2) => n_ff1_xmit(2),
+ gty_txn_o(3) => n_ff1_xmit(3),
+ gty_txn_o(4) => n_ff1_xmit(4),
+ gty_txn_o(5) => n_ff1_xmit(5),
+ gty_txn_o(6) => n_ff1_xmit(6),
+ gty_txn_o(7) => n_ff1_xmit(7),
+ gty_txn_o(8) => n_ff1_xmit(8),
+ gty_txn_o(9) => n_ff1_xmit(9),
+ gty_txn_o(10) => n_ff1_xmit(10),
+ gty_txn_o(11) => n_ff1_xmit(11),
+
+ -- quad 124
+ gty_txn_o(12) => n_ff4_xmit(0),
+ gty_txn_o(13) => n_ff4_xmit(1),
+ gty_txn_o(14) => n_ff4_xmit(2),
+ gty_txn_o(15) => n_ff4_xmit(3),
+
+ -- quad 125 - 127 (Q-S)
+ gty_txn_o(16) => n_ff2_xmit(0),
+ gty_txn_o(17) => n_ff2_xmit(1),
+ gty_txn_o(18) => n_ff2_xmit(2),
+ gty_txn_o(19) => n_ff2_xmit(3),
+ gty_txn_o(20) => n_ff2_xmit(4),
+ gty_txn_o(21) => n_ff2_xmit(5),
+ gty_txn_o(22) => n_ff2_xmit(6),
+ gty_txn_o(23) => n_ff2_xmit(7),
+ gty_txn_o(24) => n_ff2_xmit(8),
+ gty_txn_o(25) => n_ff2_xmit(9),
+ gty_txn_o(26) => n_ff2_xmit(10),
+ gty_txn_o(27) => n_ff2_xmit(11),
+
+ -- quad 128
+ gty_txn_o(28) => n_ff5_xmit(0),
+ gty_txn_o(29) => n_ff5_xmit(1),
+ gty_txn_o(30) => n_ff5_xmit(2),
+ gty_txn_o(31) => n_ff5_xmit(3),
+ -- quad 129
+ gty_txn_o(32) => n_ff6_xmit(0),
+ gty_txn_o(33) => n_ff6_xmit(1),
+ gty_txn_o(34) => n_ff6_xmit(2),
+ gty_txn_o(35) => n_ff6_xmit(3),
+ -- quad 130
+ gty_txn_o(36) => n_ff7_xmit(0),
+ gty_txn_o(37) => n_ff7_xmit(1),
+ gty_txn_o(38) => n_ff7_xmit(2),
+ gty_txn_o(39) => n_ff7_xmit(3),
+
+ -- quad 132-133 (X-Z)
+ gty_txn_o(40) => n_ff3_xmit(0),
+ gty_txn_o(41) => n_ff3_xmit(1),
+ gty_txn_o(42) => n_ff3_xmit(2),
+ gty_txn_o(43) => n_ff3_xmit(3),
+ gty_txn_o(44) => n_ff3_xmit(4),
+ gty_txn_o(45) => n_ff3_xmit(5),
+ gty_txn_o(46) => n_ff3_xmit(6),
+ gty_txn_o(47) => n_ff3_xmit(7),
+ gty_txn_o(48) => n_ff3_xmit(8),
+ gty_txn_o(49) => n_ff3_xmit(9),
+ gty_txn_o(50) => n_ff3_xmit(10),
+ gty_txn_o(51) => n_ff3_xmit(11),
+
+ -- quad 121 - 123 (AC-AE)
+ gty_txp_o(0) => p_ff1_xmit(0),
+ gty_txp_o(1) => p_ff1_xmit(1),
+ gty_txp_o(2) => p_ff1_xmit(2),
+ gty_txp_o(3) => p_ff1_xmit(3),
+ gty_txp_o(4) => p_ff1_xmit(4),
+ gty_txp_o(5) => p_ff1_xmit(5),
+ gty_txp_o(6) => p_ff1_xmit(6),
+ gty_txp_o(7) => p_ff1_xmit(7),
+ gty_txp_o(8) => p_ff1_xmit(8),
+ gty_txp_o(9) => p_ff1_xmit(9),
+ gty_txp_o(10) => p_ff1_xmit(10),
+ gty_txp_o(11) => p_ff1_xmit(11),
+
+ -- quad 124
+ gty_txp_o(12) => p_ff4_xmit(0),
+ gty_txp_o(13) => p_ff4_xmit(1),
+ gty_txp_o(14) => p_ff4_xmit(2),
+ gty_txp_o(15) => p_ff4_xmit(3),
+
+ -- quad 125 - 127 (Q-S)
+ gty_txp_o(16) => p_ff2_xmit(0),
+ gty_txp_o(17) => p_ff2_xmit(1),
+ gty_txp_o(18) => p_ff2_xmit(2),
+ gty_txp_o(19) => p_ff2_xmit(3),
+ gty_txp_o(20) => p_ff2_xmit(4),
+ gty_txp_o(21) => p_ff2_xmit(5),
+ gty_txp_o(22) => p_ff2_xmit(6),
+ gty_txp_o(23) => p_ff2_xmit(7),
+ gty_txp_o(24) => p_ff2_xmit(8),
+ gty_txp_o(25) => p_ff2_xmit(9),
+ gty_txp_o(26) => p_ff2_xmit(10),
+ gty_txp_o(27) => p_ff2_xmit(11),
+
+ -- quad 128
+ gty_txp_o(28) => p_ff5_xmit(0),
+ gty_txp_o(29) => p_ff5_xmit(1),
+ gty_txp_o(30) => p_ff5_xmit(2),
+ gty_txp_o(31) => p_ff5_xmit(3),
+ -- quad 129
+ gty_txp_o(32) => p_ff6_xmit(0),
+ gty_txp_o(33) => p_ff6_xmit(1),
+ gty_txp_o(34) => p_ff6_xmit(2),
+ gty_txp_o(35) => p_ff6_xmit(3),
+ -- quad 130
+ gty_txp_o(36) => p_ff7_xmit(0),
+ gty_txp_o(37) => p_ff7_xmit(1),
+ gty_txp_o(38) => p_ff7_xmit(2),
+ gty_txp_o(39) => p_ff7_xmit(3),
+
+ -- quad 132-133 (X-Z)
+ gty_txp_o(40) => p_ff3_xmit(0),
+ gty_txp_o(41) => p_ff3_xmit(1),
+ gty_txp_o(42) => p_ff3_xmit(2),
+ gty_txp_o(43) => p_ff3_xmit(3),
+ gty_txp_o(44) => p_ff3_xmit(4),
+ gty_txp_o(45) => p_ff3_xmit(5),
+ gty_txp_o(46) => p_ff3_xmit(6),
+ gty_txp_o(47) => p_ff3_xmit(7),
+ gty_txp_o(48) => p_ff3_xmit(8),
+ gty_txp_o(49) => p_ff3_xmit(9),
+ gty_txp_o(50) => p_ff3_xmit(10),
+ gty_txp_o(51) => p_ff3_xmit(11)
+
+ );
+
+
+ IBERT_R: entity work.ibert_ultrascale_gty_r
+ port map (
+ -- quad 221 - 223 (M,N,O)
+ gty_rxn_i(0) => n_m_recv(0),
+ gty_rxn_i(1) => n_m_recv(1),
+ gty_rxn_i(2) => n_m_recv(2),
+ gty_rxn_i(3) => n_m_recv(3),
+ gty_rxn_i(4) => n_n_recv(0),
+ gty_rxn_i(5) => n_n_recv(1),
+ gty_rxn_i(6) => n_n_recv(2),
+ gty_rxn_i(7) => n_n_recv(3),
+ gty_rxn_i(8) => n_o_recv(0),
+ gty_rxn_i(9) => n_o_recv(1),
+ gty_rxn_i(10) => n_o_recv(2),
+ gty_rxn_i(11) => n_o_recv(3),
+
+ -- quad 224 (P)
+ gty_rxn_i(12) => n_p_recv(0),
+ gty_rxn_i(13) => n_p_recv(1),
+ gty_rxn_i(14) => n_p_recv(2),
+ gty_rxn_i(15) => n_p_recv(3),
+
+ -- quad 225 - 227 (A,B,C)
+ gty_rxn_i(16) => n_a_recv(0),
+ gty_rxn_i(17) => n_a_recv(1),
+ gty_rxn_i(18) => n_a_recv(2),
+ gty_rxn_i(19) => n_a_recv(3),
+ gty_rxn_i(20) => n_b_recv(0),
+ gty_rxn_i(21) => n_b_recv(1),
+ gty_rxn_i(22) => n_b_recv(2),
+ gty_rxn_i(23) => n_b_recv(3),
+ gty_rxn_i(24) => n_c_recv(0),
+ gty_rxn_i(25) => n_c_recv(1),
+ gty_rxn_i(26) => n_c_recv(2),
+ gty_rxn_i(27) => n_c_recv(3),
+
+ -- quad 228 (D)
+ gty_rxn_i(28) => n_d_recv(0),
+ gty_rxn_i(29) => n_d_recv(1),
+ gty_rxn_i(30) => n_d_recv(2),
+ gty_rxn_i(31) => n_d_recv(3),
+ --quad 229 (E)
+ gty_rxn_i(32) => n_e_recv(0),
+ gty_rxn_i(33) => n_e_recv(1),
+ gty_rxn_i(34) => n_e_recv(2),
+ gty_rxn_i(35) => n_e_recv(3),
+ -- quad 230 (F)
+ gty_rxn_i(36) => n_f_recv(0),
+ gty_rxn_i(37) => n_f_recv(1),
+ gty_rxn_i(38) => n_f_recv(2),
+ gty_rxn_i(39) => n_f_recv(3),
+
+ -- quad 232 - 234 (H,I,J)
+ gty_rxn_i(40) => n_h_recv(0),
+ gty_rxn_i(41) => n_h_recv(1),
+ gty_rxn_i(42) => n_h_recv(2),
+ gty_rxn_i(43) => n_h_recv(3),
+ gty_rxn_i(44) => n_i_recv(0),
+ gty_rxn_i(45) => n_i_recv(1),
+ gty_rxn_i(46) => n_i_recv(2),
+ gty_rxn_i(47) => n_i_recv(3),
+ gty_rxn_i(48) => n_j_recv(0),
+ gty_rxn_i(49) => n_j_recv(1),
+ gty_rxn_i(50) => n_j_recv(2),
+ gty_rxn_i(51) => n_j_recv(3),
+
+ -- quad 221 - 223 (M,N,O)
+ gty_rxp_i(0) => p_m_recv(0),
+ gty_rxp_i(1) => p_m_recv(1),
+ gty_rxp_i(2) => p_m_recv(2),
+ gty_rxp_i(3) => p_m_recv(3),
+ gty_rxp_i(4) => p_n_recv(0),
+ gty_rxp_i(5) => p_n_recv(1),
+ gty_rxp_i(6) => p_n_recv(2),
+ gty_rxp_i(7) => p_n_recv(3),
+ gty_rxp_i(8) => p_o_recv(0),
+ gty_rxp_i(9) => p_o_recv(1),
+ gty_rxp_i(10) => p_o_recv(2),
+ gty_rxp_i(11) => p_o_recv(3),
+
+ -- quad 224 (P)
+ gty_rxp_i(12) => p_p_recv(0),
+ gty_rxp_i(13) => p_p_recv(1),
+ gty_rxp_i(14) => p_p_recv(2),
+ gty_rxp_i(15) => p_p_recv(3),
+
+ -- quad 225 - 227 (A,B,C)
+ gty_rxp_i(16) => p_a_recv(0),
+ gty_rxp_i(17) => p_a_recv(1),
+ gty_rxp_i(18) => p_a_recv(2),
+ gty_rxp_i(19) => p_a_recv(3),
+ gty_rxp_i(20) => p_b_recv(0),
+ gty_rxp_i(21) => p_b_recv(1),
+ gty_rxp_i(22) => p_b_recv(2),
+ gty_rxp_i(23) => p_b_recv(3),
+ gty_rxp_i(24) => p_c_recv(0),
+ gty_rxp_i(25) => p_c_recv(1),
+ gty_rxp_i(26) => p_c_recv(2),
+ gty_rxp_i(27) => p_c_recv(3),
+
+ -- quad 228 (D)
+ gty_rxp_i(28) => p_d_recv(0),
+ gty_rxp_i(29) => p_d_recv(1),
+ gty_rxp_i(30) => p_d_recv(2),
+ gty_rxp_i(31) => p_d_recv(3),
+ --quad 229 (E)
+ gty_rxp_i(32) => p_e_recv(0),
+ gty_rxp_i(33) => p_e_recv(1),
+ gty_rxp_i(34) => p_e_recv(2),
+ gty_rxp_i(35) => p_e_recv(3),
+ -- quad 230 (F)
+ gty_rxp_i(36) => p_f_recv(0),
+ gty_rxp_i(37) => p_f_recv(1),
+ gty_rxp_i(38) => p_f_recv(2),
+ gty_rxp_i(39) => p_f_recv(3),
+
+ -- quad 232 - 234 (H,I,J)
+ gty_rxp_i(40) => p_h_recv(0),
+ gty_rxp_i(41) => p_h_recv(1),
+ gty_rxp_i(42) => p_h_recv(2),
+ gty_rxp_i(43) => p_h_recv(3),
+ gty_rxp_i(44) => p_i_recv(0),
+ gty_rxp_i(45) => p_i_recv(1),
+ gty_rxp_i(46) => p_i_recv(2),
+ gty_rxp_i(47) => p_i_recv(3),
+ gty_rxp_i(48) => p_j_recv(0),
+ gty_rxp_i(49) => p_j_recv(1),
+ gty_rxp_i(50) => p_j_recv(2),
+ gty_rxp_i(51) => p_j_recv(3),
+
+ -- refclks
+ gty_refclk0p_i(0) => p_rt_r0_n,
+ gty_refclk0p_i(1) => p_rt_r0_p,
+ gty_refclk0p_i(2) => p_rt_r0_b,
+ gty_refclk0p_i(3) => p_rt_r0_e,
+ gty_refclk0p_i(4) => p_rt_r0_f,
+ gty_refclk0p_i(5) => p_rt_r0_i,
+
+ gty_refclk0n_i(0) => n_rt_r0_n,
+ gty_refclk0n_i(1) => n_rt_r0_p,
+ gty_refclk0n_i(2) => n_rt_r0_b,
+ gty_refclk0n_i(3) => n_rt_r0_e,
+ gty_refclk0n_i(4) => n_rt_r0_f,
+ gty_refclk0n_i(5) => n_rt_r0_i,
+
+ -- quad 221 - 123 (M,N,O)
+ gty_txn_o(0) => n_m_xmit(0),
+ gty_txn_o(1) => n_m_xmit(1),
+ gty_txn_o(2) => n_m_xmit(2),
+ gty_txn_o(3) => n_m_xmit(3),
+ gty_txn_o(4) => n_n_xmit(0),
+ gty_txn_o(5) => n_n_xmit(1),
+ gty_txn_o(6) => n_n_xmit(2),
+ gty_txn_o(7) => n_n_xmit(3),
+ gty_txn_o(8) => n_o_xmit(0),
+ gty_txn_o(9) => n_o_xmit(1),
+ gty_txn_o(10) => n_o_xmit(2),
+ gty_txn_o(11) => n_o_xmit(3),
+
+ -- quad 224 (P)
+ gty_txn_o(12) => n_p_xmit(0),
+ gty_txn_o(13) => n_p_xmit(1),
+ gty_txn_o(14) => n_p_xmit(2),
+ gty_txn_o(15) => n_p_xmit(3),
+
+ -- quad 225 - 227 (A,B,C)
+ gty_txn_o(16) => n_a_xmit(0),
+ gty_txn_o(17) => n_a_xmit(1),
+ gty_txn_o(18) => n_a_xmit(2),
+ gty_txn_o(19) => n_a_xmit(3),
+ gty_txn_o(20) => n_b_xmit(0),
+ gty_txn_o(21) => n_b_xmit(1),
+ gty_txn_o(22) => n_b_xmit(2),
+ gty_txn_o(23) => n_b_xmit(3),
+ gty_txn_o(24) => n_c_xmit(0),
+ gty_txn_o(25) => n_c_xmit(1),
+ gty_txn_o(26) => n_c_xmit(2),
+ gty_txn_o(27) => n_c_xmit(3),
+
+ -- quad 228 (D)
+ gty_txn_o(28) => n_d_xmit(0),
+ gty_txn_o(29) => n_d_xmit(1),
+ gty_txn_o(30) => n_d_xmit(2),
+ gty_txn_o(31) => n_d_xmit(3),
+ --quad 229 (E)
+ gty_txn_o(32) => n_e_xmit(0),
+ gty_txn_o(33) => n_e_xmit(1),
+ gty_txn_o(34) => n_e_xmit(2),
+ gty_txn_o(35) => n_e_xmit(3),
+ -- quad 230 (F)
+ gty_txn_o(36) => n_f_xmit(0),
+ gty_txn_o(37) => n_f_xmit(1),
+ gty_txn_o(38) => n_f_xmit(2),
+ gty_txn_o(39) => n_f_xmit(3),
+
+ -- quad 232 - 234 (H,I,J)
+ gty_txn_o(40) => n_h_xmit(0),
+ gty_txn_o(41) => n_h_xmit(1),
+ gty_txn_o(42) => n_h_xmit(2),
+ gty_txn_o(43) => n_h_xmit(3),
+ gty_txn_o(44) => n_i_xmit(0),
+ gty_txn_o(45) => n_i_xmit(1),
+ gty_txn_o(46) => n_i_xmit(2),
+ gty_txn_o(47) => n_i_xmit(3),
+ gty_txn_o(48) => n_j_xmit(0),
+ gty_txn_o(49) => n_j_xmit(1),
+ gty_txn_o(50) => n_j_xmit(2),
+ gty_txn_o(51) => n_j_xmit(3),
+
+ -- quad 221 - 223 (M,N,O)
+ gty_txp_o(0) => p_m_xmit(0),
+ gty_txp_o(1) => p_m_xmit(1),
+ gty_txp_o(2) => p_m_xmit(2),
+ gty_txp_o(3) => p_m_xmit(3),
+ gty_txp_o(4) => p_n_xmit(0),
+ gty_txp_o(5) => p_n_xmit(1),
+ gty_txp_o(6) => p_n_xmit(2),
+ gty_txp_o(7) => p_n_xmit(3),
+ gty_txp_o(8) => p_o_xmit(0),
+ gty_txp_o(9) => p_o_xmit(1),
+ gty_txp_o(10) => p_o_xmit(2),
+ gty_txp_o(11) => p_o_xmit(3),
+
+ -- quad 224 (P)
+ gty_txp_o(12) => p_p_xmit(0),
+ gty_txp_o(13) => p_p_xmit(1),
+ gty_txp_o(14) => p_p_xmit(2),
+ gty_txp_o(15) => p_p_xmit(3),
+
+ -- quad 225 - 227 (A,B,C)
+ gty_txp_o(16) => p_a_xmit(0),
+ gty_txp_o(17) => p_a_xmit(1),
+ gty_txp_o(18) => p_a_xmit(2),
+ gty_txp_o(19) => p_a_xmit(3),
+ gty_txp_o(20) => p_b_xmit(0),
+ gty_txp_o(21) => p_b_xmit(1),
+ gty_txp_o(22) => p_b_xmit(2),
+ gty_txp_o(23) => p_b_xmit(3),
+ gty_txp_o(24) => p_c_xmit(0),
+ gty_txp_o(25) => p_c_xmit(1),
+ gty_txp_o(26) => p_c_xmit(2),
+ gty_txp_o(27) => p_c_xmit(3),
+
+ -- quad 228 (D)
+ gty_txp_o(28) => p_d_xmit(0),
+ gty_txp_o(29) => p_d_xmit(1),
+ gty_txp_o(30) => p_d_xmit(2),
+ gty_txp_o(31) => p_d_xmit(3),
+ --quad 229 (E)
+ gty_txp_o(32) => p_e_xmit(0),
+ gty_txp_o(33) => p_e_xmit(1),
+ gty_txp_o(34) => p_e_xmit(2),
+ gty_txp_o(35) => p_e_xmit(3),
+ -- quad 230 (F)
+ gty_txp_o(36) => p_f_xmit(0),
+ gty_txp_o(37) => p_f_xmit(1),
+ gty_txp_o(38) => p_f_xmit(2),
+ gty_txp_o(39) => p_f_xmit(3),
+
+ -- quad 232 - 234 (H,I,J)
+ gty_txp_o(40) => p_h_xmit(0),
+ gty_txp_o(41) => p_h_xmit(1),
+ gty_txp_o(42) => p_h_xmit(2),
+ gty_txp_o(43) => p_h_xmit(3),
+ gty_txp_o(44) => p_i_xmit(0),
+ gty_txp_o(45) => p_i_xmit(1),
+ gty_txp_o(46) => p_i_xmit(2),
+ gty_txp_o(47) => p_i_xmit(3),
+ gty_txp_o(48) => p_j_xmit(0),
+ gty_txp_o(49) => p_j_xmit(1),
+ gty_txp_o(50) => p_j_xmit(2),
+ gty_txp_o(51) => p_j_xmit(3)
+
+ );
+end architecture structure;
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_heaters.xdc b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_heaters.xdc
new file mode 100644
index 0000000..eca6aaf
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_heaters.xdc
@@ -0,0 +1,102 @@
+create_pblock {pblock_gn_htr_1[0].htr_1}
+resize_pblock {pblock_gn_htr_1[0].htr_1} -add CLOCKREGION_X0Y15:CLOCKREGION_X1Y14
+add_cells_to_pblock {pblock_gn_htr_1[0].htr_1} [get_cells [list {TCDS_1/gen_heater_1[0].heater_1}]] -clear_locs
+create_pblock {pblock_gn_htr_1[1].htr_1}
+resize_pblock {pblock_gn_htr_1[1].htr_1} -add CLOCKREGION_X2Y15:CLOCKREGION_X3Y14
+add_cells_to_pblock {pblock_gn_htr_1[1].htr_1} [get_cells [list {TCDS_1/gen_heater_1[1].heater_1}]] -clear_locs
+create_pblock {pblock_gn_htr_1[2].htr_1}
+resize_pblock {pblock_gn_htr_1[2].htr_1} -add CLOCKREGION_X4Y15:CLOCKREGION_X5Y14
+add_cells_to_pblock {pblock_gn_htr_1[2].htr_1} [get_cells [list {TCDS_1/gen_heater_1[2].heater_1}]] -clear_locs
+create_pblock {pblock_gn_htr_1[3].htr_1}
+resize_pblock {pblock_gn_htr_1[3].htr_1} -add CLOCKREGION_X6Y15:CLOCKREGION_X7Y14
+add_cells_to_pblock {pblock_gn_htr_1[3].htr_1} [get_cells [list {TCDS_1/gen_heater_1[3].heater_1}]] -clear_locs
+create_pblock {pblock_gn_htr_1[4].htr_1}
+resize_pblock {pblock_gn_htr_1[4].htr_1} -add CLOCKREGION_X0Y13:CLOCKREGION_X1Y12
+add_cells_to_pblock {pblock_gn_htr_1[4].htr_1} [get_cells [list {TCDS_1/gen_heater_1[4].heater_1}]] -clear_locs
+create_pblock {pblock_gn_htr_1[5].htr_1}
+resize_pblock {pblock_gn_htr_1[5].htr_1} -add CLOCKREGION_X2Y13:CLOCKREGION_X3Y12
+add_cells_to_pblock {pblock_gn_htr_1[5].htr_1} [get_cells [list {TCDS_1/gen_heater_1[5].heater_1}]] -clear_locs
+create_pblock {pblock_gn_htr_1[6].htr_1}
+resize_pblock {pblock_gn_htr_1[6].htr_1} -add CLOCKREGION_X4Y13:CLOCKREGION_X5Y12
+add_cells_to_pblock {pblock_gn_htr_1[6].htr_1} [get_cells [list {TCDS_1/gen_heater_1[6].heater_1}]] -clear_locs
+create_pblock {pblock_gn_htr_1[7].htr_1}
+resize_pblock {pblock_gn_htr_1[7].htr_1} -add CLOCKREGION_X6Y13:CLOCKREGION_X7Y12
+add_cells_to_pblock {pblock_gn_htr_1[7].htr_1} [get_cells [list {TCDS_1/gen_heater_1[7].heater_1}]] -clear_locs
+
+
+create_pblock {pblock_gn_htr_2[8].htr_2}
+resize_pblock {pblock_gn_htr_2[8].htr_2} -add CLOCKREGION_X0Y11:CLOCKREGION_X1Y10
+add_cells_to_pblock {pblock_gn_htr_2[8].htr_2} [get_cells [list {TCDS_1/gen_heater_2[8].heater_2}]] -clear_locs
+create_pblock {pblock_gn_htr_2[9].htr_2}
+resize_pblock {pblock_gn_htr_2[9].htr_2} -add CLOCKREGION_X2Y11:CLOCKREGION_X3Y10
+add_cells_to_pblock {pblock_gn_htr_2[9].htr_2} [get_cells [list {TCDS_1/gen_heater_2[9].heater_2}]] -clear_locs
+create_pblock {pblock_gn_htr_2[10].htr_2}
+resize_pblock {pblock_gn_htr_2[10].htr_2} -add CLOCKREGION_X4Y11:CLOCKREGION_X5Y10
+add_cells_to_pblock {pblock_gn_htr_2[10].htr_2} [get_cells [list {TCDS_1/gen_heater_2[10].heater_2}]] -clear_locs
+create_pblock {pblock_gn_htr_2[11].htr_2}
+resize_pblock {pblock_gn_htr_2[11].htr_2} -add CLOCKREGION_X6Y11:CLOCKREGION_X7Y10
+add_cells_to_pblock {pblock_gn_htr_2[11].htr_2} [get_cells [list {TCDS_1/gen_heater_2[11].heater_2}]] -clear_locs
+create_pblock {pblock_gn_htr_2[12].htr_2}
+resize_pblock {pblock_gn_htr_2[12].htr_2} -add CLOCKREGION_X0Y9:CLOCKREGION_X1Y8
+add_cells_to_pblock {pblock_gn_htr_2[12].htr_2} [get_cells [list {TCDS_1/gen_heater_2[12].heater_2}]] -clear_locs
+create_pblock {pblock_gn_htr_2[13].htr_2}
+resize_pblock {pblock_gn_htr_2[13].htr_2} -add CLOCKREGION_X2Y9:CLOCKREGION_X3Y8
+add_cells_to_pblock {pblock_gn_htr_2[13].htr_2} [get_cells [list {TCDS_1/gen_heater_2[13].heater_2}]] -clear_locs
+create_pblock {pblock_gn_htr_2[14].htr_2}
+resize_pblock {pblock_gn_htr_2[14].htr_2} -add CLOCKREGION_X4Y9:CLOCKREGION_X5Y8
+add_cells_to_pblock {pblock_gn_htr_2[14].htr_2} [get_cells [list {TCDS_1/gen_heater_2[14].heater_2}]] -clear_locs
+create_pblock {pblock_gn_htr_2[15].htr_2}
+resize_pblock {pblock_gn_htr_2[15].htr_2} -add CLOCKREGION_X6Y9:CLOCKREGION_X7Y8
+add_cells_to_pblock {pblock_gn_htr_2[15].htr_2} [get_cells [list {TCDS_1/gen_heater_2[15].heater_2}]] -clear_locs
+
+
+create_pblock {pblock_gn_htr_3[16].htr_3}
+resize_pblock {pblock_gn_htr_3[16].htr_3} -add CLOCKREGION_X0Y7:CLOCKREGION_X1Y6
+add_cells_to_pblock {pblock_gn_htr_3[16].htr_3} [get_cells [list {TCDS_1/gen_heater_3[16].heater_3}]] -clear_locs
+create_pblock {pblock_gn_htr_3[17].htr_3}
+resize_pblock {pblock_gn_htr_3[17].htr_3} -add CLOCKREGION_X2Y7:CLOCKREGION_X3Y6
+add_cells_to_pblock {pblock_gn_htr_3[17].htr_3} [get_cells [list {TCDS_1/gen_heater_3[17].heater_3}]] -clear_locs
+create_pblock {pblock_gn_htr_3[18].htr_3}
+resize_pblock {pblock_gn_htr_3[18].htr_3} -add CLOCKREGION_X4Y7:CLOCKREGION_X5Y6
+add_cells_to_pblock {pblock_gn_htr_3[18].htr_3} [get_cells [list {TCDS_1/gen_heater_3[18].heater_3}]] -clear_locs
+create_pblock {pblock_gn_htr_3[19].htr_3}
+resize_pblock {pblock_gn_htr_3[19].htr_3} -add CLOCKREGION_X6Y7:CLOCKREGION_X7Y6
+add_cells_to_pblock {pblock_gn_htr_3[19].htr_3} [get_cells [list {TCDS_1/gen_heater_3[19].heater_3}]] -clear_locs
+create_pblock {pblock_gn_htr_3[20].htr_3}
+resize_pblock {pblock_gn_htr_3[20].htr_3} -add CLOCKREGION_X0Y5:CLOCKREGION_X1Y4
+add_cells_to_pblock {pblock_gn_htr_3[20].htr_3} [get_cells [list {TCDS_1/gen_heater_3[20].heater_3}]] -clear_locs
+create_pblock {pblock_gn_htr_3[21].htr_3}
+resize_pblock {pblock_gn_htr_3[21].htr_3} -add CLOCKREGION_X2Y5:CLOCKREGION_X3Y4
+add_cells_to_pblock {pblock_gn_htr_3[21].htr_3} [get_cells [list {TCDS_1/gen_heater_3[21].heater_3}]] -clear_locs
+create_pblock {pblock_gn_htr_3[22].htr_3}
+resize_pblock {pblock_gn_htr_3[22].htr_3} -add CLOCKREGION_X4Y5:CLOCKREGION_X5Y4
+add_cells_to_pblock {pblock_gn_htr_3[22].htr_3} [get_cells [list {TCDS_1/gen_heater_3[22].heater_3}]] -clear_locs
+create_pblock {pblock_gn_htr_3[23].htr_3}
+resize_pblock {pblock_gn_htr_3[23].htr_3} -add CLOCKREGION_X6Y5:CLOCKREGION_X7Y4
+add_cells_to_pblock {pblock_gn_htr_3[23].htr_3} [get_cells [list {TCDS_1/gen_heater_3[23].heater_3}]] -clear_locs
+
+
+create_pblock {pblock_gn_htr_4[24].htr_4}
+resize_pblock {pblock_gn_htr_4[24].htr_4} -add CLOCKREGION_X0Y3:CLOCKREGION_X1Y2
+add_cells_to_pblock {pblock_gn_htr_4[24].htr_4} [get_cells [list {TCDS_1/gen_heater_4[24].heater_4}]] -clear_locs
+create_pblock {pblock_gn_htr_4[25].htr_4}
+resize_pblock {pblock_gn_htr_4[25].htr_4} -add CLOCKREGION_X2Y3:CLOCKREGION_X3Y2
+add_cells_to_pblock {pblock_gn_htr_4[25].htr_4} [get_cells [list {TCDS_1/gen_heater_4[25].heater_4}]] -clear_locs
+create_pblock {pblock_gn_htr_4[26].htr_4}
+resize_pblock {pblock_gn_htr_4[26].htr_4} -add CLOCKREGION_X4Y3:CLOCKREGION_X5Y2
+add_cells_to_pblock {pblock_gn_htr_4[26].htr_4} [get_cells [list {TCDS_1/gen_heater_4[26].heater_4}]] -clear_locs
+create_pblock {pblock_gn_htr_4[27].htr_4}
+resize_pblock {pblock_gn_htr_4[27].htr_4} -add CLOCKREGION_X6Y3:CLOCKREGION_X7Y2
+add_cells_to_pblock {pblock_gn_htr_4[27].htr_4} [get_cells [list {TCDS_1/gen_heater_4[27].heater_4}]] -clear_locs
+create_pblock {pblock_gn_htr_4[28].htr_4}
+resize_pblock {pblock_gn_htr_4[28].htr_4} -add CLOCKREGION_X0Y1:CLOCKREGION_X1Y0
+add_cells_to_pblock {pblock_gn_htr_4[28].htr_4} [get_cells [list {TCDS_1/gen_heater_4[28].heater_4}]] -clear_locs
+create_pblock {pblock_gn_htr_4[29].htr_4}
+resize_pblock {pblock_gn_htr_4[29].htr_4} -add CLOCKREGION_X2Y1:CLOCKREGION_X3Y0
+add_cells_to_pblock {pblock_gn_htr_4[29].htr_4} [get_cells [list {TCDS_1/gen_heater_4[29].heater_4}]] -clear_locs
+create_pblock {pblock_gn_htr_4[30].htr_4}
+resize_pblock {pblock_gn_htr_4[30].htr_4} -add CLOCKREGION_X4Y1:CLOCKREGION_X5Y0
+add_cells_to_pblock {pblock_gn_htr_4[30].htr_4} [get_cells [list {TCDS_1/gen_heater_4[30].heater_4}]] -clear_locs
+create_pblock {pblock_gn_htr_4[31].htr_4}
+resize_pblock {pblock_gn_htr_4[31].htr_4} -add CLOCKREGION_X6Y1:CLOCKREGION_X7Y0
+add_cells_to_pblock {pblock_gn_htr_4[31].htr_4} [get_cells [list {TCDS_1/gen_heater_4[31].heater_4}]] -clear_locs
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_pins.xdc b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_pins.xdc
new file mode 100644
index 0000000..fbe9f58
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_pins.xdc
@@ -0,0 +1,1167 @@
+# pin constraint file for the Apollo 6089-119 board.
+# VU13P (or VU9P) in A2577 package
+#
+# This board has two A2577 FPGA sites. One is the "primary" site, and the other is the
+# "secondary" site. This pin constraint file is usable for both sites. There are some wiring
+# differences on the circuit board. Any differences will be noted.
+#
+# The schematic prefixes of 'f1_' or 'f2_ are dropped from names. They appear on the
+# the schematics to differentiate signals, like 'f1_led_red' vs. 'f2_led_red'. In
+# the Vivado code, they are just 'led_red' for either of the two FPGA sites.
+#
+# The schematic prefixes of 'bc' and 'ac' are dropped from names. They appear
+# on the schematics to differentiate on which side of a coupling capacitor the
+# signal appears.
+#
+# Differential pair names start with 'p_' or 'n_'.
+#
+# Except for clock inputs, signals that can be bused together use bracketed,
+# numbered suffixes.
+
+#-------------------------------------------------
+# Important! Do not remove this constraint!
+# This property ensures that all unused pins are set to high impedance.
+# If the constraint is removed, all unused pins have to be set to HiZ in the top level file.
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
+#-------------------------------------------------
+
+#-------------------------------------------------
+# Important! Do not remove this constraint!
+# Refer to UG580 "SYSMON User Guide" for "Over Temperature Automatic Shutdown"
+# shutdown on over-temperature
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]
+#-------------------------------------------------
+
+#-------------------------------------------------
+# Set internal reference voltages to 0.90 on banks with I/O signals.
+# This is required for the HSTL and DIFF_HSTL I/O standards (if used)
+# ADD VU9P BANKS IF THAT IS THE FPGA BEING USED
+#VU13P SLR#0
+#set_property INTERNAL_VREF 0.90 [get_iobanks 61]
+set_property INTERNAL_VREF 0.90 [get_iobanks 62]
+#set_property INTERNAL_VREF 0.90 [get_iobanks 63]
+#VU13P SLR#1
+set_property INTERNAL_VREF 0.90 [get_iobanks 65]
+set_property INTERNAL_VREF 0.90 [get_iobanks 66]
+#VU13P SLR#2
+set_property INTERNAL_VREF 0.90 [get_iobanks 70]
+set_property INTERNAL_VREF 0.90 [get_iobanks 71]
+#VU13P SLR#3
+set_property INTERNAL_VREF 0.90 [get_iobanks 73]
+set_property INTERNAL_VREF 0.90 [get_iobanks 74]
+set_property INTERNAL_VREF 0.90 [get_iobanks 75]
+
+#-------------------------------------------------
+
+#-------------------------------------------------
+# 200 MHz system clock on bank 66
+# This is SLR#1 on both VU13P and VU9P
+
+# 'input' clk_200: 200 MHz clock (schematic name is "ac_f*_xtal_200")
+set_property IOSTANDARD LVDS [get_ports *_clk_200]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *_clk_200]
+set_property PACKAGE_PIN AT17 [get_ports p_clk_200 ]
+set_property PACKAGE_PIN AU16 [get_ports n_clk_200 ]
+#-------------------------------------------------
+
+#-------------------------------------------------
+# other clock inputs
+
+# A copy of the RefClk#0 used by the 12-channel FireFlys on the left side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *lf_x12_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *lf_x12_r0_clk]
+set_property PACKAGE_PIN P33 [get_ports p_lf_x12_r0_clk]
+set_property PACKAGE_PIN P34 [get_ports n_lf_x12_r0_clk]
+
+# A copy of the RefClk#0 used by the 4-channel FireFlys on the left side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *lf_x4_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *lf_x4_r0_clk]
+set_property PACKAGE_PIN N32 [get_ports p_lf_x4_r0_clk]
+set_property PACKAGE_PIN M32 [get_ports n_lf_x4_r0_clk]
+
+# A copy of the RefClk#0 used by the 12-channel FireFlys on the right side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *rt_x12_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *rt_x12_r0_clk]
+set_property PACKAGE_PIN R18 [get_ports p_rt_x12_r0_clk]
+set_property PACKAGE_PIN R17 [get_ports n_rt_x12_r0_clk]
+
+# A copy of the RefClk#0 used by the 4-channel FireFlys on the right side of the FPGA.
+# This can be the output of either refclk synthesizer R0A or R0B.
+set_property IOSTANDARD LVDS [get_ports *rt_x4_r0_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *rt_x4_r0_clk]
+set_property PACKAGE_PIN N19 [get_ports p_rt_x4_r0_clk]
+set_property PACKAGE_PIN N18 [get_ports n_rt_x4_r0_clk]
+#-------------------------------------------------
+
+#-----------------------------------------------
+# 'input' "fpga_identity" to differentiate FPGA#1 from FPGA#2.
+# The signal will be HI in FPGA#1 and LO in FPGA#2.
+set_property IOSTANDARD LVCMOS18 [get_ports fpga_identity]
+set_property PACKAGE_PIN B29 [get_ports fpga_identity]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# 'output' "led": 3 bits to light a tri-color LED
+# These use different pins on F1 vs. F2. The pins are unused on the "other" FPGA,
+# so each color for both FPGAs can be driven at the same time
+set_property IOSTANDARD LVCMOS18 [get_ports led_*]
+set_property PACKAGE_PIN A30 [get_ports led_f1_blue]
+set_property PACKAGE_PIN A29 [get_ports led_f1_green]
+set_property PACKAGE_PIN A28 [get_ports led_f1_red]
+
+set_property PACKAGE_PIN BL27 [get_ports led_f2_blue]
+set_property PACKAGE_PIN BL28 [get_ports led_f2_green]
+set_property PACKAGE_PIN BL30 [get_ports led_f2_red]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# 'input' "mcu_to_f": 1 bit trom the MCU
+# 'output' "f_to_mcu": 1 bit to the MCU
+# There is no currently defined use for these.
+set_property IOSTANDARD LVCMOS18 [get_ports mcu_to_f]
+set_property IOSTANDARD LVCMOS18 [get_ports f_to_mcu]
+set_property PACKAGE_PIN L33 [get_ports mcu_to_f]
+set_property PACKAGE_PIN M36 [get_ports f_to_mcu]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# 'output' "c2c_ok": 1 bit to the MCU
+# The FPGA should set this output HI when the chip-2-chip link is working.
+set_property IOSTANDARD LVCMOS18 [get_ports c2c_ok]
+set_property PACKAGE_PIN L35 [get_ports c2c_ok]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# I2C pins
+# The "sysmon" port can be accessed before the FPGA is configured.
+# The "generic" port requires a configured FPGA with an I2C module. The information
+# that can be accessed on the generic port is user-defined.
+set_property IOSTANDARD LVCMOS18 [get_ports i2c_s*]
+set_property PACKAGE_PIN BB16 [get_ports i2c_scl_f_sysmon]
+set_property PACKAGE_PIN BC16 [get_ports i2c_sda_f_sysmon]
+set_property PACKAGE_PIN V36 [get_ports i2c_scl_f_generic]
+set_property PACKAGE_PIN J32 [get_ports i2c_sda_f_generic]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# TCDS signals to/from the service blade and to/from the "other" FPGA
+#
+# There is an asymmetry between FPGA#1 (the "primary") and FPGA#2 (the "secondary").
+# The TCDS endpoint can be either the Zynq on the SM, or FPGA#1 on the CM.
+#
+# The primary ones are connected to GTY quad AB (120 on VU13P, 119 on VU9P).
+# If, for some reason, the primary quad can't be modified and FPGA#1 is the TCDS
+# endpoint, then TCDS signals to the Zynq and FPGA#2 can be connected
+# via GTY quad L (220 on VU13P, ??? on VU9P).
+#
+# If the Zynq on the SM is the TCDS endpoint, then both FPGAs only use port #0 for TCDS
+# signals and the two FPGAs are programmed identically.
+#
+# If FPGA#1 is the TCDS endpoint, then:
+# 1) TCDS signals from the ATCA backplane connect to port#0 on FPGA#1
+# 2) TCDS information is sent from FPGA#1 to FPGA#2 on port #3
+# 3) TCDS information is sent from FPGA#1 to the Zynq on the SM on port #2.
+
+# RefClk#0 for quad AB comes from REFCLK SYNTHESIZER R1A which can be driven by:
+# a) synth oscillator
+# b) HQ_CLK from the SM
+# b1) 320 MHz if FPGA#1 is the TCDS endpoint
+# b2) 40 MHz if the SM is the TCDS endpoint
+# c) Optional front panel connector for an external LVDS clock
+# quad AB
+set_property PACKAGE_PIN BD39 [get_ports p_lf_r0_ab]
+set_property PACKAGE_PIN BD40 [get_ports n_lf_r0_ab]
+
+# RefClk#1 comes from REFCLK SYNTHESIZER R1B which can be driven by:
+# a) synth oscillator
+# b) an output from EXTERNAL REFCLK SYNTH R1A
+# c) the 40 MHz TCDS RECOVERED CLOCK from FPGA #1
+# RefClk#1 is only connected on FPGA#1, and is only used when FPGA#1 is the TCDS endpoint.
+# quad AB
+set_property PACKAGE_PIN BC41 [get_ports p_lf_r1_ab]
+set_property PACKAGE_PIN BC42 [get_ports n_lf_r1_ab]
+# quad L
+set_property PACKAGE_PIN BC11 [get_ports p_lf_r1_l]
+set_property PACKAGE_PIN BC10 [get_ports n_lf_r1_l]
+
+# Port #0 is the main TCDS path. Both FPGAs use it when the Zynq on the SM is the
+# TCDS endpoint. Only FPGA#1 uses it when FPGA#1 is the TCDS endpoint.
+# Port #0 receive (schematic name is "con*_tcds_in")
+set_property PACKAGE_PIN BG32 [get_ports p_tcds_in]
+set_property PACKAGE_PIN BG33 [get_ports n_tcds_in]
+# Port #0 transmit (schematic name is "con*_tcds_out")
+set_property PACKAGE_PIN BH39 [get_ports p_tcds_out]
+set_property PACKAGE_PIN BH40 [get_ports n_tcds_out]
+
+# Port #2 is used to send TCDS signals between FPGA#1 and the Zynq when
+# FPGA#1 is the TCDS endpoint. Port #2 is not used when the Zynq on the SM is the
+# TCDS endpoint. Port #2 is not connected to anything on FPGA#2.
+# Port #2 receive (schematic name is "tcds_from_zynq")
+# quad AB
+set_property PACKAGE_PIN BJ32 [get_ports p_tcds_from_zynq_a]
+set_property PACKAGE_PIN BJ33 [get_ports n_tcds_from_zynq_a]
+# quad L
+set_property PACKAGE_PIN BJ20 [get_ports p_tcds_from_zynq_b]
+set_property PACKAGE_PIN BJ19 [get_ports n_tcds_from_zynq_b]
+# quad AB
+# Port #2 transmit (schematic name is "tcds_to_zynq")
+# quad AB
+set_property PACKAGE_PIN BJ37 [get_ports p_tcds_to_zynq_a]
+set_property PACKAGE_PIN BJ38 [get_ports n_tcds_to_zynq_a]
+# quad L
+set_property PACKAGE_PIN BJ15 [get_ports p_tcds_to_zynq_b]
+set_property PACKAGE_PIN BJ14 [get_ports n_tcds_to_zynq_b]
+
+# Port #3 is cross-connected between the two FPGAs. It is only used when FPGA#1
+# is the TCDS endpoint.
+# Port #3 receive
+# quad AB
+set_property PACKAGE_PIN BH34 [get_ports p_tcds_cross_recv_a]
+set_property PACKAGE_PIN BH35 [get_ports n_tcds_cross_recv_a]
+# quad L
+set_property PACKAGE_PIN BH18 [get_ports p_tcds_cross_recv_b]
+set_property PACKAGE_PIN BH17 [get_ports n_tcds_cross_recv_b]
+#Port #3 transmit
+# quad AB
+set_property PACKAGE_PIN BG37 [get_ports p_tcds_cross_xmit_a]
+set_property PACKAGE_PIN BG38 [get_ports n_tcds_cross_xmit_a]
+# quad L
+set_property PACKAGE_PIN BG15 [get_ports p_tcds_cross_xmit_b]
+set_property PACKAGE_PIN BG14 [get_ports n_tcds_cross_xmit_b]
+
+# Recovered 40 MHz TCDS clock output to feed REFCLK SYNTHESIZER R1B.
+# This is only connected on FPGA#1, and is only used when FPGA#1 is the
+# TCDS endpoint. On FPGA#2, these signals are not connected, but are reserved.
+set_property IOSTANDARD LVDS [get_ports *_tcds_recov_clk]
+set_property PACKAGE_PIN BJ26 [get_ports p_tcds_recov_clk]
+set_property PACKAGE_PIN BK26 [get_ports n_tcds_recov_clk]
+
+# 40 MHz TCDS clock connected to FPGA logic. This is used in the FPGA for two
+# purposes. The first is to generate high-speed processing clocks by multiplying
+# in an MMCM. The second is to synchronize processing to the 40 MHz LHC bunch crossing.
+set_property IOSTANDARD LVDS [get_ports *_tcds40_clk]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *_tcds40_clk]
+set_property PACKAGE_PIN AR17 [get_ports p_tcds40_clk ]
+set_property PACKAGE_PIN AR16 [get_ports n_tcds40_clk ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# AXI C2C signals
+# GTY transceiver reference clocks for AXI C2C link to SM.
+# Quad L (VU13P=220, VU9P=219)
+# RefClk#1 on BC11/BC10 is used for TCDS.
+set_property PACKAGE_PIN BD13 [get_ports p_rt_r0_l]
+set_property PACKAGE_PIN BD12 [get_ports n_rt_r0_l]
+
+# GTY AXI C2C links to the SM
+# 'input' "SM_TO_F": links from the Zynq on the SM
+# 'output' "F_TO_SM": links to the Zynq on the SM
+# Quad L (VU13P=220, VU9P=219)
+# Port #0 receive
+set_property PACKAGE_PIN BG20 [get_ports {p_mgt_sm_to_f[1]} ]
+set_property PACKAGE_PIN BG19 [get_ports {n_mgt_sm_to_f[1]} ]
+# Port #0 transmit
+set_property PACKAGE_PIN BH13 [get_ports {p_mgt_f_to_sm[1]} ]
+set_property PACKAGE_PIN BH12 [get_ports {n_mgt_f_to_sm[1]} ]
+# Port #1 receive
+set_property PACKAGE_PIN BF18 [get_ports {p_mgt_sm_to_f[2]} ]
+set_property PACKAGE_PIN BF17 [get_ports {n_mgt_sm_to_f[2]} ]
+# Port #1 transmit
+set_property PACKAGE_PIN BF13 [get_ports {p_mgt_f_to_sm[2]} ]
+set_property PACKAGE_PIN BF12 [get_ports {n_mgt_f_to_sm[2]} ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 12-lane FireFLy #1
+# Quad AD (VU13P=122, VU9P=121)
+# Use the same clocks for adjacent quads AC and AE (VU13P=121/122/123, VU9P=120/121/122)
+set_property PACKAGE_PIN AY39 [get_ports p_lf_r0_ad]
+set_property PACKAGE_PIN AY40 [get_ports n_lf_r0_ad]
+set_property PACKAGE_PIN AW41 [get_ports p_lf_r1_ad]
+set_property PACKAGE_PIN AW42 [get_ports n_lf_r1_ad]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 12-lane FireFLy #2
+# Quad R (VU13P=126, VU9P=125)
+# Use the same clocks for adjacent quads Q and S (VU13P=125/126/127, VU9P=124/125/126)
+set_property PACKAGE_PIN AM39 [get_ports p_lf_r0_r]
+set_property PACKAGE_PIN AM40 [get_ports n_lf_r0_r]
+set_property PACKAGE_PIN AL41 [get_ports p_lf_r1_r]
+set_property PACKAGE_PIN AL42 [get_ports n_lf_r1_r]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 12-lane FireFLy #3
+# Quad Y (VU13P=133, VU9P=132)
+# Use the same clocks for adjacent quads X and Z (VU13P=132/133/134, VU9P=131/132/133)
+set_property PACKAGE_PIN N41 [get_ports p_lf_r0_y]
+set_property PACKAGE_PIN N42 [get_ports n_lf_r0_y]
+set_property PACKAGE_PIN M39 [get_ports p_lf_r1_y]
+set_property PACKAGE_PIN M40 [get_ports n_lf_r1_y]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 4-lane FireFLy #4
+# Quad AF (VU13P=124, VU9P=123)
+# This clock is not shared with any adjacent quads.
+set_property PACKAGE_PIN AT39 [get_ports p_lf_r0_af]
+set_property PACKAGE_PIN AT40 [get_ports n_lf_r0_af]
+set_property PACKAGE_PIN AR41 [get_ports p_lf_r1_af]
+set_property PACKAGE_PIN AR42 [get_ports n_lf_r1_af]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for 4-lane FireFLy #5,6,7
+# Quad U (VU13P=129, VU9P=128)
+# Use the same clocks for adjacent quads T and V (VU13P=128/129/130, VU9P=127/128)
+# FireFly #7 is in a different SLR on the VU9P, so an additional clock is needed
+# for quad V (129) on the VU9P package.
+set_property PACKAGE_PIN AA41 [get_ports p_lf_r0_u]
+set_property PACKAGE_PIN AA42 [get_ports n_lf_r0_u]
+set_property PACKAGE_PIN Y39 [get_ports p_lf_r1_u]
+set_property PACKAGE_PIN Y40 [get_ports n_lf_r1_u]
+# RefClk#1 on quad V is not connected.
+# Quad V (VU13P=130, VU9P=129)
+set_property PACKAGE_PIN W41 [get_ports p_lf_r0_v]
+set_property PACKAGE_PIN W42 [get_ports n_lf_r0_v]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 12-lane FireFly#3
+# Quad N (VU13P=222, VU9P=221)
+# Use the same clocks for adjacent quads M and O (VU13P=221/222/223, VU9P=220/221/222)
+set_property PACKAGE_PIN AY13 [get_ports p_rt_r0_n]
+set_property PACKAGE_PIN AY12 [get_ports n_rt_r0_n]
+set_property PACKAGE_PIN AW11 [get_ports p_rt_r1_n]
+set_property PACKAGE_PIN AW10 [get_ports n_rt_r1_n]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 4-lane FireFly#5,6,7
+# Quad B (VU13P=226, VU9P=225)
+# Use the same clocks for adjacent quads A and C (VU13P=225/226/227, VU9P=224/225/226)
+set_property PACKAGE_PIN AM13 [get_ports p_rt_r0_b ]
+set_property PACKAGE_PIN AM12 [get_ports n_rt_r0_b]
+set_property PACKAGE_PIN AL11 [get_ports p_rt_r1_b]
+set_property PACKAGE_PIN AL10 [get_ports n_rt_r1_b]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 12-lane FireFly#2
+# Quad E (VU13P=229, VU9P=228)
+# Use the same clocks for adjacent quads D and F (VU13P=228/229/230, VU9P=227/228)
+# FireFly #2 is split between different SLRs on the VU9P, so an additional clock is needed
+# for quad F (229) on the VU9P package. However, there are not enough sources for RefClk#1,
+# so if Quad F on the VU9P package needs a RefClk#1, it will have to use the clock
+# from the adjacent quad G.
+set_property PACKAGE_PIN AA11 [get_ports p_rt_r0_e]
+set_property PACKAGE_PIN AA10 [get_ports n_rt_r0_e]
+set_property PACKAGE_PIN Y13 [get_ports p_rt_r1_e]
+set_property PACKAGE_PIN Y12 [get_ports n_rt_r1_e]
+# Quad F (VU13P=230, VU9P=229)
+set_property PACKAGE_PIN W10 [get_ports n_rt_r0_f]
+set_property PACKAGE_PIN W11 [get_ports p_rt_r0_f]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 4-lane FireFly#4
+# Quad G (VU13P=231, VU9P=230)
+# This quad is not used on FPGA#2.
+# It is used on FPGA#1 to connect to quad P on FPGA#2
+set_property PACKAGE_PIN U11 [get_ports p_rt_r0_g]
+set_property PACKAGE_PIN U10 [get_ports n_rt_r0_g]
+set_property PACKAGE_PIN T13 [get_ports p_rt_r1_g]
+set_property PACKAGE_PIN T12 [get_ports n_rt_r1_g]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# Quad P (VU13P=224, VU9P=223)
+# This quad is not used on FPGA#1.
+# It is used on FPGA#2 to connect to quad G on FPGA#1
+set_property PACKAGE_PIN AT13 [get_ports p_rt_r0_p]
+set_property PACKAGE_PIN AT12 [get_ports n_rt_r0_p]
+set_property PACKAGE_PIN AR11 [get_ports p_rt_r1_p]
+set_property PACKAGE_PIN AR10 [get_ports n_rt_r1_p]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver reference clocks for FPGA-to-FPGA links
+# On single-FPGA boards with FPGA#2 jumpers, this will also
+# be the secondary 12-lane FireFly#1
+# Quad I (VU13P=233, VU9P=232)
+# Use the same clocks for adjacent quads H and J (VU13P=232/233/234, VU9P=231/232/233)
+set_property PACKAGE_PIN N11 [get_ports p_rt_r0_i]
+set_property PACKAGE_PIN N10 [get_ports n_rt_r0_i]
+set_property PACKAGE_PIN M13 [get_ports p_rt_r1_i]
+set_property PACKAGE_PIN M12 [get_ports n_rt_r1_i]
+#-----------------------------------------------
+
+
+
+#-----------------------------------------------
+# firefly#1 receivers
+# Uses quads AC, AD, AE (VU13P=121/122/123, VU9P=120/121/122)
+# Clocked from quad AD (VU13P=122, VU9P=121)
+set_property PACKAGE_PIN BK34 [get_ports { p_ff1_recv[0] } ]
+set_property PACKAGE_PIN BK35 [get_ports { n_ff1_recv[0] } ]
+set_property PACKAGE_PIN BL32 [get_ports { p_ff1_recv[1] } ]
+set_property PACKAGE_PIN BL33 [get_ports { n_ff1_recv[1] } ]
+set_property PACKAGE_PIN BC50 [get_ports { p_ff1_recv[10] } ]
+set_property PACKAGE_PIN BC51 [get_ports { n_ff1_recv[10] } ]
+set_property PACKAGE_PIN BB48 [get_ports { p_ff1_recv[11] } ]
+set_property PACKAGE_PIN BB49 [get_ports { n_ff1_recv[11] } ]
+set_property PACKAGE_PIN BL46 [get_ports { p_ff1_recv[2] } ]
+set_property PACKAGE_PIN BL47 [get_ports { n_ff1_recv[2] } ]
+set_property PACKAGE_PIN BJ46 [get_ports { p_ff1_recv[3] } ]
+set_property PACKAGE_PIN BJ47 [get_ports { n_ff1_recv[3] } ]
+set_property PACKAGE_PIN BH48 [get_ports { p_ff1_recv[4] } ]
+set_property PACKAGE_PIN BH49 [get_ports { n_ff1_recv[4] } ]
+set_property PACKAGE_PIN BG50 [get_ports { p_ff1_recv[5] } ]
+set_property PACKAGE_PIN BG51 [get_ports { n_ff1_recv[5] } ]
+set_property PACKAGE_PIN BG46 [get_ports { p_ff1_recv[6] } ]
+set_property PACKAGE_PIN BG47 [get_ports { n_ff1_recv[6] } ]
+set_property PACKAGE_PIN BF48 [get_ports { p_ff1_recv[7] } ]
+set_property PACKAGE_PIN BF49 [get_ports { n_ff1_recv[7] } ]
+set_property PACKAGE_PIN BE50 [get_ports { p_ff1_recv[8] } ]
+set_property PACKAGE_PIN BE51 [get_ports { n_ff1_recv[8] } ]
+set_property PACKAGE_PIN BD48 [get_ports { p_ff1_recv[9] } ]
+set_property PACKAGE_PIN BD49 [get_ports { n_ff1_recv[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#1 transmitters
+# Uses quads AC, AD, AE (VU13P=121/122/123, VU9P=120/121/122)
+# Clocked from quad AD (VU13P=122, VU9P=121)
+set_property PACKAGE_PIN BL37 [get_ports { p_ff1_xmit[0] } ]
+set_property PACKAGE_PIN BL38 [get_ports { n_ff1_xmit[0] } ]
+set_property PACKAGE_PIN BK39 [get_ports { p_ff1_xmit[1] } ]
+set_property PACKAGE_PIN BK40 [get_ports { n_ff1_xmit[1] } ]
+set_property PACKAGE_PIN BC45 [get_ports { p_ff1_xmit[10] } ]
+set_property PACKAGE_PIN BC46 [get_ports { n_ff1_xmit[10] } ]
+set_property PACKAGE_PIN BB43 [get_ports { p_ff1_xmit[11] } ]
+set_property PACKAGE_PIN BB44 [get_ports { n_ff1_xmit[11] } ]
+set_property PACKAGE_PIN BL41 [get_ports { p_ff1_xmit[2] } ]
+set_property PACKAGE_PIN BL42 [get_ports { n_ff1_xmit[2] } ]
+set_property PACKAGE_PIN BK43 [get_ports { p_ff1_xmit[3] } ]
+set_property PACKAGE_PIN BK44 [get_ports { n_ff1_xmit[3] } ]
+set_property PACKAGE_PIN BG41 [get_ports { p_ff1_xmit[4] } ]
+set_property PACKAGE_PIN BG42 [get_ports { n_ff1_xmit[4] } ]
+set_property PACKAGE_PIN BJ41 [get_ports { p_ff1_xmit[5] } ]
+set_property PACKAGE_PIN BJ42 [get_ports { n_ff1_xmit[5] } ]
+set_property PACKAGE_PIN BH43 [get_ports { p_ff1_xmit[6] } ]
+set_property PACKAGE_PIN BH44 [get_ports { n_ff1_xmit[6] } ]
+set_property PACKAGE_PIN BF43 [get_ports { p_ff1_xmit[7] } ]
+set_property PACKAGE_PIN BF44 [get_ports { n_ff1_xmit[7] } ]
+set_property PACKAGE_PIN BE45 [get_ports { p_ff1_xmit[8] } ]
+set_property PACKAGE_PIN BE46 [get_ports { n_ff1_xmit[8] } ]
+set_property PACKAGE_PIN BD43 [get_ports { p_ff1_xmit[9] } ]
+set_property PACKAGE_PIN BD44 [get_ports { n_ff1_xmit[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#2 receivers
+# Uses quads Q, R, S (VU13P=125/126/127, VU9P=124/125/126)
+# Clocked from quad R (VU13P=126, VU9P=125)
+set_property PACKAGE_PIN AU50 [get_ports { p_ff2_recv[0] } ]
+set_property PACKAGE_PIN AU51 [get_ports { n_ff2_recv[0] } ]
+set_property PACKAGE_PIN AT48 [get_ports { p_ff2_recv[1] } ]
+set_property PACKAGE_PIN AT49 [get_ports { n_ff2_recv[1] } ]
+set_property PACKAGE_PIN AG50 [get_ports { p_ff2_recv[10] } ]
+set_property PACKAGE_PIN AG51 [get_ports { n_ff2_recv[10] } ]
+set_property PACKAGE_PIN AF48 [get_ports { p_ff2_recv[11] } ]
+set_property PACKAGE_PIN AF49 [get_ports { n_ff2_recv[11] } ]
+set_property PACKAGE_PIN AR50 [get_ports { p_ff2_recv[2] } ]
+set_property PACKAGE_PIN AR51 [get_ports { n_ff2_recv[2] } ]
+set_property PACKAGE_PIN AP48 [get_ports { p_ff2_recv[3] } ]
+set_property PACKAGE_PIN AP49 [get_ports { n_ff2_recv[3] } ]
+set_property PACKAGE_PIN AN50 [get_ports { p_ff2_recv[4] } ]
+set_property PACKAGE_PIN AN51 [get_ports { n_ff2_recv[4] } ]
+set_property PACKAGE_PIN AM48 [get_ports { p_ff2_recv[5] } ]
+set_property PACKAGE_PIN AM49 [get_ports { n_ff2_recv[5] } ]
+set_property PACKAGE_PIN AL50 [get_ports { p_ff2_recv[6] } ]
+set_property PACKAGE_PIN AL51 [get_ports { n_ff2_recv[6] } ]
+set_property PACKAGE_PIN AK48 [get_ports { p_ff2_recv[7] } ]
+set_property PACKAGE_PIN AK49 [get_ports { n_ff2_recv[7] } ]
+set_property PACKAGE_PIN AJ50 [get_ports { p_ff2_recv[8] } ]
+set_property PACKAGE_PIN AJ51 [get_ports { n_ff2_recv[8] } ]
+set_property PACKAGE_PIN AH48 [get_ports { p_ff2_recv[9] } ]
+set_property PACKAGE_PIN AH49 [get_ports { n_ff2_recv[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#2 transmitters
+# Uses quads Q, R, S (VU13P=125/126/127, VU9P=124/125/126)
+# Clocked from quad R (VU13P=126, VU9P=125)
+set_property PACKAGE_PIN AU45 [get_ports { p_ff2_xmit[0] } ]
+set_property PACKAGE_PIN AU46 [get_ports { n_ff2_xmit[0] } ]
+set_property PACKAGE_PIN AT43 [get_ports { p_ff2_xmit[1] } ]
+set_property PACKAGE_PIN AT44 [get_ports { n_ff2_xmit[1] } ]
+set_property PACKAGE_PIN AG45 [get_ports { p_ff2_xmit[10] } ]
+set_property PACKAGE_PIN AG46 [get_ports { n_ff2_xmit[10] } ]
+set_property PACKAGE_PIN AF43 [get_ports { p_ff2_xmit[11] } ]
+set_property PACKAGE_PIN AF44 [get_ports { n_ff2_xmit[11] } ]
+set_property PACKAGE_PIN AR45 [get_ports { p_ff2_xmit[2] } ]
+set_property PACKAGE_PIN AR46 [get_ports { n_ff2_xmit[2] } ]
+set_property PACKAGE_PIN AP43 [get_ports { p_ff2_xmit[3] } ]
+set_property PACKAGE_PIN AP44 [get_ports { n_ff2_xmit[3] } ]
+set_property PACKAGE_PIN AN45 [get_ports { p_ff2_xmit[4] } ]
+set_property PACKAGE_PIN AN46 [get_ports { n_ff2_xmit[4] } ]
+set_property PACKAGE_PIN AM43 [get_ports { p_ff2_xmit[5] } ]
+set_property PACKAGE_PIN AM44 [get_ports { n_ff2_xmit[5] } ]
+set_property PACKAGE_PIN AL45 [get_ports { p_ff2_xmit[6] } ]
+set_property PACKAGE_PIN AL46 [get_ports { n_ff2_xmit[6] } ]
+set_property PACKAGE_PIN AK43 [get_ports { p_ff2_xmit[7] } ]
+set_property PACKAGE_PIN AK44 [get_ports { n_ff2_xmit[7] } ]
+set_property PACKAGE_PIN AJ45 [get_ports { p_ff2_xmit[8] } ]
+set_property PACKAGE_PIN AJ46 [get_ports { n_ff2_xmit[8] } ]
+set_property PACKAGE_PIN AH43 [get_ports { p_ff2_xmit[9] } ]
+set_property PACKAGE_PIN AH44 [get_ports { n_ff2_xmit[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#3 receivers
+# Uses quads X, Y, Z (VU13P=132/133/134, VU9P=131/132/133)
+# Clocked from quad Y (VU13P=133, VU9P=132)
+set_property PACKAGE_PIN J50 [get_ports { p_ff3_recv[0] } ]
+set_property PACKAGE_PIN J51 [get_ports { n_ff3_recv[0] } ]
+set_property PACKAGE_PIN H48 [get_ports { p_ff3_recv[1] } ]
+set_property PACKAGE_PIN H49 [get_ports { n_ff3_recv[1] } ]
+set_property PACKAGE_PIN B34 [get_ports { p_ff3_recv[10] } ]
+set_property PACKAGE_PIN B35 [get_ports { n_ff3_recv[10] } ]
+set_property PACKAGE_PIN C32 [get_ports { p_ff3_recv[11] } ]
+set_property PACKAGE_PIN C33 [get_ports { n_ff3_recv[11] } ]
+set_property PACKAGE_PIN G50 [get_ports { p_ff3_recv[2] } ]
+set_property PACKAGE_PIN G51 [get_ports { n_ff3_recv[2] } ]
+set_property PACKAGE_PIN F48 [get_ports { p_ff3_recv[3] } ]
+set_property PACKAGE_PIN F49 [get_ports { n_ff3_recv[3] } ]
+set_property PACKAGE_PIN E50 [get_ports { p_ff3_recv[4] } ]
+set_property PACKAGE_PIN E51 [get_ports { n_ff3_recv[4] } ]
+set_property PACKAGE_PIN D48 [get_ports { p_ff3_recv[5] } ]
+set_property PACKAGE_PIN D49 [get_ports { n_ff3_recv[5] } ]
+set_property PACKAGE_PIN E46 [get_ports { p_ff3_recv[6] } ]
+set_property PACKAGE_PIN E47 [get_ports { n_ff3_recv[6] } ]
+set_property PACKAGE_PIN C46 [get_ports { p_ff3_recv[7] } ]
+set_property PACKAGE_PIN C47 [get_ports { n_ff3_recv[7] } ]
+set_property PACKAGE_PIN A46 [get_ports { p_ff3_recv[8] } ]
+set_property PACKAGE_PIN A47 [get_ports { n_ff3_recv[8] } ]
+set_property PACKAGE_PIN A32 [get_ports { p_ff3_recv[9] } ]
+set_property PACKAGE_PIN A33 [get_ports { n_ff3_recv[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#3 transmitters
+# Uses quads X, Y, Z (VU13P=132/133/134, VU9P=131/132/133)
+# Clocked from quad Y (VU13P=133, VU9P=132)
+set_property PACKAGE_PIN J45 [get_ports { p_ff3_xmit[0] } ]
+set_property PACKAGE_PIN J46 [get_ports { n_ff3_xmit[0] } ]
+set_property PACKAGE_PIN H43 [get_ports { p_ff3_xmit[1] } ]
+set_property PACKAGE_PIN H44 [get_ports { n_ff3_xmit[1] } ]
+set_property PACKAGE_PIN A37 [get_ports { p_ff3_xmit[10] } ]
+set_property PACKAGE_PIN A38 [get_ports { n_ff3_xmit[10] } ]
+set_property PACKAGE_PIN C37 [get_ports { p_ff3_xmit[11] } ]
+set_property PACKAGE_PIN C38 [get_ports { n_ff3_xmit[11] } ]
+set_property PACKAGE_PIN G45 [get_ports { p_ff3_xmit[2] } ]
+set_property PACKAGE_PIN G46 [get_ports { n_ff3_xmit[2] } ]
+set_property PACKAGE_PIN F43 [get_ports { p_ff3_xmit[3] } ]
+set_property PACKAGE_PIN F44 [get_ports { n_ff3_xmit[3] } ]
+set_property PACKAGE_PIN D43 [get_ports { p_ff3_xmit[4] } ]
+set_property PACKAGE_PIN D44 [get_ports { n_ff3_xmit[4] } ]
+set_property PACKAGE_PIN B43 [get_ports { p_ff3_xmit[5] } ]
+set_property PACKAGE_PIN B44 [get_ports { n_ff3_xmit[5] } ]
+set_property PACKAGE_PIN C41 [get_ports { p_ff3_xmit[6] } ]
+set_property PACKAGE_PIN C42 [get_ports { n_ff3_xmit[6] } ]
+set_property PACKAGE_PIN E41 [get_ports { p_ff3_xmit[7] } ]
+set_property PACKAGE_PIN E42 [get_ports { n_ff3_xmit[7] } ]
+set_property PACKAGE_PIN A41 [get_ports { p_ff3_xmit[8] } ]
+set_property PACKAGE_PIN A42 [get_ports { n_ff3_xmit[8] } ]
+set_property PACKAGE_PIN B39 [get_ports { p_ff3_xmit[9] } ]
+set_property PACKAGE_PIN B40 [get_ports { n_ff3_xmit[9] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#4 receivers
+# Uses quad AF (VU13P=124, VU9P=123)
+# Clocked from quad AF (VU13P=124, VU9P=123)
+set_property PACKAGE_PIN BA50 [get_ports { p_ff4_recv[0] } ]
+set_property PACKAGE_PIN BA51 [get_ports { n_ff4_recv[0] } ]
+set_property PACKAGE_PIN AY48 [get_ports { p_ff4_recv[1] } ]
+set_property PACKAGE_PIN AY49 [get_ports { n_ff4_recv[1] } ]
+set_property PACKAGE_PIN AW50 [get_ports { p_ff4_recv[2] } ]
+set_property PACKAGE_PIN AW51 [get_ports { n_ff4_recv[2] } ]
+set_property PACKAGE_PIN AV48 [get_ports { p_ff4_recv[3] } ]
+set_property PACKAGE_PIN AV49 [get_ports { n_ff4_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#4 transmitters
+# Uses quad AF (VU13P=124, VU9P=123)
+# Clocked from quad AF (VU13P=124, VU9P=123)
+set_property PACKAGE_PIN BA45 [get_ports { p_ff4_xmit[0] } ]
+set_property PACKAGE_PIN BA46 [get_ports { n_ff4_xmit[0] } ]
+set_property PACKAGE_PIN AY43 [get_ports { p_ff4_xmit[1] } ]
+set_property PACKAGE_PIN AY44 [get_ports { n_ff4_xmit[1] } ]
+set_property PACKAGE_PIN AW45 [get_ports { p_ff4_xmit[2] } ]
+set_property PACKAGE_PIN AW46 [get_ports { n_ff4_xmit[2] } ]
+set_property PACKAGE_PIN AV43 [get_ports { p_ff4_xmit[3] } ]
+set_property PACKAGE_PIN AV44 [get_ports { n_ff4_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#5 receivers
+# Uses quad T (VU13P=128, VU9P=127)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AE50 [get_ports { p_ff5_recv[0] } ]
+set_property PACKAGE_PIN AE51 [get_ports { n_ff5_recv[0] } ]
+set_property PACKAGE_PIN AD48 [get_ports { p_ff5_recv[1] } ]
+set_property PACKAGE_PIN AD49 [get_ports { n_ff5_recv[1] } ]
+set_property PACKAGE_PIN AC50 [get_ports { p_ff5_recv[2] } ]
+set_property PACKAGE_PIN AC51 [get_ports { n_ff5_recv[2] } ]
+set_property PACKAGE_PIN AB48 [get_ports { p_ff5_recv[3] } ]
+set_property PACKAGE_PIN AB49 [get_ports { n_ff5_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#5 transmitters
+# Uses quad T (VU13P=128, VU9P=127)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AE45 [get_ports { p_ff5_xmit[0] } ]
+set_property PACKAGE_PIN AE46 [get_ports { n_ff5_xmit[0] } ]
+set_property PACKAGE_PIN AD43 [get_ports { p_ff5_xmit[1] } ]
+set_property PACKAGE_PIN AD44 [get_ports { n_ff5_xmit[1] } ]
+set_property PACKAGE_PIN AC45 [get_ports { p_ff5_xmit[2] } ]
+set_property PACKAGE_PIN AC46 [get_ports { n_ff5_xmit[2] } ]
+set_property PACKAGE_PIN AB43 [get_ports { p_ff5_xmit[3] } ]
+set_property PACKAGE_PIN AB44 [get_ports { n_ff5_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#6 receivers
+# Uses quad U (VU13P=129, VU9P=128)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AA50 [get_ports { p_ff6_recv[0] } ]
+set_property PACKAGE_PIN AA51 [get_ports { n_ff6_recv[0] } ]
+set_property PACKAGE_PIN Y48 [get_ports { p_ff6_recv[1] } ]
+set_property PACKAGE_PIN Y49 [get_ports { n_ff6_recv[1] } ]
+set_property PACKAGE_PIN W50 [get_ports { p_ff6_recv[2] } ]
+set_property PACKAGE_PIN W51 [get_ports { n_ff6_recv[2] } ]
+set_property PACKAGE_PIN V48 [get_ports { p_ff6_recv[3] } ]
+set_property PACKAGE_PIN V49 [get_ports { n_ff6_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#6 transmitters
+# Uses quad U (VU13P=129, VU9P=128)
+# Clocked from quad U (VU13P=129, VU9P=128)
+set_property PACKAGE_PIN AA45 [get_ports { p_ff6_xmit[0] } ]
+set_property PACKAGE_PIN AA46 [get_ports { n_ff6_xmit[0] } ]
+set_property PACKAGE_PIN Y43 [get_ports { p_ff6_xmit[1] } ]
+set_property PACKAGE_PIN Y44 [get_ports { n_ff6_xmit[1] } ]
+set_property PACKAGE_PIN W45 [get_ports { p_ff6_xmit[2] } ]
+set_property PACKAGE_PIN W46 [get_ports { n_ff6_xmit[2] } ]
+set_property PACKAGE_PIN V43 [get_ports { p_ff6_xmit[3] } ]
+set_property PACKAGE_PIN V44 [get_ports { n_ff6_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#7 receivers
+# Uses quad V (VU13P=130, VU9P=129)
+# In the VU9P, this is in a different SLR than FireFly#5,6
+# Clocked from quad U on VU13P (VU13P=129)
+# Clocked from quad V on VU9P (VU9P=129)
+set_property PACKAGE_PIN U50 [get_ports { p_ff7_recv[0] } ]
+set_property PACKAGE_PIN U51 [get_ports { n_ff7_recv[0] } ]
+set_property PACKAGE_PIN T48 [get_ports { p_ff7_recv[1] } ]
+set_property PACKAGE_PIN T49 [get_ports { n_ff7_recv[1] } ]
+set_property PACKAGE_PIN R50 [get_ports { p_ff7_recv[2] } ]
+set_property PACKAGE_PIN R51 [get_ports { n_ff7_recv[2] } ]
+set_property PACKAGE_PIN P48 [get_ports { p_ff7_recv[3] } ]
+set_property PACKAGE_PIN P49 [get_ports { n_ff7_recv[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# firefly#7 transmitters
+# Uses quad V (VU13P=130, VU9P=129)
+# In the VU9P, this is in a different SLR than FireFly#5,6
+# Clocked from quad U on VU13P (VU13P=129)
+# Clocked from quad V on VU9P (VU9P=129)
+set_property PACKAGE_PIN U45 [get_ports { p_ff7_xmit[0] } ]
+set_property PACKAGE_PIN U46 [get_ports { n_ff7_xmit[0] } ]
+set_property PACKAGE_PIN T43 [get_ports { p_ff7_xmit[1] } ]
+set_property PACKAGE_PIN T44 [get_ports { n_ff7_xmit[1] } ]
+set_property PACKAGE_PIN R45 [get_ports { p_ff7_xmit[2] } ]
+set_property PACKAGE_PIN R46 [get_ports { n_ff7_xmit[2] } ]
+set_property PACKAGE_PIN P43 [get_ports { p_ff7_xmit[3] } ]
+set_property PACKAGE_PIN P44 [get_ports { n_ff7_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad A connects to FPGA#2 quad F
+# FPGA#1 quad F connects to FPGA#2 quad A
+# Quad A (VU13P=225, VU9P=224)
+# Quad F (VU13P=230, VU9P=229)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad A will also
+# connect to the secondary 4-lane FireFly#7
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad F will also
+# connect to the secondary 12-lane FireFly#2
+# FPGA#1 and FPGA#2 quad A are clocked from quad B (VU13P=226, VU9P=225)
+# FPGA#1 and FPGA#2 quad F is clocked from quad F (VU13P=230, VU9P=229)
+#
+# Quad A receivers
+set_property PACKAGE_PIN AU2 [get_ports { p_a_recv[0] } ]
+set_property PACKAGE_PIN AU1 [get_ports { n_a_recv[0] } ]
+set_property PACKAGE_PIN AT4 [get_ports { p_a_recv[1] } ]
+set_property PACKAGE_PIN AT3 [get_ports { n_a_recv[1] } ]
+set_property PACKAGE_PIN AR2 [get_ports { p_a_recv[2] } ]
+set_property PACKAGE_PIN AR1 [get_ports { n_a_recv[2] } ]
+set_property PACKAGE_PIN AP4 [get_ports { p_a_recv[3] } ]
+set_property PACKAGE_PIN AP3 [get_ports { n_a_recv[3] } ]
+
+# Quad A transmitters
+set_property PACKAGE_PIN AU7 [get_ports { p_a_xmit[0] } ]
+set_property PACKAGE_PIN AU6 [get_ports { n_a_xmit[0] } ]
+set_property PACKAGE_PIN AT9 [get_ports { p_a_xmit[1] } ]
+set_property PACKAGE_PIN AT8 [get_ports { n_a_xmit[1] } ]
+set_property PACKAGE_PIN AR7 [get_ports { p_a_xmit[2] } ]
+set_property PACKAGE_PIN AR6 [get_ports { n_a_xmit[2] } ]
+set_property PACKAGE_PIN AP9 [get_ports { p_a_xmit[3] } ]
+set_property PACKAGE_PIN AP8 [get_ports { n_a_xmit[3] } ]
+
+# Quad F receivers
+set_property PACKAGE_PIN U2 [get_ports { p_f_recv[0] } ]
+set_property PACKAGE_PIN U1 [get_ports { n_f_recv[0] } ]
+set_property PACKAGE_PIN T4 [get_ports { p_f_recv[1] } ]
+set_property PACKAGE_PIN T3 [get_ports { n_f_recv[1] } ]
+set_property PACKAGE_PIN R2 [get_ports { p_f_recv[2] } ]
+set_property PACKAGE_PIN R1 [get_ports { n_f_recv[2] } ]
+set_property PACKAGE_PIN P4 [get_ports { p_f_recv[3] } ]
+set_property PACKAGE_PIN P3 [get_ports { n_f_recv[3] } ]
+
+#Quad F transmitters
+set_property PACKAGE_PIN U7 [get_ports { p_f_xmit[0] } ]
+set_property PACKAGE_PIN U6 [get_ports { n_f_xmit[0] } ]
+set_property PACKAGE_PIN T9 [get_ports { p_f_xmit[1] } ]
+set_property PACKAGE_PIN T8 [get_ports { n_f_xmit[1] } ]
+set_property PACKAGE_PIN R7 [get_ports { p_f_xmit[2] } ]
+set_property PACKAGE_PIN R6 [get_ports { n_f_xmit[2] } ]
+set_property PACKAGE_PIN P9 [get_ports { p_f_xmit[3] } ]
+set_property PACKAGE_PIN P8 [get_ports { n_f_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad B connects to FPGA#2 quad E
+# FPGA#1 quad E connects to FPGA#2 quad B
+# Quad B (VU13P=226, VU9P=225)
+# Quad E (VU13P=229, VU9P=228)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad B will also
+# connect to the secondary 4-lane FireFly#6
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad E will also
+# connect to the secondary 12-lane FireFly#2
+# FPGA#1 and FPGA#2 quad B are clocked from quad B (VU13P=226, VU9P=225)
+# FPGA#1 and FPGA#2 quad E is clocked from quad E (VU13P=229, VU9P=228)
+#
+# Quad B receivers
+set_property PACKAGE_PIN AN2 [get_ports { p_b_recv[0] } ]
+set_property PACKAGE_PIN AN1 [get_ports { n_b_recv[0] } ]
+set_property PACKAGE_PIN AM4 [get_ports { p_b_recv[1] } ]
+set_property PACKAGE_PIN AM3 [get_ports { n_b_recv[1] } ]
+set_property PACKAGE_PIN AL2 [get_ports { p_b_recv[2] } ]
+set_property PACKAGE_PIN AL1 [get_ports { n_b_recv[2] } ]
+set_property PACKAGE_PIN AK4 [get_ports { p_b_recv[3] } ]
+set_property PACKAGE_PIN AK3 [get_ports { n_b_recv[3] } ]
+
+# Quad B transmitters
+set_property PACKAGE_PIN AN7 [get_ports { p_b_xmit[0] } ]
+set_property PACKAGE_PIN AN6 [get_ports { n_b_xmit[0] } ]
+set_property PACKAGE_PIN AM9 [get_ports { p_b_xmit[1] } ]
+set_property PACKAGE_PIN AM8 [get_ports { n_b_xmit[1] } ]
+set_property PACKAGE_PIN AL7 [get_ports { p_b_xmit[2] } ]
+set_property PACKAGE_PIN AL6 [get_ports { n_b_xmit[2] } ]
+set_property PACKAGE_PIN AK9 [get_ports { p_b_xmit[3] } ]
+set_property PACKAGE_PIN AK8 [get_ports { n_b_xmit[3] } ]
+
+# Quad E receivers
+set_property PACKAGE_PIN AA2 [get_ports { p_e_recv[0] } ]
+set_property PACKAGE_PIN AA1 [get_ports { n_e_recv[0] } ]
+set_property PACKAGE_PIN Y4 [get_ports { p_e_recv[1] } ]
+set_property PACKAGE_PIN Y3 [get_ports { n_e_recv[1] } ]
+set_property PACKAGE_PIN W2 [get_ports { p_e_recv[2] } ]
+set_property PACKAGE_PIN W1 [get_ports { n_e_recv[2] } ]
+set_property PACKAGE_PIN V4 [get_ports { p_e_recv[3] } ]
+set_property PACKAGE_PIN V3 [get_ports { n_e_recv[3] } ]
+
+# Quad E transmitters
+set_property PACKAGE_PIN AA7 [get_ports { p_e_xmit[0] } ]
+set_property PACKAGE_PIN AA6 [get_ports { n_e_xmit[0] } ]
+set_property PACKAGE_PIN Y9 [get_ports { p_e_xmit[1] } ]
+set_property PACKAGE_PIN Y8 [get_ports { n_e_xmit[1] } ]
+set_property PACKAGE_PIN W7 [get_ports { p_e_xmit[2] } ]
+set_property PACKAGE_PIN W6 [get_ports { n_e_xmit[2] } ]
+set_property PACKAGE_PIN V9 [get_ports { p_e_xmit[3] } ]
+set_property PACKAGE_PIN V8 [get_ports { n_e_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad C connects to FPGA#2 quad D
+# FPGA#1 quad D connects to FPGA#2 quad C
+# Quad C (VU13P=227, VU9P=226)
+# Quad D (VU13P=228, VU9P=227)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad C will also
+# connect to the secondary 4-lane FireFly#5
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad D will also
+# connect to the secondary 12-lane FireFly#2
+# FPGA#1 and FPGA#2 quad C are clocked from quad B (VU13P=226, VU9P=225)
+# FPGA#1 and FPGA#2 quad D are clocked from quad E (VU13P=229, VU9P=228)
+#
+# Quad C receivers
+set_property PACKAGE_PIN AJ2 [get_ports { p_c_recv[0] } ]
+set_property PACKAGE_PIN AJ1 [get_ports { n_c_recv[0] } ]
+set_property PACKAGE_PIN AH4 [get_ports { p_c_recv[1] } ]
+set_property PACKAGE_PIN AH3 [get_ports { n_c_recv[1] } ]
+set_property PACKAGE_PIN AG2 [get_ports { p_c_recv[2] } ]
+set_property PACKAGE_PIN AG1 [get_ports { n_c_recv[2] } ]
+set_property PACKAGE_PIN AF4 [get_ports { p_c_recv[3] } ]
+set_property PACKAGE_PIN AF3 [get_ports { n_c_recv[3] } ]
+
+# Quad C transmitters
+set_property PACKAGE_PIN AJ7 [get_ports { p_c_xmit[0] } ]
+set_property PACKAGE_PIN AJ6 [get_ports { n_c_xmit[0] } ]
+set_property PACKAGE_PIN AH9 [get_ports { p_c_xmit[1] } ]
+set_property PACKAGE_PIN AH8 [get_ports { n_c_xmit[1] } ]
+set_property PACKAGE_PIN AG7 [get_ports { p_c_xmit[2] } ]
+set_property PACKAGE_PIN AG6 [get_ports { n_c_xmit[2] } ]
+set_property PACKAGE_PIN AF9 [get_ports { p_c_xmit[3] } ]
+set_property PACKAGE_PIN AF8 [get_ports { n_c_xmit[3] } ]
+
+# Quad D receivers
+set_property PACKAGE_PIN AE2 [get_ports { p_d_recv[0] } ]
+set_property PACKAGE_PIN AE1 [get_ports { n_d_recv[0] } ]
+set_property PACKAGE_PIN AD4 [get_ports { p_d_recv[1] } ]
+set_property PACKAGE_PIN AD3 [get_ports { n_d_recv[1] } ]
+set_property PACKAGE_PIN AC2 [get_ports { p_d_recv[2] } ]
+set_property PACKAGE_PIN AC1 [get_ports { n_d_recv[2] } ]
+set_property PACKAGE_PIN AB4 [get_ports { p_d_recv[3] } ]
+set_property PACKAGE_PIN AB3 [get_ports { n_d_recv[3] } ]
+
+# Quad D transmitters
+set_property PACKAGE_PIN AE7 [get_ports { p_d_xmit[0] } ]
+set_property PACKAGE_PIN AE6 [get_ports { n_d_xmit[0] } ]
+set_property PACKAGE_PIN AD9 [get_ports { p_d_xmit[1] } ]
+set_property PACKAGE_PIN AD8 [get_ports { n_d_xmit[1] } ]
+set_property PACKAGE_PIN AC7 [get_ports { p_d_xmit[2] } ]
+set_property PACKAGE_PIN AC6 [get_ports { n_d_xmit[2] } ]
+set_property PACKAGE_PIN AB9 [get_ports { p_d_xmit[3] } ]
+set_property PACKAGE_PIN AB8 [get_ports { n_d_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad G connects to FPGA#2 quad P
+# FPGA#1 quad P and FPGA#2 quad G are not used
+# Quad G (VU13P=231, VU9P=230)
+# Quad P (VU13P=224, VU9P=223)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad G will also
+# connect to the secondary 4-lane FireFly#4
+# FPGA#1 quad G clocked from quad G (VU13P=231, VU9P=230)
+# FPGA#2 quad P is clocked from quad P (VU13P=224, VU9P=223)
+#
+# Quad G receivers
+set_property PACKAGE_PIN N2 [get_ports { p_g_recv[0] } ]
+set_property PACKAGE_PIN N1 [get_ports { n_g_recv[0] } ]
+set_property PACKAGE_PIN M4 [get_ports { p_g_recv[1] } ]
+set_property PACKAGE_PIN M3 [get_ports { n_g_recv[1] } ]
+set_property PACKAGE_PIN L2 [get_ports { p_g_recv[2] } ]
+set_property PACKAGE_PIN L1 [get_ports { n_g_recv[2] } ]
+set_property PACKAGE_PIN K4 [get_ports { p_g_recv[3] } ]
+set_property PACKAGE_PIN K3 [get_ports { n_g_recv[3] } ]
+
+# Quad G transmitters
+set_property PACKAGE_PIN N7 [get_ports { p_g_xmit[0] } ]
+set_property PACKAGE_PIN N6 [get_ports { n_g_xmit[0] } ]
+set_property PACKAGE_PIN M9 [get_ports { p_g_xmit[1] } ]
+set_property PACKAGE_PIN M8 [get_ports { n_g_xmit[1] } ]
+set_property PACKAGE_PIN L7 [get_ports { p_g_xmit[2] } ]
+set_property PACKAGE_PIN L6 [get_ports { n_g_xmit[2] } ]
+set_property PACKAGE_PIN K9 [get_ports { p_g_xmit[3] } ]
+set_property PACKAGE_PIN K8 [get_ports { n_g_xmit[3] } ]
+
+# Quad P receivers
+set_property PACKAGE_PIN BA2 [get_ports { p_p_recv[0] } ]
+set_property PACKAGE_PIN BA1 [get_ports { n_p_recv[0] } ]
+set_property PACKAGE_PIN AY4 [get_ports { p_p_recv[1] } ]
+set_property PACKAGE_PIN AY3 [get_ports { n_p_recv[1] } ]
+set_property PACKAGE_PIN AW2 [get_ports { p_p_recv[2] } ]
+set_property PACKAGE_PIN AW1 [get_ports { n_p_recv[2] } ]
+set_property PACKAGE_PIN AV4 [get_ports { p_p_recv[3] } ]
+set_property PACKAGE_PIN AV3 [get_ports { n_p_recv[3] } ]
+
+# Quad P transmitters
+set_property PACKAGE_PIN BA7 [get_ports { p_p_xmit[0] } ]
+set_property PACKAGE_PIN BA6 [get_ports { n_p_xmit[0] } ]
+set_property PACKAGE_PIN AY9 [get_ports { p_p_xmit[1] } ]
+set_property PACKAGE_PIN AY8 [get_ports { n_p_xmit[1] } ]
+set_property PACKAGE_PIN AW7 [get_ports { p_p_xmit[2] } ]
+set_property PACKAGE_PIN AW6 [get_ports { n_p_xmit[2] } ]
+set_property PACKAGE_PIN AV9 [get_ports { p_p_xmit[3] } ]
+set_property PACKAGE_PIN AV8 [get_ports { n_p_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad H connects to FPGA#2 quad O
+# FPGA#1 quad O connects to FPGA#2 quad H
+# Quad H (VU13P=232, VU9P=231)
+# Quad O (VU13P=223, VU9P=222)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad H will also
+# connect to the secondary 12-lane FireFly#1
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad O will also
+# connect to the secondary 12-lane FireFly#3
+# FPGA#1 and FPGA#2 quad H are clocked from quad I (VU13P=233, VU9P=232)
+# FPGA#1 and FPGA#2 quad O are clocked from quad N (VU13P=222, VU9P=221)
+#
+# Quad H receivers
+set_property PACKAGE_PIN J2 [get_ports { p_h_recv[0] } ]
+set_property PACKAGE_PIN J1 [get_ports { n_h_recv[0] } ]
+set_property PACKAGE_PIN H4 [get_ports { p_h_recv[1] } ]
+set_property PACKAGE_PIN H3 [get_ports { n_h_recv[1] } ]
+set_property PACKAGE_PIN G2 [get_ports { p_h_recv[2] } ]
+set_property PACKAGE_PIN G1 [get_ports { n_h_recv[2] } ]
+set_property PACKAGE_PIN F4 [get_ports { p_h_recv[3] } ]
+set_property PACKAGE_PIN F3 [get_ports { n_h_recv[3] } ]
+
+# Quad H transmitters
+set_property PACKAGE_PIN J7 [get_ports { p_h_xmit[0] } ]
+set_property PACKAGE_PIN J6 [get_ports { n_h_xmit[0] } ]
+set_property PACKAGE_PIN H9 [get_ports { p_h_xmit[1] } ]
+set_property PACKAGE_PIN H8 [get_ports { n_h_xmit[1] } ]
+set_property PACKAGE_PIN G7 [get_ports { p_h_xmit[2] } ]
+set_property PACKAGE_PIN G6 [get_ports { n_h_xmit[2] } ]
+set_property PACKAGE_PIN F9 [get_ports { p_h_xmit[3] } ]
+set_property PACKAGE_PIN F8 [get_ports { n_h_xmit[3] } ]
+
+# Quad O receivers
+set_property PACKAGE_PIN BE2 [get_ports { p_o_recv[0] } ]
+set_property PACKAGE_PIN BE1 [get_ports { n_o_recv[0] } ]
+set_property PACKAGE_PIN BD4 [get_ports { p_o_recv[1] } ]
+set_property PACKAGE_PIN BD3 [get_ports { n_o_recv[1] } ]
+set_property PACKAGE_PIN BC2 [get_ports { p_o_recv[2] } ]
+set_property PACKAGE_PIN BC1 [get_ports { n_o_recv[2] } ]
+set_property PACKAGE_PIN BB4 [get_ports { p_o_recv[3] } ]
+set_property PACKAGE_PIN BB3 [get_ports { n_o_recv[3] } ]
+
+# Quad O transmitters
+set_property PACKAGE_PIN BE7 [get_ports { p_o_xmit[0] } ]
+set_property PACKAGE_PIN BE6 [get_ports { n_o_xmit[0] } ]
+set_property PACKAGE_PIN BD9 [get_ports { p_o_xmit[1] } ]
+set_property PACKAGE_PIN BD8 [get_ports { n_o_xmit[1] } ]
+set_property PACKAGE_PIN BC7 [get_ports { p_o_xmit[2] } ]
+set_property PACKAGE_PIN BC6 [get_ports { n_o_xmit[2] } ]
+set_property PACKAGE_PIN BB9 [get_ports { p_o_xmit[3] } ]
+set_property PACKAGE_PIN BB8 [get_ports { n_o_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad I connects to FPGA#2 quad N
+# FPGA#1 quad N connects to FPGA#2 quad I
+# Quad I (VU13P=233, VU9P=232)
+# Quad N (VU13P=222, VU9P=221)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad I will also
+# connect to the secondary 12-lane FireFly#1
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad N will also
+# connect to the secondary 12-lane FireFly#3
+# FPGA#1 and FPGA#2 quad I are clocked from quad I (VU13P=233, VU9P=232)
+# FPGA#1 and FPGA#2 quad N are clocked from quad N (VU13P=222, VU9P=221)
+#
+# Quad I receivers
+set_property PACKAGE_PIN E2 [get_ports { p_i_recv[0] } ]
+set_property PACKAGE_PIN E1 [get_ports { n_i_recv[0] } ]
+set_property PACKAGE_PIN D4 [get_ports { p_i_recv[1] } ]
+set_property PACKAGE_PIN D3 [get_ports { n_i_recv[1] } ]
+set_property PACKAGE_PIN E6 [get_ports { p_i_recv[2] } ]
+set_property PACKAGE_PIN E5 [get_ports { n_i_recv[2] } ]
+set_property PACKAGE_PIN C6 [get_ports { p_i_recv[3] } ]
+set_property PACKAGE_PIN C5 [get_ports { n_i_recv[3] } ]
+
+# Quad I transmitters
+set_property PACKAGE_PIN D9 [get_ports { p_i_xmit[0] } ]
+set_property PACKAGE_PIN D8 [get_ports { n_i_xmit[0] } ]
+set_property PACKAGE_PIN B9 [get_ports { p_i_xmit[1] } ]
+set_property PACKAGE_PIN B8 [get_ports { n_i_xmit[1] } ]
+set_property PACKAGE_PIN C11 [get_ports { p_i_xmit[2] } ]
+set_property PACKAGE_PIN C10 [get_ports { n_i_xmit[2] } ]
+set_property PACKAGE_PIN E11 [get_ports { p_i_xmit[3] } ]
+set_property PACKAGE_PIN E10 [get_ports { n_i_xmit[3] } ]
+
+# Quad N receivers
+set_property PACKAGE_PIN BH4 [get_ports { p_n_recv[0] } ]
+set_property PACKAGE_PIN BH3 [get_ports { n_n_recv[0] } ]
+set_property PACKAGE_PIN BG2 [get_ports { p_n_recv[1] } ]
+set_property PACKAGE_PIN BG1 [get_ports { n_n_recv[1] } ]
+set_property PACKAGE_PIN BG6 [get_ports { p_n_recv[2] } ]
+set_property PACKAGE_PIN BG5 [get_ports { n_n_recv[2] } ]
+set_property PACKAGE_PIN BF4 [get_ports { p_n_recv[3] } ]
+set_property PACKAGE_PIN BF3 [get_ports { n_n_recv[3] } ]
+
+# Quad N transmitters
+set_property PACKAGE_PIN BG11 [get_ports { p_n_xmit[0] } ]
+set_property PACKAGE_PIN BG10 [get_ports { n_n_xmit[0] } ]
+set_property PACKAGE_PIN BJ11 [get_ports { p_n_xmit[1] } ]
+set_property PACKAGE_PIN BJ10 [get_ports { n_n_xmit[1] } ]
+set_property PACKAGE_PIN BH9 [get_ports { p_n_xmit[2] } ]
+set_property PACKAGE_PIN BH8 [get_ports { n_n_xmit[2] } ]
+set_property PACKAGE_PIN BF9 [get_ports { p_n_xmit[3] } ]
+set_property PACKAGE_PIN BF8 [get_ports { n_n_xmit[3] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# GTY transceiver for FPGA-to-FPGA links
+# FPGA#1 quad J connects to FPGA#2 quad M
+# FPGA#1 quad M connects to FPGA#2 quad J
+# Quad J (VU13P=234, VU9P=233)
+# Quad M (VU13P=221, VU9P=220)
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad J will also
+# connect to the secondary 12-lane FireFly#1
+# On single-FPGA boards with FPGA#2 jumpers, FPGA#1 quad M will also
+# connect to the secondary 12-lane FireFly#3
+# FPGA#1 and FPGA#2 quad J are clocked from quad I (VU13P=233, VU9P=232)
+# FPGA#1 and FPGA#2 quad M are clocked from quad N (VU13P=222, VU9P=221)
+#
+# Quad J receivers
+set_property PACKAGE_PIN A6 [get_ports { p_j_recv[0] } ]
+set_property PACKAGE_PIN A5 [get_ports { n_j_recv[0] } ]
+set_property PACKAGE_PIN A20 [get_ports { p_j_recv[1] } ]
+set_property PACKAGE_PIN A19 [get_ports { n_j_recv[1] } ]
+set_property PACKAGE_PIN B18 [get_ports { p_j_recv[2] } ]
+set_property PACKAGE_PIN B17 [get_ports { n_j_recv[2] } ]
+set_property PACKAGE_PIN C20 [get_ports { p_j_recv[3] } ]
+set_property PACKAGE_PIN C19 [get_ports { n_j_recv[3] } ]
+
+# Quad J transmitters
+set_property PACKAGE_PIN A11 [get_ports { p_j_xmit[0] } ]
+set_property PACKAGE_PIN A10 [get_ports { n_j_xmit[0] } ]
+set_property PACKAGE_PIN B13 [get_ports { p_j_xmit[1] } ]
+set_property PACKAGE_PIN B12 [get_ports { n_j_xmit[1] } ]
+set_property PACKAGE_PIN A15 [get_ports { p_j_xmit[2] } ]
+set_property PACKAGE_PIN A14 [get_ports { n_j_xmit[2] } ]
+set_property PACKAGE_PIN C15 [get_ports { p_j_xmit[3] } ]
+set_property PACKAGE_PIN C14 [get_ports { n_j_xmit[3] } ]
+
+# Quad M receivers
+set_property PACKAGE_PIN BK18 [get_ports { p_m_recv[0] } ]
+set_property PACKAGE_PIN BK17 [get_ports { n_m_recv[0] } ]
+set_property PACKAGE_PIN BL20 [get_ports { p_m_recv[1] } ]
+set_property PACKAGE_PIN BL19 [get_ports { n_m_recv[1] } ]
+set_property PACKAGE_PIN BL6 [get_ports { p_m_recv[2] } ]
+set_property PACKAGE_PIN BL5 [get_ports { n_m_recv[2] } ]
+set_property PACKAGE_PIN BJ6 [get_ports { p_m_recv[3] } ]
+set_property PACKAGE_PIN BJ5 [get_ports { n_m_recv[3] } ]
+
+# Quad M transmitters
+set_property PACKAGE_PIN BL15 [get_ports { p_m_xmit[0] } ]
+set_property PACKAGE_PIN BL14 [get_ports { n_m_xmit[0] } ]
+set_property PACKAGE_PIN BK13 [get_ports { p_m_xmit[1] } ]
+set_property PACKAGE_PIN BK12 [get_ports { n_m_xmit[1] } ]
+set_property PACKAGE_PIN BL11 [get_ports { p_m_xmit[2] } ]
+set_property PACKAGE_PIN BL10 [get_ports { n_m_xmit[2] } ]
+set_property PACKAGE_PIN BK9 [get_ports { p_m_xmit[3] } ]
+set_property PACKAGE_PIN BK8 [get_ports { n_m_xmit[3] } ]
+#-----------------------------------------------
+
+
+#-----------------------------------------------
+# Front panel HDMI-sytle test connector
+# 'test_conn_0' connects to global clock-capable input pins
+set_property IOSTANDARD LVDS [get_ports p_test_conn*]
+set_property IOSTANDARD LVDS [get_ports n_test_conn*]
+# Enable the DIFF_TERM_ADV property for any ports used as inputs
+#set_property DIFF_TERM_ADV TERM_100 [get_ports p_test_conn*]
+#set_property DIFF_TERM_ADV TERM_100 [get_ports n_test_conn*]
+set_property PACKAGE_PIN BD28 [get_ports p_test_conn_0 ]
+set_property PACKAGE_PIN BE28 [get_ports n_test_conn_0 ]
+set_property PACKAGE_PIN AW31 [get_ports p_test_conn_1 ]
+set_property PACKAGE_PIN AY31 [get_ports n_test_conn_1 ]
+set_property PACKAGE_PIN AV29 [get_ports p_test_conn_2 ]
+set_property PACKAGE_PIN AW29 [get_ports n_test_conn_2 ]
+set_property PACKAGE_PIN AU31 [get_ports p_test_conn_3 ]
+set_property PACKAGE_PIN AV31 [get_ports n_test_conn_3 ]
+set_property PACKAGE_PIN AY30 [get_ports p_test_conn_4 ]
+set_property PACKAGE_PIN BA30 [get_ports n_test_conn_4 ]
+
+set_property IOSTANDARD LVCMOS18 [get_ports test_conn_5]
+set_property IOSTANDARD LVCMOS18 [get_ports test_conn_6]
+set_property PACKAGE_PIN BA29 [get_ports test_conn_5 ]
+set_property PACKAGE_PIN BA28 [get_ports test_conn_6 ]
+#-----------------------------------------------
+
+
+#-----------------------------------------------
+# Spare input signals from the "other" FPGA.
+# These cross-connect to the spare output signals on the other FPGA
+# 'in_spare[2]' is connected to global glock-capable input pins
+set_property IOSTANDARD LVDS [get_ports *_in_spare*]
+set_property DIFF_TERM_ADV TERM_100 [get_ports *_in_spare*]
+set_property PACKAGE_PIN E30 [get_ports { p_in_spare[0] } ]
+set_property PACKAGE_PIN D30 [get_ports { n_in_spare[0] } ]
+set_property PACKAGE_PIN D28 [get_ports { p_in_spare[1] } ]
+set_property PACKAGE_PIN D29 [get_ports { n_in_spare[1] } ]
+set_property PACKAGE_PIN C29 [get_ports { p_in_spare[2] } ]
+set_property PACKAGE_PIN C30 [get_ports { n_in_spare[2] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# Spare output signals to the "other" FPGA.
+# These cross-connect to the spare input signals on the other FPGA
+set_property IOSTANDARD LVDS [get_ports *_out_spare*]
+set_property PACKAGE_PIN BG29 [get_ports { p_out_spare[0] } ]
+set_property PACKAGE_PIN BH29 [get_ports { n_out_spare[0] } ]
+set_property PACKAGE_PIN BF29 [get_ports { p_out_spare[1] } ]
+set_property PACKAGE_PIN BG30 [get_ports { n_out_spare[1] } ]
+set_property PACKAGE_PIN BG26 [get_ports { p_out_spare[2] } ]
+set_property PACKAGE_PIN BG27 [get_ports { n_out_spare[2] } ]
+#-----------------------------------------------
+
+#-----------------------------------------------
+# Spare pins to 1mm x 1mm headers on the bottom of the board
+# They could be used in an emergency as I/Os, or for debugging
+# hdr1 and hdr2 are on global clock-capable pins
+set_property IOSTANDARD LVDS [get_ports hdr1]
+set_property IOSTANDARD LVDS [get_ports hdr2]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr3]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr4]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr5]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr6]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr7]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr8]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr9]
+set_property IOSTANDARD LVCMOS18 [get_ports hdr10]
+set_property PACKAGE_PIN L28 [get_ports hdr1 ]
+set_property PACKAGE_PIN L29 [get_ports hdr2 ]
+set_property PACKAGE_PIN C26 [get_ports hdr3 ]
+set_property PACKAGE_PIN B26 [get_ports hdr4 ]
+set_property PACKAGE_PIN A25 [get_ports hdr5 ]
+set_property PACKAGE_PIN B25 [get_ports hdr6 ]
+set_property PACKAGE_PIN A24 [get_ports hdr7 ]
+set_property PACKAGE_PIN B24 [get_ports hdr8 ]
+set_property PACKAGE_PIN A23 [get_ports hdr9 ]
+set_property PACKAGE_PIN A22 [get_ports hdr10 ]
+
+#-----------------------------------------------
+
diff --git a/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_timing.xdc b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_timing.xdc
new file mode 100644
index 0000000..a3b699b
--- /dev/null
+++ b/configs/Cornell_rev2_p2_VU13p-1-SM_USP_heaters_allQuads25G/src/top_timing.xdc
@@ -0,0 +1,5 @@
+# 200 MHz oscillator
+create_clock -period 5.000 -waveform {0.000 2.5000} [get_nets clk_200]
+
+# 40 MHz extracted clock
+create_clock -period 25.000 -waveform {0.000 12.5000} [get_nets amc13_clk_40]
\ No newline at end of file