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neo-mmrm-test.dtsi
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neo-mmrm-test.dtsi
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&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,neo-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"disp_cc_mdss_dptx0_link_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&camcc CAM_CC_BPS_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_ICP_CLK_SRC>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&videocc VIDEO_CC_MVS1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>;
clock_rates =
/* domain csid lowsvs svs svs_L1 nom turbo */
<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 0 727000000 0>,
<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 0 727000000 0>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 0 480000000 0>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 0 700000000 0>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 0 600000000 0>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 0 480000000 0>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 0 600000000 0>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 0 400000000 0>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 0 480000000 0>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 0 600000000 0>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 0 480000000 0>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 0 37500000 0>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 0 37500000 0>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 0 80000000 0>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 0 400000000 0>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 0 1650000000 0>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 0 514000000 0>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 0 810000 0>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 0 1332000000 0>;
};
};