The language server provides a couple of features from the Verible SystemVerilog productivity suite right in the editor.
- Linting: Checks your code against a number of lint rules and provides 'wiggly lines' with diagnostic output and even offers auto-fixes when available.
- Formatting: Offers Format Document/Selection according to the Verible formatting style. The 'look' can be configured if needed.
- Outline: Shows the high-level structure of your modules and functions in the outline tree. Labelled begin/end blocks are also included.
- Hover: Highlight symbols related to the one under the cursor.
- Go-To-Definition: Jump to the definition of the symbol under the cursor.
- Go-To-References: Jump to the references of the symbol under the cursor.
- AUTO-expansion: Features known from Emacs
Verilog-mode, used for expanding
various
/*AUTO...*/
pragmas in Verilog and SystemVerilog code. These expansions are available as code actions.AUTOARG
– generates a list of non-ANSI ports in a module header,- [🎉 New]
AUTOINST
withAUTO_TEMPLATE
– generates connections in a module instance based on the instantiated module's ports, - [🎉 New]
AUTOINPUT
,AUTOOUTPUT
,AUTOINOUT
– declares ports based on connections generated byAUTOINST
, - [🎉 New]
AUTOWIRE
– declares wires based on connections generated byAUTOINST
, - [🎉 New]
AUTOREG
– declares regs for outputs not connected to any module instance.
The Verible plug-in needs the verible-verilog-ls
executable installed
on your machine.
On Linux and Windows, the plug-in will try to download the necessary executable (if it's not already available).
Get a binary distribution for your Operating System at https://github.com/chipsalliance/verible/releases
Alternatively, build Verible from source.
File bugs on the public github issue tracker. Provide (sanitized) code examples if needed to illustrate an issue.