From 772e434d76ddfdeb967e2426c0618efaa8d60be8 Mon Sep 17 00:00:00 2001 From: Ramin Aghajafari <153928265+ramin4667@users.noreply.github.com> Date: Fri, 1 Nov 2024 14:33:18 -0400 Subject: [PATCH 01/13] FIX: The open export page fix for unit tests (#5363) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com> --- .../filtersolutions_core/export_to_aedt.py | 2 +- .../resources/library_parts.cfg | 32 ++++---- .../test_lumped_export/test_export_to_aedt.py | 82 ++----------------- 3 files changed, 23 insertions(+), 93 deletions(-) diff --git a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py index 6b9849cf7f3..61750324238 100644 --- a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py +++ b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py @@ -1310,7 +1310,7 @@ def substrate_resistivity(self, substrate_input): ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) @property - def substrate_loss_tangent(self) -> Union[SubstrateType, str]: + def substrate_loss_tangent(self) -> Union[SubstrateEr, str]: """Substrate's loss tangent. The value can be either a string or an instance of the ``SubstrateEr`` enum. The default is ``0.0005`` for ``SubstrateEr.ALUMINA``. diff --git a/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg b/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg index d53e30325bd..4062cb29a22 100644 --- a/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg +++ b/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg @@ -1,31 +1,31 @@ modsubType=2 -modsubEr=4.5 -modsubRho=5.8E+07 -modsubTand=0.035 -modsubH=0.002 -modsubT=5E-07 +modsubEr=9.8 +modsubRho=1.43 +modsubTand=0.0005 +modsubH=0.00127 +modsubT=2.54E-06 modsubS=0.00127 modsubC=0.00635 -modsubErsel=-1 -modsubRhosel=-1 -modsubTandsel=-1 -modsubTanddef=0 +modsubErsel=1 +modsubRhosel=3 +modsubTandsel=1 +modsubTanddef=1 modsubiSubSel=0 -modsubName=User Defined Substrate +modsubName=Alumina modsubBrow= -modsubNameVal=4.5 +modsubNameVal=Alumina: 9.8 modAnsSubIndex=0 modAWRSubIndex=0 webAWRSubIndex=0 locAWRSubIndex=0 -ModelData=2 +ModelData=0 ModelDataV=1 ModelInd=0 -ModelCap=3 +ModelCap=0 ModelRes=0 -ModelIndV=1 -ModelCapV=1 -ModelResV=1 +ModelIndV=0 +ModelCapV=0 +ModelResV=0 modRatLen=2 modRatZ=1 Interc=1 diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py index 488f05aa701..876c335be0a 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py @@ -50,7 +50,6 @@ class TestClass: def test_modelithics_inductor_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -59,7 +58,6 @@ def test_modelithics_inductor_list_count(self): def test_modelithics_inductor_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -72,7 +70,6 @@ def test_modelithics_inductor_list(self): def test_modelithics_inductor_selection(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -85,7 +82,6 @@ def test_modelithics_inductor_selection(self): def test_modelithics_inductor_family_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -98,7 +94,6 @@ def test_modelithics_inductor_family_list_count(self): def test_modelithics_inductor_family_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -113,7 +108,6 @@ def test_modelithics_inductor_family_list(self): def test_modelithics_inductor_family_list_add_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -128,7 +122,6 @@ def test_modelithics_inductor_family_list_add_family(self): def test_modelithics_inductor_family_list_remove_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_remove_family(second_modelithics_inductor) lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS @@ -143,16 +136,14 @@ def test_modelithics_inductor_family_list_remove_family(self): def test_modelithics_capacitor_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_capacitor_list_count == 140 + assert lumpdesign.export_to_aedt.modelithics_capacitor_list_count == 143 def test_modelithics_capacitor_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -165,7 +156,6 @@ def test_modelithics_capacitor_list(self): def test_modelithics_capacitor_selection(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -178,7 +168,6 @@ def test_modelithics_capacitor_selection(self): def test_modelithics_capacitor_family_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -191,7 +180,6 @@ def test_modelithics_capacitor_family_list_count(self): def test_modelithics_capacitor_family_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -206,7 +194,6 @@ def test_modelithics_capacitor_family_list(self): def test_modelithics_capacitor_family_list_add_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -221,7 +208,6 @@ def test_modelithics_capacitor_family_list_add_family(self): def test_modelithics_capacitor_family_list_remove_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -237,7 +223,6 @@ def test_modelithics_capacitor_family_list_remove_family(self): def test_modelithics_resistor_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -246,7 +231,6 @@ def test_modelithics_resistor_list_count(self): def test_modelithics_resistor_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -259,7 +243,6 @@ def test_modelithics_resistor_list(self): def test_modelithics_resistor_selection(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -272,7 +255,6 @@ def test_modelithics_resistor_selection(self): def test_modelithics_resistor_family_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -285,7 +267,6 @@ def test_modelithics_resistor_family_list_count(self): def test_modelithics_resistor_family_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -300,7 +281,6 @@ def test_modelithics_resistor_family_list(self): def test_modelithics_resistor_family_list_add_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -315,7 +295,6 @@ def test_modelithics_resistor_family_list_add_family(self): def test_modelithics_resistor_family_list_remove_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -331,136 +310,117 @@ def test_modelithics_resistor_family_list_remove_family(self): def test_schematic_name(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.schematic_name = "my_schematic" assert lumpdesign.export_to_aedt.schematic_name == "my_schematic" def test_simulate_after_export_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.simulate_after_export_enabled == False lumpdesign.export_to_aedt.simulate_after_export_enabled = True assert lumpdesign.export_to_aedt.simulate_after_export_enabled == True def test_include_group_delay_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_group_delay_enabled == False lumpdesign.export_to_aedt.include_group_delay_enabled = True assert lumpdesign.export_to_aedt.include_group_delay_enabled == True def test_include_gt_gain_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_gt_gain_enabled == False lumpdesign.export_to_aedt.include_gt_gain_enabled = True assert lumpdesign.export_to_aedt.include_gt_gain_enabled == True def test_include_vgsl_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_vgsl_enabled == False lumpdesign.export_to_aedt.include_vgsl_enabled = True assert lumpdesign.export_to_aedt.include_vgsl_enabled == True def test_include_vgin_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_vgin_enabled == False lumpdesign.export_to_aedt.include_vgin_enabled = True assert lumpdesign.export_to_aedt.include_vgin_enabled == True def test_include_input_return_loss_s11_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == True lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled = False assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == False def test_include_forward_transfer_s21_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == True lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled = False assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == False def test_include_reverse_transfer_s12_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == False lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled = True assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == True def test_include_output_return_loss_s22_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == False lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled = True assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == True def test_db_format_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.db_format_enabled == True lumpdesign.export_to_aedt.db_format_enabled = False assert lumpdesign.export_to_aedt.db_format_enabled == False def test_rectangular_plot_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.rectangular_plot_enabled == True lumpdesign.export_to_aedt.rectangular_plot_enabled = False assert lumpdesign.export_to_aedt.rectangular_plot_enabled == False def test_smith_plot_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.smith_plot_enabled == False lumpdesign.export_to_aedt.smith_plot_enabled = True assert lumpdesign.export_to_aedt.smith_plot_enabled == True def test_polar_plot_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.polar_plot_enabled == False lumpdesign.export_to_aedt.polar_plot_enabled = True assert lumpdesign.export_to_aedt.polar_plot_enabled == True def test_table_data_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.table_data_enabled == False lumpdesign.export_to_aedt.table_data_enabled = True assert lumpdesign.export_to_aedt.table_data_enabled == True def test_optimitrics_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.optimitrics_enabled == True lumpdesign.export_to_aedt.optimitrics_enabled = False assert lumpdesign.export_to_aedt.optimitrics_enabled == False def test_optimize_after_export_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.optimize_after_export_enabled == False lumpdesign.export_to_aedt.optimize_after_export_enabled = True assert lumpdesign.export_to_aedt.optimize_after_export_enabled == True def test_load_library_parts_config(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.load_library_parts_config(resource_path("library_parts.cfg")) lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.substrate_er == "4.5" - assert lumpdesign.export_to_aedt.substrate_resistivity == "5.8E+07 " - assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "500 nm" - assert lumpdesign.export_to_aedt.substrate_dielectric_height == "2 mm" - assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.035 " + assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA + assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD + assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" + assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" + assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA def test_save_library_parts_config(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS lumpdesign.export_to_aedt.substrate_er = "2.25" lumpdesign.export_to_aedt.substrate_resistivity = "4.2E+07 " @@ -478,7 +438,6 @@ def test_save_library_parts_config(self): def test_import_tuned_variables(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.simulate_after_export_enabled = True lumpdesign.export_to_aedt.optimize_after_export_enabled = True lumpdesign.export_to_aedt.export_design() @@ -488,9 +447,6 @@ def test_import_tuned_variables(self): def test_part_libraries(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.export_to_aedt._open_aedt_export() - assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.LUMPED assert len(PartLibraries) == 3 lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS @@ -498,91 +454,78 @@ def test_part_libraries(self): def test_interconnect_length_to_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_length_to_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "3" def test_interconnect_minimum_length_to_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.5" lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio = "0.6" assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.6" def test_interconnect_maximum_length_to_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "3" def test_interconnect_line_to_termination_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "1" lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio = "2" assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "2" def test_interconnect_minimum_line_to_termination_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.5" lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio = "0.6" assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.6" def test_interconnect_maximum_line_to_termination_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "3" def test_interconnect_length_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_length_value == "2.54 mm" lumpdesign.export_to_aedt.interconnect_length_value = "3 mm" assert lumpdesign.export_to_aedt.interconnect_length_value == "3 mm" def test_interconnect_minimum_length_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "1.27 mm" lumpdesign.export_to_aedt.interconnect_minimum_length_value = "0.6 mm" assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "0.6 mm" def test_interconnect_maximum_length_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "5.08 mm" lumpdesign.export_to_aedt.interconnect_maximum_length_value = "6 mm" assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "6 mm" def test_interconnect_line_width_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_line_width_value == "1.27 mm" lumpdesign.export_to_aedt.interconnect_line_width_value = "2 mm" assert lumpdesign.export_to_aedt.interconnect_line_width_value == "2 mm" def test_interconnect_minimum_width_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "635 um" lumpdesign.export_to_aedt.interconnect_minimum_width_value = "725 um" assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "725 um" def test_interconnect_maximum_width_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "2.54 mm" lumpdesign.export_to_aedt.interconnect_maximum_width_value = "3 mm" assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "3 mm" def test_interconnect_inductor_tolerance_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "1" lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value = "10" @@ -590,7 +533,6 @@ def test_interconnect_inductor_tolerance_value(self): def test_interconnect_capacitor_tolerance_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "1" lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value = "10" @@ -598,14 +540,12 @@ def test_interconnect_capacitor_tolerance_value(self): def test_interconnect_geometry_optimization_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == True lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled = False assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == False def test_substrate_type(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_type == SubstrateType.MICROSTRIP assert len(SubstrateType) == 5 for substrate in SubstrateType: @@ -614,7 +554,6 @@ def test_substrate_type(self): def test_substrate_er(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for er in SubstrateEr: @@ -625,7 +564,6 @@ def test_substrate_er(self): def test_substrate_resistivity(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD assert len(SubstrateResistivity) == 11 for resistivity in SubstrateResistivity: @@ -636,7 +574,6 @@ def test_substrate_resistivity(self): def test_substrate_loss_tangent(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for loss in SubstrateEr: @@ -647,21 +584,18 @@ def test_substrate_loss_tangent(self): def test_substrate_conductor_thickness(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" lumpdesign.export_to_aedt.substrate_conductor_thickness = "1.25 um" assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "1.25 um" def test_substrate_dielectric_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" lumpdesign.export_to_aedt.substrate_dielectric_height = "1.22 mm" assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.22 mm" def test_substrate_unbalanced_lower_dielectric_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "6.35 mm" @@ -670,7 +604,6 @@ def test_substrate_unbalanced_lower_dielectric_height(self): def test_substrate_suspend_dielectric_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_type = SubstrateType.SUSPEND assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "1.27 mm" lumpdesign.export_to_aedt.substrate_suspend_dielectric_height = "3.2 mm" @@ -678,7 +611,6 @@ def test_substrate_suspend_dielectric_height(self): def test_substrate_cover_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_cover_height_enabled = True assert lumpdesign.export_to_aedt.substrate_cover_height == "6.35 mm" lumpdesign.export_to_aedt.substrate_cover_height = "2.5 mm" @@ -686,7 +618,6 @@ def test_substrate_cover_height(self): def test_substrate_unbalanced_stripline_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == False lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True @@ -694,7 +625,6 @@ def test_substrate_unbalanced_stripline_enabled(self): def test_substrate_cover_height_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == False lumpdesign.export_to_aedt.substrate_cover_height_enabled = True assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == True From afc99f3fe8c43bc3e5f58c24934f9f12b01bce49 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Sun, 3 Nov 2024 16:24:57 +0100 Subject: [PATCH 02/13] BUILD: update pytest-cov requirement from <5.1,>=4.0.0 to >=4.0.0,<6.1 (#5369) Signed-off-by: dependabot[bot] Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- pyproject.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index c17cf092b9a..95cce2f80b3 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -47,7 +47,7 @@ dependencies = [ [project.optional-dependencies] unit-tests = [ "pytest>=7.4.0,<8.4", - "pytest-cov>=4.0.0,<5.1", + "pytest-cov>=4.0.0,<6.1", "mock>=5.1.0,<5.2", ] tests = [ @@ -60,7 +60,7 @@ tests = [ "osmnx>=1.1.0,<1.10", "pandas>=1.1.0,<2.3", "pytest>=7.4.0,<8.4", - "pytest-cov>=4.0.0,<5.1", + "pytest-cov>=4.0.0,<6.1", "pytest-xdist>=3.5.0,<3.7", "pyvista[io]>=0.38.0,<0.45", # Never directly imported but required when loading ML related file see #4713 From 9c3dbc5f735a287a177e9c3c4346a2a90cc53481 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Sun, 3 Nov 2024 16:26:10 +0100 Subject: [PATCH 03/13] BUILD: update jupyterlab requirement from <4.3,>=3.6.0 to >=3.6.0,<4.4 (#5370) Signed-off-by: dependabot[bot] Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- pyproject.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyproject.toml b/pyproject.toml index 95cce2f80b3..ace06729149 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -117,7 +117,7 @@ installer = [ "scikit-rf>=0.30.0,<1.4", "SRTM.py", "utm", - "jupyterlab>=3.6.0,<4.3", + "jupyterlab>=3.6.0,<4.4", "ipython>=7.30.0,<8.30", "ipyvtklink>=0.2.0,<0.2.4", ] From 6e90d311d0ed7835d990c330eca87357178f3f12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Morais?= <146729917+SMoraisAnsys@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:45:44 +0100 Subject: [PATCH 04/13] BUILD: Update ansys theme version (#5372) --- .github/workflows/ci_cd.yml | 3 --- .github/workflows/nightly-docs.yml | 3 --- doc/source/conf.py | 10 +++++----- pyproject.toml | 4 +--- 4 files changed, 6 insertions(+), 14 deletions(-) diff --git a/.github/workflows/ci_cd.yml b/.github/workflows/ci_cd.yml index 9e38911b3b9..db85ca4f814 100644 --- a/.github/workflows/ci_cd.yml +++ b/.github/workflows/ci_cd.yml @@ -16,9 +16,6 @@ env: MAIN_PYTHON_VERSION: '3.10' PACKAGE_NAME: 'PyAEDT' DOCUMENTATION_CNAME: 'aedt.docs.pyansys.com' - MEILISEARCH_API_KEY: ${{ secrets.MEILISEARCH_API_KEY }} - MEILISEARCH_HOST_URL: ${{ vars.MEILISEARCH_HOST_URL }} - MEILISEARCH_PUBLIC_API_KEY: ${{ secrets.MEILISEARCH_PUBLIC_API_KEY }} ON_CI: True PYTEST_ARGUMENTS: '-vvv --color=yes -ra --durations=25 --maxfail=10 --cov=ansys.aedt.core --cov-report=html --cov-report=xml --junitxml=junit/test-results.xml' diff --git a/.github/workflows/nightly-docs.yml b/.github/workflows/nightly-docs.yml index eda50f8c67e..1289b1e5649 100644 --- a/.github/workflows/nightly-docs.yml +++ b/.github/workflows/nightly-docs.yml @@ -9,9 +9,6 @@ env: ANSYSLMD_LICENSE_FILE: ${{ format('1055@{0}', secrets.LICENSE_SERVER) }} MAIN_PYTHON_VERSION: '3.10' DOCUMENTATION_CNAME: 'aedt.docs.pyansys.com' - MEILISEARCH_API_KEY: ${{ secrets.MEILISEARCH_API_KEY }} - MEILISEARCH_HOST_URL: ${{ vars.MEILISEARCH_HOST_URL }} - MEILISEARCH_PUBLIC_API_KEY: ${{ secrets.MEILISEARCH_PUBLIC_API_KEY }} concurrency: group: ${{ github.workflow }}-${{ github.ref }} diff --git a/doc/source/conf.py b/doc/source/conf.py index 6a4e7c92bbc..0d6225a46d2 100644 --- a/doc/source/conf.py +++ b/doc/source/conf.py @@ -291,11 +291,11 @@ def setup(app): }, "collapse_navigation": True, "navigation_with_keys": True, - "use_meilisearch": { - "api_key": os.getenv("MEILISEARCH_PUBLIC_API_KEY", ""), - "index_uids": { - f"pyaedt-v{get_version_match(__version__).replace('.', '-')}": "PyAEDT", - }, + "static_search": { + "threshold": 0.5, + "minMatchCharLength": 2, + "limite": 10, + "ignoreLocation": True, }, } diff --git a/pyproject.toml b/pyproject.toml index ace06729149..7da3b829daa 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -76,9 +76,8 @@ dotnet = [ "dotnetcore2==3.1.23; platform_system=='Linux'", "pywin32>=303; platform_system=='Windows'", ] - doc = [ - "ansys-sphinx-theme>=0.10.0,<1.1", + "ansys-sphinx-theme>=1.0.0,<1.3", "numpydoc>=1.5.0,<1.9", "recommonmark", "Sphinx>=7.1.0,<8.2", @@ -90,7 +89,6 @@ doc = [ "sphinx_design>=0.4.0,<0.7", "pyvista[io]>=0.38.0,<0.45", ] - all = [ "matplotlib>=3.5.0,<3.10", "numpy>=1.20.0,<2", From 6d4daa1c0b8b798a9ff88dd7d771ff94e45fa5af Mon Sep 17 00:00:00 2001 From: Alberto Di Maria <84965833+Alberto-DM@users.noreply.github.com> Date: Mon, 4 Nov 2024 11:51:54 +0100 Subject: [PATCH 05/13] FIX: Remove the clipboard isolation env variable in the kernel_converter script (#5331) --- .../aedt/core/workflows/project/kernel_converter.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/ansys/aedt/core/workflows/project/kernel_converter.py b/src/ansys/aedt/core/workflows/project/kernel_converter.py index 2f8b4149d14..8adb60ef14e 100644 --- a/src/ansys/aedt/core/workflows/project/kernel_converter.py +++ b/src/ansys/aedt/core/workflows/project/kernel_converter.py @@ -283,6 +283,13 @@ def convert(args): files_path += search_files(args["file_path"], "*.aedt") else: files_path = [args["file_path"]] + # Remove the clipboard isolation env variable if present + env_var_name = "ANS_USE_ISOLATED_CLIPBOARD" + saved_env_var = None + if env_var_name in os.environ: + saved_env_var = os.environ[env_var_name] + del os.environ[env_var_name] + output_desktop = Desktop( new_desktop=True, version=version, @@ -303,6 +310,10 @@ def convert(args): input_desktop.release_desktop() output_desktop.release_desktop(False, False) + # Reset the clipboard isolation env variable if it was present + if saved_env_var is not None: + os.environ[env_var_name] = saved_env_var + if __name__ == "__main__": args = get_arguments(extension_arguments, extension_description) From ea34abc7dfc266aa4f465832d2a0510e8d0299a6 Mon Sep 17 00:00:00 2001 From: Samuel Lopez <85613111+Samuelopez-ansys@users.noreply.github.com> Date: Tue, 5 Nov 2024 08:42:38 +0100 Subject: [PATCH 06/13] FIX: Assign impedance to sheet in Eigenmode (#5374) --- src/ansys/aedt/core/hfss.py | 71 +--------------------------- tests/system/general/test_20_HFSS.py | 10 +++- 2 files changed, 10 insertions(+), 71 deletions(-) diff --git a/src/ansys/aedt/core/hfss.py b/src/ansys/aedt/core/hfss.py index fe4c3bf4fa4..ce9b9386d29 100644 --- a/src/ansys/aedt/core/hfss.py +++ b/src/ansys/aedt/core/hfss.py @@ -3508,75 +3508,6 @@ def assign_lumped_rlc_to_sheet( return self._create_boundary(name, props, "Lumped RLC") return False - @pyaedt_function_handler(sheet_name="assignment", sourcename="name", is_infground="is_inifinite_ground") - def assign_impedance_to_sheet(self, assignment, name=None, resistance=50, reactance=0, is_inifinite_ground=False): - """Create an impedance taking one sheet. - - Parameters - ---------- - assignment : str or list - One or more names of the sheets to apply the boundary to. - name : str, optional - Name of the impedance. The default is ``None``. - resistance : optional - Resistance value in ohms. The default is ``50``. If ``None``, - this parameter is disabled. - reactance : optional - Reactance value in ohms. The default is ``0``. If ``None``, - this parameter is disabled. - is_inifinite_ground : bool, optional - Whether the impedance is an infinite ground. The default is ``False``. - - Returns - ------- - :class:`ansys.aedt.core.modules.boundary.BoundaryObject` - Boundary object if successful, ``False`` otherwise. - - References - ---------- - - >>> oModule.AssignImpedance - - Examples - -------- - - Create a sheet and use it to create an impedance. - - >>> sheet = hfss.modeler.create_rectangle(hfss.PLANE.XY, - ... [0, 0, -90], [10, 2], name="ImpedanceSheet", - ... material="Copper") - >>> impedance_to_sheet = hfss.assign_impedance_to_sheet(sheet.name,"ImpedanceFromSheet",100,50) - >>> type(impedance_to_sheet) - - - """ - - if self.solution_type in ["Modal", "Terminal", "Transient Network"]: - if not name: - name = generate_unique_name("Imped") - elif name in self.modeler.get_boundaries_name(): - name = generate_unique_name(name) - - objects = self.modeler.convert_to_selections(assignment, True) - - props = dict( - { - "Faces": objects, - } - ) - if isinstance(objects[0], str): - props = dict( - { - "Objects": objects, - } - ) - props["Resistance"] = str(resistance) - props["Reactance"] = str(reactance) - props["InfGroundPlane"] = is_inifinite_ground - - return self._create_boundary(name, props, "Impedance") - return False - @pyaedt_function_handler( sheet_name="assignment", sourcename="name", is_infground="is_infinite_ground", reference_cs="coordinate_system" ) @@ -3643,7 +3574,7 @@ def assign_impedance_to_sheet( """ - if self.solution_type in ["Modal", "Terminal", "Transient Network"]: + if self.solution_type in ["Modal", "Terminal", "Transient Network", "Eigenmode"]: if not name: name = generate_unique_name("Imped") elif name in self.modeler.get_boundaries_name(): diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py index 8bf8447e0c2..15e54a4ecb1 100644 --- a/tests/system/general/test_20_HFSS.py +++ b/tests/system/general/test_20_HFSS.py @@ -737,7 +737,7 @@ def test_15_create_perfects_on_sheets(self): assert perfect_e_eigen.name in self.aedtapp.modeler.get_boundaries_name() self.aedtapp.solution_type = "solution_type" - def test_16_create_impedance_on_sheets(self): + def test_16_a_create_impedance_on_sheets(self): rect = self.aedtapp.modeler.create_rectangle( self.aedtapp.PLANE.XY, [0, 0, 0], [10, 2], name="ImpBound", material="Copper" ) @@ -760,6 +760,14 @@ def test_16_create_impedance_on_sheets(self): imp3 = self.aedtapp.assign_impedance_to_sheet(impedance_box.top_face_z.id, "TL4", [50, 20, 0, 0], [25, 0, 5, 0]) assert imp3.name in self.aedtapp.modeler.get_boundaries_name() + def test_16_b_create_impedance_on_sheets_eigenmode(self, add_app): + aedtapp = add_app(solution_type="Eigenmode", project_name="test_16_b") + rect = aedtapp.modeler.create_rectangle( + aedtapp.PLANE.XY, [0, 0, 0], [10, 2], name="ImpBound", material="Copper" + ) + imp1 = aedtapp.assign_impedance_to_sheet(rect.name, "TL2", 50, 25) + assert imp1.name in aedtapp.modeler.get_boundaries_name() + def test_17_create_lumpedrlc_on_sheets(self): rect = self.aedtapp.modeler.create_rectangle( self.aedtapp.PLANE.XY, [0, 0, 0], [10, 2], name="rlcBound", material="Copper" From 3c8503b2a90fea38fac0215dcc1a9245c711812c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Morais?= <146729917+SMoraisAnsys@users.noreply.github.com> Date: Tue, 5 Nov 2024 18:46:06 +0100 Subject: [PATCH 07/13] TEST: Improve touchstone parser coverage (#5349) --- .../advanced/touchstone_parser.py | 42 +++--------- tests/conftest.py | 14 ++++ tests/integration/test_touchstone_data.py | 66 +++++++++++++++++++ .../general/test_44_TouchstoneParser.py | 59 ++++++++++++++++- 4 files changed, 148 insertions(+), 33 deletions(-) create mode 100644 tests/integration/test_touchstone_data.py diff --git a/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py b/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py index a0d81bec98c..8f46baa50d3 100644 --- a/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py +++ b/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py @@ -29,6 +29,7 @@ import subprocess import warnings +from ansys.aedt.core.aedt_logger import pyaedt_logger as logger from ansys.aedt.core.generic.aedt_versions import aedt_versions from ansys.aedt.core.generic.general_methods import pyaedt_function_handler @@ -67,30 +68,6 @@ keys = {REAL_IMAG: ("real", "imag"), MAG_ANGLE: ("mag", "deg"), DB_ANGLE: ("db20", "deg")} -def _parse_ports_name(file): - """Parse and interpret the option line in the touchstone file. - - Parameters - ---------- - file : str - Path of the touchstone file. - - Returns - ------- - List of str - Names of the ports in the touchstone file. - - """ - portnames = [] - line = file.readline() - while not line.startswith("! Port"): - line = file.readline() - while line.startswith("! Port"): - portnames.append(line.split(" = ")[1].strip()) - line = file.readline() - return portnames - - class TouchstoneData(rf.Network): """Contains data information from Touchstone Read call.""" @@ -180,7 +157,7 @@ def plot_insertion_losses(self, threshold=-3, plot=True): List of tuples representing insertion loss excitations. """ temp_list = self.get_insertion_loss_index(threshold=threshold) - if plot: # pragma: no cover + if plot: for i in temp_list: self.plot_s_db(*i, logx=self.log_x) plt.show() @@ -208,9 +185,9 @@ def plot(self, index_couples=None, show=True): self.plot_s_db(*i, logx=self.log_x) if show: plt.show() - return plt + return True - def plot_return_losses(self): # pragma: no cover + def plot_return_losses(self): """Plot all return losses. Returns @@ -260,6 +237,7 @@ def get_mixed_mode_touchstone_data(self, num_of_diff_ports=None, port_ordering=" ts_diff.renumber(port_order, new_port_order) else: + logger.error("Invalid input provided for 'port_ordering'.") return False ts_diff.se2gmm(num_of_diff_ports) @@ -320,7 +298,7 @@ def get_insertion_loss_index_from_prefix(self, tx_prefix, rx_prefix): receiver_list = [i for i in self.port_names if rx_prefix in i] values = [] if len(trlist) != len(receiver_list): - print("TX and RX should be same length lists") + logger.error("TX and RX should be same length lists.") return False for i, j in zip(trlist, receiver_list): values.append([self.port_names.index(i), self.port_names.index(j)]) @@ -587,12 +565,12 @@ def find_touchstone_files(input_dir): Dictionary with the SNP file names as the key and the absolute path as the value. """ out = {} - if not os.path.exists(input_dir): # pragma: no cover + if not os.path.exists(input_dir): return out pat_snp = re.compile(r"\.s\d+p$", re.IGNORECASE) - sNpFiles = {f: os.path.join(input_dir, f) for f in os.listdir(input_dir) if re.search(pat_snp, f)} + files = {f: os.path.join(input_dir, f) for f in os.listdir(input_dir) if re.search(pat_snp, f)} pat_ts = re.compile("\.ts$") for f in os.listdir(input_dir): if re.search(pat_ts, f): - sNpFiles[f] = os.path.abspath(os.path.join(input_dir, f)) - return sNpFiles + files[f] = os.path.abspath(os.path.join(input_dir, f)) + return files diff --git a/tests/conftest.py b/tests/conftest.py index f23f5a2648e..2daabf60f5b 100644 --- a/tests/conftest.py +++ b/tests/conftest.py @@ -45,3 +45,17 @@ def pytest_collection_modifyitems(config: pytest.Config, items: List[pytest.Item item.add_marker(pytest.mark.solvers) elif item.nodeid.startswith(SYSTEM_GENERAL_TEST_PREFIX): item.add_marker(pytest.mark.general) + + +@pytest.fixture +def touchstone_file(tmp_path): + file_path = tmp_path / "dummy.s2p" + file_content = """ +! Terminal data exported +! Port[1] = Port1 +! Port[2] = Port2 +0.1 0.1 0.2 +""" + + file_path.write_text(file_content) + return file_path diff --git a/tests/integration/test_touchstone_data.py b/tests/integration/test_touchstone_data.py new file mode 100644 index 00000000000..336b86bd7e2 --- /dev/null +++ b/tests/integration/test_touchstone_data.py @@ -0,0 +1,66 @@ +# -*- coding: utf-8 -*- +# +# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# SPDX-License-Identifier: MIT +# +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +from unittest.mock import patch + +from ansys.aedt.core.visualization.advanced.touchstone_parser import TouchstoneData + + +@patch("ansys.aedt.core.visualization.advanced.touchstone_parser.plt") +def test_plot_insertion_losses(mock_show, touchstone_file): + ts = TouchstoneData(touchstone_file=touchstone_file) + res = ts.plot_insertion_losses() + + assert res is not [] + mock_show.show.assert_called_once() + + +@patch.object(TouchstoneData, "plot_s_db") +@patch("ansys.aedt.core.visualization.advanced.touchstone_parser.plt") +def test_plot(mock_show, mock_plot_s_db, touchstone_file): + ts = TouchstoneData(touchstone_file=touchstone_file) + res = ts.plot(show=True) + + assert res + mock_show.show.assert_called_once() + + +@patch.object(TouchstoneData, "plot_s_db") +@patch("ansys.aedt.core.visualization.advanced.touchstone_parser.plt") +def test_plot_next_xtalk_losses(mock_show, mock_plot_s_db, touchstone_file): + ts = TouchstoneData(touchstone_file=touchstone_file) + res = ts.plot_next_xtalk_losses() + + assert res + mock_show.show.assert_called_once() + + +@patch.object(TouchstoneData, "plot_s_db") +@patch("ansys.aedt.core.visualization.advanced.touchstone_parser.plt") +def test_plot_fext_xtalk_losses(mock_show, mock_plot_s_db, touchstone_file): + ts = TouchstoneData(touchstone_file=touchstone_file) + res = ts.plot_fext_xtalk_losses("Port", "Port") + + assert res + mock_show.show.assert_called_once() diff --git a/tests/system/general/test_44_TouchstoneParser.py b/tests/system/general/test_44_TouchstoneParser.py index 9242fe85fbb..77068edea35 100644 --- a/tests/system/general/test_44_TouchstoneParser.py +++ b/tests/system/general/test_44_TouchstoneParser.py @@ -22,9 +22,13 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. +import logging import os from ansys.aedt.core import Hfss3dLayout +from ansys.aedt.core.visualization.advanced.touchstone_parser import TouchstoneData +from ansys.aedt.core.visualization.advanced.touchstone_parser import find_touchstone_files +from mock import patch import pytest from tests import TESTS_GENERAL_PATH @@ -57,7 +61,6 @@ def test_01_get_touchstone_data(self): assert ts_data.get_fext_xtalk_index_from_prefix("diff1", "diff2") def test_02_read_ts_file(self): - from ansys.aedt.core.visualization.advanced.touchstone_parser import TouchstoneData ts1 = TouchstoneData(touchstone_file=os.path.join(test_T44_dir, "port_order_1234.s8p")) assert ts1.get_mixed_mode_touchstone_data() @@ -77,3 +80,57 @@ def test_03_check_touchstone_file(self): assert v[1] elif v and v[0] == "causality": assert not v[1] + + +def test_get_mixed_mode_touchstone_data_failure(touchstone_file, caplog: pytest.LogCaptureFixture): + ts = TouchstoneData(touchstone_file=touchstone_file) + + assert not ts.get_mixed_mode_touchstone_data(port_ordering="12") + assert [ + record + for record in caplog.records + if record.levelno == logging.ERROR and record.message == "Invalid input provided for 'port_ordering'." + ] + + +def test_get_return_loss_index_with_dummy_prefix(touchstone_file): + ts = TouchstoneData(touchstone_file=touchstone_file) + res = ts.get_return_loss_index(excitation_name_prefix="dummy_prefix") + + assert not res + + +def test_get_insertion_loss_index_from_prefix_failure(touchstone_file, caplog: pytest.LogCaptureFixture): + ts = TouchstoneData(touchstone_file=touchstone_file) + res = ts.get_insertion_loss_index_from_prefix("Port", "Dummy") + + assert not res + assert [ + record + for record in caplog.records + if record.levelno == logging.ERROR and record.message == "TX and RX should be same length lists." + ] + + +def test_get_next_xtalk_index_with_dummy_prefix(touchstone_file): + ts = TouchstoneData(touchstone_file=touchstone_file) + res = ts.get_next_xtalk_index("Dummy") + + assert not res + + +@patch("os.path.exists", return_value=False) +def test_find_touchstone_files_with_non_existing_directory(mock_exists): + res = find_touchstone_files("dummy_path") + + assert res == {} + + +@patch("os.path.exists", return_value=True) +@patch("os.listdir") +def test_find_touchstone_files_success(mock_listdir, mock_exists): + mock_listdir.return_value = {"dummy.ts", "dummy.txt"} + res = find_touchstone_files("dummy_path") + + assert "dummy.ts" in res + assert "dummy.txt" not in res From 9f0e163d823e013a7c5fcfb3670adf0a135c33c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Morais?= <146729917+SMoraisAnsys@users.noreply.github.com> Date: Wed, 6 Nov 2024 09:10:08 +0100 Subject: [PATCH 08/13] REFACTOR: General code improvements (#5378) --- src/ansys/aedt/core/modeler/schematic.py | 3 ++- src/ansys/aedt/core/modules/material_workbench.py | 14 ++++++++++++-- src/ansys/aedt/core/modules/solve_setup.py | 12 ++++++------ .../advanced/farfield_visualization.py | 14 ++++++++++---- .../aedt/core/workflows/templates/pyaedt_utils.py | 2 +- 5 files changed, 31 insertions(+), 14 deletions(-) diff --git a/src/ansys/aedt/core/modeler/schematic.py b/src/ansys/aedt/core/modeler/schematic.py index fb66aae0121..5d4320e40f0 100644 --- a/src/ansys/aedt/core/modeler/schematic.py +++ b/src/ansys/aedt/core/modeler/schematic.py @@ -589,7 +589,8 @@ def primitives(self): @model_units.setter def model_units(self, units): """Set the model units as a string e.g. "mm".""" - assert units in AEDT_UNITS["Length"], f"Invalid units string {units}" + if units not in AEDT_UNITS["Length"]: + raise RuntimeError(f"Invalid units string {units}.") self.oeditor.SetActivelUnits(["NAME:Units Parameter", "Units:=", units, "Rescale:=", False]) @pyaedt_function_handler(selections="assignment", pos="offset") diff --git a/src/ansys/aedt/core/modules/material_workbench.py b/src/ansys/aedt/core/modules/material_workbench.py index ce6bd6e57cb..0fa47920eac 100644 --- a/src/ansys/aedt/core/modules/material_workbench.py +++ b/src/ansys/aedt/core/modules/material_workbench.py @@ -31,10 +31,14 @@ from collections import defaultdict import copy import re -import xml.etree.ElementTree as ET +from xml.etree.ElementTree import ParseError +from ansys.aedt.core.aedt_logger import pyaedt_logger as logger from ansys.aedt.core.generic.data_handlers import normalize_string_format from ansys.aedt.core.modules.material import MatProperties +import defusedxml + +defusedxml.defuse_stdlib() class MaterialWorkbench: @@ -86,7 +90,13 @@ def _etree_to_dict(t): @staticmethod def _parse_xml(file_path): """Parse an XML file and convert it into a dictionary.""" - tree = ET.parse(file_path) + # Load the XML file + try: + tree = defusedxml.ElementTree.parse(file_path) + except ParseError: # pragma: no cover + logger.error(f"Unable to parse {file_path}.") + return + root = tree.getroot() return MaterialWorkbench._etree_to_dict(root) diff --git a/src/ansys/aedt/core/modules/solve_setup.py b/src/ansys/aedt/core/modules/solve_setup.py index d5bd625fb1b..71b5c09638c 100644 --- a/src/ansys/aedt/core/modules/solve_setup.py +++ b/src/ansys/aedt/core/modules/solve_setup.py @@ -33,8 +33,8 @@ from __future__ import absolute_import # noreorder import os.path -from random import randrange import re +import secrets import time import warnings @@ -2016,7 +2016,7 @@ def _get_net_names(self, app, file_fullname, unite): if len(object_names) == 1: object_p = aedtapp.modeler[object_names[0]] object_p.name = net_name - object_p.color = [randrange(255), randrange(255), randrange(255)] # nosec + object_p.color = [secrets.randbelow(255), secrets.randbelow(255), secrets.randbelow(255)] elif len(object_names) > 1: if unite: united_object = aedtapp.modeler.unite(object_names, purge=True) @@ -2024,10 +2024,10 @@ def _get_net_names(self, app, file_fullname, unite): if obj_ind: aedtapp.modeler.objects[obj_ind].name = net_name aedtapp.modeler.objects[obj_ind].color = [ - randrange(255), - randrange(255), - randrange(255), - ] # nosec + secrets.randbelow(255), + secrets.randbelow(255), + secrets.randbelow(255), + ] else: name_cont = 0 for body in object_names: diff --git a/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py b/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py index 219f2cf7423..488780ba25b 100644 --- a/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py +++ b/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py @@ -41,6 +41,8 @@ from ansys.aedt.core.visualization.plot.matplotlib import is_notebook from ansys.aedt.core.visualization.plot.pyvista import ModelPlotter from ansys.aedt.core.visualization.plot.pyvista import get_structured_mesh +import defusedxml +from defusedxml.ElementTree import ParseError try: import numpy as np @@ -60,6 +62,8 @@ ) pv = None +defusedxml.defuse_stdlib() + class FfdSolutionData(object): """Provides antenna far-field data. @@ -1812,12 +1816,14 @@ def antenna_metadata_from_xml(input_file): Metadata information. """ - import xml.etree.ElementTree as ET # nosec - # Load the XML file - tree = ET.parse(input_file) # nosec - root = tree.getroot() + try: + tree = defusedxml.ElementTree.parse(input_file) + except ParseError: # pragma: no cover + logger.error(f"Unable to parse {input_file}.") + return + root = tree.getroot() element_patterns = root.find("ElementPatterns") sources = [] diff --git a/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py b/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py index 2c91258a451..8f65431a8c8 100644 --- a/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py +++ b/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py @@ -143,7 +143,7 @@ def environment_variables(oDesktop): def generate_unique_name(root_name, suffix="", n=6): char_set = string.ascii_uppercase + string.digits - unique_name = root_name + "_" + "".join(random.choice(char_set) for _ in range(n)) # nosec + unique_name = root_name + "_" + "".join(random.choice(char_set) for _ in range(n)) # nosec B311 if suffix: unique_name += suffix return unique_name From 73be523fbd1b9e22f4458e7a10c00bddd90226a7 Mon Sep 17 00:00:00 2001 From: Samuel Lopez <85613111+Samuelopez-ansys@users.noreply.github.com> Date: Wed, 6 Nov 2024 15:29:49 +0100 Subject: [PATCH 09/13] FIX: Check valid name and file (#5383) --- .../aedt/core/workflows/installer/extension_manager.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/ansys/aedt/core/workflows/installer/extension_manager.py b/src/ansys/aedt/core/workflows/installer/extension_manager.py index b57565df6e9..d5a52976290 100644 --- a/src/ansys/aedt/core/workflows/installer/extension_manager.py +++ b/src/ansys/aedt/core/workflows/installer/extension_manager.py @@ -256,6 +256,9 @@ def button_is_clicked( name = selected_toolkit_info.get("name") icon = os.path.abspath(os.path.join(product_path, selected_toolkit_info.get("icon"))) + valid_name = name is not None and not os.path.isdir(name) + valid_file = file is not None and os.path.isfile(file) + if selected_toolkit_name != "Custom" and selected_toolkit_info.get("pip"): if is_toolkit_installed(selected_toolkit_name, toolkit_level) and install_action: desktop.logger.info(f"Updating {selected_toolkit_name}") @@ -277,7 +280,8 @@ def button_is_clicked( else: desktop.logger.info(f"{selected_toolkit_name} not installed") - else: + elif valid_name and valid_file: + if install_action: desktop.logger.info("Install {}".format(name)) @@ -287,6 +291,7 @@ def button_is_clicked( file = os.path.join( os.path.dirname(ansys.aedt.core.workflows.templates.__file__), "extension_template.py" ) + if os.path.isfile(executable_interpreter): template_file = "run_pyaedt_toolkit_script" if selected_toolkit_info: From 51de3f192a30e8d036d5f00dbe64a5845fffe8c6 Mon Sep 17 00:00:00 2001 From: Isaac Waldron Date: Wed, 6 Nov 2024 09:31:25 -0500 Subject: [PATCH 10/13] FEAT: Expose port properties on Components3dLayout (#5376) --- .../aedt/core/modeler/pcb/object_3d_layout.py | 171 +- .../T40/ANSYS-HSD_V1.aedb/edb.def | Bin 4142752 -> 4144439 bytes .../example_models/T40/ANSYS-HSD_V1.aedt | 2203 +++++++++++------ tests/system/general/test_01_3dlayout_edb.py | 27 + 4 files changed, 1537 insertions(+), 864 deletions(-) diff --git a/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py b/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py index b505a225eb3..12c85725348 100644 --- a/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py +++ b/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py @@ -31,6 +31,8 @@ import math import re +from typing import Optional +from typing import Tuple from ansys.aedt.core.generic.constants import unit_converter from ansys.aedt.core.generic.general_methods import _dim_arg @@ -48,6 +50,7 @@ class Object3DLayout(object): def __init__(self, primitives, prim_type=None): self._primitives = primitives + self.logger = self._primitives.logger self._oeditor = self._primitives.oeditor self._n = 10 self.prim_type = prim_type @@ -267,7 +270,7 @@ def create_clearance_on_component(self, extra_soldermask_clearance=5e-3): bool """ if self.prim_type != "component": - self._primitives.logger.error("Clearance applies only to components.") + self.logger.error("Clearance applies only to components.") return False bbox = self.bounding_box start_points = [bbox[0] - extra_soldermask_clearance, bbox[1] - extra_soldermask_clearance] @@ -467,6 +470,37 @@ def __init__(self, primitives, name="", edb_object=None): self.edb_object = edb_object self._pins = {} + @staticmethod + def __get_die_properties(model_info): + s = r".+DieProp\(dt=(.+?), do=(.+?), dh='(.+?)', lid=(.+?)\)" + m = re.search(s, model_info) + dt = 0 + do = 0 + dh = "0" + lid = -100 + if m: + dt = int(m.group(1)) + do = int(m.group(2)) + dh = str(m.group(3)) + lid = int(m.group(4)) + return dt, do, dh, lid + + @staticmethod + def __get_port_properties(model_info): + s = r".+PortProp\(rh='(.+?)', rsa=(.+?), rsx='(.+?)', rsy='(.+?)'\)" + m = re.search(s, model_info) + rsx = "0" + rsy = "0" + rsa = True + rh = "0" + if m: + rh = m.group(1) + rsx = m.group(3) + rsy = m.group(4) + if m.group(2) == "false": + rsa = False + return rh, rsa, rsx, rsy + @property def part(self): """Retrieve the component part. @@ -499,8 +533,7 @@ def part_type(self): """ return self._oeditor.GetPropertyValue("BaseElementTab", self.name, "Part Type") - @property - def _part_type_id(self): + def __part_type_id(self): parts = {"Other": 0, "Resistor": 1, "Inductor": 2, "Capacitor": 3, "IC": 4, "IO": 5} if self.part_type in parts: return parts[self.part_type] @@ -530,10 +563,83 @@ def enabled(self): @enabled.setter def enabled(self, status): - if self._part_type_id in [0, 4, 5]: + if self.__part_type_id() in [0, 4, 5]: return False self._oeditor.EnableComponents(["NAME:Components", self.name], status) + @property + def die_properties(self) -> Optional[Tuple[int, int, str, int]]: + """Get die properties from component. + + Returns + ------- + Tuple[int, int, str, int] + Tuple of die type (``0`` for None, ``1``, for FlipChip, or ``2`` for WireBond), die orientation (``0`` for + Chip Top or ``1`` for Chip Bottom), die height as a string, and a reserved property as an integer. + """ + if self.__part_type_id() != 4: + return None + return Components3DLayout.__get_die_properties(self.__get_model_info()) + + def __has_port_properties(self) -> bool: + return self.__part_type_id() in [0, 4, 5] + + @property + def port_properties(self) -> Optional[Tuple[str, bool, str, str]]: + """Get port properties from component. + + Returns + ------- + Tuple[str, bool, str, str] + Tuple of reference offset [str], reference size auto [bool], reference size X dimension [str], reference + size Y dimension [str]. + """ + if not self.__has_port_properties(): + return None + return Components3DLayout.__get_port_properties(self.__get_model_info()) + + @port_properties.setter + def port_properties(self, values: Tuple[str, bool, str, str]): + rh, rsa, rsx, rsy = values + if not self.__has_port_properties(): + self.logger.warning( + f"Cannot set port_properties on {self.name!r} with part type ID {self.__part_type_id()!r}" + ) + return + if self.__part_type_id() == 4: + prop_name = "ICProp:=" + else: + prop_name = "IOProp:=" + port_properties = ["rh:=", rh, "rsa:=", rsa, "rsx:=", rsx, "rsy:=", rsy] + + args = [ + "NAME:Model Info", + [ + "NAME:Model", + prop_name, + [ + "PortProp:=", + port_properties, + ], + ], + ] + if self.__part_type_id() == 4: + dt, do, dh, lid = self.die_properties + args[1] = [ + "NAME:Model", + prop_name, + [ + "DieProp:=", + ["dt:=", dt, "do:=", do, "dh:=", dh, "lid:=", lid], + "PortProp:=", + port_properties, + ], + "CompType:=", + 4, + ] + + self.change_property(args) + @property def solderball_enabled(self): """Check if solderball is enabled. @@ -543,7 +649,7 @@ def solderball_enabled(self): bool ``True`` when successful, ``False`` when failed. """ - if self._part_type_id not in [0, 4, 5]: + if not self.__has_port_properties(): return False component_info = str(list(self._oeditor.GetComponentInfo(self.name))).replace("'", "").replace('"', "") if "sbsh=Cyl" in component_info or "sbsh=Sph" in component_info: @@ -559,7 +665,7 @@ def die_enabled(self): bool ``True`` when successful, ``False`` when failed. """ - if self._part_type_id not in [0, 4, 5]: + if not self.__has_port_properties(): return False component_info = str(list(self._oeditor.GetComponentInfo(self.name))).replace("'", "").replace('"', "") if "dt=1" in component_info or "dt=2" in component_info: @@ -574,7 +680,7 @@ def die_type(self): ------- str """ - if self._part_type_id not in [0, 4, 5]: + if not self.__has_port_properties(): return False component_info = str(list(self._oeditor.GetComponentInfo(self.name))).replace("'", "").replace('"', "") if "dt=1" in component_info: @@ -620,12 +726,12 @@ def set_die_type( bool ``True`` when successful, ``False`` when failed. """ - if self._part_type_id not in [0, 4, 5]: + if not self.__has_port_properties(): return False if auto_reference: reference_x = "0" reference_y = "0" - if self._part_type_id == 4: + if self.__part_type_id() == 4: prop_name = "ICProp:=" else: prop_name = "IOProp:=" @@ -690,43 +796,17 @@ def set_solderball( bool ``True`` when successful, ``False`` when failed or the wrong component type. """ - if self._part_type_id not in [0, 4, 5]: + if not self.__has_port_properties(): return False - props = self._oeditor.GetComponentInfo(self.name) - model = "" - for p in props: - if "PortProp(" in p: - model = p - break - s = r".+PortProp\(rh='(.+?)', rsa=(.+?), rsx='(.+?)', rsy='(.+?)'\)" - m = re.search(s, model) - rsx = "0" - rsy = "0" - rsa = True - rh = "0" - if m: - rh = m.group(1) - rsx = m.group(3) - rsy = m.group(4) - if m.group(2) == "false": - rsa = False + model_info = self.__get_model_info() + rh, rsa, rsx, rsy = Components3DLayout.__get_port_properties(model_info) if reference_offset: rh = reference_offset - if self._part_type_id == 4: + if self.__part_type_id() == 4: prop_name = "ICProp:=" if not self.die_enabled: self.set_die_type() - s = r".+DieProp\(dt=(.+?), do=(.+?), dh='(.+?)', lid=(.+?)\)" - m = re.search(s, model) - dt = 0 - do = 0 - dh = "0" - lid = -100 - if m: - dt = int(m.group(1)) - do = int(m.group(2)) - dh = str(m.group(3)) - lid = int(m.group(4)) + dt, do, dh, lid = Components3DLayout.__get_die_properties(model_info) args = [ "NAME:Model Info", @@ -784,6 +864,15 @@ def set_solderball( ] return self.change_property(args) + def __get_model_info(self): + props = self._oeditor.GetComponentInfo(self.name) + model_info = "" + for p in props: + if "PortProp(" in p: + model_info = p + break + return model_info + @property def pins(self): """Component pins. @@ -806,7 +895,7 @@ def model(self): ------- :class:`ansys.aedt.core.modeler.cad.object_3dlayout.ModelInfoRlc` """ - if self._part_type_id in [1, 2, 3]: + if self.__part_type_id() in [1, 2, 3]: return ModelInfoRlc(self, self.name) diff --git a/tests/system/general/example_models/T40/ANSYS-HSD_V1.aedb/edb.def b/tests/system/general/example_models/T40/ANSYS-HSD_V1.aedb/edb.def index 0f6f690823f64b59be74993526207b0e2175bbec..a2748ae758b4002a35ac1425ab3adcee99c115b9 100644 GIT binary patch delta 1809 zcmbu9du&rx9LINWd)jsKaGPT*W31z0H`vN;*Y$R61A8 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+++ b/tests/system/general/example_models/T40/ANSYS-HSD_V1.aedt @@ -68,7 +68,7 @@ $begin 'AnsoftProject' ReadVersion=11 $begin 'EDB' Path='' - LastUpdateTimeStamp=1687268212 + LastUpdateTimeStamp=1730736753 $end 'EDB' $begin 'DesignMgrEnvironment' CompInstCounter=1 @@ -190,6 +190,32 @@ $begin 'AnsoftProject' LibLocation='Project' ModSinceLib=true $end 'Solder Resist' + $begin 'solder' + CoordinateSystemType='Cartesian' + BulkOrSurfaceType=1 + $begin 'PhysicsTypes' + set('Electromagnetic', 'Thermal', 'Structural') + $end 'PhysicsTypes' + $begin 'AttachedData' + $begin 'MatAppearanceData' + property_data='appearance_data' + Red=184 + Green=184 + Blue=179 + $end 'MatAppearanceData' + $end 'AttachedData' + conductivity='7000000' + thermal_conductivity='48' + mass_density='8000' + specific_heat='167' + youngs_modulus='69000000000' + poissons_ratio='0.4' + thermal_expansion_coefficient='1.59e-06' + ModTime=1499970477 + Library='Materials' + LibLocation='SysLibrary' + ModSinceLib=false + $end 'solder' $end 'Materials' $begin 'SurfaceMaterials' $end 'SurfaceMaterials' @@ -3983,7 +4009,7 @@ $begin 'AnsoftProject' $begin 'SolutionManager' $begin 'SimDataExtractors' $begin 'Version ID Map' - V=1 + V=4 $end 'Version ID Map' $end 'SimDataExtractors' $end 'SolutionManager' @@ -4055,7 +4081,7 @@ $begin 'AnsoftProject' Notes=$begin_cdata$ $end_cdata$ $begin 'AnimationSetups' $end 'AnimationSetups' - CacheHeaderFile='HDR06587864416872682124.tmp' + CacheHeaderFile='HDR026412984017307367534.tmp' $end 'PlanarEMCircuit' $begin 'DataInstances' DesignEditor='TopLevel' @@ -4088,7 +4114,7 @@ $begin 'AnsoftProject' DesignInstanceID=1 $begin 'WindowPosition' $begin 'EditorWindow' - Circuit(Layout(View(WindowPos(3, -1, -1, -8, -31, 0, 0, 136, 50), Extent(-0.880303025245667, -1, 0.880303025245667, 1, 13233.0194641431, 13227.407029494, -0.0304119139909744, 0.0617876723408699, 0.142900109291077, 0.079305037856102, 1), ViewingXfm(-0.843162536621094, 0.385907143354416, -0.47620815038681, 0.205886602401733, 313.394195556641, 321.303497314453, 8.60090065002441, 0, 0, 0, 0, 8.60090065002441, 0, 0, 0, 0, 8.60090065002441, 0, -0.581592679023743, -0.325543016195297, -317.356353759766, 1))), Layout()) + Circuit(Layout(View(WindowPos(3, -1, -1, -8, -31, 0, 0, 136, 50), Extent(-0.880303025245667, -1, 0.880303025245667, 1, 124149.806071328, 123994.966714253, -0.00693838158622384, 0.0408204905688763, 0.0110833793878555, 0.00408080965280533, 1), ViewingXfm(-2.71597599983215, 2.71597599983215, -1, 1, -226.236145019531, 226.725463867188, 405.695373535156, -39.9712066650391, -272.048675537109, 0, -206.875793457031, 275.056610107422, -348.916625976563, 0, 181.138809204102, 403.661376953125, 210.814010620117, 0, 0.68451714515686, -19.0060615539551, 33.5877227783203, 1))), Layout()) $end 'EditorWindow' $end 'WindowPosition' $begin 'ReportSetup' @@ -4194,9 +4220,9 @@ $begin 'AnsoftProject' currentTextStyle=0 currentTraceStyle=0 prevBounds(-0.880303025245667, -1, 0.880303025245667, 1) - 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reason="Introduced in 2024R1") def test_24_open_ic_mode_design(self): assert self.ic_mode_design.ic_mode + + def test_25a_set_port_properties(self): + component: Components3DLayout = self.aedtapp.modeler.components["Q1"] + assert component.port_properties == ("0", True, "0", "0") + new_values = ("10um", False, "0um", "0um") + component.port_properties = new_values + assert component.port_properties == new_values + + def test_25b_set_port_properties_on_ic_component(self): + component: Components3DLayout = self.aedtapp.modeler.components["U10"] + original_die_properties = component.die_properties + assert component.port_properties == ("0", True, "0", "0") + new_values = ("10um", False, "0um", "0um") + component.port_properties = new_values + assert component.port_properties == new_values + assert component.die_properties == original_die_properties + + def test_25c_get_properties_on_rlc_component(self): + component: Components3DLayout = self.aedtapp.modeler.components["C1"] + assert component.die_properties is None + assert component.port_properties is None + + def test_25d_set_port_properties_on_rlc_component(self): + component: Components3DLayout = self.aedtapp.modeler.components["C1"] + component.port_properties = ("10um", False, "0um", "0um") + assert component.port_properties is None From 72dd3bd9fb74ab80b561cd246f8770e130151d6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Morais?= <146729917+SMoraisAnsys@users.noreply.github.com> Date: Wed, 6 Nov 2024 15:35:07 +0100 Subject: [PATCH 11/13] CI: Update bug template python versions (#5380) --- .github/ISSUE_TEMPLATE/bug.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/ISSUE_TEMPLATE/bug.yml b/.github/ISSUE_TEMPLATE/bug.yml index d9e673cffc5..47a74452da9 100644 --- a/.github/ISSUE_TEMPLATE/bug.yml +++ b/.github/ISSUE_TEMPLATE/bug.yml @@ -64,7 +64,7 @@ body: - '3.9' - '3.10' - '3.11' - - 'IronPython' + - '3.12' validations: required: true From c46eca847a46781a07e55efa6fb933ffa22d7116 Mon Sep 17 00:00:00 2001 From: Massimo Capodiferro <77293250+maxcapodi78@users.noreply.github.com> Date: Wed, 6 Nov 2024 17:37:29 +0100 Subject: [PATCH 12/13] FEAT: Import nastran improvements (#5364) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: maxcapodi78 Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com> Co-authored-by: Samuelopez-ansys --- src/ansys/aedt/core/application/design.py | 1 + src/ansys/aedt/core/modeler/cad/primitives.py | 8 +- src/ansys/aedt/core/modeler/modeler_3d.py | 11 ++- src/ansys/aedt/core/modules/solve_setup.py | 11 +++ .../aedt/core/visualization/advanced/misc.py | 75 ++++++++++++++++++- .../general/example_models/T20/test_cad_2.nas | 35 ++++++++- tests/system/general/test_20_HFSS.py | 4 +- tests/system/solvers/test_45_workflows.py | 2 +- 8 files changed, 133 insertions(+), 14 deletions(-) diff --git a/src/ansys/aedt/core/application/design.py b/src/ansys/aedt/core/application/design.py index b3fbd0acd09..ca7af8a9020 100644 --- a/src/ansys/aedt/core/application/design.py +++ b/src/ansys/aedt/core/application/design.py @@ -3132,6 +3132,7 @@ def change_validation_settings( ---------- entity_check_level : str, optional Entity check level. The default is ``"Strict"``. + Options are ``"Strict"``, ``"Basic"``, ``"Warning Only"``, ``"None"``. ignore_unclassified : bool, optional Whether to ignore unclassified elements. The default is ``False``. skip_intersections : bool, optional diff --git a/src/ansys/aedt/core/modeler/cad/primitives.py b/src/ansys/aedt/core/modeler/cad/primitives.py index 4da34256a9a..71a5a065c9f 100644 --- a/src/ansys/aedt/core/modeler/cad/primitives.py +++ b/src/ansys/aedt/core/modeler/cad/primitives.py @@ -4777,6 +4777,7 @@ def import_3d_cad( reduce_percentage=0, reduce_error=0, merge_planar_faces=True, + merge_angle=0.02, ): """Import a CAD model. @@ -4787,9 +4788,6 @@ def import_3d_cad( healing : bool, optional Whether to perform healing. The default is ``False``, in which case healing is not performed. - healing : int, optional - Whether to perform healing. The default is ``0``, in which - case healing is not performed. refresh_all_ids : bool, optional Whether to refresh all IDs after the CAD file is loaded. The default is ``True``. Refreshing IDs can take a lot of time in @@ -4818,6 +4816,8 @@ def import_3d_cad( Stl error percentage during reduce operation. Default is ``0``. merge_planar_faces : bool, optional Stl automatic planar face merge during import. Default is ``True``. + merge_angle : float, optional + Stl import angle in radians for which faces will be considered planar. Default is ``2e-2``. Returns ------- @@ -4844,7 +4844,7 @@ def import_3d_cad( vArg1.append("CreateGroup:="), vArg1.append(create_group) vArg1.append("STLFileUnit:="), vArg1.append("Auto") vArg1.append("MergeFacesAngle:="), vArg1.append( - 0.02 if input_file.endswith(".stl") and merge_planar_faces else -1 + merge_angle if input_file.endswith(".stl") and merge_planar_faces else -1 ) if input_file.endswith(".stl"): vArg1.append("HealSTL:="), vArg1.append(heal_stl) diff --git a/src/ansys/aedt/core/modeler/modeler_3d.py b/src/ansys/aedt/core/modeler/modeler_3d.py index 8c83a9ebc6a..834453b494a 100644 --- a/src/ansys/aedt/core/modeler/modeler_3d.py +++ b/src/ansys/aedt/core/modeler/modeler_3d.py @@ -1042,6 +1042,7 @@ def import_nastran( enable_planar_merge="True", save_only_stl=False, preview=False, + merge_angle=1e-3, ): """Import Nastran file into 3D Modeler by converting the faces to stl and reading it. The solids are translated directly to AEDT format. @@ -1070,10 +1071,13 @@ def import_nastran( Whether to import the model in HFSS or only generate the stl file. preview : bool, optional Whether to preview the model in pyvista or skip it. + merge_angle : float, optional + Angle in radians for which faces will be considered planar. Default is ``1e-3``. Returns ------- - List of :class:`ansys.aedt.core.modeler.Object3d.Object3d` + List of :class:`ansys.aedt.core.modeler.Object3d.Object3d`, dict + New object created and nastran dictionary. """ autosave = ( True if self._app.odesktop.GetRegistryInt("Desktop/Settings/ProjectOptions/DoAutoSave") == 1 else False @@ -1089,7 +1093,7 @@ def import_nastran( preview=preview, ) if save_only_stl: - return output_stls + return output_stls, nas_to_dict self._app.desktop_class.close_windows() self.logger.info("Importing STL in 3D Modeler") @@ -1100,6 +1104,7 @@ def import_nastran( create_lightweigth_part=import_as_light_weight, healing=False, merge_planar_faces=enable_stl_merge, + merge_angle=merge_angle, ) self.logger.info(f"Model {os.path.split(output_stl)[-1]} imported") self._app.save_project() @@ -1202,7 +1207,7 @@ def import_nastran( self._app.oproject.SetActiveDesign(self._app.design_name) self._app.odesktop.EnableAutoSave(autosave) self.logger.info_timer("Nastran model correctly imported.") - return new_objects + return new_objects, nas_to_dict @pyaedt_function_handler() def import_from_openstreet_map( diff --git a/src/ansys/aedt/core/modules/solve_setup.py b/src/ansys/aedt/core/modules/solve_setup.py index 71b5c09638c..88296a9b5eb 100644 --- a/src/ansys/aedt/core/modules/solve_setup.py +++ b/src/ansys/aedt/core/modules/solve_setup.py @@ -80,6 +80,17 @@ def default_intrinsics(self): dict Dictionary which keys are typically Freq, Phase or Time.""" intr = {} + if "HFSS 3D Layout" in self._app.design_type: # pragma no cover + try: + intr["Freq"] = ( + self._app.modeler.edb.setups[self.name] + .adaptive_settings.adaptive_frequency_data_list[0] + .adaptive_frequency + ) + intr["Phase"] = "0deg" + return intr + except Exception: + settings.logger.debug("Failed to retrieve adaptive frequency.") for i in self._app.design_solutions.intrinsics: if i == "Freq" and "Frequency" in self.props: intr[i] = self.props["Frequency"] diff --git a/src/ansys/aedt/core/visualization/advanced/misc.py b/src/ansys/aedt/core/visualization/advanced/misc.py index 56be25d2b4b..7eebeab484b 100644 --- a/src/ansys/aedt/core/visualization/advanced/misc.py +++ b/src/ansys/aedt/core/visualization/advanced/misc.py @@ -293,7 +293,7 @@ def _parse_nastran(file_path): def parse_lines(input_lines, input_pid=0, in_assembly="Main"): if in_assembly not in nas_to_dict["Assemblies"]: - nas_to_dict["Assemblies"][in_assembly] = {"Triangles": {}, "Solids": {}, "Lines": {}} + nas_to_dict["Assemblies"][in_assembly] = {"Triangles": {}, "Solids": {}, "Lines": {}, "Shells": {}} def get_point(ll, start, length): n = ll[start : start + length].strip() @@ -301,11 +301,15 @@ def get_point(ll, start, length): n = n[0] + n[1:].replace("-", "e-") return n + line_header = "" for lk in range(len(input_lines)): line = input_lines[lk] line_type = line[:8].strip() obj_type = "Triangles" - if line.startswith("$") or line.startswith("*"): + if line.startswith("$"): + line_header = line[1:] + continue + elif line.startswith("*"): continue elif line_type in ["GRID", "GRID*"]: num_points = 3 @@ -331,6 +335,14 @@ def get_point(ll, start, length): elif line_type in ["CPYRA", "CPYRAM", "CPYRA*", "CPYRAM*"]: num_points = 5 obj_type = "Solids" + elif line_type in ["CHEXA", "CHEXA*"]: + num_points = 8 + obj_type = "Solids" + elif line_type in ["PSHELL", "PSHELL*"]: + num_points = 1 + obj_type = "Shells" + elif line_type in ["MPC", "MPC*"]: + num_points = 16 else: continue @@ -343,7 +355,9 @@ def get_point(ll, start, length): pp = 0 start_pointer = start_pointer + word_length object_id = line[start_pointer : start_pointer + word_length] - if obj_type != "Grid": + if obj_type == "Shells": + nas_to_dict["Assemblies"][in_assembly][obj_type][grid_id] = [] + elif obj_type != "Grid": object_id = int(object_id) if object_id not in nas_to_dict["Assemblies"][in_assembly][obj_type]: nas_to_dict["Assemblies"][in_assembly][obj_type][object_id] = [] @@ -382,6 +396,57 @@ def get_point(ll, start, length): nas_to_dict["PointsId"][int(points[3])], ] nas_to_dict["Assemblies"][in_assembly]["Triangles"][object_id].append(tri) + elif line_type in ["PSHELL", "PSHELL*"]: + nas_to_dict["Assemblies"][in_assembly]["Shells"][grid_id] = [str(object_id.strip()), points[0]] + elif line_type in ["MPC", "MPC*"]: + if ( + line_header + and f'Port_{line_header.replace(",", "_")}_{object_id}' + not in nas_to_dict["Assemblies"][in_assembly]["Triangles"] + ): + name = f'Port_{line_header.replace(",", "_")}_{object_id}' + else: + name = f"Port_{object_id}" + tri = [ + nas_to_dict["PointsId"][int(points[2])], + nas_to_dict["PointsId"][int(points[7])], + nas_to_dict["PointsId"][int(points[10])], + ] + nas_to_dict["Assemblies"][in_assembly]["Triangles"][name] = [tri] + tri = [ + nas_to_dict["PointsId"][int(points[2])], + nas_to_dict["PointsId"][int(points[7])], + nas_to_dict["PointsId"][int(points[15])], + ] + nas_to_dict["Assemblies"][in_assembly]["Triangles"][name].append(tri) + tri = [ + nas_to_dict["PointsId"][int(points[2])], + nas_to_dict["PointsId"][int(points[10])], + nas_to_dict["PointsId"][int(points[15])], + ] + nas_to_dict["Assemblies"][in_assembly]["Triangles"][name].append(tri) + elif line_type in ["CHEXA", "CHEXA*"]: + + def add_hexa_tria(p1, p2, p3, hexa_obj): + tri = [ + nas_to_dict["PointsId"][int(points[p1])], + nas_to_dict["PointsId"][int(points[p2])], + nas_to_dict["PointsId"][int(points[p3])], + ] + nas_to_dict["Assemblies"][in_assembly]["Solids"][hexa_obj].append(tri) + + add_hexa_tria(0, 1, 2, object_id) + add_hexa_tria(0, 2, 3, object_id) + add_hexa_tria(0, 1, 4, object_id) + add_hexa_tria(1, 4, 5, object_id) + add_hexa_tria(1, 2, 6, object_id) + add_hexa_tria(1, 6, 5, object_id) + add_hexa_tria(4, 7, 6, object_id) + add_hexa_tria(4, 6, 5, object_id) + add_hexa_tria(0, 3, 7, object_id) + add_hexa_tria(0, 7, 4, object_id) + add_hexa_tria(3, 2, 7, object_id) + add_hexa_tria(2, 7, 6, object_id) else: from itertools import combinations @@ -605,6 +670,8 @@ def preview_pyvista(dict_in): k += 1 for triangles in assembly["Triangles"].values(): + if not triangles: + continue tri_out = triangles fin = [[3] + list(i) for i in tri_out] if not color_by_assembly: @@ -614,6 +681,8 @@ def preview_pyvista(dict_in): pl.add_mesh(pv.PolyData(p_out, faces=fin), color=colors[-1], **dargs) for triangles in assembly["Solids"].values(): + if not triangles: + continue import pandas as pd df = pd.Series(triangles) diff --git a/tests/system/general/example_models/T20/test_cad_2.nas b/tests/system/general/example_models/T20/test_cad_2.nas index 9d8c73c690e..7b89dde287d 100644 --- a/tests/system/general/example_models/T20/test_cad_2.nas +++ b/tests/system/general/example_models/T20/test_cad_2.nas @@ -21,7 +21,23 @@ GRID* 8 819.99916 484.24676* * 1079.1764 GRID* 9 821.99916 484.24676* * 1079.1764 -CTRIA3* 75986 19 4 5 +GRID* 90 3765.52592783397558.001498934318*00000AB +*00000AB541.722189090299 +GRID* 1007203 3768.69988565771557.793636519251*00007FF +*00007FF 541.81042145073 +GRID* 1007202 3768.47407216604554.871992937834*00007FD +*00007FD543.050585572983 +GRID* 1007190 3765.30011434228555.079855352895*00007F9 +*00007F9542.962353212553 +GRID* 1007050 3765.52592894026557.591009507438*00007C7 +*00007C7540.755134147607 +GRID* 1007009 3768.69988566721 557.38314620061*00007AD +*00007AD540.843366890436 +GRID* 1007010 3768.47407145353554.460132692972*00007AF +*00007AF 542.08029593078 +GRID* 1007012 3765.3001147491 554.6679176985*00007B1 +*00007B1541.991878140273 +CTRIA3* 75986 24217 4 5 * 6 CQUAD4* 75987 19 4 5 * 6 7 @@ -30,6 +46,23 @@ CTETRA* 75988 19 4 5 CPYRAM* 75989 19 9 5 * 6 7 8 CROD* 7599 19 9 8 +CHEXA* 55 23376 90 1007203*0000ACB +*0000ACB 1007202 1007190 1007050 1007009*0000ACC +*0000ACC 1007010 1007012 *0000ACD +*0000ACD +$33672406-01_27_CROSSMEMBER REAR SEAT HIGH 90 BEV_PartBody +PSHELL* 24217 280500 1.2 280500*00014C8 +*00014C8 1. 280500 *00014C9 +*00014C9 *00014CA +*00014CA +$Joint +$Q3D_Joint_182096_1_4.5mm +MPC* 1 9 1 1.*00014CE +*00014CE 5 1 1. *00014CF +*00014CF 6 1 1.*00014D0 +*00014D0 7 1 1. *00014D1 +*00014D1 4 1 1.*00014D2 +*00014D2 ENDDATA $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py index 15e54a4ecb1..30ef07f19e0 100644 --- a/tests/system/general/test_20_HFSS.py +++ b/tests/system/general/test_20_HFSS.py @@ -1443,9 +1443,9 @@ def test_59_test_nastran(self): example_project = os.path.join(TESTS_GENERAL_PATH, "example_models", test_subfolder, "test_cad.nas") example_project2 = os.path.join(TESTS_GENERAL_PATH, "example_models", test_subfolder, "test_cad_2.nas") - cads = self.aedtapp.modeler.import_nastran(example_project, lines_thickness=0.1) + cads, _ = self.aedtapp.modeler.import_nastran(example_project, lines_thickness=0.1) assert len(cads) > 0 - stl = self.aedtapp.modeler.import_nastran(example_project, decimation=0.3, preview=True, save_only_stl=True) + stl, _ = self.aedtapp.modeler.import_nastran(example_project, decimation=0.3, preview=True, save_only_stl=True) assert os.path.exists(stl[0]) assert self.aedtapp.modeler.import_nastran(example_project2, decimation=0.1, preview=True, save_only_stl=True) assert self.aedtapp.modeler.import_nastran(example_project2, decimation=0.5) diff --git a/tests/system/solvers/test_45_workflows.py b/tests/system/solvers/test_45_workflows.py index 6c1115d3e4f..df9ce3c1d34 100644 --- a/tests/system/solvers/test_45_workflows.py +++ b/tests/system/solvers/test_45_workflows.py @@ -158,7 +158,7 @@ def test_05_project_import_nastran(self, add_app, local_scratch): ) assert main({"is_test": True, "file_path": file_path, "lightweight": True, "decimate": 0.0, "planar": True}) - assert len(aedtapp.modeler.object_list) == 3 + assert len(aedtapp.modeler.object_list) == 4 aedtapp.close_project(aedtapp.project_name) def test_06_project_import_stl(self, add_app, local_scratch): From e580d7a796e1400452ea307565712e7199746f59 Mon Sep 17 00:00:00 2001 From: Massimo Capodiferro <77293250+maxcapodi78@users.noreply.github.com> Date: Wed, 6 Nov 2024 18:13:50 +0100 Subject: [PATCH 13/13] FIX: Improve 3d layout plots (#5355) Co-authored-by: maxcapodi78 Co-authored-by: Samuel Lopez <85613111+Samuelopez-ansys@users.noreply.github.com> --- .../core/visualization/post/post_common_3d.py | 151 +++++++++++++++--- .../general/test_41_3dlayout_modeler.py | 11 ++ 2 files changed, 141 insertions(+), 21 deletions(-) diff --git a/src/ansys/aedt/core/visualization/post/post_common_3d.py b/src/ansys/aedt/core/visualization/post/post_common_3d.py index 736d76d3b03..398a1fce4cf 100644 --- a/src/ansys/aedt/core/visualization/post/post_common_3d.py +++ b/src/ansys/aedt/core/visualization/post/post_common_3d.py @@ -207,6 +207,7 @@ def _get_intrinsic(self, setup): @pyaedt_function_handler(list_objs="assignment") def _get_volume_objects(self, assignment): + obj_list = [] if self._app.solution_type not in ["HFSS3DLayout", "HFSS 3D Layout Design"]: obj_list = [] editor = self._app._odesign.SetActiveEditor("3D Modeler") @@ -1340,36 +1341,53 @@ def create_fieldplot_line_traces( ) @pyaedt_function_handler() - def _get_3dl_layers_nets(self, layers, nets, setup): + def _get_all_3dl_layers_nets(self, setup): + try: + get_ids = self._odesign.GetGeometryIdsForAllNetLayerCombinations(setup) + except: # pragma no cover + get_ids = [] + k = 0 + get_ids_dict = {} + key = "" + list_to_add = [] + while k < len(get_ids): + if get_ids[k].startswith("PlotGeomInfo"): + if key: + get_ids_dict[key] = list_to_add + key = get_ids[k].replace("PlotGeomInfo for ", "").replace(" (net/layer combination):", "") + list_to_add = [] + else: + try: + list_to_add.append(int(get_ids[k])) + except ValueError: + pass + k = k + 1 + return get_ids_dict + + @pyaedt_function_handler() + def _get_3dl_layers_nets(self, layers, nets, setup, include_dielectrics): lst_faces = [] new_layers = [] + ids_dict = self._get_all_3dl_layers_nets(setup) if not layers: - new_layers.extend([f"{i}" for i in self._app.modeler.edb.stackup.dielectric_layers.keys()]) + if include_dielectrics: + new_layers.extend([f"{i}" for i in self._app.modeler.edb.stackup.dielectric_layers.keys()]) for layer in self._app.modeler.edb.stackup.signal_layers.keys(): if not nets: nets = list(self._app.modeler.edb.nets.nets.keys()) for el in nets: - try: - get_ids = self._odesign.GetGeometryIdsForNetLayerCombination(el, layer, setup) - except: - get_ids = [] - if isinstance(get_ids, (tuple, list)) and len(get_ids) > 2: - lst_faces.extend([int(i) for i in get_ids[2:]]) - + if f"{el}/{layer}" in ids_dict: + lst_faces.extend(ids_dict[f"{el}/{layer}"]) else: for layer in layers: - if layer in self._app.modeler.edb.stackup.dielectric_layers: + if layer in self._app.modeler.edb.stackup.dielectric_layers and include_dielectrics: new_layers.append(f"{layer}") elif layer in self._app.modeler.edb.stackup.signal_layers: if not nets: nets = list(self._app.modeler.edb.nets.nets.keys()) for el in nets: - try: - get_ids = self._odesign.GetGeometryIdsForNetLayerCombination(el, layer, setup) - except: - get_ids = [] - if isinstance(get_ids, (tuple, list)) and len(get_ids) > 2: - lst_faces.extend([int(i) for i in get_ids[2:]]) + if f"{el}/{layer}" in ids_dict: + lst_faces.extend(ids_dict[f"{el}/{layer}"]) return lst_faces, new_layers @pyaedt_function_handler() @@ -1395,9 +1413,9 @@ def create_fieldplot_layers( ): # type: (list, str, str, list, bool, dict, str) -> FieldPlot """Create a field plot of stacked layer plot. - This plot is valid from AEDT 2023 R2 and later in HFSS 3D Layout. + This plot is valid from AEDT 2023 R2 and later in HFSS 3D Layout. Nets can be used as a filter. + Dielectrics will be included into the plot. It works when a layout components in 3d modeler is used. - In order to plot on signal layers use the method ``create_fieldplot_layers_nets``. Parameters ---------- @@ -1414,6 +1432,9 @@ def create_fieldplot_layers( use in the export or ``LastAdaptive``. nets : list, optional List of nets to filter the field plot. Optional. + plot_on_surface : bool, optional + Whether if the plot has to be on surfaces or inside the objects. + It is applicable only to layout components. Default is ``True``. intrinsics : dict, str, optional Intrinsic variables required to compute the field before the export. These are typically: frequency, time and phase. @@ -1453,7 +1474,7 @@ def create_fieldplot_layers( return self.field_plots[name] if self._app.design_type in ["HFSS 3D Layout Design"]: - lst_faces, new_layers = self._get_3dl_layers_nets(layers, nets, setup) + lst_faces, new_layers = self._get_3dl_layers_nets(layers, nets, setup, include_dielectrics=True) if new_layers: plt = self._create_fieldplot( new_layers, quantity, setup, intrinsics, "ObjList", name, create_plot=False @@ -1484,12 +1505,89 @@ def create_fieldplot_layers( return self._create_fieldplot(dielectrics, quantity, setup, intrinsics, "ObjList", name) return False + @pyaedt_function_handler() + def create_fieldplot_nets( + self, nets, quantity, setup=None, layers=None, plot_on_surface=True, intrinsics=None, name=None + ): + # type: (list, str, str, list, bool, dict, str) -> FieldPlot + """Create a field plot of stacked layer plot based on a net selections. Layers can be used as a filter. + Dielectrics will be excluded from the plot. + This plot is valid from AEDT 2023 R2 and later in HFSS 3D Layout. + It works when a layout components in 3d modeler is used. + + Parameters + ---------- + nets : list, optional + List of nets to filter the field plot. + quantity : str + Name of the quantity to plot. + setup : str, optional + Name of the setup. The default is ``None``, in which case the ``nominal_adaptive`` + setup is used. Make sure to build a setup string in the form of + ``"SetupName : SetupSweep"``, where ``SetupSweep`` is the sweep name to + use in the export or ``LastAdaptive``. + layers : list, optional + List of layers to plot. For example: + ``["Layer1","Layer2"]``. If empty list is provided + all layers are considered. + intrinsics : dict, str, optional + Intrinsic variables required to compute the field before the export. + These are typically: frequency, time and phase. + It can be provided either as a dictionary or as a string. + If it is a dictionary, keys depend on the solution type and can be expressed in lower or camel case as: + + - ``"Freq"`` or ``"Frequency"``. + - ``"Time"``. + - ``"Phase"``. + + If it is a string, it can either be ``"Freq"`` or ``"Time"`` depending on the solution type. + The default is ``None`` in which case the intrinsics value is automatically computed based on the setup. + plot_on_surface : bool, optional + Whether if the plot has to be on surfaces or inside the objects. + It is applicable only to layout components. Default is ``True``. + name : str, optional + Name of the field plot to create. + + Returns + ------- + :class:``ansys.aedt.core.modules.solutions.FieldPlot`` or bool + Plot object. + + References + ---------- + >>> oModule.CreateFieldPlot + """ + intrinsics = self._app._check_intrinsics(intrinsics, setup=setup) + if not setup: + setup = self._app.existing_analysis_sweeps[0] + if nets is None: + nets = [] + if not ( + "APhi" in self.post_solution_type and settings.aedt_version >= "2023.2" + ) and not self._app.design_type in ["HFSS", "HFSS 3D Layout Design"]: + self.logger.error("This method requires AEDT 2023 R2 and Maxwell 3D Transient APhi Formulation.") + return False + if name and name in list(self.field_plots.keys()): + self.logger.info(f"Plot {name} exists. returning the object.") + return self.field_plots[name] + + if self._app.design_type in ["HFSS 3D Layout Design"]: + lst_faces, new_layers = self._get_3dl_layers_nets(layers, nets, setup, include_dielectrics=False) + return self._create_fieldplot(lst_faces, quantity, setup, intrinsics, "FacesList", name) + else: + _, new_layers = self._get_3d_layers_nets(layers, nets) + if plot_on_surface: + plot_type = "LayerNetsExtFace" + else: + plot_type = "LayerNets" + return self._create_fieldplot(new_layers, quantity, setup, intrinsics, plot_type, name) + @pyaedt_function_handler(quantity_name="quantity", setup_name="setup") def create_fieldplot_layers_nets( self, layers_nets, quantity, setup=None, intrinsics=None, plot_on_surface=True, plot_name=None ): # type: (list, str, str, dict, bool, str) -> FieldPlot - """Create a field plot of stacked layer plot. + """Create a field plot of stacked layer plot on specified matrix of layers and nets. This plot is valid from AEDT 2023 R2 and later in HFSS 3D Layout and any modeler where a layout component is used. @@ -1520,7 +1618,8 @@ def create_fieldplot_layers_nets( If it is a string, it can either be ``"Freq"`` or ``"Time"`` depending on the solution type. The default is ``None`` in which case the intrinsics value is automatically computed based on the setup. plot_on_surface : bool, optional - Whether the plot is to be on the surface or volume of traces. + Whether if the plot has to be on surfaces or inside the objects. + It is applicable only to layout components. Default is ``True``. plot_name : str, optional Name of the field plot to create. @@ -1548,7 +1647,17 @@ def create_fieldplot_layers_nets( if not setup: setup = self._app.existing_analysis_sweeps[0] lst = [] + if len(layers_nets) == 0: + + dicts_in = self._get_all_3dl_layers_nets(setup) + for _, v in dicts_in.items(): + lst.extend(v) for layer in layers_nets: + if len(layer) == 1: + dicts_in = self._get_all_3dl_layers_nets(setup) + for v, i in dicts_in.items(): + if v.split("/")[1] == layer[0] or v.split("/")[0] == layer[0]: + lst.extend(i) for el in layer[1:]: el = "" if el == "no-net" else el try: diff --git a/tests/system/general/test_41_3dlayout_modeler.py b/tests/system/general/test_41_3dlayout_modeler.py index e4ec1129816..d05fafd4e00 100644 --- a/tests/system/general/test_41_3dlayout_modeler.py +++ b/tests/system/general/test_41_3dlayout_modeler.py @@ -837,6 +837,17 @@ def test_42_post_processing_3d_layout(self, add_app): assert pl1 assert pl1.export_image_from_aedtplt(tempfile.gettempdir()) + pl2 = test.post.create_fieldplot_nets( + ["V3P3_S5"], + "Mag_E", + layers=["LYR_1"], + intrinsics={"Freq": "1GHz"}, + name="Test_Layers2", + ) + + assert pl2 + assert pl2.export_image_from_aedtplt(tempfile.gettempdir()) + self.aedtapp.close_project(test.project_name) @pytest.mark.skipif(is_linux, reason="Bug on linux")