From 0faf92870162b91571e0e4b3260271187f224e75 Mon Sep 17 00:00:00 2001 From: Hui Zhou Date: Tue, 12 Nov 2024 16:23:12 +0100 Subject: [PATCH] DOCS: configure layout doc (#5409) Co-authored-by: ring630 <@gmail.com> --- .../project/configure_edb.rst | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst b/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst index d8317179049..077094fa6e2 100644 --- a/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst +++ b/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst @@ -18,10 +18,6 @@ integrity as well as power integrity analysis. :width: 800 :alt: Principle of working of Layout UI -Please refer to EDB Configuration `User Guide`_ for details - -.. _User Guide: https://edb.docs.pyansys.com/version/stable/examples/use_configuration/index.html - -------------------------------------------------------------------------- A brief description of which options are defined in the configuration file -------------------------------------------------------------------------- @@ -83,4 +79,20 @@ Configure design in siwave project 3, Click ``Select and Apply Configuration`` and browse to your configuration files. -4, In the second pop-up window. Specify where to save the new project. \ No newline at end of file +4, In the second pop-up window. Specify where to save the new project. + +~~~~~~~~~ +Resources +~~~~~~~~~ + +1, EDB Configuration `User Guide`_ for details + +.. _User Guide: https://edb.docs.pyansys.com/version/stable/examples/use_configuration/index.html + +2, `Demo video`_ + +.. _Demo video: https://www.linkedin.com/posts/electronics-simulation_accelerate-hfss-configuration-via-ansys-pyedb-activity-7252325488168177666-ypbN/?utm_source=share&utm_medium=member_desktop + +3, `Webinar Automating Signal and Power Integrity workflow with PyAEDT`_ + +.. _Webinar Automating Signal and Power Integrity workflow with PyAEDT: https://www.ansys.com/webinars/automating-signal-power-integrity-workflow-pyaedt?campaignID=7013g000000Y8uOAAS&utm_campaign=product&utm_content=digital_electronics_oktopost-Ansys+Electronics_oktopost-%25campaign_n&utm_medium=social-organic&utm_source=LinkedIn \ No newline at end of file