diff --git a/.github/workflows/NanoPi-Build.yml b/.github/workflows/NanoPi-Build.yml index bf29c39..bf88c11 100644 --- a/.github/workflows/NanoPi-Build.yml +++ b/.github/workflows/NanoPi-Build.yml @@ -49,7 +49,7 @@ jobs: needs: init strategy: matrix: - nanopi_model: [R2S, R4S] + nanopi_model: [R2S, R2C, R4S] runs-on: ubuntu-20.04 if: github.event.repository.owner.id == github.event.sender.id diff --git a/README.md b/README.md index bb191ec..2e7b3f2 100644 --- a/README.md +++ b/README.md @@ -38,6 +38,8 @@ Automated builds of OpenWrt for FriendlyARM NanoPi R2S & R4S boards ## Changelog +#### 2022-04-12 +- Add NanoPi R2C in uboot and branch 21.02 #### 2022-03-28 - Add branch 22.03 #### 2022-02-12 diff --git a/openwrt-21.02/steps/03_patch_openwrt.sh b/openwrt-21.02/steps/03_patch_openwrt.sh index 3f3d086..8064cde 100755 --- a/openwrt-21.02/steps/03_patch_openwrt.sh +++ b/openwrt-21.02/steps/03_patch_openwrt.sh @@ -45,6 +45,20 @@ endef TARGET_DEVICES += friendlyarm_nanopi-r4s EOT +cat <> target/linux/rockchip/image/armv8.mk + +define Device/friendlyarm_nanopi-r2c + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R2C + SOC := rk3328 + UBOOT_DEVICE_NAME := nanopi-r2c-rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-usb-net-rtl8152 +endef +TARGET_DEVICES += friendlyarm_nanopi-r2c +EOT + + # r8152 driver from friendlywrt for kernel 5.4 # add extra patch to update r8152 driver to v.1.11.11 # note : driver 2.13 and 2.14 seem unstable from this thread diff --git a/openwrt-21.02/steps/06-create_config_from_seed.sh b/openwrt-21.02/steps/06-create_config_from_seed.sh index 2e1e108..14e4bc4 100755 --- a/openwrt-21.02/steps/06-create_config_from_seed.sh +++ b/openwrt-21.02/steps/06-create_config_from_seed.sh @@ -20,4 +20,10 @@ if [[ "$1" == "R2S" ]]; then sed -i 's/cortex-a72.cortex-a53/cortex-a53/' .config fi +if [[ "$1" == "R2C" ]]; then + echo "NanoPi R2C model, post patching .config" + sed -i 's/nanopi-r4s/nanopi-r2c/' .config + sed -i 's/cortex-a72.cortex-a53/cortex-a53/' .config +fi + make defconfig diff --git a/package/uboot-rockchip/Makefile b/package/uboot-rockchip/Makefile index b886ef0..486bc3c 100644 --- a/package/uboot-rockchip/Makefile +++ b/package/uboot-rockchip/Makefile @@ -24,6 +24,17 @@ endef # RK3328 boards +define U-Boot/nanopi-r2c-rk3328 + BUILD_SUBTARGET:=armv8 + NAME:=NanoPi R2C + BUILD_DEVICES:= \ + friendlyarm_nanopi-r2c + DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3328_bl31.elf + OF_PLATDATA:=$(1) +endef + define U-Boot/nanopi-r2s-rk3328 BUILD_SUBTARGET:=armv8 NAME:=NanoPi R2S @@ -72,6 +83,7 @@ UBOOT_TARGETS := \ nanopi-r4s-rk3399 \ rock-pi-4-rk3399 \ rockpro64-rk3399 \ + nanopi-r2c-rk3328 \ nanopi-r2s-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/uboot-rockchip/patches/201-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/uboot-rockchip/patches/201-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch new file mode 100644 index 0000000..2e3dc17 --- /dev/null +++ b/package/uboot-rockchip/patches/201-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -0,0 +1,182 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index d3e89ca3ba..d5f64ac432 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ + + dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb \ ++ rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2s.dtb \ + rk3328-orangepi-r1-plus.dtb \ + rk3328-roc-cc.dtb \ +diff --git a/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi +new file mode 100644 +index 0000000000..c2e86d0f0e +--- /dev/null ++++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ * (C) Copyright 2021 Tianling Shen ++ */ ++ ++#include "rk3328-nanopi-r2s-u-boot.dtsi" +diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts b/arch/arm/dts/rk3328-nanopi-r2c.dts +new file mode 100644 +index 0000000000..adf91a0306 +--- /dev/null ++++ b/arch/arm/dts/rk3328-nanopi-r2c.dts +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2021 Tianling Shen ++ */ ++ ++/dts-v1/; ++ ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R2C"; ++ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8521s>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8521s: ethernet-phy@3 { ++ compatible = "ethernet-phy-id0000.011a", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&lan_led { ++ label = "nanopi-r2c:green:lan"; ++}; ++ ++&sys_led { ++ label = "nanopi-r2c:red:sys"; ++}; ++ ++&wan_led { ++ label = "nanopi-r2c:green:wan"; ++}; +diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig +new file mode 100644 +index 0000000000..7bc7a3274f +--- /dev/null ++++ b/configs/nanopi-r2c-rk3328_defconfig +@@ -0,0 +1,98 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_TPL_LIBCOMMON_SUPPORT=y ++CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEBUG_UART=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_TPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSINFO=y ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h b/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h new file mode 100644 index 0000000..0919e4e --- /dev/null +++ b/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h @@ -0,0 +1,23 @@ +/* + * DO NOT MODIFY + * + * Declares externs for all device/uclass instances. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include + +/* driver declarations - these allow DM_DRIVER_GET() to be used */ +extern U_BOOT_DRIVER(rockchip_rk3328_cru); +extern U_BOOT_DRIVER(rockchip_rk3328_dmc); +extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); +extern U_BOOT_DRIVER(ns16550_serial); +extern U_BOOT_DRIVER(rockchip_rk3328_grf); + +/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ +extern UCLASS_DRIVER(clk); +extern UCLASS_DRIVER(mmc); +extern UCLASS_DRIVER(ram); +extern UCLASS_DRIVER(serial); +extern UCLASS_DRIVER(syscon); diff --git a/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c b/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c new file mode 100644 index 0000000..e5b330c --- /dev/null +++ b/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c @@ -0,0 +1,155 @@ +/* + * DO NOT MODIFY + * + * Declares the U_BOOT_DRIVER() records and platform data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +/* Allow use of U_BOOT_DRVINFO() in this file */ +#define DT_PLAT_C + +#include +#include +#include + +/* + * driver_info declarations, ordered by 'struct driver_info' linker_list idx: + * + * idx driver_info driver + * --- -------------------- -------------------- + * 0: clock_controller_at_ff440000 rockchip_rk3328_cru + * 1: dmc rockchip_rk3328_dmc + * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc + * 3: serial_at_ff130000 ns16550_serial + * 4: syscon_at_ff100000 rockchip_rk3328_grf + * --- -------------------- -------------------- + */ + +/* + * Node /clock-controller@ff440000 index 0 + * driver rockchip_rk3328_cru parent None + */ +static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { + .reg = {0xff440000, 0x1000}, + .rockchip_grf = 0x3a, +}; +U_BOOT_DRVINFO(clock_controller_at_ff440000) = { + .name = "rockchip_rk3328_cru", + .plat = &dtv_clock_controller_at_ff440000, + .plat_size = sizeof(dtv_clock_controller_at_ff440000), + .parent_idx = -1, +}; + +/* + * Node /dmc index 1 + * driver rockchip_rk3328_dmc parent None + */ +static struct dtd_rockchip_rk3328_dmc dtv_dmc = { + .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, + 0xff720000, 0x1000, 0xff798000, 0x1000}, + .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, + 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, + 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, + 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, + 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, + 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, + 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, + 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, + 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, + 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, + 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, + 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, + 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, + 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x79, 0x9}, +}; +U_BOOT_DRVINFO(dmc) = { + .name = "rockchip_rk3328_dmc", + .plat = &dtv_dmc, + .plat_size = sizeof(dtv_dmc), + .parent_idx = -1, +}; + +/* + * Node /mmc@ff500000 index 2 + * driver rockchip_rk3288_dw_mshc parent None + */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_sd_highspeed = true, + .clocks = { + {0, {317}}, + {0, {33}}, + {0, {74}}, + {0, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .sd_uhs_sdr104 = true, + .sd_uhs_sdr12 = true, + .sd_uhs_sdr25 = true, + .sd_uhs_sdr50 = true, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x4b, + .vqmmc_supply = 0x1e, +}; +U_BOOT_DRVINFO(mmc_at_ff500000) = { + .name = "rockchip_rk3288_dw_mshc", + .plat = &dtv_mmc_at_ff500000, + .plat_size = sizeof(dtv_mmc_at_ff500000), + .parent_idx = -1, +}; + +/* + * Node /serial@ff130000 index 3 + * driver ns16550_serial parent None + */ +static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {0, {40}}, + {0, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x26, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DRVINFO(serial_at_ff130000) = { + .name = "ns16550_serial", + .plat = &dtv_serial_at_ff130000, + .plat_size = sizeof(dtv_serial_at_ff130000), + .parent_idx = -1, +}; + +/* + * Node /syscon@ff100000 index 4 + * driver rockchip_rk3328_grf parent None + */ +static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DRVINFO(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .plat = &dtv_syscon_at_ff100000, + .plat_size = sizeof(dtv_syscon_at_ff100000), + .parent_idx = -1, +}; + diff --git a/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h b/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h new file mode 100644 index 0000000..b1ff08a --- /dev/null +++ b/package/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h @@ -0,0 +1,51 @@ +/* + * DO NOT MODIFY + * + * Defines the structs used to hold devicetree data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include +struct dtd_ns16550_serial { + fdt32_t clock_frequency; + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt64_t reg[2]; + fdt32_t reg_io_width; + fdt32_t reg_shift; +}; +struct dtd_rockchip_rk3288_dw_mshc { + fdt32_t bus_width; + bool cap_sd_highspeed; + struct phandle_1_arg clocks[4]; + bool disable_wp; + fdt32_t fifo_depth; + fdt32_t interrupts[3]; + fdt32_t max_frequency; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; + bool sd_uhs_sdr104; + bool sd_uhs_sdr12; + bool sd_uhs_sdr25; + bool sd_uhs_sdr50; + bool u_boot_spl_fifo_mode; + fdt32_t vmmc_supply; + fdt32_t vqmmc_supply; +}; +struct dtd_rockchip_rk3328_cru { + fdt64_t reg[2]; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_dmc { + fdt64_t reg[12]; + fdt32_t rockchip_sdram_params[196]; +}; +struct dtd_rockchip_rk3328_grf { + fdt64_t reg[2]; +};