diff --git a/arch/arm64/boot/dts/arrow/Makefile b/arch/arm64/boot/dts/arrow/Makefile new file mode 100644 index 0000000000000..6270cbd284c05 --- /dev/null +++ b/arch/arm64/boot/dts/arrow/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex5_axe5_eagle.dtb +dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb +dtb-$(CONFIG_ARCH_DM) += socfpga_dm_simics.dtb diff --git a/arch/arm64/boot/dts/arrow/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/arrow/socfpga_agilex5.dtsi new file mode 100644 index 0000000000000..d4353610ba32f --- /dev/null +++ b/arch/arm64/boot/dts/arrow/socfpga_agilex5.dtsi @@ -0,0 +1,1166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +/ { + compatible = "intel,socfpga-agilex"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x2000000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x100>; + next-level-cache = <&L2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x200>; + next-level-cache = <&L2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x300>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3>; + }; + + L3: l3-cache { + compatible = "cache"; + }; + + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: interrupt-controller@1d000000 { + compatible = "arm,gic-v3", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells =<2>; + interrupt-controller; + #redistributor-regions = <1>; + label = "GIC"; + status = "okay"; + ranges; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x1d000000 0 0x10000>, + <0x0 0x1d060000 0 0x100000>; + + its: msi-controller@1d040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x1d040000 0x0 0x20000>; + label = "ITS"; + msi-controller; + status = "okay"; + }; + }; + + /* Clock tree 5 main sources*/ + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + usbphy0: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&intc>; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + base_fpga_region { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; + + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10810000 0x3500>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "macirq_tx0", + "macirq_tx1", + "macirq_tx2", + "macirq_tx3", + "macirq_tx4", + "macirq_tx5", + "macirq_tx6", + "macirq_tx7", + "macirq_rx0", + "macirq_rx1", + "macirq_rx2", + "macirq_rx3", + "macirq_rx4", + "macirq_rx5", + "macirq_rx6", + "macirq_rx7"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac0_setup>; + snps,mtl-rx-config = <&mtl_rx_emac0_setup>; + snps,mtl-tx-config = <&mtl_tx_emac0_setup>; + snps,pbl = <32>; + snps,pblx8; + snps,multi-irq-en; + snps,tso; + snps,rx-vlan-offload; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + altr,smtg-hub; + iommus = <&smmu 1>; + + status = "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac0_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac0_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-queues-with-coe = <2>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10820000 0x3500>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "macirq_tx0", + "macirq_tx1", + "macirq_tx2", + "macirq_tx3", + "macirq_tx4", + "macirq_tx5", + "macirq_tx6", + "macirq_tx7", + "macirq_rx0", + "macirq_rx1", + "macirq_rx2", + "macirq_rx3", + "macirq_rx4", + "macirq_rx5", + "macirq_rx6", + "macirq_rx7"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac1_setup>; + snps,mtl-rx-config = <&mtl_rx_emac1_setup>; + snps,mtl-tx-config = <&mtl_tx_emac1_setup>; + snps,pbl = <32>; + snps,pblx8; + snps,multi-irq-en; + snps,tso; + snps,rx-vlan-offload; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + altr,smtg-hub; + iommus = <&smmu 2>; + + status = "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac1_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac1_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-queues-with-coe = <2>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10830000 0x3500>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "macirq_tx0", + "macirq_tx1", + "macirq_tx2", + "macirq_tx3", + "macirq_tx4", + "macirq_tx5", + "macirq_tx6", + "macirq_tx7", + "macirq_rx0", + "macirq_rx1", + "macirq_rx2", + "macirq_rx3", + "macirq_rx4", + "macirq_rx5", + "macirq_rx6", + "macirq_rx7"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac2_setup>; + snps,mtl-rx-config = <&mtl_rx_emac2_setup>; + snps,mtl-tx-config = <&mtl_tx_emac2_setup>; + snps,pbl = <32>; + snps,pblx8; + snps,multi-irq-en; + snps,tso; + snps,rx-vlan-offload; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + altr,smtg-hub; + iommus = <&smmu 3>; + + status = "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac2_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac2_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-queues-with-coe = <2>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + + i2c0: i2c@10c02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02800 0x100>; + interrupts = ; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@10c02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02900 0x100>; + interrupts = ; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@10c02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02a00 0x100>; + interrupts = ; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@10c02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02b00 0x100>; + interrupts = ; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@10c02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02c00 0x100>; + interrupts = ; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i3c0: i3c@10da0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da0000 0x1000>; + interrupts = ; + resets = <&rst I3C0_RESET>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + i3c1: i3c@10da1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da1000 0x1000>; + interrupts = ; + resets = <&rst I3C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + gpio0: gpio@10c03200 { + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03200 0x100>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + gpio1: gpio@10C03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x10C03300 0x100>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + mmc: mmc0@10808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,agilex5-sd4hc", "cdns,sd4hc"; + reg = <0x10808000 0x1000>; + interrupts = ; + fifo-depth = <0x800>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMCLK>; + clock-names = "biu", "ciu"; + iommus = <&smmu 5>; + status = "disabled"; + }; + + nand: nand-controller@10b80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cdns,hp-nfc"; + reg = <0x10b80000 0x10000>, + <0x10840000 0x1000>; + reg-names = "reg", "sdma"; + interrupts = ; + clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; + clock-names = "nf_clk"; + cdns,board-delay-ps = <4830>; + iommus = <&smmu 4>; + status = "disabled"; + }; + + ocram: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0x40000>; + }; + + dmac0: dma-controller@10DB0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x10DB0000 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + snps,dma-40-bit-mask; + iommus = <&smmu 8>; + status = "okay"; + }; + + dmac1: dma-controller@10DC0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x10DC0000 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + snps,dma-40-bit-mask; + iommus = <&smmu 9>; + status = "okay"; + }; + + rst: rstmgr@10d11000 { + #reset-cells = <1>; + compatible = "altr,stratix10-rst-mgr"; + reg = <0x10d11000 0x100>; + }; + + smmu: iommu@16000000 { + compatible = "arm,smmu-v3"; + reg = <0x16000000 0x30000>; + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "priq"; + dma-coherent; + #iommu-cells = <1>; + status = "disabled"; + }; + + spi0: spi@10da4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da4000 0x1000>; + interrupts = ; + resets = <&rst SPIM0_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names ="tx", "rx"; + + status = "disabled"; + + flash: m25p128@0 { + status = "okay"; + compatible = "st,m25p80"; + spi-max-frequency = <25000000>; + m25p,fast-read; + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi_flash_part0"; + reg = <0x0 0x100000>; + }; + }; + + }; + + spi1: spi@10da5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da5000 0x1000>; + interrupts = ; + resets = <&rst SPIM1_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0x10d12000 0x500>; + }; + + timer0: timer0@10c03000 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0x10c03000 0x100>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer1: timer1@10c03100 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0x10c03100 0x100>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer2: timer2@10d00000 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0x10d00000 0x100>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer3: timer3@10d00100 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0x10d00100 0x100>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + uart0: serial@10c02000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + uart1: serial@10c02100 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02100 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + usb0: usb@10b00000 { + compatible = "snps,dwc2"; + reg = <0x10b00000 0x40000>; + interrupts = ; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; + clock-names = "otg"; + iommus = <&smmu 6>; + status = "disabled"; + }; + + usb31: usb1@11000000 { + compatible = "intel,agilex5-dwc3"; + reg = <0x11000000 0x100000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "dwc3", "dwc3-ecc"; + iommus = <&smmu 7>; + status = "disabled"; + + usb@11000000{ + compatible = "snps,dwc3"; + reg = <0x11000000 0x100000>; + interrupts = ; + phys = <&usbphy0>, <&usbphy0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + maximum-speed = "super-speed-plus"; + snps,dis_u2_sysphy-quirk; + snps,dma_set_40_bit_mask_quirk; + }; + }; + + eccmgr { + compatible = "altr,socfpga-s10-ecc-manager", + "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = , + , + , + , + , + ; + interrupt-names = "global_sbe", "io96b0" , "io96b1", + "sdm_qspi_sbe", "sdm_qspi_dbe", "seu"; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + ocram-ecc@108cc000 { + compatible = "altr,socfpga-s10-ocram-ecc", + "altr,socfpga-a10-ocram-ecc"; + reg = <0x108cc000 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@108c4000 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0x108c4000 0x100>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + tsn0-rx-ecc@108c0000 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0x108c0000 0x100>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + tsn0-tx-ecc@108c0400 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0x108c0400 0x100>; + interrupts = <5 4>; + }; + + tsn1-rx-ecc@108c0800 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0x108c0800 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + }; + + tsn1-tx-ecc@108c0C00 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0x108c0C00 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + }; + + tsn2-rx-ecc@108c1000 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0x108c1000 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + }; + + tsn2-tx-ecc@108c1400 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0x108c1400 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb31-ram0-ecc@108c4C00 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0x108c4C00 0x100>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb31-ram1-ecc@108c4800 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0x108c4800 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb31-ram2-ecc@108c4400 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0x108c4400 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + }; + + io96b0-ecc { + compatible = "altr,socfpga-io96b-ecc"; + reg = <0x18400000 0x1000>; + interrupts = <95 IRQ_TYPE_EDGE_RISING>; + }; + + io96b1-ecc { + compatible = "altr,socfpga-io96b-ecc"; + reg = <0x18800000 0x1000>; + interrupts = <120 IRQ_TYPE_EDGE_RISING>; + }; + + sdm-qspi-ecc@10a22000 { + compatible = "altr,socfpga-sdm-qspi-ecc"; + reg = <0x10a22000 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + watchdog0: watchdog@10d00200 { + compatible = "snps,dw-wdt"; + reg = <0x10d00200 0x100>; + interrupts = ; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible = "snps,dw-wdt"; + reg = <0x10d00300 0x100>; + interrupts = ; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible = "snps,dw-wdt"; + reg = <0x10d00400 0x100>; + interrupts = ; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible = "snps,dw-wdt"; + reg = <0x10d00500 0x100>; + interrupts = ; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + watchdog4: watchdog@10d00600 { + compatible = "snps,dw-wdt"; + reg = <0x10d00600 0x100>; + interrupts = ; + resets = <&rst WATCHDOG4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + qspi: spi@108d2000 { + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x108d2000 0x100>, + <0x10900000 0x100000>; + interrupts = ; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + + firmware { + svc { + compatible = "intel,agilex5-svc"; + method = "smc"; + memory-region = <&service_reserved>; + iommus = <&smmu 10>; + + fpga_mgr: fpga-mgr { + compatible = "intel,agilex-soc-fpga-mgr"; + }; + + fcs: fcs { + compatible = "intel,agilex-soc-fcs"; + platform = "agilex"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_eagle.dts b/arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_eagle.dts new file mode 100644 index 0000000000000..fecd23e8a11ef --- /dev/null +++ b/arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_eagle.dts @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Arrow Electronics, Inc. + */ +#include "../intel/socfpga_agilex5.dtsi" + + +/ { + model = "SoCFPGA Agilex5 Arrow AXE5-Eagle"; + compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=uart8250,mmio32,0x10c02000,115200n8 \ + root=/dev/ram0 rw initrd=0x10000000 init=/sbin/init \ + ramdisk_size=10000000 earlycon=uart8250,mmio32,0x10c02000,115200n8 \ + panic=-1 nosmp rootfstype=ext3"; + }; + + /*leds { + compatible = "gpio-leds"; + + hps0 { + label = "hps_led0"; + gpios = <&porta 6 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&porta 7 GPIO_ACTIVE_HIGH>; + }; + + fpga0_led_red { + label = "fpga_led0_red"; + gpios = <&led_pio0 2 1>; + }; + + fpga0_led_green { + label = "fpga_led0_green"; + gpios = <&led_pio0 1 1>; + }; + + fpga0_led_blue { + label = "fpga_led0_blue"; + gpios = <&led_pio0 0 1>; + }; + + fpga1_led_red { + label = "fpga_led1_red"; + gpios = <&led_pio1 2 1>; + }; + + fpga1_led_green { + label = "fpga_led1_green"; + gpios = <&led_pio1 1 1>; + }; + + fpga1_led_blue { + label = "fpga_led1_blue"; + gpios = <&led_pio1 0 1>; + }; + + fpga2_led_red { + label = "fpga_led2_red"; + gpios = <&led_pio2 2 1>; + }; + + fpga2_led_green { + label = "fpga_led2_green"; + gpios = <&led_pio2 1 1>; + }; + + fpga2_led_blue { + label = "fpga_led2_blue"; + gpios = <&led_pio2 0 1>; + }; + + fpga3_led_red { + label = "fpga_led3_red"; + gpios = <&led_pio3 2 1>; + }; + + fpga3_led_green { + label = "fpga_led3_green"; + gpios = <&led_pio3 1 1>; + }; + + fpga3_led_blue { + label = "fpga_led3_blue"; + gpios = <&led_pio3 0 1>; + }; + + }; */ + + gpio-keys { + compatible = "gpio-keys"; + + hps_sw0 { + label = "hps_sw0"; + gpios = <&porta 10 0>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; + }; + + hps_sw1 { + label = "hps_sw1"; + gpios = <&porta 1 0>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; + }; + + hps_pb0 { + label = "hps_pb0"; + gpios = <&porta 8 1>; + linux,code = <187>; /* KEY_F17 */ + }; + + hps_pb1 { + label = "hps_pb1"; + gpios = <&porta 9 1>; + linux,code = <188>; /* KEY_F18 */ + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + #address-cells = <0x2>; + #size-cells = <0x2>; + u-boot,dm-pre-reloc; + }; + + dma_clk: dma_clk { + #clock-cells = <0x0>; + compatible = "fixed-clock"; + clock-frequency = <250000000>; + clock-output-names = "dma_clock"; + }; + + hdmi_pll: hdmi_pll { + compatible = "altr,altera_iopll-18.1"; + #clock-cells = <1>; + hdmi_pll_outclk0: hdmi_pll_outclk0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148437500>; + clock-output-names = "hdmi_pll-outclk0"; + }; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3_3: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + soc { + sys_hps_bridges: bridge@20000000 { + compatible = "simple-bus"; + reg = <0x20000000 0x20000000>; + reg-names = "axi_h2f_lw"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00000001 0x08000000 0x28000000 0x00000008>, + <0x00000001 0x08000010 0x28000010 0x00000010>, + <0x00000001 0x08000020 0x28000020 0x00000010>, + <0x00000001 0x08000030 0x28000030 0x00000010>, + <0x00000001 0x08000040 0x28000040 0x00000010>, + <0x00000001 0x08000050 0x28000050 0x00000010>, + <0x00000001 0x08000060 0x28000060 0x00000010>, + <0x00000001 0x10000000 0x30000000 0x00010000>, + <0x00000001 0x10010000 0x30010000 0x00000800>; + + sys_id: sys-id@108000000 { + compatible = "altr,sysid-1.0"; + reg = <0x00000001 0x08000000 0x08>; + }; + + /* pio device tree entry. for additional information see /linux/Documentation/devicetree/bindings/gpio/gpio-altera.txt */ + + button_pio: button-pio@108000010 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x08000010 0x10>; + interrupt-parent = <&intc>; + interrupts = <0 20 4>; + altr,ngpio = <2>; + #gpio-cells = <2>; + gpio-controller; + interrupt-cells = <1>; + interrupt-controller; + altr,interrupt-type = ; + }; + + dipsw_pio: button-pio@108000020 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x08000020 0x10>; + interrupt-parent = <&intc>; + interrupts = <0 18 4>; + altr,ngpio = <2>; + #gpio-cells = <2>; + gpio-controller; + interrupt-cells = <1>; + interrupt-controller; + altr,interrupt-type = ; + }; + + led_pio0: led-pio0@108000030 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x08000030 0x10>; + altr,ngpio = <3>; + #gpio-cells = <2>; + gpio-controller; + }; + + led_pio1: led-pio1@108000040 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x08000040 0x10>; + altr,ngpio = <3>; + #gpio-cells = <2>; + gpio-controller; + }; + + led_pio2: led-pio2@108000050 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x01000050 0x10>; + altr,ngpio = <3>; + #gpio-cells = <2>; + gpio-controller; + }; + + led_pio3: led-pio3@108000060 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x01000060 0x10>; + altr,ngpio = <3>; + #gpio-cells = <2>; + gpio-controller; + }; + + + hdmi_dma: hdmi-dma@110010000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x00000001 0x10010000 0x0800>; + #dma-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 21 4>; + clocks = <&dma_clk 0>; + status = "okay"; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <256>; + adi,source-bus-type = <0>; + adi,destination-bus-width = <64>; + adi,destination-bus-type = <1>; + }; + }; + }; + + + axi_hdmi: axi-hdmi@110000000 { + compatible = "adi,axi-hdmi-tx-1.00.a"; + reg = <0x00000001 0x10000000 0x10000>; + dmas = <&hdmi_dma 0>; + dma-names = "video"; + clocks = <&hdmi_pll 0>; + status = "okay"; + + port { + axi_hdmi_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gmac0 { + status = "disabled"; + phy-mode = "rgmii-id"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + emac0_phy0: ethernet-phy@1 { + reg = <1>; + adi,rx-internal-delay-ps = <2000>; + adi,tx-internal-delay-ps = <2000>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + emac2_phy0: ethernet-phy@1 { + reg = <1>; + adi,rx-internal-delay-ps = <2000>; + adi,tx-internal-delay-ps = <2000>; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tca9544@70 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + status = "okay"; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + adv7511: adv7511@39 { + compatible = "adi,adv7511"; + reg = <0x39>, <0x3f>; + reg-names = "primary", "edid"; + + adi,input-depth = <8>; + adi,input-colorspace = "yuv422"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "right"; + adi,clock-delay = <(0)>; + + avdd-supply = <&vdd>; + dvdd-supply = <&vdd>; + pvdd-supply = <&vdd>; + dvdd-3v-supply = <&vdd_3_3>; + bgvdd-supply = <&vdd>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&axi_hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + }; + + }; + }; + }; + + }; +}; + + +&mmc { + status = "okay"; + bus-width = <4>; + disable-wp; + no-1-8-v; + cap-sd-highspeed; + sd-uhs-sdr50; + sdhci-caps = <0x00000000 0x0000c800>; + sdhci-caps-mask = <0x00002000 0x0000ff00>; + no-sdio; + cdns,phy-use-ext-lpbk-dqs = <1>; + cdns,phy-use-lpbk-dqs = <1>; + cdns,phy-use-phony-dqs = <1>; + cdns,phy-use-phony-dqs-cmd = <1>; + cdns,phy-io-mask-always-on = <0>; + cdns,phy-io-mask-end = <5>; + cdns,phy-io-mask-start = <0>; + cdns,phy-data-select-oe-end = <1>; + cdns,phy-sync-method = <1>; + cdns,phy-sw-half-cycle-shift = <0>; + cdns,phy-rd-del-sel = <52>; + cdns,phy-underrun-suppress = <1>; + cdns,phy-gate-cfg-always-on = <1>; + cdns,phy-param-dll-bypass-mode = <1>; + cdns,phy-param-phase-detect-sel = <2>; + cdns,phy-param-dll-start-point = <254>; + cdns,phy-read-dqs-cmd-delay = <0>; + cdns,phy-clk-wrdqs-delay = <0>; + cdns,phy-clk-wr-delay = <0>; + cdns,phy-read-dqs-delay = <0>; + cdns,phy-phony-dqs-timing = <0>; + cdns,hrs09-rddata-en = <1>; + cdns,hrs09-rdcmd-en = <1>; + cdns,hrs09-extended-wr-mode = <1>; + cdns,hrs09-extended-rd-mode = <1>; + cdns,hrs10-hcsdclkadj = <3>; + cdns,hrs16-wrdata1-sdclk-dly = <0>; + cdns,hrs16-wrdata0-sdclk-dly = <0>; + cdns,hrs16-wrcmd1-sdclk-dly = <0>; + cdns,hrs16-wrcmd0-sdclk-dly = <0>; + cdns,hrs16-wrdata1-dly = <0>; + cdns,hrs16-wrdata0-dly = <0>; + cdns,hrs16-wrcmd1-dly = <0>; + cdns,hrs16-wrcmd0-dly = <0>; + cdns,hrs07-rw-compensate = <10>; + cdns,hrs07-idelay-val = <0>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "disabled"; + disable-over-current; +}; + +&usb31 { + status = "okay"; +}; + +&dwc3_0 { + dr_mode = "host"; +}; + +&smmu { + status = "okay"; +}; + +&watchdog0 { + status = "disabled"; +}; +&watchdog1 { + status = "disabled"; +}; +&watchdog2 { + status = "disabled"; +}; +&watchdog3 { + status = "disabled"; +}; +&watchdog4 { + status = "disabled"; +}; + +&qspi { + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + rsu-handle = <&qspi_boot>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_usb_peripheral.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_usb_peripheral.dts index 20eb867b7fbb0..90da6cf5bf059 100755 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_usb_peripheral.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_usb_peripheral.dts @@ -146,7 +146,7 @@ }; &dwc3_0 { - dr_mode = "peripheral"; + dr_mode = "host"; }; &smmu { diff --git a/arch/arm64/configs/socfpga_agilex5_axe5_eagle_defconfig b/arch/arm64/configs/socfpga_agilex5_axe5_eagle_defconfig new file mode 100644 index 0000000000000..b1dbf31e443a0 --- /dev/null +++ b/arch/arm64/configs/socfpga_agilex5_axe5_eagle_defconfig @@ -0,0 +1,1410 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PROFILING=y +CONFIG_ARCH_ACTIONS=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_ALPINE=y +CONFIG_ARCH_APPLE=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCMBCA=y +CONFIG_ARCH_BCM_IPROC=y +CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BRCMSTB=y +CONFIG_ARCH_DM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_K3=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_LG1K=y +CONFIG_ARCH_HISI=y +CONFIG_ARCH_KEEMBAY=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MESON=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NXP=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_NPCM=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_S32=y +CONFIG_ARCH_SEATTLE=y +CONFIG_ARCH_INTEL_SOCFPGA=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_TESLA_FSD=y +CONFIG_ARCH_SPRD=y +CONFIG_ARCH_THUNDER=y +CONFIG_ARCH_THUNDER2=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_VISCONTI=y +CONFIG_ARCH_XGENE=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_ARCH_STRATIX10SWVP=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NUMA=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_XEN=y +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_HIBERNATION=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ENERGY_MODEL=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPUFREQ_DT=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m +CONFIG_ARM_ARMADA_37XX_CPUFREQ=y +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=m +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_ARM_QCOM_CPUFREQ_HW=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=m +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_ARM_TEGRA186_CPUFREQ=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_ACPI=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_DEV_INTEL_FCS=m +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=m +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_IP_VS=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_GATE=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_RCAR=m +CONFIG_CAN_RCAR_CANFD=m +CONFIG_CAN_MCP251XFD=m +CONFIG_BT=m +CONFIG_BT_HIDP=m +# CONFIG_BT_LE is not set +CONFIG_BT_LEDS=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_QCOMSMD=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=m +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_NFC=m +CONFIG_NFC_NCI=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_PCI_AARDVARK=y +CONFIG_PCI_TEGRA=y +CONFIG_PCIE_RCAR_HOST=y +CONFIG_PCIE_RCAR_EP=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCIE_ALTERA=y +CONFIG_PCIE_ALTERA_MSI=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCIE_ROCKCHIP_HOST=m +CONFIG_PCIE_BRCMSTB=m +CONFIG_PCI_IMX6=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_QCOM=y +CONFIG_PCIE_ARMADA_8K=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCIE_HISI_STB=y +CONFIG_PCIE_TEGRA194_HOST=m +CONFIG_PCIE_VISCONTI_HOST=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_HISILICON_LPC=y +CONFIG_TEGRA_ACONNECT=m +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_INTEL_STRATIX10_SERVICE=y +CONFIG_INTEL_STRATIX10_RSU=m +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_MARVELL=y +CONFIG_MTD_NAND_BRCMNAND=m +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=m +CONFIG_QCOM_COINCELL=m +CONFIG_QCOM_FASTRPC=m +CONFIG_SRAM=y +CONFIG_PCI_ENDPOINT_TEST=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_UACCE=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_MEGARAID_SAS=y +CONFIG_SCSI_MPT3SAS=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_BRCM=m +CONFIG_AHCI_CEVA=y +CONFIG_AHCI_MVEBU=y +CONFIG_AHCI_XGENE=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_SATA_RCAR=y +CONFIG_PATA_PLATFORM=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_MSCC_FELIX=m +CONFIG_AMD_XGBE=y +CONFIG_NET_XGENE=y +CONFIG_ATL1C=m +CONFIG_BCMGENET=m +CONFIG_BNX2X=m +CONFIG_SYSTEMPORT=m +CONFIG_MACB=y +CONFIG_THUNDER_NIC_PF=y +CONFIG_FEC=y +CONFIG_FSL_FMAN=y +CONFIG_FSL_DPAA_ETH=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_ENETC_QOS=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_HNS3=y +CONFIG_HNS3_HCLGE=y +CONFIG_HNS3_ENET=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_MVNETA=y +CONFIG_MVPP2=y +CONFIG_SKY2=y +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_R8169=m +CONFIG_SH_ETH=y +CONFIG_RAVB=y +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_SNI_AVE=y +CONFIG_SNI_NETSEC=y +CONFIG_DWMAC_TEGRA=m +CONFIG_STMMAC_ETH=y +CONFIG_TI_K3_AM65_CPSW_NUSS=y +CONFIG_QCOM_IPA=m +CONFIG_MESON_GXL_PHY=m +CONFIG_AQUANTIA_PHY=y +CONFIG_BCM54140_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_DP83867_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_SNOC=m +CONFIG_WCN36XX=m +CONFIG_ATH11K=m +CONFIG_ATH11K_AHB=m +CONFIG_ATH11K_PCI=m +CONFIG_BRCMFMAC=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SNVS_PWRKEY=m +CONFIG_KEYBOARD_IMX_SC_KEY=m +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_PM8XXX_VIBRATOR=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_HISI_POWERKEY=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_EM=y +CONFIG_SERIAL_8250_OMAP=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MESON=y +CONFIG_SERIAL_MESON_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_TEGRA=y +CONFIG_SERIAL_TEGRA_TCU=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_QCOM_GENI=y +CONFIG_SERIAL_QCOM_GENI_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_SERIAL_MVEBU_UART=y +CONFIG_SERIAL_OWL=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_BCM2835=m +CONFIG_I2C_CADENCE=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_GPIO=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_MESON=y +CONFIG_I2C_MT65XX=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OMAP=y +CONFIG_I2C_OWL=y +CONFIG_I2C_PXA=y +CONFIG_I2C_QCOM_CCI=m +CONFIG_I2C_QCOM_GENI=m +CONFIG_I2C_QUP=y +CONFIG_I2C_RIIC=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_RZV2M=m +CONFIG_I2C_S3C2410=y +CONFIG_I2C_SH_MOBILE=y +CONFIG_I2C_TEGRA=y +CONFIG_I2C_UNIPHIER_F=y +CONFIG_I2C_RCAR=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SPI=y +CONFIG_SPI_ARMADA_3700=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_IMX=m +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_MESON_SPICC=m +CONFIG_SPI_MESON_SPIFC=m +CONFIG_SPI_ORION=y +CONFIG_SPI_PL022=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_RPCIF=m +CONFIG_SPI_RSPI=m +CONFIG_SPI_QCOM_QSPI=m +CONFIG_SPI_QUP=y +CONFIG_SPI_QCOM_GENI=m +CONFIG_SPI_S3C64XX=y +CONFIG_SPI_SH_MSIOF=m +CONFIG_SPI_SUN6I=y +CONFIG_SPI_TEGRA210_QUAD=m +CONFIG_SPI_TEGRA114=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_OWL=y +CONFIG_PINCTRL_S700=y +CONFIG_PINCTRL_S900=y +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y +CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX93=y +CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_IPQ6018=y +CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_MSM8994=y +CONFIG_PINCTRL_MSM8996=y +CONFIG_PINCTRL_MSM8998=y +CONFIG_PINCTRL_QCS404=y +CONFIG_PINCTRL_QDF2XXX=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SC7180=y +CONFIG_PINCTRL_SC7280=y +CONFIG_PINCTRL_SC8180X=yls /dev +CONFIG_PINCTRL_SC8280XP=y +CONFIG_PINCTRL_SDM845=y +CONFIG_PINCTRL_SM8150=y +CONFIG_PINCTRL_SM8250=y +CONFIG_PINCTRL_SM8350=y +CONFIG_PINCTRL_SM8450=y +CONFIG_PINCTRL_LPASS_LPI=m +CONFIG_GPIOLIB=y +CONFIG_GPIO_ALTERA=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_DAVINCI=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_MB86S7X=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_RCAR=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_GPIO_VISCONTI=y +CONFIG_GPIO_WCD934X=m +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_XGENE_SB=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_MAX77620=y +CONFIG_GPIO_SL28CPLD=m +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=m +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_SBS=m +CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_MAX17042=m +CONFIG_CHARGER_MT6360=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_SENSORS_ARM_SCMI=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SL28CPLD=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX_SC_THERMAL=m +CONFIG_IMX8MM_THERMAL=m +CONFIG_QORIQ_THERMAL=m +CONFIG_SUN8I_THERMAL=y +CONFIG_ROCKCHIP_THERMAL=m +CONFIG_RCAR_THERMAL=y +CONFIG_RCAR_GEN3_THERMAL=y +CONFIG_RZG2L_THERMAL=y +CONFIG_ARMADA_THERMAL=y +CONFIG_BCM2711_THERMAL=m +CONFIG_BCM2835_THERMAL=m +CONFIG_BRCMSTB_THERMAL=m +CONFIG_EXYNOS_THERMAL=y +CONFIG_TEGRA_SOCTHERM=m +CONFIG_TEGRA_BPMP_THERMAL=m +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_SPMI_ADC_TM5=m +CONFIG_QCOM_SPMI_TEMP_ALARM=m +CONFIG_QCOM_LMH=m +CONFIG_UNIPHIER_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_SL28CPLD_WATCHDOG=m +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_S3C2410_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_SUNXI_WATCHDOG=m +CONFIG_IMX2_WDT=y +CONFIG_IMX_SC_WDT=m +CONFIG_QCOM_WDT=m +CONFIG_MESON_GXBB_WATCHDOG=m +CONFIG_MESON_WATCHDOG=m +CONFIG_ARM_SMC_WATCHDOG=y +CONFIG_RENESAS_WDT=y +CONFIG_RENESAS_RZG2LWDT=y +CONFIG_UNIPHIER_WATCHDOG=y +CONFIG_PM8916_WATCHDOG=m +CONFIG_BCM2835_WDT=y +CONFIG_BCM7038_WDT=m +CONFIG_NPCM7XX_WATCHDOG=y +CONFIG_MFD_ALTERA_SYSMGR=y +CONFIG_MFD_BD9571MWV=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=y +CONFIG_MFD_EXYNOS_LPASS=m +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_HI655X_PMIC=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MT6360=y +CONFIG_MFD_MT6397=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_RK808=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_SL28CPLD=y +CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_WCD934X=m +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD718XX=y +CONFIG_REGULATOR_BD9571MWV=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_HI6421V530=y +CONFIG_REGULATOR_HI655X=y +CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_MP8859=y +CONFIG_REGULATOR_MT6358=y +CONFIG_REGULATOR_MT6359=y +CONFIG_REGULATOR_MT6360=y +CONFIG_REGULATOR_MT6397=y +CONFIG_REGULATOR_PCA9450=y +CONFIG_REGULATOR_PF8X00=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_RPMH=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RK808=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_VCTRL=m +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_RC_DEVICES=y +CONFIG_IR_MESON=m +CONFIG_IR_SUNXI=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_QCOM_CAMSS=m +CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_RCAR_ISP=m +CONFIG_VIDEO_RCAR_CSI2=m +CONFIG_VIDEO_RCAR_VIN=m +CONFIG_VIDEO_RENESAS_FCP=m +CONFIG_VIDEO_RENESAS_FDP1=m +CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_VIDEO_RCAR_DRIF=m +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m +CONFIG_VIDEO_SAMSUNG_S5P_MFC=m +CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +#CONFIG_DRM=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_HDLCD=m +CONFIG_DRM_MALI_DISPLAY=m +CONFIG_DRM_KOMEDA=m +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_EXYNOS=m +CONFIG_DRM_EXYNOS5433_DECON=y +CONFIG_DRM_EXYNOS7_DECON=y +CONFIG_DRM_EXYNOS_DSI=y +# CONFIG_DRM_EXYNOS_DP is not set +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_DRM_EXYNOS_MIC=y +CONFIG_DRM_ROCKCHIP=m +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_CDN_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_ROCKCHIP_LVDS=y +CONFIG_DRM_RCAR_DU=m +CONFIG_DRM_RCAR_DW_HDMI=m +CONFIG_DRM_RCAR_MIPI_DSI=m +CONFIG_DRM_SUN4I=m +CONFIG_DRM_SUN6I_DSI=m +CONFIG_DRM_SUN8I_DW_HDMI=m +CONFIG_DRM_SUN8I_MIXER=m +CONFIG_DRM_MSM=m +CONFIG_DRM_TEGRA=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_NWL_MIPI_DSI=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TI_SN65DSI86=m +#CONFIG_DRM_I2C_ADV7511=m +#CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_IMX_DCSS=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MEDIATEK=m +CONFIG_DRM_MEDIATEK_HDMI=m +CONFIG_DRM_MXSFB=m +CONFIG_DRM_MESON=m +CONFIG_DRM_PL111=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_PANFROST=m +CONFIG_DRM_TIDSS=m +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_EFI=y +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_HDA_TEGRA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_SOC=y +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_IMX_AUDMIX=m +CONFIG_SND_MESON_AXG_SOUND_CARD=m +CONFIG_SND_MESON_GX_SOUND_CARD=m +CONFIG_SND_SOC_QCOM=m +CONFIG_SND_SOC_APQ8016_SBC=m +CONFIG_SND_SOC_MSM8996=m +CONFIG_SND_SOC_SDM845=m +CONFIG_SND_SOC_SM8250=m +CONFIG_SND_SOC_SC7180=m +CONFIG_SND_SOC_SC7280=m +CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_SND_SOC_ROCKCHIP_SPDIF=m +CONFIG_SND_SOC_ROCKCHIP_RT5645=m +CONFIG_SND_SOC_RK3399_GRU_SOUND=m +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_RZ=m +CONFIG_SND_SUN8I_CODEC=m +CONFIG_SND_SUN8I_CODEC_ANALOG=m +CONFIG_SND_SUN50I_CODEC_ANALOG=m +CONFIG_SND_SUN4I_I2S=m +CONFIG_SND_SUN4I_SPDIF=m +CONFIG_SND_SOC_TEGRA=m +CONFIG_SND_SOC_TEGRA210_AHUB=m +CONFIG_SND_SOC_TEGRA210_DMIC=m +CONFIG_SND_SOC_TEGRA210_I2S=m +CONFIG_SND_SOC_TEGRA210_OPE=m +CONFIG_SND_SOC_TEGRA186_ASRC=m +CONFIG_SND_SOC_TEGRA186_DSPK=m +CONFIG_SND_SOC_TEGRA210_ADMAIF=m +CONFIG_SND_SOC_TEGRA210_MVC=m +CONFIG_SND_SOC_TEGRA210_SFC=m +CONFIG_SND_SOC_TEGRA210_AMX=m +CONFIG_SND_SOC_TEGRA210_ADX=m +CONFIG_SND_SOC_TEGRA210_MIXER=m +CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_WCD9335=m +CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_HID_MULTITOUCH=m +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_OF=m +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_TEGRA=y +CONFIG_USB_BRCMSTB=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_RENESAS_USBHS_HCD=m +CONFIG_USB_RENESAS_USBHS=m +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_MTU3=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=n +CONFIG_USB_DWC3_DUAL_ROLE=y +CONFIG_USB_COMMON=y +CONFIG_USB_HAS_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_RENESAS_USB3=m +CONFIG_USB_TEGRA_XUDC=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MMC_MESON_GX=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SPI=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_UNIPHIER=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_HI3798CV200=y +CONFIG_MMC_DW_K3=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SUNXI=y +CONFIG_MMC_BCM2835=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MMC_OWL=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=m +CONFIG_SCSI_UFS_HISI=y +CONFIG_SCSI_UFS_RENESAS=m +CONFIG_SCSI_UFS_EXYNOS=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_QCOM_LPG=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_EDAC=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_LAYERSCAPE=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_CROS_EC=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=m +CONFIG_RTC_DRV_S3C=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_DRV_ARMADA38X=y +CONFIG_RTC_DRV_PM8XXX=m +CONFIG_RTC_DRV_TEGRA=y +CONFIG_RTC_DRV_SNVS=m +CONFIG_RTC_DRV_IMX_SC=m +CONFIG_RTC_DRV_MT6397=m +CONFIG_RTC_DRV_XGENE=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y +CONFIG_DMA_SUN6I=m +CONFIG_FSL_EDMA=y +CONFIG_IMX_SDMA=m +CONFIG_K3_DMA=y +CONFIG_MV_XOR=y +CONFIG_MV_XOR_V2=y +CONFIG_OWL_DMA=y +CONFIG_PL330_DMA=y +CONFIG_TEGRA186_GPC_DMA=y +CONFIG_TEGRA20_APB_DMA=y +CONFIG_TEGRA210_ADMA=m +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_GPI_DMA=m +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_RCAR_DMAC=y +CONFIG_RENESAS_USB_DMAC=m +CONFIG_RZ_DMAC=y +CONFIG_TI_K3_UDMA=y +CONFIG_TI_K3_UDMA_GLUE_LAYER=y +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_VFIO=m +CONFIG_VFIO_PCI=m +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_IMX_MEDIA=m +CONFIG_VIDEO_MAX96712=m +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_CHARDEV=m +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_FSL_SAI=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_VC5=y +CONFIG_COMMON_CLK_NPCM8XX=y +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_CLK_RASPBERRYPI=m +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_CLK_IMX8ULP=y +CONFIG_CLK_IMX93=y +CONFIG_TI_SCI_CLK=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_A53PLL=y +CONFIG_QCOM_CLK_APCS_MSM8916=y +CONFIG_QCOM_CLK_APCC_MSM8996=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_QCOM_CLK_RPMH=y +CONFIG_IPQ_GCC_6018=y +CONFIG_IPQ_GCC_8074=y +CONFIG_MSM_GCC_8916=y +CONFIG_MSM_GCC_8994=y +CONFIG_MSM_MMCC_8996=y +CONFIG_MSM_GCC_8998=y +CONFIG_QCS_GCC_404=y +CONFIG_SC_GCC_7180=y +CONFIG_SC_GCC_7280=y +CONFIG_SC_GCC_8180X=y +CONFIG_SC_GCC_8280XP=y +CONFIG_SDM_CAMCC_845=m +CONFIG_SDM_GPUCC_845=y +CONFIG_SDM_VIDEOCC_845=y +CONFIG_SDM_DISPCC_845=y +CONFIG_SM_DISPCC_8250=y +CONFIG_SM_GCC_8350=y +CONFIG_SM_GCC_8450=y +CONFIG_SM_GPUCC_8150=y +CONFIG_SM_GPUCC_8250=y +CONFIG_SM_VIDEOCC_8250=y +CONFIG_QCOM_HFPLL=y +CONFIG_CLK_GFM_LPASS_SM8250=m +CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_RENESAS_OSTM=y +CONFIG_ARM_MHU=y +CONFIG_IMX_MBOX=y +CONFIG_PLATFORM_MHU=y +CONFIG_BCM2835_MBOX=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_QCOM_IPCC=y +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_TEGRA_IOMMU_SMMU=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_MTK_IOMMU=y +CONFIG_QCOM_IOMMU=y +CONFIG_REMOTEPROC=y +CONFIG_QCOM_Q6V5_ADSP=m +CONFIG_QCOM_Q6V5_MSS=m +CONFIG_QCOM_Q6V5_PAS=m +CONFIG_QCOM_SYSMON=m +CONFIG_QCOM_WCNSS_PIL=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=m +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_OWL_PM_DOMAINS=y +CONFIG_RASPBERRYPI_POWER=y +CONFIG_FSL_DPAA=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_RCPM=y +CONFIG_MTK_DEVAPC=m +CONFIG_MTK_PMIC_WRAP=y +CONFIG_QCOM_AOSS_QMP=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QCOM_CPR=y +CONFIG_QCOM_GENI_SE=y +CONFIG_QCOM_LLCC=m +CONFIG_QCOM_OCMEM=m +CONFIG_QCOM_RMTFS_MEM=m +CONFIG_QCOM_RPMH=y +CONFIG_QCOM_RPMHPD=y +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_QCOM_SOCINFO=m +CONFIG_QCOM_SPM=m +CONFIG_QCOM_STATS=m +CONFIG_QCOM_WCNSS_CTRL=m +CONFIG_QCOM_APR=m +CONFIG_QCOM_ICC_BWMON=m +CONFIG_ARCH_R8A77995=y +CONFIG_ARCH_R8A77990=y +CONFIG_ARCH_R8A77950=y +CONFIG_ARCH_R8A77951=y +CONFIG_ARCH_R8A77965=y +CONFIG_ARCH_R8A77960=y +CONFIG_ARCH_R8A77961=y +CONFIG_ARCH_R8A779F0=y +CONFIG_ARCH_R8A77980=y +CONFIG_ARCH_R8A77970=y +CONFIG_ARCH_R8A779A0=y +CONFIG_ARCH_R8A779G0=y +CONFIG_ARCH_R8A774C0=y +CONFIG_ARCH_R8A774E1=y +CONFIG_ARCH_R8A774A1=y +CONFIG_ARCH_R8A774B1=y +CONFIG_ARCH_R9A07G043=y +CONFIG_ARCH_R9A07G044=y +CONFIG_ARCH_R9A07G054=y +CONFIG_ARCH_R9A09G011=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_ARCH_TEGRA_132_SOC=y +CONFIG_ARCH_TEGRA_210_SOC=y +CONFIG_ARCH_TEGRA_186_SOC=y +CONFIG_ARCH_TEGRA_194_SOC=y +CONFIG_ARCH_TEGRA_234_SOC=y +CONFIG_TI_SCI_PM_DOMAINS=y +CONFIG_ARM_IMX_BUS_DEVFREQ=m +CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_RENESAS_RPCIF=m +CONFIG_IIO=y +CONFIG_EXYNOS_ADC=y +CONFIG_MAX9611=m +CONFIG_QCOM_SPMI_VADC=m +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_ROCKCHIP_SARADC=m +CONFIG_RZG2L_ADC=m +CONFIG_TI_ADS1015=m +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_SENSORS_ISL29018=m +CONFIG_VCNL4000=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_MPL3115=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_BRCMSTB=m +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_IMX27=m +CONFIG_PWM_MESON=m +CONFIG_PWM_MTK_DISP=m +CONFIG_PWM_MEDIATEK=m +CONFIG_PWM_RCAR=m +CONFIG_PWM_RENESAS_TPU=m +CONFIG_PWM_ROCKCHIP=y +CONFIG_PWM_SAMSUNG=y +CONFIG_PWM_SL28CPLD=m +CONFIG_PWM_SUN4I=m +CONFIG_PWM_TEGRA=m +CONFIG_PWM_VISCONTI=m +CONFIG_SL28CPLD_INTC=y +CONFIG_QCOM_PDC=y +CONFIG_RESET_IMX7=y +CONFIG_RESET_QCOM_AOSS=y +CONFIG_RESET_QCOM_PDC=m +CONFIG_RESET_RZG2L_USBPHY_CTRL=y +CONFIG_RESET_TI_SCI=y +CONFIG_PHY_XGENE=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_MIXEL_MIPI_DPHY=m +CONFIG_PHY_FSL_IMX8M_PCIE=y +CONFIG_PHY_HI6220_USB=y +CONFIG_PHY_HISTB_COMBPHY=y +CONFIG_PHY_HISI_INNO_USB2=y +CONFIG_PHY_MVEBU_CP110_COMPHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_PHY_QCOM_EDP=m +CONFIG_PHY_QCOM_PCIE2=m +CONFIG_PHY_QCOM_QMP=m +CONFIG_PHY_QCOM_QUSB2=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m +CONFIG_PHY_QCOM_USB_HS_28NM=m +CONFIG_PHY_QCOM_USB_SS=m +CONFIG_PHY_RCAR_GEN3_PCIE=y +CONFIG_PHY_RCAR_GEN3_USB2=y +CONFIG_PHY_RCAR_GEN3_USB3=m +CONFIG_PHY_ROCKCHIP_EMMC=y +CONFIG_PHY_ROCKCHIP_INNO_HDMI=m +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m +CONFIG_PHY_ROCKCHIP_PCIE=m +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_SAMSUNG_UFS=y +CONFIG_PHY_UNIPHIER_USB2=y +CONFIG_PHY_UNIPHIER_USB3=y +CONFIG_PHY_TEGRA_XUSB=y +CONFIG_PHY_AM654_SERDES=m +CONFIG_PHY_J721E_WIZ=m +CONFIG_ARM_CCI_PMU=m +CONFIG_ARM_CCN=m +CONFIG_ARM_CMN=m +CONFIG_ARM_SMMU_V3_PMU=m +CONFIG_ARM_DSU_PMU=m +CONFIG_FSL_IMX8_DDR_PMU=m +CONFIG_ARM_SPE_PMU=m +CONFIG_ARM_DMC620_PMU=m +CONFIG_QCOM_L2_PMU=y +CONFIG_QCOM_L3_PMU=y +CONFIG_HISI_PMU=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_NVMEM_MTK_EFUSE=y +CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_NVMEM_ROCKCHIP_EFUSE=y +CONFIG_NVMEM_SUNXI_SID=y +CONFIG_NVMEM_UNIPHIER_EFUSE=y +CONFIG_NVMEM_MESON_EFUSE=m +CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_LAYERSCAPE_SFP=m +CONFIG_FPGA=y +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_STRATIX10_SOC=m +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SLIMBUS=m +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_SLIM_QCOM_NGD_CTRL=m +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_IMX=m +CONFIG_INTERCONNECT_IMX8MM=m +CONFIG_INTERCONNECT_IMX8MN=m +CONFIG_INTERCONNECT_IMX8MQ=m +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_MSM8916=m +CONFIG_INTERCONNECT_QCOM_MSM8996=m +CONFIG_INTERCONNECT_QCOM_OSM_L3=m +CONFIG_INTERCONNECT_QCOM_QCS404=m +CONFIG_INTERCONNECT_QCOM_SC7180=m +CONFIG_INTERCONNECT_QCOM_SC7280=y +CONFIG_INTERCONNECT_QCOM_SC8180X=y +CONFIG_INTERCONNECT_QCOM_SC8280XP=y +CONFIG_INTERCONNECT_QCOM_SDM845=y +CONFIG_INTERCONNECT_QCOM_SM8150=m +CONFIG_INTERCONNECT_QCOM_SM8250=m +CONFIG_INTERCONNECT_QCOM_SM8350=m +CONFIG_INTERCONNECT_QCOM_SM8450=m +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_OF_CONFIGFS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_SECURITY=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_DEV_SUN8I_CE=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m +CONFIG_CRYPTO_DEV_QCOM_RNG=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_HISI_SEC2=m +CONFIG_CRYPTO_DEV_HISI_ZIP=m +CONFIG_CRYPTO_DEV_HISI_HPRE=m +CONFIG_CRYPTO_DEV_HISI_TRNG=m +#CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_CORESIGHT=m +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m +CONFIG_CORESIGHT_CATU=m +CONFIG_CORESIGHT_SINK_TPIU=m +CONFIG_CORESIGHT_SINK_ETBV10=m +CONFIG_CORESIGHT_STM=m +CONFIG_CORESIGHT_CPU_DEBUG=m +CONFIG_CORESIGHT_CTI=m +CONFIG_MEMTEST=y +CONFIG_HW_RANDOM=m +CONFIG_MTD_UBI=y +CONFIG_UBIFS_FS=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n +# TSN phy support +CONFIG_ADIN_PHY=y +CONFIG_ADIN1100_PHY=y +CONFIG_COMPILE_TEST=y +# DRM and ADV7511 support +CONFIG_DRM=y +CONFIG_HAS_IOMEM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_I2C_ADV7511=y +# AXI_HDMI fpga ip support +CONFIG_DRM_ADI_AXI_HDMI=y +# contiguous memory allocation for the video frame buffer support +CONFIG_CMA=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=128 +# DMA support +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_REGMAP_MMIO=y +CONFIG_AXI_DMAC=y +# CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_COMMON_CLK=y +CONFIG_ALTERA_SYSID=y diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index f30dabc99795d..689c6ef4c3885 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -18,7 +18,7 @@ #include #include #include -#include + #include #include #include @@ -56,9 +56,9 @@ #define AXI_DMAC_DMA_DST_TYPE_GET(x) FIELD_GET(AXI_DMAC_DMA_DST_TYPE_MSK, x) #define AXI_DMAC_DMA_DST_WIDTH_MSK GENMASK(3, 0) #define AXI_DMAC_DMA_DST_WIDTH_GET(x) FIELD_GET(AXI_DMAC_DMA_DST_WIDTH_MSK, x) -#define AXI_DMAC_REG_COHERENCY_DESC 0x14 -#define AXI_DMAC_DST_COHERENT_MSK BIT(0) -#define AXI_DMAC_DST_COHERENT_GET(x) FIELD_GET(AXI_DMAC_DST_COHERENT_MSK, x) + + + #define AXI_DMAC_REG_IRQ_MASK 0x80 #define AXI_DMAC_REG_IRQ_PENDING 0x84 @@ -79,6 +79,9 @@ #define AXI_DMAC_REG_STATUS 0x430 #define AXI_DMAC_REG_CURRENT_SRC_ADDR 0x434 #define AXI_DMAC_REG_CURRENT_DEST_ADDR 0x438 +#define AXI_DMAC_REG_DBG0 0x43c +#define AXI_DMAC_REG_DBG1 0x440 +#define AXI_DMAC_REG_DBG2 0x444 #define AXI_DMAC_REG_PARTIAL_XFER_LEN 0x44c #define AXI_DMAC_REG_PARTIAL_XFER_ID 0x450 @@ -149,6 +152,8 @@ struct axi_dmac { struct dma_device dma_dev; struct axi_dmac_chan chan; + + struct device_dma_parameters dma_parms; }; static struct axi_dmac *chan_to_axi_dmac(struct axi_dmac_chan *chan) @@ -413,6 +418,8 @@ static irqreturn_t axi_dmac_interrupt_handler(int irq, void *devid) struct axi_dmac *dmac = devid; unsigned int pending; bool start_next = false; + + pending = axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING); if (!pending) @@ -502,8 +509,13 @@ static struct axi_dmac_sg *axi_dmac_fill_linear_sg(struct axi_dmac_chan *chan, unsigned int segment_size; unsigned int len; - /* Split into multiple equally sized segments if necessary */ - num_segments = DIV_ROUND_UP(period_len, chan->max_length); + /* + * Split into multiple equally sized segments if necessary. + * chan->max_length can be UINT_MAX, so ensure there are no overflows + * resuting in divide-by-zero errors by casting to u64. + */ + num_segments = DIV_ROUND_UP_ULL((u64)period_len, + (u64)chan->max_length); segment_size = DIV_ROUND_UP(period_len, num_segments); /* Take care of alignment */ segment_size = ((segment_size - 1) | chan->length_align_mask) + 1; @@ -577,6 +589,21 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg( return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } +static int axi_dmac_device_config(struct dma_chan *c, + struct dma_slave_config *slave_config) +{ + struct axi_dmac_chan *chan = to_axi_dmac_chan(c); + struct axi_dmac *dmac = chan_to_axi_dmac(chan); + + /* no configuration required, a sanity check is done instead */ + if (slave_config->direction != chan->direction) { + dev_err(dmac->dma_dev.dev, "Direction not supported by this DMA Channel"); + return -EINVAL; + } + + return 0; +} + static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic( struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, @@ -713,6 +740,9 @@ static bool axi_dmac_regmap_rdwr(struct device *dev, unsigned int reg) case AXI_DMAC_REG_STATUS: case AXI_DMAC_REG_CURRENT_SRC_ADDR: case AXI_DMAC_REG_CURRENT_DEST_ADDR: + case AXI_DMAC_REG_DBG0: + case AXI_DMAC_REG_DBG1: + case AXI_DMAC_REG_DBG2: case AXI_DMAC_REG_PARTIAL_XFER_LEN: case AXI_DMAC_REG_PARTIAL_XFER_ID: return true; @@ -766,6 +796,7 @@ static int axi_dmac_parse_chan_dt(struct device_node *of_chan, ret = of_property_read_u32(of_chan, "adi,source-bus-type", &val); if (ret) return ret; + if (val > AXI_DMAC_BUS_TYPE_FIFO) return -EINVAL; chan->src_type = val; @@ -773,6 +804,7 @@ static int axi_dmac_parse_chan_dt(struct device_node *of_chan, ret = of_property_read_u32(of_chan, "adi,destination-bus-type", &val); if (ret) return ret; + if (val > AXI_DMAC_BUS_TYPE_FIFO) return -EINVAL; chan->dest_type = val; @@ -799,6 +831,7 @@ static int axi_dmac_parse_dt(struct device *dev, struct axi_dmac *dmac) of_channels = of_get_child_by_name(dev->of_node, "adi,channels"); if (of_channels == NULL) + return -ENODEV; for_each_child_of_node(of_channels, of_chan) { @@ -806,6 +839,7 @@ static int axi_dmac_parse_dt(struct device *dev, struct axi_dmac *dmac) if (ret) { of_node_put(of_chan); of_node_put(of_channels); + return -EINVAL; } } @@ -911,19 +945,23 @@ static int axi_dmac_probe(struct platform_device *pdev) struct dma_device *dma_dev; struct axi_dmac *dmac; struct resource *res; - struct regmap *regmap; + unsigned int version; int ret; + printk("axi_dmac: entry\n"); + dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL); if (!dmac) return -ENOMEM; + dmac->irq = platform_get_irq(pdev, 0); if (dmac->irq < 0) return dmac->irq; if (dmac->irq == 0) return -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); dmac->base = devm_ioremap_resource(&pdev->dev, res); @@ -938,18 +976,27 @@ static int axi_dmac_probe(struct platform_device *pdev) if (ret < 0) return ret; + INIT_LIST_HEAD(&dmac->chan.active_descs); + version = axi_dmac_read(dmac, ADI_AXI_REG_VERSION); + + if (version >= ADI_AXI_PCORE_VER(4, 3, 'a')) + ret = axi_dmac_read_chan_config(&pdev->dev, dmac); else + ret = axi_dmac_parse_dt(&pdev->dev, dmac); + if (ret < 0) - goto err_clk_disable; - - INIT_LIST_HEAD(&dmac->chan.active_descs); + return ret; + + + + pdev->dev.dma_parms = &dmac->dma_parms; dma_set_max_seg_size(&pdev->dev, UINT_MAX); dma_dev = &dmac->dma_dev; @@ -960,6 +1007,7 @@ static int axi_dmac_probe(struct platform_device *pdev) dma_dev->device_tx_status = dma_cookie_status; dma_dev->device_issue_pending = axi_dmac_issue_pending; dma_dev->device_prep_slave_sg = axi_dmac_prep_slave_sg; + dma_dev->device_config = axi_dmac_device_config; dma_dev->device_prep_dma_cyclic = axi_dmac_prep_dma_cyclic; dma_dev->device_prep_interleaved_dma = axi_dmac_prep_interleaved; dma_dev->device_terminate_all = axi_dmac_terminate_all; @@ -983,18 +1031,18 @@ static int axi_dmac_probe(struct platform_device *pdev) axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00); - if (of_dma_is_coherent(pdev->dev.of_node)) { - ret = axi_dmac_read(dmac, AXI_DMAC_REG_COHERENCY_DESC); - - if (version < ADI_AXI_PCORE_VER(4, 4, 'a') || - !AXI_DMAC_DST_COHERENT_GET(ret)) { - dev_err(dmac->dma_dev.dev, - "Coherent DMA not supported in hardware"); - ret = -EINVAL; - goto err_clk_disable; - } - } - + + + + + + + + + + + + ret = dma_async_device_register(dma_dev); if (ret) goto err_clk_disable; @@ -1011,17 +1059,19 @@ static int axi_dmac_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dmac); - regmap = devm_regmap_init_mmio(&pdev->dev, dmac->base, - &axi_dmac_regmap_config); - if (IS_ERR(regmap)) { - ret = PTR_ERR(regmap); - goto err_free_irq; - } + devm_regmap_init_mmio(&pdev->dev, dmac->base, &axi_dmac_regmap_config); + + + + + + + return 0; -err_free_irq: - free_irq(dmac->irq, dmac); + + err_unregister_of: of_dma_controller_free(pdev->dev.of_node); err_unregister_device: diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index f30f99166531f..2b79c29fceab5 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -298,6 +298,8 @@ source "drivers/gpu/drm/nouveau/Kconfig" source "drivers/gpu/drm/i915/Kconfig" +source "drivers/gpu/drm/adi_axi_hdmi/Kconfig" + source "drivers/gpu/drm/kmb/Kconfig" config DRM_VGEM diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 0b283e46f28b8..6197dbde30f63 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_DRM_ARMADA) += armada/ obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/ obj-y += rcar-du/ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ +obj-$(CONFIG_DRM_ADI_AXI_HDMI) += adi_axi_hdmi/ obj-y += omapdrm/ obj-$(CONFIG_DRM_SUN4I) += sun4i/ obj-y += tilcdc/ diff --git a/drivers/gpu/drm/adi_axi_hdmi/Kconfig b/drivers/gpu/drm/adi_axi_hdmi/Kconfig new file mode 100644 index 0000000000000..0b10f6f0759d8 --- /dev/null +++ b/drivers/gpu/drm/adi_axi_hdmi/Kconfig @@ -0,0 +1,8 @@ +config DRM_ADI_AXI_HDMI + tristate "DRM Support for Analog Devices HDMI FPGA platforms" + depends on DRM + default n + select DRM_GEM_DMA_HELPER + select DRM_KMS_HELPER + select XILINX_VDMA + select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE diff --git a/drivers/gpu/drm/adi_axi_hdmi/Makefile b/drivers/gpu/drm/adi_axi_hdmi/Makefile new file mode 100644 index 0000000000000..5a889bde39743 --- /dev/null +++ b/drivers/gpu/drm/adi_axi_hdmi/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the drm device driver. This driver provides support for the +# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. + +adi_axi_hdmi-y := axi_hdmi_encoder.o axi_hdmi_crtc.o axi_hdmi_drv.o + +obj-$(CONFIG_DRM_ADI_AXI_HDMI) += adi_axi_hdmi.o diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c new file mode 100644 index 0000000000000..2a21f4cac6f63 --- /dev/null +++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c @@ -0,0 +1,251 @@ +/* + * Analog Devices AXI HDMI DRM driver. + * + * Copyright 2012 Analog Devices Inc. + * Author: Lars-Peter Clausen + * + * Licensed under the GPL-2. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "axi_hdmi_drv.h" + +struct axi_hdmi_crtc { + struct drm_crtc drm_crtc; + struct drm_plane plane; + + struct dma_chan *dma; + struct dma_interleaved_template *dma_template; +}; + +static struct axi_hdmi_crtc *plane_to_axi_hdmi_crtc(struct drm_plane *plane) +{ + return container_of(plane, struct axi_hdmi_crtc, plane); +} + +static struct axi_hdmi_crtc *to_axi_hdmi_crtc(struct drm_crtc *crtc) +{ + return container_of(crtc, struct axi_hdmi_crtc, drm_crtc); +} + +static struct dma_async_tx_descriptor *axi_hdmi_vdma_prep_interleaved_desc( + struct drm_plane *plane) +{ + struct axi_hdmi_crtc *axi_hdmi_crtc = plane_to_axi_hdmi_crtc(plane); + struct drm_framebuffer *fb = plane->state->fb; + size_t offset, hw_row_size; + struct drm_gem_dma_object *obj; + +#if IS_ENABLED(CONFIG_XILINX_DMA) + struct xilinx_vdma_config vdma_config; + + if (!strncmp(axi_hdmi_crtc->dma->device->dev->driver->name, "xilinx-vdma", 11)) { + memset(&vdma_config, 0, sizeof(vdma_config)); + vdma_config.park = 1; + vdma_config.coalesc = 0xff; + xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config); + } +#endif + + obj = drm_fb_dma_get_gem_obj(plane->state->fb, 0); + + offset = plane->state->crtc_x * fb->format->cpp[0] + + plane->state->crtc_y * fb->pitches[0]; + + /* Interleaved DMA is used that way: + * Each interleaved frame is a row (hsize) implemented in ONE + * chunk (sgl has len 1). + * The number of interleaved frames is the number of rows (vsize). + * The icg in used to pack data to the HW, so that the buffer len + * is fb->piches[0], but the actual size for the hw is somewhat less + */ + axi_hdmi_crtc->dma_template->dir = DMA_MEM_TO_DEV; + axi_hdmi_crtc->dma_template->src_start = obj->dma_addr + offset; + /* sgl list have just one entry (each interleaved frame have 1 chunk) */ + axi_hdmi_crtc->dma_template->frame_size = 1; + /* the number of interleaved frame, each has the size specified in sgl */ + axi_hdmi_crtc->dma_template->numf = plane->state->crtc_h; + axi_hdmi_crtc->dma_template->src_sgl = 1; + axi_hdmi_crtc->dma_template->src_inc = 1; + + /* vdma IP does not provide any addr to the hdmi IP, so dst_inc + * and dst_sgl should make no any difference. + */ + axi_hdmi_crtc->dma_template->dst_inc = 0; + axi_hdmi_crtc->dma_template->dst_sgl = 0; + + hw_row_size = plane->state->crtc_w * fb->format->cpp[0]; + axi_hdmi_crtc->dma_template->sgl[0].size = hw_row_size; + + /* the vdma driver seems to look at icg, and not src_icg */ + axi_hdmi_crtc->dma_template->sgl[0].icg = + fb->pitches[0] - hw_row_size; + + return dmaengine_prep_interleaved_dma(axi_hdmi_crtc->dma, + axi_hdmi_crtc->dma_template, DMA_CYCLIC); +} + +static void axi_hdmi_plane_atomic_update(struct drm_plane *plane, + struct drm_atomic_state *old_state) +{ + struct axi_hdmi_crtc *axi_hdmi_crtc = plane_to_axi_hdmi_crtc(plane); + struct dma_async_tx_descriptor *desc; + + if (!plane->state->crtc || !plane->state->fb) + return; + + dmaengine_terminate_all(axi_hdmi_crtc->dma); + + desc = axi_hdmi_vdma_prep_interleaved_desc(plane); + if (!desc) { + pr_err("Failed to prepare DMA descriptor\n"); + return; + } + + dmaengine_submit(desc); + dma_async_issue_pending(axi_hdmi_crtc->dma); +} + +static void axi_hdmi_crtc_enable(struct drm_crtc *crtc, + struct drm_atomic_state *old_state) +{ +} + +static void axi_hdmi_crtc_disable(struct drm_crtc *crtc, + struct drm_atomic_state *old_state) +{ + struct axi_hdmi_crtc *axi_hdmi_crtc = to_axi_hdmi_crtc(crtc); + + dmaengine_terminate_all(axi_hdmi_crtc->dma); +} + +static void axi_hdmi_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_pending_vblank_event *event = crtc->state->event; + + if (event) { + crtc->state->event = NULL; + + spin_lock_irq(&crtc->dev->event_lock); + drm_crtc_send_vblank_event(crtc, event); + spin_unlock_irq(&crtc->dev->event_lock); + } +} + +static const struct drm_crtc_helper_funcs axi_hdmi_crtc_helper_funcs = { + .atomic_enable = axi_hdmi_crtc_enable, + .atomic_disable = axi_hdmi_crtc_disable, + .atomic_begin = axi_hdmi_crtc_atomic_begin, +}; + +static void axi_hdmi_crtc_destroy(struct drm_crtc *crtc) +{ + struct axi_hdmi_crtc *axi_hdmi_crtc = to_axi_hdmi_crtc(crtc); + + drm_crtc_cleanup(crtc); + kfree(axi_hdmi_crtc->dma_template); + kfree(axi_hdmi_crtc); +} + +static const struct drm_crtc_funcs axi_hdmi_crtc_funcs = { + .destroy = axi_hdmi_crtc_destroy, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .reset = drm_atomic_helper_crtc_reset, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +}; + +static const struct drm_plane_helper_funcs axi_hdmi_plane_helper_funcs = { + .atomic_update = axi_hdmi_plane_atomic_update, +}; + +static void axi_hdmi_plane_destroy(struct drm_plane *plane) +{ + drm_plane_cleanup(plane); +} + +static const struct drm_plane_funcs axi_hdmi_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = axi_hdmi_plane_destroy, + .reset = drm_atomic_helper_plane_reset, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, +}; + +static const u32 axi_hdmi_supported_formats[] = { + DRM_FORMAT_XRGB8888, +}; + +struct drm_crtc *axi_hdmi_crtc_create(struct drm_device *dev) +{ + struct axi_hdmi_private *p = dev->dev_private; + struct axi_hdmi_crtc *axi_hdmi_crtc; + struct drm_crtc *crtc; + struct drm_plane *plane; + int ret; + + if (!dma_has_cap(DMA_INTERLEAVE, p->dma->device->cap_mask)) { + DRM_ERROR("DMA needs to support interleaved transfers\n"); + return ERR_PTR(-EINVAL); + } + + axi_hdmi_crtc = kzalloc(sizeof(*axi_hdmi_crtc), GFP_KERNEL); + if (!axi_hdmi_crtc) + return ERR_PTR(-ENOMEM); + + crtc = &axi_hdmi_crtc->drm_crtc; + plane = &axi_hdmi_crtc->plane; + + /* we know we'll always use only one data chunk */ + axi_hdmi_crtc->dma_template = kzalloc( + sizeof(struct dma_interleaved_template) + + sizeof(struct data_chunk), GFP_KERNEL); + if (!axi_hdmi_crtc->dma_template) { + ret = -ENOMEM; + goto err_free_crtc; + } + + ret = drm_universal_plane_init(dev, plane, 0xff, &axi_hdmi_plane_funcs, + axi_hdmi_supported_formats, + ARRAY_SIZE(axi_hdmi_supported_formats), NULL, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) + goto err_free_dma_template; + + drm_plane_helper_add(plane, &axi_hdmi_plane_helper_funcs); + + axi_hdmi_crtc->dma = p->dma; + + ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, + &axi_hdmi_crtc_funcs, NULL); + if (ret) + goto err_plane_destroy; + drm_crtc_helper_add(crtc, &axi_hdmi_crtc_helper_funcs); + + return crtc; + +err_plane_destroy: + axi_hdmi_plane_destroy(plane); +err_free_dma_template: + kfree(axi_hdmi_crtc->dma_template); +err_free_crtc: + kfree(axi_hdmi_crtc); + + return ERR_PTR(ret); +} diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_drv.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_drv.c new file mode 100644 index 0000000000000..faa3b03811c92 --- /dev/null +++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_drv.c @@ -0,0 +1,226 @@ +/* + * Analog Devices AXI HDMI DRM driver. + * + * Copyright 2012 Analog Devices Inc. + * Author: Lars-Peter Clausen + * + * Licensed under the GPL-2. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "axi_hdmi_drv.h" + +#define DRIVER_NAME "axi_hdmi_drm" +#define DRIVER_DESC "AXI HDMI DRM" +#define DRIVER_DATE "20120930" +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 0 + +static struct drm_mode_config_funcs axi_hdmi_mode_config_funcs = { + .fb_create = drm_gem_fb_create, + .output_poll_changed = drm_fb_helper_output_poll_changed, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static void axi_hdmi_mode_config_init(struct drm_device *dev) +{ + drm_mode_config_init(dev); + + dev->mode_config.min_width = 0; + dev->mode_config.min_height = 0; + + dev->mode_config.max_width = 4096; + dev->mode_config.max_height = 4096; + + dev->mode_config.funcs = &axi_hdmi_mode_config_funcs; +} + +static int axi_hdmi_init(struct drm_driver *ddrv, struct device *dev) +{ + struct axi_hdmi_private *private = dev_get_drvdata(dev); + struct drm_device *ddev; + struct drm_encoder *encoder; + int ret; + ddev = drm_dev_alloc(ddrv, dev); + if (IS_ERR(ddev)) + return PTR_ERR(ddev); + private->drm_dev = ddev; + + ddev->dev_private = private; + axi_hdmi_mode_config_init(ddev); + + private->crtc = axi_hdmi_crtc_create(ddev); + if (IS_ERR(private->crtc)) { + ret = PTR_ERR(private->crtc); + goto err_crtc; + } + encoder = axi_hdmi_encoder_create(ddev); + if (IS_ERR(encoder)) { + ret = PTR_ERR(encoder); + goto err_crtc; + } + drm_mode_config_reset(ddev); + + /* init kms poll for handling hpd */ + drm_kms_helper_poll_init(ddev); + + ret = drm_dev_register(ddev, 0); + if (ret) + goto err_crtc; + drm_fbdev_generic_setup(ddev, 32); + return 0; +err_crtc: + drm_mode_config_cleanup(ddev); + + return ret; +} + +static void axi_hdmi_unload(struct drm_device *dev) +{ + drm_kms_helper_poll_fini(dev); + drm_mode_config_cleanup(dev); +} + +static const struct file_operations axi_hdmi_driver_fops = { + .owner = THIS_MODULE, + .open = drm_open, + .mmap = drm_gem_mmap, + .poll = drm_poll, + .read = drm_read, + .unlocked_ioctl = drm_ioctl, + .release = drm_release, +}; + +static struct drm_driver axi_hdmi_driver = { + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, + .unload = axi_hdmi_unload, + .lastclose = drm_fb_helper_lastclose, + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_import_sg_table = drm_gem_dma_prime_import_sg_table, + .dumb_create = drm_gem_dma_dumb_create, + .fops = &axi_hdmi_driver_fops, + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, + .major = DRIVER_MAJOR, + .minor = DRIVER_MINOR, +}; + +static const struct of_device_id adv7511_encoder_of_match[] = { + { + .compatible = "adi,axi-hdmi-tx-1.00.a", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, adv7511_encoder_of_match); + +static int axi_hdmi_platform_probe(struct platform_device *pdev) +{ + const struct of_device_id *id; + struct device_node *np = pdev->dev.of_node; + struct axi_hdmi_private *private; + struct device_node *slave_node, *ep_node; + struct of_endpoint ep; + struct resource *res; + int ret; + + private = devm_kzalloc(&pdev->dev, sizeof(*private), GFP_KERNEL); + if (!private) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + private->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(private->base)) + return PTR_ERR(private->base); + + /*private->hdmi_clock = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(private->hdmi_clock)) { + return -EPROBE_DEFER; + }*/ + + ep_node = of_graph_get_next_endpoint(np, NULL); + if (ep_node) { + ret = of_graph_parse_endpoint(ep_node, &ep); + if (ret) { + of_node_put(ep_node); + return ret; + } + if (ep.port != 0 && ep.id != 0) { + of_node_put(ep_node); + return -EINVAL; + } + slave_node = of_graph_get_remote_port_parent(ep_node); + of_node_put(ep_node); + } else { + slave_node = of_parse_phandle(np, "encoder-slave", 0); + } + + if (!slave_node) + return -EINVAL; + + private->is_rgb = of_property_read_bool(np, "adi,is-rgb"); + + id = of_match_node(adv7511_encoder_of_match, np); + + private->encoder_slave = of_find_i2c_device_by_node(slave_node); + of_node_put(slave_node); + + if (!private->encoder_slave || !private->encoder_slave->dev.driver) + return -EPROBE_DEFER; + + private->dma = dma_request_slave_channel(&pdev->dev, "video"); + if (private->dma == NULL) { + return -EPROBE_DEFER; + } + + platform_set_drvdata(pdev, private); + + return axi_hdmi_init(&axi_hdmi_driver, &pdev->dev); +} + +static int axi_hdmi_platform_remove(struct platform_device *pdev) +{ + struct axi_hdmi_private *private = platform_get_drvdata(pdev); + + drm_atomic_helper_shutdown(private->drm_dev); + + drm_put_dev(private->drm_dev); + dma_release_channel(private->dma); + return 0; +} + +static struct platform_driver adv7511_encoder_driver = { + .driver = { + .name = "axi-hdmi", + .owner = THIS_MODULE, + .of_match_table = adv7511_encoder_of_match, + }, + .probe = axi_hdmi_platform_probe, + .remove = axi_hdmi_platform_remove, +}; +module_platform_driver(adv7511_encoder_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_DESCRIPTION(""); diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_drv.h b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_drv.h new file mode 100644 index 0000000000000..6570c9e9353c9 --- /dev/null +++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_drv.h @@ -0,0 +1,44 @@ +/* + * Analog Devices AXI HDMI DRM driver. + * + * Copyright 2012 Analog Devices Inc. + * Author: Lars-Peter Clausen + * + * Licensed under the GPL-2. + */ + +#ifndef _AXI_HDMI_DRV_H_ +#define _AXI_HDMI_DRV_H_ + +#include +#include +#include +#include + +struct xlnx_pcm_dma_params { + struct device_node *of_node; + int chan_id; +}; + +struct axi_hdmi_encoder; + +struct axi_hdmi_private { + struct drm_device *drm_dev; + struct drm_crtc *crtc; + struct axi_hdmi_encoder *encoder; + struct i2c_client *encoder_slave; + + void __iomem *base; + + struct clk *hdmi_clock; + bool clk_enabled; + + struct dma_chan *dma; + + bool is_rgb; +}; + +struct drm_crtc* axi_hdmi_crtc_create(struct drm_device *dev); +struct drm_encoder *axi_hdmi_encoder_create(struct drm_device *dev); + +#endif diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_encoder.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_encoder.c new file mode 100644 index 0000000000000..4d33d4c3a07a9 --- /dev/null +++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_encoder.c @@ -0,0 +1,349 @@ +/* + * Analog Devices AXI HDMI DRM driver. + * + * Copyright 2012 Analog Devices Inc. + * Author: Lars-Peter Clausen + * + * Licensed under the GPL-2. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "axi_hdmi_drv.h" + +#define AXI_HDMI_STATUS_VMDA_UNDERFLOW BIT(4) +#define AXI_HDMI_STATUS_VMDA_OVERFLOW BIT(3) +#define AXI_HDMI_STATUS_VMDA_BE_ERROR BIT(2) +#define AXI_HDMI_STATUS_VMDA_TPM_OOS BIT(1) +#define AXI_HDMI_STATUS_HDMI_TPM_OOS BIT(0) + +#define AXI_HDMI_COLOR_PATTERN_ENABLE BIT(24) + +#define AXI_HDMI_REG_RESET 0x040 +#define AXI_HDMI_REG_CTRL 0x044 +#define AXI_HDMI_REG_SOURCE_SEL 0x048 +#define AXI_HDMI_REG_COLORPATTERN 0x04c +#define AXI_HDMI_REG_STATUS 0x05c +#define AXI_HDMI_REG_VDMA_STATUS 0x060 +#define AXI_HDMI_REG_TPM_STATUS 0x064 +#define AXI_HDMI_REG_CLIPP_MAX 0x068 +#define AXI_HDMI_REG_CLIPP_MIN 0x06c +#define AXI_HDMI_REG_HTIMING1 0x400 +#define AXI_HDMI_REG_HTIMING2 0x404 +#define AXI_HDMI_REG_HTIMING3 0x408 +#define AXI_HDMI_REG_VTIMING1 0x440 +#define AXI_HDMI_REG_VTIMING2 0x444 +#define AXI_HDMI_REG_VTIMING3 0x448 + +#define AXI_HDMI_RESET_ENABLE BIT(0) + +#define AXI_HDMI_CTRL_SS_BYPASS BIT(2) +#define AXI_HDMI_CTRL_FULL_RANGE BIT(1) +#define AXI_HDMI_CTRL_CSC_BYPASS BIT(0) + +#define AXI_HDMI_SOURCE_SEL_COLORPATTERN 0x3 +#define AXI_HDMI_SOURCE_SEL_TESTPATTERN 0x2 +#define AXI_HDMI_SOURCE_SEL_NORMAL 0x1 +#define AXI_HDMI_SOURCE_SEL_NONE 0x0 + +static const struct debugfs_reg32 axi_hdmi_encoder_debugfs_regs[] = { + { "Reset", AXI_HDMI_REG_RESET }, + { "Control", AXI_HDMI_REG_CTRL }, + { "Source select", AXI_HDMI_REG_SOURCE_SEL }, + { "Colorpattern", AXI_HDMI_REG_COLORPATTERN }, + { "Status", AXI_HDMI_REG_STATUS }, + { "VDMA status", AXI_HDMI_REG_VDMA_STATUS }, + { "TPM status", AXI_HDMI_REG_TPM_STATUS }, + { "HTiming1", AXI_HDMI_REG_HTIMING1 }, + { "HTiming2", AXI_HDMI_REG_HTIMING2 }, + { "HTiming3", AXI_HDMI_REG_HTIMING3 }, + { "VTiming1", AXI_HDMI_REG_VTIMING1 }, + { "VTiming2", AXI_HDMI_REG_VTIMING2 }, + { "VTiming3", AXI_HDMI_REG_VTIMING3 }, +}; + +static const uint16_t adv7511_csc_ycbcr_to_rgb[] = { + 0x0734, 0x04ad, 0x0000, 0x1c1b, + 0x1ddc, 0x04ad, 0x1f24, 0x0135, + 0x0000, 0x04ad, 0x087c, 0x1b77, +}; + +struct axi_hdmi_encoder { + struct drm_encoder_slave encoder; + struct drm_connector connector; + +#ifdef CONFIG_DEBUG_FS + struct debugfs_regset32 regset; +#endif +}; + +static inline struct axi_hdmi_encoder *to_axi_hdmi_encoder(struct drm_encoder *enc) +{ + return container_of(enc, struct axi_hdmi_encoder, encoder.base); +} + +static inline struct drm_encoder *connector_to_encoder(struct drm_connector *connector) +{ + struct axi_hdmi_encoder *enc = container_of(connector, struct axi_hdmi_encoder, connector); + return &enc->encoder.base; +} + +static void axi_hdmi_set_color_range(struct axi_hdmi_private *private, + unsigned int low, unsigned int high) +{ + writel(high, private->base + AXI_HDMI_REG_CLIPP_MAX); + writel(low, private->base + AXI_HDMI_REG_CLIPP_MIN); +} + +#ifdef CONFIG_DEBUG_FS + +static int axi_hdmi_debugfs_cp_get(void *data, u64 *val) +{ + struct axi_hdmi_private *private = data; + *val = readl(private->base + AXI_HDMI_REG_COLORPATTERN); + return 0; +} + +static int axi_hdmi_debugfs_cp_set(void *data, u64 val) +{ + struct axi_hdmi_private *private = data; + + writel(val, private->base + AXI_HDMI_REG_COLORPATTERN); + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(axi_hdmi_cp_fops, axi_hdmi_debugfs_cp_get, + axi_hdmi_debugfs_cp_set, "0x%06llx\n"); + +static const char * const axi_hdmi_mode_text[] = { + [AXI_HDMI_SOURCE_SEL_NONE] = "none", + [AXI_HDMI_SOURCE_SEL_NORMAL] = "normal", + [AXI_HDMI_SOURCE_SEL_TESTPATTERN] = "testpattern", + [AXI_HDMI_SOURCE_SEL_COLORPATTERN] = "colorpattern", +}; + +static ssize_t axi_hdmi_read_mode(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct axi_hdmi_private *private = file->private_data; + uint32_t src; + const char *fmt; + size_t len = 0; + char buf[50]; + int i; + + src = readl(private->base + AXI_HDMI_REG_SOURCE_SEL); + + for (i = 0; i < ARRAY_SIZE(axi_hdmi_mode_text); i++) { + if (src == i) + fmt = "[%s] "; + else + fmt = "%s "; + len += scnprintf(buf + len, sizeof(buf) - len, fmt, + axi_hdmi_mode_text[i]); + } + + buf[len - 1] = '\n'; + + return simple_read_from_buffer(userbuf, count, ppos, buf, len); +} + +static ssize_t axi_hdmi_set_mode(struct file *file, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct axi_hdmi_private *private = file->private_data; + char buf[20]; + unsigned int ctrl; + unsigned int i; + + count = min_t(size_t, count, sizeof(buf) - 1); + if (copy_from_user(buf, userbuf, count)) + return -EFAULT; + + buf[count] = '\0'; + + for (i = 0; i < ARRAY_SIZE(axi_hdmi_mode_text); i++) { + if (sysfs_streq(axi_hdmi_mode_text[i], buf)) + break; + } + + if (i == ARRAY_SIZE(axi_hdmi_mode_text)) + return -EINVAL; + + writel(i, private->base + AXI_HDMI_REG_SOURCE_SEL); + + if (i == AXI_HDMI_SOURCE_SEL_TESTPATTERN) { + axi_hdmi_set_color_range(private, 0, 0xffffff); + ctrl = AXI_HDMI_CTRL_CSC_BYPASS | AXI_HDMI_CTRL_SS_BYPASS | + AXI_HDMI_CTRL_FULL_RANGE; + } else { + if (private->is_rgb) { + axi_hdmi_set_color_range(private, 0, 0xffffff); + ctrl = AXI_HDMI_CTRL_CSC_BYPASS; + } else { + axi_hdmi_set_color_range(private, 0x101010, 0xf0ebf0); + ctrl = 0; + } + } + + writel(ctrl, private->base + AXI_HDMI_REG_CTRL); + + return count; +} + +static const struct file_operations axi_hdmi_mode_fops = { + .open = simple_open, + .read = axi_hdmi_read_mode, + .write = axi_hdmi_set_mode, +}; + +static void axi_hdmi_debugfs_init(struct axi_hdmi_encoder *encoder) +{ + struct axi_hdmi_private *priv = encoder->encoder.base.dev->dev_private; + + encoder->regset.base = priv->base; + encoder->regset.regs = axi_hdmi_encoder_debugfs_regs; + encoder->regset.nregs = ARRAY_SIZE(axi_hdmi_encoder_debugfs_regs); + + debugfs_create_regset32(dev_name(encoder->encoder.base.dev->dev), S_IRUGO, NULL, &encoder->regset); + debugfs_create_file("color_pattern", 0600, NULL, priv, &axi_hdmi_cp_fops); + debugfs_create_file("mode", 0600, NULL, priv, &axi_hdmi_mode_fops); +} + +#else + +static inline void axi_hdmi_debugfs_init(struct axi_hdmi_encoder *enc) +{ +} + +#endif + +static void axi_hdmi_encoder_enable(struct drm_encoder *encoder) +{ + struct axi_hdmi_private *private = encoder->dev->dev_private; + + /* if (!private->clk_enabled) { + clk_prepare_enable(private->hdmi_clock); + private->clk_enabled = true; + }*/ + writel(AXI_HDMI_RESET_ENABLE, private->base + AXI_HDMI_REG_RESET); +} + +static void axi_hdmi_encoder_disable(struct drm_encoder *encoder) +{ + struct axi_hdmi_private *private = encoder->dev->dev_private; + + writel(0, private->base + AXI_HDMI_REG_RESET); + if (private->clk_enabled) { + clk_disable_unprepare(private->hdmi_clock); + private->clk_enabled = false; + } +} + +static void axi_hdmi_encoder_mode_set(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct axi_hdmi_private *private = encoder->dev->dev_private; + struct drm_display_mode *mode = &crtc_state->mode; + unsigned int h_de_min, h_de_max; + unsigned int v_de_min, v_de_max; + unsigned int val; + + h_de_min = mode->htotal - mode->hsync_start; + h_de_max = h_de_min + mode->hdisplay; + v_de_min = mode->vtotal - mode->vsync_start; + v_de_max = v_de_min + mode->vdisplay; + + val = (mode->hdisplay << 16) | mode->htotal; + writel(val, private->base + AXI_HDMI_REG_HTIMING1); + val = mode->hsync_end - mode->hsync_start; + writel(val, private->base + AXI_HDMI_REG_HTIMING2); + val = (h_de_max << 16) | h_de_min; + writel(val, private->base + AXI_HDMI_REG_HTIMING3); + + val = (mode->vdisplay << 16) | mode->vtotal; + writel(val, private->base + AXI_HDMI_REG_VTIMING1); + val = mode->vsync_end - mode->vsync_start; + writel(val, private->base + AXI_HDMI_REG_VTIMING2); + val = (v_de_max << 16) | v_de_min; + writel(val, private->base + AXI_HDMI_REG_VTIMING3); + + clk_set_rate(private->hdmi_clock, mode->clock * 1000); +} + +static const struct drm_encoder_helper_funcs axi_hdmi_encoder_helper_funcs = { + .enable = axi_hdmi_encoder_enable, + .disable = axi_hdmi_encoder_disable, + .atomic_mode_set = axi_hdmi_encoder_mode_set, +}; + +static void axi_hdmi_encoder_destroy(struct drm_encoder *encoder) +{ + struct axi_hdmi_encoder *axi_hdmi_encoder = + to_axi_hdmi_encoder(encoder); + + drm_encoder_cleanup(encoder); + kfree(axi_hdmi_encoder); +} + +static const struct drm_encoder_funcs axi_hdmi_encoder_funcs = { + .destroy = axi_hdmi_encoder_destroy, +}; + +struct drm_encoder *axi_hdmi_encoder_create(struct drm_device *dev) +{ + struct drm_encoder *encoder; + struct axi_hdmi_encoder *axi_hdmi_encoder; + struct axi_hdmi_private *priv = dev->dev_private; + struct drm_bridge *bridge; + int ret; + + axi_hdmi_encoder = kzalloc(sizeof(*axi_hdmi_encoder), GFP_KERNEL); + if (!axi_hdmi_encoder) + return NULL; + encoder = &axi_hdmi_encoder->encoder.base; + encoder->possible_crtcs = 1; + drm_encoder_init(dev, encoder, &axi_hdmi_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + drm_encoder_helper_add(encoder, &axi_hdmi_encoder_helper_funcs); + bridge = of_drm_find_bridge(priv->encoder_slave->dev.of_node); + if (bridge) { + bridge->encoder = encoder; + /* + * Check if we really need to create th drm_connector. + * If not, DRM_BRIDGE_ATTACH_NO_CONNECTOR can be passed instead + * 0 + */ + ret = drm_bridge_attach(encoder, bridge, NULL, 0); + if (ret) { + drm_encoder_cleanup(encoder); + return NULL; + } + } + + axi_hdmi_debugfs_init(axi_hdmi_encoder); + writel(AXI_HDMI_SOURCE_SEL_NORMAL, priv->base + AXI_HDMI_REG_SOURCE_SEL); + if (priv->is_rgb) { + writel(AXI_HDMI_CTRL_CSC_BYPASS, priv->base + AXI_HDMI_REG_CTRL); + axi_hdmi_set_color_range(priv, 0, 0xffffff); + } else { + axi_hdmi_set_color_range(priv, 0x101010, 0xf0ebf0); + } + return encoder; +} diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 76e46713b2f0c..c3b3b3cd895ea 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -2031,7 +2031,6 @@ int drm_fb_helper_initial_config(struct drm_fb_helper *fb_helper, int bpp_sel) if (!drm_fbdev_emulation) return 0; - mutex_lock(&fb_helper->lock); ret = __drm_fb_helper_initial_config_and_unlock(fb_helper, bpp_sel); @@ -2066,7 +2065,6 @@ int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper) if (!drm_fbdev_emulation || !fb_helper) return 0; - mutex_lock(&fb_helper->lock); if (fb_helper->deferred_setup) { err = __drm_fb_helper_initial_config_and_unlock(fb_helper,