From 18b9132e9040520260dcc142400195484c8dbe2a Mon Sep 17 00:00:00 2001 From: Anderson Ignacio da Silva Date: Tue, 18 Jun 2024 20:30:09 +0100 Subject: [PATCH] Cleanup on monitor.py and double SRAM size to get errors while running the test Signed-off-by: Anderson Ignacio da Silva --- cocotbext/ahb/ahb_master.py | 6 +- cocotbext/ahb/utils.py | 2 +- monitor.py | 169 ------------------------------------ noxfile.py | 12 +-- ship.sh | 2 +- tests/test_ahb_lite_sram.py | 4 +- 6 files changed, 13 insertions(+), 182 deletions(-) delete mode 100644 monitor.py diff --git a/cocotbext/ahb/ahb_master.py b/cocotbext/ahb/ahb_master.py index e7c2af0..6fba13a 100644 --- a/cocotbext/ahb/ahb_master.py +++ b/cocotbext/ahb/ahb_master.py @@ -4,10 +4,10 @@ # License : MIT license # Author : Anderson I. da Silva (aignacio) # Date : 08.10.2023 -# Last Modified Date: 15.06.2024 +# Last Modified Date: 18.06.2024 -import cocotb import logging +import cocotb import copy import datetime @@ -186,7 +186,7 @@ async def _send_txn( f"AHB {op} txn:\n" f"\tID = {index}\n" f"\tADDR = 0x{txn_addr:x}\n" - f"\tDATA = 0x{value[index+1]:x}\n" + f"\tDATA = 0x{value[index + 1]:x}\n" f"\tSIZE = {txn_size} bytes" ) self.bus.hwdata.value = txn_data diff --git a/cocotbext/ahb/utils.py b/cocotbext/ahb/utils.py index c0095ed..75d30ea 100644 --- a/cocotbext/ahb/utils.py +++ b/cocotbext/ahb/utils.py @@ -29,7 +29,7 @@ def hexdump_line(data, offset, row_size=16): for ch in data[0:row_size]: h += f"{ch:02x} " c += chr(ch) if 32 < ch < 127 else "." - return f"{offset:08x}: {h:{row_size*3}} {c}" + return f"{offset:08x}: {h:{row_size * 3}} {c}" def hexdump(data, start=0, length=None, row_size=16, prefix="", offset=0): diff --git a/monitor.py b/monitor.py deleted file mode 100644 index 8cbd604..0000000 --- a/monitor.py +++ /dev/null @@ -1,169 +0,0 @@ -#!/usr/bin/env python3 -# -*- coding: utf-8 -*- -# File : ahb_monitor.py -# License : MIT license -# Author : Anderson I. da Silva (aignacio) -# Date : 27.10.2023 -# Last Modified Date: 10.06.2024 -import cocotb -import logging -import random -import copy -import datetime - -from .ahb_types import AHBTrans, AHBWrite, AHBSize, AHBResp -from .ahb_bus import AHBBus -from .version import __version__ - -from cocotb.triggers import RisingEdge, FallingEdge -from cocotb.handle import SimHandleBase -from cocotb.types import LogicArray -from cocotb.binary import BinaryValue -from cocotb_bus.monitors import Monitor -from typing import Optional, Union, Generator, List, Any -from .memory import Memory - - -class AHBMonitor(Monitor): - def __init__( - self, bus: AHBBus, clock: str, reset: str, prefix: str = None, **kwargs: Any - ) -> None: - name = prefix if prefix is not None else bus.entity._name + "_ahb_monitor" - - self.clk = clock - self.rst = reset - self.bus = bus - - # We extend from Monitor base class because we don't need to recreate - # the internal bus property as it already exists from AHBBus - Monitor.__init__(self, **kwargs) - - self.log.info(f"AHB ({name}) Monitor") - self.log.info("cocotbext-ahb version %s", __version__) - self.log.info( - f"Copyright (c) {datetime.datetime.now().year} Anderson Ignacio da Silva" - ) - self.log.info("https://github.com/aignacio/cocotbext-ahb") - - async def _monitor_recv(self): - """Watch the pins and reconstruct transactions.""" - - pending = False - stable_signals = {} - - while True: - curr_hready = copy.deepcopy(self.bus.hready.value) - - await FallingEdge(self.clk) - - if (self.bus.hready == 1) and self.bus.hresp == AHBResp.ERROR: - if curr_hready != 0: - raise AssertionError( - "AHB PROTOCOL VIOLATION: Previous hready must be low when AHB Resp == Error and hready == 1" - ) - - # print(f"pending: {pending}") - # Ensure master does not change its qualifiers before hready - if (pending is True) and (self.bus.hready.value == 0): - self._check_signals(stable_signals) - elif (pending is True) and (self.bus.hready.value == 1): - self._check_signals(stable_signals) - pending = False - self._recv(stable_signals) - - # Check for new txn - # print(f"hready: {self.bus.hready.value}") - # print(f"check inputs: {self._check_inputs()}") - # print(f"check valid_tx: {self._check_valid_txn()}") - if ( - self.bus.hready.value == 0 - and self._check_inputs() - and self._check_valid_txn() - ): - pending = True - stable_signals = { - "htrans": copy.deepcopy(self.bus.htrans.value), - "hwrite": copy.deepcopy(self.bus.hwrite.value), - "haddr": copy.deepcopy(self.bus.haddr.value), - "hsize": copy.deepcopy(self.bus.hsize.value), - } - if self.bus.hsel_exist: - stable_signals["hsel"] = copy.deepcopy(self.bus.hsel.value) - else: - pending = False - - def _check_inputs(self) -> bool: - """Check any of the master signals are resolvable (i.e not 'z')""" - signals = { - "htrans": self.bus.htrans, - "hwrite": self.bus.hwrite, - "haddr": self.bus.haddr, - "hsize": self.bus.hsize, - } - - if self.bus.hsel_exist: - signals["hsel"] = self.bus.hsel - - if self.bus.hready_in_exist: - signals["hready_in"] = self.bus.hready_in - - for var, val in signals.items(): - if val.value.is_resolvable is False: - # self.log.warn(f"{var} is not resolvable") - return False - return True - - def _check_valid_txn(self) -> bool: - htrans_st = (AHBTrans(self.bus.htrans.value) != AHBTrans.IDLE) and ( - AHBTrans(self.bus.htrans.value) != AHBTrans.BUSY - ) - - if self.bus.hsel_exist: - if self.bus.hready_in_exist: - if ( - (self.bus.hsel.value == 1) - and (self.bus.hready_in.value == 1) - and htrans_st - ): - return True - else: - return False - else: - if (self.bus.hsel.value == 1) and htrans_st: - return True - else: - return False - else: - if htrans_st: - return True - else: - return False - - def _check_signals(self, stable): - """Check any of the master signals are resolvable (i.e not 'z')""" - if self.bus.hsel_exist: - current = { - "hsel": self.bus.hsel, - "htrans": self.bus.htrans, - "hwrite": self.bus.hwrite, - "haddr": self.bus.haddr, - "hsize": self.bus.hsize, - } - else: - current = { - "htrans": self.bus.htrans, - "hwrite": self.bus.hwrite, - "haddr": self.bus.haddr, - "hsize": self.bus.hsize, - } - - for signal in current: - if current[signal].value.is_resolvable is not True: - raise AssertionError(f"Signal master.{signal} is not resolvable!") - if current[signal].value != stable[signal]: - if (signal == "htrans") and (self.bus.hresp.value == AHBResp.ERROR): - pass - else: - raise AssertionError( - f"AHB PROTOCOL VIOLATION: Master.{signal} signal should not change before slave.hready == 1" - ) diff --git a/noxfile.py b/noxfile.py index 9aaa3c7..42e3261 100644 --- a/noxfile.py +++ b/noxfile.py @@ -4,12 +4,12 @@ # License : MIT license # Author : Anderson I. da Silva (aignacio) # Date : 08.10.2023 -# Last Modified Date: 14.06.2024 +# Last Modified Date: 18.06.2024 import nox -@nox.session(python=["3.6", "3.7", "3.8", "3.9", "3.10"], reuse_venv=True) +@nox.session(python=["3.6", "3.7", "3.8", "3.9", "3.10", "3.11", "3.12"], reuse_venv=True) def run(session): session.env["DUT"] = "ahb_template" session.env["SIM"] = "icarus" @@ -23,9 +23,9 @@ def run(session): "pytest-sugar", "pytest-cov", "pytest-split", - "cocotb-bus == 0.2.1", - "cocotb-test == 0.2.4", - "cocotb >= 1.8.0", + "cocotb-bus==0.2.1", + "cocotb-test==0.2.4", + "cocotb>=1.8.0" ) session.install("-e", ".") session.run( @@ -41,7 +41,7 @@ def run(session): ) -@nox.session(python=["3.9", "3.10"]) +@nox.session(python=["3.9", "3.10", "3.11", "3.12"], reuse_venv=True) def lint(session): session.install("flake8") session.run("flake8") diff --git a/ship.sh b/ship.sh index 7711525..5def786 100755 --- a/ship.sh +++ b/ship.sh @@ -1,2 +1,2 @@ #!/bin/bash -docker run -it --rm -v $(pwd):/cocotbext-ahb/ -w /cocotbext-ahb/ aignacio/rtldev bash +docker run -it --rm -v $(pwd):/cocotbext-ahb/ -w /cocotbext-ahb/ aignacio/icarus bash diff --git a/tests/test_ahb_lite_sram.py b/tests/test_ahb_lite_sram.py index ae0a103..f5fd4f7 100644 --- a/tests/test_ahb_lite_sram.py +++ b/tests/test_ahb_lite_sram.py @@ -3,7 +3,7 @@ # License : MIT license # Author : Anderson I. da Silva (aignacio) # Date : 08.10.2023 -# Last Modified Date: 16.06.2024 +# Last Modified Date: 18.06.2024 import cocotb import os @@ -94,7 +94,7 @@ async def run_test(dut, bp_fn=None, pip_mode=False): # Generate a list of unique addresses with the double of memory size # to create error responses - address = random.sample(range(0, 1 * mem_size_kib * 1024, 8), N) + address = random.sample(range(0, 2 * mem_size_kib * 1024, 8), N) # Generate a list of random 32-bit values value = [rnd_val(data_width) for _ in range(N)] # Generate a list of random sizes