From 5a53212bc05094aa499408af100834e03821f503 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Thu, 18 Jul 2024 16:20:15 +0200 Subject: [PATCH] Initial VAY draft Signed-off-by: Claire Xenia Wolf --- Makefile | 30 +++++++++---- kernel/rtlil.h | 119 +++++++++++++++++++++++++++++++++++++++++++++---- kernel/yosys.h | 12 +++++ 3 files changed, 144 insertions(+), 17 deletions(-) diff --git a/Makefile b/Makefile index 0ccdbe2c959..ae3d8d7907c 100644 --- a/Makefile +++ b/Makefile @@ -25,6 +25,9 @@ ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_ZLIB := 1 +# enable virtual APIs, create "vay" executable instead of "yosys" +ENABLE_VIRTUAL_APIS := 0 + # python wrappers ENABLE_PYOSYS := 0 @@ -77,7 +80,11 @@ OBJS = GENFILES = EXTRA_OBJS = EXTRA_TARGETS = +ifeq ($(ENABLE_VIRTUAL_APIS),1) +TARGETS = $(PROGRAM_PREFIX)vay$(EXE) $(PROGRAM_PREFIX)vay-config +else TARGETS = $(PROGRAM_PREFIX)yosys$(EXE) $(PROGRAM_PREFIX)yosys-config +endif PRETTY = 1 SMALL = 0 @@ -101,6 +108,9 @@ EXE_LDFLAGS := -Wl,--export-all-symbols -Wl,--out-implib,libyosys_exe.a PLUGIN_LDFLAGS += -L"$(LIBDIR)" PLUGIN_LDLIBS := -lyosys_exe endif +ifeq ($(ENABLE_VIRTUAL_APIS),1) +CXXFLAGS := $(CXXFLAGS) -D_YOSYS_VAY_ +endif PKG_CONFIG ?= pkg-config SED ?= sed @@ -376,8 +386,12 @@ $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, emcc, mxe, endif ifeq ($(ENABLE_LIBYOSYS),1) +ifeq ($(ENABLE_VIRTUAL_APIS,1) +TARGETS += libvay.so +else TARGETS += libyosys.so endif +endif ifeq ($(ENABLE_PYOSYS),1) # Detect name of boost_python library. Some distros use boost_python-py, other boost_python, some only use the major version number, some a concatenation of major and minor version numbers @@ -750,14 +764,14 @@ ifeq ($(CONFIG),emcc) yosys.js: $(filter-out yosysjs-$(YOSYS_VER).zip,$(EXTRA_TARGETS)) endif -$(PROGRAM_PREFIX)yosys$(EXE): $(OBJS) - $(P) $(LD) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LDFLAGS) $(LDFLAGS) $(OBJS) $(LDLIBS) $(LDLIBS_VERIFIC) +$(PROGRAM_PREFIX)yosys$(EXE) $(PROGRAM_PREFIX)vay$(EXE): $(OBJS) + $(P) $(LD) -o $@ $(EXE_LDFLAGS) $(LDFLAGS) $(OBJS) $(LDLIBS) $(LDLIBS_VERIFIC) -libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) +libyosys.so libvay.so: $(filter-out kernel/driver.o,$(OBJS)) ifeq ($(OS), Darwin) - $(P) $(LD) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC) + $(P) $(LD) -o $@ -shared -Wl,-install_name,$(LIBDIR)/$@ $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC) else - $(P) $(LD) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC) + $(P) $(LD) -o $@ -shared -Wl,-soname,$(LIBDIR)/$@ $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC) endif %.o: %.cc @@ -793,11 +807,11 @@ CXXFLAGS_NOVERIFIC = $(CXXFLAGS) LDLIBS_NOVERIFIC = $(LDLIBS) endif -$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in +$(PROGRAM_PREFIX)yosys-config $(PROGRAM_PREFIX)vay-config: misc/yosys-config.in $(P) $(SED) -e 's#@CXXFLAGS@#$(subst -Ilibs/dlfcn-win32,,$(subst -I. -I"$(YOSYS_SRC)",-I"$(DATDIR)/include",$(strip $(CXXFLAGS_NOVERIFIC))))#;' \ -e 's#@CXX@#$(strip $(CXX))#;' -e 's#@LDFLAGS@#$(strip $(LDFLAGS) $(PLUGIN_LDFLAGS))#;' -e 's#@LDLIBS@#$(strip $(LDLIBS_NOVERIFIC) $(PLUGIN_LDLIBS))#;' \ - -e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config - $(Q) chmod +x $(PROGRAM_PREFIX)yosys-config + -e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $@ + $(Q) chmod +x $@ abc/abc-$(ABCREV)$(EXE) abc/libabc-$(ABCREV).a: $(P) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 928bc044049..584725288a7 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -74,6 +74,14 @@ namespace RTLIL struct Process; struct Binding; +#ifdef _YOSYS_VAY_ + struct CoarseCell; // same as Cell in a NOVAY build + struct FineCell; // only single-bit ports and no parameters + struct AYFineCell; // cell with single-bit ports "A" and "Y" and no parameters + struct ABYFineCell; // cell with single-bit ports "A", "B", and "Y" and no parameters + // ... +#endif + typedef std::pair SigSig; struct IdString @@ -1155,6 +1163,10 @@ struct RTLIL::Design #ifdef WITH_PYTHON static std::map *get_all_designs(void); #endif + + // Memory profiling API + int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const; }; struct RTLIL::Module : public RTLIL::AttrObject @@ -1497,6 +1509,10 @@ struct RTLIL::Module : public RTLIL::AttrObject #ifdef WITH_PYTHON static std::map *get_all_modules(void); #endif + + // Memory profiling API + int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const; }; struct RTLIL::Wire : public RTLIL::AttrObject @@ -1523,6 +1539,10 @@ struct RTLIL::Wire : public RTLIL::AttrObject #ifdef WITH_PYTHON static std::map *get_all_wires(void); #endif + + // Memory profiling API + int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const; }; inline int GetSize(RTLIL::Wire *wire) { @@ -1546,23 +1566,46 @@ struct RTLIL::Memory : public RTLIL::AttrObject struct RTLIL::Cell : public RTLIL::AttrObject { - unsigned int hashidx_; - unsigned int hash() const { return hashidx_; } + // do not simply copy cells + Cell(RTLIL::Cell &other) = delete; + void operator=(RTLIL::Cell &other) = delete; protected: // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; Cell(); - ~Cell(); + YS_VAY_VIRTUAL ~Cell(); public: - // do not simply copy cells - Cell(RTLIL::Cell &other) = delete; - void operator=(RTLIL::Cell &other) = delete; - RTLIL::Module *module; RTLIL::IdString name; RTLIL::IdString type; + +#ifdef _YOSYS_VAY_ + // Virtual Coarse Cell API (abstract) + virtual RTLIL::SigSpec getPort(const RTLIL::IdString &portname) const = 0; + //... + + // Virtual Fine Cell API (with default implementations) + virtual RTLIL::SigBit getPortBit(const RTLIL::IdString &portname) const { return getPort(portname).as_bit(); } + ///... + + // Virtual Compact Cell API (with default implementations) + virtual RTLIL::SigSpec getPortA() const { return getPort(ID::A); } + virtual RTLIL::SigBit getPortBitA() const { return getPort(ID::A).as_bit(); } + ///... + + // Memory profiling API + virtual int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const = 0; +}; + +struct RTLIL::CoarseCell final : public RTLIL::Cell +{ +#endif + unsigned int hashidx_; + unsigned int hash() const { return hashidx_; } + dict connections_; dict parameters; @@ -1570,8 +1613,8 @@ struct RTLIL::Cell : public RTLIL::AttrObject bool hasPort(const RTLIL::IdString &portname) const; void unsetPort(const RTLIL::IdString &portname); void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal); - const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const; - const dict &connections() const; + YS_NOVAY_CONSTREF(RTLIL::SigSpec) getPort(const RTLIL::IdString &portname) const; + YS_NOVAY_CONSTREF(dict) connections() const; // information about cell ports bool known() const; @@ -1602,8 +1645,66 @@ struct RTLIL::Cell : public RTLIL::AttrObject bool has_memid() const; bool is_mem_cell() const; + + // Memory profiling API + int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const; }; +#ifdef _YOSYS_VAY_ +struct RTLIL::FineCell final : public RTLIL::Cell +{ + dict connections_; + + //... + + // Memory profiling API + int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const; +}; + +struct RTLIL::AYFineCell final : public RTLIL::Cell +{ + SigBit portA_, portY_; + + virtual RTLIL::SigSpec getPort(const RTLIL::IdString &portname) const { + if (portname == ID::A) return portA_; + if (portname == ID::Y) return portY_; + log_abort(); + } + //... + RTLIL::SigSpec getPortA() const { return portA_; } + RTLIL::SigBit getPortBitA() const { return portA_; } + //... + + // Memory profiling API + int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const; +}; + +struct RTLIL::ABYFineCell final : public RTLIL::Cell +{ + SigBit portA_, portB_, portY_; + + virtual RTLIL::SigSpec getPort(const RTLIL::IdString &portname) const { + if (portname == ID::A) return portA_; + if (portname == ID::B) return portB_; + if (portname == ID::Y) return portY_; + log_abort(); + } + //... + RTLIL::SigSpec getPortA() const { return portA_; } + RTLIL::SigBit getPortBitA() const { return portA_; } + //... + + // Memory profiling API + int getAllocations(std::vector tags, + std::vector>> *allocsPtr = nullptr) const; +}; + +//... +#endif + struct RTLIL::CaseRule : public RTLIL::AttrObject { std::vector compare; diff --git a/kernel/yosys.h b/kernel/yosys.h index 97a79861e15..f4742374fee 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -166,6 +166,18 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p # define YS_FALLTHROUGH #endif +#define YS_COMMA , + +#ifdef _YOSYS_VAY_ +# define YS_VAY_VIRTUAL virtual +# define YS_VAY_ABSTRACT = 0 +# define YS_NOVAY_CONSTREF(type) type +#else +# define YS_VAY_VIRTUAL +# define YS_VAY_ABSTRACT +# define YS_NOVAY_CONSTREF(type) const type & +#endif + YOSYS_NAMESPACE_BEGIN // Note: All headers included in hashlib.h must be included