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Start adding RFB simulation models
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@mmicko
mmicko committed May 20, 2024
1 parent f047e0a commit 36e6766
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103 changes: 0 additions & 103 deletions techlibs/nanoxplore/cells_bb_u.v
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Original file line number Diff line number Diff line change
Expand Up @@ -2338,109 +2338,6 @@ module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, D
parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
endmodule

(* blackbox *)
module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
, WA2, WA3, WA4, WA5, WA6, WE, WEA);
input I1;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I17;
input I18;
input I19;
input I2;
input I20;
input I21;
input I22;
input I23;
input I24;
input I25;
input I26;
input I27;
input I28;
input I29;
input I3;
input I30;
input I31;
input I32;
input I33;
input I34;
input I35;
input I36;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
output O1;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O17;
output O18;
output O19;
output O2;
output O20;
output O21;
output O22;
output O23;
output O24;
output O25;
output O26;
output O27;
output O28;
output O29;
output O3;
output O30;
output O31;
output O32;
output O33;
output O34;
output O35;
output O36;
output O4;
output O5;
output O6;
output O7;
output O8;
output O9;
input RA1;
input RA10;
input RA2;
input RA3;
input RA4;
input RA5;
input RA6;
input RA7;
input RA8;
input RA9;
input WA1;
input WA2;
input WA3;
input WA4;
input WA5;
input WA6;
input WCK;
input WE;
input WEA;
parameter mem_ctxt = "";
parameter mode = 0;
parameter wck_edge = 1'b0;
endmodule


(* blackbox *)
module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
Expand Down
202 changes: 202 additions & 0 deletions techlibs/nanoxplore/cells_sim_u.v
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Expand Up @@ -28,3 +28,205 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
endgenerate
assign SO = inv_out ? ~SO_int : SO_int;
endmodule

(* abc9_box, lib_whitebox *)
module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
, WA2, WA3, WA4, WA5, WA6, WE, WEA);
input I1;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I17;
input I18;
input I19;
input I2;
input I20;
input I21;
input I22;
input I23;
input I24;
input I25;
input I26;
input I27;
input I28;
input I29;
input I3;
input I30;
input I31;
input I32;
input I33;
input I34;
input I35;
input I36;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
output O1;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O17;
output O18;
output O19;
output O2;
output O20;
output O21;
output O22;
output O23;
output O24;
output O25;
output O26;
output O27;
output O28;
output O29;
output O3;
output O30;
output O31;
output O32;
output O33;
output O34;
output O35;
output O36;
output O4;
output O5;
output O6;
output O7;
output O8;
output O9;
input RA1;
input RA10;
input RA2;
input RA3;
input RA4;
input RA5;
input RA6;
input RA7;
input RA8;
input RA9;
input WA1;
input WA2;
input WA3;
input WA4;
input WA5;
input WA6;
input WCK;
input WE;
input WEA;
parameter mem_ctxt = "";
parameter mode = 0;
parameter wck_edge = 1'b0;

wire clock = WCK ^ wck_edge;

generate
if (mode==0) begin
reg [17:0] mem [31:0];

integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = 18'b0;
end
wire [4:0] WA = { WA5, WA4, WA3, WA2, WA1 };
wire [4:0] RA = { RA5, RA4, RA3, RA2, RA1 };
wire [17:0] I = { I18, I17, I16, I15, I14, I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1 };

always @(posedge clock)
if (WE)
mem[WA] <= I;

assign { O18, O17, O16, O15, O14, O13, O12, O11, O10, O9, O8, O7, O6, O5, O4, O3, O2, O1 } = mem[RA];
end
else if (mode==1) begin
reg [17:0] mem [31:0];

integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = 18'b0;
end
wire [4:0] WA = { WA5, WA4, WA3, WA2, WA1 };
wire [4:0] RA = { WA5, WA4, WA3, WA2, WA1 };
wire [17:0] I = { I18, I17, I16, I15, I14, I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1 };

always @(posedge clock)
if (WE)
mem[WA] <= I;

assign { O18, O17, O16, O15, O14, O13, O12, O11, O10, O9, O8, O7, O6, O5, O4, O3, O2, O1 } = mem[RA];
end
else if (mode==2) begin
reg [17:0] mem [63:0];

integer i;
initial begin
for (i = 0; i < 63; i = i + 1)
mem[i] = 18'b0;
end
wire [5:0] WA = { WA6, WA5, WA4, WA3, WA2, WA1 };
wire [5:0] RA = { RA6, RA5, RA4, RA3, RA2, RA1 };
wire [17:0] I = { I18, I17, I16, I15, I14, I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1 };

always @(posedge clock)
if (WE)
mem[WA] <= I;

assign { O18, O17, O16, O15, O14, O13, O12, O11, O10, O9, O8, O7, O6, O5, O4, O3, O2, O1 } = mem[RA];
end
else if (mode==3) begin
reg [35:0] mem [31:0];

integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = 36'b0;
end

wire [4:0] WA = { WA5, WA4, WA3, WA2, WA1 };
wire [4:0] RA = { RA5, RA4, RA3, RA2, RA1 };
wire [35:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28, I27, I26, I25, I24, I23, I22, I21, I20, I19, I18, I17, I16, I15, I14, I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1 };

always @(posedge clock)
if (WE)
mem[WA] <= I;

assign { O36, O35, O34, O33, O32, O31, O30, O29, O28, O27, O26, O25, O24, O23, O22, O21, O20, O19, O18, O17, O16, O15, O14, O13, O12, O11, O10, O9, O8, O7, O6, O5, O4, O3, O2, O1 } = mem[RA];
end
else if (mode==4) begin
reg [17:0] mem [31:0];

integer i;
initial begin
for (i = 0; i < 31; i = i + 1)
mem[i] = 0;
end
wire [4:0] WA = { WA5, WA4, WA3, WA2, WA1 };
wire [4:0] RA_A = { RA5, RA4, RA3, RA2, RA1 };
wire [4:0] RA_B = { RA10, RA9, RA8, RA7, RA6 };
wire [17:0] I = { I18, I17, I16, I15, I14, I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1 };

always @(posedge clock)
if (WE)
mem[WA] <= I;

assign { O18, O17, O16, O15, O14, O13, O12, O11, O10, O9, O8, O7, O6, O5, O4, O3, O2, O1 } = mem[RA_A];
assign { O36, O35, O34, O33, O32, O31, O30, O29, O28, O27, O26, O25, O24, O23, O22, O21, O20, O19} = mem[RA_B];
end
else
$error("Unknown NX_RFB_U mode");
endgenerate
endmodule
6 changes: 3 additions & 3 deletions techlibs/nanoxplore/rf_rams_u.txt
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Expand Up @@ -7,7 +7,7 @@

ram distributed $__NX_RFB_U_DPREG_ {
option "MODE" 0 {
cost 35;
cost 30;
widthscale 30;
abits 5;
widths 18 global;
Expand Down Expand Up @@ -53,8 +53,8 @@ ram distributed $__NX_RFB_U_SPREG_ {
# NX_RFB_U in mode 4 (NX_XRFB_2R_1W)

ram distributed $__NX_XRFB_2R_1W_ {
cost 30;
widthscale;
cost 40;
widthscale 30;
abits 5;
width 18;
init no_undef;
Expand Down
2 changes: 1 addition & 1 deletion tests/arch/nanoxplore/fsm.ys
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Expand Up @@ -12,5 +12,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd fsm # Constrain all select calls below inside the top module

select -assert-count 6 t:NX_DFF
select -assert-count 14 t:NX_LUT
select -assert-min 13 t:NX_LUT
select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
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