From 38d171d0dd2db2eb6dd4a197509815cbd67f9848 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 2 Oct 2024 12:34:54 +1300 Subject: [PATCH 01/11] B extension starts with Zba - Update `insn_shimm` and `insn_alu` to support unsigned words (`uwmode`). This is used when the result is of width XLEN but the lower 32 bits from one of the inputs (rs1) is zero-extended. - Update `isa_propagate` to match multi-letter extensions e.g. `Zba`. - Add Zba instructions and the beginnings of the rest of the B extension. --- insns/generate.py | 80 +- insns/insn_add_uw.v | 59 + insns/insn_sh1add.v | 59 + insns/insn_sh1add_uw.v | 59 + insns/insn_sh2add.v | 59 + insns/insn_sh2add_uw.v | 59 + insns/insn_sh3add.v | 59 + insns/insn_sh3add_uw.v | 59 + insns/insn_slli_uw.v | 59 + insns/isa_rv32iZba.txt | 40 + insns/isa_rv32iZba.v | 2081 ++++++++++++++++++++++++++++ insns/isa_rv32ib.txt | 40 + insns/isa_rv32ib.v | 2081 ++++++++++++++++++++++++++++ insns/isa_rv64iZba.txt | 57 + insns/isa_rv64iZba.v | 2948 ++++++++++++++++++++++++++++++++++++++++ insns/isa_rv64ib.txt | 57 + insns/isa_rv64ib.v | 2948 ++++++++++++++++++++++++++++++++++++++++ 17 files changed, 10793 insertions(+), 11 deletions(-) create mode 100644 insns/insn_add_uw.v create mode 100644 insns/insn_sh1add.v create mode 100644 insns/insn_sh1add_uw.v create mode 100644 insns/insn_sh2add.v create mode 100644 insns/insn_sh2add_uw.v create mode 100644 insns/insn_sh3add.v create mode 100644 insns/insn_sh3add_uw.v create mode 100644 insns/insn_slli_uw.v create mode 100644 insns/isa_rv32iZba.txt create mode 100644 insns/isa_rv32iZba.v create mode 100644 insns/isa_rv32ib.txt create mode 100644 insns/isa_rv32ib.v create mode 100644 insns/isa_rv64iZba.txt create mode 100644 insns/isa_rv64iZba.v create mode 100644 insns/isa_rv64ib.txt create mode 100644 insns/isa_rv64ib.v diff --git a/insns/generate.py b/insns/generate.py index e0de0ea2..8f4f9b6d 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -14,12 +14,14 @@ # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +import re + current_isa = [] isa_database = dict() defaults_cache = None MISA_A = 1 << 0 # Atomic -MISA_B = 1 << 1 # -reserved- +MISA_B = 1 << 1 # Bit manipulation MISA_C = 1 << 2 # Compressed MISA_D = 1 << 3 # Double-precision float MISA_E = 1 << 4 # RV32E base ISA @@ -579,13 +581,18 @@ def insn_imm(insn, funct3, expr, wmode=False, misa=0): footer(f) -def insn_shimm(insn, funct6, funct3, expr, wmode=False, misa=0): +def insn_shimm(insn, funct6, funct3, expr, wmode=False, uwmode=False, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_i_shift(f) misa_check(f, misa) - if wmode: + if uwmode: + assert not wmode + xtra_shamt_check = "1" + result_range = "`RISCV_FORMAL_XLEN-1:0" + opcode = "0011011" + elif wmode: xtra_shamt_check = "!insn_shamt[5]" result_range = "31:0" opcode = "0011011" @@ -608,13 +615,17 @@ def insn_shimm(insn, funct6, funct3, expr, wmode=False, misa=0): footer(f) -def insn_alu(insn, funct7, funct3, expr, alt_add=None, alt_sub=None, shamt=False, wmode=False, misa=0): +def insn_alu(insn, funct7, funct3, expr, alt_add=None, alt_sub=None, shamt=False, wmode=False, uwmode=False, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_r(f) misa_check(f, misa) - if wmode: + if uwmode: + assert not wmode + result_range = "`RISCV_FORMAL_XLEN-1:0" + opcode = "0111011" + elif wmode: result_range = "31:0" opcode = "0111011" else: @@ -1238,6 +1249,37 @@ def insn_c_mvadd(insn, funct4, add, misa=MISA_C): # insn_amo("amominu_d", "11000", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : (rvfi_mem_rdata < rvfi_rs2_rdata[63:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])") # insn_amo("amomaxu_d", "11100", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : (rvfi_mem_rdata > rvfi_rs2_rdata[63:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])") +## Bit Manipulation ISA (B) + +### Zba: Address generation + +current_isa = ["rv32iZba"] + +insn_alu("sh1add", "0010000", "010", "rvfi_rs2_rdata + (rvfi_rs1_rdata << 1)", misa=MISA_B) +insn_alu("sh2add", "0010000", "100", "rvfi_rs2_rdata + (rvfi_rs1_rdata << 2)", misa=MISA_B) +insn_alu("sh3add", "0010000", "110", "rvfi_rs2_rdata + (rvfi_rs1_rdata << 3)", misa=MISA_B) + +current_isa = ["rv64iZba"] + +insn_alu("add_uw", "0000100", "000", "rvfi_rs2_rdata + rvfi_rs1_rdata[31:0]", uwmode=True, misa=MISA_B) +insn_alu("sh1add_uw", "0010000", "010", "rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 1)", uwmode=True, misa=MISA_B) +insn_alu("sh2add_uw", "0010000", "100", "rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 2)", uwmode=True, misa=MISA_B) +insn_alu("sh3add_uw", "0010000", "110", "rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 3)", uwmode=True, misa=MISA_B) +insn_shimm("slli_uw", "000010", "001", "rvfi_rs1_rdata[31:0] << insn_shamt", uwmode=True, misa=MISA_B) +# insn_alu("zext_w", wmode=True, misa=MISA_B) # ??? + +### Zbb: Basic bit-manipulation + +current_isa = ["rv32iZbb"] + +current_isa = ["rv64iZbb"] + +### Zbs: Single-bit instructions + +current_isa = ["rv32iZbs"] + +current_isa = ["rv64iZbs"] + ## Compressed Integer ISA (IC) current_isa = ["rv32ic"] @@ -1283,17 +1325,24 @@ def insn_c_mvadd(insn, funct4, add, misa=MISA_C): def isa_propagate_pair(from_isa, to_isa): global isa_database - assert from_isa in isa_database + assert from_isa in isa_database, f'{from_isa} not in {list(isa_database.keys())}' if to_isa not in isa_database: isa_database[to_isa] = set() isa_database[to_isa] |= isa_database[from_isa] +# RISC-V ISA extensions are more than just a single character '[a-z]': +# multi-letter extensions begin with Z X or S (technically Ss Sh Sv or Sm) +# followed by one or more letters '[ZXS][a-z]+'; any extension may also have a +# version number with the 'p' character as major/minor separator '([0-9p]+)?'. +# Case also seems to be variable, so use 're.IGNORECASE'. +rv_ext_pat = r'([ZXS][a-z]+|[a-z])([0-9p]+)?' + def isa_propagate(suffix): - for i in range(2 ** len(suffix)): - src = "" - for k in range(len(suffix)): - if ((i >> k) & 1) == 0: - src += suffix[k] + if suffix: + isa_propagate_pair("rv32i", "rv32i"+suffix) + isa_propagate_pair("rv64i", "rv64i"+suffix) + for match in re.finditer(rv_ext_pat, suffix, flags=re.IGNORECASE): + src = match.group() if src != suffix: isa_propagate_pair("rv32i"+src, "rv32i"+suffix) isa_propagate_pair("rv64i"+src, "rv64i"+suffix) @@ -1304,6 +1353,15 @@ def isa_propagate(suffix): isa_propagate("m") isa_propagate("mc") +## B extension is Zba, Zbb, and Zbs +for ext in ["Zba", "Zbb", "Zbs"]: + if "rv32i"+ext not in isa_database: + continue + isa_propagate(ext) + isa_propagate_pair("rv32i"+ext, "rv32ib") + isa_propagate_pair("rv64i"+ext, "rv64ib") +isa_propagate_pair("rv32ib", "rv64ib") + ## ISA Fixup for isa, insns in isa_database.items(): diff --git a/insns/insn_add_uw.v b/insns/insn_add_uw.v new file mode 100644 index 00000000..76782cb6 --- /dev/null +++ b/insns/insn_add_uw.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_add_uw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ADD_UW instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata + rvfi_rs1_rdata[31:0]; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000100 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sh1add.v b/insns/insn_sh1add.v new file mode 100644 index 00000000..f617a5e6 --- /dev/null +++ b/insns/insn_sh1add.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sh1add ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SH1ADD instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata + (rvfi_rs1_rdata << 1); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0010000 && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sh1add_uw.v b/insns/insn_sh1add_uw.v new file mode 100644 index 00000000..577f3e4a --- /dev/null +++ b/insns/insn_sh1add_uw.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sh1add_uw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SH1ADD_UW instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 1); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0010000 && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0111011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sh2add.v b/insns/insn_sh2add.v new file mode 100644 index 00000000..42fbf8c0 --- /dev/null +++ b/insns/insn_sh2add.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sh2add ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SH2ADD instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata + (rvfi_rs1_rdata << 2); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0010000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sh2add_uw.v b/insns/insn_sh2add_uw.v new file mode 100644 index 00000000..da087d81 --- /dev/null +++ b/insns/insn_sh2add_uw.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sh2add_uw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SH2ADD_UW instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 2); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0010000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0111011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sh3add.v b/insns/insn_sh3add.v new file mode 100644 index 00000000..e29c73a5 --- /dev/null +++ b/insns/insn_sh3add.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sh3add ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SH3ADD instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata + (rvfi_rs1_rdata << 3); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0010000 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sh3add_uw.v b/insns/insn_sh3add_uw.v new file mode 100644 index 00000000..4d92aa8a --- /dev/null +++ b/insns/insn_sh3add_uw.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sh3add_uw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SH3ADD_UW instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 3); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0010000 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0111011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_slli_uw.v b/insns/insn_slli_uw.v new file mode 100644 index 00000000..4297bba9 --- /dev/null +++ b/insns/insn_slli_uw.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_slli_uw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // I-type instruction format (shift variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SLLI_UW instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata[31:0] << insn_shamt; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011 && 1; + assign spec_rs1_addr = insn_rs1; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_rs2_addr = 0; + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/isa_rv32iZba.txt b/insns/isa_rv32iZba.txt new file mode 100644 index 00000000..dfc72770 --- /dev/null +++ b/insns/isa_rv32iZba.txt @@ -0,0 +1,40 @@ +add +addi +and +andi +auipc +beq +bge +bgeu +blt +bltu +bne +jal +jalr +lb +lbu +lh +lhu +lui +lw +or +ori +sb +sh +sh1add +sh2add +sh3add +sll +slli +slt +slti +sltiu +sltu +sra +srai +srl +srli +sub +sw +xor +xori diff --git a/insns/isa_rv32iZba.v b/insns/isa_rv32iZba.v new file mode 100644 index 00000000..33b1c573 --- /dev/null +++ b/insns/isa_rv32iZba.v @@ -0,0 +1,2081 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv32iZba ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sh1add_valid; + wire spec_insn_sh1add_trap; + wire [ 4 : 0] spec_insn_sh1add_rs1_addr; + wire [ 4 : 0] spec_insn_sh1add_rs2_addr; + wire [ 4 : 0] spec_insn_sh1add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_csr_misa_rmask; +`endif + + rvfi_insn_sh1add insn_sh1add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh1add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh1add_valid), + .spec_trap(spec_insn_sh1add_trap), + .spec_rs1_addr(spec_insn_sh1add_rs1_addr), + .spec_rs2_addr(spec_insn_sh1add_rs2_addr), + .spec_rd_addr(spec_insn_sh1add_rd_addr), + .spec_rd_wdata(spec_insn_sh1add_rd_wdata), + .spec_pc_wdata(spec_insn_sh1add_pc_wdata), + .spec_mem_addr(spec_insn_sh1add_mem_addr), + .spec_mem_rmask(spec_insn_sh1add_mem_rmask), + .spec_mem_wmask(spec_insn_sh1add_mem_wmask), + .spec_mem_wdata(spec_insn_sh1add_mem_wdata) + ); + + wire spec_insn_sh2add_valid; + wire spec_insn_sh2add_trap; + wire [ 4 : 0] spec_insn_sh2add_rs1_addr; + wire [ 4 : 0] spec_insn_sh2add_rs2_addr; + wire [ 4 : 0] spec_insn_sh2add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_csr_misa_rmask; +`endif + + rvfi_insn_sh2add insn_sh2add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh2add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh2add_valid), + .spec_trap(spec_insn_sh2add_trap), + .spec_rs1_addr(spec_insn_sh2add_rs1_addr), + .spec_rs2_addr(spec_insn_sh2add_rs2_addr), + .spec_rd_addr(spec_insn_sh2add_rd_addr), + .spec_rd_wdata(spec_insn_sh2add_rd_wdata), + .spec_pc_wdata(spec_insn_sh2add_pc_wdata), + .spec_mem_addr(spec_insn_sh2add_mem_addr), + .spec_mem_rmask(spec_insn_sh2add_mem_rmask), + .spec_mem_wmask(spec_insn_sh2add_mem_wmask), + .spec_mem_wdata(spec_insn_sh2add_mem_wdata) + ); + + wire spec_insn_sh3add_valid; + wire spec_insn_sh3add_trap; + wire [ 4 : 0] spec_insn_sh3add_rs1_addr; + wire [ 4 : 0] spec_insn_sh3add_rs2_addr; + wire [ 4 : 0] spec_insn_sh3add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_csr_misa_rmask; +`endif + + rvfi_insn_sh3add insn_sh3add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh3add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh3add_valid), + .spec_trap(spec_insn_sh3add_trap), + .spec_rs1_addr(spec_insn_sh3add_rs1_addr), + .spec_rs2_addr(spec_insn_sh3add_rs2_addr), + .spec_rd_addr(spec_insn_sh3add_rd_addr), + .spec_rd_wdata(spec_insn_sh3add_rd_wdata), + .spec_pc_wdata(spec_insn_sh3add_pc_wdata), + .spec_mem_addr(spec_insn_sh3add_mem_addr), + .spec_mem_rmask(spec_insn_sh3add_mem_rmask), + .spec_mem_wmask(spec_insn_sh3add_mem_wmask), + .spec_mem_wdata(spec_insn_sh3add_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sh1add_valid ? spec_insn_sh1add_valid : + spec_insn_sh2add_valid ? spec_insn_sh2add_valid : + spec_insn_sh3add_valid ? spec_insn_sh3add_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sh1add_valid ? spec_insn_sh1add_trap : + spec_insn_sh2add_valid ? spec_insn_sh2add_trap : + spec_insn_sh3add_valid ? spec_insn_sh3add_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs1_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs1_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs2_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs2_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_pc_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_pc_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_csr_misa_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_csr_misa_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; +`endif +endmodule diff --git a/insns/isa_rv32ib.txt b/insns/isa_rv32ib.txt new file mode 100644 index 00000000..dfc72770 --- /dev/null +++ b/insns/isa_rv32ib.txt @@ -0,0 +1,40 @@ +add +addi +and +andi +auipc +beq +bge +bgeu +blt +bltu +bne +jal +jalr +lb +lbu +lh +lhu +lui +lw +or +ori +sb +sh +sh1add +sh2add +sh3add +sll +slli +slt +slti +sltiu +sltu +sra +srai +srl +srli +sub +sw +xor +xori diff --git a/insns/isa_rv32ib.v b/insns/isa_rv32ib.v new file mode 100644 index 00000000..6a595dcf --- /dev/null +++ b/insns/isa_rv32ib.v @@ -0,0 +1,2081 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv32ib ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sh1add_valid; + wire spec_insn_sh1add_trap; + wire [ 4 : 0] spec_insn_sh1add_rs1_addr; + wire [ 4 : 0] spec_insn_sh1add_rs2_addr; + wire [ 4 : 0] spec_insn_sh1add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_csr_misa_rmask; +`endif + + rvfi_insn_sh1add insn_sh1add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh1add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh1add_valid), + .spec_trap(spec_insn_sh1add_trap), + .spec_rs1_addr(spec_insn_sh1add_rs1_addr), + .spec_rs2_addr(spec_insn_sh1add_rs2_addr), + .spec_rd_addr(spec_insn_sh1add_rd_addr), + .spec_rd_wdata(spec_insn_sh1add_rd_wdata), + .spec_pc_wdata(spec_insn_sh1add_pc_wdata), + .spec_mem_addr(spec_insn_sh1add_mem_addr), + .spec_mem_rmask(spec_insn_sh1add_mem_rmask), + .spec_mem_wmask(spec_insn_sh1add_mem_wmask), + .spec_mem_wdata(spec_insn_sh1add_mem_wdata) + ); + + wire spec_insn_sh2add_valid; + wire spec_insn_sh2add_trap; + wire [ 4 : 0] spec_insn_sh2add_rs1_addr; + wire [ 4 : 0] spec_insn_sh2add_rs2_addr; + wire [ 4 : 0] spec_insn_sh2add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_csr_misa_rmask; +`endif + + rvfi_insn_sh2add insn_sh2add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh2add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh2add_valid), + .spec_trap(spec_insn_sh2add_trap), + .spec_rs1_addr(spec_insn_sh2add_rs1_addr), + .spec_rs2_addr(spec_insn_sh2add_rs2_addr), + .spec_rd_addr(spec_insn_sh2add_rd_addr), + .spec_rd_wdata(spec_insn_sh2add_rd_wdata), + .spec_pc_wdata(spec_insn_sh2add_pc_wdata), + .spec_mem_addr(spec_insn_sh2add_mem_addr), + .spec_mem_rmask(spec_insn_sh2add_mem_rmask), + .spec_mem_wmask(spec_insn_sh2add_mem_wmask), + .spec_mem_wdata(spec_insn_sh2add_mem_wdata) + ); + + wire spec_insn_sh3add_valid; + wire spec_insn_sh3add_trap; + wire [ 4 : 0] spec_insn_sh3add_rs1_addr; + wire [ 4 : 0] spec_insn_sh3add_rs2_addr; + wire [ 4 : 0] spec_insn_sh3add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_csr_misa_rmask; +`endif + + rvfi_insn_sh3add insn_sh3add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh3add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh3add_valid), + .spec_trap(spec_insn_sh3add_trap), + .spec_rs1_addr(spec_insn_sh3add_rs1_addr), + .spec_rs2_addr(spec_insn_sh3add_rs2_addr), + .spec_rd_addr(spec_insn_sh3add_rd_addr), + .spec_rd_wdata(spec_insn_sh3add_rd_wdata), + .spec_pc_wdata(spec_insn_sh3add_pc_wdata), + .spec_mem_addr(spec_insn_sh3add_mem_addr), + .spec_mem_rmask(spec_insn_sh3add_mem_rmask), + .spec_mem_wmask(spec_insn_sh3add_mem_wmask), + .spec_mem_wdata(spec_insn_sh3add_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sh1add_valid ? spec_insn_sh1add_valid : + spec_insn_sh2add_valid ? spec_insn_sh2add_valid : + spec_insn_sh3add_valid ? spec_insn_sh3add_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sh1add_valid ? spec_insn_sh1add_trap : + spec_insn_sh2add_valid ? spec_insn_sh2add_trap : + spec_insn_sh3add_valid ? spec_insn_sh3add_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs1_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs1_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs2_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs2_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_pc_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_pc_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_csr_misa_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_csr_misa_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; +`endif +endmodule diff --git a/insns/isa_rv64iZba.txt b/insns/isa_rv64iZba.txt new file mode 100644 index 00000000..bb162e74 --- /dev/null +++ b/insns/isa_rv64iZba.txt @@ -0,0 +1,57 @@ +add +add_uw +addi +addiw +addw +and +andi +auipc +beq +bge +bgeu +blt +bltu +bne +jal +jalr +lb +lbu +ld +lh +lhu +lui +lw +lwu +or +ori +sb +sd +sh +sh1add +sh1add_uw +sh2add +sh2add_uw +sh3add +sh3add_uw +sll +slli +slli_uw +slliw +sllw +slt +slti +sltiu +sltu +sra +srai +sraiw +sraw +srl +srli +srliw +srlw +sub +subw +sw +xor +xori diff --git a/insns/isa_rv64iZba.v b/insns/isa_rv64iZba.v new file mode 100644 index 00000000..b6454c95 --- /dev/null +++ b/insns/isa_rv64iZba.v @@ -0,0 +1,2948 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv64iZba ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_add_uw_valid; + wire spec_insn_add_uw_trap; + wire [ 4 : 0] spec_insn_add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_csr_misa_rmask; +`endif + + rvfi_insn_add_uw insn_add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_uw_valid), + .spec_trap(spec_insn_add_uw_trap), + .spec_rs1_addr(spec_insn_add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_add_uw_rs2_addr), + .spec_rd_addr(spec_insn_add_uw_rd_addr), + .spec_rd_wdata(spec_insn_add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_add_uw_pc_wdata), + .spec_mem_addr(spec_insn_add_uw_mem_addr), + .spec_mem_rmask(spec_insn_add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_add_uw_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_addiw_valid; + wire spec_insn_addiw_trap; + wire [ 4 : 0] spec_insn_addiw_rs1_addr; + wire [ 4 : 0] spec_insn_addiw_rs2_addr; + wire [ 4 : 0] spec_insn_addiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; +`endif + + rvfi_insn_addiw insn_addiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addiw_valid), + .spec_trap(spec_insn_addiw_trap), + .spec_rs1_addr(spec_insn_addiw_rs1_addr), + .spec_rs2_addr(spec_insn_addiw_rs2_addr), + .spec_rd_addr(spec_insn_addiw_rd_addr), + .spec_rd_wdata(spec_insn_addiw_rd_wdata), + .spec_pc_wdata(spec_insn_addiw_pc_wdata), + .spec_mem_addr(spec_insn_addiw_mem_addr), + .spec_mem_rmask(spec_insn_addiw_mem_rmask), + .spec_mem_wmask(spec_insn_addiw_mem_wmask), + .spec_mem_wdata(spec_insn_addiw_mem_wdata) + ); + + wire spec_insn_addw_valid; + wire spec_insn_addw_trap; + wire [ 4 : 0] spec_insn_addw_rs1_addr; + wire [ 4 : 0] spec_insn_addw_rs2_addr; + wire [ 4 : 0] spec_insn_addw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; +`endif + + rvfi_insn_addw insn_addw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addw_valid), + .spec_trap(spec_insn_addw_trap), + .spec_rs1_addr(spec_insn_addw_rs1_addr), + .spec_rs2_addr(spec_insn_addw_rs2_addr), + .spec_rd_addr(spec_insn_addw_rd_addr), + .spec_rd_wdata(spec_insn_addw_rd_wdata), + .spec_pc_wdata(spec_insn_addw_pc_wdata), + .spec_mem_addr(spec_insn_addw_mem_addr), + .spec_mem_rmask(spec_insn_addw_mem_rmask), + .spec_mem_wmask(spec_insn_addw_mem_wmask), + .spec_mem_wdata(spec_insn_addw_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_ld_valid; + wire spec_insn_ld_trap; + wire [ 4 : 0] spec_insn_ld_rs1_addr; + wire [ 4 : 0] spec_insn_ld_rs2_addr; + wire [ 4 : 0] spec_insn_ld_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; +`endif + + rvfi_insn_ld insn_ld ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ld_valid), + .spec_trap(spec_insn_ld_trap), + .spec_rs1_addr(spec_insn_ld_rs1_addr), + .spec_rs2_addr(spec_insn_ld_rs2_addr), + .spec_rd_addr(spec_insn_ld_rd_addr), + .spec_rd_wdata(spec_insn_ld_rd_wdata), + .spec_pc_wdata(spec_insn_ld_pc_wdata), + .spec_mem_addr(spec_insn_ld_mem_addr), + .spec_mem_rmask(spec_insn_ld_mem_rmask), + .spec_mem_wmask(spec_insn_ld_mem_wmask), + .spec_mem_wdata(spec_insn_ld_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_lwu_valid; + wire spec_insn_lwu_trap; + wire [ 4 : 0] spec_insn_lwu_rs1_addr; + wire [ 4 : 0] spec_insn_lwu_rs2_addr; + wire [ 4 : 0] spec_insn_lwu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; +`endif + + rvfi_insn_lwu insn_lwu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lwu_valid), + .spec_trap(spec_insn_lwu_trap), + .spec_rs1_addr(spec_insn_lwu_rs1_addr), + .spec_rs2_addr(spec_insn_lwu_rs2_addr), + .spec_rd_addr(spec_insn_lwu_rd_addr), + .spec_rd_wdata(spec_insn_lwu_rd_wdata), + .spec_pc_wdata(spec_insn_lwu_pc_wdata), + .spec_mem_addr(spec_insn_lwu_mem_addr), + .spec_mem_rmask(spec_insn_lwu_mem_rmask), + .spec_mem_wmask(spec_insn_lwu_mem_wmask), + .spec_mem_wdata(spec_insn_lwu_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sd_valid; + wire spec_insn_sd_trap; + wire [ 4 : 0] spec_insn_sd_rs1_addr; + wire [ 4 : 0] spec_insn_sd_rs2_addr; + wire [ 4 : 0] spec_insn_sd_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; +`endif + + rvfi_insn_sd insn_sd ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sd_valid), + .spec_trap(spec_insn_sd_trap), + .spec_rs1_addr(spec_insn_sd_rs1_addr), + .spec_rs2_addr(spec_insn_sd_rs2_addr), + .spec_rd_addr(spec_insn_sd_rd_addr), + .spec_rd_wdata(spec_insn_sd_rd_wdata), + .spec_pc_wdata(spec_insn_sd_pc_wdata), + .spec_mem_addr(spec_insn_sd_mem_addr), + .spec_mem_rmask(spec_insn_sd_mem_rmask), + .spec_mem_wmask(spec_insn_sd_mem_wmask), + .spec_mem_wdata(spec_insn_sd_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sh1add_valid; + wire spec_insn_sh1add_trap; + wire [ 4 : 0] spec_insn_sh1add_rs1_addr; + wire [ 4 : 0] spec_insn_sh1add_rs2_addr; + wire [ 4 : 0] spec_insn_sh1add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_csr_misa_rmask; +`endif + + rvfi_insn_sh1add insn_sh1add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh1add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh1add_valid), + .spec_trap(spec_insn_sh1add_trap), + .spec_rs1_addr(spec_insn_sh1add_rs1_addr), + .spec_rs2_addr(spec_insn_sh1add_rs2_addr), + .spec_rd_addr(spec_insn_sh1add_rd_addr), + .spec_rd_wdata(spec_insn_sh1add_rd_wdata), + .spec_pc_wdata(spec_insn_sh1add_pc_wdata), + .spec_mem_addr(spec_insn_sh1add_mem_addr), + .spec_mem_rmask(spec_insn_sh1add_mem_rmask), + .spec_mem_wmask(spec_insn_sh1add_mem_wmask), + .spec_mem_wdata(spec_insn_sh1add_mem_wdata) + ); + + wire spec_insn_sh1add_uw_valid; + wire spec_insn_sh1add_uw_trap; + wire [ 4 : 0] spec_insn_sh1add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_sh1add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_sh1add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_csr_misa_rmask; +`endif + + rvfi_insn_sh1add_uw insn_sh1add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh1add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh1add_uw_valid), + .spec_trap(spec_insn_sh1add_uw_trap), + .spec_rs1_addr(spec_insn_sh1add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_sh1add_uw_rs2_addr), + .spec_rd_addr(spec_insn_sh1add_uw_rd_addr), + .spec_rd_wdata(spec_insn_sh1add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_sh1add_uw_pc_wdata), + .spec_mem_addr(spec_insn_sh1add_uw_mem_addr), + .spec_mem_rmask(spec_insn_sh1add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_sh1add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_sh1add_uw_mem_wdata) + ); + + wire spec_insn_sh2add_valid; + wire spec_insn_sh2add_trap; + wire [ 4 : 0] spec_insn_sh2add_rs1_addr; + wire [ 4 : 0] spec_insn_sh2add_rs2_addr; + wire [ 4 : 0] spec_insn_sh2add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_csr_misa_rmask; +`endif + + rvfi_insn_sh2add insn_sh2add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh2add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh2add_valid), + .spec_trap(spec_insn_sh2add_trap), + .spec_rs1_addr(spec_insn_sh2add_rs1_addr), + .spec_rs2_addr(spec_insn_sh2add_rs2_addr), + .spec_rd_addr(spec_insn_sh2add_rd_addr), + .spec_rd_wdata(spec_insn_sh2add_rd_wdata), + .spec_pc_wdata(spec_insn_sh2add_pc_wdata), + .spec_mem_addr(spec_insn_sh2add_mem_addr), + .spec_mem_rmask(spec_insn_sh2add_mem_rmask), + .spec_mem_wmask(spec_insn_sh2add_mem_wmask), + .spec_mem_wdata(spec_insn_sh2add_mem_wdata) + ); + + wire spec_insn_sh2add_uw_valid; + wire spec_insn_sh2add_uw_trap; + wire [ 4 : 0] spec_insn_sh2add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_sh2add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_sh2add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_csr_misa_rmask; +`endif + + rvfi_insn_sh2add_uw insn_sh2add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh2add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh2add_uw_valid), + .spec_trap(spec_insn_sh2add_uw_trap), + .spec_rs1_addr(spec_insn_sh2add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_sh2add_uw_rs2_addr), + .spec_rd_addr(spec_insn_sh2add_uw_rd_addr), + .spec_rd_wdata(spec_insn_sh2add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_sh2add_uw_pc_wdata), + .spec_mem_addr(spec_insn_sh2add_uw_mem_addr), + .spec_mem_rmask(spec_insn_sh2add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_sh2add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_sh2add_uw_mem_wdata) + ); + + wire spec_insn_sh3add_valid; + wire spec_insn_sh3add_trap; + wire [ 4 : 0] spec_insn_sh3add_rs1_addr; + wire [ 4 : 0] spec_insn_sh3add_rs2_addr; + wire [ 4 : 0] spec_insn_sh3add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_csr_misa_rmask; +`endif + + rvfi_insn_sh3add insn_sh3add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh3add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh3add_valid), + .spec_trap(spec_insn_sh3add_trap), + .spec_rs1_addr(spec_insn_sh3add_rs1_addr), + .spec_rs2_addr(spec_insn_sh3add_rs2_addr), + .spec_rd_addr(spec_insn_sh3add_rd_addr), + .spec_rd_wdata(spec_insn_sh3add_rd_wdata), + .spec_pc_wdata(spec_insn_sh3add_pc_wdata), + .spec_mem_addr(spec_insn_sh3add_mem_addr), + .spec_mem_rmask(spec_insn_sh3add_mem_rmask), + .spec_mem_wmask(spec_insn_sh3add_mem_wmask), + .spec_mem_wdata(spec_insn_sh3add_mem_wdata) + ); + + wire spec_insn_sh3add_uw_valid; + wire spec_insn_sh3add_uw_trap; + wire [ 4 : 0] spec_insn_sh3add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_sh3add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_sh3add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_csr_misa_rmask; +`endif + + rvfi_insn_sh3add_uw insn_sh3add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh3add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh3add_uw_valid), + .spec_trap(spec_insn_sh3add_uw_trap), + .spec_rs1_addr(spec_insn_sh3add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_sh3add_uw_rs2_addr), + .spec_rd_addr(spec_insn_sh3add_uw_rd_addr), + .spec_rd_wdata(spec_insn_sh3add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_sh3add_uw_pc_wdata), + .spec_mem_addr(spec_insn_sh3add_uw_mem_addr), + .spec_mem_rmask(spec_insn_sh3add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_sh3add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_sh3add_uw_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slli_uw_valid; + wire spec_insn_slli_uw_trap; + wire [ 4 : 0] spec_insn_slli_uw_rs1_addr; + wire [ 4 : 0] spec_insn_slli_uw_rs2_addr; + wire [ 4 : 0] spec_insn_slli_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_csr_misa_rmask; +`endif + + rvfi_insn_slli_uw insn_slli_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_uw_valid), + .spec_trap(spec_insn_slli_uw_trap), + .spec_rs1_addr(spec_insn_slli_uw_rs1_addr), + .spec_rs2_addr(spec_insn_slli_uw_rs2_addr), + .spec_rd_addr(spec_insn_slli_uw_rd_addr), + .spec_rd_wdata(spec_insn_slli_uw_rd_wdata), + .spec_pc_wdata(spec_insn_slli_uw_pc_wdata), + .spec_mem_addr(spec_insn_slli_uw_mem_addr), + .spec_mem_rmask(spec_insn_slli_uw_mem_rmask), + .spec_mem_wmask(spec_insn_slli_uw_mem_wmask), + .spec_mem_wdata(spec_insn_slli_uw_mem_wdata) + ); + + wire spec_insn_slliw_valid; + wire spec_insn_slliw_trap; + wire [ 4 : 0] spec_insn_slliw_rs1_addr; + wire [ 4 : 0] spec_insn_slliw_rs2_addr; + wire [ 4 : 0] spec_insn_slliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; +`endif + + rvfi_insn_slliw insn_slliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slliw_valid), + .spec_trap(spec_insn_slliw_trap), + .spec_rs1_addr(spec_insn_slliw_rs1_addr), + .spec_rs2_addr(spec_insn_slliw_rs2_addr), + .spec_rd_addr(spec_insn_slliw_rd_addr), + .spec_rd_wdata(spec_insn_slliw_rd_wdata), + .spec_pc_wdata(spec_insn_slliw_pc_wdata), + .spec_mem_addr(spec_insn_slliw_mem_addr), + .spec_mem_rmask(spec_insn_slliw_mem_rmask), + .spec_mem_wmask(spec_insn_slliw_mem_wmask), + .spec_mem_wdata(spec_insn_slliw_mem_wdata) + ); + + wire spec_insn_sllw_valid; + wire spec_insn_sllw_trap; + wire [ 4 : 0] spec_insn_sllw_rs1_addr; + wire [ 4 : 0] spec_insn_sllw_rs2_addr; + wire [ 4 : 0] spec_insn_sllw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; +`endif + + rvfi_insn_sllw insn_sllw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sllw_valid), + .spec_trap(spec_insn_sllw_trap), + .spec_rs1_addr(spec_insn_sllw_rs1_addr), + .spec_rs2_addr(spec_insn_sllw_rs2_addr), + .spec_rd_addr(spec_insn_sllw_rd_addr), + .spec_rd_wdata(spec_insn_sllw_rd_wdata), + .spec_pc_wdata(spec_insn_sllw_pc_wdata), + .spec_mem_addr(spec_insn_sllw_mem_addr), + .spec_mem_rmask(spec_insn_sllw_mem_rmask), + .spec_mem_wmask(spec_insn_sllw_mem_wmask), + .spec_mem_wdata(spec_insn_sllw_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_sraiw_valid; + wire spec_insn_sraiw_trap; + wire [ 4 : 0] spec_insn_sraiw_rs1_addr; + wire [ 4 : 0] spec_insn_sraiw_rs2_addr; + wire [ 4 : 0] spec_insn_sraiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; +`endif + + rvfi_insn_sraiw insn_sraiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraiw_valid), + .spec_trap(spec_insn_sraiw_trap), + .spec_rs1_addr(spec_insn_sraiw_rs1_addr), + .spec_rs2_addr(spec_insn_sraiw_rs2_addr), + .spec_rd_addr(spec_insn_sraiw_rd_addr), + .spec_rd_wdata(spec_insn_sraiw_rd_wdata), + .spec_pc_wdata(spec_insn_sraiw_pc_wdata), + .spec_mem_addr(spec_insn_sraiw_mem_addr), + .spec_mem_rmask(spec_insn_sraiw_mem_rmask), + .spec_mem_wmask(spec_insn_sraiw_mem_wmask), + .spec_mem_wdata(spec_insn_sraiw_mem_wdata) + ); + + wire spec_insn_sraw_valid; + wire spec_insn_sraw_trap; + wire [ 4 : 0] spec_insn_sraw_rs1_addr; + wire [ 4 : 0] spec_insn_sraw_rs2_addr; + wire [ 4 : 0] spec_insn_sraw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; +`endif + + rvfi_insn_sraw insn_sraw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraw_valid), + .spec_trap(spec_insn_sraw_trap), + .spec_rs1_addr(spec_insn_sraw_rs1_addr), + .spec_rs2_addr(spec_insn_sraw_rs2_addr), + .spec_rd_addr(spec_insn_sraw_rd_addr), + .spec_rd_wdata(spec_insn_sraw_rd_wdata), + .spec_pc_wdata(spec_insn_sraw_pc_wdata), + .spec_mem_addr(spec_insn_sraw_mem_addr), + .spec_mem_rmask(spec_insn_sraw_mem_rmask), + .spec_mem_wmask(spec_insn_sraw_mem_wmask), + .spec_mem_wdata(spec_insn_sraw_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_srliw_valid; + wire spec_insn_srliw_trap; + wire [ 4 : 0] spec_insn_srliw_rs1_addr; + wire [ 4 : 0] spec_insn_srliw_rs2_addr; + wire [ 4 : 0] spec_insn_srliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; +`endif + + rvfi_insn_srliw insn_srliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srliw_valid), + .spec_trap(spec_insn_srliw_trap), + .spec_rs1_addr(spec_insn_srliw_rs1_addr), + .spec_rs2_addr(spec_insn_srliw_rs2_addr), + .spec_rd_addr(spec_insn_srliw_rd_addr), + .spec_rd_wdata(spec_insn_srliw_rd_wdata), + .spec_pc_wdata(spec_insn_srliw_pc_wdata), + .spec_mem_addr(spec_insn_srliw_mem_addr), + .spec_mem_rmask(spec_insn_srliw_mem_rmask), + .spec_mem_wmask(spec_insn_srliw_mem_wmask), + .spec_mem_wdata(spec_insn_srliw_mem_wdata) + ); + + wire spec_insn_srlw_valid; + wire spec_insn_srlw_trap; + wire [ 4 : 0] spec_insn_srlw_rs1_addr; + wire [ 4 : 0] spec_insn_srlw_rs2_addr; + wire [ 4 : 0] spec_insn_srlw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; +`endif + + rvfi_insn_srlw insn_srlw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srlw_valid), + .spec_trap(spec_insn_srlw_trap), + .spec_rs1_addr(spec_insn_srlw_rs1_addr), + .spec_rs2_addr(spec_insn_srlw_rs2_addr), + .spec_rd_addr(spec_insn_srlw_rd_addr), + .spec_rd_wdata(spec_insn_srlw_rd_wdata), + .spec_pc_wdata(spec_insn_srlw_pc_wdata), + .spec_mem_addr(spec_insn_srlw_mem_addr), + .spec_mem_rmask(spec_insn_srlw_mem_rmask), + .spec_mem_wmask(spec_insn_srlw_mem_wmask), + .spec_mem_wdata(spec_insn_srlw_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_subw_valid; + wire spec_insn_subw_trap; + wire [ 4 : 0] spec_insn_subw_rs1_addr; + wire [ 4 : 0] spec_insn_subw_rs2_addr; + wire [ 4 : 0] spec_insn_subw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; +`endif + + rvfi_insn_subw insn_subw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_subw_valid), + .spec_trap(spec_insn_subw_trap), + .spec_rs1_addr(spec_insn_subw_rs1_addr), + .spec_rs2_addr(spec_insn_subw_rs2_addr), + .spec_rd_addr(spec_insn_subw_rd_addr), + .spec_rd_wdata(spec_insn_subw_rd_wdata), + .spec_pc_wdata(spec_insn_subw_pc_wdata), + .spec_mem_addr(spec_insn_subw_mem_addr), + .spec_mem_rmask(spec_insn_subw_mem_rmask), + .spec_mem_wmask(spec_insn_subw_mem_wmask), + .spec_mem_wdata(spec_insn_subw_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_add_uw_valid ? spec_insn_add_uw_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_addiw_valid ? spec_insn_addiw_valid : + spec_insn_addw_valid ? spec_insn_addw_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_ld_valid ? spec_insn_ld_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_lwu_valid ? spec_insn_lwu_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sd_valid ? spec_insn_sd_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sh1add_valid ? spec_insn_sh1add_valid : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_valid : + spec_insn_sh2add_valid ? spec_insn_sh2add_valid : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_valid : + spec_insn_sh3add_valid ? spec_insn_sh3add_valid : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_valid : + spec_insn_slliw_valid ? spec_insn_slliw_valid : + spec_insn_sllw_valid ? spec_insn_sllw_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_sraiw_valid ? spec_insn_sraiw_valid : + spec_insn_sraw_valid ? spec_insn_sraw_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_srliw_valid ? spec_insn_srliw_valid : + spec_insn_srlw_valid ? spec_insn_srlw_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_subw_valid ? spec_insn_subw_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_add_uw_valid ? spec_insn_add_uw_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_addiw_valid ? spec_insn_addiw_trap : + spec_insn_addw_valid ? spec_insn_addw_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_ld_valid ? spec_insn_ld_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_lwu_valid ? spec_insn_lwu_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sd_valid ? spec_insn_sd_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sh1add_valid ? spec_insn_sh1add_trap : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_trap : + spec_insn_sh2add_valid ? spec_insn_sh2add_trap : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_trap : + spec_insn_sh3add_valid ? spec_insn_sh3add_trap : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_trap : + spec_insn_slliw_valid ? spec_insn_slliw_trap : + spec_insn_sllw_valid ? spec_insn_sllw_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_sraiw_valid ? spec_insn_sraiw_trap : + spec_insn_sraw_valid ? spec_insn_sraw_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_srliw_valid ? spec_insn_srliw_trap : + spec_insn_srlw_valid ? spec_insn_srlw_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_subw_valid ? spec_insn_subw_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : + spec_insn_addw_valid ? spec_insn_addw_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_ld_valid ? spec_insn_ld_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sd_valid ? spec_insn_sd_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs1_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs1_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs1_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rs1_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs1_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rs1_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_subw_valid ? spec_insn_subw_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : + spec_insn_addw_valid ? spec_insn_addw_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_ld_valid ? spec_insn_ld_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sd_valid ? spec_insn_sd_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs2_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs2_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs2_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rs2_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs2_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rs2_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_subw_valid ? spec_insn_subw_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : + spec_insn_addw_valid ? spec_insn_addw_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_ld_valid ? spec_insn_ld_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sd_valid ? spec_insn_sd_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rd_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rd_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_subw_valid ? spec_insn_subw_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_add_uw_valid ? spec_insn_add_uw_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : + spec_insn_addw_valid ? spec_insn_addw_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_ld_valid ? spec_insn_ld_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sd_valid ? spec_insn_sd_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_wdata : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_wdata : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rd_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_wdata : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rd_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_subw_valid ? spec_insn_subw_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_add_uw_valid ? spec_insn_add_uw_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : + spec_insn_addw_valid ? spec_insn_addw_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_ld_valid ? spec_insn_ld_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sd_valid ? spec_insn_sd_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_pc_wdata : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_pc_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_pc_wdata : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_pc_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_pc_wdata : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_pc_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_subw_valid ? spec_insn_subw_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : + spec_insn_addw_valid ? spec_insn_addw_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_ld_valid ? spec_insn_ld_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sd_valid ? spec_insn_sd_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_addr : + spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : + spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : + spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : + spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_subw_valid ? spec_insn_subw_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : + spec_insn_addw_valid ? spec_insn_addw_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_ld_valid ? spec_insn_ld_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sd_valid ? spec_insn_sd_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_rmask : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_rmask : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_rmask : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_subw_valid ? spec_insn_subw_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : + spec_insn_addw_valid ? spec_insn_addw_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_ld_valid ? spec_insn_ld_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sd_valid ? spec_insn_sd_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wmask : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wmask : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_wmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wmask : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_wmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_subw_valid ? spec_insn_subw_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : + spec_insn_addw_valid ? spec_insn_addw_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_ld_valid ? spec_insn_ld_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sd_valid ? spec_insn_sd_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wdata : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wdata : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wdata : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_subw_valid ? spec_insn_subw_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_add_uw_valid ? spec_insn_add_uw_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : + spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_csr_misa_rmask : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_csr_misa_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_csr_misa_rmask : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_csr_misa_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_csr_misa_rmask : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_csr_misa_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; +`endif +endmodule diff --git a/insns/isa_rv64ib.txt b/insns/isa_rv64ib.txt new file mode 100644 index 00000000..bb162e74 --- /dev/null +++ b/insns/isa_rv64ib.txt @@ -0,0 +1,57 @@ +add +add_uw +addi +addiw +addw +and +andi +auipc +beq +bge +bgeu +blt +bltu +bne +jal +jalr +lb +lbu +ld +lh +lhu +lui +lw +lwu +or +ori +sb +sd +sh +sh1add +sh1add_uw +sh2add +sh2add_uw +sh3add +sh3add_uw +sll +slli +slli_uw +slliw +sllw +slt +slti +sltiu +sltu +sra +srai +sraiw +sraw +srl +srli +srliw +srlw +sub +subw +sw +xor +xori diff --git a/insns/isa_rv64ib.v b/insns/isa_rv64ib.v new file mode 100644 index 00000000..b9c2a24f --- /dev/null +++ b/insns/isa_rv64ib.v @@ -0,0 +1,2948 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv64ib ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_add_uw_valid; + wire spec_insn_add_uw_trap; + wire [ 4 : 0] spec_insn_add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_uw_csr_misa_rmask; +`endif + + rvfi_insn_add_uw insn_add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_uw_valid), + .spec_trap(spec_insn_add_uw_trap), + .spec_rs1_addr(spec_insn_add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_add_uw_rs2_addr), + .spec_rd_addr(spec_insn_add_uw_rd_addr), + .spec_rd_wdata(spec_insn_add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_add_uw_pc_wdata), + .spec_mem_addr(spec_insn_add_uw_mem_addr), + .spec_mem_rmask(spec_insn_add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_add_uw_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_addiw_valid; + wire spec_insn_addiw_trap; + wire [ 4 : 0] spec_insn_addiw_rs1_addr; + wire [ 4 : 0] spec_insn_addiw_rs2_addr; + wire [ 4 : 0] spec_insn_addiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; +`endif + + rvfi_insn_addiw insn_addiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addiw_valid), + .spec_trap(spec_insn_addiw_trap), + .spec_rs1_addr(spec_insn_addiw_rs1_addr), + .spec_rs2_addr(spec_insn_addiw_rs2_addr), + .spec_rd_addr(spec_insn_addiw_rd_addr), + .spec_rd_wdata(spec_insn_addiw_rd_wdata), + .spec_pc_wdata(spec_insn_addiw_pc_wdata), + .spec_mem_addr(spec_insn_addiw_mem_addr), + .spec_mem_rmask(spec_insn_addiw_mem_rmask), + .spec_mem_wmask(spec_insn_addiw_mem_wmask), + .spec_mem_wdata(spec_insn_addiw_mem_wdata) + ); + + wire spec_insn_addw_valid; + wire spec_insn_addw_trap; + wire [ 4 : 0] spec_insn_addw_rs1_addr; + wire [ 4 : 0] spec_insn_addw_rs2_addr; + wire [ 4 : 0] spec_insn_addw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; +`endif + + rvfi_insn_addw insn_addw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addw_valid), + .spec_trap(spec_insn_addw_trap), + .spec_rs1_addr(spec_insn_addw_rs1_addr), + .spec_rs2_addr(spec_insn_addw_rs2_addr), + .spec_rd_addr(spec_insn_addw_rd_addr), + .spec_rd_wdata(spec_insn_addw_rd_wdata), + .spec_pc_wdata(spec_insn_addw_pc_wdata), + .spec_mem_addr(spec_insn_addw_mem_addr), + .spec_mem_rmask(spec_insn_addw_mem_rmask), + .spec_mem_wmask(spec_insn_addw_mem_wmask), + .spec_mem_wdata(spec_insn_addw_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_ld_valid; + wire spec_insn_ld_trap; + wire [ 4 : 0] spec_insn_ld_rs1_addr; + wire [ 4 : 0] spec_insn_ld_rs2_addr; + wire [ 4 : 0] spec_insn_ld_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; +`endif + + rvfi_insn_ld insn_ld ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ld_valid), + .spec_trap(spec_insn_ld_trap), + .spec_rs1_addr(spec_insn_ld_rs1_addr), + .spec_rs2_addr(spec_insn_ld_rs2_addr), + .spec_rd_addr(spec_insn_ld_rd_addr), + .spec_rd_wdata(spec_insn_ld_rd_wdata), + .spec_pc_wdata(spec_insn_ld_pc_wdata), + .spec_mem_addr(spec_insn_ld_mem_addr), + .spec_mem_rmask(spec_insn_ld_mem_rmask), + .spec_mem_wmask(spec_insn_ld_mem_wmask), + .spec_mem_wdata(spec_insn_ld_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_lwu_valid; + wire spec_insn_lwu_trap; + wire [ 4 : 0] spec_insn_lwu_rs1_addr; + wire [ 4 : 0] spec_insn_lwu_rs2_addr; + wire [ 4 : 0] spec_insn_lwu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; +`endif + + rvfi_insn_lwu insn_lwu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lwu_valid), + .spec_trap(spec_insn_lwu_trap), + .spec_rs1_addr(spec_insn_lwu_rs1_addr), + .spec_rs2_addr(spec_insn_lwu_rs2_addr), + .spec_rd_addr(spec_insn_lwu_rd_addr), + .spec_rd_wdata(spec_insn_lwu_rd_wdata), + .spec_pc_wdata(spec_insn_lwu_pc_wdata), + .spec_mem_addr(spec_insn_lwu_mem_addr), + .spec_mem_rmask(spec_insn_lwu_mem_rmask), + .spec_mem_wmask(spec_insn_lwu_mem_wmask), + .spec_mem_wdata(spec_insn_lwu_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sd_valid; + wire spec_insn_sd_trap; + wire [ 4 : 0] spec_insn_sd_rs1_addr; + wire [ 4 : 0] spec_insn_sd_rs2_addr; + wire [ 4 : 0] spec_insn_sd_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; +`endif + + rvfi_insn_sd insn_sd ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sd_valid), + .spec_trap(spec_insn_sd_trap), + .spec_rs1_addr(spec_insn_sd_rs1_addr), + .spec_rs2_addr(spec_insn_sd_rs2_addr), + .spec_rd_addr(spec_insn_sd_rd_addr), + .spec_rd_wdata(spec_insn_sd_rd_wdata), + .spec_pc_wdata(spec_insn_sd_pc_wdata), + .spec_mem_addr(spec_insn_sd_mem_addr), + .spec_mem_rmask(spec_insn_sd_mem_rmask), + .spec_mem_wmask(spec_insn_sd_mem_wmask), + .spec_mem_wdata(spec_insn_sd_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sh1add_valid; + wire spec_insn_sh1add_trap; + wire [ 4 : 0] spec_insn_sh1add_rs1_addr; + wire [ 4 : 0] spec_insn_sh1add_rs2_addr; + wire [ 4 : 0] spec_insn_sh1add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_csr_misa_rmask; +`endif + + rvfi_insn_sh1add insn_sh1add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh1add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh1add_valid), + .spec_trap(spec_insn_sh1add_trap), + .spec_rs1_addr(spec_insn_sh1add_rs1_addr), + .spec_rs2_addr(spec_insn_sh1add_rs2_addr), + .spec_rd_addr(spec_insn_sh1add_rd_addr), + .spec_rd_wdata(spec_insn_sh1add_rd_wdata), + .spec_pc_wdata(spec_insn_sh1add_pc_wdata), + .spec_mem_addr(spec_insn_sh1add_mem_addr), + .spec_mem_rmask(spec_insn_sh1add_mem_rmask), + .spec_mem_wmask(spec_insn_sh1add_mem_wmask), + .spec_mem_wdata(spec_insn_sh1add_mem_wdata) + ); + + wire spec_insn_sh1add_uw_valid; + wire spec_insn_sh1add_uw_trap; + wire [ 4 : 0] spec_insn_sh1add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_sh1add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_sh1add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh1add_uw_csr_misa_rmask; +`endif + + rvfi_insn_sh1add_uw insn_sh1add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh1add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh1add_uw_valid), + .spec_trap(spec_insn_sh1add_uw_trap), + .spec_rs1_addr(spec_insn_sh1add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_sh1add_uw_rs2_addr), + .spec_rd_addr(spec_insn_sh1add_uw_rd_addr), + .spec_rd_wdata(spec_insn_sh1add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_sh1add_uw_pc_wdata), + .spec_mem_addr(spec_insn_sh1add_uw_mem_addr), + .spec_mem_rmask(spec_insn_sh1add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_sh1add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_sh1add_uw_mem_wdata) + ); + + wire spec_insn_sh2add_valid; + wire spec_insn_sh2add_trap; + wire [ 4 : 0] spec_insn_sh2add_rs1_addr; + wire [ 4 : 0] spec_insn_sh2add_rs2_addr; + wire [ 4 : 0] spec_insn_sh2add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_csr_misa_rmask; +`endif + + rvfi_insn_sh2add insn_sh2add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh2add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh2add_valid), + .spec_trap(spec_insn_sh2add_trap), + .spec_rs1_addr(spec_insn_sh2add_rs1_addr), + .spec_rs2_addr(spec_insn_sh2add_rs2_addr), + .spec_rd_addr(spec_insn_sh2add_rd_addr), + .spec_rd_wdata(spec_insn_sh2add_rd_wdata), + .spec_pc_wdata(spec_insn_sh2add_pc_wdata), + .spec_mem_addr(spec_insn_sh2add_mem_addr), + .spec_mem_rmask(spec_insn_sh2add_mem_rmask), + .spec_mem_wmask(spec_insn_sh2add_mem_wmask), + .spec_mem_wdata(spec_insn_sh2add_mem_wdata) + ); + + wire spec_insn_sh2add_uw_valid; + wire spec_insn_sh2add_uw_trap; + wire [ 4 : 0] spec_insn_sh2add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_sh2add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_sh2add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh2add_uw_csr_misa_rmask; +`endif + + rvfi_insn_sh2add_uw insn_sh2add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh2add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh2add_uw_valid), + .spec_trap(spec_insn_sh2add_uw_trap), + .spec_rs1_addr(spec_insn_sh2add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_sh2add_uw_rs2_addr), + .spec_rd_addr(spec_insn_sh2add_uw_rd_addr), + .spec_rd_wdata(spec_insn_sh2add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_sh2add_uw_pc_wdata), + .spec_mem_addr(spec_insn_sh2add_uw_mem_addr), + .spec_mem_rmask(spec_insn_sh2add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_sh2add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_sh2add_uw_mem_wdata) + ); + + wire spec_insn_sh3add_valid; + wire spec_insn_sh3add_trap; + wire [ 4 : 0] spec_insn_sh3add_rs1_addr; + wire [ 4 : 0] spec_insn_sh3add_rs2_addr; + wire [ 4 : 0] spec_insn_sh3add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_csr_misa_rmask; +`endif + + rvfi_insn_sh3add insn_sh3add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh3add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh3add_valid), + .spec_trap(spec_insn_sh3add_trap), + .spec_rs1_addr(spec_insn_sh3add_rs1_addr), + .spec_rs2_addr(spec_insn_sh3add_rs2_addr), + .spec_rd_addr(spec_insn_sh3add_rd_addr), + .spec_rd_wdata(spec_insn_sh3add_rd_wdata), + .spec_pc_wdata(spec_insn_sh3add_pc_wdata), + .spec_mem_addr(spec_insn_sh3add_mem_addr), + .spec_mem_rmask(spec_insn_sh3add_mem_rmask), + .spec_mem_wmask(spec_insn_sh3add_mem_wmask), + .spec_mem_wdata(spec_insn_sh3add_mem_wdata) + ); + + wire spec_insn_sh3add_uw_valid; + wire spec_insn_sh3add_uw_trap; + wire [ 4 : 0] spec_insn_sh3add_uw_rs1_addr; + wire [ 4 : 0] spec_insn_sh3add_uw_rs2_addr; + wire [ 4 : 0] spec_insn_sh3add_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh3add_uw_csr_misa_rmask; +`endif + + rvfi_insn_sh3add_uw insn_sh3add_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh3add_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh3add_uw_valid), + .spec_trap(spec_insn_sh3add_uw_trap), + .spec_rs1_addr(spec_insn_sh3add_uw_rs1_addr), + .spec_rs2_addr(spec_insn_sh3add_uw_rs2_addr), + .spec_rd_addr(spec_insn_sh3add_uw_rd_addr), + .spec_rd_wdata(spec_insn_sh3add_uw_rd_wdata), + .spec_pc_wdata(spec_insn_sh3add_uw_pc_wdata), + .spec_mem_addr(spec_insn_sh3add_uw_mem_addr), + .spec_mem_rmask(spec_insn_sh3add_uw_mem_rmask), + .spec_mem_wmask(spec_insn_sh3add_uw_mem_wmask), + .spec_mem_wdata(spec_insn_sh3add_uw_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slli_uw_valid; + wire spec_insn_slli_uw_trap; + wire [ 4 : 0] spec_insn_slli_uw_rs1_addr; + wire [ 4 : 0] spec_insn_slli_uw_rs2_addr; + wire [ 4 : 0] spec_insn_slli_uw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_uw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_uw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_uw_csr_misa_rmask; +`endif + + rvfi_insn_slli_uw insn_slli_uw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_uw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_uw_valid), + .spec_trap(spec_insn_slli_uw_trap), + .spec_rs1_addr(spec_insn_slli_uw_rs1_addr), + .spec_rs2_addr(spec_insn_slli_uw_rs2_addr), + .spec_rd_addr(spec_insn_slli_uw_rd_addr), + .spec_rd_wdata(spec_insn_slli_uw_rd_wdata), + .spec_pc_wdata(spec_insn_slli_uw_pc_wdata), + .spec_mem_addr(spec_insn_slli_uw_mem_addr), + .spec_mem_rmask(spec_insn_slli_uw_mem_rmask), + .spec_mem_wmask(spec_insn_slli_uw_mem_wmask), + .spec_mem_wdata(spec_insn_slli_uw_mem_wdata) + ); + + wire spec_insn_slliw_valid; + wire spec_insn_slliw_trap; + wire [ 4 : 0] spec_insn_slliw_rs1_addr; + wire [ 4 : 0] spec_insn_slliw_rs2_addr; + wire [ 4 : 0] spec_insn_slliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; +`endif + + rvfi_insn_slliw insn_slliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slliw_valid), + .spec_trap(spec_insn_slliw_trap), + .spec_rs1_addr(spec_insn_slliw_rs1_addr), + .spec_rs2_addr(spec_insn_slliw_rs2_addr), + .spec_rd_addr(spec_insn_slliw_rd_addr), + .spec_rd_wdata(spec_insn_slliw_rd_wdata), + .spec_pc_wdata(spec_insn_slliw_pc_wdata), + .spec_mem_addr(spec_insn_slliw_mem_addr), + .spec_mem_rmask(spec_insn_slliw_mem_rmask), + .spec_mem_wmask(spec_insn_slliw_mem_wmask), + .spec_mem_wdata(spec_insn_slliw_mem_wdata) + ); + + wire spec_insn_sllw_valid; + wire spec_insn_sllw_trap; + wire [ 4 : 0] spec_insn_sllw_rs1_addr; + wire [ 4 : 0] spec_insn_sllw_rs2_addr; + wire [ 4 : 0] spec_insn_sllw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; +`endif + + rvfi_insn_sllw insn_sllw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sllw_valid), + .spec_trap(spec_insn_sllw_trap), + .spec_rs1_addr(spec_insn_sllw_rs1_addr), + .spec_rs2_addr(spec_insn_sllw_rs2_addr), + .spec_rd_addr(spec_insn_sllw_rd_addr), + .spec_rd_wdata(spec_insn_sllw_rd_wdata), + .spec_pc_wdata(spec_insn_sllw_pc_wdata), + .spec_mem_addr(spec_insn_sllw_mem_addr), + .spec_mem_rmask(spec_insn_sllw_mem_rmask), + .spec_mem_wmask(spec_insn_sllw_mem_wmask), + .spec_mem_wdata(spec_insn_sllw_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_sraiw_valid; + wire spec_insn_sraiw_trap; + wire [ 4 : 0] spec_insn_sraiw_rs1_addr; + wire [ 4 : 0] spec_insn_sraiw_rs2_addr; + wire [ 4 : 0] spec_insn_sraiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; +`endif + + rvfi_insn_sraiw insn_sraiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraiw_valid), + .spec_trap(spec_insn_sraiw_trap), + .spec_rs1_addr(spec_insn_sraiw_rs1_addr), + .spec_rs2_addr(spec_insn_sraiw_rs2_addr), + .spec_rd_addr(spec_insn_sraiw_rd_addr), + .spec_rd_wdata(spec_insn_sraiw_rd_wdata), + .spec_pc_wdata(spec_insn_sraiw_pc_wdata), + .spec_mem_addr(spec_insn_sraiw_mem_addr), + .spec_mem_rmask(spec_insn_sraiw_mem_rmask), + .spec_mem_wmask(spec_insn_sraiw_mem_wmask), + .spec_mem_wdata(spec_insn_sraiw_mem_wdata) + ); + + wire spec_insn_sraw_valid; + wire spec_insn_sraw_trap; + wire [ 4 : 0] spec_insn_sraw_rs1_addr; + wire [ 4 : 0] spec_insn_sraw_rs2_addr; + wire [ 4 : 0] spec_insn_sraw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; +`endif + + rvfi_insn_sraw insn_sraw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraw_valid), + .spec_trap(spec_insn_sraw_trap), + .spec_rs1_addr(spec_insn_sraw_rs1_addr), + .spec_rs2_addr(spec_insn_sraw_rs2_addr), + .spec_rd_addr(spec_insn_sraw_rd_addr), + .spec_rd_wdata(spec_insn_sraw_rd_wdata), + .spec_pc_wdata(spec_insn_sraw_pc_wdata), + .spec_mem_addr(spec_insn_sraw_mem_addr), + .spec_mem_rmask(spec_insn_sraw_mem_rmask), + .spec_mem_wmask(spec_insn_sraw_mem_wmask), + .spec_mem_wdata(spec_insn_sraw_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_srliw_valid; + wire spec_insn_srliw_trap; + wire [ 4 : 0] spec_insn_srliw_rs1_addr; + wire [ 4 : 0] spec_insn_srliw_rs2_addr; + wire [ 4 : 0] spec_insn_srliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; +`endif + + rvfi_insn_srliw insn_srliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srliw_valid), + .spec_trap(spec_insn_srliw_trap), + .spec_rs1_addr(spec_insn_srliw_rs1_addr), + .spec_rs2_addr(spec_insn_srliw_rs2_addr), + .spec_rd_addr(spec_insn_srliw_rd_addr), + .spec_rd_wdata(spec_insn_srliw_rd_wdata), + .spec_pc_wdata(spec_insn_srliw_pc_wdata), + .spec_mem_addr(spec_insn_srliw_mem_addr), + .spec_mem_rmask(spec_insn_srliw_mem_rmask), + .spec_mem_wmask(spec_insn_srliw_mem_wmask), + .spec_mem_wdata(spec_insn_srliw_mem_wdata) + ); + + wire spec_insn_srlw_valid; + wire spec_insn_srlw_trap; + wire [ 4 : 0] spec_insn_srlw_rs1_addr; + wire [ 4 : 0] spec_insn_srlw_rs2_addr; + wire [ 4 : 0] spec_insn_srlw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; +`endif + + rvfi_insn_srlw insn_srlw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srlw_valid), + .spec_trap(spec_insn_srlw_trap), + .spec_rs1_addr(spec_insn_srlw_rs1_addr), + .spec_rs2_addr(spec_insn_srlw_rs2_addr), + .spec_rd_addr(spec_insn_srlw_rd_addr), + .spec_rd_wdata(spec_insn_srlw_rd_wdata), + .spec_pc_wdata(spec_insn_srlw_pc_wdata), + .spec_mem_addr(spec_insn_srlw_mem_addr), + .spec_mem_rmask(spec_insn_srlw_mem_rmask), + .spec_mem_wmask(spec_insn_srlw_mem_wmask), + .spec_mem_wdata(spec_insn_srlw_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_subw_valid; + wire spec_insn_subw_trap; + wire [ 4 : 0] spec_insn_subw_rs1_addr; + wire [ 4 : 0] spec_insn_subw_rs2_addr; + wire [ 4 : 0] spec_insn_subw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; +`endif + + rvfi_insn_subw insn_subw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_subw_valid), + .spec_trap(spec_insn_subw_trap), + .spec_rs1_addr(spec_insn_subw_rs1_addr), + .spec_rs2_addr(spec_insn_subw_rs2_addr), + .spec_rd_addr(spec_insn_subw_rd_addr), + .spec_rd_wdata(spec_insn_subw_rd_wdata), + .spec_pc_wdata(spec_insn_subw_pc_wdata), + .spec_mem_addr(spec_insn_subw_mem_addr), + .spec_mem_rmask(spec_insn_subw_mem_rmask), + .spec_mem_wmask(spec_insn_subw_mem_wmask), + .spec_mem_wdata(spec_insn_subw_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_add_uw_valid ? spec_insn_add_uw_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_addiw_valid ? spec_insn_addiw_valid : + spec_insn_addw_valid ? spec_insn_addw_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_ld_valid ? spec_insn_ld_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_lwu_valid ? spec_insn_lwu_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sd_valid ? spec_insn_sd_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sh1add_valid ? spec_insn_sh1add_valid : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_valid : + spec_insn_sh2add_valid ? spec_insn_sh2add_valid : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_valid : + spec_insn_sh3add_valid ? spec_insn_sh3add_valid : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_valid : + spec_insn_slliw_valid ? spec_insn_slliw_valid : + spec_insn_sllw_valid ? spec_insn_sllw_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_sraiw_valid ? spec_insn_sraiw_valid : + spec_insn_sraw_valid ? spec_insn_sraw_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_srliw_valid ? spec_insn_srliw_valid : + spec_insn_srlw_valid ? spec_insn_srlw_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_subw_valid ? spec_insn_subw_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_add_uw_valid ? spec_insn_add_uw_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_addiw_valid ? spec_insn_addiw_trap : + spec_insn_addw_valid ? spec_insn_addw_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_ld_valid ? spec_insn_ld_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_lwu_valid ? spec_insn_lwu_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sd_valid ? spec_insn_sd_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sh1add_valid ? spec_insn_sh1add_trap : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_trap : + spec_insn_sh2add_valid ? spec_insn_sh2add_trap : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_trap : + spec_insn_sh3add_valid ? spec_insn_sh3add_trap : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_trap : + spec_insn_slliw_valid ? spec_insn_slliw_trap : + spec_insn_sllw_valid ? spec_insn_sllw_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_sraiw_valid ? spec_insn_sraiw_trap : + spec_insn_sraw_valid ? spec_insn_sraw_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_srliw_valid ? spec_insn_srliw_trap : + spec_insn_srlw_valid ? spec_insn_srlw_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_subw_valid ? spec_insn_subw_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : + spec_insn_addw_valid ? spec_insn_addw_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_ld_valid ? spec_insn_ld_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sd_valid ? spec_insn_sd_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs1_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs1_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs1_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rs1_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs1_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rs1_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_subw_valid ? spec_insn_subw_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : + spec_insn_addw_valid ? spec_insn_addw_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_ld_valid ? spec_insn_ld_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sd_valid ? spec_insn_sd_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rs2_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs2_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rs2_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rs2_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rs2_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rs2_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_subw_valid ? spec_insn_subw_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : + spec_insn_addw_valid ? spec_insn_addw_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_ld_valid ? spec_insn_ld_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sd_valid ? spec_insn_sd_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rd_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rd_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_subw_valid ? spec_insn_subw_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_add_uw_valid ? spec_insn_add_uw_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : + spec_insn_addw_valid ? spec_insn_addw_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_ld_valid ? spec_insn_ld_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sd_valid ? spec_insn_sd_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_rd_wdata : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_rd_wdata : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rd_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_rd_wdata : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_rd_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_subw_valid ? spec_insn_subw_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_add_uw_valid ? spec_insn_add_uw_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : + spec_insn_addw_valid ? spec_insn_addw_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_ld_valid ? spec_insn_ld_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sd_valid ? spec_insn_sd_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_pc_wdata : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_pc_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_pc_wdata : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_pc_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_pc_wdata : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_pc_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_subw_valid ? spec_insn_subw_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : + spec_insn_addw_valid ? spec_insn_addw_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_ld_valid ? spec_insn_ld_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sd_valid ? spec_insn_sd_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_addr : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_addr : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_addr : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_addr : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_addr : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_addr : + spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : + spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : + spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : + spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_subw_valid ? spec_insn_subw_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : + spec_insn_addw_valid ? spec_insn_addw_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_ld_valid ? spec_insn_ld_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sd_valid ? spec_insn_sd_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_rmask : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_rmask : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_rmask : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_subw_valid ? spec_insn_subw_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : + spec_insn_addw_valid ? spec_insn_addw_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_ld_valid ? spec_insn_ld_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sd_valid ? spec_insn_sd_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wmask : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wmask : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_wmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wmask : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_wmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_subw_valid ? spec_insn_subw_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : + spec_insn_addw_valid ? spec_insn_addw_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_ld_valid ? spec_insn_ld_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sd_valid ? spec_insn_sd_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wdata : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wdata : + spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wdata : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_wdata : + spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wdata : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_subw_valid ? spec_insn_subw_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_add_uw_valid ? spec_insn_add_uw_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : + spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sh1add_valid ? spec_insn_sh1add_csr_misa_rmask : + spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_csr_misa_rmask : + spec_insn_sh2add_valid ? spec_insn_sh2add_csr_misa_rmask : + spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_csr_misa_rmask : + spec_insn_sh3add_valid ? spec_insn_sh3add_csr_misa_rmask : + spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slli_uw_valid ? spec_insn_slli_uw_csr_misa_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; +`endif +endmodule From 9c356b49452c796279c741ce879441e5e3d424ac Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 3 Oct 2024 12:08:46 +1300 Subject: [PATCH 02/11] Next comes Zbb - Add B-type format. - Implement (most) Zbb instructions. - Add `insnt_count` and `insn_ext` for bit count and extension instructions. - Be unconvinced that the count checks will work as intended. - Be confused about `orc_b` and `rev8` instructions and leave them commented out for now. --- insns/generate.py | 127 ++ insns/insn_andn.v | 59 + insns/insn_clz.v | 71 + insns/insn_clzw.v | 71 + insns/insn_cpop.v | 70 + insns/insn_cpopw.v | 70 + insns/insn_ctz.v | 73 + insns/insn_ctzw.v | 73 + insns/insn_max.v | 59 + insns/insn_maxu.v | 59 + insns/insn_min.v | 59 + insns/insn_minu.v | 59 + insns/insn_orn.v | 59 + insns/insn_rol.v | 60 + insns/insn_rolw.v | 60 + insns/insn_ror.v | 60 + insns/insn_rori.v | 59 + insns/insn_roriw.v | 59 + insns/insn_rorw.v | 60 + insns/insn_sext_b.v | 59 + insns/insn_sext_h.v | 59 + insns/insn_xnor.v | 59 + insns/insn_zext_h.v | 59 + insns/isa_rv32iZbb.txt | 53 + insns/isa_rv32iZbb.v | 2744 ++++++++++++++++++++++++++++++ insns/isa_rv32ib.txt | 16 + insns/isa_rv32ib.v | 840 ++++++++- insns/isa_rv64iZbb.txt | 71 + insns/isa_rv64iZbb.v | 3662 ++++++++++++++++++++++++++++++++++++++++ insns/isa_rv64ib.txt | 22 + insns/isa_rv64ib.v | 1146 ++++++++++++- 31 files changed, 10033 insertions(+), 24 deletions(-) create mode 100644 insns/insn_andn.v create mode 100644 insns/insn_clz.v create mode 100644 insns/insn_clzw.v create mode 100644 insns/insn_cpop.v create mode 100644 insns/insn_cpopw.v create mode 100644 insns/insn_ctz.v create mode 100644 insns/insn_ctzw.v create mode 100644 insns/insn_max.v create mode 100644 insns/insn_maxu.v create mode 100644 insns/insn_min.v create mode 100644 insns/insn_minu.v create mode 100644 insns/insn_orn.v create mode 100644 insns/insn_rol.v create mode 100644 insns/insn_rolw.v create mode 100644 insns/insn_ror.v create mode 100644 insns/insn_rori.v create mode 100644 insns/insn_roriw.v create mode 100644 insns/insn_rorw.v create mode 100644 insns/insn_sext_b.v create mode 100644 insns/insn_sext_h.v create mode 100644 insns/insn_xnor.v create mode 100644 insns/insn_zext_h.v create mode 100644 insns/isa_rv32iZbb.txt create mode 100644 insns/isa_rv32iZbb.v create mode 100644 insns/isa_rv64iZbb.txt create mode 100644 insns/isa_rv64iZbb.v diff --git a/insns/generate.py b/insns/generate.py index 8f4f9b6d..f932cb98 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -195,6 +195,18 @@ def format_i_shift(f): print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) +def format_b(f): + print("", file=f) + # TODO: figure out if there is an official name for this format + print(" // B-type instruction format", file=f) + print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) + print(" wire [6:0] insn_funct7 = rvfi_insn[31:25];", file=f) + print(" wire [4:0] insn_funct5 = rvfi_insn[24:20];", file=f) + print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) + print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) + print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) + print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) + def format_s(f): print("", file=f) print(" // S-type instruction format", file=f) @@ -1112,6 +1124,95 @@ def insn_c_mvadd(insn, funct4, add, misa=MISA_C): footer(f) +def insn_count(insn, funct5, trailing=False, pop=False, wmode=False, misa=MISA_B): + with open("insn_%s.v" % insn, "w") as f: + header(f, insn) + format_b(f) + misa_check(f, misa) + + if wmode: + result_width = "32" + result_range = "31:0" + opcode = "0011011" + else: + result_width = "`RISCV_FORMAL_XLEN" + result_range = "`RISCV_FORMAL_XLEN-1:0" + opcode = "0010011" + + print("", file=f) + print(" // %s instruction" % insn.upper(), file=f) + print(" integer i;", file=f) + print(" reg [%s] result;" % result_range, file=f) + print(" reg found;", file=f) + + print(" always @(rvfi_rs1_rdata)", file=f) + print(" begin", file=f) + print(" result = 0;", file=f) + print(" found = 0;", file=f) + print(f" for (i=0; i<{result_width}; i=i+1)", file=f) + print(" begin", file=f) + if pop: # count all ones + assert not trailing + print(" result = result + rvfi_rs1_rdata[i];", file=f) + elif trailing: # count trailing zeros + print(" if (rvfi_rs1_rdata[i] == 1'b1)", file=f) + print(" result = 0;", file=f) + print(" else", file=f) + print(" result = result + 1;", file=f) + else: # count leading zeros + print(" found = found | rvfi_rs1_rdata[i];", file=f) + print(" result = result + ~(rvfi_rs1_rdata[i] | found);", file=f) + print(" end", file=f) + print(" end", file=f) + + assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b %s && insn_funct3 == 3'b 001 && insn_opcode == 7'b %s" % (funct5, opcode)) + assign(f, "spec_rs1_addr", "insn_rs1") + assign(f, "spec_rs2_addr", "insn_rs2") + assign(f, "spec_rd_addr", "insn_rd") + if wmode: + assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0") + else: + assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") + assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") + + footer(f) + +def insn_ext(insn, funct5, signed=False, bmode=False, misa=MISA_B): + with open("insn_%s.v" % insn, "w") as f: + header(f, insn) + format_b(f) + misa_check(f, misa) + + if bmode: + result_width = "8" + opcode = "0011011" + else: # hmode + result_width = "16" + opcode = "0010011" + + if signed: + funct7 = "0110000" + funct3 = "001" + opcode = "0010011" + result_extension = f"result[{result_width}-1]" + else: + funct7 = "0000100" + funct3 = "100" + opcode = "{011, `RISCV_FORMAL_XLEN != 32, 011}" + result_extension = "0" + + print("", file=f) + print(" // %s instruction" % insn.upper(), file=f) + print(" wire [%s-1:0] result = rvfi_rs1_rdata[%s-1:0];" % (result_width, result_width), file=f) + assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct7 == 7'b %s && insn_funct5 == 5'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s" % (funct7, funct5, funct3, opcode)) + assign(f, "spec_rs1_addr", "insn_rs1") + assign(f, "spec_rs2_addr", "insn_rs2") + assign(f, "spec_rd_addr", "insn_rd") + assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-%s{%s}}, result} : 0" % (result_width, result_extension)) + assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") + + footer(f) + ## Base Integer ISA (I) current_isa = ["rv32i"] @@ -1272,8 +1373,34 @@ def insn_c_mvadd(insn, funct4, add, misa=MISA_C): current_isa = ["rv32iZbb"] +insn_alu("andn", "0100000", "111", "rvfi_rs1_rdata & ~rvfi_rs2_rdata", misa=MISA_B) +insn_alu("orn", "0100000", "110", "rvfi_rs1_rdata | ~rvfi_rs2_rdata", misa=MISA_B) +insn_alu("xnor", "0100000", "100", "~(rvfi_rs1_rdata ^ rvfi_rs2_rdata)", misa=MISA_B) +insn_count("clz", "00000", misa=MISA_B) +insn_count("ctz", "00001", trailing=True, misa=MISA_B) +insn_count("cpop", "00010", pop=True, misa=MISA_B) +insn_alu("max", "0000101", "110", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs2_rdata : rvfi_rs1_rdata", misa=MISA_B) +insn_alu("maxu", "0000101", "111", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs2_rdata : rvfi_rs1_rdata", misa=MISA_B) +insn_alu("min", "0000101", "100", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs1_rdata : rvfi_rs2_rdata", misa=MISA_B) +insn_alu("minu", "0000101", "101", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs1_rdata : rvfi_rs2_rdata", misa=MISA_B) +insn_ext("sext_b", "00100", signed=True, bmode=True, misa=MISA_B) +insn_ext("sext_h", "00101", signed=True, misa=MISA_B) +insn_ext("zext_h", "00000", misa=MISA_B) +insn_alu("rol", "0110000", "001", "(rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) +insn_alu("ror", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) +insn_shimm("rori", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt))", misa=MISA_B) +# insn_("orc_b", "001010000111", "101", "", misa=MISA_B) +# insn_("rev8", "011010011000", "101", "", misa=MISA_B) + current_isa = ["rv64iZbb"] +insn_count("clzw", "00000", wmode=True, misa=MISA_B) +insn_count("ctzw", "00001", trailing=True, wmode=True, misa=MISA_B) +insn_count("cpopw", "00010", pop=True, wmode=True, misa=MISA_B) +insn_alu("rolw", "0110000", "001", "(rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) +insn_alu("rorw", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) +insn_shimm("roriw", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt))", wmode=True, misa=MISA_B) + ### Zbs: Single-bit instructions current_isa = ["rv32iZbs"] diff --git a/insns/insn_andn.v b/insns/insn_andn.v new file mode 100644 index 00000000..d3d821c2 --- /dev/null +++ b/insns/insn_andn.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_andn ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ANDN instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & ~rvfi_rs2_rdata; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_clz.v b/insns/insn_clz.v new file mode 100644 index 00000000..3ee8d348 --- /dev/null +++ b/insns/insn_clz.v @@ -0,0 +1,71 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_clz ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // CLZ instruction + integer i; + reg [`RISCV_FORMAL_XLEN-1:0] result; + reg found; + always @(rvfi_rs1_rdata) + begin + result = 0; + found = 0; + for (i=0; i<`RISCV_FORMAL_XLEN; i=i+1) + begin + found = found | rvfi_rs1_rdata[i]; + result = result + ~(rvfi_rs1_rdata[i] | found); + end + end + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_clzw.v b/insns/insn_clzw.v new file mode 100644 index 00000000..f4974126 --- /dev/null +++ b/insns/insn_clzw.v @@ -0,0 +1,71 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_clzw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // CLZW instruction + integer i; + reg [31:0] result; + reg found; + always @(rvfi_rs1_rdata) + begin + result = 0; + found = 0; + for (i=0; i<32; i=i+1) + begin + found = found | rvfi_rs1_rdata[i]; + result = result + ~(rvfi_rs1_rdata[i] | found); + end + end + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_cpop.v b/insns/insn_cpop.v new file mode 100644 index 00000000..39c881a6 --- /dev/null +++ b/insns/insn_cpop.v @@ -0,0 +1,70 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_cpop ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // CPOP instruction + integer i; + reg [`RISCV_FORMAL_XLEN-1:0] result; + reg found; + always @(rvfi_rs1_rdata) + begin + result = 0; + found = 0; + for (i=0; i<`RISCV_FORMAL_XLEN; i=i+1) + begin + result = result + rvfi_rs1_rdata[i]; + end + end + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_cpopw.v b/insns/insn_cpopw.v new file mode 100644 index 00000000..9b0e81ec --- /dev/null +++ b/insns/insn_cpopw.v @@ -0,0 +1,70 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_cpopw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // CPOPW instruction + integer i; + reg [31:0] result; + reg found; + always @(rvfi_rs1_rdata) + begin + result = 0; + found = 0; + for (i=0; i<32; i=i+1) + begin + result = result + rvfi_rs1_rdata[i]; + end + end + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_ctz.v b/insns/insn_ctz.v new file mode 100644 index 00000000..3ccb2615 --- /dev/null +++ b/insns/insn_ctz.v @@ -0,0 +1,73 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_ctz ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // CTZ instruction + integer i; + reg [`RISCV_FORMAL_XLEN-1:0] result; + reg found; + always @(rvfi_rs1_rdata) + begin + result = 0; + found = 0; + for (i=0; i<`RISCV_FORMAL_XLEN; i=i+1) + begin + if (rvfi_rs1_rdata[i] == 1'b1) + result = 0; + else + result = result + 1; + end + end + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_ctzw.v b/insns/insn_ctzw.v new file mode 100644 index 00000000..991d0217 --- /dev/null +++ b/insns/insn_ctzw.v @@ -0,0 +1,73 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_ctzw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // CTZW instruction + integer i; + reg [31:0] result; + reg found; + always @(rvfi_rs1_rdata) + begin + result = 0; + found = 0; + for (i=0; i<32; i=i+1) + begin + if (rvfi_rs1_rdata[i] == 1'b1) + result = 0; + else + result = result + 1; + end + end + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_max.v b/insns/insn_max.v new file mode 100644 index 00000000..45fea18a --- /dev/null +++ b/insns/insn_max.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_max ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // MAX instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs2_rdata : rvfi_rs1_rdata; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000101 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_maxu.v b/insns/insn_maxu.v new file mode 100644 index 00000000..60e488c8 --- /dev/null +++ b/insns/insn_maxu.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_maxu ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // MAXU instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs2_rdata : rvfi_rs1_rdata; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000101 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_min.v b/insns/insn_min.v new file mode 100644 index 00000000..40da856f --- /dev/null +++ b/insns/insn_min.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_min ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // MIN instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs1_rdata : rvfi_rs2_rdata; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000101 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_minu.v b/insns/insn_minu.v new file mode 100644 index 00000000..ec9b684d --- /dev/null +++ b/insns/insn_minu.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_minu ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // MINU instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs1_rdata : rvfi_rs2_rdata; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000101 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_orn.v b/insns/insn_orn.v new file mode 100644 index 00000000..b9413a27 --- /dev/null +++ b/insns/insn_orn.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_orn ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ORN instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | ~rvfi_rs2_rdata; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_rol.v b/insns/insn_rol.v new file mode 100644 index 00000000..999771bd --- /dev/null +++ b/insns/insn_rol.v @@ -0,0 +1,60 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_rol ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ROL instruction + wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0]; + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (`RISCV_FORMAL_XLEN - shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_rolw.v b/insns/insn_rolw.v new file mode 100644 index 00000000..afc2845e --- /dev/null +++ b/insns/insn_rolw.v @@ -0,0 +1,60 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_rolw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ROLW instruction + wire [4:0] shamt = rvfi_rs2_rdata[4:0]; + wire [31:0] result = (rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (32 - shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0111011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_ror.v b/insns/insn_ror.v new file mode 100644 index 00000000..0ba2916c --- /dev/null +++ b/insns/insn_ror.v @@ -0,0 +1,60 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_ror ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ROR instruction + wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0]; + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_rori.v b/insns/insn_rori.v new file mode 100644 index 00000000..4c5fb393 --- /dev/null +++ b/insns/insn_rori.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_rori ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // I-type instruction format (shift variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // RORI instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_rs1_addr = insn_rs1; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_rs2_addr = 0; + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_roriw.v b/insns/insn_roriw.v new file mode 100644 index 00000000..d1de58de --- /dev/null +++ b/insns/insn_roriw.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_roriw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // I-type instruction format (shift variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // RORIW instruction + wire [31:0] result = (rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; + assign spec_rs1_addr = insn_rs1; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_rs2_addr = 0; + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_rorw.v b/insns/insn_rorw.v new file mode 100644 index 00000000..b3bf7e24 --- /dev/null +++ b/insns/insn_rorw.v @@ -0,0 +1,60 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_rorw ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // RORW instruction + wire [4:0] shamt = rvfi_rs2_rdata[4:0]; + wire [31:0] result = (rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sext_b.v b/insns/insn_sext_b.v new file mode 100644 index 00000000..e5785c4a --- /dev/null +++ b/insns/insn_sext_b.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sext_b ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SEXT_B instruction + wire [8-1:0] result = rvfi_rs1_rdata[8-1:0]; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-8{result[8-1]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_sext_h.v b/insns/insn_sext_h.v new file mode 100644 index 00000000..77c30e9f --- /dev/null +++ b/insns/insn_sext_h.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_sext_h ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // SEXT_H instruction + wire [16-1:0] result = rvfi_rs1_rdata[16-1:0]; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00101 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-16{result[16-1]}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_xnor.v b/insns/insn_xnor.v new file mode 100644 index 00000000..638b9abf --- /dev/null +++ b/insns/insn_xnor.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_xnor ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // XNOR instruction + wire [`RISCV_FORMAL_XLEN-1:0] result = ~(rvfi_rs1_rdata ^ rvfi_rs2_rdata); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_zext_h.v b/insns/insn_zext_h.v new file mode 100644 index 00000000..d60c7be4 --- /dev/null +++ b/insns/insn_zext_h.v @@ -0,0 +1,59 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_zext_h ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // B-type instruction format + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [4:0] insn_funct5 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ZEXT_H instruction + wire [16-1:0] result = rvfi_rs1_rdata[16-1:0]; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000100 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b {011, `RISCV_FORMAL_XLEN != 32, 011}; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-16{0}}, result} : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/isa_rv32iZbb.txt b/insns/isa_rv32iZbb.txt new file mode 100644 index 00000000..4777c312 --- /dev/null +++ b/insns/isa_rv32iZbb.txt @@ -0,0 +1,53 @@ +add +addi +and +andi +andn +auipc +beq +bge +bgeu +blt +bltu +bne +clz +cpop +ctz +jal +jalr +lb +lbu +lh +lhu +lui +lw +max +maxu +min +minu +or +ori +orn +rol +ror +rori +sb +sext_b +sext_h +sh +sll +slli +slt +slti +sltiu +sltu +sra +srai +srl +srli +sub +sw +xnor +xor +xori +zext_h diff --git a/insns/isa_rv32iZbb.v b/insns/isa_rv32iZbb.v new file mode 100644 index 00000000..fbf6c300 --- /dev/null +++ b/insns/isa_rv32iZbb.v @@ -0,0 +1,2744 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv32iZbb ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_andn_valid; + wire spec_insn_andn_trap; + wire [ 4 : 0] spec_insn_andn_rs1_addr; + wire [ 4 : 0] spec_insn_andn_rs2_addr; + wire [ 4 : 0] spec_insn_andn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_csr_misa_rmask; +`endif + + rvfi_insn_andn insn_andn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andn_valid), + .spec_trap(spec_insn_andn_trap), + .spec_rs1_addr(spec_insn_andn_rs1_addr), + .spec_rs2_addr(spec_insn_andn_rs2_addr), + .spec_rd_addr(spec_insn_andn_rd_addr), + .spec_rd_wdata(spec_insn_andn_rd_wdata), + .spec_pc_wdata(spec_insn_andn_pc_wdata), + .spec_mem_addr(spec_insn_andn_mem_addr), + .spec_mem_rmask(spec_insn_andn_mem_rmask), + .spec_mem_wmask(spec_insn_andn_mem_wmask), + .spec_mem_wdata(spec_insn_andn_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_clz_valid; + wire spec_insn_clz_trap; + wire [ 4 : 0] spec_insn_clz_rs1_addr; + wire [ 4 : 0] spec_insn_clz_rs2_addr; + wire [ 4 : 0] spec_insn_clz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_csr_misa_rmask; +`endif + + rvfi_insn_clz insn_clz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_clz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_clz_valid), + .spec_trap(spec_insn_clz_trap), + .spec_rs1_addr(spec_insn_clz_rs1_addr), + .spec_rs2_addr(spec_insn_clz_rs2_addr), + .spec_rd_addr(spec_insn_clz_rd_addr), + .spec_rd_wdata(spec_insn_clz_rd_wdata), + .spec_pc_wdata(spec_insn_clz_pc_wdata), + .spec_mem_addr(spec_insn_clz_mem_addr), + .spec_mem_rmask(spec_insn_clz_mem_rmask), + .spec_mem_wmask(spec_insn_clz_mem_wmask), + .spec_mem_wdata(spec_insn_clz_mem_wdata) + ); + + wire spec_insn_cpop_valid; + wire spec_insn_cpop_trap; + wire [ 4 : 0] spec_insn_cpop_rs1_addr; + wire [ 4 : 0] spec_insn_cpop_rs2_addr; + wire [ 4 : 0] spec_insn_cpop_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_csr_misa_rmask; +`endif + + rvfi_insn_cpop insn_cpop ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_cpop_csr_misa_rmask), +`endif + .spec_valid(spec_insn_cpop_valid), + .spec_trap(spec_insn_cpop_trap), + .spec_rs1_addr(spec_insn_cpop_rs1_addr), + .spec_rs2_addr(spec_insn_cpop_rs2_addr), + .spec_rd_addr(spec_insn_cpop_rd_addr), + .spec_rd_wdata(spec_insn_cpop_rd_wdata), + .spec_pc_wdata(spec_insn_cpop_pc_wdata), + .spec_mem_addr(spec_insn_cpop_mem_addr), + .spec_mem_rmask(spec_insn_cpop_mem_rmask), + .spec_mem_wmask(spec_insn_cpop_mem_wmask), + .spec_mem_wdata(spec_insn_cpop_mem_wdata) + ); + + wire spec_insn_ctz_valid; + wire spec_insn_ctz_trap; + wire [ 4 : 0] spec_insn_ctz_rs1_addr; + wire [ 4 : 0] spec_insn_ctz_rs2_addr; + wire [ 4 : 0] spec_insn_ctz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_csr_misa_rmask; +`endif + + rvfi_insn_ctz insn_ctz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ctz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ctz_valid), + .spec_trap(spec_insn_ctz_trap), + .spec_rs1_addr(spec_insn_ctz_rs1_addr), + .spec_rs2_addr(spec_insn_ctz_rs2_addr), + .spec_rd_addr(spec_insn_ctz_rd_addr), + .spec_rd_wdata(spec_insn_ctz_rd_wdata), + .spec_pc_wdata(spec_insn_ctz_pc_wdata), + .spec_mem_addr(spec_insn_ctz_mem_addr), + .spec_mem_rmask(spec_insn_ctz_mem_rmask), + .spec_mem_wmask(spec_insn_ctz_mem_wmask), + .spec_mem_wdata(spec_insn_ctz_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_max_valid; + wire spec_insn_max_trap; + wire [ 4 : 0] spec_insn_max_rs1_addr; + wire [ 4 : 0] spec_insn_max_rs2_addr; + wire [ 4 : 0] spec_insn_max_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_csr_misa_rmask; +`endif + + rvfi_insn_max insn_max ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_max_csr_misa_rmask), +`endif + .spec_valid(spec_insn_max_valid), + .spec_trap(spec_insn_max_trap), + .spec_rs1_addr(spec_insn_max_rs1_addr), + .spec_rs2_addr(spec_insn_max_rs2_addr), + .spec_rd_addr(spec_insn_max_rd_addr), + .spec_rd_wdata(spec_insn_max_rd_wdata), + .spec_pc_wdata(spec_insn_max_pc_wdata), + .spec_mem_addr(spec_insn_max_mem_addr), + .spec_mem_rmask(spec_insn_max_mem_rmask), + .spec_mem_wmask(spec_insn_max_mem_wmask), + .spec_mem_wdata(spec_insn_max_mem_wdata) + ); + + wire spec_insn_maxu_valid; + wire spec_insn_maxu_trap; + wire [ 4 : 0] spec_insn_maxu_rs1_addr; + wire [ 4 : 0] spec_insn_maxu_rs2_addr; + wire [ 4 : 0] spec_insn_maxu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_csr_misa_rmask; +`endif + + rvfi_insn_maxu insn_maxu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_maxu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_maxu_valid), + .spec_trap(spec_insn_maxu_trap), + .spec_rs1_addr(spec_insn_maxu_rs1_addr), + .spec_rs2_addr(spec_insn_maxu_rs2_addr), + .spec_rd_addr(spec_insn_maxu_rd_addr), + .spec_rd_wdata(spec_insn_maxu_rd_wdata), + .spec_pc_wdata(spec_insn_maxu_pc_wdata), + .spec_mem_addr(spec_insn_maxu_mem_addr), + .spec_mem_rmask(spec_insn_maxu_mem_rmask), + .spec_mem_wmask(spec_insn_maxu_mem_wmask), + .spec_mem_wdata(spec_insn_maxu_mem_wdata) + ); + + wire spec_insn_min_valid; + wire spec_insn_min_trap; + wire [ 4 : 0] spec_insn_min_rs1_addr; + wire [ 4 : 0] spec_insn_min_rs2_addr; + wire [ 4 : 0] spec_insn_min_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_csr_misa_rmask; +`endif + + rvfi_insn_min insn_min ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_min_csr_misa_rmask), +`endif + .spec_valid(spec_insn_min_valid), + .spec_trap(spec_insn_min_trap), + .spec_rs1_addr(spec_insn_min_rs1_addr), + .spec_rs2_addr(spec_insn_min_rs2_addr), + .spec_rd_addr(spec_insn_min_rd_addr), + .spec_rd_wdata(spec_insn_min_rd_wdata), + .spec_pc_wdata(spec_insn_min_pc_wdata), + .spec_mem_addr(spec_insn_min_mem_addr), + .spec_mem_rmask(spec_insn_min_mem_rmask), + .spec_mem_wmask(spec_insn_min_mem_wmask), + .spec_mem_wdata(spec_insn_min_mem_wdata) + ); + + wire spec_insn_minu_valid; + wire spec_insn_minu_trap; + wire [ 4 : 0] spec_insn_minu_rs1_addr; + wire [ 4 : 0] spec_insn_minu_rs2_addr; + wire [ 4 : 0] spec_insn_minu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_csr_misa_rmask; +`endif + + rvfi_insn_minu insn_minu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_minu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_minu_valid), + .spec_trap(spec_insn_minu_trap), + .spec_rs1_addr(spec_insn_minu_rs1_addr), + .spec_rs2_addr(spec_insn_minu_rs2_addr), + .spec_rd_addr(spec_insn_minu_rd_addr), + .spec_rd_wdata(spec_insn_minu_rd_wdata), + .spec_pc_wdata(spec_insn_minu_pc_wdata), + .spec_mem_addr(spec_insn_minu_mem_addr), + .spec_mem_rmask(spec_insn_minu_mem_rmask), + .spec_mem_wmask(spec_insn_minu_mem_wmask), + .spec_mem_wdata(spec_insn_minu_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_orn_valid; + wire spec_insn_orn_trap; + wire [ 4 : 0] spec_insn_orn_rs1_addr; + wire [ 4 : 0] spec_insn_orn_rs2_addr; + wire [ 4 : 0] spec_insn_orn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_csr_misa_rmask; +`endif + + rvfi_insn_orn insn_orn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_orn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_orn_valid), + .spec_trap(spec_insn_orn_trap), + .spec_rs1_addr(spec_insn_orn_rs1_addr), + .spec_rs2_addr(spec_insn_orn_rs2_addr), + .spec_rd_addr(spec_insn_orn_rd_addr), + .spec_rd_wdata(spec_insn_orn_rd_wdata), + .spec_pc_wdata(spec_insn_orn_pc_wdata), + .spec_mem_addr(spec_insn_orn_mem_addr), + .spec_mem_rmask(spec_insn_orn_mem_rmask), + .spec_mem_wmask(spec_insn_orn_mem_wmask), + .spec_mem_wdata(spec_insn_orn_mem_wdata) + ); + + wire spec_insn_rol_valid; + wire spec_insn_rol_trap; + wire [ 4 : 0] spec_insn_rol_rs1_addr; + wire [ 4 : 0] spec_insn_rol_rs2_addr; + wire [ 4 : 0] spec_insn_rol_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_csr_misa_rmask; +`endif + + rvfi_insn_rol insn_rol ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rol_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rol_valid), + .spec_trap(spec_insn_rol_trap), + .spec_rs1_addr(spec_insn_rol_rs1_addr), + .spec_rs2_addr(spec_insn_rol_rs2_addr), + .spec_rd_addr(spec_insn_rol_rd_addr), + .spec_rd_wdata(spec_insn_rol_rd_wdata), + .spec_pc_wdata(spec_insn_rol_pc_wdata), + .spec_mem_addr(spec_insn_rol_mem_addr), + .spec_mem_rmask(spec_insn_rol_mem_rmask), + .spec_mem_wmask(spec_insn_rol_mem_wmask), + .spec_mem_wdata(spec_insn_rol_mem_wdata) + ); + + wire spec_insn_ror_valid; + wire spec_insn_ror_trap; + wire [ 4 : 0] spec_insn_ror_rs1_addr; + wire [ 4 : 0] spec_insn_ror_rs2_addr; + wire [ 4 : 0] spec_insn_ror_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_csr_misa_rmask; +`endif + + rvfi_insn_ror insn_ror ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ror_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ror_valid), + .spec_trap(spec_insn_ror_trap), + .spec_rs1_addr(spec_insn_ror_rs1_addr), + .spec_rs2_addr(spec_insn_ror_rs2_addr), + .spec_rd_addr(spec_insn_ror_rd_addr), + .spec_rd_wdata(spec_insn_ror_rd_wdata), + .spec_pc_wdata(spec_insn_ror_pc_wdata), + .spec_mem_addr(spec_insn_ror_mem_addr), + .spec_mem_rmask(spec_insn_ror_mem_rmask), + .spec_mem_wmask(spec_insn_ror_mem_wmask), + .spec_mem_wdata(spec_insn_ror_mem_wdata) + ); + + wire spec_insn_rori_valid; + wire spec_insn_rori_trap; + wire [ 4 : 0] spec_insn_rori_rs1_addr; + wire [ 4 : 0] spec_insn_rori_rs2_addr; + wire [ 4 : 0] spec_insn_rori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_csr_misa_rmask; +`endif + + rvfi_insn_rori insn_rori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rori_valid), + .spec_trap(spec_insn_rori_trap), + .spec_rs1_addr(spec_insn_rori_rs1_addr), + .spec_rs2_addr(spec_insn_rori_rs2_addr), + .spec_rd_addr(spec_insn_rori_rd_addr), + .spec_rd_wdata(spec_insn_rori_rd_wdata), + .spec_pc_wdata(spec_insn_rori_pc_wdata), + .spec_mem_addr(spec_insn_rori_mem_addr), + .spec_mem_rmask(spec_insn_rori_mem_rmask), + .spec_mem_wmask(spec_insn_rori_mem_wmask), + .spec_mem_wdata(spec_insn_rori_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sext_b_valid; + wire spec_insn_sext_b_trap; + wire [ 4 : 0] spec_insn_sext_b_rs1_addr; + wire [ 4 : 0] spec_insn_sext_b_rs2_addr; + wire [ 4 : 0] spec_insn_sext_b_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_csr_misa_rmask; +`endif + + rvfi_insn_sext_b insn_sext_b ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_b_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_b_valid), + .spec_trap(spec_insn_sext_b_trap), + .spec_rs1_addr(spec_insn_sext_b_rs1_addr), + .spec_rs2_addr(spec_insn_sext_b_rs2_addr), + .spec_rd_addr(spec_insn_sext_b_rd_addr), + .spec_rd_wdata(spec_insn_sext_b_rd_wdata), + .spec_pc_wdata(spec_insn_sext_b_pc_wdata), + .spec_mem_addr(spec_insn_sext_b_mem_addr), + .spec_mem_rmask(spec_insn_sext_b_mem_rmask), + .spec_mem_wmask(spec_insn_sext_b_mem_wmask), + .spec_mem_wdata(spec_insn_sext_b_mem_wdata) + ); + + wire spec_insn_sext_h_valid; + wire spec_insn_sext_h_trap; + wire [ 4 : 0] spec_insn_sext_h_rs1_addr; + wire [ 4 : 0] spec_insn_sext_h_rs2_addr; + wire [ 4 : 0] spec_insn_sext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_csr_misa_rmask; +`endif + + rvfi_insn_sext_h insn_sext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_h_valid), + .spec_trap(spec_insn_sext_h_trap), + .spec_rs1_addr(spec_insn_sext_h_rs1_addr), + .spec_rs2_addr(spec_insn_sext_h_rs2_addr), + .spec_rd_addr(spec_insn_sext_h_rd_addr), + .spec_rd_wdata(spec_insn_sext_h_rd_wdata), + .spec_pc_wdata(spec_insn_sext_h_pc_wdata), + .spec_mem_addr(spec_insn_sext_h_mem_addr), + .spec_mem_rmask(spec_insn_sext_h_mem_rmask), + .spec_mem_wmask(spec_insn_sext_h_mem_wmask), + .spec_mem_wdata(spec_insn_sext_h_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xnor_valid; + wire spec_insn_xnor_trap; + wire [ 4 : 0] spec_insn_xnor_rs1_addr; + wire [ 4 : 0] spec_insn_xnor_rs2_addr; + wire [ 4 : 0] spec_insn_xnor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_csr_misa_rmask; +`endif + + rvfi_insn_xnor insn_xnor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xnor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xnor_valid), + .spec_trap(spec_insn_xnor_trap), + .spec_rs1_addr(spec_insn_xnor_rs1_addr), + .spec_rs2_addr(spec_insn_xnor_rs2_addr), + .spec_rd_addr(spec_insn_xnor_rd_addr), + .spec_rd_wdata(spec_insn_xnor_rd_wdata), + .spec_pc_wdata(spec_insn_xnor_pc_wdata), + .spec_mem_addr(spec_insn_xnor_mem_addr), + .spec_mem_rmask(spec_insn_xnor_mem_rmask), + .spec_mem_wmask(spec_insn_xnor_mem_wmask), + .spec_mem_wdata(spec_insn_xnor_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + wire spec_insn_zext_h_valid; + wire spec_insn_zext_h_trap; + wire [ 4 : 0] spec_insn_zext_h_rs1_addr; + wire [ 4 : 0] spec_insn_zext_h_rs2_addr; + wire [ 4 : 0] spec_insn_zext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_csr_misa_rmask; +`endif + + rvfi_insn_zext_h insn_zext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_zext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_zext_h_valid), + .spec_trap(spec_insn_zext_h_trap), + .spec_rs1_addr(spec_insn_zext_h_rs1_addr), + .spec_rs2_addr(spec_insn_zext_h_rs2_addr), + .spec_rd_addr(spec_insn_zext_h_rd_addr), + .spec_rd_wdata(spec_insn_zext_h_rd_wdata), + .spec_pc_wdata(spec_insn_zext_h_pc_wdata), + .spec_mem_addr(spec_insn_zext_h_mem_addr), + .spec_mem_rmask(spec_insn_zext_h_mem_rmask), + .spec_mem_wmask(spec_insn_zext_h_mem_wmask), + .spec_mem_wdata(spec_insn_zext_h_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_andn_valid ? spec_insn_andn_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_clz_valid ? spec_insn_clz_valid : + spec_insn_cpop_valid ? spec_insn_cpop_valid : + spec_insn_ctz_valid ? spec_insn_ctz_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_max_valid ? spec_insn_max_valid : + spec_insn_maxu_valid ? spec_insn_maxu_valid : + spec_insn_min_valid ? spec_insn_min_valid : + spec_insn_minu_valid ? spec_insn_minu_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_orn_valid ? spec_insn_orn_valid : + spec_insn_rol_valid ? spec_insn_rol_valid : + spec_insn_ror_valid ? spec_insn_ror_valid : + spec_insn_rori_valid ? spec_insn_rori_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sext_b_valid ? spec_insn_sext_b_valid : + spec_insn_sext_h_valid ? spec_insn_sext_h_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xnor_valid ? spec_insn_xnor_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : + spec_insn_zext_h_valid ? spec_insn_zext_h_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_andn_valid ? spec_insn_andn_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_clz_valid ? spec_insn_clz_trap : + spec_insn_cpop_valid ? spec_insn_cpop_trap : + spec_insn_ctz_valid ? spec_insn_ctz_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_max_valid ? spec_insn_max_trap : + spec_insn_maxu_valid ? spec_insn_maxu_trap : + spec_insn_min_valid ? spec_insn_min_trap : + spec_insn_minu_valid ? spec_insn_minu_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_orn_valid ? spec_insn_orn_trap : + spec_insn_rol_valid ? spec_insn_rol_trap : + spec_insn_ror_valid ? spec_insn_ror_trap : + spec_insn_rori_valid ? spec_insn_rori_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sext_b_valid ? spec_insn_sext_b_trap : + spec_insn_sext_h_valid ? spec_insn_sext_h_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xnor_valid ? spec_insn_xnor_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : + spec_insn_zext_h_valid ? spec_insn_zext_h_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_andn_valid ? spec_insn_andn_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_clz_valid ? spec_insn_clz_rs1_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs1_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_max_valid ? spec_insn_max_rs1_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs1_addr : + spec_insn_min_valid ? spec_insn_min_rs1_addr : + spec_insn_minu_valid ? spec_insn_minu_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_orn_valid ? spec_insn_orn_rs1_addr : + spec_insn_rol_valid ? spec_insn_rol_rs1_addr : + spec_insn_ror_valid ? spec_insn_ror_rs1_addr : + spec_insn_rori_valid ? spec_insn_rori_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs1_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_andn_valid ? spec_insn_andn_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_clz_valid ? spec_insn_clz_rs2_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs2_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_max_valid ? spec_insn_max_rs2_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs2_addr : + spec_insn_min_valid ? spec_insn_min_rs2_addr : + spec_insn_minu_valid ? spec_insn_minu_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_orn_valid ? spec_insn_orn_rs2_addr : + spec_insn_rol_valid ? spec_insn_rol_rs2_addr : + spec_insn_ror_valid ? spec_insn_ror_rs2_addr : + spec_insn_rori_valid ? spec_insn_rori_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs2_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_andn_valid ? spec_insn_andn_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_clz_valid ? spec_insn_clz_rd_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rd_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_max_valid ? spec_insn_max_rd_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rd_addr : + spec_insn_min_valid ? spec_insn_min_rd_addr : + spec_insn_minu_valid ? spec_insn_minu_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_orn_valid ? spec_insn_orn_rd_addr : + spec_insn_rol_valid ? spec_insn_rol_rd_addr : + spec_insn_ror_valid ? spec_insn_ror_rd_addr : + spec_insn_rori_valid ? spec_insn_rori_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_andn_valid ? spec_insn_andn_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_clz_valid ? spec_insn_clz_rd_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_rd_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_max_valid ? spec_insn_max_rd_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_rd_wdata : + spec_insn_min_valid ? spec_insn_min_rd_wdata : + spec_insn_minu_valid ? spec_insn_minu_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_orn_valid ? spec_insn_orn_rd_wdata : + spec_insn_rol_valid ? spec_insn_rol_rd_wdata : + spec_insn_ror_valid ? spec_insn_ror_rd_wdata : + spec_insn_rori_valid ? spec_insn_rori_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_andn_valid ? spec_insn_andn_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_clz_valid ? spec_insn_clz_pc_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_pc_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_max_valid ? spec_insn_max_pc_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_pc_wdata : + spec_insn_min_valid ? spec_insn_min_pc_wdata : + spec_insn_minu_valid ? spec_insn_minu_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_orn_valid ? spec_insn_orn_pc_wdata : + spec_insn_rol_valid ? spec_insn_rol_pc_wdata : + spec_insn_ror_valid ? spec_insn_ror_pc_wdata : + spec_insn_rori_valid ? spec_insn_rori_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_pc_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_andn_valid ? spec_insn_andn_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_clz_valid ? spec_insn_clz_mem_addr : + spec_insn_cpop_valid ? spec_insn_cpop_mem_addr : + spec_insn_ctz_valid ? spec_insn_ctz_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_max_valid ? spec_insn_max_mem_addr : + spec_insn_maxu_valid ? spec_insn_maxu_mem_addr : + spec_insn_min_valid ? spec_insn_min_mem_addr : + spec_insn_minu_valid ? spec_insn_minu_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_orn_valid ? spec_insn_orn_mem_addr : + spec_insn_rol_valid ? spec_insn_rol_mem_addr : + spec_insn_ror_valid ? spec_insn_ror_mem_addr : + spec_insn_rori_valid ? spec_insn_rori_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xnor_valid ? spec_insn_xnor_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_andn_valid ? spec_insn_andn_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_clz_valid ? spec_insn_clz_mem_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_max_valid ? spec_insn_max_mem_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_rmask : + spec_insn_min_valid ? spec_insn_min_mem_rmask : + spec_insn_minu_valid ? spec_insn_minu_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_orn_valid ? spec_insn_orn_mem_rmask : + spec_insn_rol_valid ? spec_insn_rol_mem_rmask : + spec_insn_ror_valid ? spec_insn_ror_mem_rmask : + spec_insn_rori_valid ? spec_insn_rori_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_andn_valid ? spec_insn_andn_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_clz_valid ? spec_insn_clz_mem_wmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_max_valid ? spec_insn_max_mem_wmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wmask : + spec_insn_min_valid ? spec_insn_min_mem_wmask : + spec_insn_minu_valid ? spec_insn_minu_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_orn_valid ? spec_insn_orn_mem_wmask : + spec_insn_rol_valid ? spec_insn_rol_mem_wmask : + spec_insn_ror_valid ? spec_insn_ror_mem_wmask : + spec_insn_rori_valid ? spec_insn_rori_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_andn_valid ? spec_insn_andn_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_clz_valid ? spec_insn_clz_mem_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_max_valid ? spec_insn_max_mem_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wdata : + spec_insn_min_valid ? spec_insn_min_mem_wdata : + spec_insn_minu_valid ? spec_insn_minu_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_orn_valid ? spec_insn_orn_mem_wdata : + spec_insn_rol_valid ? spec_insn_rol_mem_wdata : + spec_insn_ror_valid ? spec_insn_ror_mem_wdata : + spec_insn_rori_valid ? spec_insn_rori_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_andn_valid ? spec_insn_andn_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_clz_valid ? spec_insn_clz_csr_misa_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_csr_misa_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_max_valid ? spec_insn_max_csr_misa_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_csr_misa_rmask : + spec_insn_min_valid ? spec_insn_min_csr_misa_rmask : + spec_insn_minu_valid ? spec_insn_minu_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_orn_valid ? spec_insn_orn_csr_misa_rmask : + spec_insn_rol_valid ? spec_insn_rol_csr_misa_rmask : + spec_insn_ror_valid ? spec_insn_ror_csr_misa_rmask : + spec_insn_rori_valid ? spec_insn_rori_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_csr_misa_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_csr_misa_rmask : 0; +`endif +endmodule diff --git a/insns/isa_rv32ib.txt b/insns/isa_rv32ib.txt index dfc72770..b6b76eac 100644 --- a/insns/isa_rv32ib.txt +++ b/insns/isa_rv32ib.txt @@ -2,6 +2,7 @@ add addi and andi +andn auipc beq bge @@ -9,6 +10,9 @@ bgeu blt bltu bne +clz +cpop +ctz jal jalr lb @@ -17,9 +21,19 @@ lh lhu lui lw +max +maxu +min +minu or ori +orn +rol +ror +rori sb +sext_b +sext_h sh sh1add sh2add @@ -36,5 +50,7 @@ srl srli sub sw +xnor xor xori +zext_h diff --git a/insns/isa_rv32ib.v b/insns/isa_rv32ib.v index 6a595dcf..975f0e74 100644 --- a/insns/isa_rv32ib.v +++ b/insns/isa_rv32ib.v @@ -180,6 +180,45 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_andi_mem_wdata) ); + wire spec_insn_andn_valid; + wire spec_insn_andn_trap; + wire [ 4 : 0] spec_insn_andn_rs1_addr; + wire [ 4 : 0] spec_insn_andn_rs2_addr; + wire [ 4 : 0] spec_insn_andn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_csr_misa_rmask; +`endif + + rvfi_insn_andn insn_andn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andn_valid), + .spec_trap(spec_insn_andn_trap), + .spec_rs1_addr(spec_insn_andn_rs1_addr), + .spec_rs2_addr(spec_insn_andn_rs2_addr), + .spec_rd_addr(spec_insn_andn_rd_addr), + .spec_rd_wdata(spec_insn_andn_rd_wdata), + .spec_pc_wdata(spec_insn_andn_pc_wdata), + .spec_mem_addr(spec_insn_andn_mem_addr), + .spec_mem_rmask(spec_insn_andn_mem_rmask), + .spec_mem_wmask(spec_insn_andn_mem_wmask), + .spec_mem_wdata(spec_insn_andn_mem_wdata) + ); + wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; @@ -453,6 +492,123 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_bne_mem_wdata) ); + wire spec_insn_clz_valid; + wire spec_insn_clz_trap; + wire [ 4 : 0] spec_insn_clz_rs1_addr; + wire [ 4 : 0] spec_insn_clz_rs2_addr; + wire [ 4 : 0] spec_insn_clz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_csr_misa_rmask; +`endif + + rvfi_insn_clz insn_clz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_clz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_clz_valid), + .spec_trap(spec_insn_clz_trap), + .spec_rs1_addr(spec_insn_clz_rs1_addr), + .spec_rs2_addr(spec_insn_clz_rs2_addr), + .spec_rd_addr(spec_insn_clz_rd_addr), + .spec_rd_wdata(spec_insn_clz_rd_wdata), + .spec_pc_wdata(spec_insn_clz_pc_wdata), + .spec_mem_addr(spec_insn_clz_mem_addr), + .spec_mem_rmask(spec_insn_clz_mem_rmask), + .spec_mem_wmask(spec_insn_clz_mem_wmask), + .spec_mem_wdata(spec_insn_clz_mem_wdata) + ); + + wire spec_insn_cpop_valid; + wire spec_insn_cpop_trap; + wire [ 4 : 0] spec_insn_cpop_rs1_addr; + wire [ 4 : 0] spec_insn_cpop_rs2_addr; + wire [ 4 : 0] spec_insn_cpop_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_csr_misa_rmask; +`endif + + rvfi_insn_cpop insn_cpop ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_cpop_csr_misa_rmask), +`endif + .spec_valid(spec_insn_cpop_valid), + .spec_trap(spec_insn_cpop_trap), + .spec_rs1_addr(spec_insn_cpop_rs1_addr), + .spec_rs2_addr(spec_insn_cpop_rs2_addr), + .spec_rd_addr(spec_insn_cpop_rd_addr), + .spec_rd_wdata(spec_insn_cpop_rd_wdata), + .spec_pc_wdata(spec_insn_cpop_pc_wdata), + .spec_mem_addr(spec_insn_cpop_mem_addr), + .spec_mem_rmask(spec_insn_cpop_mem_rmask), + .spec_mem_wmask(spec_insn_cpop_mem_wmask), + .spec_mem_wdata(spec_insn_cpop_mem_wdata) + ); + + wire spec_insn_ctz_valid; + wire spec_insn_ctz_trap; + wire [ 4 : 0] spec_insn_ctz_rs1_addr; + wire [ 4 : 0] spec_insn_ctz_rs2_addr; + wire [ 4 : 0] spec_insn_ctz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_csr_misa_rmask; +`endif + + rvfi_insn_ctz insn_ctz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ctz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ctz_valid), + .spec_trap(spec_insn_ctz_trap), + .spec_rs1_addr(spec_insn_ctz_rs1_addr), + .spec_rs2_addr(spec_insn_ctz_rs2_addr), + .spec_rd_addr(spec_insn_ctz_rd_addr), + .spec_rd_wdata(spec_insn_ctz_rd_wdata), + .spec_pc_wdata(spec_insn_ctz_pc_wdata), + .spec_mem_addr(spec_insn_ctz_mem_addr), + .spec_mem_rmask(spec_insn_ctz_mem_rmask), + .spec_mem_wmask(spec_insn_ctz_mem_wmask), + .spec_mem_wdata(spec_insn_ctz_mem_wdata) + ); + wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; @@ -765,6 +921,162 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_lw_mem_wdata) ); + wire spec_insn_max_valid; + wire spec_insn_max_trap; + wire [ 4 : 0] spec_insn_max_rs1_addr; + wire [ 4 : 0] spec_insn_max_rs2_addr; + wire [ 4 : 0] spec_insn_max_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_csr_misa_rmask; +`endif + + rvfi_insn_max insn_max ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_max_csr_misa_rmask), +`endif + .spec_valid(spec_insn_max_valid), + .spec_trap(spec_insn_max_trap), + .spec_rs1_addr(spec_insn_max_rs1_addr), + .spec_rs2_addr(spec_insn_max_rs2_addr), + .spec_rd_addr(spec_insn_max_rd_addr), + .spec_rd_wdata(spec_insn_max_rd_wdata), + .spec_pc_wdata(spec_insn_max_pc_wdata), + .spec_mem_addr(spec_insn_max_mem_addr), + .spec_mem_rmask(spec_insn_max_mem_rmask), + .spec_mem_wmask(spec_insn_max_mem_wmask), + .spec_mem_wdata(spec_insn_max_mem_wdata) + ); + + wire spec_insn_maxu_valid; + wire spec_insn_maxu_trap; + wire [ 4 : 0] spec_insn_maxu_rs1_addr; + wire [ 4 : 0] spec_insn_maxu_rs2_addr; + wire [ 4 : 0] spec_insn_maxu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_csr_misa_rmask; +`endif + + rvfi_insn_maxu insn_maxu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_maxu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_maxu_valid), + .spec_trap(spec_insn_maxu_trap), + .spec_rs1_addr(spec_insn_maxu_rs1_addr), + .spec_rs2_addr(spec_insn_maxu_rs2_addr), + .spec_rd_addr(spec_insn_maxu_rd_addr), + .spec_rd_wdata(spec_insn_maxu_rd_wdata), + .spec_pc_wdata(spec_insn_maxu_pc_wdata), + .spec_mem_addr(spec_insn_maxu_mem_addr), + .spec_mem_rmask(spec_insn_maxu_mem_rmask), + .spec_mem_wmask(spec_insn_maxu_mem_wmask), + .spec_mem_wdata(spec_insn_maxu_mem_wdata) + ); + + wire spec_insn_min_valid; + wire spec_insn_min_trap; + wire [ 4 : 0] spec_insn_min_rs1_addr; + wire [ 4 : 0] spec_insn_min_rs2_addr; + wire [ 4 : 0] spec_insn_min_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_csr_misa_rmask; +`endif + + rvfi_insn_min insn_min ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_min_csr_misa_rmask), +`endif + .spec_valid(spec_insn_min_valid), + .spec_trap(spec_insn_min_trap), + .spec_rs1_addr(spec_insn_min_rs1_addr), + .spec_rs2_addr(spec_insn_min_rs2_addr), + .spec_rd_addr(spec_insn_min_rd_addr), + .spec_rd_wdata(spec_insn_min_rd_wdata), + .spec_pc_wdata(spec_insn_min_pc_wdata), + .spec_mem_addr(spec_insn_min_mem_addr), + .spec_mem_rmask(spec_insn_min_mem_rmask), + .spec_mem_wmask(spec_insn_min_mem_wmask), + .spec_mem_wdata(spec_insn_min_mem_wdata) + ); + + wire spec_insn_minu_valid; + wire spec_insn_minu_trap; + wire [ 4 : 0] spec_insn_minu_rs1_addr; + wire [ 4 : 0] spec_insn_minu_rs2_addr; + wire [ 4 : 0] spec_insn_minu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_csr_misa_rmask; +`endif + + rvfi_insn_minu insn_minu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_minu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_minu_valid), + .spec_trap(spec_insn_minu_trap), + .spec_rs1_addr(spec_insn_minu_rs1_addr), + .spec_rs2_addr(spec_insn_minu_rs2_addr), + .spec_rd_addr(spec_insn_minu_rd_addr), + .spec_rd_wdata(spec_insn_minu_rd_wdata), + .spec_pc_wdata(spec_insn_minu_pc_wdata), + .spec_mem_addr(spec_insn_minu_mem_addr), + .spec_mem_rmask(spec_insn_minu_mem_rmask), + .spec_mem_wmask(spec_insn_minu_mem_wmask), + .spec_mem_wdata(spec_insn_minu_mem_wdata) + ); + wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; @@ -843,6 +1155,162 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_ori_mem_wdata) ); + wire spec_insn_orn_valid; + wire spec_insn_orn_trap; + wire [ 4 : 0] spec_insn_orn_rs1_addr; + wire [ 4 : 0] spec_insn_orn_rs2_addr; + wire [ 4 : 0] spec_insn_orn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_csr_misa_rmask; +`endif + + rvfi_insn_orn insn_orn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_orn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_orn_valid), + .spec_trap(spec_insn_orn_trap), + .spec_rs1_addr(spec_insn_orn_rs1_addr), + .spec_rs2_addr(spec_insn_orn_rs2_addr), + .spec_rd_addr(spec_insn_orn_rd_addr), + .spec_rd_wdata(spec_insn_orn_rd_wdata), + .spec_pc_wdata(spec_insn_orn_pc_wdata), + .spec_mem_addr(spec_insn_orn_mem_addr), + .spec_mem_rmask(spec_insn_orn_mem_rmask), + .spec_mem_wmask(spec_insn_orn_mem_wmask), + .spec_mem_wdata(spec_insn_orn_mem_wdata) + ); + + wire spec_insn_rol_valid; + wire spec_insn_rol_trap; + wire [ 4 : 0] spec_insn_rol_rs1_addr; + wire [ 4 : 0] spec_insn_rol_rs2_addr; + wire [ 4 : 0] spec_insn_rol_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_csr_misa_rmask; +`endif + + rvfi_insn_rol insn_rol ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rol_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rol_valid), + .spec_trap(spec_insn_rol_trap), + .spec_rs1_addr(spec_insn_rol_rs1_addr), + .spec_rs2_addr(spec_insn_rol_rs2_addr), + .spec_rd_addr(spec_insn_rol_rd_addr), + .spec_rd_wdata(spec_insn_rol_rd_wdata), + .spec_pc_wdata(spec_insn_rol_pc_wdata), + .spec_mem_addr(spec_insn_rol_mem_addr), + .spec_mem_rmask(spec_insn_rol_mem_rmask), + .spec_mem_wmask(spec_insn_rol_mem_wmask), + .spec_mem_wdata(spec_insn_rol_mem_wdata) + ); + + wire spec_insn_ror_valid; + wire spec_insn_ror_trap; + wire [ 4 : 0] spec_insn_ror_rs1_addr; + wire [ 4 : 0] spec_insn_ror_rs2_addr; + wire [ 4 : 0] spec_insn_ror_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_csr_misa_rmask; +`endif + + rvfi_insn_ror insn_ror ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ror_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ror_valid), + .spec_trap(spec_insn_ror_trap), + .spec_rs1_addr(spec_insn_ror_rs1_addr), + .spec_rs2_addr(spec_insn_ror_rs2_addr), + .spec_rd_addr(spec_insn_ror_rd_addr), + .spec_rd_wdata(spec_insn_ror_rd_wdata), + .spec_pc_wdata(spec_insn_ror_pc_wdata), + .spec_mem_addr(spec_insn_ror_mem_addr), + .spec_mem_rmask(spec_insn_ror_mem_rmask), + .spec_mem_wmask(spec_insn_ror_mem_wmask), + .spec_mem_wdata(spec_insn_ror_mem_wdata) + ); + + wire spec_insn_rori_valid; + wire spec_insn_rori_trap; + wire [ 4 : 0] spec_insn_rori_rs1_addr; + wire [ 4 : 0] spec_insn_rori_rs2_addr; + wire [ 4 : 0] spec_insn_rori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_csr_misa_rmask; +`endif + + rvfi_insn_rori insn_rori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rori_valid), + .spec_trap(spec_insn_rori_trap), + .spec_rs1_addr(spec_insn_rori_rs1_addr), + .spec_rs2_addr(spec_insn_rori_rs2_addr), + .spec_rd_addr(spec_insn_rori_rd_addr), + .spec_rd_wdata(spec_insn_rori_rd_wdata), + .spec_pc_wdata(spec_insn_rori_pc_wdata), + .spec_mem_addr(spec_insn_rori_mem_addr), + .spec_mem_rmask(spec_insn_rori_mem_rmask), + .spec_mem_wmask(spec_insn_rori_mem_wmask), + .spec_mem_wdata(spec_insn_rori_mem_wdata) + ); + wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; @@ -882,6 +1350,84 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_sb_mem_wdata) ); + wire spec_insn_sext_b_valid; + wire spec_insn_sext_b_trap; + wire [ 4 : 0] spec_insn_sext_b_rs1_addr; + wire [ 4 : 0] spec_insn_sext_b_rs2_addr; + wire [ 4 : 0] spec_insn_sext_b_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_csr_misa_rmask; +`endif + + rvfi_insn_sext_b insn_sext_b ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_b_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_b_valid), + .spec_trap(spec_insn_sext_b_trap), + .spec_rs1_addr(spec_insn_sext_b_rs1_addr), + .spec_rs2_addr(spec_insn_sext_b_rs2_addr), + .spec_rd_addr(spec_insn_sext_b_rd_addr), + .spec_rd_wdata(spec_insn_sext_b_rd_wdata), + .spec_pc_wdata(spec_insn_sext_b_pc_wdata), + .spec_mem_addr(spec_insn_sext_b_mem_addr), + .spec_mem_rmask(spec_insn_sext_b_mem_rmask), + .spec_mem_wmask(spec_insn_sext_b_mem_wmask), + .spec_mem_wdata(spec_insn_sext_b_mem_wdata) + ); + + wire spec_insn_sext_h_valid; + wire spec_insn_sext_h_trap; + wire [ 4 : 0] spec_insn_sext_h_rs1_addr; + wire [ 4 : 0] spec_insn_sext_h_rs2_addr; + wire [ 4 : 0] spec_insn_sext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_csr_misa_rmask; +`endif + + rvfi_insn_sext_h insn_sext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_h_valid), + .spec_trap(spec_insn_sext_h_trap), + .spec_rs1_addr(spec_insn_sext_h_rs1_addr), + .spec_rs2_addr(spec_insn_sext_h_rs2_addr), + .spec_rd_addr(spec_insn_sext_h_rd_addr), + .spec_rd_wdata(spec_insn_sext_h_rd_wdata), + .spec_pc_wdata(spec_insn_sext_h_pc_wdata), + .spec_mem_addr(spec_insn_sext_h_mem_addr), + .spec_mem_rmask(spec_insn_sext_h_mem_rmask), + .spec_mem_wmask(spec_insn_sext_h_mem_wmask), + .spec_mem_wdata(spec_insn_sext_h_mem_wdata) + ); + wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; @@ -1506,6 +2052,45 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_sw_mem_wdata) ); + wire spec_insn_xnor_valid; + wire spec_insn_xnor_trap; + wire [ 4 : 0] spec_insn_xnor_rs1_addr; + wire [ 4 : 0] spec_insn_xnor_rs2_addr; + wire [ 4 : 0] spec_insn_xnor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_csr_misa_rmask; +`endif + + rvfi_insn_xnor insn_xnor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xnor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xnor_valid), + .spec_trap(spec_insn_xnor_trap), + .spec_rs1_addr(spec_insn_xnor_rs1_addr), + .spec_rs2_addr(spec_insn_xnor_rs2_addr), + .spec_rd_addr(spec_insn_xnor_rd_addr), + .spec_rd_wdata(spec_insn_xnor_rd_wdata), + .spec_pc_wdata(spec_insn_xnor_pc_wdata), + .spec_mem_addr(spec_insn_xnor_mem_addr), + .spec_mem_rmask(spec_insn_xnor_mem_rmask), + .spec_mem_wmask(spec_insn_xnor_mem_wmask), + .spec_mem_wdata(spec_insn_xnor_mem_wdata) + ); + wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; @@ -1584,11 +2169,51 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_xori_mem_wdata) ); + wire spec_insn_zext_h_valid; + wire spec_insn_zext_h_trap; + wire [ 4 : 0] spec_insn_zext_h_rs1_addr; + wire [ 4 : 0] spec_insn_zext_h_rs2_addr; + wire [ 4 : 0] spec_insn_zext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_csr_misa_rmask; +`endif + + rvfi_insn_zext_h insn_zext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_zext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_zext_h_valid), + .spec_trap(spec_insn_zext_h_trap), + .spec_rs1_addr(spec_insn_zext_h_rs1_addr), + .spec_rs2_addr(spec_insn_zext_h_rs2_addr), + .spec_rd_addr(spec_insn_zext_h_rd_addr), + .spec_rd_wdata(spec_insn_zext_h_rd_wdata), + .spec_pc_wdata(spec_insn_zext_h_pc_wdata), + .spec_mem_addr(spec_insn_zext_h_mem_addr), + .spec_mem_rmask(spec_insn_zext_h_mem_rmask), + .spec_mem_wmask(spec_insn_zext_h_mem_wmask), + .spec_mem_wdata(spec_insn_zext_h_mem_wdata) + ); + assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_andn_valid ? spec_insn_andn_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : @@ -1596,6 +2221,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_clz_valid ? spec_insn_clz_valid : + spec_insn_cpop_valid ? spec_insn_cpop_valid : + spec_insn_ctz_valid ? spec_insn_ctz_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : @@ -1604,9 +2232,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_max_valid ? spec_insn_max_valid : + spec_insn_maxu_valid ? spec_insn_maxu_valid : + spec_insn_min_valid ? spec_insn_min_valid : + spec_insn_minu_valid ? spec_insn_minu_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_orn_valid ? spec_insn_orn_valid : + spec_insn_rol_valid ? spec_insn_rol_valid : + spec_insn_ror_valid ? spec_insn_ror_valid : + spec_insn_rori_valid ? spec_insn_rori_valid : spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sext_b_valid ? spec_insn_sext_b_valid : + spec_insn_sext_h_valid ? spec_insn_sext_h_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sh1add_valid ? spec_insn_sh1add_valid : spec_insn_sh2add_valid ? spec_insn_sh2add_valid : @@ -1623,13 +2261,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xnor_valid ? spec_insn_xnor_valid : spec_insn_xor_valid ? spec_insn_xor_valid : - spec_insn_xori_valid ? spec_insn_xori_valid : 0; + spec_insn_xori_valid ? spec_insn_xori_valid : + spec_insn_zext_h_valid ? spec_insn_zext_h_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_andn_valid ? spec_insn_andn_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : @@ -1637,6 +2278,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_clz_valid ? spec_insn_clz_trap : + spec_insn_cpop_valid ? spec_insn_cpop_trap : + spec_insn_ctz_valid ? spec_insn_ctz_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : @@ -1645,9 +2289,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_max_valid ? spec_insn_max_trap : + spec_insn_maxu_valid ? spec_insn_maxu_trap : + spec_insn_min_valid ? spec_insn_min_trap : + spec_insn_minu_valid ? spec_insn_minu_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_orn_valid ? spec_insn_orn_trap : + spec_insn_rol_valid ? spec_insn_rol_trap : + spec_insn_ror_valid ? spec_insn_ror_trap : + spec_insn_rori_valid ? spec_insn_rori_trap : spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sext_b_valid ? spec_insn_sext_b_trap : + spec_insn_sext_h_valid ? spec_insn_sext_h_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sh1add_valid ? spec_insn_sh1add_trap : spec_insn_sh2add_valid ? spec_insn_sh2add_trap : @@ -1664,13 +2318,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xnor_valid ? spec_insn_xnor_trap : spec_insn_xor_valid ? spec_insn_xor_trap : - spec_insn_xori_valid ? spec_insn_xori_trap : 0; + spec_insn_xori_valid ? spec_insn_xori_trap : + spec_insn_zext_h_valid ? spec_insn_zext_h_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_andn_valid ? spec_insn_andn_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : @@ -1678,6 +2335,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_clz_valid ? spec_insn_clz_rs1_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs1_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : @@ -1686,9 +2346,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_max_valid ? spec_insn_max_rs1_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs1_addr : + spec_insn_min_valid ? spec_insn_min_rs1_addr : + spec_insn_minu_valid ? spec_insn_minu_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_orn_valid ? spec_insn_orn_rs1_addr : + spec_insn_rol_valid ? spec_insn_rol_rs1_addr : + spec_insn_ror_valid ? spec_insn_ror_rs1_addr : + spec_insn_rori_valid ? spec_insn_rori_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs1_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_rs1_addr : spec_insn_sh2add_valid ? spec_insn_sh2add_rs1_addr : @@ -1705,13 +2375,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : - spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_andn_valid ? spec_insn_andn_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : @@ -1719,6 +2392,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_clz_valid ? spec_insn_clz_rs2_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs2_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : @@ -1727,9 +2403,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_max_valid ? spec_insn_max_rs2_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs2_addr : + spec_insn_min_valid ? spec_insn_min_rs2_addr : + spec_insn_minu_valid ? spec_insn_minu_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_orn_valid ? spec_insn_orn_rs2_addr : + spec_insn_rol_valid ? spec_insn_rol_rs2_addr : + spec_insn_ror_valid ? spec_insn_ror_rs2_addr : + spec_insn_rori_valid ? spec_insn_rori_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs2_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_rs2_addr : spec_insn_sh2add_valid ? spec_insn_sh2add_rs2_addr : @@ -1746,13 +2432,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : - spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_andn_valid ? spec_insn_andn_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : @@ -1760,6 +2449,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_clz_valid ? spec_insn_clz_rd_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rd_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : @@ -1768,9 +2460,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_max_valid ? spec_insn_max_rd_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rd_addr : + spec_insn_min_valid ? spec_insn_min_rd_addr : + spec_insn_minu_valid ? spec_insn_minu_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_orn_valid ? spec_insn_orn_rd_addr : + spec_insn_rol_valid ? spec_insn_rol_rd_addr : + spec_insn_ror_valid ? spec_insn_ror_rd_addr : + spec_insn_rori_valid ? spec_insn_rori_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_rd_addr : spec_insn_sh2add_valid ? spec_insn_sh2add_rd_addr : @@ -1787,13 +2489,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : - spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_rd_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_andn_valid ? spec_insn_andn_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : @@ -1801,6 +2506,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_clz_valid ? spec_insn_clz_rd_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_rd_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : @@ -1809,9 +2517,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_max_valid ? spec_insn_max_rd_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_rd_wdata : + spec_insn_min_valid ? spec_insn_min_rd_wdata : + spec_insn_minu_valid ? spec_insn_minu_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_orn_valid ? spec_insn_orn_rd_wdata : + spec_insn_rol_valid ? spec_insn_rol_rd_wdata : + spec_insn_ror_valid ? spec_insn_ror_rd_wdata : + spec_insn_rori_valid ? spec_insn_rori_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sh1add_valid ? spec_insn_sh1add_rd_wdata : spec_insn_sh2add_valid ? spec_insn_sh2add_rd_wdata : @@ -1828,13 +2546,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : - spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_andn_valid ? spec_insn_andn_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : @@ -1842,6 +2563,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_clz_valid ? spec_insn_clz_pc_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_pc_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : @@ -1850,9 +2574,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_max_valid ? spec_insn_max_pc_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_pc_wdata : + spec_insn_min_valid ? spec_insn_min_pc_wdata : + spec_insn_minu_valid ? spec_insn_minu_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_orn_valid ? spec_insn_orn_pc_wdata : + spec_insn_rol_valid ? spec_insn_rol_pc_wdata : + spec_insn_ror_valid ? spec_insn_ror_pc_wdata : + spec_insn_rori_valid ? spec_insn_rori_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_pc_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sh1add_valid ? spec_insn_sh1add_pc_wdata : spec_insn_sh2add_valid ? spec_insn_sh2add_pc_wdata : @@ -1869,13 +2603,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : - spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_andn_valid ? spec_insn_andn_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : @@ -1883,6 +2620,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_clz_valid ? spec_insn_clz_mem_addr : + spec_insn_cpop_valid ? spec_insn_cpop_mem_addr : + spec_insn_ctz_valid ? spec_insn_ctz_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : @@ -1891,9 +2631,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_max_valid ? spec_insn_max_mem_addr : + spec_insn_maxu_valid ? spec_insn_maxu_mem_addr : + spec_insn_min_valid ? spec_insn_min_mem_addr : + spec_insn_minu_valid ? spec_insn_minu_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_orn_valid ? spec_insn_orn_mem_addr : + spec_insn_rol_valid ? spec_insn_rol_mem_addr : + spec_insn_ror_valid ? spec_insn_ror_mem_addr : + spec_insn_rori_valid ? spec_insn_rori_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_addr : spec_insn_sh2add_valid ? spec_insn_sh2add_mem_addr : @@ -1910,13 +2660,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xnor_valid ? spec_insn_xnor_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : - spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_andn_valid ? spec_insn_andn_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : @@ -1924,6 +2677,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_clz_valid ? spec_insn_clz_mem_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : @@ -1932,9 +2688,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_max_valid ? spec_insn_max_mem_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_rmask : + spec_insn_min_valid ? spec_insn_min_mem_rmask : + spec_insn_minu_valid ? spec_insn_minu_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_orn_valid ? spec_insn_orn_mem_rmask : + spec_insn_rol_valid ? spec_insn_rol_mem_rmask : + spec_insn_ror_valid ? spec_insn_ror_mem_rmask : + spec_insn_rori_valid ? spec_insn_rori_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_rmask : spec_insn_sh2add_valid ? spec_insn_sh2add_mem_rmask : @@ -1951,13 +2717,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : - spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_andn_valid ? spec_insn_andn_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : @@ -1965,6 +2734,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_clz_valid ? spec_insn_clz_mem_wmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : @@ -1973,9 +2745,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_max_valid ? spec_insn_max_mem_wmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wmask : + spec_insn_min_valid ? spec_insn_min_mem_wmask : + spec_insn_minu_valid ? spec_insn_minu_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_orn_valid ? spec_insn_orn_mem_wmask : + spec_insn_rol_valid ? spec_insn_rol_mem_wmask : + spec_insn_ror_valid ? spec_insn_ror_mem_wmask : + spec_insn_rori_valid ? spec_insn_rori_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wmask : spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wmask : @@ -1992,13 +2774,16 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : - spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_andn_valid ? spec_insn_andn_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : @@ -2006,6 +2791,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_clz_valid ? spec_insn_clz_mem_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : @@ -2014,9 +2802,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_max_valid ? spec_insn_max_mem_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wdata : + spec_insn_min_valid ? spec_insn_min_mem_wdata : + spec_insn_minu_valid ? spec_insn_minu_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_orn_valid ? spec_insn_orn_mem_wdata : + spec_insn_rol_valid ? spec_insn_rol_mem_wdata : + spec_insn_ror_valid ? spec_insn_ror_mem_wdata : + spec_insn_rori_valid ? spec_insn_rori_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wdata : spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wdata : @@ -2033,14 +2831,17 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : - spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_andn_valid ? spec_insn_andn_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : @@ -2048,6 +2849,9 @@ module rvfi_isa_rv32ib ( spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_clz_valid ? spec_insn_clz_csr_misa_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_csr_misa_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : @@ -2056,9 +2860,19 @@ module rvfi_isa_rv32ib ( spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_max_valid ? spec_insn_max_csr_misa_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_csr_misa_rmask : + spec_insn_min_valid ? spec_insn_min_csr_misa_rmask : + spec_insn_minu_valid ? spec_insn_minu_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_orn_valid ? spec_insn_orn_csr_misa_rmask : + spec_insn_rol_valid ? spec_insn_rol_csr_misa_rmask : + spec_insn_ror_valid ? spec_insn_ror_csr_misa_rmask : + spec_insn_rori_valid ? spec_insn_rori_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_csr_misa_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sh1add_valid ? spec_insn_sh1add_csr_misa_rmask : spec_insn_sh2add_valid ? spec_insn_sh2add_csr_misa_rmask : @@ -2075,7 +2889,9 @@ module rvfi_isa_rv32ib ( spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : - spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_csr_misa_rmask : 0; `endif endmodule diff --git a/insns/isa_rv64iZbb.txt b/insns/isa_rv64iZbb.txt new file mode 100644 index 00000000..f8c45060 --- /dev/null +++ b/insns/isa_rv64iZbb.txt @@ -0,0 +1,71 @@ +add +addi +addiw +addw +and +andi +andn +auipc +beq +bge +bgeu +blt +bltu +bne +clz +clzw +cpop +cpopw +ctz +ctzw +jal +jalr +lb +lbu +ld +lh +lhu +lui +lw +lwu +max +maxu +min +minu +or +ori +orn +rol +rolw +ror +rori +roriw +rorw +sb +sd +sext_b +sext_h +sh +sll +slli +slliw +sllw +slt +slti +sltiu +sltu +sra +srai +sraiw +sraw +srl +srli +srliw +srlw +sub +subw +sw +xnor +xor +xori +zext_h diff --git a/insns/isa_rv64iZbb.v b/insns/isa_rv64iZbb.v new file mode 100644 index 00000000..c06801c8 --- /dev/null +++ b/insns/isa_rv64iZbb.v @@ -0,0 +1,3662 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv64iZbb ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_addiw_valid; + wire spec_insn_addiw_trap; + wire [ 4 : 0] spec_insn_addiw_rs1_addr; + wire [ 4 : 0] spec_insn_addiw_rs2_addr; + wire [ 4 : 0] spec_insn_addiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; +`endif + + rvfi_insn_addiw insn_addiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addiw_valid), + .spec_trap(spec_insn_addiw_trap), + .spec_rs1_addr(spec_insn_addiw_rs1_addr), + .spec_rs2_addr(spec_insn_addiw_rs2_addr), + .spec_rd_addr(spec_insn_addiw_rd_addr), + .spec_rd_wdata(spec_insn_addiw_rd_wdata), + .spec_pc_wdata(spec_insn_addiw_pc_wdata), + .spec_mem_addr(spec_insn_addiw_mem_addr), + .spec_mem_rmask(spec_insn_addiw_mem_rmask), + .spec_mem_wmask(spec_insn_addiw_mem_wmask), + .spec_mem_wdata(spec_insn_addiw_mem_wdata) + ); + + wire spec_insn_addw_valid; + wire spec_insn_addw_trap; + wire [ 4 : 0] spec_insn_addw_rs1_addr; + wire [ 4 : 0] spec_insn_addw_rs2_addr; + wire [ 4 : 0] spec_insn_addw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; +`endif + + rvfi_insn_addw insn_addw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addw_valid), + .spec_trap(spec_insn_addw_trap), + .spec_rs1_addr(spec_insn_addw_rs1_addr), + .spec_rs2_addr(spec_insn_addw_rs2_addr), + .spec_rd_addr(spec_insn_addw_rd_addr), + .spec_rd_wdata(spec_insn_addw_rd_wdata), + .spec_pc_wdata(spec_insn_addw_pc_wdata), + .spec_mem_addr(spec_insn_addw_mem_addr), + .spec_mem_rmask(spec_insn_addw_mem_rmask), + .spec_mem_wmask(spec_insn_addw_mem_wmask), + .spec_mem_wdata(spec_insn_addw_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_andn_valid; + wire spec_insn_andn_trap; + wire [ 4 : 0] spec_insn_andn_rs1_addr; + wire [ 4 : 0] spec_insn_andn_rs2_addr; + wire [ 4 : 0] spec_insn_andn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_csr_misa_rmask; +`endif + + rvfi_insn_andn insn_andn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andn_valid), + .spec_trap(spec_insn_andn_trap), + .spec_rs1_addr(spec_insn_andn_rs1_addr), + .spec_rs2_addr(spec_insn_andn_rs2_addr), + .spec_rd_addr(spec_insn_andn_rd_addr), + .spec_rd_wdata(spec_insn_andn_rd_wdata), + .spec_pc_wdata(spec_insn_andn_pc_wdata), + .spec_mem_addr(spec_insn_andn_mem_addr), + .spec_mem_rmask(spec_insn_andn_mem_rmask), + .spec_mem_wmask(spec_insn_andn_mem_wmask), + .spec_mem_wdata(spec_insn_andn_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_clz_valid; + wire spec_insn_clz_trap; + wire [ 4 : 0] spec_insn_clz_rs1_addr; + wire [ 4 : 0] spec_insn_clz_rs2_addr; + wire [ 4 : 0] spec_insn_clz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_csr_misa_rmask; +`endif + + rvfi_insn_clz insn_clz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_clz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_clz_valid), + .spec_trap(spec_insn_clz_trap), + .spec_rs1_addr(spec_insn_clz_rs1_addr), + .spec_rs2_addr(spec_insn_clz_rs2_addr), + .spec_rd_addr(spec_insn_clz_rd_addr), + .spec_rd_wdata(spec_insn_clz_rd_wdata), + .spec_pc_wdata(spec_insn_clz_pc_wdata), + .spec_mem_addr(spec_insn_clz_mem_addr), + .spec_mem_rmask(spec_insn_clz_mem_rmask), + .spec_mem_wmask(spec_insn_clz_mem_wmask), + .spec_mem_wdata(spec_insn_clz_mem_wdata) + ); + + wire spec_insn_clzw_valid; + wire spec_insn_clzw_trap; + wire [ 4 : 0] spec_insn_clzw_rs1_addr; + wire [ 4 : 0] spec_insn_clzw_rs2_addr; + wire [ 4 : 0] spec_insn_clzw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clzw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clzw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_csr_misa_rmask; +`endif + + rvfi_insn_clzw insn_clzw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_clzw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_clzw_valid), + .spec_trap(spec_insn_clzw_trap), + .spec_rs1_addr(spec_insn_clzw_rs1_addr), + .spec_rs2_addr(spec_insn_clzw_rs2_addr), + .spec_rd_addr(spec_insn_clzw_rd_addr), + .spec_rd_wdata(spec_insn_clzw_rd_wdata), + .spec_pc_wdata(spec_insn_clzw_pc_wdata), + .spec_mem_addr(spec_insn_clzw_mem_addr), + .spec_mem_rmask(spec_insn_clzw_mem_rmask), + .spec_mem_wmask(spec_insn_clzw_mem_wmask), + .spec_mem_wdata(spec_insn_clzw_mem_wdata) + ); + + wire spec_insn_cpop_valid; + wire spec_insn_cpop_trap; + wire [ 4 : 0] spec_insn_cpop_rs1_addr; + wire [ 4 : 0] spec_insn_cpop_rs2_addr; + wire [ 4 : 0] spec_insn_cpop_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_csr_misa_rmask; +`endif + + rvfi_insn_cpop insn_cpop ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_cpop_csr_misa_rmask), +`endif + .spec_valid(spec_insn_cpop_valid), + .spec_trap(spec_insn_cpop_trap), + .spec_rs1_addr(spec_insn_cpop_rs1_addr), + .spec_rs2_addr(spec_insn_cpop_rs2_addr), + .spec_rd_addr(spec_insn_cpop_rd_addr), + .spec_rd_wdata(spec_insn_cpop_rd_wdata), + .spec_pc_wdata(spec_insn_cpop_pc_wdata), + .spec_mem_addr(spec_insn_cpop_mem_addr), + .spec_mem_rmask(spec_insn_cpop_mem_rmask), + .spec_mem_wmask(spec_insn_cpop_mem_wmask), + .spec_mem_wdata(spec_insn_cpop_mem_wdata) + ); + + wire spec_insn_cpopw_valid; + wire spec_insn_cpopw_trap; + wire [ 4 : 0] spec_insn_cpopw_rs1_addr; + wire [ 4 : 0] spec_insn_cpopw_rs2_addr; + wire [ 4 : 0] spec_insn_cpopw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpopw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpopw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_csr_misa_rmask; +`endif + + rvfi_insn_cpopw insn_cpopw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_cpopw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_cpopw_valid), + .spec_trap(spec_insn_cpopw_trap), + .spec_rs1_addr(spec_insn_cpopw_rs1_addr), + .spec_rs2_addr(spec_insn_cpopw_rs2_addr), + .spec_rd_addr(spec_insn_cpopw_rd_addr), + .spec_rd_wdata(spec_insn_cpopw_rd_wdata), + .spec_pc_wdata(spec_insn_cpopw_pc_wdata), + .spec_mem_addr(spec_insn_cpopw_mem_addr), + .spec_mem_rmask(spec_insn_cpopw_mem_rmask), + .spec_mem_wmask(spec_insn_cpopw_mem_wmask), + .spec_mem_wdata(spec_insn_cpopw_mem_wdata) + ); + + wire spec_insn_ctz_valid; + wire spec_insn_ctz_trap; + wire [ 4 : 0] spec_insn_ctz_rs1_addr; + wire [ 4 : 0] spec_insn_ctz_rs2_addr; + wire [ 4 : 0] spec_insn_ctz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_csr_misa_rmask; +`endif + + rvfi_insn_ctz insn_ctz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ctz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ctz_valid), + .spec_trap(spec_insn_ctz_trap), + .spec_rs1_addr(spec_insn_ctz_rs1_addr), + .spec_rs2_addr(spec_insn_ctz_rs2_addr), + .spec_rd_addr(spec_insn_ctz_rd_addr), + .spec_rd_wdata(spec_insn_ctz_rd_wdata), + .spec_pc_wdata(spec_insn_ctz_pc_wdata), + .spec_mem_addr(spec_insn_ctz_mem_addr), + .spec_mem_rmask(spec_insn_ctz_mem_rmask), + .spec_mem_wmask(spec_insn_ctz_mem_wmask), + .spec_mem_wdata(spec_insn_ctz_mem_wdata) + ); + + wire spec_insn_ctzw_valid; + wire spec_insn_ctzw_trap; + wire [ 4 : 0] spec_insn_ctzw_rs1_addr; + wire [ 4 : 0] spec_insn_ctzw_rs2_addr; + wire [ 4 : 0] spec_insn_ctzw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctzw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctzw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_csr_misa_rmask; +`endif + + rvfi_insn_ctzw insn_ctzw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ctzw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ctzw_valid), + .spec_trap(spec_insn_ctzw_trap), + .spec_rs1_addr(spec_insn_ctzw_rs1_addr), + .spec_rs2_addr(spec_insn_ctzw_rs2_addr), + .spec_rd_addr(spec_insn_ctzw_rd_addr), + .spec_rd_wdata(spec_insn_ctzw_rd_wdata), + .spec_pc_wdata(spec_insn_ctzw_pc_wdata), + .spec_mem_addr(spec_insn_ctzw_mem_addr), + .spec_mem_rmask(spec_insn_ctzw_mem_rmask), + .spec_mem_wmask(spec_insn_ctzw_mem_wmask), + .spec_mem_wdata(spec_insn_ctzw_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_ld_valid; + wire spec_insn_ld_trap; + wire [ 4 : 0] spec_insn_ld_rs1_addr; + wire [ 4 : 0] spec_insn_ld_rs2_addr; + wire [ 4 : 0] spec_insn_ld_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; +`endif + + rvfi_insn_ld insn_ld ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ld_valid), + .spec_trap(spec_insn_ld_trap), + .spec_rs1_addr(spec_insn_ld_rs1_addr), + .spec_rs2_addr(spec_insn_ld_rs2_addr), + .spec_rd_addr(spec_insn_ld_rd_addr), + .spec_rd_wdata(spec_insn_ld_rd_wdata), + .spec_pc_wdata(spec_insn_ld_pc_wdata), + .spec_mem_addr(spec_insn_ld_mem_addr), + .spec_mem_rmask(spec_insn_ld_mem_rmask), + .spec_mem_wmask(spec_insn_ld_mem_wmask), + .spec_mem_wdata(spec_insn_ld_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_lwu_valid; + wire spec_insn_lwu_trap; + wire [ 4 : 0] spec_insn_lwu_rs1_addr; + wire [ 4 : 0] spec_insn_lwu_rs2_addr; + wire [ 4 : 0] spec_insn_lwu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; +`endif + + rvfi_insn_lwu insn_lwu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lwu_valid), + .spec_trap(spec_insn_lwu_trap), + .spec_rs1_addr(spec_insn_lwu_rs1_addr), + .spec_rs2_addr(spec_insn_lwu_rs2_addr), + .spec_rd_addr(spec_insn_lwu_rd_addr), + .spec_rd_wdata(spec_insn_lwu_rd_wdata), + .spec_pc_wdata(spec_insn_lwu_pc_wdata), + .spec_mem_addr(spec_insn_lwu_mem_addr), + .spec_mem_rmask(spec_insn_lwu_mem_rmask), + .spec_mem_wmask(spec_insn_lwu_mem_wmask), + .spec_mem_wdata(spec_insn_lwu_mem_wdata) + ); + + wire spec_insn_max_valid; + wire spec_insn_max_trap; + wire [ 4 : 0] spec_insn_max_rs1_addr; + wire [ 4 : 0] spec_insn_max_rs2_addr; + wire [ 4 : 0] spec_insn_max_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_csr_misa_rmask; +`endif + + rvfi_insn_max insn_max ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_max_csr_misa_rmask), +`endif + .spec_valid(spec_insn_max_valid), + .spec_trap(spec_insn_max_trap), + .spec_rs1_addr(spec_insn_max_rs1_addr), + .spec_rs2_addr(spec_insn_max_rs2_addr), + .spec_rd_addr(spec_insn_max_rd_addr), + .spec_rd_wdata(spec_insn_max_rd_wdata), + .spec_pc_wdata(spec_insn_max_pc_wdata), + .spec_mem_addr(spec_insn_max_mem_addr), + .spec_mem_rmask(spec_insn_max_mem_rmask), + .spec_mem_wmask(spec_insn_max_mem_wmask), + .spec_mem_wdata(spec_insn_max_mem_wdata) + ); + + wire spec_insn_maxu_valid; + wire spec_insn_maxu_trap; + wire [ 4 : 0] spec_insn_maxu_rs1_addr; + wire [ 4 : 0] spec_insn_maxu_rs2_addr; + wire [ 4 : 0] spec_insn_maxu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_csr_misa_rmask; +`endif + + rvfi_insn_maxu insn_maxu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_maxu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_maxu_valid), + .spec_trap(spec_insn_maxu_trap), + .spec_rs1_addr(spec_insn_maxu_rs1_addr), + .spec_rs2_addr(spec_insn_maxu_rs2_addr), + .spec_rd_addr(spec_insn_maxu_rd_addr), + .spec_rd_wdata(spec_insn_maxu_rd_wdata), + .spec_pc_wdata(spec_insn_maxu_pc_wdata), + .spec_mem_addr(spec_insn_maxu_mem_addr), + .spec_mem_rmask(spec_insn_maxu_mem_rmask), + .spec_mem_wmask(spec_insn_maxu_mem_wmask), + .spec_mem_wdata(spec_insn_maxu_mem_wdata) + ); + + wire spec_insn_min_valid; + wire spec_insn_min_trap; + wire [ 4 : 0] spec_insn_min_rs1_addr; + wire [ 4 : 0] spec_insn_min_rs2_addr; + wire [ 4 : 0] spec_insn_min_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_csr_misa_rmask; +`endif + + rvfi_insn_min insn_min ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_min_csr_misa_rmask), +`endif + .spec_valid(spec_insn_min_valid), + .spec_trap(spec_insn_min_trap), + .spec_rs1_addr(spec_insn_min_rs1_addr), + .spec_rs2_addr(spec_insn_min_rs2_addr), + .spec_rd_addr(spec_insn_min_rd_addr), + .spec_rd_wdata(spec_insn_min_rd_wdata), + .spec_pc_wdata(spec_insn_min_pc_wdata), + .spec_mem_addr(spec_insn_min_mem_addr), + .spec_mem_rmask(spec_insn_min_mem_rmask), + .spec_mem_wmask(spec_insn_min_mem_wmask), + .spec_mem_wdata(spec_insn_min_mem_wdata) + ); + + wire spec_insn_minu_valid; + wire spec_insn_minu_trap; + wire [ 4 : 0] spec_insn_minu_rs1_addr; + wire [ 4 : 0] spec_insn_minu_rs2_addr; + wire [ 4 : 0] spec_insn_minu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_csr_misa_rmask; +`endif + + rvfi_insn_minu insn_minu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_minu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_minu_valid), + .spec_trap(spec_insn_minu_trap), + .spec_rs1_addr(spec_insn_minu_rs1_addr), + .spec_rs2_addr(spec_insn_minu_rs2_addr), + .spec_rd_addr(spec_insn_minu_rd_addr), + .spec_rd_wdata(spec_insn_minu_rd_wdata), + .spec_pc_wdata(spec_insn_minu_pc_wdata), + .spec_mem_addr(spec_insn_minu_mem_addr), + .spec_mem_rmask(spec_insn_minu_mem_rmask), + .spec_mem_wmask(spec_insn_minu_mem_wmask), + .spec_mem_wdata(spec_insn_minu_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_orn_valid; + wire spec_insn_orn_trap; + wire [ 4 : 0] spec_insn_orn_rs1_addr; + wire [ 4 : 0] spec_insn_orn_rs2_addr; + wire [ 4 : 0] spec_insn_orn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_csr_misa_rmask; +`endif + + rvfi_insn_orn insn_orn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_orn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_orn_valid), + .spec_trap(spec_insn_orn_trap), + .spec_rs1_addr(spec_insn_orn_rs1_addr), + .spec_rs2_addr(spec_insn_orn_rs2_addr), + .spec_rd_addr(spec_insn_orn_rd_addr), + .spec_rd_wdata(spec_insn_orn_rd_wdata), + .spec_pc_wdata(spec_insn_orn_pc_wdata), + .spec_mem_addr(spec_insn_orn_mem_addr), + .spec_mem_rmask(spec_insn_orn_mem_rmask), + .spec_mem_wmask(spec_insn_orn_mem_wmask), + .spec_mem_wdata(spec_insn_orn_mem_wdata) + ); + + wire spec_insn_rol_valid; + wire spec_insn_rol_trap; + wire [ 4 : 0] spec_insn_rol_rs1_addr; + wire [ 4 : 0] spec_insn_rol_rs2_addr; + wire [ 4 : 0] spec_insn_rol_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_csr_misa_rmask; +`endif + + rvfi_insn_rol insn_rol ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rol_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rol_valid), + .spec_trap(spec_insn_rol_trap), + .spec_rs1_addr(spec_insn_rol_rs1_addr), + .spec_rs2_addr(spec_insn_rol_rs2_addr), + .spec_rd_addr(spec_insn_rol_rd_addr), + .spec_rd_wdata(spec_insn_rol_rd_wdata), + .spec_pc_wdata(spec_insn_rol_pc_wdata), + .spec_mem_addr(spec_insn_rol_mem_addr), + .spec_mem_rmask(spec_insn_rol_mem_rmask), + .spec_mem_wmask(spec_insn_rol_mem_wmask), + .spec_mem_wdata(spec_insn_rol_mem_wdata) + ); + + wire spec_insn_rolw_valid; + wire spec_insn_rolw_trap; + wire [ 4 : 0] spec_insn_rolw_rs1_addr; + wire [ 4 : 0] spec_insn_rolw_rs2_addr; + wire [ 4 : 0] spec_insn_rolw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rolw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rolw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_csr_misa_rmask; +`endif + + rvfi_insn_rolw insn_rolw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rolw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rolw_valid), + .spec_trap(spec_insn_rolw_trap), + .spec_rs1_addr(spec_insn_rolw_rs1_addr), + .spec_rs2_addr(spec_insn_rolw_rs2_addr), + .spec_rd_addr(spec_insn_rolw_rd_addr), + .spec_rd_wdata(spec_insn_rolw_rd_wdata), + .spec_pc_wdata(spec_insn_rolw_pc_wdata), + .spec_mem_addr(spec_insn_rolw_mem_addr), + .spec_mem_rmask(spec_insn_rolw_mem_rmask), + .spec_mem_wmask(spec_insn_rolw_mem_wmask), + .spec_mem_wdata(spec_insn_rolw_mem_wdata) + ); + + wire spec_insn_ror_valid; + wire spec_insn_ror_trap; + wire [ 4 : 0] spec_insn_ror_rs1_addr; + wire [ 4 : 0] spec_insn_ror_rs2_addr; + wire [ 4 : 0] spec_insn_ror_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_csr_misa_rmask; +`endif + + rvfi_insn_ror insn_ror ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ror_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ror_valid), + .spec_trap(spec_insn_ror_trap), + .spec_rs1_addr(spec_insn_ror_rs1_addr), + .spec_rs2_addr(spec_insn_ror_rs2_addr), + .spec_rd_addr(spec_insn_ror_rd_addr), + .spec_rd_wdata(spec_insn_ror_rd_wdata), + .spec_pc_wdata(spec_insn_ror_pc_wdata), + .spec_mem_addr(spec_insn_ror_mem_addr), + .spec_mem_rmask(spec_insn_ror_mem_rmask), + .spec_mem_wmask(spec_insn_ror_mem_wmask), + .spec_mem_wdata(spec_insn_ror_mem_wdata) + ); + + wire spec_insn_rori_valid; + wire spec_insn_rori_trap; + wire [ 4 : 0] spec_insn_rori_rs1_addr; + wire [ 4 : 0] spec_insn_rori_rs2_addr; + wire [ 4 : 0] spec_insn_rori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_csr_misa_rmask; +`endif + + rvfi_insn_rori insn_rori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rori_valid), + .spec_trap(spec_insn_rori_trap), + .spec_rs1_addr(spec_insn_rori_rs1_addr), + .spec_rs2_addr(spec_insn_rori_rs2_addr), + .spec_rd_addr(spec_insn_rori_rd_addr), + .spec_rd_wdata(spec_insn_rori_rd_wdata), + .spec_pc_wdata(spec_insn_rori_pc_wdata), + .spec_mem_addr(spec_insn_rori_mem_addr), + .spec_mem_rmask(spec_insn_rori_mem_rmask), + .spec_mem_wmask(spec_insn_rori_mem_wmask), + .spec_mem_wdata(spec_insn_rori_mem_wdata) + ); + + wire spec_insn_roriw_valid; + wire spec_insn_roriw_trap; + wire [ 4 : 0] spec_insn_roriw_rs1_addr; + wire [ 4 : 0] spec_insn_roriw_rs2_addr; + wire [ 4 : 0] spec_insn_roriw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_roriw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_roriw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_csr_misa_rmask; +`endif + + rvfi_insn_roriw insn_roriw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_roriw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_roriw_valid), + .spec_trap(spec_insn_roriw_trap), + .spec_rs1_addr(spec_insn_roriw_rs1_addr), + .spec_rs2_addr(spec_insn_roriw_rs2_addr), + .spec_rd_addr(spec_insn_roriw_rd_addr), + .spec_rd_wdata(spec_insn_roriw_rd_wdata), + .spec_pc_wdata(spec_insn_roriw_pc_wdata), + .spec_mem_addr(spec_insn_roriw_mem_addr), + .spec_mem_rmask(spec_insn_roriw_mem_rmask), + .spec_mem_wmask(spec_insn_roriw_mem_wmask), + .spec_mem_wdata(spec_insn_roriw_mem_wdata) + ); + + wire spec_insn_rorw_valid; + wire spec_insn_rorw_trap; + wire [ 4 : 0] spec_insn_rorw_rs1_addr; + wire [ 4 : 0] spec_insn_rorw_rs2_addr; + wire [ 4 : 0] spec_insn_rorw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rorw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rorw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_csr_misa_rmask; +`endif + + rvfi_insn_rorw insn_rorw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rorw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rorw_valid), + .spec_trap(spec_insn_rorw_trap), + .spec_rs1_addr(spec_insn_rorw_rs1_addr), + .spec_rs2_addr(spec_insn_rorw_rs2_addr), + .spec_rd_addr(spec_insn_rorw_rd_addr), + .spec_rd_wdata(spec_insn_rorw_rd_wdata), + .spec_pc_wdata(spec_insn_rorw_pc_wdata), + .spec_mem_addr(spec_insn_rorw_mem_addr), + .spec_mem_rmask(spec_insn_rorw_mem_rmask), + .spec_mem_wmask(spec_insn_rorw_mem_wmask), + .spec_mem_wdata(spec_insn_rorw_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sd_valid; + wire spec_insn_sd_trap; + wire [ 4 : 0] spec_insn_sd_rs1_addr; + wire [ 4 : 0] spec_insn_sd_rs2_addr; + wire [ 4 : 0] spec_insn_sd_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; +`endif + + rvfi_insn_sd insn_sd ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sd_valid), + .spec_trap(spec_insn_sd_trap), + .spec_rs1_addr(spec_insn_sd_rs1_addr), + .spec_rs2_addr(spec_insn_sd_rs2_addr), + .spec_rd_addr(spec_insn_sd_rd_addr), + .spec_rd_wdata(spec_insn_sd_rd_wdata), + .spec_pc_wdata(spec_insn_sd_pc_wdata), + .spec_mem_addr(spec_insn_sd_mem_addr), + .spec_mem_rmask(spec_insn_sd_mem_rmask), + .spec_mem_wmask(spec_insn_sd_mem_wmask), + .spec_mem_wdata(spec_insn_sd_mem_wdata) + ); + + wire spec_insn_sext_b_valid; + wire spec_insn_sext_b_trap; + wire [ 4 : 0] spec_insn_sext_b_rs1_addr; + wire [ 4 : 0] spec_insn_sext_b_rs2_addr; + wire [ 4 : 0] spec_insn_sext_b_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_csr_misa_rmask; +`endif + + rvfi_insn_sext_b insn_sext_b ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_b_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_b_valid), + .spec_trap(spec_insn_sext_b_trap), + .spec_rs1_addr(spec_insn_sext_b_rs1_addr), + .spec_rs2_addr(spec_insn_sext_b_rs2_addr), + .spec_rd_addr(spec_insn_sext_b_rd_addr), + .spec_rd_wdata(spec_insn_sext_b_rd_wdata), + .spec_pc_wdata(spec_insn_sext_b_pc_wdata), + .spec_mem_addr(spec_insn_sext_b_mem_addr), + .spec_mem_rmask(spec_insn_sext_b_mem_rmask), + .spec_mem_wmask(spec_insn_sext_b_mem_wmask), + .spec_mem_wdata(spec_insn_sext_b_mem_wdata) + ); + + wire spec_insn_sext_h_valid; + wire spec_insn_sext_h_trap; + wire [ 4 : 0] spec_insn_sext_h_rs1_addr; + wire [ 4 : 0] spec_insn_sext_h_rs2_addr; + wire [ 4 : 0] spec_insn_sext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_csr_misa_rmask; +`endif + + rvfi_insn_sext_h insn_sext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_h_valid), + .spec_trap(spec_insn_sext_h_trap), + .spec_rs1_addr(spec_insn_sext_h_rs1_addr), + .spec_rs2_addr(spec_insn_sext_h_rs2_addr), + .spec_rd_addr(spec_insn_sext_h_rd_addr), + .spec_rd_wdata(spec_insn_sext_h_rd_wdata), + .spec_pc_wdata(spec_insn_sext_h_pc_wdata), + .spec_mem_addr(spec_insn_sext_h_mem_addr), + .spec_mem_rmask(spec_insn_sext_h_mem_rmask), + .spec_mem_wmask(spec_insn_sext_h_mem_wmask), + .spec_mem_wdata(spec_insn_sext_h_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slliw_valid; + wire spec_insn_slliw_trap; + wire [ 4 : 0] spec_insn_slliw_rs1_addr; + wire [ 4 : 0] spec_insn_slliw_rs2_addr; + wire [ 4 : 0] spec_insn_slliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; +`endif + + rvfi_insn_slliw insn_slliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slliw_valid), + .spec_trap(spec_insn_slliw_trap), + .spec_rs1_addr(spec_insn_slliw_rs1_addr), + .spec_rs2_addr(spec_insn_slliw_rs2_addr), + .spec_rd_addr(spec_insn_slliw_rd_addr), + .spec_rd_wdata(spec_insn_slliw_rd_wdata), + .spec_pc_wdata(spec_insn_slliw_pc_wdata), + .spec_mem_addr(spec_insn_slliw_mem_addr), + .spec_mem_rmask(spec_insn_slliw_mem_rmask), + .spec_mem_wmask(spec_insn_slliw_mem_wmask), + .spec_mem_wdata(spec_insn_slliw_mem_wdata) + ); + + wire spec_insn_sllw_valid; + wire spec_insn_sllw_trap; + wire [ 4 : 0] spec_insn_sllw_rs1_addr; + wire [ 4 : 0] spec_insn_sllw_rs2_addr; + wire [ 4 : 0] spec_insn_sllw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; +`endif + + rvfi_insn_sllw insn_sllw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sllw_valid), + .spec_trap(spec_insn_sllw_trap), + .spec_rs1_addr(spec_insn_sllw_rs1_addr), + .spec_rs2_addr(spec_insn_sllw_rs2_addr), + .spec_rd_addr(spec_insn_sllw_rd_addr), + .spec_rd_wdata(spec_insn_sllw_rd_wdata), + .spec_pc_wdata(spec_insn_sllw_pc_wdata), + .spec_mem_addr(spec_insn_sllw_mem_addr), + .spec_mem_rmask(spec_insn_sllw_mem_rmask), + .spec_mem_wmask(spec_insn_sllw_mem_wmask), + .spec_mem_wdata(spec_insn_sllw_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_sraiw_valid; + wire spec_insn_sraiw_trap; + wire [ 4 : 0] spec_insn_sraiw_rs1_addr; + wire [ 4 : 0] spec_insn_sraiw_rs2_addr; + wire [ 4 : 0] spec_insn_sraiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; +`endif + + rvfi_insn_sraiw insn_sraiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraiw_valid), + .spec_trap(spec_insn_sraiw_trap), + .spec_rs1_addr(spec_insn_sraiw_rs1_addr), + .spec_rs2_addr(spec_insn_sraiw_rs2_addr), + .spec_rd_addr(spec_insn_sraiw_rd_addr), + .spec_rd_wdata(spec_insn_sraiw_rd_wdata), + .spec_pc_wdata(spec_insn_sraiw_pc_wdata), + .spec_mem_addr(spec_insn_sraiw_mem_addr), + .spec_mem_rmask(spec_insn_sraiw_mem_rmask), + .spec_mem_wmask(spec_insn_sraiw_mem_wmask), + .spec_mem_wdata(spec_insn_sraiw_mem_wdata) + ); + + wire spec_insn_sraw_valid; + wire spec_insn_sraw_trap; + wire [ 4 : 0] spec_insn_sraw_rs1_addr; + wire [ 4 : 0] spec_insn_sraw_rs2_addr; + wire [ 4 : 0] spec_insn_sraw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; +`endif + + rvfi_insn_sraw insn_sraw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraw_valid), + .spec_trap(spec_insn_sraw_trap), + .spec_rs1_addr(spec_insn_sraw_rs1_addr), + .spec_rs2_addr(spec_insn_sraw_rs2_addr), + .spec_rd_addr(spec_insn_sraw_rd_addr), + .spec_rd_wdata(spec_insn_sraw_rd_wdata), + .spec_pc_wdata(spec_insn_sraw_pc_wdata), + .spec_mem_addr(spec_insn_sraw_mem_addr), + .spec_mem_rmask(spec_insn_sraw_mem_rmask), + .spec_mem_wmask(spec_insn_sraw_mem_wmask), + .spec_mem_wdata(spec_insn_sraw_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_srliw_valid; + wire spec_insn_srliw_trap; + wire [ 4 : 0] spec_insn_srliw_rs1_addr; + wire [ 4 : 0] spec_insn_srliw_rs2_addr; + wire [ 4 : 0] spec_insn_srliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; +`endif + + rvfi_insn_srliw insn_srliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srliw_valid), + .spec_trap(spec_insn_srliw_trap), + .spec_rs1_addr(spec_insn_srliw_rs1_addr), + .spec_rs2_addr(spec_insn_srliw_rs2_addr), + .spec_rd_addr(spec_insn_srliw_rd_addr), + .spec_rd_wdata(spec_insn_srliw_rd_wdata), + .spec_pc_wdata(spec_insn_srliw_pc_wdata), + .spec_mem_addr(spec_insn_srliw_mem_addr), + .spec_mem_rmask(spec_insn_srliw_mem_rmask), + .spec_mem_wmask(spec_insn_srliw_mem_wmask), + .spec_mem_wdata(spec_insn_srliw_mem_wdata) + ); + + wire spec_insn_srlw_valid; + wire spec_insn_srlw_trap; + wire [ 4 : 0] spec_insn_srlw_rs1_addr; + wire [ 4 : 0] spec_insn_srlw_rs2_addr; + wire [ 4 : 0] spec_insn_srlw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; +`endif + + rvfi_insn_srlw insn_srlw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srlw_valid), + .spec_trap(spec_insn_srlw_trap), + .spec_rs1_addr(spec_insn_srlw_rs1_addr), + .spec_rs2_addr(spec_insn_srlw_rs2_addr), + .spec_rd_addr(spec_insn_srlw_rd_addr), + .spec_rd_wdata(spec_insn_srlw_rd_wdata), + .spec_pc_wdata(spec_insn_srlw_pc_wdata), + .spec_mem_addr(spec_insn_srlw_mem_addr), + .spec_mem_rmask(spec_insn_srlw_mem_rmask), + .spec_mem_wmask(spec_insn_srlw_mem_wmask), + .spec_mem_wdata(spec_insn_srlw_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_subw_valid; + wire spec_insn_subw_trap; + wire [ 4 : 0] spec_insn_subw_rs1_addr; + wire [ 4 : 0] spec_insn_subw_rs2_addr; + wire [ 4 : 0] spec_insn_subw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; +`endif + + rvfi_insn_subw insn_subw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_subw_valid), + .spec_trap(spec_insn_subw_trap), + .spec_rs1_addr(spec_insn_subw_rs1_addr), + .spec_rs2_addr(spec_insn_subw_rs2_addr), + .spec_rd_addr(spec_insn_subw_rd_addr), + .spec_rd_wdata(spec_insn_subw_rd_wdata), + .spec_pc_wdata(spec_insn_subw_pc_wdata), + .spec_mem_addr(spec_insn_subw_mem_addr), + .spec_mem_rmask(spec_insn_subw_mem_rmask), + .spec_mem_wmask(spec_insn_subw_mem_wmask), + .spec_mem_wdata(spec_insn_subw_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xnor_valid; + wire spec_insn_xnor_trap; + wire [ 4 : 0] spec_insn_xnor_rs1_addr; + wire [ 4 : 0] spec_insn_xnor_rs2_addr; + wire [ 4 : 0] spec_insn_xnor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_csr_misa_rmask; +`endif + + rvfi_insn_xnor insn_xnor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xnor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xnor_valid), + .spec_trap(spec_insn_xnor_trap), + .spec_rs1_addr(spec_insn_xnor_rs1_addr), + .spec_rs2_addr(spec_insn_xnor_rs2_addr), + .spec_rd_addr(spec_insn_xnor_rd_addr), + .spec_rd_wdata(spec_insn_xnor_rd_wdata), + .spec_pc_wdata(spec_insn_xnor_pc_wdata), + .spec_mem_addr(spec_insn_xnor_mem_addr), + .spec_mem_rmask(spec_insn_xnor_mem_rmask), + .spec_mem_wmask(spec_insn_xnor_mem_wmask), + .spec_mem_wdata(spec_insn_xnor_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + wire spec_insn_zext_h_valid; + wire spec_insn_zext_h_trap; + wire [ 4 : 0] spec_insn_zext_h_rs1_addr; + wire [ 4 : 0] spec_insn_zext_h_rs2_addr; + wire [ 4 : 0] spec_insn_zext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_csr_misa_rmask; +`endif + + rvfi_insn_zext_h insn_zext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_zext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_zext_h_valid), + .spec_trap(spec_insn_zext_h_trap), + .spec_rs1_addr(spec_insn_zext_h_rs1_addr), + .spec_rs2_addr(spec_insn_zext_h_rs2_addr), + .spec_rd_addr(spec_insn_zext_h_rd_addr), + .spec_rd_wdata(spec_insn_zext_h_rd_wdata), + .spec_pc_wdata(spec_insn_zext_h_pc_wdata), + .spec_mem_addr(spec_insn_zext_h_mem_addr), + .spec_mem_rmask(spec_insn_zext_h_mem_rmask), + .spec_mem_wmask(spec_insn_zext_h_mem_wmask), + .spec_mem_wdata(spec_insn_zext_h_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_addiw_valid ? spec_insn_addiw_valid : + spec_insn_addw_valid ? spec_insn_addw_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_andn_valid ? spec_insn_andn_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_clz_valid ? spec_insn_clz_valid : + spec_insn_clzw_valid ? spec_insn_clzw_valid : + spec_insn_cpop_valid ? spec_insn_cpop_valid : + spec_insn_cpopw_valid ? spec_insn_cpopw_valid : + spec_insn_ctz_valid ? spec_insn_ctz_valid : + spec_insn_ctzw_valid ? spec_insn_ctzw_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_ld_valid ? spec_insn_ld_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_lwu_valid ? spec_insn_lwu_valid : + spec_insn_max_valid ? spec_insn_max_valid : + spec_insn_maxu_valid ? spec_insn_maxu_valid : + spec_insn_min_valid ? spec_insn_min_valid : + spec_insn_minu_valid ? spec_insn_minu_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_orn_valid ? spec_insn_orn_valid : + spec_insn_rol_valid ? spec_insn_rol_valid : + spec_insn_rolw_valid ? spec_insn_rolw_valid : + spec_insn_ror_valid ? spec_insn_ror_valid : + spec_insn_rori_valid ? spec_insn_rori_valid : + spec_insn_roriw_valid ? spec_insn_roriw_valid : + spec_insn_rorw_valid ? spec_insn_rorw_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sd_valid ? spec_insn_sd_valid : + spec_insn_sext_b_valid ? spec_insn_sext_b_valid : + spec_insn_sext_h_valid ? spec_insn_sext_h_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slliw_valid ? spec_insn_slliw_valid : + spec_insn_sllw_valid ? spec_insn_sllw_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_sraiw_valid ? spec_insn_sraiw_valid : + spec_insn_sraw_valid ? spec_insn_sraw_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_srliw_valid ? spec_insn_srliw_valid : + spec_insn_srlw_valid ? spec_insn_srlw_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_subw_valid ? spec_insn_subw_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xnor_valid ? spec_insn_xnor_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : + spec_insn_zext_h_valid ? spec_insn_zext_h_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_addiw_valid ? spec_insn_addiw_trap : + spec_insn_addw_valid ? spec_insn_addw_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_andn_valid ? spec_insn_andn_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_clz_valid ? spec_insn_clz_trap : + spec_insn_clzw_valid ? spec_insn_clzw_trap : + spec_insn_cpop_valid ? spec_insn_cpop_trap : + spec_insn_cpopw_valid ? spec_insn_cpopw_trap : + spec_insn_ctz_valid ? spec_insn_ctz_trap : + spec_insn_ctzw_valid ? spec_insn_ctzw_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_ld_valid ? spec_insn_ld_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_lwu_valid ? spec_insn_lwu_trap : + spec_insn_max_valid ? spec_insn_max_trap : + spec_insn_maxu_valid ? spec_insn_maxu_trap : + spec_insn_min_valid ? spec_insn_min_trap : + spec_insn_minu_valid ? spec_insn_minu_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_orn_valid ? spec_insn_orn_trap : + spec_insn_rol_valid ? spec_insn_rol_trap : + spec_insn_rolw_valid ? spec_insn_rolw_trap : + spec_insn_ror_valid ? spec_insn_ror_trap : + spec_insn_rori_valid ? spec_insn_rori_trap : + spec_insn_roriw_valid ? spec_insn_roriw_trap : + spec_insn_rorw_valid ? spec_insn_rorw_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sd_valid ? spec_insn_sd_trap : + spec_insn_sext_b_valid ? spec_insn_sext_b_trap : + spec_insn_sext_h_valid ? spec_insn_sext_h_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slliw_valid ? spec_insn_slliw_trap : + spec_insn_sllw_valid ? spec_insn_sllw_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_sraiw_valid ? spec_insn_sraiw_trap : + spec_insn_sraw_valid ? spec_insn_sraw_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_srliw_valid ? spec_insn_srliw_trap : + spec_insn_srlw_valid ? spec_insn_srlw_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_subw_valid ? spec_insn_subw_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xnor_valid ? spec_insn_xnor_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : + spec_insn_zext_h_valid ? spec_insn_zext_h_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : + spec_insn_addw_valid ? spec_insn_addw_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_andn_valid ? spec_insn_andn_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_clz_valid ? spec_insn_clz_rs1_addr : + spec_insn_clzw_valid ? spec_insn_clzw_rs1_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs1_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_rs1_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs1_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_ld_valid ? spec_insn_ld_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : + spec_insn_max_valid ? spec_insn_max_rs1_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs1_addr : + spec_insn_min_valid ? spec_insn_min_rs1_addr : + spec_insn_minu_valid ? spec_insn_minu_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_orn_valid ? spec_insn_orn_rs1_addr : + spec_insn_rol_valid ? spec_insn_rol_rs1_addr : + spec_insn_rolw_valid ? spec_insn_rolw_rs1_addr : + spec_insn_ror_valid ? spec_insn_ror_rs1_addr : + spec_insn_rori_valid ? spec_insn_rori_rs1_addr : + spec_insn_roriw_valid ? spec_insn_roriw_rs1_addr : + spec_insn_rorw_valid ? spec_insn_rorw_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sd_valid ? spec_insn_sd_rs1_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs1_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_subw_valid ? spec_insn_subw_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : + spec_insn_addw_valid ? spec_insn_addw_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_andn_valid ? spec_insn_andn_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_clz_valid ? spec_insn_clz_rs2_addr : + spec_insn_clzw_valid ? spec_insn_clzw_rs2_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs2_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_rs2_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs2_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_ld_valid ? spec_insn_ld_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : + spec_insn_max_valid ? spec_insn_max_rs2_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs2_addr : + spec_insn_min_valid ? spec_insn_min_rs2_addr : + spec_insn_minu_valid ? spec_insn_minu_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_orn_valid ? spec_insn_orn_rs2_addr : + spec_insn_rol_valid ? spec_insn_rol_rs2_addr : + spec_insn_rolw_valid ? spec_insn_rolw_rs2_addr : + spec_insn_ror_valid ? spec_insn_ror_rs2_addr : + spec_insn_rori_valid ? spec_insn_rori_rs2_addr : + spec_insn_roriw_valid ? spec_insn_roriw_rs2_addr : + spec_insn_rorw_valid ? spec_insn_rorw_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sd_valid ? spec_insn_sd_rs2_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs2_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_subw_valid ? spec_insn_subw_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : + spec_insn_addw_valid ? spec_insn_addw_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_andn_valid ? spec_insn_andn_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_clz_valid ? spec_insn_clz_rd_addr : + spec_insn_clzw_valid ? spec_insn_clzw_rd_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rd_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_rd_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rd_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_ld_valid ? spec_insn_ld_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : + spec_insn_max_valid ? spec_insn_max_rd_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rd_addr : + spec_insn_min_valid ? spec_insn_min_rd_addr : + spec_insn_minu_valid ? spec_insn_minu_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_orn_valid ? spec_insn_orn_rd_addr : + spec_insn_rol_valid ? spec_insn_rol_rd_addr : + spec_insn_rolw_valid ? spec_insn_rolw_rd_addr : + spec_insn_ror_valid ? spec_insn_ror_rd_addr : + spec_insn_rori_valid ? spec_insn_rori_rd_addr : + spec_insn_roriw_valid ? spec_insn_roriw_rd_addr : + spec_insn_rorw_valid ? spec_insn_rorw_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sd_valid ? spec_insn_sd_rd_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_subw_valid ? spec_insn_subw_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : + spec_insn_addw_valid ? spec_insn_addw_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_andn_valid ? spec_insn_andn_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_clz_valid ? spec_insn_clz_rd_wdata : + spec_insn_clzw_valid ? spec_insn_clzw_rd_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_rd_wdata : + spec_insn_cpopw_valid ? spec_insn_cpopw_rd_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_rd_wdata : + spec_insn_ctzw_valid ? spec_insn_ctzw_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_ld_valid ? spec_insn_ld_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : + spec_insn_max_valid ? spec_insn_max_rd_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_rd_wdata : + spec_insn_min_valid ? spec_insn_min_rd_wdata : + spec_insn_minu_valid ? spec_insn_minu_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_orn_valid ? spec_insn_orn_rd_wdata : + spec_insn_rol_valid ? spec_insn_rol_rd_wdata : + spec_insn_rolw_valid ? spec_insn_rolw_rd_wdata : + spec_insn_ror_valid ? spec_insn_ror_rd_wdata : + spec_insn_rori_valid ? spec_insn_rori_rd_wdata : + spec_insn_roriw_valid ? spec_insn_roriw_rd_wdata : + spec_insn_rorw_valid ? spec_insn_rorw_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sd_valid ? spec_insn_sd_rd_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_subw_valid ? spec_insn_subw_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : + spec_insn_addw_valid ? spec_insn_addw_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_andn_valid ? spec_insn_andn_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_clz_valid ? spec_insn_clz_pc_wdata : + spec_insn_clzw_valid ? spec_insn_clzw_pc_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_pc_wdata : + spec_insn_cpopw_valid ? spec_insn_cpopw_pc_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_pc_wdata : + spec_insn_ctzw_valid ? spec_insn_ctzw_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_ld_valid ? spec_insn_ld_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : + spec_insn_max_valid ? spec_insn_max_pc_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_pc_wdata : + spec_insn_min_valid ? spec_insn_min_pc_wdata : + spec_insn_minu_valid ? spec_insn_minu_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_orn_valid ? spec_insn_orn_pc_wdata : + spec_insn_rol_valid ? spec_insn_rol_pc_wdata : + spec_insn_rolw_valid ? spec_insn_rolw_pc_wdata : + spec_insn_ror_valid ? spec_insn_ror_pc_wdata : + spec_insn_rori_valid ? spec_insn_rori_pc_wdata : + spec_insn_roriw_valid ? spec_insn_roriw_pc_wdata : + spec_insn_rorw_valid ? spec_insn_rorw_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sd_valid ? spec_insn_sd_pc_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_pc_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_subw_valid ? spec_insn_subw_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : + spec_insn_addw_valid ? spec_insn_addw_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_andn_valid ? spec_insn_andn_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_clz_valid ? spec_insn_clz_mem_addr : + spec_insn_clzw_valid ? spec_insn_clzw_mem_addr : + spec_insn_cpop_valid ? spec_insn_cpop_mem_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_addr : + spec_insn_ctz_valid ? spec_insn_ctz_mem_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_ld_valid ? spec_insn_ld_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : + spec_insn_max_valid ? spec_insn_max_mem_addr : + spec_insn_maxu_valid ? spec_insn_maxu_mem_addr : + spec_insn_min_valid ? spec_insn_min_mem_addr : + spec_insn_minu_valid ? spec_insn_minu_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_orn_valid ? spec_insn_orn_mem_addr : + spec_insn_rol_valid ? spec_insn_rol_mem_addr : + spec_insn_rolw_valid ? spec_insn_rolw_mem_addr : + spec_insn_ror_valid ? spec_insn_ror_mem_addr : + spec_insn_rori_valid ? spec_insn_rori_mem_addr : + spec_insn_roriw_valid ? spec_insn_roriw_mem_addr : + spec_insn_rorw_valid ? spec_insn_rorw_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sd_valid ? spec_insn_sd_mem_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : + spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : + spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : + spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_subw_valid ? spec_insn_subw_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xnor_valid ? spec_insn_xnor_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : + spec_insn_addw_valid ? spec_insn_addw_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_andn_valid ? spec_insn_andn_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_clz_valid ? spec_insn_clz_mem_rmask : + spec_insn_clzw_valid ? spec_insn_clzw_mem_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_rmask : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_rmask : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_ld_valid ? spec_insn_ld_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : + spec_insn_max_valid ? spec_insn_max_mem_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_rmask : + spec_insn_min_valid ? spec_insn_min_mem_rmask : + spec_insn_minu_valid ? spec_insn_minu_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_orn_valid ? spec_insn_orn_mem_rmask : + spec_insn_rol_valid ? spec_insn_rol_mem_rmask : + spec_insn_rolw_valid ? spec_insn_rolw_mem_rmask : + spec_insn_ror_valid ? spec_insn_ror_mem_rmask : + spec_insn_rori_valid ? spec_insn_rori_mem_rmask : + spec_insn_roriw_valid ? spec_insn_roriw_mem_rmask : + spec_insn_rorw_valid ? spec_insn_rorw_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sd_valid ? spec_insn_sd_mem_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_subw_valid ? spec_insn_subw_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : + spec_insn_addw_valid ? spec_insn_addw_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_andn_valid ? spec_insn_andn_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_clz_valid ? spec_insn_clz_mem_wmask : + spec_insn_clzw_valid ? spec_insn_clzw_mem_wmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wmask : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_wmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wmask : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_ld_valid ? spec_insn_ld_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : + spec_insn_max_valid ? spec_insn_max_mem_wmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wmask : + spec_insn_min_valid ? spec_insn_min_mem_wmask : + spec_insn_minu_valid ? spec_insn_minu_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_orn_valid ? spec_insn_orn_mem_wmask : + spec_insn_rol_valid ? spec_insn_rol_mem_wmask : + spec_insn_rolw_valid ? spec_insn_rolw_mem_wmask : + spec_insn_ror_valid ? spec_insn_ror_mem_wmask : + spec_insn_rori_valid ? spec_insn_rori_mem_wmask : + spec_insn_roriw_valid ? spec_insn_roriw_mem_wmask : + spec_insn_rorw_valid ? spec_insn_rorw_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sd_valid ? spec_insn_sd_mem_wmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_subw_valid ? spec_insn_subw_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : + spec_insn_addw_valid ? spec_insn_addw_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_andn_valid ? spec_insn_andn_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_clz_valid ? spec_insn_clz_mem_wdata : + spec_insn_clzw_valid ? spec_insn_clzw_mem_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wdata : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wdata : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_ld_valid ? spec_insn_ld_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : + spec_insn_max_valid ? spec_insn_max_mem_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wdata : + spec_insn_min_valid ? spec_insn_min_mem_wdata : + spec_insn_minu_valid ? spec_insn_minu_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_orn_valid ? spec_insn_orn_mem_wdata : + spec_insn_rol_valid ? spec_insn_rol_mem_wdata : + spec_insn_rolw_valid ? spec_insn_rolw_mem_wdata : + spec_insn_ror_valid ? spec_insn_ror_mem_wdata : + spec_insn_rori_valid ? spec_insn_rori_mem_wdata : + spec_insn_roriw_valid ? spec_insn_roriw_mem_wdata : + spec_insn_rorw_valid ? spec_insn_rorw_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sd_valid ? spec_insn_sd_mem_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_subw_valid ? spec_insn_subw_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : + spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_andn_valid ? spec_insn_andn_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_clz_valid ? spec_insn_clz_csr_misa_rmask : + spec_insn_clzw_valid ? spec_insn_clzw_csr_misa_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_csr_misa_rmask : + spec_insn_cpopw_valid ? spec_insn_cpopw_csr_misa_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_csr_misa_rmask : + spec_insn_ctzw_valid ? spec_insn_ctzw_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : + spec_insn_max_valid ? spec_insn_max_csr_misa_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_csr_misa_rmask : + spec_insn_min_valid ? spec_insn_min_csr_misa_rmask : + spec_insn_minu_valid ? spec_insn_minu_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_orn_valid ? spec_insn_orn_csr_misa_rmask : + spec_insn_rol_valid ? spec_insn_rol_csr_misa_rmask : + spec_insn_rolw_valid ? spec_insn_rolw_csr_misa_rmask : + spec_insn_ror_valid ? spec_insn_ror_csr_misa_rmask : + spec_insn_rori_valid ? spec_insn_rori_csr_misa_rmask : + spec_insn_roriw_valid ? spec_insn_roriw_csr_misa_rmask : + spec_insn_rorw_valid ? spec_insn_rorw_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_csr_misa_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_csr_misa_rmask : 0; +`endif +endmodule diff --git a/insns/isa_rv64ib.txt b/insns/isa_rv64ib.txt index bb162e74..12fd7059 100644 --- a/insns/isa_rv64ib.txt +++ b/insns/isa_rv64ib.txt @@ -5,6 +5,7 @@ addiw addw and andi +andn auipc beq bge @@ -12,6 +13,12 @@ bgeu blt bltu bne +clz +clzw +cpop +cpopw +ctz +ctzw jal jalr lb @@ -22,10 +29,23 @@ lhu lui lw lwu +max +maxu +min +minu or ori +orn +rol +rolw +ror +rori +roriw +rorw sb sd +sext_b +sext_h sh sh1add sh1add_uw @@ -53,5 +73,7 @@ srlw sub subw sw +xnor xor xori +zext_h diff --git a/insns/isa_rv64ib.v b/insns/isa_rv64ib.v index b9c2a24f..c3ab8e10 100644 --- a/insns/isa_rv64ib.v +++ b/insns/isa_rv64ib.v @@ -297,6 +297,45 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_andi_mem_wdata) ); + wire spec_insn_andn_valid; + wire spec_insn_andn_trap; + wire [ 4 : 0] spec_insn_andn_rs1_addr; + wire [ 4 : 0] spec_insn_andn_rs2_addr; + wire [ 4 : 0] spec_insn_andn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andn_csr_misa_rmask; +`endif + + rvfi_insn_andn insn_andn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andn_valid), + .spec_trap(spec_insn_andn_trap), + .spec_rs1_addr(spec_insn_andn_rs1_addr), + .spec_rs2_addr(spec_insn_andn_rs2_addr), + .spec_rd_addr(spec_insn_andn_rd_addr), + .spec_rd_wdata(spec_insn_andn_rd_wdata), + .spec_pc_wdata(spec_insn_andn_pc_wdata), + .spec_mem_addr(spec_insn_andn_mem_addr), + .spec_mem_rmask(spec_insn_andn_mem_rmask), + .spec_mem_wmask(spec_insn_andn_mem_wmask), + .spec_mem_wdata(spec_insn_andn_mem_wdata) + ); + wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; @@ -570,6 +609,240 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_bne_mem_wdata) ); + wire spec_insn_clz_valid; + wire spec_insn_clz_trap; + wire [ 4 : 0] spec_insn_clz_rs1_addr; + wire [ 4 : 0] spec_insn_clz_rs2_addr; + wire [ 4 : 0] spec_insn_clz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clz_csr_misa_rmask; +`endif + + rvfi_insn_clz insn_clz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_clz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_clz_valid), + .spec_trap(spec_insn_clz_trap), + .spec_rs1_addr(spec_insn_clz_rs1_addr), + .spec_rs2_addr(spec_insn_clz_rs2_addr), + .spec_rd_addr(spec_insn_clz_rd_addr), + .spec_rd_wdata(spec_insn_clz_rd_wdata), + .spec_pc_wdata(spec_insn_clz_pc_wdata), + .spec_mem_addr(spec_insn_clz_mem_addr), + .spec_mem_rmask(spec_insn_clz_mem_rmask), + .spec_mem_wmask(spec_insn_clz_mem_wmask), + .spec_mem_wdata(spec_insn_clz_mem_wdata) + ); + + wire spec_insn_clzw_valid; + wire spec_insn_clzw_trap; + wire [ 4 : 0] spec_insn_clzw_rs1_addr; + wire [ 4 : 0] spec_insn_clzw_rs2_addr; + wire [ 4 : 0] spec_insn_clzw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clzw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clzw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_clzw_csr_misa_rmask; +`endif + + rvfi_insn_clzw insn_clzw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_clzw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_clzw_valid), + .spec_trap(spec_insn_clzw_trap), + .spec_rs1_addr(spec_insn_clzw_rs1_addr), + .spec_rs2_addr(spec_insn_clzw_rs2_addr), + .spec_rd_addr(spec_insn_clzw_rd_addr), + .spec_rd_wdata(spec_insn_clzw_rd_wdata), + .spec_pc_wdata(spec_insn_clzw_pc_wdata), + .spec_mem_addr(spec_insn_clzw_mem_addr), + .spec_mem_rmask(spec_insn_clzw_mem_rmask), + .spec_mem_wmask(spec_insn_clzw_mem_wmask), + .spec_mem_wdata(spec_insn_clzw_mem_wdata) + ); + + wire spec_insn_cpop_valid; + wire spec_insn_cpop_trap; + wire [ 4 : 0] spec_insn_cpop_rs1_addr; + wire [ 4 : 0] spec_insn_cpop_rs2_addr; + wire [ 4 : 0] spec_insn_cpop_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpop_csr_misa_rmask; +`endif + + rvfi_insn_cpop insn_cpop ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_cpop_csr_misa_rmask), +`endif + .spec_valid(spec_insn_cpop_valid), + .spec_trap(spec_insn_cpop_trap), + .spec_rs1_addr(spec_insn_cpop_rs1_addr), + .spec_rs2_addr(spec_insn_cpop_rs2_addr), + .spec_rd_addr(spec_insn_cpop_rd_addr), + .spec_rd_wdata(spec_insn_cpop_rd_wdata), + .spec_pc_wdata(spec_insn_cpop_pc_wdata), + .spec_mem_addr(spec_insn_cpop_mem_addr), + .spec_mem_rmask(spec_insn_cpop_mem_rmask), + .spec_mem_wmask(spec_insn_cpop_mem_wmask), + .spec_mem_wdata(spec_insn_cpop_mem_wdata) + ); + + wire spec_insn_cpopw_valid; + wire spec_insn_cpopw_trap; + wire [ 4 : 0] spec_insn_cpopw_rs1_addr; + wire [ 4 : 0] spec_insn_cpopw_rs2_addr; + wire [ 4 : 0] spec_insn_cpopw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpopw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpopw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_cpopw_csr_misa_rmask; +`endif + + rvfi_insn_cpopw insn_cpopw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_cpopw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_cpopw_valid), + .spec_trap(spec_insn_cpopw_trap), + .spec_rs1_addr(spec_insn_cpopw_rs1_addr), + .spec_rs2_addr(spec_insn_cpopw_rs2_addr), + .spec_rd_addr(spec_insn_cpopw_rd_addr), + .spec_rd_wdata(spec_insn_cpopw_rd_wdata), + .spec_pc_wdata(spec_insn_cpopw_pc_wdata), + .spec_mem_addr(spec_insn_cpopw_mem_addr), + .spec_mem_rmask(spec_insn_cpopw_mem_rmask), + .spec_mem_wmask(spec_insn_cpopw_mem_wmask), + .spec_mem_wdata(spec_insn_cpopw_mem_wdata) + ); + + wire spec_insn_ctz_valid; + wire spec_insn_ctz_trap; + wire [ 4 : 0] spec_insn_ctz_rs1_addr; + wire [ 4 : 0] spec_insn_ctz_rs2_addr; + wire [ 4 : 0] spec_insn_ctz_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctz_csr_misa_rmask; +`endif + + rvfi_insn_ctz insn_ctz ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ctz_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ctz_valid), + .spec_trap(spec_insn_ctz_trap), + .spec_rs1_addr(spec_insn_ctz_rs1_addr), + .spec_rs2_addr(spec_insn_ctz_rs2_addr), + .spec_rd_addr(spec_insn_ctz_rd_addr), + .spec_rd_wdata(spec_insn_ctz_rd_wdata), + .spec_pc_wdata(spec_insn_ctz_pc_wdata), + .spec_mem_addr(spec_insn_ctz_mem_addr), + .spec_mem_rmask(spec_insn_ctz_mem_rmask), + .spec_mem_wmask(spec_insn_ctz_mem_wmask), + .spec_mem_wdata(spec_insn_ctz_mem_wdata) + ); + + wire spec_insn_ctzw_valid; + wire spec_insn_ctzw_trap; + wire [ 4 : 0] spec_insn_ctzw_rs1_addr; + wire [ 4 : 0] spec_insn_ctzw_rs2_addr; + wire [ 4 : 0] spec_insn_ctzw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctzw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctzw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ctzw_csr_misa_rmask; +`endif + + rvfi_insn_ctzw insn_ctzw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ctzw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ctzw_valid), + .spec_trap(spec_insn_ctzw_trap), + .spec_rs1_addr(spec_insn_ctzw_rs1_addr), + .spec_rs2_addr(spec_insn_ctzw_rs2_addr), + .spec_rd_addr(spec_insn_ctzw_rd_addr), + .spec_rd_wdata(spec_insn_ctzw_rd_wdata), + .spec_pc_wdata(spec_insn_ctzw_pc_wdata), + .spec_mem_addr(spec_insn_ctzw_mem_addr), + .spec_mem_rmask(spec_insn_ctzw_mem_rmask), + .spec_mem_wmask(spec_insn_ctzw_mem_wmask), + .spec_mem_wdata(spec_insn_ctzw_mem_wdata) + ); + wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; @@ -960,6 +1233,162 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_lwu_mem_wdata) ); + wire spec_insn_max_valid; + wire spec_insn_max_trap; + wire [ 4 : 0] spec_insn_max_rs1_addr; + wire [ 4 : 0] spec_insn_max_rs2_addr; + wire [ 4 : 0] spec_insn_max_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_max_csr_misa_rmask; +`endif + + rvfi_insn_max insn_max ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_max_csr_misa_rmask), +`endif + .spec_valid(spec_insn_max_valid), + .spec_trap(spec_insn_max_trap), + .spec_rs1_addr(spec_insn_max_rs1_addr), + .spec_rs2_addr(spec_insn_max_rs2_addr), + .spec_rd_addr(spec_insn_max_rd_addr), + .spec_rd_wdata(spec_insn_max_rd_wdata), + .spec_pc_wdata(spec_insn_max_pc_wdata), + .spec_mem_addr(spec_insn_max_mem_addr), + .spec_mem_rmask(spec_insn_max_mem_rmask), + .spec_mem_wmask(spec_insn_max_mem_wmask), + .spec_mem_wdata(spec_insn_max_mem_wdata) + ); + + wire spec_insn_maxu_valid; + wire spec_insn_maxu_trap; + wire [ 4 : 0] spec_insn_maxu_rs1_addr; + wire [ 4 : 0] spec_insn_maxu_rs2_addr; + wire [ 4 : 0] spec_insn_maxu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_maxu_csr_misa_rmask; +`endif + + rvfi_insn_maxu insn_maxu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_maxu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_maxu_valid), + .spec_trap(spec_insn_maxu_trap), + .spec_rs1_addr(spec_insn_maxu_rs1_addr), + .spec_rs2_addr(spec_insn_maxu_rs2_addr), + .spec_rd_addr(spec_insn_maxu_rd_addr), + .spec_rd_wdata(spec_insn_maxu_rd_wdata), + .spec_pc_wdata(spec_insn_maxu_pc_wdata), + .spec_mem_addr(spec_insn_maxu_mem_addr), + .spec_mem_rmask(spec_insn_maxu_mem_rmask), + .spec_mem_wmask(spec_insn_maxu_mem_wmask), + .spec_mem_wdata(spec_insn_maxu_mem_wdata) + ); + + wire spec_insn_min_valid; + wire spec_insn_min_trap; + wire [ 4 : 0] spec_insn_min_rs1_addr; + wire [ 4 : 0] spec_insn_min_rs2_addr; + wire [ 4 : 0] spec_insn_min_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_min_csr_misa_rmask; +`endif + + rvfi_insn_min insn_min ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_min_csr_misa_rmask), +`endif + .spec_valid(spec_insn_min_valid), + .spec_trap(spec_insn_min_trap), + .spec_rs1_addr(spec_insn_min_rs1_addr), + .spec_rs2_addr(spec_insn_min_rs2_addr), + .spec_rd_addr(spec_insn_min_rd_addr), + .spec_rd_wdata(spec_insn_min_rd_wdata), + .spec_pc_wdata(spec_insn_min_pc_wdata), + .spec_mem_addr(spec_insn_min_mem_addr), + .spec_mem_rmask(spec_insn_min_mem_rmask), + .spec_mem_wmask(spec_insn_min_mem_wmask), + .spec_mem_wdata(spec_insn_min_mem_wdata) + ); + + wire spec_insn_minu_valid; + wire spec_insn_minu_trap; + wire [ 4 : 0] spec_insn_minu_rs1_addr; + wire [ 4 : 0] spec_insn_minu_rs2_addr; + wire [ 4 : 0] spec_insn_minu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_minu_csr_misa_rmask; +`endif + + rvfi_insn_minu insn_minu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_minu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_minu_valid), + .spec_trap(spec_insn_minu_trap), + .spec_rs1_addr(spec_insn_minu_rs1_addr), + .spec_rs2_addr(spec_insn_minu_rs2_addr), + .spec_rd_addr(spec_insn_minu_rd_addr), + .spec_rd_wdata(spec_insn_minu_rd_wdata), + .spec_pc_wdata(spec_insn_minu_pc_wdata), + .spec_mem_addr(spec_insn_minu_mem_addr), + .spec_mem_rmask(spec_insn_minu_mem_rmask), + .spec_mem_wmask(spec_insn_minu_mem_wmask), + .spec_mem_wdata(spec_insn_minu_mem_wdata) + ); + wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; @@ -1038,6 +1467,279 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_ori_mem_wdata) ); + wire spec_insn_orn_valid; + wire spec_insn_orn_trap; + wire [ 4 : 0] spec_insn_orn_rs1_addr; + wire [ 4 : 0] spec_insn_orn_rs2_addr; + wire [ 4 : 0] spec_insn_orn_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_orn_csr_misa_rmask; +`endif + + rvfi_insn_orn insn_orn ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_orn_csr_misa_rmask), +`endif + .spec_valid(spec_insn_orn_valid), + .spec_trap(spec_insn_orn_trap), + .spec_rs1_addr(spec_insn_orn_rs1_addr), + .spec_rs2_addr(spec_insn_orn_rs2_addr), + .spec_rd_addr(spec_insn_orn_rd_addr), + .spec_rd_wdata(spec_insn_orn_rd_wdata), + .spec_pc_wdata(spec_insn_orn_pc_wdata), + .spec_mem_addr(spec_insn_orn_mem_addr), + .spec_mem_rmask(spec_insn_orn_mem_rmask), + .spec_mem_wmask(spec_insn_orn_mem_wmask), + .spec_mem_wdata(spec_insn_orn_mem_wdata) + ); + + wire spec_insn_rol_valid; + wire spec_insn_rol_trap; + wire [ 4 : 0] spec_insn_rol_rs1_addr; + wire [ 4 : 0] spec_insn_rol_rs2_addr; + wire [ 4 : 0] spec_insn_rol_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rol_csr_misa_rmask; +`endif + + rvfi_insn_rol insn_rol ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rol_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rol_valid), + .spec_trap(spec_insn_rol_trap), + .spec_rs1_addr(spec_insn_rol_rs1_addr), + .spec_rs2_addr(spec_insn_rol_rs2_addr), + .spec_rd_addr(spec_insn_rol_rd_addr), + .spec_rd_wdata(spec_insn_rol_rd_wdata), + .spec_pc_wdata(spec_insn_rol_pc_wdata), + .spec_mem_addr(spec_insn_rol_mem_addr), + .spec_mem_rmask(spec_insn_rol_mem_rmask), + .spec_mem_wmask(spec_insn_rol_mem_wmask), + .spec_mem_wdata(spec_insn_rol_mem_wdata) + ); + + wire spec_insn_rolw_valid; + wire spec_insn_rolw_trap; + wire [ 4 : 0] spec_insn_rolw_rs1_addr; + wire [ 4 : 0] spec_insn_rolw_rs2_addr; + wire [ 4 : 0] spec_insn_rolw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rolw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rolw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rolw_csr_misa_rmask; +`endif + + rvfi_insn_rolw insn_rolw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rolw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rolw_valid), + .spec_trap(spec_insn_rolw_trap), + .spec_rs1_addr(spec_insn_rolw_rs1_addr), + .spec_rs2_addr(spec_insn_rolw_rs2_addr), + .spec_rd_addr(spec_insn_rolw_rd_addr), + .spec_rd_wdata(spec_insn_rolw_rd_wdata), + .spec_pc_wdata(spec_insn_rolw_pc_wdata), + .spec_mem_addr(spec_insn_rolw_mem_addr), + .spec_mem_rmask(spec_insn_rolw_mem_rmask), + .spec_mem_wmask(spec_insn_rolw_mem_wmask), + .spec_mem_wdata(spec_insn_rolw_mem_wdata) + ); + + wire spec_insn_ror_valid; + wire spec_insn_ror_trap; + wire [ 4 : 0] spec_insn_ror_rs1_addr; + wire [ 4 : 0] spec_insn_ror_rs2_addr; + wire [ 4 : 0] spec_insn_ror_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ror_csr_misa_rmask; +`endif + + rvfi_insn_ror insn_ror ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ror_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ror_valid), + .spec_trap(spec_insn_ror_trap), + .spec_rs1_addr(spec_insn_ror_rs1_addr), + .spec_rs2_addr(spec_insn_ror_rs2_addr), + .spec_rd_addr(spec_insn_ror_rd_addr), + .spec_rd_wdata(spec_insn_ror_rd_wdata), + .spec_pc_wdata(spec_insn_ror_pc_wdata), + .spec_mem_addr(spec_insn_ror_mem_addr), + .spec_mem_rmask(spec_insn_ror_mem_rmask), + .spec_mem_wmask(spec_insn_ror_mem_wmask), + .spec_mem_wdata(spec_insn_ror_mem_wdata) + ); + + wire spec_insn_rori_valid; + wire spec_insn_rori_trap; + wire [ 4 : 0] spec_insn_rori_rs1_addr; + wire [ 4 : 0] spec_insn_rori_rs2_addr; + wire [ 4 : 0] spec_insn_rori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rori_csr_misa_rmask; +`endif + + rvfi_insn_rori insn_rori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rori_valid), + .spec_trap(spec_insn_rori_trap), + .spec_rs1_addr(spec_insn_rori_rs1_addr), + .spec_rs2_addr(spec_insn_rori_rs2_addr), + .spec_rd_addr(spec_insn_rori_rd_addr), + .spec_rd_wdata(spec_insn_rori_rd_wdata), + .spec_pc_wdata(spec_insn_rori_pc_wdata), + .spec_mem_addr(spec_insn_rori_mem_addr), + .spec_mem_rmask(spec_insn_rori_mem_rmask), + .spec_mem_wmask(spec_insn_rori_mem_wmask), + .spec_mem_wdata(spec_insn_rori_mem_wdata) + ); + + wire spec_insn_roriw_valid; + wire spec_insn_roriw_trap; + wire [ 4 : 0] spec_insn_roriw_rs1_addr; + wire [ 4 : 0] spec_insn_roriw_rs2_addr; + wire [ 4 : 0] spec_insn_roriw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_roriw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_roriw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_roriw_csr_misa_rmask; +`endif + + rvfi_insn_roriw insn_roriw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_roriw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_roriw_valid), + .spec_trap(spec_insn_roriw_trap), + .spec_rs1_addr(spec_insn_roriw_rs1_addr), + .spec_rs2_addr(spec_insn_roriw_rs2_addr), + .spec_rd_addr(spec_insn_roriw_rd_addr), + .spec_rd_wdata(spec_insn_roriw_rd_wdata), + .spec_pc_wdata(spec_insn_roriw_pc_wdata), + .spec_mem_addr(spec_insn_roriw_mem_addr), + .spec_mem_rmask(spec_insn_roriw_mem_rmask), + .spec_mem_wmask(spec_insn_roriw_mem_wmask), + .spec_mem_wdata(spec_insn_roriw_mem_wdata) + ); + + wire spec_insn_rorw_valid; + wire spec_insn_rorw_trap; + wire [ 4 : 0] spec_insn_rorw_rs1_addr; + wire [ 4 : 0] spec_insn_rorw_rs2_addr; + wire [ 4 : 0] spec_insn_rorw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rorw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rorw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rorw_csr_misa_rmask; +`endif + + rvfi_insn_rorw insn_rorw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_rorw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_rorw_valid), + .spec_trap(spec_insn_rorw_trap), + .spec_rs1_addr(spec_insn_rorw_rs1_addr), + .spec_rs2_addr(spec_insn_rorw_rs2_addr), + .spec_rd_addr(spec_insn_rorw_rd_addr), + .spec_rd_wdata(spec_insn_rorw_rd_wdata), + .spec_pc_wdata(spec_insn_rorw_pc_wdata), + .spec_mem_addr(spec_insn_rorw_mem_addr), + .spec_mem_rmask(spec_insn_rorw_mem_rmask), + .spec_mem_wmask(spec_insn_rorw_mem_wmask), + .spec_mem_wdata(spec_insn_rorw_mem_wdata) + ); + wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; @@ -1116,6 +1818,84 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_sd_mem_wdata) ); + wire spec_insn_sext_b_valid; + wire spec_insn_sext_b_trap; + wire [ 4 : 0] spec_insn_sext_b_rs1_addr; + wire [ 4 : 0] spec_insn_sext_b_rs2_addr; + wire [ 4 : 0] spec_insn_sext_b_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_b_csr_misa_rmask; +`endif + + rvfi_insn_sext_b insn_sext_b ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_b_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_b_valid), + .spec_trap(spec_insn_sext_b_trap), + .spec_rs1_addr(spec_insn_sext_b_rs1_addr), + .spec_rs2_addr(spec_insn_sext_b_rs2_addr), + .spec_rd_addr(spec_insn_sext_b_rd_addr), + .spec_rd_wdata(spec_insn_sext_b_rd_wdata), + .spec_pc_wdata(spec_insn_sext_b_pc_wdata), + .spec_mem_addr(spec_insn_sext_b_mem_addr), + .spec_mem_rmask(spec_insn_sext_b_mem_rmask), + .spec_mem_wmask(spec_insn_sext_b_mem_wmask), + .spec_mem_wdata(spec_insn_sext_b_mem_wdata) + ); + + wire spec_insn_sext_h_valid; + wire spec_insn_sext_h_trap; + wire [ 4 : 0] spec_insn_sext_h_rs1_addr; + wire [ 4 : 0] spec_insn_sext_h_rs2_addr; + wire [ 4 : 0] spec_insn_sext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sext_h_csr_misa_rmask; +`endif + + rvfi_insn_sext_h insn_sext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sext_h_valid), + .spec_trap(spec_insn_sext_h_trap), + .spec_rs1_addr(spec_insn_sext_h_rs1_addr), + .spec_rs2_addr(spec_insn_sext_h_rs2_addr), + .spec_rd_addr(spec_insn_sext_h_rd_addr), + .spec_rd_wdata(spec_insn_sext_h_rd_wdata), + .spec_pc_wdata(spec_insn_sext_h_pc_wdata), + .spec_mem_addr(spec_insn_sext_h_mem_addr), + .spec_mem_rmask(spec_insn_sext_h_mem_rmask), + .spec_mem_wmask(spec_insn_sext_h_mem_wmask), + .spec_mem_wdata(spec_insn_sext_h_mem_wdata) + ); + wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; @@ -2169,6 +2949,45 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_sw_mem_wdata) ); + wire spec_insn_xnor_valid; + wire spec_insn_xnor_trap; + wire [ 4 : 0] spec_insn_xnor_rs1_addr; + wire [ 4 : 0] spec_insn_xnor_rs2_addr; + wire [ 4 : 0] spec_insn_xnor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xnor_csr_misa_rmask; +`endif + + rvfi_insn_xnor insn_xnor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xnor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xnor_valid), + .spec_trap(spec_insn_xnor_trap), + .spec_rs1_addr(spec_insn_xnor_rs1_addr), + .spec_rs2_addr(spec_insn_xnor_rs2_addr), + .spec_rd_addr(spec_insn_xnor_rd_addr), + .spec_rd_wdata(spec_insn_xnor_rd_wdata), + .spec_pc_wdata(spec_insn_xnor_pc_wdata), + .spec_mem_addr(spec_insn_xnor_mem_addr), + .spec_mem_rmask(spec_insn_xnor_mem_rmask), + .spec_mem_wmask(spec_insn_xnor_mem_wmask), + .spec_mem_wdata(spec_insn_xnor_mem_wdata) + ); + wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; @@ -2247,6 +3066,45 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_xori_mem_wdata) ); + wire spec_insn_zext_h_valid; + wire spec_insn_zext_h_trap; + wire [ 4 : 0] spec_insn_zext_h_rs1_addr; + wire [ 4 : 0] spec_insn_zext_h_rs2_addr; + wire [ 4 : 0] spec_insn_zext_h_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_zext_h_csr_misa_rmask; +`endif + + rvfi_insn_zext_h insn_zext_h ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_zext_h_csr_misa_rmask), +`endif + .spec_valid(spec_insn_zext_h_valid), + .spec_trap(spec_insn_zext_h_trap), + .spec_rs1_addr(spec_insn_zext_h_rs1_addr), + .spec_rs2_addr(spec_insn_zext_h_rs2_addr), + .spec_rd_addr(spec_insn_zext_h_rd_addr), + .spec_rd_wdata(spec_insn_zext_h_rd_wdata), + .spec_pc_wdata(spec_insn_zext_h_pc_wdata), + .spec_mem_addr(spec_insn_zext_h_mem_addr), + .spec_mem_rmask(spec_insn_zext_h_mem_rmask), + .spec_mem_wmask(spec_insn_zext_h_mem_wmask), + .spec_mem_wdata(spec_insn_zext_h_mem_wdata) + ); + assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_add_uw_valid ? spec_insn_add_uw_valid : @@ -2255,6 +3113,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_andn_valid ? spec_insn_andn_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : @@ -2262,6 +3121,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_clz_valid ? spec_insn_clz_valid : + spec_insn_clzw_valid ? spec_insn_clzw_valid : + spec_insn_cpop_valid ? spec_insn_cpop_valid : + spec_insn_cpopw_valid ? spec_insn_cpopw_valid : + spec_insn_ctz_valid ? spec_insn_ctz_valid : + spec_insn_ctzw_valid ? spec_insn_ctzw_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : @@ -2272,10 +3137,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_lwu_valid ? spec_insn_lwu_valid : + spec_insn_max_valid ? spec_insn_max_valid : + spec_insn_maxu_valid ? spec_insn_maxu_valid : + spec_insn_min_valid ? spec_insn_min_valid : + spec_insn_minu_valid ? spec_insn_minu_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_orn_valid ? spec_insn_orn_valid : + spec_insn_rol_valid ? spec_insn_rol_valid : + spec_insn_rolw_valid ? spec_insn_rolw_valid : + spec_insn_ror_valid ? spec_insn_ror_valid : + spec_insn_rori_valid ? spec_insn_rori_valid : + spec_insn_roriw_valid ? spec_insn_roriw_valid : + spec_insn_rorw_valid ? spec_insn_rorw_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sd_valid ? spec_insn_sd_valid : + spec_insn_sext_b_valid ? spec_insn_sext_b_valid : + spec_insn_sext_h_valid ? spec_insn_sext_h_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sh1add_valid ? spec_insn_sh1add_valid : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_valid : @@ -2303,8 +3181,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_subw_valid ? spec_insn_subw_valid : spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xnor_valid ? spec_insn_xnor_valid : spec_insn_xor_valid ? spec_insn_xor_valid : - spec_insn_xori_valid ? spec_insn_xori_valid : 0; + spec_insn_xori_valid ? spec_insn_xori_valid : + spec_insn_zext_h_valid ? spec_insn_zext_h_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_add_uw_valid ? spec_insn_add_uw_trap : @@ -2313,6 +3193,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_andn_valid ? spec_insn_andn_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : @@ -2320,6 +3201,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_clz_valid ? spec_insn_clz_trap : + spec_insn_clzw_valid ? spec_insn_clzw_trap : + spec_insn_cpop_valid ? spec_insn_cpop_trap : + spec_insn_cpopw_valid ? spec_insn_cpopw_trap : + spec_insn_ctz_valid ? spec_insn_ctz_trap : + spec_insn_ctzw_valid ? spec_insn_ctzw_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : @@ -2330,10 +3217,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_lwu_valid ? spec_insn_lwu_trap : + spec_insn_max_valid ? spec_insn_max_trap : + spec_insn_maxu_valid ? spec_insn_maxu_trap : + spec_insn_min_valid ? spec_insn_min_trap : + spec_insn_minu_valid ? spec_insn_minu_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_orn_valid ? spec_insn_orn_trap : + spec_insn_rol_valid ? spec_insn_rol_trap : + spec_insn_rolw_valid ? spec_insn_rolw_trap : + spec_insn_ror_valid ? spec_insn_ror_trap : + spec_insn_rori_valid ? spec_insn_rori_trap : + spec_insn_roriw_valid ? spec_insn_roriw_trap : + spec_insn_rorw_valid ? spec_insn_rorw_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sd_valid ? spec_insn_sd_trap : + spec_insn_sext_b_valid ? spec_insn_sext_b_trap : + spec_insn_sext_h_valid ? spec_insn_sext_h_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sh1add_valid ? spec_insn_sh1add_trap : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_trap : @@ -2361,8 +3261,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_subw_valid ? spec_insn_subw_trap : spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xnor_valid ? spec_insn_xnor_trap : spec_insn_xor_valid ? spec_insn_xor_trap : - spec_insn_xori_valid ? spec_insn_xori_trap : 0; + spec_insn_xori_valid ? spec_insn_xori_trap : + spec_insn_zext_h_valid ? spec_insn_zext_h_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_add_uw_valid ? spec_insn_add_uw_rs1_addr : @@ -2371,6 +3273,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_andn_valid ? spec_insn_andn_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : @@ -2378,6 +3281,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_clz_valid ? spec_insn_clz_rs1_addr : + spec_insn_clzw_valid ? spec_insn_clzw_rs1_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs1_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_rs1_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs1_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : @@ -2388,10 +3297,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : + spec_insn_max_valid ? spec_insn_max_rs1_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs1_addr : + spec_insn_min_valid ? spec_insn_min_rs1_addr : + spec_insn_minu_valid ? spec_insn_minu_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_orn_valid ? spec_insn_orn_rs1_addr : + spec_insn_rol_valid ? spec_insn_rol_rs1_addr : + spec_insn_rolw_valid ? spec_insn_rolw_rs1_addr : + spec_insn_ror_valid ? spec_insn_ror_rs1_addr : + spec_insn_rori_valid ? spec_insn_rori_rs1_addr : + spec_insn_roriw_valid ? spec_insn_roriw_rs1_addr : + spec_insn_rorw_valid ? spec_insn_rorw_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sd_valid ? spec_insn_sd_rs1_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs1_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_rs1_addr : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs1_addr : @@ -2419,8 +3341,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_subw_valid ? spec_insn_subw_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : - spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_add_uw_valid ? spec_insn_add_uw_rs2_addr : @@ -2429,6 +3353,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_andn_valid ? spec_insn_andn_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : @@ -2436,6 +3361,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_clz_valid ? spec_insn_clz_rs2_addr : + spec_insn_clzw_valid ? spec_insn_clzw_rs2_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rs2_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_rs2_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rs2_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : @@ -2446,10 +3377,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : + spec_insn_max_valid ? spec_insn_max_rs2_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rs2_addr : + spec_insn_min_valid ? spec_insn_min_rs2_addr : + spec_insn_minu_valid ? spec_insn_minu_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_orn_valid ? spec_insn_orn_rs2_addr : + spec_insn_rol_valid ? spec_insn_rol_rs2_addr : + spec_insn_rolw_valid ? spec_insn_rolw_rs2_addr : + spec_insn_ror_valid ? spec_insn_ror_rs2_addr : + spec_insn_rori_valid ? spec_insn_rori_rs2_addr : + spec_insn_roriw_valid ? spec_insn_roriw_rs2_addr : + spec_insn_rorw_valid ? spec_insn_rorw_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sd_valid ? spec_insn_sd_rs2_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rs2_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_rs2_addr : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs2_addr : @@ -2477,8 +3421,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_subw_valid ? spec_insn_subw_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : - spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_add_uw_valid ? spec_insn_add_uw_rd_addr : @@ -2487,6 +3433,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_andn_valid ? spec_insn_andn_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : @@ -2494,6 +3441,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_clz_valid ? spec_insn_clz_rd_addr : + spec_insn_clzw_valid ? spec_insn_clzw_rd_addr : + spec_insn_cpop_valid ? spec_insn_cpop_rd_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_rd_addr : + spec_insn_ctz_valid ? spec_insn_ctz_rd_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : @@ -2504,10 +3457,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : + spec_insn_max_valid ? spec_insn_max_rd_addr : + spec_insn_maxu_valid ? spec_insn_maxu_rd_addr : + spec_insn_min_valid ? spec_insn_min_rd_addr : + spec_insn_minu_valid ? spec_insn_minu_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_orn_valid ? spec_insn_orn_rd_addr : + spec_insn_rol_valid ? spec_insn_rol_rd_addr : + spec_insn_rolw_valid ? spec_insn_rolw_rd_addr : + spec_insn_ror_valid ? spec_insn_ror_rd_addr : + spec_insn_rori_valid ? spec_insn_rori_rd_addr : + spec_insn_roriw_valid ? spec_insn_roriw_rd_addr : + spec_insn_rorw_valid ? spec_insn_rorw_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sd_valid ? spec_insn_sd_rd_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_rd_addr : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_addr : @@ -2535,8 +3501,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_subw_valid ? spec_insn_subw_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xnor_valid ? spec_insn_xnor_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : - spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_rd_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_add_uw_valid ? spec_insn_add_uw_rd_wdata : @@ -2545,6 +3513,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_andn_valid ? spec_insn_andn_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : @@ -2552,6 +3521,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_clz_valid ? spec_insn_clz_rd_wdata : + spec_insn_clzw_valid ? spec_insn_clzw_rd_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_rd_wdata : + spec_insn_cpopw_valid ? spec_insn_cpopw_rd_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_rd_wdata : + spec_insn_ctzw_valid ? spec_insn_ctzw_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : @@ -2562,10 +3537,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : + spec_insn_max_valid ? spec_insn_max_rd_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_rd_wdata : + spec_insn_min_valid ? spec_insn_min_rd_wdata : + spec_insn_minu_valid ? spec_insn_minu_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_orn_valid ? spec_insn_orn_rd_wdata : + spec_insn_rol_valid ? spec_insn_rol_rd_wdata : + spec_insn_rolw_valid ? spec_insn_rolw_rd_wdata : + spec_insn_ror_valid ? spec_insn_ror_rd_wdata : + spec_insn_rori_valid ? spec_insn_rori_rd_wdata : + spec_insn_roriw_valid ? spec_insn_roriw_rd_wdata : + spec_insn_rorw_valid ? spec_insn_rorw_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sd_valid ? spec_insn_sd_rd_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_rd_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sh1add_valid ? spec_insn_sh1add_rd_wdata : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_wdata : @@ -2593,8 +3581,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_subw_valid ? spec_insn_subw_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : - spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_add_uw_valid ? spec_insn_add_uw_pc_wdata : @@ -2603,6 +3593,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_andn_valid ? spec_insn_andn_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : @@ -2610,6 +3601,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_clz_valid ? spec_insn_clz_pc_wdata : + spec_insn_clzw_valid ? spec_insn_clzw_pc_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_pc_wdata : + spec_insn_cpopw_valid ? spec_insn_cpopw_pc_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_pc_wdata : + spec_insn_ctzw_valid ? spec_insn_ctzw_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : @@ -2620,10 +3617,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : + spec_insn_max_valid ? spec_insn_max_pc_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_pc_wdata : + spec_insn_min_valid ? spec_insn_min_pc_wdata : + spec_insn_minu_valid ? spec_insn_minu_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_orn_valid ? spec_insn_orn_pc_wdata : + spec_insn_rol_valid ? spec_insn_rol_pc_wdata : + spec_insn_rolw_valid ? spec_insn_rolw_pc_wdata : + spec_insn_ror_valid ? spec_insn_ror_pc_wdata : + spec_insn_rori_valid ? spec_insn_rori_pc_wdata : + spec_insn_roriw_valid ? spec_insn_roriw_pc_wdata : + spec_insn_rorw_valid ? spec_insn_rorw_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sd_valid ? spec_insn_sd_pc_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_pc_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sh1add_valid ? spec_insn_sh1add_pc_wdata : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_pc_wdata : @@ -2651,8 +3661,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_subw_valid ? spec_insn_subw_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : - spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_add_uw_valid ? spec_insn_add_uw_mem_addr : @@ -2661,6 +3673,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_andn_valid ? spec_insn_andn_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : @@ -2668,6 +3681,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_clz_valid ? spec_insn_clz_mem_addr : + spec_insn_clzw_valid ? spec_insn_clzw_mem_addr : + spec_insn_cpop_valid ? spec_insn_cpop_mem_addr : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_addr : + spec_insn_ctz_valid ? spec_insn_ctz_mem_addr : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : @@ -2678,10 +3697,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : + spec_insn_max_valid ? spec_insn_max_mem_addr : + spec_insn_maxu_valid ? spec_insn_maxu_mem_addr : + spec_insn_min_valid ? spec_insn_min_mem_addr : + spec_insn_minu_valid ? spec_insn_minu_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_orn_valid ? spec_insn_orn_mem_addr : + spec_insn_rol_valid ? spec_insn_rol_mem_addr : + spec_insn_rolw_valid ? spec_insn_rolw_mem_addr : + spec_insn_ror_valid ? spec_insn_ror_mem_addr : + spec_insn_rori_valid ? spec_insn_rori_mem_addr : + spec_insn_roriw_valid ? spec_insn_roriw_mem_addr : + spec_insn_rorw_valid ? spec_insn_rorw_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sd_valid ? spec_insn_sd_mem_addr : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_addr : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_addr : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_addr : @@ -2709,8 +3741,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_subw_valid ? spec_insn_subw_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xnor_valid ? spec_insn_xnor_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : - spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_addr : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_add_uw_valid ? spec_insn_add_uw_mem_rmask : @@ -2719,6 +3753,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_andn_valid ? spec_insn_andn_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : @@ -2726,6 +3761,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_clz_valid ? spec_insn_clz_mem_rmask : + spec_insn_clzw_valid ? spec_insn_clzw_mem_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_rmask : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_rmask : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : @@ -2736,10 +3777,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : + spec_insn_max_valid ? spec_insn_max_mem_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_rmask : + spec_insn_min_valid ? spec_insn_min_mem_rmask : + spec_insn_minu_valid ? spec_insn_minu_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_orn_valid ? spec_insn_orn_mem_rmask : + spec_insn_rol_valid ? spec_insn_rol_mem_rmask : + spec_insn_rolw_valid ? spec_insn_rolw_mem_rmask : + spec_insn_ror_valid ? spec_insn_ror_mem_rmask : + spec_insn_rori_valid ? spec_insn_rori_mem_rmask : + spec_insn_roriw_valid ? spec_insn_roriw_mem_rmask : + spec_insn_rorw_valid ? spec_insn_rorw_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sd_valid ? spec_insn_sd_mem_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_rmask : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_rmask : @@ -2767,8 +3821,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_subw_valid ? spec_insn_subw_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : - spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wmask : @@ -2777,6 +3833,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_andn_valid ? spec_insn_andn_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : @@ -2784,6 +3841,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_clz_valid ? spec_insn_clz_mem_wmask : + spec_insn_clzw_valid ? spec_insn_clzw_mem_wmask : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wmask : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_wmask : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wmask : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : @@ -2794,10 +3857,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : + spec_insn_max_valid ? spec_insn_max_mem_wmask : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wmask : + spec_insn_min_valid ? spec_insn_min_mem_wmask : + spec_insn_minu_valid ? spec_insn_minu_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_orn_valid ? spec_insn_orn_mem_wmask : + spec_insn_rol_valid ? spec_insn_rol_mem_wmask : + spec_insn_rolw_valid ? spec_insn_rolw_mem_wmask : + spec_insn_ror_valid ? spec_insn_ror_mem_wmask : + spec_insn_rori_valid ? spec_insn_rori_mem_wmask : + spec_insn_roriw_valid ? spec_insn_roriw_mem_wmask : + spec_insn_rorw_valid ? spec_insn_rorw_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sd_valid ? spec_insn_sd_mem_wmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wmask : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wmask : @@ -2825,8 +3901,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_subw_valid ? spec_insn_subw_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : - spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wdata : @@ -2835,6 +3913,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_andn_valid ? spec_insn_andn_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : @@ -2842,6 +3921,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_clz_valid ? spec_insn_clz_mem_wdata : + spec_insn_clzw_valid ? spec_insn_clzw_mem_wdata : + spec_insn_cpop_valid ? spec_insn_cpop_mem_wdata : + spec_insn_cpopw_valid ? spec_insn_cpopw_mem_wdata : + spec_insn_ctz_valid ? spec_insn_ctz_mem_wdata : + spec_insn_ctzw_valid ? spec_insn_ctzw_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : @@ -2852,10 +3937,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : + spec_insn_max_valid ? spec_insn_max_mem_wdata : + spec_insn_maxu_valid ? spec_insn_maxu_mem_wdata : + spec_insn_min_valid ? spec_insn_min_mem_wdata : + spec_insn_minu_valid ? spec_insn_minu_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_orn_valid ? spec_insn_orn_mem_wdata : + spec_insn_rol_valid ? spec_insn_rol_mem_wdata : + spec_insn_rolw_valid ? spec_insn_rolw_mem_wdata : + spec_insn_ror_valid ? spec_insn_ror_mem_wdata : + spec_insn_rori_valid ? spec_insn_rori_mem_wdata : + spec_insn_roriw_valid ? spec_insn_roriw_mem_wdata : + spec_insn_rorw_valid ? spec_insn_rorw_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sd_valid ? spec_insn_sd_mem_wdata : + spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wdata : + spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wdata : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wdata : @@ -2883,8 +3981,10 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_subw_valid ? spec_insn_subw_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xnor_valid ? spec_insn_xnor_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : - spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : + spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : @@ -2894,6 +3994,7 @@ module rvfi_isa_rv64ib ( spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_andn_valid ? spec_insn_andn_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : @@ -2901,6 +4002,12 @@ module rvfi_isa_rv64ib ( spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_clz_valid ? spec_insn_clz_csr_misa_rmask : + spec_insn_clzw_valid ? spec_insn_clzw_csr_misa_rmask : + spec_insn_cpop_valid ? spec_insn_cpop_csr_misa_rmask : + spec_insn_cpopw_valid ? spec_insn_cpopw_csr_misa_rmask : + spec_insn_ctz_valid ? spec_insn_ctz_csr_misa_rmask : + spec_insn_ctzw_valid ? spec_insn_ctzw_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : @@ -2911,10 +4018,23 @@ module rvfi_isa_rv64ib ( spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : + spec_insn_max_valid ? spec_insn_max_csr_misa_rmask : + spec_insn_maxu_valid ? spec_insn_maxu_csr_misa_rmask : + spec_insn_min_valid ? spec_insn_min_csr_misa_rmask : + spec_insn_minu_valid ? spec_insn_minu_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_orn_valid ? spec_insn_orn_csr_misa_rmask : + spec_insn_rol_valid ? spec_insn_rol_csr_misa_rmask : + spec_insn_rolw_valid ? spec_insn_rolw_csr_misa_rmask : + spec_insn_ror_valid ? spec_insn_ror_csr_misa_rmask : + spec_insn_rori_valid ? spec_insn_rori_csr_misa_rmask : + spec_insn_roriw_valid ? spec_insn_roriw_csr_misa_rmask : + spec_insn_rorw_valid ? spec_insn_rorw_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : + spec_insn_sext_b_valid ? spec_insn_sext_b_csr_misa_rmask : + spec_insn_sext_h_valid ? spec_insn_sext_h_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sh1add_valid ? spec_insn_sh1add_csr_misa_rmask : spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_csr_misa_rmask : @@ -2942,7 +4062,9 @@ module rvfi_isa_rv64ib ( spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xnor_valid ? spec_insn_xnor_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : - spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : + spec_insn_zext_h_valid ? spec_insn_zext_h_csr_misa_rmask : 0; `endif endmodule From 85096dccae27a5e18b85dff9b35b01fcbac50fa2 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 3 Oct 2024 12:32:13 +1300 Subject: [PATCH 03/11] Zbs - Add bitwise variation on R-type instruction format. - Add `insn_bit` function for bitwise functions in Zbs extension. - Add Zbs instructions. --- insns/generate.py | 49 +- insns/insn_bclr.v | 61 + insns/insn_bclri.v | 61 + insns/insn_bext.v | 61 + insns/insn_bexti.v | 61 + insns/insn_binv.v | 61 + insns/insn_binvi.v | 61 + insns/insn_bset.v | 61 + insns/insn_bseti.v | 61 + insns/isa_rv32iZbs.txt | 45 + insns/isa_rv32iZbs.v | 2336 +++++++++++++++++++++++++++++++ insns/isa_rv32ib.txt | 8 + insns/isa_rv32ib.v | 408 ++++++ insns/isa_rv64iZbs.txt | 57 + insns/isa_rv64iZbs.v | 2948 ++++++++++++++++++++++++++++++++++++++++ insns/isa_rv64ib.txt | 8 + insns/isa_rv64ib.v | 408 ++++++ 17 files changed, 6754 insertions(+), 1 deletion(-) create mode 100644 insns/insn_bclr.v create mode 100644 insns/insn_bclri.v create mode 100644 insns/insn_bext.v create mode 100644 insns/insn_bexti.v create mode 100644 insns/insn_binv.v create mode 100644 insns/insn_binvi.v create mode 100644 insns/insn_bset.v create mode 100644 insns/insn_bseti.v create mode 100644 insns/isa_rv32iZbs.txt create mode 100644 insns/isa_rv32iZbs.v create mode 100644 insns/isa_rv64iZbs.txt create mode 100644 insns/isa_rv64iZbs.v diff --git a/insns/generate.py b/insns/generate.py index f932cb98..122b34ca 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -174,6 +174,18 @@ def format_ra(f): print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) +def format_rb(f): + print("", file=f) + print(" // R-type instruction format (bitwise variation)", file=f) + print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) + print(" wire [6:0] insn_funct7 = rvfi_insn[31:25];", file=f) + print(" wire [5:0] insn_shamt = rvfi_insn[25:20];", file=f) + print(" wire [4:0] insn_rs2 = rvfi_insn[24:20];", file=f) + print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) + print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) + print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) + print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) + def format_i(f): print("", file=f) print(" // I-type instruction format", file=f) @@ -1213,6 +1225,34 @@ def insn_ext(insn, funct5, signed=False, bmode=False, misa=MISA_B): footer(f) +def insn_bit(insn, funct6, funct3, expr, imode=False, misa=MISA_B): + with open("insn_%s.v" % insn, "w") as f: + header(f, insn) + format_rb(f) + misa_check(f, misa) + + if imode: + opcode = "0010011" + xtra_shamt_check = "(!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)" + index = "shamt & (`RISCV_FORMAL_XLEN - 1)" + else: + opcode = "0110011" + xtra_shamt_check = "1" + index = "rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1)" + + print("", file=f) + print(" // %s instruction" % insn.upper(), file=f) + print(" wire [`RISCV_FORMAL_XLEN-1:0] index = %s;" % index, file=f) + print(" wire [`RISCV_FORMAL_XLEN-1:0] result = %s;" % expr, file=f) + assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct6 == 6'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s && %s" % (funct6, funct3, opcode, xtra_shamt_check)) + assign(f, "spec_rs1_addr", "insn_rs1") + assign(f, "spec_rs2_addr", "insn_rs2") + assign(f, "spec_rd_addr", "insn_rd") + assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") + assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") + + footer(f) + ## Base Integer ISA (I) current_isa = ["rv32i"] @@ -1405,7 +1445,14 @@ def insn_ext(insn, funct5, signed=False, bmode=False, misa=MISA_B): current_isa = ["rv32iZbs"] -current_isa = ["rv64iZbs"] +insn_bit("bclr", "0100100", "001", "rvfi_rs1_rdata & ~(1 << index)", misa=MISA_B) +insn_bit("bclri", "0100100", "001", "rvfi_rs1_rdata & ~(1 << index)", imode=True, misa=MISA_B) +insn_bit("bext", "0100100", "101", "(rvfi_rs1_rdata >> index) & 1", misa=MISA_B) +insn_bit("bexti", "0100100", "101", "(rvfi_rs1_rdata >> index) & 1", imode=True, misa=MISA_B) +insn_bit("binv", "0110100", "001", "rvfi_rs1_rdata ^ (1 << index)", misa=MISA_B) +insn_bit("binvi", "0110100", "001", "rvfi_rs1_rdata ^ (1 << index)", imode=True, misa=MISA_B) +insn_bit("bset", "0010100", "001", "rvfi_rs1_rdata | (1 << index)", misa=MISA_B) +insn_bit("bseti", "0010100", "001", "rvfi_rs1_rdata | (1 << index)", imode=True, misa=MISA_B) ## Compressed Integer ISA (IC) diff --git a/insns/insn_bclr.v b/insns/insn_bclr.v new file mode 100644 index 00000000..4a8f3f46 --- /dev/null +++ b/insns/insn_bclr.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_bclr ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BCLR instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & ~(1 << index); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && 1; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_bclri.v b/insns/insn_bclri.v new file mode 100644 index 00000000..75fe5a9c --- /dev/null +++ b/insns/insn_bclri.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_bclri ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BCLRI instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & ~(1 << index); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_bext.v b/insns/insn_bext.v new file mode 100644 index 00000000..6dcbd338 --- /dev/null +++ b/insns/insn_bext.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_bext ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BEXT instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> index) & 1; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011 && 1; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_bexti.v b/insns/insn_bexti.v new file mode 100644 index 00000000..fd7cb697 --- /dev/null +++ b/insns/insn_bexti.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_bexti ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BEXTI instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> index) & 1; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_binv.v b/insns/insn_binv.v new file mode 100644 index 00000000..937fdcbe --- /dev/null +++ b/insns/insn_binv.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_binv ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BINV instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ (1 << index); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && 1; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_binvi.v b/insns/insn_binvi.v new file mode 100644 index 00000000..a0bc75d4 --- /dev/null +++ b/insns/insn_binvi.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_binvi ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BINVI instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ (1 << index); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_bset.v b/insns/insn_bset.v new file mode 100644 index 00000000..40deb19d --- /dev/null +++ b/insns/insn_bset.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_bset ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BSET instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | (1 << index); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0010100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && 1; + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/insn_bseti.v b/insns/insn_bseti.v new file mode 100644 index 00000000..08a16c56 --- /dev/null +++ b/insns/insn_bseti.v @@ -0,0 +1,61 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_bseti ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // R-type instruction format (bitwise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [5:0] insn_shamt = rvfi_insn[25:20]; + wire [4:0] insn_rs2 = rvfi_insn[24:20]; + wire [4:0] insn_rs1 = rvfi_insn[19:15]; + wire [2:0] insn_funct3 = rvfi_insn[14:12]; + wire [4:0] insn_rd = rvfi_insn[11: 7]; + wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // BSETI instruction + wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | (1 << index); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0010100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_rs1_addr = insn_rs1; + assign spec_rs2_addr = insn_rs2; + assign spec_rd_addr = insn_rd; + assign spec_rd_wdata = spec_rd_addr ? result : 0; + assign spec_pc_wdata = rvfi_pc_rdata + 4; + + // default assignments + assign spec_trap = !misa_ok; + assign spec_mem_addr = 0; + assign spec_mem_rmask = 0; + assign spec_mem_wmask = 0; + assign spec_mem_wdata = 0; +endmodule diff --git a/insns/isa_rv32iZbs.txt b/insns/isa_rv32iZbs.txt new file mode 100644 index 00000000..b96909b9 --- /dev/null +++ b/insns/isa_rv32iZbs.txt @@ -0,0 +1,45 @@ +add +addi +and +andi +auipc +bclr +bclri +beq +bext +bexti +bge +bgeu +binv +binvi +blt +bltu +bne +bset +bseti +jal +jalr +lb +lbu +lh +lhu +lui +lw +or +ori +sb +sh +sll +slli +slt +slti +sltiu +sltu +sra +srai +srl +srli +sub +sw +xor +xori diff --git a/insns/isa_rv32iZbs.v b/insns/isa_rv32iZbs.v new file mode 100644 index 00000000..bde8f09e --- /dev/null +++ b/insns/isa_rv32iZbs.v @@ -0,0 +1,2336 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv32iZbs ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_bclr_valid; + wire spec_insn_bclr_trap; + wire [ 4 : 0] spec_insn_bclr_rs1_addr; + wire [ 4 : 0] spec_insn_bclr_rs2_addr; + wire [ 4 : 0] spec_insn_bclr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_csr_misa_rmask; +`endif + + rvfi_insn_bclr insn_bclr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclr_valid), + .spec_trap(spec_insn_bclr_trap), + .spec_rs1_addr(spec_insn_bclr_rs1_addr), + .spec_rs2_addr(spec_insn_bclr_rs2_addr), + .spec_rd_addr(spec_insn_bclr_rd_addr), + .spec_rd_wdata(spec_insn_bclr_rd_wdata), + .spec_pc_wdata(spec_insn_bclr_pc_wdata), + .spec_mem_addr(spec_insn_bclr_mem_addr), + .spec_mem_rmask(spec_insn_bclr_mem_rmask), + .spec_mem_wmask(spec_insn_bclr_mem_wmask), + .spec_mem_wdata(spec_insn_bclr_mem_wdata) + ); + + wire spec_insn_bclri_valid; + wire spec_insn_bclri_trap; + wire [ 4 : 0] spec_insn_bclri_rs1_addr; + wire [ 4 : 0] spec_insn_bclri_rs2_addr; + wire [ 4 : 0] spec_insn_bclri_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_csr_misa_rmask; +`endif + + rvfi_insn_bclri insn_bclri ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclri_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclri_valid), + .spec_trap(spec_insn_bclri_trap), + .spec_rs1_addr(spec_insn_bclri_rs1_addr), + .spec_rs2_addr(spec_insn_bclri_rs2_addr), + .spec_rd_addr(spec_insn_bclri_rd_addr), + .spec_rd_wdata(spec_insn_bclri_rd_wdata), + .spec_pc_wdata(spec_insn_bclri_pc_wdata), + .spec_mem_addr(spec_insn_bclri_mem_addr), + .spec_mem_rmask(spec_insn_bclri_mem_rmask), + .spec_mem_wmask(spec_insn_bclri_mem_wmask), + .spec_mem_wdata(spec_insn_bclri_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bext_valid; + wire spec_insn_bext_trap; + wire [ 4 : 0] spec_insn_bext_rs1_addr; + wire [ 4 : 0] spec_insn_bext_rs2_addr; + wire [ 4 : 0] spec_insn_bext_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_csr_misa_rmask; +`endif + + rvfi_insn_bext insn_bext ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bext_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bext_valid), + .spec_trap(spec_insn_bext_trap), + .spec_rs1_addr(spec_insn_bext_rs1_addr), + .spec_rs2_addr(spec_insn_bext_rs2_addr), + .spec_rd_addr(spec_insn_bext_rd_addr), + .spec_rd_wdata(spec_insn_bext_rd_wdata), + .spec_pc_wdata(spec_insn_bext_pc_wdata), + .spec_mem_addr(spec_insn_bext_mem_addr), + .spec_mem_rmask(spec_insn_bext_mem_rmask), + .spec_mem_wmask(spec_insn_bext_mem_wmask), + .spec_mem_wdata(spec_insn_bext_mem_wdata) + ); + + wire spec_insn_bexti_valid; + wire spec_insn_bexti_trap; + wire [ 4 : 0] spec_insn_bexti_rs1_addr; + wire [ 4 : 0] spec_insn_bexti_rs2_addr; + wire [ 4 : 0] spec_insn_bexti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_csr_misa_rmask; +`endif + + rvfi_insn_bexti insn_bexti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bexti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bexti_valid), + .spec_trap(spec_insn_bexti_trap), + .spec_rs1_addr(spec_insn_bexti_rs1_addr), + .spec_rs2_addr(spec_insn_bexti_rs2_addr), + .spec_rd_addr(spec_insn_bexti_rd_addr), + .spec_rd_wdata(spec_insn_bexti_rd_wdata), + .spec_pc_wdata(spec_insn_bexti_pc_wdata), + .spec_mem_addr(spec_insn_bexti_mem_addr), + .spec_mem_rmask(spec_insn_bexti_mem_rmask), + .spec_mem_wmask(spec_insn_bexti_mem_wmask), + .spec_mem_wdata(spec_insn_bexti_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_binv_valid; + wire spec_insn_binv_trap; + wire [ 4 : 0] spec_insn_binv_rs1_addr; + wire [ 4 : 0] spec_insn_binv_rs2_addr; + wire [ 4 : 0] spec_insn_binv_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_csr_misa_rmask; +`endif + + rvfi_insn_binv insn_binv ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binv_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binv_valid), + .spec_trap(spec_insn_binv_trap), + .spec_rs1_addr(spec_insn_binv_rs1_addr), + .spec_rs2_addr(spec_insn_binv_rs2_addr), + .spec_rd_addr(spec_insn_binv_rd_addr), + .spec_rd_wdata(spec_insn_binv_rd_wdata), + .spec_pc_wdata(spec_insn_binv_pc_wdata), + .spec_mem_addr(spec_insn_binv_mem_addr), + .spec_mem_rmask(spec_insn_binv_mem_rmask), + .spec_mem_wmask(spec_insn_binv_mem_wmask), + .spec_mem_wdata(spec_insn_binv_mem_wdata) + ); + + wire spec_insn_binvi_valid; + wire spec_insn_binvi_trap; + wire [ 4 : 0] spec_insn_binvi_rs1_addr; + wire [ 4 : 0] spec_insn_binvi_rs2_addr; + wire [ 4 : 0] spec_insn_binvi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_csr_misa_rmask; +`endif + + rvfi_insn_binvi insn_binvi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binvi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binvi_valid), + .spec_trap(spec_insn_binvi_trap), + .spec_rs1_addr(spec_insn_binvi_rs1_addr), + .spec_rs2_addr(spec_insn_binvi_rs2_addr), + .spec_rd_addr(spec_insn_binvi_rd_addr), + .spec_rd_wdata(spec_insn_binvi_rd_wdata), + .spec_pc_wdata(spec_insn_binvi_pc_wdata), + .spec_mem_addr(spec_insn_binvi_mem_addr), + .spec_mem_rmask(spec_insn_binvi_mem_rmask), + .spec_mem_wmask(spec_insn_binvi_mem_wmask), + .spec_mem_wdata(spec_insn_binvi_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_bset_valid; + wire spec_insn_bset_trap; + wire [ 4 : 0] spec_insn_bset_rs1_addr; + wire [ 4 : 0] spec_insn_bset_rs2_addr; + wire [ 4 : 0] spec_insn_bset_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_csr_misa_rmask; +`endif + + rvfi_insn_bset insn_bset ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bset_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bset_valid), + .spec_trap(spec_insn_bset_trap), + .spec_rs1_addr(spec_insn_bset_rs1_addr), + .spec_rs2_addr(spec_insn_bset_rs2_addr), + .spec_rd_addr(spec_insn_bset_rd_addr), + .spec_rd_wdata(spec_insn_bset_rd_wdata), + .spec_pc_wdata(spec_insn_bset_pc_wdata), + .spec_mem_addr(spec_insn_bset_mem_addr), + .spec_mem_rmask(spec_insn_bset_mem_rmask), + .spec_mem_wmask(spec_insn_bset_mem_wmask), + .spec_mem_wdata(spec_insn_bset_mem_wdata) + ); + + wire spec_insn_bseti_valid; + wire spec_insn_bseti_trap; + wire [ 4 : 0] spec_insn_bseti_rs1_addr; + wire [ 4 : 0] spec_insn_bseti_rs2_addr; + wire [ 4 : 0] spec_insn_bseti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_csr_misa_rmask; +`endif + + rvfi_insn_bseti insn_bseti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bseti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bseti_valid), + .spec_trap(spec_insn_bseti_trap), + .spec_rs1_addr(spec_insn_bseti_rs1_addr), + .spec_rs2_addr(spec_insn_bseti_rs2_addr), + .spec_rd_addr(spec_insn_bseti_rd_addr), + .spec_rd_wdata(spec_insn_bseti_rd_wdata), + .spec_pc_wdata(spec_insn_bseti_pc_wdata), + .spec_mem_addr(spec_insn_bseti_mem_addr), + .spec_mem_rmask(spec_insn_bseti_mem_rmask), + .spec_mem_wmask(spec_insn_bseti_mem_wmask), + .spec_mem_wdata(spec_insn_bseti_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_bclr_valid ? spec_insn_bclr_valid : + spec_insn_bclri_valid ? spec_insn_bclri_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bext_valid ? spec_insn_bext_valid : + spec_insn_bexti_valid ? spec_insn_bexti_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_binv_valid ? spec_insn_binv_valid : + spec_insn_binvi_valid ? spec_insn_binvi_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_bset_valid ? spec_insn_bset_valid : + spec_insn_bseti_valid ? spec_insn_bseti_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_bclr_valid ? spec_insn_bclr_trap : + spec_insn_bclri_valid ? spec_insn_bclri_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bext_valid ? spec_insn_bext_trap : + spec_insn_bexti_valid ? spec_insn_bexti_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_binv_valid ? spec_insn_binv_trap : + spec_insn_binvi_valid ? spec_insn_binvi_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_bset_valid ? spec_insn_bset_trap : + spec_insn_bseti_valid ? spec_insn_bseti_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs1_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bext_valid ? spec_insn_bext_rs1_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_binv_valid ? spec_insn_binv_rs1_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_bset_valid ? spec_insn_bset_rs1_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs2_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bext_valid ? spec_insn_bext_rs2_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_binv_valid ? spec_insn_binv_rs2_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_bset_valid ? spec_insn_bset_rs2_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rd_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bext_valid ? spec_insn_bext_rd_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_binv_valid ? spec_insn_binv_rd_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_bset_valid ? spec_insn_bset_rd_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_rd_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bext_valid ? spec_insn_bext_rd_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_binv_valid ? spec_insn_binv_rd_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_bset_valid ? spec_insn_bset_rd_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_pc_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bext_valid ? spec_insn_bext_pc_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_binv_valid ? spec_insn_binv_pc_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_bset_valid ? spec_insn_bset_pc_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_bclr_valid ? spec_insn_bclr_mem_addr : + spec_insn_bclri_valid ? spec_insn_bclri_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bext_valid ? spec_insn_bext_mem_addr : + spec_insn_bexti_valid ? spec_insn_bexti_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_binv_valid ? spec_insn_binv_mem_addr : + spec_insn_binvi_valid ? spec_insn_binvi_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_bset_valid ? spec_insn_bset_mem_addr : + spec_insn_bseti_valid ? spec_insn_bseti_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bext_valid ? spec_insn_bext_mem_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_binv_valid ? spec_insn_binv_mem_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_bset_valid ? spec_insn_bset_mem_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bext_valid ? spec_insn_bext_mem_wmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_binv_valid ? spec_insn_binv_mem_wmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_bset_valid ? spec_insn_bset_mem_wmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bext_valid ? spec_insn_bext_mem_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_binv_valid ? spec_insn_binv_mem_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_bset_valid ? spec_insn_bset_mem_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_csr_misa_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bext_valid ? spec_insn_bext_csr_misa_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_binv_valid ? spec_insn_binv_csr_misa_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_bset_valid ? spec_insn_bset_csr_misa_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; +`endif +endmodule diff --git a/insns/isa_rv32ib.txt b/insns/isa_rv32ib.txt index b6b76eac..0898ceff 100644 --- a/insns/isa_rv32ib.txt +++ b/insns/isa_rv32ib.txt @@ -4,12 +4,20 @@ and andi andn auipc +bclr +bclri beq +bext +bexti bge bgeu +binv +binvi blt bltu bne +bset +bseti clz cpop ctz diff --git a/insns/isa_rv32ib.v b/insns/isa_rv32ib.v index 975f0e74..7389ad6a 100644 --- a/insns/isa_rv32ib.v +++ b/insns/isa_rv32ib.v @@ -258,6 +258,84 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); + wire spec_insn_bclr_valid; + wire spec_insn_bclr_trap; + wire [ 4 : 0] spec_insn_bclr_rs1_addr; + wire [ 4 : 0] spec_insn_bclr_rs2_addr; + wire [ 4 : 0] spec_insn_bclr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_csr_misa_rmask; +`endif + + rvfi_insn_bclr insn_bclr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclr_valid), + .spec_trap(spec_insn_bclr_trap), + .spec_rs1_addr(spec_insn_bclr_rs1_addr), + .spec_rs2_addr(spec_insn_bclr_rs2_addr), + .spec_rd_addr(spec_insn_bclr_rd_addr), + .spec_rd_wdata(spec_insn_bclr_rd_wdata), + .spec_pc_wdata(spec_insn_bclr_pc_wdata), + .spec_mem_addr(spec_insn_bclr_mem_addr), + .spec_mem_rmask(spec_insn_bclr_mem_rmask), + .spec_mem_wmask(spec_insn_bclr_mem_wmask), + .spec_mem_wdata(spec_insn_bclr_mem_wdata) + ); + + wire spec_insn_bclri_valid; + wire spec_insn_bclri_trap; + wire [ 4 : 0] spec_insn_bclri_rs1_addr; + wire [ 4 : 0] spec_insn_bclri_rs2_addr; + wire [ 4 : 0] spec_insn_bclri_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_csr_misa_rmask; +`endif + + rvfi_insn_bclri insn_bclri ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclri_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclri_valid), + .spec_trap(spec_insn_bclri_trap), + .spec_rs1_addr(spec_insn_bclri_rs1_addr), + .spec_rs2_addr(spec_insn_bclri_rs2_addr), + .spec_rd_addr(spec_insn_bclri_rd_addr), + .spec_rd_wdata(spec_insn_bclri_rd_wdata), + .spec_pc_wdata(spec_insn_bclri_pc_wdata), + .spec_mem_addr(spec_insn_bclri_mem_addr), + .spec_mem_rmask(spec_insn_bclri_mem_rmask), + .spec_mem_wmask(spec_insn_bclri_mem_wmask), + .spec_mem_wdata(spec_insn_bclri_mem_wdata) + ); + wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; @@ -297,6 +375,84 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_beq_mem_wdata) ); + wire spec_insn_bext_valid; + wire spec_insn_bext_trap; + wire [ 4 : 0] spec_insn_bext_rs1_addr; + wire [ 4 : 0] spec_insn_bext_rs2_addr; + wire [ 4 : 0] spec_insn_bext_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_csr_misa_rmask; +`endif + + rvfi_insn_bext insn_bext ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bext_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bext_valid), + .spec_trap(spec_insn_bext_trap), + .spec_rs1_addr(spec_insn_bext_rs1_addr), + .spec_rs2_addr(spec_insn_bext_rs2_addr), + .spec_rd_addr(spec_insn_bext_rd_addr), + .spec_rd_wdata(spec_insn_bext_rd_wdata), + .spec_pc_wdata(spec_insn_bext_pc_wdata), + .spec_mem_addr(spec_insn_bext_mem_addr), + .spec_mem_rmask(spec_insn_bext_mem_rmask), + .spec_mem_wmask(spec_insn_bext_mem_wmask), + .spec_mem_wdata(spec_insn_bext_mem_wdata) + ); + + wire spec_insn_bexti_valid; + wire spec_insn_bexti_trap; + wire [ 4 : 0] spec_insn_bexti_rs1_addr; + wire [ 4 : 0] spec_insn_bexti_rs2_addr; + wire [ 4 : 0] spec_insn_bexti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_csr_misa_rmask; +`endif + + rvfi_insn_bexti insn_bexti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bexti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bexti_valid), + .spec_trap(spec_insn_bexti_trap), + .spec_rs1_addr(spec_insn_bexti_rs1_addr), + .spec_rs2_addr(spec_insn_bexti_rs2_addr), + .spec_rd_addr(spec_insn_bexti_rd_addr), + .spec_rd_wdata(spec_insn_bexti_rd_wdata), + .spec_pc_wdata(spec_insn_bexti_pc_wdata), + .spec_mem_addr(spec_insn_bexti_mem_addr), + .spec_mem_rmask(spec_insn_bexti_mem_rmask), + .spec_mem_wmask(spec_insn_bexti_mem_wmask), + .spec_mem_wdata(spec_insn_bexti_mem_wdata) + ); + wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; @@ -375,6 +531,84 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); + wire spec_insn_binv_valid; + wire spec_insn_binv_trap; + wire [ 4 : 0] spec_insn_binv_rs1_addr; + wire [ 4 : 0] spec_insn_binv_rs2_addr; + wire [ 4 : 0] spec_insn_binv_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_csr_misa_rmask; +`endif + + rvfi_insn_binv insn_binv ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binv_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binv_valid), + .spec_trap(spec_insn_binv_trap), + .spec_rs1_addr(spec_insn_binv_rs1_addr), + .spec_rs2_addr(spec_insn_binv_rs2_addr), + .spec_rd_addr(spec_insn_binv_rd_addr), + .spec_rd_wdata(spec_insn_binv_rd_wdata), + .spec_pc_wdata(spec_insn_binv_pc_wdata), + .spec_mem_addr(spec_insn_binv_mem_addr), + .spec_mem_rmask(spec_insn_binv_mem_rmask), + .spec_mem_wmask(spec_insn_binv_mem_wmask), + .spec_mem_wdata(spec_insn_binv_mem_wdata) + ); + + wire spec_insn_binvi_valid; + wire spec_insn_binvi_trap; + wire [ 4 : 0] spec_insn_binvi_rs1_addr; + wire [ 4 : 0] spec_insn_binvi_rs2_addr; + wire [ 4 : 0] spec_insn_binvi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_csr_misa_rmask; +`endif + + rvfi_insn_binvi insn_binvi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binvi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binvi_valid), + .spec_trap(spec_insn_binvi_trap), + .spec_rs1_addr(spec_insn_binvi_rs1_addr), + .spec_rs2_addr(spec_insn_binvi_rs2_addr), + .spec_rd_addr(spec_insn_binvi_rd_addr), + .spec_rd_wdata(spec_insn_binvi_rd_wdata), + .spec_pc_wdata(spec_insn_binvi_pc_wdata), + .spec_mem_addr(spec_insn_binvi_mem_addr), + .spec_mem_rmask(spec_insn_binvi_mem_rmask), + .spec_mem_wmask(spec_insn_binvi_mem_wmask), + .spec_mem_wdata(spec_insn_binvi_mem_wdata) + ); + wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; @@ -492,6 +726,84 @@ module rvfi_isa_rv32ib ( .spec_mem_wdata(spec_insn_bne_mem_wdata) ); + wire spec_insn_bset_valid; + wire spec_insn_bset_trap; + wire [ 4 : 0] spec_insn_bset_rs1_addr; + wire [ 4 : 0] spec_insn_bset_rs2_addr; + wire [ 4 : 0] spec_insn_bset_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_csr_misa_rmask; +`endif + + rvfi_insn_bset insn_bset ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bset_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bset_valid), + .spec_trap(spec_insn_bset_trap), + .spec_rs1_addr(spec_insn_bset_rs1_addr), + .spec_rs2_addr(spec_insn_bset_rs2_addr), + .spec_rd_addr(spec_insn_bset_rd_addr), + .spec_rd_wdata(spec_insn_bset_rd_wdata), + .spec_pc_wdata(spec_insn_bset_pc_wdata), + .spec_mem_addr(spec_insn_bset_mem_addr), + .spec_mem_rmask(spec_insn_bset_mem_rmask), + .spec_mem_wmask(spec_insn_bset_mem_wmask), + .spec_mem_wdata(spec_insn_bset_mem_wdata) + ); + + wire spec_insn_bseti_valid; + wire spec_insn_bseti_trap; + wire [ 4 : 0] spec_insn_bseti_rs1_addr; + wire [ 4 : 0] spec_insn_bseti_rs2_addr; + wire [ 4 : 0] spec_insn_bseti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_csr_misa_rmask; +`endif + + rvfi_insn_bseti insn_bseti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bseti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bseti_valid), + .spec_trap(spec_insn_bseti_trap), + .spec_rs1_addr(spec_insn_bseti_rs1_addr), + .spec_rs2_addr(spec_insn_bseti_rs2_addr), + .spec_rd_addr(spec_insn_bseti_rd_addr), + .spec_rd_wdata(spec_insn_bseti_rd_wdata), + .spec_pc_wdata(spec_insn_bseti_pc_wdata), + .spec_mem_addr(spec_insn_bseti_mem_addr), + .spec_mem_rmask(spec_insn_bseti_mem_rmask), + .spec_mem_wmask(spec_insn_bseti_mem_wmask), + .spec_mem_wdata(spec_insn_bseti_mem_wdata) + ); + wire spec_insn_clz_valid; wire spec_insn_clz_trap; wire [ 4 : 0] spec_insn_clz_rs1_addr; @@ -2215,12 +2527,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_andn_valid ? spec_insn_andn_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_bclr_valid ? spec_insn_bclr_valid : + spec_insn_bclri_valid ? spec_insn_bclri_valid : spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bext_valid ? spec_insn_bext_valid : + spec_insn_bexti_valid ? spec_insn_bexti_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_binv_valid ? spec_insn_binv_valid : + spec_insn_binvi_valid ? spec_insn_binvi_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_bset_valid ? spec_insn_bset_valid : + spec_insn_bseti_valid ? spec_insn_bseti_valid : spec_insn_clz_valid ? spec_insn_clz_valid : spec_insn_cpop_valid ? spec_insn_cpop_valid : spec_insn_ctz_valid ? spec_insn_ctz_valid : @@ -2272,12 +2592,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_andn_valid ? spec_insn_andn_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_bclr_valid ? spec_insn_bclr_trap : + spec_insn_bclri_valid ? spec_insn_bclri_trap : spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bext_valid ? spec_insn_bext_trap : + spec_insn_bexti_valid ? spec_insn_bexti_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_binv_valid ? spec_insn_binv_trap : + spec_insn_binvi_valid ? spec_insn_binvi_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_bset_valid ? spec_insn_bset_trap : + spec_insn_bseti_valid ? spec_insn_bseti_trap : spec_insn_clz_valid ? spec_insn_clz_trap : spec_insn_cpop_valid ? spec_insn_cpop_trap : spec_insn_ctz_valid ? spec_insn_ctz_trap : @@ -2329,12 +2657,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_andn_valid ? spec_insn_andn_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs1_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bext_valid ? spec_insn_bext_rs1_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_binv_valid ? spec_insn_binv_rs1_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_bset_valid ? spec_insn_bset_rs1_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs1_addr : spec_insn_clz_valid ? spec_insn_clz_rs1_addr : spec_insn_cpop_valid ? spec_insn_cpop_rs1_addr : spec_insn_ctz_valid ? spec_insn_ctz_rs1_addr : @@ -2386,12 +2722,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_andn_valid ? spec_insn_andn_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs2_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bext_valid ? spec_insn_bext_rs2_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_binv_valid ? spec_insn_binv_rs2_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_bset_valid ? spec_insn_bset_rs2_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs2_addr : spec_insn_clz_valid ? spec_insn_clz_rs2_addr : spec_insn_cpop_valid ? spec_insn_cpop_rs2_addr : spec_insn_ctz_valid ? spec_insn_ctz_rs2_addr : @@ -2443,12 +2787,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_andn_valid ? spec_insn_andn_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rd_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bext_valid ? spec_insn_bext_rd_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_binv_valid ? spec_insn_binv_rd_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_bset_valid ? spec_insn_bset_rd_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rd_addr : spec_insn_clz_valid ? spec_insn_clz_rd_addr : spec_insn_cpop_valid ? spec_insn_cpop_rd_addr : spec_insn_ctz_valid ? spec_insn_ctz_rd_addr : @@ -2500,12 +2852,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_andn_valid ? spec_insn_andn_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_rd_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bext_valid ? spec_insn_bext_rd_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_binv_valid ? spec_insn_binv_rd_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_bset_valid ? spec_insn_bset_rd_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_rd_wdata : spec_insn_clz_valid ? spec_insn_clz_rd_wdata : spec_insn_cpop_valid ? spec_insn_cpop_rd_wdata : spec_insn_ctz_valid ? spec_insn_ctz_rd_wdata : @@ -2557,12 +2917,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_andn_valid ? spec_insn_andn_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_pc_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bext_valid ? spec_insn_bext_pc_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_binv_valid ? spec_insn_binv_pc_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_bset_valid ? spec_insn_bset_pc_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_pc_wdata : spec_insn_clz_valid ? spec_insn_clz_pc_wdata : spec_insn_cpop_valid ? spec_insn_cpop_pc_wdata : spec_insn_ctz_valid ? spec_insn_ctz_pc_wdata : @@ -2614,12 +2982,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_andn_valid ? spec_insn_andn_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_bclr_valid ? spec_insn_bclr_mem_addr : + spec_insn_bclri_valid ? spec_insn_bclri_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bext_valid ? spec_insn_bext_mem_addr : + spec_insn_bexti_valid ? spec_insn_bexti_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_binv_valid ? spec_insn_binv_mem_addr : + spec_insn_binvi_valid ? spec_insn_binvi_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_bset_valid ? spec_insn_bset_mem_addr : + spec_insn_bseti_valid ? spec_insn_bseti_mem_addr : spec_insn_clz_valid ? spec_insn_clz_mem_addr : spec_insn_cpop_valid ? spec_insn_cpop_mem_addr : spec_insn_ctz_valid ? spec_insn_ctz_mem_addr : @@ -2671,12 +3047,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_andn_valid ? spec_insn_andn_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bext_valid ? spec_insn_bext_mem_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_binv_valid ? spec_insn_binv_mem_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_bset_valid ? spec_insn_bset_mem_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_rmask : spec_insn_clz_valid ? spec_insn_clz_mem_rmask : spec_insn_cpop_valid ? spec_insn_cpop_mem_rmask : spec_insn_ctz_valid ? spec_insn_ctz_mem_rmask : @@ -2728,12 +3112,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_andn_valid ? spec_insn_andn_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bext_valid ? spec_insn_bext_mem_wmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_binv_valid ? spec_insn_binv_mem_wmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_bset_valid ? spec_insn_bset_mem_wmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wmask : spec_insn_clz_valid ? spec_insn_clz_mem_wmask : spec_insn_cpop_valid ? spec_insn_cpop_mem_wmask : spec_insn_ctz_valid ? spec_insn_ctz_mem_wmask : @@ -2785,12 +3177,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_andn_valid ? spec_insn_andn_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bext_valid ? spec_insn_bext_mem_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_binv_valid ? spec_insn_binv_mem_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_bset_valid ? spec_insn_bset_mem_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wdata : spec_insn_clz_valid ? spec_insn_clz_mem_wdata : spec_insn_cpop_valid ? spec_insn_cpop_mem_wdata : spec_insn_ctz_valid ? spec_insn_ctz_mem_wdata : @@ -2843,12 +3243,20 @@ module rvfi_isa_rv32ib ( spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_andn_valid ? spec_insn_andn_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_csr_misa_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bext_valid ? spec_insn_bext_csr_misa_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_binv_valid ? spec_insn_binv_csr_misa_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_bset_valid ? spec_insn_bset_csr_misa_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_csr_misa_rmask : spec_insn_clz_valid ? spec_insn_clz_csr_misa_rmask : spec_insn_cpop_valid ? spec_insn_cpop_csr_misa_rmask : spec_insn_ctz_valid ? spec_insn_ctz_csr_misa_rmask : diff --git a/insns/isa_rv64iZbs.txt b/insns/isa_rv64iZbs.txt new file mode 100644 index 00000000..7da6127f --- /dev/null +++ b/insns/isa_rv64iZbs.txt @@ -0,0 +1,57 @@ +add +addi +addiw +addw +and +andi +auipc +bclr +bclri +beq +bext +bexti +bge +bgeu +binv +binvi +blt +bltu +bne +bset +bseti +jal +jalr +lb +lbu +ld +lh +lhu +lui +lw +lwu +or +ori +sb +sd +sh +sll +slli +slliw +sllw +slt +slti +sltiu +sltu +sra +srai +sraiw +sraw +srl +srli +srliw +srlw +sub +subw +sw +xor +xori diff --git a/insns/isa_rv64iZbs.v b/insns/isa_rv64iZbs.v new file mode 100644 index 00000000..8d70d574 --- /dev/null +++ b/insns/isa_rv64iZbs.v @@ -0,0 +1,2948 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_isa_rv64iZbs ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + wire spec_insn_add_valid; + wire spec_insn_add_trap; + wire [ 4 : 0] spec_insn_add_rs1_addr; + wire [ 4 : 0] spec_insn_add_rs2_addr; + wire [ 4 : 0] spec_insn_add_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; +`endif + + rvfi_insn_add insn_add ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), +`endif + .spec_valid(spec_insn_add_valid), + .spec_trap(spec_insn_add_trap), + .spec_rs1_addr(spec_insn_add_rs1_addr), + .spec_rs2_addr(spec_insn_add_rs2_addr), + .spec_rd_addr(spec_insn_add_rd_addr), + .spec_rd_wdata(spec_insn_add_rd_wdata), + .spec_pc_wdata(spec_insn_add_pc_wdata), + .spec_mem_addr(spec_insn_add_mem_addr), + .spec_mem_rmask(spec_insn_add_mem_rmask), + .spec_mem_wmask(spec_insn_add_mem_wmask), + .spec_mem_wdata(spec_insn_add_mem_wdata) + ); + + wire spec_insn_addi_valid; + wire spec_insn_addi_trap; + wire [ 4 : 0] spec_insn_addi_rs1_addr; + wire [ 4 : 0] spec_insn_addi_rs2_addr; + wire [ 4 : 0] spec_insn_addi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; +`endif + + rvfi_insn_addi insn_addi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addi_valid), + .spec_trap(spec_insn_addi_trap), + .spec_rs1_addr(spec_insn_addi_rs1_addr), + .spec_rs2_addr(spec_insn_addi_rs2_addr), + .spec_rd_addr(spec_insn_addi_rd_addr), + .spec_rd_wdata(spec_insn_addi_rd_wdata), + .spec_pc_wdata(spec_insn_addi_pc_wdata), + .spec_mem_addr(spec_insn_addi_mem_addr), + .spec_mem_rmask(spec_insn_addi_mem_rmask), + .spec_mem_wmask(spec_insn_addi_mem_wmask), + .spec_mem_wdata(spec_insn_addi_mem_wdata) + ); + + wire spec_insn_addiw_valid; + wire spec_insn_addiw_trap; + wire [ 4 : 0] spec_insn_addiw_rs1_addr; + wire [ 4 : 0] spec_insn_addiw_rs2_addr; + wire [ 4 : 0] spec_insn_addiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; +`endif + + rvfi_insn_addiw insn_addiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addiw_valid), + .spec_trap(spec_insn_addiw_trap), + .spec_rs1_addr(spec_insn_addiw_rs1_addr), + .spec_rs2_addr(spec_insn_addiw_rs2_addr), + .spec_rd_addr(spec_insn_addiw_rd_addr), + .spec_rd_wdata(spec_insn_addiw_rd_wdata), + .spec_pc_wdata(spec_insn_addiw_pc_wdata), + .spec_mem_addr(spec_insn_addiw_mem_addr), + .spec_mem_rmask(spec_insn_addiw_mem_rmask), + .spec_mem_wmask(spec_insn_addiw_mem_wmask), + .spec_mem_wdata(spec_insn_addiw_mem_wdata) + ); + + wire spec_insn_addw_valid; + wire spec_insn_addw_trap; + wire [ 4 : 0] spec_insn_addw_rs1_addr; + wire [ 4 : 0] spec_insn_addw_rs2_addr; + wire [ 4 : 0] spec_insn_addw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; +`endif + + rvfi_insn_addw insn_addw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_addw_valid), + .spec_trap(spec_insn_addw_trap), + .spec_rs1_addr(spec_insn_addw_rs1_addr), + .spec_rs2_addr(spec_insn_addw_rs2_addr), + .spec_rd_addr(spec_insn_addw_rd_addr), + .spec_rd_wdata(spec_insn_addw_rd_wdata), + .spec_pc_wdata(spec_insn_addw_pc_wdata), + .spec_mem_addr(spec_insn_addw_mem_addr), + .spec_mem_rmask(spec_insn_addw_mem_rmask), + .spec_mem_wmask(spec_insn_addw_mem_wmask), + .spec_mem_wdata(spec_insn_addw_mem_wdata) + ); + + wire spec_insn_and_valid; + wire spec_insn_and_trap; + wire [ 4 : 0] spec_insn_and_rs1_addr; + wire [ 4 : 0] spec_insn_and_rs2_addr; + wire [ 4 : 0] spec_insn_and_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; +`endif + + rvfi_insn_and insn_and ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), +`endif + .spec_valid(spec_insn_and_valid), + .spec_trap(spec_insn_and_trap), + .spec_rs1_addr(spec_insn_and_rs1_addr), + .spec_rs2_addr(spec_insn_and_rs2_addr), + .spec_rd_addr(spec_insn_and_rd_addr), + .spec_rd_wdata(spec_insn_and_rd_wdata), + .spec_pc_wdata(spec_insn_and_pc_wdata), + .spec_mem_addr(spec_insn_and_mem_addr), + .spec_mem_rmask(spec_insn_and_mem_rmask), + .spec_mem_wmask(spec_insn_and_mem_wmask), + .spec_mem_wdata(spec_insn_and_mem_wdata) + ); + + wire spec_insn_andi_valid; + wire spec_insn_andi_trap; + wire [ 4 : 0] spec_insn_andi_rs1_addr; + wire [ 4 : 0] spec_insn_andi_rs2_addr; + wire [ 4 : 0] spec_insn_andi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; +`endif + + rvfi_insn_andi insn_andi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_andi_valid), + .spec_trap(spec_insn_andi_trap), + .spec_rs1_addr(spec_insn_andi_rs1_addr), + .spec_rs2_addr(spec_insn_andi_rs2_addr), + .spec_rd_addr(spec_insn_andi_rd_addr), + .spec_rd_wdata(spec_insn_andi_rd_wdata), + .spec_pc_wdata(spec_insn_andi_pc_wdata), + .spec_mem_addr(spec_insn_andi_mem_addr), + .spec_mem_rmask(spec_insn_andi_mem_rmask), + .spec_mem_wmask(spec_insn_andi_mem_wmask), + .spec_mem_wdata(spec_insn_andi_mem_wdata) + ); + + wire spec_insn_auipc_valid; + wire spec_insn_auipc_trap; + wire [ 4 : 0] spec_insn_auipc_rs1_addr; + wire [ 4 : 0] spec_insn_auipc_rs2_addr; + wire [ 4 : 0] spec_insn_auipc_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; +`endif + + rvfi_insn_auipc insn_auipc ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), +`endif + .spec_valid(spec_insn_auipc_valid), + .spec_trap(spec_insn_auipc_trap), + .spec_rs1_addr(spec_insn_auipc_rs1_addr), + .spec_rs2_addr(spec_insn_auipc_rs2_addr), + .spec_rd_addr(spec_insn_auipc_rd_addr), + .spec_rd_wdata(spec_insn_auipc_rd_wdata), + .spec_pc_wdata(spec_insn_auipc_pc_wdata), + .spec_mem_addr(spec_insn_auipc_mem_addr), + .spec_mem_rmask(spec_insn_auipc_mem_rmask), + .spec_mem_wmask(spec_insn_auipc_mem_wmask), + .spec_mem_wdata(spec_insn_auipc_mem_wdata) + ); + + wire spec_insn_bclr_valid; + wire spec_insn_bclr_trap; + wire [ 4 : 0] spec_insn_bclr_rs1_addr; + wire [ 4 : 0] spec_insn_bclr_rs2_addr; + wire [ 4 : 0] spec_insn_bclr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_csr_misa_rmask; +`endif + + rvfi_insn_bclr insn_bclr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclr_valid), + .spec_trap(spec_insn_bclr_trap), + .spec_rs1_addr(spec_insn_bclr_rs1_addr), + .spec_rs2_addr(spec_insn_bclr_rs2_addr), + .spec_rd_addr(spec_insn_bclr_rd_addr), + .spec_rd_wdata(spec_insn_bclr_rd_wdata), + .spec_pc_wdata(spec_insn_bclr_pc_wdata), + .spec_mem_addr(spec_insn_bclr_mem_addr), + .spec_mem_rmask(spec_insn_bclr_mem_rmask), + .spec_mem_wmask(spec_insn_bclr_mem_wmask), + .spec_mem_wdata(spec_insn_bclr_mem_wdata) + ); + + wire spec_insn_bclri_valid; + wire spec_insn_bclri_trap; + wire [ 4 : 0] spec_insn_bclri_rs1_addr; + wire [ 4 : 0] spec_insn_bclri_rs2_addr; + wire [ 4 : 0] spec_insn_bclri_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_csr_misa_rmask; +`endif + + rvfi_insn_bclri insn_bclri ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclri_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclri_valid), + .spec_trap(spec_insn_bclri_trap), + .spec_rs1_addr(spec_insn_bclri_rs1_addr), + .spec_rs2_addr(spec_insn_bclri_rs2_addr), + .spec_rd_addr(spec_insn_bclri_rd_addr), + .spec_rd_wdata(spec_insn_bclri_rd_wdata), + .spec_pc_wdata(spec_insn_bclri_pc_wdata), + .spec_mem_addr(spec_insn_bclri_mem_addr), + .spec_mem_rmask(spec_insn_bclri_mem_rmask), + .spec_mem_wmask(spec_insn_bclri_mem_wmask), + .spec_mem_wdata(spec_insn_bclri_mem_wdata) + ); + + wire spec_insn_beq_valid; + wire spec_insn_beq_trap; + wire [ 4 : 0] spec_insn_beq_rs1_addr; + wire [ 4 : 0] spec_insn_beq_rs2_addr; + wire [ 4 : 0] spec_insn_beq_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; +`endif + + rvfi_insn_beq insn_beq ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), +`endif + .spec_valid(spec_insn_beq_valid), + .spec_trap(spec_insn_beq_trap), + .spec_rs1_addr(spec_insn_beq_rs1_addr), + .spec_rs2_addr(spec_insn_beq_rs2_addr), + .spec_rd_addr(spec_insn_beq_rd_addr), + .spec_rd_wdata(spec_insn_beq_rd_wdata), + .spec_pc_wdata(spec_insn_beq_pc_wdata), + .spec_mem_addr(spec_insn_beq_mem_addr), + .spec_mem_rmask(spec_insn_beq_mem_rmask), + .spec_mem_wmask(spec_insn_beq_mem_wmask), + .spec_mem_wdata(spec_insn_beq_mem_wdata) + ); + + wire spec_insn_bext_valid; + wire spec_insn_bext_trap; + wire [ 4 : 0] spec_insn_bext_rs1_addr; + wire [ 4 : 0] spec_insn_bext_rs2_addr; + wire [ 4 : 0] spec_insn_bext_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_csr_misa_rmask; +`endif + + rvfi_insn_bext insn_bext ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bext_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bext_valid), + .spec_trap(spec_insn_bext_trap), + .spec_rs1_addr(spec_insn_bext_rs1_addr), + .spec_rs2_addr(spec_insn_bext_rs2_addr), + .spec_rd_addr(spec_insn_bext_rd_addr), + .spec_rd_wdata(spec_insn_bext_rd_wdata), + .spec_pc_wdata(spec_insn_bext_pc_wdata), + .spec_mem_addr(spec_insn_bext_mem_addr), + .spec_mem_rmask(spec_insn_bext_mem_rmask), + .spec_mem_wmask(spec_insn_bext_mem_wmask), + .spec_mem_wdata(spec_insn_bext_mem_wdata) + ); + + wire spec_insn_bexti_valid; + wire spec_insn_bexti_trap; + wire [ 4 : 0] spec_insn_bexti_rs1_addr; + wire [ 4 : 0] spec_insn_bexti_rs2_addr; + wire [ 4 : 0] spec_insn_bexti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_csr_misa_rmask; +`endif + + rvfi_insn_bexti insn_bexti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bexti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bexti_valid), + .spec_trap(spec_insn_bexti_trap), + .spec_rs1_addr(spec_insn_bexti_rs1_addr), + .spec_rs2_addr(spec_insn_bexti_rs2_addr), + .spec_rd_addr(spec_insn_bexti_rd_addr), + .spec_rd_wdata(spec_insn_bexti_rd_wdata), + .spec_pc_wdata(spec_insn_bexti_pc_wdata), + .spec_mem_addr(spec_insn_bexti_mem_addr), + .spec_mem_rmask(spec_insn_bexti_mem_rmask), + .spec_mem_wmask(spec_insn_bexti_mem_wmask), + .spec_mem_wdata(spec_insn_bexti_mem_wdata) + ); + + wire spec_insn_bge_valid; + wire spec_insn_bge_trap; + wire [ 4 : 0] spec_insn_bge_rs1_addr; + wire [ 4 : 0] spec_insn_bge_rs2_addr; + wire [ 4 : 0] spec_insn_bge_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; +`endif + + rvfi_insn_bge insn_bge ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bge_valid), + .spec_trap(spec_insn_bge_trap), + .spec_rs1_addr(spec_insn_bge_rs1_addr), + .spec_rs2_addr(spec_insn_bge_rs2_addr), + .spec_rd_addr(spec_insn_bge_rd_addr), + .spec_rd_wdata(spec_insn_bge_rd_wdata), + .spec_pc_wdata(spec_insn_bge_pc_wdata), + .spec_mem_addr(spec_insn_bge_mem_addr), + .spec_mem_rmask(spec_insn_bge_mem_rmask), + .spec_mem_wmask(spec_insn_bge_mem_wmask), + .spec_mem_wdata(spec_insn_bge_mem_wdata) + ); + + wire spec_insn_bgeu_valid; + wire spec_insn_bgeu_trap; + wire [ 4 : 0] spec_insn_bgeu_rs1_addr; + wire [ 4 : 0] spec_insn_bgeu_rs2_addr; + wire [ 4 : 0] spec_insn_bgeu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; +`endif + + rvfi_insn_bgeu insn_bgeu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bgeu_valid), + .spec_trap(spec_insn_bgeu_trap), + .spec_rs1_addr(spec_insn_bgeu_rs1_addr), + .spec_rs2_addr(spec_insn_bgeu_rs2_addr), + .spec_rd_addr(spec_insn_bgeu_rd_addr), + .spec_rd_wdata(spec_insn_bgeu_rd_wdata), + .spec_pc_wdata(spec_insn_bgeu_pc_wdata), + .spec_mem_addr(spec_insn_bgeu_mem_addr), + .spec_mem_rmask(spec_insn_bgeu_mem_rmask), + .spec_mem_wmask(spec_insn_bgeu_mem_wmask), + .spec_mem_wdata(spec_insn_bgeu_mem_wdata) + ); + + wire spec_insn_binv_valid; + wire spec_insn_binv_trap; + wire [ 4 : 0] spec_insn_binv_rs1_addr; + wire [ 4 : 0] spec_insn_binv_rs2_addr; + wire [ 4 : 0] spec_insn_binv_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_csr_misa_rmask; +`endif + + rvfi_insn_binv insn_binv ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binv_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binv_valid), + .spec_trap(spec_insn_binv_trap), + .spec_rs1_addr(spec_insn_binv_rs1_addr), + .spec_rs2_addr(spec_insn_binv_rs2_addr), + .spec_rd_addr(spec_insn_binv_rd_addr), + .spec_rd_wdata(spec_insn_binv_rd_wdata), + .spec_pc_wdata(spec_insn_binv_pc_wdata), + .spec_mem_addr(spec_insn_binv_mem_addr), + .spec_mem_rmask(spec_insn_binv_mem_rmask), + .spec_mem_wmask(spec_insn_binv_mem_wmask), + .spec_mem_wdata(spec_insn_binv_mem_wdata) + ); + + wire spec_insn_binvi_valid; + wire spec_insn_binvi_trap; + wire [ 4 : 0] spec_insn_binvi_rs1_addr; + wire [ 4 : 0] spec_insn_binvi_rs2_addr; + wire [ 4 : 0] spec_insn_binvi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_csr_misa_rmask; +`endif + + rvfi_insn_binvi insn_binvi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binvi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binvi_valid), + .spec_trap(spec_insn_binvi_trap), + .spec_rs1_addr(spec_insn_binvi_rs1_addr), + .spec_rs2_addr(spec_insn_binvi_rs2_addr), + .spec_rd_addr(spec_insn_binvi_rd_addr), + .spec_rd_wdata(spec_insn_binvi_rd_wdata), + .spec_pc_wdata(spec_insn_binvi_pc_wdata), + .spec_mem_addr(spec_insn_binvi_mem_addr), + .spec_mem_rmask(spec_insn_binvi_mem_rmask), + .spec_mem_wmask(spec_insn_binvi_mem_wmask), + .spec_mem_wdata(spec_insn_binvi_mem_wdata) + ); + + wire spec_insn_blt_valid; + wire spec_insn_blt_trap; + wire [ 4 : 0] spec_insn_blt_rs1_addr; + wire [ 4 : 0] spec_insn_blt_rs2_addr; + wire [ 4 : 0] spec_insn_blt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; +`endif + + rvfi_insn_blt insn_blt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_blt_valid), + .spec_trap(spec_insn_blt_trap), + .spec_rs1_addr(spec_insn_blt_rs1_addr), + .spec_rs2_addr(spec_insn_blt_rs2_addr), + .spec_rd_addr(spec_insn_blt_rd_addr), + .spec_rd_wdata(spec_insn_blt_rd_wdata), + .spec_pc_wdata(spec_insn_blt_pc_wdata), + .spec_mem_addr(spec_insn_blt_mem_addr), + .spec_mem_rmask(spec_insn_blt_mem_rmask), + .spec_mem_wmask(spec_insn_blt_mem_wmask), + .spec_mem_wdata(spec_insn_blt_mem_wdata) + ); + + wire spec_insn_bltu_valid; + wire spec_insn_bltu_trap; + wire [ 4 : 0] spec_insn_bltu_rs1_addr; + wire [ 4 : 0] spec_insn_bltu_rs2_addr; + wire [ 4 : 0] spec_insn_bltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; +`endif + + rvfi_insn_bltu insn_bltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bltu_valid), + .spec_trap(spec_insn_bltu_trap), + .spec_rs1_addr(spec_insn_bltu_rs1_addr), + .spec_rs2_addr(spec_insn_bltu_rs2_addr), + .spec_rd_addr(spec_insn_bltu_rd_addr), + .spec_rd_wdata(spec_insn_bltu_rd_wdata), + .spec_pc_wdata(spec_insn_bltu_pc_wdata), + .spec_mem_addr(spec_insn_bltu_mem_addr), + .spec_mem_rmask(spec_insn_bltu_mem_rmask), + .spec_mem_wmask(spec_insn_bltu_mem_wmask), + .spec_mem_wdata(spec_insn_bltu_mem_wdata) + ); + + wire spec_insn_bne_valid; + wire spec_insn_bne_trap; + wire [ 4 : 0] spec_insn_bne_rs1_addr; + wire [ 4 : 0] spec_insn_bne_rs2_addr; + wire [ 4 : 0] spec_insn_bne_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; +`endif + + rvfi_insn_bne insn_bne ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bne_valid), + .spec_trap(spec_insn_bne_trap), + .spec_rs1_addr(spec_insn_bne_rs1_addr), + .spec_rs2_addr(spec_insn_bne_rs2_addr), + .spec_rd_addr(spec_insn_bne_rd_addr), + .spec_rd_wdata(spec_insn_bne_rd_wdata), + .spec_pc_wdata(spec_insn_bne_pc_wdata), + .spec_mem_addr(spec_insn_bne_mem_addr), + .spec_mem_rmask(spec_insn_bne_mem_rmask), + .spec_mem_wmask(spec_insn_bne_mem_wmask), + .spec_mem_wdata(spec_insn_bne_mem_wdata) + ); + + wire spec_insn_bset_valid; + wire spec_insn_bset_trap; + wire [ 4 : 0] spec_insn_bset_rs1_addr; + wire [ 4 : 0] spec_insn_bset_rs2_addr; + wire [ 4 : 0] spec_insn_bset_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_csr_misa_rmask; +`endif + + rvfi_insn_bset insn_bset ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bset_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bset_valid), + .spec_trap(spec_insn_bset_trap), + .spec_rs1_addr(spec_insn_bset_rs1_addr), + .spec_rs2_addr(spec_insn_bset_rs2_addr), + .spec_rd_addr(spec_insn_bset_rd_addr), + .spec_rd_wdata(spec_insn_bset_rd_wdata), + .spec_pc_wdata(spec_insn_bset_pc_wdata), + .spec_mem_addr(spec_insn_bset_mem_addr), + .spec_mem_rmask(spec_insn_bset_mem_rmask), + .spec_mem_wmask(spec_insn_bset_mem_wmask), + .spec_mem_wdata(spec_insn_bset_mem_wdata) + ); + + wire spec_insn_bseti_valid; + wire spec_insn_bseti_trap; + wire [ 4 : 0] spec_insn_bseti_rs1_addr; + wire [ 4 : 0] spec_insn_bseti_rs2_addr; + wire [ 4 : 0] spec_insn_bseti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_csr_misa_rmask; +`endif + + rvfi_insn_bseti insn_bseti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bseti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bseti_valid), + .spec_trap(spec_insn_bseti_trap), + .spec_rs1_addr(spec_insn_bseti_rs1_addr), + .spec_rs2_addr(spec_insn_bseti_rs2_addr), + .spec_rd_addr(spec_insn_bseti_rd_addr), + .spec_rd_wdata(spec_insn_bseti_rd_wdata), + .spec_pc_wdata(spec_insn_bseti_pc_wdata), + .spec_mem_addr(spec_insn_bseti_mem_addr), + .spec_mem_rmask(spec_insn_bseti_mem_rmask), + .spec_mem_wmask(spec_insn_bseti_mem_wmask), + .spec_mem_wdata(spec_insn_bseti_mem_wdata) + ); + + wire spec_insn_jal_valid; + wire spec_insn_jal_trap; + wire [ 4 : 0] spec_insn_jal_rs1_addr; + wire [ 4 : 0] spec_insn_jal_rs2_addr; + wire [ 4 : 0] spec_insn_jal_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; +`endif + + rvfi_insn_jal insn_jal ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jal_valid), + .spec_trap(spec_insn_jal_trap), + .spec_rs1_addr(spec_insn_jal_rs1_addr), + .spec_rs2_addr(spec_insn_jal_rs2_addr), + .spec_rd_addr(spec_insn_jal_rd_addr), + .spec_rd_wdata(spec_insn_jal_rd_wdata), + .spec_pc_wdata(spec_insn_jal_pc_wdata), + .spec_mem_addr(spec_insn_jal_mem_addr), + .spec_mem_rmask(spec_insn_jal_mem_rmask), + .spec_mem_wmask(spec_insn_jal_mem_wmask), + .spec_mem_wdata(spec_insn_jal_mem_wdata) + ); + + wire spec_insn_jalr_valid; + wire spec_insn_jalr_trap; + wire [ 4 : 0] spec_insn_jalr_rs1_addr; + wire [ 4 : 0] spec_insn_jalr_rs2_addr; + wire [ 4 : 0] spec_insn_jalr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; +`endif + + rvfi_insn_jalr insn_jalr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_jalr_valid), + .spec_trap(spec_insn_jalr_trap), + .spec_rs1_addr(spec_insn_jalr_rs1_addr), + .spec_rs2_addr(spec_insn_jalr_rs2_addr), + .spec_rd_addr(spec_insn_jalr_rd_addr), + .spec_rd_wdata(spec_insn_jalr_rd_wdata), + .spec_pc_wdata(spec_insn_jalr_pc_wdata), + .spec_mem_addr(spec_insn_jalr_mem_addr), + .spec_mem_rmask(spec_insn_jalr_mem_rmask), + .spec_mem_wmask(spec_insn_jalr_mem_wmask), + .spec_mem_wdata(spec_insn_jalr_mem_wdata) + ); + + wire spec_insn_lb_valid; + wire spec_insn_lb_trap; + wire [ 4 : 0] spec_insn_lb_rs1_addr; + wire [ 4 : 0] spec_insn_lb_rs2_addr; + wire [ 4 : 0] spec_insn_lb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; +`endif + + rvfi_insn_lb insn_lb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lb_valid), + .spec_trap(spec_insn_lb_trap), + .spec_rs1_addr(spec_insn_lb_rs1_addr), + .spec_rs2_addr(spec_insn_lb_rs2_addr), + .spec_rd_addr(spec_insn_lb_rd_addr), + .spec_rd_wdata(spec_insn_lb_rd_wdata), + .spec_pc_wdata(spec_insn_lb_pc_wdata), + .spec_mem_addr(spec_insn_lb_mem_addr), + .spec_mem_rmask(spec_insn_lb_mem_rmask), + .spec_mem_wmask(spec_insn_lb_mem_wmask), + .spec_mem_wdata(spec_insn_lb_mem_wdata) + ); + + wire spec_insn_lbu_valid; + wire spec_insn_lbu_trap; + wire [ 4 : 0] spec_insn_lbu_rs1_addr; + wire [ 4 : 0] spec_insn_lbu_rs2_addr; + wire [ 4 : 0] spec_insn_lbu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; +`endif + + rvfi_insn_lbu insn_lbu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lbu_valid), + .spec_trap(spec_insn_lbu_trap), + .spec_rs1_addr(spec_insn_lbu_rs1_addr), + .spec_rs2_addr(spec_insn_lbu_rs2_addr), + .spec_rd_addr(spec_insn_lbu_rd_addr), + .spec_rd_wdata(spec_insn_lbu_rd_wdata), + .spec_pc_wdata(spec_insn_lbu_pc_wdata), + .spec_mem_addr(spec_insn_lbu_mem_addr), + .spec_mem_rmask(spec_insn_lbu_mem_rmask), + .spec_mem_wmask(spec_insn_lbu_mem_wmask), + .spec_mem_wdata(spec_insn_lbu_mem_wdata) + ); + + wire spec_insn_ld_valid; + wire spec_insn_ld_trap; + wire [ 4 : 0] spec_insn_ld_rs1_addr; + wire [ 4 : 0] spec_insn_ld_rs2_addr; + wire [ 4 : 0] spec_insn_ld_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; +`endif + + rvfi_insn_ld insn_ld ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ld_valid), + .spec_trap(spec_insn_ld_trap), + .spec_rs1_addr(spec_insn_ld_rs1_addr), + .spec_rs2_addr(spec_insn_ld_rs2_addr), + .spec_rd_addr(spec_insn_ld_rd_addr), + .spec_rd_wdata(spec_insn_ld_rd_wdata), + .spec_pc_wdata(spec_insn_ld_pc_wdata), + .spec_mem_addr(spec_insn_ld_mem_addr), + .spec_mem_rmask(spec_insn_ld_mem_rmask), + .spec_mem_wmask(spec_insn_ld_mem_wmask), + .spec_mem_wdata(spec_insn_ld_mem_wdata) + ); + + wire spec_insn_lh_valid; + wire spec_insn_lh_trap; + wire [ 4 : 0] spec_insn_lh_rs1_addr; + wire [ 4 : 0] spec_insn_lh_rs2_addr; + wire [ 4 : 0] spec_insn_lh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; +`endif + + rvfi_insn_lh insn_lh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lh_valid), + .spec_trap(spec_insn_lh_trap), + .spec_rs1_addr(spec_insn_lh_rs1_addr), + .spec_rs2_addr(spec_insn_lh_rs2_addr), + .spec_rd_addr(spec_insn_lh_rd_addr), + .spec_rd_wdata(spec_insn_lh_rd_wdata), + .spec_pc_wdata(spec_insn_lh_pc_wdata), + .spec_mem_addr(spec_insn_lh_mem_addr), + .spec_mem_rmask(spec_insn_lh_mem_rmask), + .spec_mem_wmask(spec_insn_lh_mem_wmask), + .spec_mem_wdata(spec_insn_lh_mem_wdata) + ); + + wire spec_insn_lhu_valid; + wire spec_insn_lhu_trap; + wire [ 4 : 0] spec_insn_lhu_rs1_addr; + wire [ 4 : 0] spec_insn_lhu_rs2_addr; + wire [ 4 : 0] spec_insn_lhu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; +`endif + + rvfi_insn_lhu insn_lhu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lhu_valid), + .spec_trap(spec_insn_lhu_trap), + .spec_rs1_addr(spec_insn_lhu_rs1_addr), + .spec_rs2_addr(spec_insn_lhu_rs2_addr), + .spec_rd_addr(spec_insn_lhu_rd_addr), + .spec_rd_wdata(spec_insn_lhu_rd_wdata), + .spec_pc_wdata(spec_insn_lhu_pc_wdata), + .spec_mem_addr(spec_insn_lhu_mem_addr), + .spec_mem_rmask(spec_insn_lhu_mem_rmask), + .spec_mem_wmask(spec_insn_lhu_mem_wmask), + .spec_mem_wdata(spec_insn_lhu_mem_wdata) + ); + + wire spec_insn_lui_valid; + wire spec_insn_lui_trap; + wire [ 4 : 0] spec_insn_lui_rs1_addr; + wire [ 4 : 0] spec_insn_lui_rs2_addr; + wire [ 4 : 0] spec_insn_lui_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; +`endif + + rvfi_insn_lui insn_lui ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lui_valid), + .spec_trap(spec_insn_lui_trap), + .spec_rs1_addr(spec_insn_lui_rs1_addr), + .spec_rs2_addr(spec_insn_lui_rs2_addr), + .spec_rd_addr(spec_insn_lui_rd_addr), + .spec_rd_wdata(spec_insn_lui_rd_wdata), + .spec_pc_wdata(spec_insn_lui_pc_wdata), + .spec_mem_addr(spec_insn_lui_mem_addr), + .spec_mem_rmask(spec_insn_lui_mem_rmask), + .spec_mem_wmask(spec_insn_lui_mem_wmask), + .spec_mem_wdata(spec_insn_lui_mem_wdata) + ); + + wire spec_insn_lw_valid; + wire spec_insn_lw_trap; + wire [ 4 : 0] spec_insn_lw_rs1_addr; + wire [ 4 : 0] spec_insn_lw_rs2_addr; + wire [ 4 : 0] spec_insn_lw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; +`endif + + rvfi_insn_lw insn_lw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lw_valid), + .spec_trap(spec_insn_lw_trap), + .spec_rs1_addr(spec_insn_lw_rs1_addr), + .spec_rs2_addr(spec_insn_lw_rs2_addr), + .spec_rd_addr(spec_insn_lw_rd_addr), + .spec_rd_wdata(spec_insn_lw_rd_wdata), + .spec_pc_wdata(spec_insn_lw_pc_wdata), + .spec_mem_addr(spec_insn_lw_mem_addr), + .spec_mem_rmask(spec_insn_lw_mem_rmask), + .spec_mem_wmask(spec_insn_lw_mem_wmask), + .spec_mem_wdata(spec_insn_lw_mem_wdata) + ); + + wire spec_insn_lwu_valid; + wire spec_insn_lwu_trap; + wire [ 4 : 0] spec_insn_lwu_rs1_addr; + wire [ 4 : 0] spec_insn_lwu_rs2_addr; + wire [ 4 : 0] spec_insn_lwu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; +`endif + + rvfi_insn_lwu insn_lwu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_lwu_valid), + .spec_trap(spec_insn_lwu_trap), + .spec_rs1_addr(spec_insn_lwu_rs1_addr), + .spec_rs2_addr(spec_insn_lwu_rs2_addr), + .spec_rd_addr(spec_insn_lwu_rd_addr), + .spec_rd_wdata(spec_insn_lwu_rd_wdata), + .spec_pc_wdata(spec_insn_lwu_pc_wdata), + .spec_mem_addr(spec_insn_lwu_mem_addr), + .spec_mem_rmask(spec_insn_lwu_mem_rmask), + .spec_mem_wmask(spec_insn_lwu_mem_wmask), + .spec_mem_wdata(spec_insn_lwu_mem_wdata) + ); + + wire spec_insn_or_valid; + wire spec_insn_or_trap; + wire [ 4 : 0] spec_insn_or_rs1_addr; + wire [ 4 : 0] spec_insn_or_rs2_addr; + wire [ 4 : 0] spec_insn_or_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; +`endif + + rvfi_insn_or insn_or ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), +`endif + .spec_valid(spec_insn_or_valid), + .spec_trap(spec_insn_or_trap), + .spec_rs1_addr(spec_insn_or_rs1_addr), + .spec_rs2_addr(spec_insn_or_rs2_addr), + .spec_rd_addr(spec_insn_or_rd_addr), + .spec_rd_wdata(spec_insn_or_rd_wdata), + .spec_pc_wdata(spec_insn_or_pc_wdata), + .spec_mem_addr(spec_insn_or_mem_addr), + .spec_mem_rmask(spec_insn_or_mem_rmask), + .spec_mem_wmask(spec_insn_or_mem_wmask), + .spec_mem_wdata(spec_insn_or_mem_wdata) + ); + + wire spec_insn_ori_valid; + wire spec_insn_ori_trap; + wire [ 4 : 0] spec_insn_ori_rs1_addr; + wire [ 4 : 0] spec_insn_ori_rs2_addr; + wire [ 4 : 0] spec_insn_ori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; +`endif + + rvfi_insn_ori insn_ori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_ori_valid), + .spec_trap(spec_insn_ori_trap), + .spec_rs1_addr(spec_insn_ori_rs1_addr), + .spec_rs2_addr(spec_insn_ori_rs2_addr), + .spec_rd_addr(spec_insn_ori_rd_addr), + .spec_rd_wdata(spec_insn_ori_rd_wdata), + .spec_pc_wdata(spec_insn_ori_pc_wdata), + .spec_mem_addr(spec_insn_ori_mem_addr), + .spec_mem_rmask(spec_insn_ori_mem_rmask), + .spec_mem_wmask(spec_insn_ori_mem_wmask), + .spec_mem_wdata(spec_insn_ori_mem_wdata) + ); + + wire spec_insn_sb_valid; + wire spec_insn_sb_trap; + wire [ 4 : 0] spec_insn_sb_rs1_addr; + wire [ 4 : 0] spec_insn_sb_rs2_addr; + wire [ 4 : 0] spec_insn_sb_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; +`endif + + rvfi_insn_sb insn_sb ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sb_valid), + .spec_trap(spec_insn_sb_trap), + .spec_rs1_addr(spec_insn_sb_rs1_addr), + .spec_rs2_addr(spec_insn_sb_rs2_addr), + .spec_rd_addr(spec_insn_sb_rd_addr), + .spec_rd_wdata(spec_insn_sb_rd_wdata), + .spec_pc_wdata(spec_insn_sb_pc_wdata), + .spec_mem_addr(spec_insn_sb_mem_addr), + .spec_mem_rmask(spec_insn_sb_mem_rmask), + .spec_mem_wmask(spec_insn_sb_mem_wmask), + .spec_mem_wdata(spec_insn_sb_mem_wdata) + ); + + wire spec_insn_sd_valid; + wire spec_insn_sd_trap; + wire [ 4 : 0] spec_insn_sd_rs1_addr; + wire [ 4 : 0] spec_insn_sd_rs2_addr; + wire [ 4 : 0] spec_insn_sd_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; +`endif + + rvfi_insn_sd insn_sd ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sd_valid), + .spec_trap(spec_insn_sd_trap), + .spec_rs1_addr(spec_insn_sd_rs1_addr), + .spec_rs2_addr(spec_insn_sd_rs2_addr), + .spec_rd_addr(spec_insn_sd_rd_addr), + .spec_rd_wdata(spec_insn_sd_rd_wdata), + .spec_pc_wdata(spec_insn_sd_pc_wdata), + .spec_mem_addr(spec_insn_sd_mem_addr), + .spec_mem_rmask(spec_insn_sd_mem_rmask), + .spec_mem_wmask(spec_insn_sd_mem_wmask), + .spec_mem_wdata(spec_insn_sd_mem_wdata) + ); + + wire spec_insn_sh_valid; + wire spec_insn_sh_trap; + wire [ 4 : 0] spec_insn_sh_rs1_addr; + wire [ 4 : 0] spec_insn_sh_rs2_addr; + wire [ 4 : 0] spec_insn_sh_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; +`endif + + rvfi_insn_sh insn_sh ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sh_valid), + .spec_trap(spec_insn_sh_trap), + .spec_rs1_addr(spec_insn_sh_rs1_addr), + .spec_rs2_addr(spec_insn_sh_rs2_addr), + .spec_rd_addr(spec_insn_sh_rd_addr), + .spec_rd_wdata(spec_insn_sh_rd_wdata), + .spec_pc_wdata(spec_insn_sh_pc_wdata), + .spec_mem_addr(spec_insn_sh_mem_addr), + .spec_mem_rmask(spec_insn_sh_mem_rmask), + .spec_mem_wmask(spec_insn_sh_mem_wmask), + .spec_mem_wdata(spec_insn_sh_mem_wdata) + ); + + wire spec_insn_sll_valid; + wire spec_insn_sll_trap; + wire [ 4 : 0] spec_insn_sll_rs1_addr; + wire [ 4 : 0] spec_insn_sll_rs2_addr; + wire [ 4 : 0] spec_insn_sll_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; +`endif + + rvfi_insn_sll insn_sll ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sll_valid), + .spec_trap(spec_insn_sll_trap), + .spec_rs1_addr(spec_insn_sll_rs1_addr), + .spec_rs2_addr(spec_insn_sll_rs2_addr), + .spec_rd_addr(spec_insn_sll_rd_addr), + .spec_rd_wdata(spec_insn_sll_rd_wdata), + .spec_pc_wdata(spec_insn_sll_pc_wdata), + .spec_mem_addr(spec_insn_sll_mem_addr), + .spec_mem_rmask(spec_insn_sll_mem_rmask), + .spec_mem_wmask(spec_insn_sll_mem_wmask), + .spec_mem_wdata(spec_insn_sll_mem_wdata) + ); + + wire spec_insn_slli_valid; + wire spec_insn_slli_trap; + wire [ 4 : 0] spec_insn_slli_rs1_addr; + wire [ 4 : 0] spec_insn_slli_rs2_addr; + wire [ 4 : 0] spec_insn_slli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; +`endif + + rvfi_insn_slli insn_slli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slli_valid), + .spec_trap(spec_insn_slli_trap), + .spec_rs1_addr(spec_insn_slli_rs1_addr), + .spec_rs2_addr(spec_insn_slli_rs2_addr), + .spec_rd_addr(spec_insn_slli_rd_addr), + .spec_rd_wdata(spec_insn_slli_rd_wdata), + .spec_pc_wdata(spec_insn_slli_pc_wdata), + .spec_mem_addr(spec_insn_slli_mem_addr), + .spec_mem_rmask(spec_insn_slli_mem_rmask), + .spec_mem_wmask(spec_insn_slli_mem_wmask), + .spec_mem_wdata(spec_insn_slli_mem_wdata) + ); + + wire spec_insn_slliw_valid; + wire spec_insn_slliw_trap; + wire [ 4 : 0] spec_insn_slliw_rs1_addr; + wire [ 4 : 0] spec_insn_slliw_rs2_addr; + wire [ 4 : 0] spec_insn_slliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; +`endif + + rvfi_insn_slliw insn_slliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slliw_valid), + .spec_trap(spec_insn_slliw_trap), + .spec_rs1_addr(spec_insn_slliw_rs1_addr), + .spec_rs2_addr(spec_insn_slliw_rs2_addr), + .spec_rd_addr(spec_insn_slliw_rd_addr), + .spec_rd_wdata(spec_insn_slliw_rd_wdata), + .spec_pc_wdata(spec_insn_slliw_pc_wdata), + .spec_mem_addr(spec_insn_slliw_mem_addr), + .spec_mem_rmask(spec_insn_slliw_mem_rmask), + .spec_mem_wmask(spec_insn_slliw_mem_wmask), + .spec_mem_wdata(spec_insn_slliw_mem_wdata) + ); + + wire spec_insn_sllw_valid; + wire spec_insn_sllw_trap; + wire [ 4 : 0] spec_insn_sllw_rs1_addr; + wire [ 4 : 0] spec_insn_sllw_rs2_addr; + wire [ 4 : 0] spec_insn_sllw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; +`endif + + rvfi_insn_sllw insn_sllw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sllw_valid), + .spec_trap(spec_insn_sllw_trap), + .spec_rs1_addr(spec_insn_sllw_rs1_addr), + .spec_rs2_addr(spec_insn_sllw_rs2_addr), + .spec_rd_addr(spec_insn_sllw_rd_addr), + .spec_rd_wdata(spec_insn_sllw_rd_wdata), + .spec_pc_wdata(spec_insn_sllw_pc_wdata), + .spec_mem_addr(spec_insn_sllw_mem_addr), + .spec_mem_rmask(spec_insn_sllw_mem_rmask), + .spec_mem_wmask(spec_insn_sllw_mem_wmask), + .spec_mem_wdata(spec_insn_sllw_mem_wdata) + ); + + wire spec_insn_slt_valid; + wire spec_insn_slt_trap; + wire [ 4 : 0] spec_insn_slt_rs1_addr; + wire [ 4 : 0] spec_insn_slt_rs2_addr; + wire [ 4 : 0] spec_insn_slt_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; +`endif + + rvfi_insn_slt insn_slt ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slt_valid), + .spec_trap(spec_insn_slt_trap), + .spec_rs1_addr(spec_insn_slt_rs1_addr), + .spec_rs2_addr(spec_insn_slt_rs2_addr), + .spec_rd_addr(spec_insn_slt_rd_addr), + .spec_rd_wdata(spec_insn_slt_rd_wdata), + .spec_pc_wdata(spec_insn_slt_pc_wdata), + .spec_mem_addr(spec_insn_slt_mem_addr), + .spec_mem_rmask(spec_insn_slt_mem_rmask), + .spec_mem_wmask(spec_insn_slt_mem_wmask), + .spec_mem_wdata(spec_insn_slt_mem_wdata) + ); + + wire spec_insn_slti_valid; + wire spec_insn_slti_trap; + wire [ 4 : 0] spec_insn_slti_rs1_addr; + wire [ 4 : 0] spec_insn_slti_rs2_addr; + wire [ 4 : 0] spec_insn_slti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; +`endif + + rvfi_insn_slti insn_slti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_slti_valid), + .spec_trap(spec_insn_slti_trap), + .spec_rs1_addr(spec_insn_slti_rs1_addr), + .spec_rs2_addr(spec_insn_slti_rs2_addr), + .spec_rd_addr(spec_insn_slti_rd_addr), + .spec_rd_wdata(spec_insn_slti_rd_wdata), + .spec_pc_wdata(spec_insn_slti_pc_wdata), + .spec_mem_addr(spec_insn_slti_mem_addr), + .spec_mem_rmask(spec_insn_slti_mem_rmask), + .spec_mem_wmask(spec_insn_slti_mem_wmask), + .spec_mem_wdata(spec_insn_slti_mem_wdata) + ); + + wire spec_insn_sltiu_valid; + wire spec_insn_sltiu_trap; + wire [ 4 : 0] spec_insn_sltiu_rs1_addr; + wire [ 4 : 0] spec_insn_sltiu_rs2_addr; + wire [ 4 : 0] spec_insn_sltiu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; +`endif + + rvfi_insn_sltiu insn_sltiu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltiu_valid), + .spec_trap(spec_insn_sltiu_trap), + .spec_rs1_addr(spec_insn_sltiu_rs1_addr), + .spec_rs2_addr(spec_insn_sltiu_rs2_addr), + .spec_rd_addr(spec_insn_sltiu_rd_addr), + .spec_rd_wdata(spec_insn_sltiu_rd_wdata), + .spec_pc_wdata(spec_insn_sltiu_pc_wdata), + .spec_mem_addr(spec_insn_sltiu_mem_addr), + .spec_mem_rmask(spec_insn_sltiu_mem_rmask), + .spec_mem_wmask(spec_insn_sltiu_mem_wmask), + .spec_mem_wdata(spec_insn_sltiu_mem_wdata) + ); + + wire spec_insn_sltu_valid; + wire spec_insn_sltu_trap; + wire [ 4 : 0] spec_insn_sltu_rs1_addr; + wire [ 4 : 0] spec_insn_sltu_rs2_addr; + wire [ 4 : 0] spec_insn_sltu_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; +`endif + + rvfi_insn_sltu insn_sltu ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sltu_valid), + .spec_trap(spec_insn_sltu_trap), + .spec_rs1_addr(spec_insn_sltu_rs1_addr), + .spec_rs2_addr(spec_insn_sltu_rs2_addr), + .spec_rd_addr(spec_insn_sltu_rd_addr), + .spec_rd_wdata(spec_insn_sltu_rd_wdata), + .spec_pc_wdata(spec_insn_sltu_pc_wdata), + .spec_mem_addr(spec_insn_sltu_mem_addr), + .spec_mem_rmask(spec_insn_sltu_mem_rmask), + .spec_mem_wmask(spec_insn_sltu_mem_wmask), + .spec_mem_wdata(spec_insn_sltu_mem_wdata) + ); + + wire spec_insn_sra_valid; + wire spec_insn_sra_trap; + wire [ 4 : 0] spec_insn_sra_rs1_addr; + wire [ 4 : 0] spec_insn_sra_rs2_addr; + wire [ 4 : 0] spec_insn_sra_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; +`endif + + rvfi_insn_sra insn_sra ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sra_valid), + .spec_trap(spec_insn_sra_trap), + .spec_rs1_addr(spec_insn_sra_rs1_addr), + .spec_rs2_addr(spec_insn_sra_rs2_addr), + .spec_rd_addr(spec_insn_sra_rd_addr), + .spec_rd_wdata(spec_insn_sra_rd_wdata), + .spec_pc_wdata(spec_insn_sra_pc_wdata), + .spec_mem_addr(spec_insn_sra_mem_addr), + .spec_mem_rmask(spec_insn_sra_mem_rmask), + .spec_mem_wmask(spec_insn_sra_mem_wmask), + .spec_mem_wdata(spec_insn_sra_mem_wdata) + ); + + wire spec_insn_srai_valid; + wire spec_insn_srai_trap; + wire [ 4 : 0] spec_insn_srai_rs1_addr; + wire [ 4 : 0] spec_insn_srai_rs2_addr; + wire [ 4 : 0] spec_insn_srai_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; +`endif + + rvfi_insn_srai insn_srai ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srai_valid), + .spec_trap(spec_insn_srai_trap), + .spec_rs1_addr(spec_insn_srai_rs1_addr), + .spec_rs2_addr(spec_insn_srai_rs2_addr), + .spec_rd_addr(spec_insn_srai_rd_addr), + .spec_rd_wdata(spec_insn_srai_rd_wdata), + .spec_pc_wdata(spec_insn_srai_pc_wdata), + .spec_mem_addr(spec_insn_srai_mem_addr), + .spec_mem_rmask(spec_insn_srai_mem_rmask), + .spec_mem_wmask(spec_insn_srai_mem_wmask), + .spec_mem_wdata(spec_insn_srai_mem_wdata) + ); + + wire spec_insn_sraiw_valid; + wire spec_insn_sraiw_trap; + wire [ 4 : 0] spec_insn_sraiw_rs1_addr; + wire [ 4 : 0] spec_insn_sraiw_rs2_addr; + wire [ 4 : 0] spec_insn_sraiw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; +`endif + + rvfi_insn_sraiw insn_sraiw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraiw_valid), + .spec_trap(spec_insn_sraiw_trap), + .spec_rs1_addr(spec_insn_sraiw_rs1_addr), + .spec_rs2_addr(spec_insn_sraiw_rs2_addr), + .spec_rd_addr(spec_insn_sraiw_rd_addr), + .spec_rd_wdata(spec_insn_sraiw_rd_wdata), + .spec_pc_wdata(spec_insn_sraiw_pc_wdata), + .spec_mem_addr(spec_insn_sraiw_mem_addr), + .spec_mem_rmask(spec_insn_sraiw_mem_rmask), + .spec_mem_wmask(spec_insn_sraiw_mem_wmask), + .spec_mem_wdata(spec_insn_sraiw_mem_wdata) + ); + + wire spec_insn_sraw_valid; + wire spec_insn_sraw_trap; + wire [ 4 : 0] spec_insn_sraw_rs1_addr; + wire [ 4 : 0] spec_insn_sraw_rs2_addr; + wire [ 4 : 0] spec_insn_sraw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; +`endif + + rvfi_insn_sraw insn_sraw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sraw_valid), + .spec_trap(spec_insn_sraw_trap), + .spec_rs1_addr(spec_insn_sraw_rs1_addr), + .spec_rs2_addr(spec_insn_sraw_rs2_addr), + .spec_rd_addr(spec_insn_sraw_rd_addr), + .spec_rd_wdata(spec_insn_sraw_rd_wdata), + .spec_pc_wdata(spec_insn_sraw_pc_wdata), + .spec_mem_addr(spec_insn_sraw_mem_addr), + .spec_mem_rmask(spec_insn_sraw_mem_rmask), + .spec_mem_wmask(spec_insn_sraw_mem_wmask), + .spec_mem_wdata(spec_insn_sraw_mem_wdata) + ); + + wire spec_insn_srl_valid; + wire spec_insn_srl_trap; + wire [ 4 : 0] spec_insn_srl_rs1_addr; + wire [ 4 : 0] spec_insn_srl_rs2_addr; + wire [ 4 : 0] spec_insn_srl_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; +`endif + + rvfi_insn_srl insn_srl ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srl_valid), + .spec_trap(spec_insn_srl_trap), + .spec_rs1_addr(spec_insn_srl_rs1_addr), + .spec_rs2_addr(spec_insn_srl_rs2_addr), + .spec_rd_addr(spec_insn_srl_rd_addr), + .spec_rd_wdata(spec_insn_srl_rd_wdata), + .spec_pc_wdata(spec_insn_srl_pc_wdata), + .spec_mem_addr(spec_insn_srl_mem_addr), + .spec_mem_rmask(spec_insn_srl_mem_rmask), + .spec_mem_wmask(spec_insn_srl_mem_wmask), + .spec_mem_wdata(spec_insn_srl_mem_wdata) + ); + + wire spec_insn_srli_valid; + wire spec_insn_srli_trap; + wire [ 4 : 0] spec_insn_srli_rs1_addr; + wire [ 4 : 0] spec_insn_srli_rs2_addr; + wire [ 4 : 0] spec_insn_srli_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; +`endif + + rvfi_insn_srli insn_srli ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srli_valid), + .spec_trap(spec_insn_srli_trap), + .spec_rs1_addr(spec_insn_srli_rs1_addr), + .spec_rs2_addr(spec_insn_srli_rs2_addr), + .spec_rd_addr(spec_insn_srli_rd_addr), + .spec_rd_wdata(spec_insn_srli_rd_wdata), + .spec_pc_wdata(spec_insn_srli_pc_wdata), + .spec_mem_addr(spec_insn_srli_mem_addr), + .spec_mem_rmask(spec_insn_srli_mem_rmask), + .spec_mem_wmask(spec_insn_srli_mem_wmask), + .spec_mem_wdata(spec_insn_srli_mem_wdata) + ); + + wire spec_insn_srliw_valid; + wire spec_insn_srliw_trap; + wire [ 4 : 0] spec_insn_srliw_rs1_addr; + wire [ 4 : 0] spec_insn_srliw_rs2_addr; + wire [ 4 : 0] spec_insn_srliw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; +`endif + + rvfi_insn_srliw insn_srliw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srliw_valid), + .spec_trap(spec_insn_srliw_trap), + .spec_rs1_addr(spec_insn_srliw_rs1_addr), + .spec_rs2_addr(spec_insn_srliw_rs2_addr), + .spec_rd_addr(spec_insn_srliw_rd_addr), + .spec_rd_wdata(spec_insn_srliw_rd_wdata), + .spec_pc_wdata(spec_insn_srliw_pc_wdata), + .spec_mem_addr(spec_insn_srliw_mem_addr), + .spec_mem_rmask(spec_insn_srliw_mem_rmask), + .spec_mem_wmask(spec_insn_srliw_mem_wmask), + .spec_mem_wdata(spec_insn_srliw_mem_wdata) + ); + + wire spec_insn_srlw_valid; + wire spec_insn_srlw_trap; + wire [ 4 : 0] spec_insn_srlw_rs1_addr; + wire [ 4 : 0] spec_insn_srlw_rs2_addr; + wire [ 4 : 0] spec_insn_srlw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; +`endif + + rvfi_insn_srlw insn_srlw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_srlw_valid), + .spec_trap(spec_insn_srlw_trap), + .spec_rs1_addr(spec_insn_srlw_rs1_addr), + .spec_rs2_addr(spec_insn_srlw_rs2_addr), + .spec_rd_addr(spec_insn_srlw_rd_addr), + .spec_rd_wdata(spec_insn_srlw_rd_wdata), + .spec_pc_wdata(spec_insn_srlw_pc_wdata), + .spec_mem_addr(spec_insn_srlw_mem_addr), + .spec_mem_rmask(spec_insn_srlw_mem_rmask), + .spec_mem_wmask(spec_insn_srlw_mem_wmask), + .spec_mem_wdata(spec_insn_srlw_mem_wdata) + ); + + wire spec_insn_sub_valid; + wire spec_insn_sub_trap; + wire [ 4 : 0] spec_insn_sub_rs1_addr; + wire [ 4 : 0] spec_insn_sub_rs2_addr; + wire [ 4 : 0] spec_insn_sub_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; +`endif + + rvfi_insn_sub insn_sub ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sub_valid), + .spec_trap(spec_insn_sub_trap), + .spec_rs1_addr(spec_insn_sub_rs1_addr), + .spec_rs2_addr(spec_insn_sub_rs2_addr), + .spec_rd_addr(spec_insn_sub_rd_addr), + .spec_rd_wdata(spec_insn_sub_rd_wdata), + .spec_pc_wdata(spec_insn_sub_pc_wdata), + .spec_mem_addr(spec_insn_sub_mem_addr), + .spec_mem_rmask(spec_insn_sub_mem_rmask), + .spec_mem_wmask(spec_insn_sub_mem_wmask), + .spec_mem_wdata(spec_insn_sub_mem_wdata) + ); + + wire spec_insn_subw_valid; + wire spec_insn_subw_trap; + wire [ 4 : 0] spec_insn_subw_rs1_addr; + wire [ 4 : 0] spec_insn_subw_rs2_addr; + wire [ 4 : 0] spec_insn_subw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; +`endif + + rvfi_insn_subw insn_subw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_subw_valid), + .spec_trap(spec_insn_subw_trap), + .spec_rs1_addr(spec_insn_subw_rs1_addr), + .spec_rs2_addr(spec_insn_subw_rs2_addr), + .spec_rd_addr(spec_insn_subw_rd_addr), + .spec_rd_wdata(spec_insn_subw_rd_wdata), + .spec_pc_wdata(spec_insn_subw_pc_wdata), + .spec_mem_addr(spec_insn_subw_mem_addr), + .spec_mem_rmask(spec_insn_subw_mem_rmask), + .spec_mem_wmask(spec_insn_subw_mem_wmask), + .spec_mem_wdata(spec_insn_subw_mem_wdata) + ); + + wire spec_insn_sw_valid; + wire spec_insn_sw_trap; + wire [ 4 : 0] spec_insn_sw_rs1_addr; + wire [ 4 : 0] spec_insn_sw_rs2_addr; + wire [ 4 : 0] spec_insn_sw_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; +`endif + + rvfi_insn_sw insn_sw ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), +`endif + .spec_valid(spec_insn_sw_valid), + .spec_trap(spec_insn_sw_trap), + .spec_rs1_addr(spec_insn_sw_rs1_addr), + .spec_rs2_addr(spec_insn_sw_rs2_addr), + .spec_rd_addr(spec_insn_sw_rd_addr), + .spec_rd_wdata(spec_insn_sw_rd_wdata), + .spec_pc_wdata(spec_insn_sw_pc_wdata), + .spec_mem_addr(spec_insn_sw_mem_addr), + .spec_mem_rmask(spec_insn_sw_mem_rmask), + .spec_mem_wmask(spec_insn_sw_mem_wmask), + .spec_mem_wdata(spec_insn_sw_mem_wdata) + ); + + wire spec_insn_xor_valid; + wire spec_insn_xor_trap; + wire [ 4 : 0] spec_insn_xor_rs1_addr; + wire [ 4 : 0] spec_insn_xor_rs2_addr; + wire [ 4 : 0] spec_insn_xor_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; +`endif + + rvfi_insn_xor insn_xor ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xor_valid), + .spec_trap(spec_insn_xor_trap), + .spec_rs1_addr(spec_insn_xor_rs1_addr), + .spec_rs2_addr(spec_insn_xor_rs2_addr), + .spec_rd_addr(spec_insn_xor_rd_addr), + .spec_rd_wdata(spec_insn_xor_rd_wdata), + .spec_pc_wdata(spec_insn_xor_pc_wdata), + .spec_mem_addr(spec_insn_xor_mem_addr), + .spec_mem_rmask(spec_insn_xor_mem_rmask), + .spec_mem_wmask(spec_insn_xor_mem_wmask), + .spec_mem_wdata(spec_insn_xor_mem_wdata) + ); + + wire spec_insn_xori_valid; + wire spec_insn_xori_trap; + wire [ 4 : 0] spec_insn_xori_rs1_addr; + wire [ 4 : 0] spec_insn_xori_rs2_addr; + wire [ 4 : 0] spec_insn_xori_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; +`endif + + rvfi_insn_xori insn_xori ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), +`endif + .spec_valid(spec_insn_xori_valid), + .spec_trap(spec_insn_xori_trap), + .spec_rs1_addr(spec_insn_xori_rs1_addr), + .spec_rs2_addr(spec_insn_xori_rs2_addr), + .spec_rd_addr(spec_insn_xori_rd_addr), + .spec_rd_wdata(spec_insn_xori_rd_wdata), + .spec_pc_wdata(spec_insn_xori_pc_wdata), + .spec_mem_addr(spec_insn_xori_mem_addr), + .spec_mem_rmask(spec_insn_xori_mem_rmask), + .spec_mem_wmask(spec_insn_xori_mem_wmask), + .spec_mem_wdata(spec_insn_xori_mem_wdata) + ); + + assign spec_valid = + spec_insn_add_valid ? spec_insn_add_valid : + spec_insn_addi_valid ? spec_insn_addi_valid : + spec_insn_addiw_valid ? spec_insn_addiw_valid : + spec_insn_addw_valid ? spec_insn_addw_valid : + spec_insn_and_valid ? spec_insn_and_valid : + spec_insn_andi_valid ? spec_insn_andi_valid : + spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_bclr_valid ? spec_insn_bclr_valid : + spec_insn_bclri_valid ? spec_insn_bclri_valid : + spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bext_valid ? spec_insn_bext_valid : + spec_insn_bexti_valid ? spec_insn_bexti_valid : + spec_insn_bge_valid ? spec_insn_bge_valid : + spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_binv_valid ? spec_insn_binv_valid : + spec_insn_binvi_valid ? spec_insn_binvi_valid : + spec_insn_blt_valid ? spec_insn_blt_valid : + spec_insn_bltu_valid ? spec_insn_bltu_valid : + spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_bset_valid ? spec_insn_bset_valid : + spec_insn_bseti_valid ? spec_insn_bseti_valid : + spec_insn_jal_valid ? spec_insn_jal_valid : + spec_insn_jalr_valid ? spec_insn_jalr_valid : + spec_insn_lb_valid ? spec_insn_lb_valid : + spec_insn_lbu_valid ? spec_insn_lbu_valid : + spec_insn_ld_valid ? spec_insn_ld_valid : + spec_insn_lh_valid ? spec_insn_lh_valid : + spec_insn_lhu_valid ? spec_insn_lhu_valid : + spec_insn_lui_valid ? spec_insn_lui_valid : + spec_insn_lw_valid ? spec_insn_lw_valid : + spec_insn_lwu_valid ? spec_insn_lwu_valid : + spec_insn_or_valid ? spec_insn_or_valid : + spec_insn_ori_valid ? spec_insn_ori_valid : + spec_insn_sb_valid ? spec_insn_sb_valid : + spec_insn_sd_valid ? spec_insn_sd_valid : + spec_insn_sh_valid ? spec_insn_sh_valid : + spec_insn_sll_valid ? spec_insn_sll_valid : + spec_insn_slli_valid ? spec_insn_slli_valid : + spec_insn_slliw_valid ? spec_insn_slliw_valid : + spec_insn_sllw_valid ? spec_insn_sllw_valid : + spec_insn_slt_valid ? spec_insn_slt_valid : + spec_insn_slti_valid ? spec_insn_slti_valid : + spec_insn_sltiu_valid ? spec_insn_sltiu_valid : + spec_insn_sltu_valid ? spec_insn_sltu_valid : + spec_insn_sra_valid ? spec_insn_sra_valid : + spec_insn_srai_valid ? spec_insn_srai_valid : + spec_insn_sraiw_valid ? spec_insn_sraiw_valid : + spec_insn_sraw_valid ? spec_insn_sraw_valid : + spec_insn_srl_valid ? spec_insn_srl_valid : + spec_insn_srli_valid ? spec_insn_srli_valid : + spec_insn_srliw_valid ? spec_insn_srliw_valid : + spec_insn_srlw_valid ? spec_insn_srlw_valid : + spec_insn_sub_valid ? spec_insn_sub_valid : + spec_insn_subw_valid ? spec_insn_subw_valid : + spec_insn_sw_valid ? spec_insn_sw_valid : + spec_insn_xor_valid ? spec_insn_xor_valid : + spec_insn_xori_valid ? spec_insn_xori_valid : 0; + assign spec_trap = + spec_insn_add_valid ? spec_insn_add_trap : + spec_insn_addi_valid ? spec_insn_addi_trap : + spec_insn_addiw_valid ? spec_insn_addiw_trap : + spec_insn_addw_valid ? spec_insn_addw_trap : + spec_insn_and_valid ? spec_insn_and_trap : + spec_insn_andi_valid ? spec_insn_andi_trap : + spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_bclr_valid ? spec_insn_bclr_trap : + spec_insn_bclri_valid ? spec_insn_bclri_trap : + spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bext_valid ? spec_insn_bext_trap : + spec_insn_bexti_valid ? spec_insn_bexti_trap : + spec_insn_bge_valid ? spec_insn_bge_trap : + spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_binv_valid ? spec_insn_binv_trap : + spec_insn_binvi_valid ? spec_insn_binvi_trap : + spec_insn_blt_valid ? spec_insn_blt_trap : + spec_insn_bltu_valid ? spec_insn_bltu_trap : + spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_bset_valid ? spec_insn_bset_trap : + spec_insn_bseti_valid ? spec_insn_bseti_trap : + spec_insn_jal_valid ? spec_insn_jal_trap : + spec_insn_jalr_valid ? spec_insn_jalr_trap : + spec_insn_lb_valid ? spec_insn_lb_trap : + spec_insn_lbu_valid ? spec_insn_lbu_trap : + spec_insn_ld_valid ? spec_insn_ld_trap : + spec_insn_lh_valid ? spec_insn_lh_trap : + spec_insn_lhu_valid ? spec_insn_lhu_trap : + spec_insn_lui_valid ? spec_insn_lui_trap : + spec_insn_lw_valid ? spec_insn_lw_trap : + spec_insn_lwu_valid ? spec_insn_lwu_trap : + spec_insn_or_valid ? spec_insn_or_trap : + spec_insn_ori_valid ? spec_insn_ori_trap : + spec_insn_sb_valid ? spec_insn_sb_trap : + spec_insn_sd_valid ? spec_insn_sd_trap : + spec_insn_sh_valid ? spec_insn_sh_trap : + spec_insn_sll_valid ? spec_insn_sll_trap : + spec_insn_slli_valid ? spec_insn_slli_trap : + spec_insn_slliw_valid ? spec_insn_slliw_trap : + spec_insn_sllw_valid ? spec_insn_sllw_trap : + spec_insn_slt_valid ? spec_insn_slt_trap : + spec_insn_slti_valid ? spec_insn_slti_trap : + spec_insn_sltiu_valid ? spec_insn_sltiu_trap : + spec_insn_sltu_valid ? spec_insn_sltu_trap : + spec_insn_sra_valid ? spec_insn_sra_trap : + spec_insn_srai_valid ? spec_insn_srai_trap : + spec_insn_sraiw_valid ? spec_insn_sraiw_trap : + spec_insn_sraw_valid ? spec_insn_sraw_trap : + spec_insn_srl_valid ? spec_insn_srl_trap : + spec_insn_srli_valid ? spec_insn_srli_trap : + spec_insn_srliw_valid ? spec_insn_srliw_trap : + spec_insn_srlw_valid ? spec_insn_srlw_trap : + spec_insn_sub_valid ? spec_insn_sub_trap : + spec_insn_subw_valid ? spec_insn_subw_trap : + spec_insn_sw_valid ? spec_insn_sw_trap : + spec_insn_xor_valid ? spec_insn_xor_trap : + spec_insn_xori_valid ? spec_insn_xori_trap : 0; + assign spec_rs1_addr = + spec_insn_add_valid ? spec_insn_add_rs1_addr : + spec_insn_addi_valid ? spec_insn_addi_rs1_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : + spec_insn_addw_valid ? spec_insn_addw_rs1_addr : + spec_insn_and_valid ? spec_insn_and_rs1_addr : + spec_insn_andi_valid ? spec_insn_andi_rs1_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs1_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs1_addr : + spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bext_valid ? spec_insn_bext_rs1_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs1_addr : + spec_insn_bge_valid ? spec_insn_bge_rs1_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_binv_valid ? spec_insn_binv_rs1_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs1_addr : + spec_insn_blt_valid ? spec_insn_blt_rs1_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : + spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_bset_valid ? spec_insn_bset_rs1_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs1_addr : + spec_insn_jal_valid ? spec_insn_jal_rs1_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : + spec_insn_lb_valid ? spec_insn_lb_rs1_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : + spec_insn_ld_valid ? spec_insn_ld_rs1_addr : + spec_insn_lh_valid ? spec_insn_lh_rs1_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : + spec_insn_lui_valid ? spec_insn_lui_rs1_addr : + spec_insn_lw_valid ? spec_insn_lw_rs1_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : + spec_insn_or_valid ? spec_insn_or_rs1_addr : + spec_insn_ori_valid ? spec_insn_ori_rs1_addr : + spec_insn_sb_valid ? spec_insn_sb_rs1_addr : + spec_insn_sd_valid ? spec_insn_sd_rs1_addr : + spec_insn_sh_valid ? spec_insn_sh_rs1_addr : + spec_insn_sll_valid ? spec_insn_sll_rs1_addr : + spec_insn_slli_valid ? spec_insn_slli_rs1_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : + spec_insn_slt_valid ? spec_insn_slt_rs1_addr : + spec_insn_slti_valid ? spec_insn_slti_rs1_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : + spec_insn_sra_valid ? spec_insn_sra_rs1_addr : + spec_insn_srai_valid ? spec_insn_srai_rs1_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : + spec_insn_srl_valid ? spec_insn_srl_rs1_addr : + spec_insn_srli_valid ? spec_insn_srli_rs1_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : + spec_insn_sub_valid ? spec_insn_sub_rs1_addr : + spec_insn_subw_valid ? spec_insn_subw_rs1_addr : + spec_insn_sw_valid ? spec_insn_sw_rs1_addr : + spec_insn_xor_valid ? spec_insn_xor_rs1_addr : + spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; + assign spec_rs2_addr = + spec_insn_add_valid ? spec_insn_add_rs2_addr : + spec_insn_addi_valid ? spec_insn_addi_rs2_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : + spec_insn_addw_valid ? spec_insn_addw_rs2_addr : + spec_insn_and_valid ? spec_insn_and_rs2_addr : + spec_insn_andi_valid ? spec_insn_andi_rs2_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs2_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs2_addr : + spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bext_valid ? spec_insn_bext_rs2_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs2_addr : + spec_insn_bge_valid ? spec_insn_bge_rs2_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_binv_valid ? spec_insn_binv_rs2_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs2_addr : + spec_insn_blt_valid ? spec_insn_blt_rs2_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : + spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_bset_valid ? spec_insn_bset_rs2_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs2_addr : + spec_insn_jal_valid ? spec_insn_jal_rs2_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : + spec_insn_lb_valid ? spec_insn_lb_rs2_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : + spec_insn_ld_valid ? spec_insn_ld_rs2_addr : + spec_insn_lh_valid ? spec_insn_lh_rs2_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : + spec_insn_lui_valid ? spec_insn_lui_rs2_addr : + spec_insn_lw_valid ? spec_insn_lw_rs2_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : + spec_insn_or_valid ? spec_insn_or_rs2_addr : + spec_insn_ori_valid ? spec_insn_ori_rs2_addr : + spec_insn_sb_valid ? spec_insn_sb_rs2_addr : + spec_insn_sd_valid ? spec_insn_sd_rs2_addr : + spec_insn_sh_valid ? spec_insn_sh_rs2_addr : + spec_insn_sll_valid ? spec_insn_sll_rs2_addr : + spec_insn_slli_valid ? spec_insn_slli_rs2_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : + spec_insn_slt_valid ? spec_insn_slt_rs2_addr : + spec_insn_slti_valid ? spec_insn_slti_rs2_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : + spec_insn_sra_valid ? spec_insn_sra_rs2_addr : + spec_insn_srai_valid ? spec_insn_srai_rs2_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : + spec_insn_srl_valid ? spec_insn_srl_rs2_addr : + spec_insn_srli_valid ? spec_insn_srli_rs2_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : + spec_insn_sub_valid ? spec_insn_sub_rs2_addr : + spec_insn_subw_valid ? spec_insn_subw_rs2_addr : + spec_insn_sw_valid ? spec_insn_sw_rs2_addr : + spec_insn_xor_valid ? spec_insn_xor_rs2_addr : + spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; + assign spec_rd_addr = + spec_insn_add_valid ? spec_insn_add_rd_addr : + spec_insn_addi_valid ? spec_insn_addi_rd_addr : + spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : + spec_insn_addw_valid ? spec_insn_addw_rd_addr : + spec_insn_and_valid ? spec_insn_and_rd_addr : + spec_insn_andi_valid ? spec_insn_andi_rd_addr : + spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rd_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rd_addr : + spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bext_valid ? spec_insn_bext_rd_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rd_addr : + spec_insn_bge_valid ? spec_insn_bge_rd_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_binv_valid ? spec_insn_binv_rd_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rd_addr : + spec_insn_blt_valid ? spec_insn_blt_rd_addr : + spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : + spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_bset_valid ? spec_insn_bset_rd_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rd_addr : + spec_insn_jal_valid ? spec_insn_jal_rd_addr : + spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : + spec_insn_lb_valid ? spec_insn_lb_rd_addr : + spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : + spec_insn_ld_valid ? spec_insn_ld_rd_addr : + spec_insn_lh_valid ? spec_insn_lh_rd_addr : + spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : + spec_insn_lui_valid ? spec_insn_lui_rd_addr : + spec_insn_lw_valid ? spec_insn_lw_rd_addr : + spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : + spec_insn_or_valid ? spec_insn_or_rd_addr : + spec_insn_ori_valid ? spec_insn_ori_rd_addr : + spec_insn_sb_valid ? spec_insn_sb_rd_addr : + spec_insn_sd_valid ? spec_insn_sd_rd_addr : + spec_insn_sh_valid ? spec_insn_sh_rd_addr : + spec_insn_sll_valid ? spec_insn_sll_rd_addr : + spec_insn_slli_valid ? spec_insn_slli_rd_addr : + spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : + spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : + spec_insn_slt_valid ? spec_insn_slt_rd_addr : + spec_insn_slti_valid ? spec_insn_slti_rd_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : + spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : + spec_insn_sra_valid ? spec_insn_sra_rd_addr : + spec_insn_srai_valid ? spec_insn_srai_rd_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : + spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : + spec_insn_srl_valid ? spec_insn_srl_rd_addr : + spec_insn_srli_valid ? spec_insn_srli_rd_addr : + spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : + spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : + spec_insn_sub_valid ? spec_insn_sub_rd_addr : + spec_insn_subw_valid ? spec_insn_subw_rd_addr : + spec_insn_sw_valid ? spec_insn_sw_rd_addr : + spec_insn_xor_valid ? spec_insn_xor_rd_addr : + spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; + assign spec_rd_wdata = + spec_insn_add_valid ? spec_insn_add_rd_wdata : + spec_insn_addi_valid ? spec_insn_addi_rd_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : + spec_insn_addw_valid ? spec_insn_addw_rd_wdata : + spec_insn_and_valid ? spec_insn_and_rd_wdata : + spec_insn_andi_valid ? spec_insn_andi_rd_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_rd_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_rd_wdata : + spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bext_valid ? spec_insn_bext_rd_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_rd_wdata : + spec_insn_bge_valid ? spec_insn_bge_rd_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_binv_valid ? spec_insn_binv_rd_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_rd_wdata : + spec_insn_blt_valid ? spec_insn_blt_rd_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : + spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_bset_valid ? spec_insn_bset_rd_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_rd_wdata : + spec_insn_jal_valid ? spec_insn_jal_rd_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : + spec_insn_lb_valid ? spec_insn_lb_rd_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : + spec_insn_ld_valid ? spec_insn_ld_rd_wdata : + spec_insn_lh_valid ? spec_insn_lh_rd_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : + spec_insn_lui_valid ? spec_insn_lui_rd_wdata : + spec_insn_lw_valid ? spec_insn_lw_rd_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : + spec_insn_or_valid ? spec_insn_or_rd_wdata : + spec_insn_ori_valid ? spec_insn_ori_rd_wdata : + spec_insn_sb_valid ? spec_insn_sb_rd_wdata : + spec_insn_sd_valid ? spec_insn_sd_rd_wdata : + spec_insn_sh_valid ? spec_insn_sh_rd_wdata : + spec_insn_sll_valid ? spec_insn_sll_rd_wdata : + spec_insn_slli_valid ? spec_insn_slli_rd_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : + spec_insn_slt_valid ? spec_insn_slt_rd_wdata : + spec_insn_slti_valid ? spec_insn_slti_rd_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : + spec_insn_sra_valid ? spec_insn_sra_rd_wdata : + spec_insn_srai_valid ? spec_insn_srai_rd_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : + spec_insn_srl_valid ? spec_insn_srl_rd_wdata : + spec_insn_srli_valid ? spec_insn_srli_rd_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : + spec_insn_sub_valid ? spec_insn_sub_rd_wdata : + spec_insn_subw_valid ? spec_insn_subw_rd_wdata : + spec_insn_sw_valid ? spec_insn_sw_rd_wdata : + spec_insn_xor_valid ? spec_insn_xor_rd_wdata : + spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; + assign spec_pc_wdata = + spec_insn_add_valid ? spec_insn_add_pc_wdata : + spec_insn_addi_valid ? spec_insn_addi_pc_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : + spec_insn_addw_valid ? spec_insn_addw_pc_wdata : + spec_insn_and_valid ? spec_insn_and_pc_wdata : + spec_insn_andi_valid ? spec_insn_andi_pc_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_pc_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_pc_wdata : + spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bext_valid ? spec_insn_bext_pc_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_pc_wdata : + spec_insn_bge_valid ? spec_insn_bge_pc_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_binv_valid ? spec_insn_binv_pc_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_pc_wdata : + spec_insn_blt_valid ? spec_insn_blt_pc_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : + spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_bset_valid ? spec_insn_bset_pc_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_pc_wdata : + spec_insn_jal_valid ? spec_insn_jal_pc_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : + spec_insn_lb_valid ? spec_insn_lb_pc_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : + spec_insn_ld_valid ? spec_insn_ld_pc_wdata : + spec_insn_lh_valid ? spec_insn_lh_pc_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : + spec_insn_lui_valid ? spec_insn_lui_pc_wdata : + spec_insn_lw_valid ? spec_insn_lw_pc_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : + spec_insn_or_valid ? spec_insn_or_pc_wdata : + spec_insn_ori_valid ? spec_insn_ori_pc_wdata : + spec_insn_sb_valid ? spec_insn_sb_pc_wdata : + spec_insn_sd_valid ? spec_insn_sd_pc_wdata : + spec_insn_sh_valid ? spec_insn_sh_pc_wdata : + spec_insn_sll_valid ? spec_insn_sll_pc_wdata : + spec_insn_slli_valid ? spec_insn_slli_pc_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : + spec_insn_slt_valid ? spec_insn_slt_pc_wdata : + spec_insn_slti_valid ? spec_insn_slti_pc_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : + spec_insn_sra_valid ? spec_insn_sra_pc_wdata : + spec_insn_srai_valid ? spec_insn_srai_pc_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : + spec_insn_srl_valid ? spec_insn_srl_pc_wdata : + spec_insn_srli_valid ? spec_insn_srli_pc_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : + spec_insn_sub_valid ? spec_insn_sub_pc_wdata : + spec_insn_subw_valid ? spec_insn_subw_pc_wdata : + spec_insn_sw_valid ? spec_insn_sw_pc_wdata : + spec_insn_xor_valid ? spec_insn_xor_pc_wdata : + spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; + assign spec_mem_addr = + spec_insn_add_valid ? spec_insn_add_mem_addr : + spec_insn_addi_valid ? spec_insn_addi_mem_addr : + spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : + spec_insn_addw_valid ? spec_insn_addw_mem_addr : + spec_insn_and_valid ? spec_insn_and_mem_addr : + spec_insn_andi_valid ? spec_insn_andi_mem_addr : + spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_bclr_valid ? spec_insn_bclr_mem_addr : + spec_insn_bclri_valid ? spec_insn_bclri_mem_addr : + spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bext_valid ? spec_insn_bext_mem_addr : + spec_insn_bexti_valid ? spec_insn_bexti_mem_addr : + spec_insn_bge_valid ? spec_insn_bge_mem_addr : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_binv_valid ? spec_insn_binv_mem_addr : + spec_insn_binvi_valid ? spec_insn_binvi_mem_addr : + spec_insn_blt_valid ? spec_insn_blt_mem_addr : + spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : + spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_bset_valid ? spec_insn_bset_mem_addr : + spec_insn_bseti_valid ? spec_insn_bseti_mem_addr : + spec_insn_jal_valid ? spec_insn_jal_mem_addr : + spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : + spec_insn_lb_valid ? spec_insn_lb_mem_addr : + spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : + spec_insn_ld_valid ? spec_insn_ld_mem_addr : + spec_insn_lh_valid ? spec_insn_lh_mem_addr : + spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : + spec_insn_lui_valid ? spec_insn_lui_mem_addr : + spec_insn_lw_valid ? spec_insn_lw_mem_addr : + spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : + spec_insn_or_valid ? spec_insn_or_mem_addr : + spec_insn_ori_valid ? spec_insn_ori_mem_addr : + spec_insn_sb_valid ? spec_insn_sb_mem_addr : + spec_insn_sd_valid ? spec_insn_sd_mem_addr : + spec_insn_sh_valid ? spec_insn_sh_mem_addr : + spec_insn_sll_valid ? spec_insn_sll_mem_addr : + spec_insn_slli_valid ? spec_insn_slli_mem_addr : + spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : + spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : + spec_insn_slt_valid ? spec_insn_slt_mem_addr : + spec_insn_slti_valid ? spec_insn_slti_mem_addr : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : + spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : + spec_insn_sra_valid ? spec_insn_sra_mem_addr : + spec_insn_srai_valid ? spec_insn_srai_mem_addr : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : + spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : + spec_insn_srl_valid ? spec_insn_srl_mem_addr : + spec_insn_srli_valid ? spec_insn_srli_mem_addr : + spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : + spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : + spec_insn_sub_valid ? spec_insn_sub_mem_addr : + spec_insn_subw_valid ? spec_insn_subw_mem_addr : + spec_insn_sw_valid ? spec_insn_sw_mem_addr : + spec_insn_xor_valid ? spec_insn_xor_mem_addr : + spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; + assign spec_mem_rmask = + spec_insn_add_valid ? spec_insn_add_mem_rmask : + spec_insn_addi_valid ? spec_insn_addi_mem_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : + spec_insn_addw_valid ? spec_insn_addw_mem_rmask : + spec_insn_and_valid ? spec_insn_and_mem_rmask : + spec_insn_andi_valid ? spec_insn_andi_mem_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_rmask : + spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bext_valid ? spec_insn_bext_mem_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_rmask : + spec_insn_bge_valid ? spec_insn_bge_mem_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_binv_valid ? spec_insn_binv_mem_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_rmask : + spec_insn_blt_valid ? spec_insn_blt_mem_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : + spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_bset_valid ? spec_insn_bset_mem_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_rmask : + spec_insn_jal_valid ? spec_insn_jal_mem_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : + spec_insn_lb_valid ? spec_insn_lb_mem_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : + spec_insn_ld_valid ? spec_insn_ld_mem_rmask : + spec_insn_lh_valid ? spec_insn_lh_mem_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : + spec_insn_lui_valid ? spec_insn_lui_mem_rmask : + spec_insn_lw_valid ? spec_insn_lw_mem_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : + spec_insn_or_valid ? spec_insn_or_mem_rmask : + spec_insn_ori_valid ? spec_insn_ori_mem_rmask : + spec_insn_sb_valid ? spec_insn_sb_mem_rmask : + spec_insn_sd_valid ? spec_insn_sd_mem_rmask : + spec_insn_sh_valid ? spec_insn_sh_mem_rmask : + spec_insn_sll_valid ? spec_insn_sll_mem_rmask : + spec_insn_slli_valid ? spec_insn_slli_mem_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : + spec_insn_slt_valid ? spec_insn_slt_mem_rmask : + spec_insn_slti_valid ? spec_insn_slti_mem_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : + spec_insn_sra_valid ? spec_insn_sra_mem_rmask : + spec_insn_srai_valid ? spec_insn_srai_mem_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : + spec_insn_srl_valid ? spec_insn_srl_mem_rmask : + spec_insn_srli_valid ? spec_insn_srli_mem_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : + spec_insn_sub_valid ? spec_insn_sub_mem_rmask : + spec_insn_subw_valid ? spec_insn_subw_mem_rmask : + spec_insn_sw_valid ? spec_insn_sw_mem_rmask : + spec_insn_xor_valid ? spec_insn_xor_mem_rmask : + spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; + assign spec_mem_wmask = + spec_insn_add_valid ? spec_insn_add_mem_wmask : + spec_insn_addi_valid ? spec_insn_addi_mem_wmask : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : + spec_insn_addw_valid ? spec_insn_addw_mem_wmask : + spec_insn_and_valid ? spec_insn_and_mem_wmask : + spec_insn_andi_valid ? spec_insn_andi_mem_wmask : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wmask : + spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bext_valid ? spec_insn_bext_mem_wmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wmask : + spec_insn_bge_valid ? spec_insn_bge_mem_wmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_binv_valid ? spec_insn_binv_mem_wmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wmask : + spec_insn_blt_valid ? spec_insn_blt_mem_wmask : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : + spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_bset_valid ? spec_insn_bset_mem_wmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wmask : + spec_insn_jal_valid ? spec_insn_jal_mem_wmask : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : + spec_insn_lb_valid ? spec_insn_lb_mem_wmask : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : + spec_insn_ld_valid ? spec_insn_ld_mem_wmask : + spec_insn_lh_valid ? spec_insn_lh_mem_wmask : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : + spec_insn_lui_valid ? spec_insn_lui_mem_wmask : + spec_insn_lw_valid ? spec_insn_lw_mem_wmask : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : + spec_insn_or_valid ? spec_insn_or_mem_wmask : + spec_insn_ori_valid ? spec_insn_ori_mem_wmask : + spec_insn_sb_valid ? spec_insn_sb_mem_wmask : + spec_insn_sd_valid ? spec_insn_sd_mem_wmask : + spec_insn_sh_valid ? spec_insn_sh_mem_wmask : + spec_insn_sll_valid ? spec_insn_sll_mem_wmask : + spec_insn_slli_valid ? spec_insn_slli_mem_wmask : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : + spec_insn_slt_valid ? spec_insn_slt_mem_wmask : + spec_insn_slti_valid ? spec_insn_slti_mem_wmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : + spec_insn_sra_valid ? spec_insn_sra_mem_wmask : + spec_insn_srai_valid ? spec_insn_srai_mem_wmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : + spec_insn_srl_valid ? spec_insn_srl_mem_wmask : + spec_insn_srli_valid ? spec_insn_srli_mem_wmask : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : + spec_insn_sub_valid ? spec_insn_sub_mem_wmask : + spec_insn_subw_valid ? spec_insn_subw_mem_wmask : + spec_insn_sw_valid ? spec_insn_sw_mem_wmask : + spec_insn_xor_valid ? spec_insn_xor_mem_wmask : + spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; + assign spec_mem_wdata = + spec_insn_add_valid ? spec_insn_add_mem_wdata : + spec_insn_addi_valid ? spec_insn_addi_mem_wdata : + spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : + spec_insn_addw_valid ? spec_insn_addw_mem_wdata : + spec_insn_and_valid ? spec_insn_and_mem_wdata : + spec_insn_andi_valid ? spec_insn_andi_mem_wdata : + spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wdata : + spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bext_valid ? spec_insn_bext_mem_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wdata : + spec_insn_bge_valid ? spec_insn_bge_mem_wdata : + spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_binv_valid ? spec_insn_binv_mem_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wdata : + spec_insn_blt_valid ? spec_insn_blt_mem_wdata : + spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : + spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_bset_valid ? spec_insn_bset_mem_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wdata : + spec_insn_jal_valid ? spec_insn_jal_mem_wdata : + spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : + spec_insn_lb_valid ? spec_insn_lb_mem_wdata : + spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : + spec_insn_ld_valid ? spec_insn_ld_mem_wdata : + spec_insn_lh_valid ? spec_insn_lh_mem_wdata : + spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : + spec_insn_lui_valid ? spec_insn_lui_mem_wdata : + spec_insn_lw_valid ? spec_insn_lw_mem_wdata : + spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : + spec_insn_or_valid ? spec_insn_or_mem_wdata : + spec_insn_ori_valid ? spec_insn_ori_mem_wdata : + spec_insn_sb_valid ? spec_insn_sb_mem_wdata : + spec_insn_sd_valid ? spec_insn_sd_mem_wdata : + spec_insn_sh_valid ? spec_insn_sh_mem_wdata : + spec_insn_sll_valid ? spec_insn_sll_mem_wdata : + spec_insn_slli_valid ? spec_insn_slli_mem_wdata : + spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : + spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : + spec_insn_slt_valid ? spec_insn_slt_mem_wdata : + spec_insn_slti_valid ? spec_insn_slti_mem_wdata : + spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : + spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : + spec_insn_sra_valid ? spec_insn_sra_mem_wdata : + spec_insn_srai_valid ? spec_insn_srai_mem_wdata : + spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : + spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : + spec_insn_srl_valid ? spec_insn_srl_mem_wdata : + spec_insn_srli_valid ? spec_insn_srli_mem_wdata : + spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : + spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : + spec_insn_sub_valid ? spec_insn_sub_mem_wdata : + spec_insn_subw_valid ? spec_insn_subw_mem_wdata : + spec_insn_sw_valid ? spec_insn_sw_mem_wdata : + spec_insn_xor_valid ? spec_insn_xor_mem_wdata : + spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; +`ifdef RISCV_FORMAL_CSR_MISA + assign spec_csr_misa_rmask = + spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : + spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : + spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : + spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : + spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : + spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : + spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_csr_misa_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_csr_misa_rmask : + spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bext_valid ? spec_insn_bext_csr_misa_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_csr_misa_rmask : + spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : + spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_binv_valid ? spec_insn_binv_csr_misa_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_csr_misa_rmask : + spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : + spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : + spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_bset_valid ? spec_insn_bset_csr_misa_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_csr_misa_rmask : + spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : + spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : + spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : + spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : + spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : + spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : + spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : + spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : + spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : + spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : + spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : + spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : + spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : + spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : + spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : + spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : + spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : + spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : + spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : + spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : + spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : + spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : + spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : + spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : + spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : + spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : + spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : + spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : + spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : + spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : + spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : + spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : + spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : + spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : + spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : + spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; +`endif +endmodule diff --git a/insns/isa_rv64ib.txt b/insns/isa_rv64ib.txt index 12fd7059..cf468596 100644 --- a/insns/isa_rv64ib.txt +++ b/insns/isa_rv64ib.txt @@ -7,12 +7,20 @@ and andi andn auipc +bclr +bclri beq +bext +bexti bge bgeu +binv +binvi blt bltu bne +bset +bseti clz clzw cpop diff --git a/insns/isa_rv64ib.v b/insns/isa_rv64ib.v index c3ab8e10..607a75f9 100644 --- a/insns/isa_rv64ib.v +++ b/insns/isa_rv64ib.v @@ -375,6 +375,84 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); + wire spec_insn_bclr_valid; + wire spec_insn_bclr_trap; + wire [ 4 : 0] spec_insn_bclr_rs1_addr; + wire [ 4 : 0] spec_insn_bclr_rs2_addr; + wire [ 4 : 0] spec_insn_bclr_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclr_csr_misa_rmask; +`endif + + rvfi_insn_bclr insn_bclr ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclr_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclr_valid), + .spec_trap(spec_insn_bclr_trap), + .spec_rs1_addr(spec_insn_bclr_rs1_addr), + .spec_rs2_addr(spec_insn_bclr_rs2_addr), + .spec_rd_addr(spec_insn_bclr_rd_addr), + .spec_rd_wdata(spec_insn_bclr_rd_wdata), + .spec_pc_wdata(spec_insn_bclr_pc_wdata), + .spec_mem_addr(spec_insn_bclr_mem_addr), + .spec_mem_rmask(spec_insn_bclr_mem_rmask), + .spec_mem_wmask(spec_insn_bclr_mem_wmask), + .spec_mem_wdata(spec_insn_bclr_mem_wdata) + ); + + wire spec_insn_bclri_valid; + wire spec_insn_bclri_trap; + wire [ 4 : 0] spec_insn_bclri_rs1_addr; + wire [ 4 : 0] spec_insn_bclri_rs2_addr; + wire [ 4 : 0] spec_insn_bclri_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bclri_csr_misa_rmask; +`endif + + rvfi_insn_bclri insn_bclri ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bclri_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bclri_valid), + .spec_trap(spec_insn_bclri_trap), + .spec_rs1_addr(spec_insn_bclri_rs1_addr), + .spec_rs2_addr(spec_insn_bclri_rs2_addr), + .spec_rd_addr(spec_insn_bclri_rd_addr), + .spec_rd_wdata(spec_insn_bclri_rd_wdata), + .spec_pc_wdata(spec_insn_bclri_pc_wdata), + .spec_mem_addr(spec_insn_bclri_mem_addr), + .spec_mem_rmask(spec_insn_bclri_mem_rmask), + .spec_mem_wmask(spec_insn_bclri_mem_wmask), + .spec_mem_wdata(spec_insn_bclri_mem_wdata) + ); + wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; @@ -414,6 +492,84 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_beq_mem_wdata) ); + wire spec_insn_bext_valid; + wire spec_insn_bext_trap; + wire [ 4 : 0] spec_insn_bext_rs1_addr; + wire [ 4 : 0] spec_insn_bext_rs2_addr; + wire [ 4 : 0] spec_insn_bext_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bext_csr_misa_rmask; +`endif + + rvfi_insn_bext insn_bext ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bext_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bext_valid), + .spec_trap(spec_insn_bext_trap), + .spec_rs1_addr(spec_insn_bext_rs1_addr), + .spec_rs2_addr(spec_insn_bext_rs2_addr), + .spec_rd_addr(spec_insn_bext_rd_addr), + .spec_rd_wdata(spec_insn_bext_rd_wdata), + .spec_pc_wdata(spec_insn_bext_pc_wdata), + .spec_mem_addr(spec_insn_bext_mem_addr), + .spec_mem_rmask(spec_insn_bext_mem_rmask), + .spec_mem_wmask(spec_insn_bext_mem_wmask), + .spec_mem_wdata(spec_insn_bext_mem_wdata) + ); + + wire spec_insn_bexti_valid; + wire spec_insn_bexti_trap; + wire [ 4 : 0] spec_insn_bexti_rs1_addr; + wire [ 4 : 0] spec_insn_bexti_rs2_addr; + wire [ 4 : 0] spec_insn_bexti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bexti_csr_misa_rmask; +`endif + + rvfi_insn_bexti insn_bexti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bexti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bexti_valid), + .spec_trap(spec_insn_bexti_trap), + .spec_rs1_addr(spec_insn_bexti_rs1_addr), + .spec_rs2_addr(spec_insn_bexti_rs2_addr), + .spec_rd_addr(spec_insn_bexti_rd_addr), + .spec_rd_wdata(spec_insn_bexti_rd_wdata), + .spec_pc_wdata(spec_insn_bexti_pc_wdata), + .spec_mem_addr(spec_insn_bexti_mem_addr), + .spec_mem_rmask(spec_insn_bexti_mem_rmask), + .spec_mem_wmask(spec_insn_bexti_mem_wmask), + .spec_mem_wdata(spec_insn_bexti_mem_wdata) + ); + wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; @@ -492,6 +648,84 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); + wire spec_insn_binv_valid; + wire spec_insn_binv_trap; + wire [ 4 : 0] spec_insn_binv_rs1_addr; + wire [ 4 : 0] spec_insn_binv_rs2_addr; + wire [ 4 : 0] spec_insn_binv_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binv_csr_misa_rmask; +`endif + + rvfi_insn_binv insn_binv ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binv_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binv_valid), + .spec_trap(spec_insn_binv_trap), + .spec_rs1_addr(spec_insn_binv_rs1_addr), + .spec_rs2_addr(spec_insn_binv_rs2_addr), + .spec_rd_addr(spec_insn_binv_rd_addr), + .spec_rd_wdata(spec_insn_binv_rd_wdata), + .spec_pc_wdata(spec_insn_binv_pc_wdata), + .spec_mem_addr(spec_insn_binv_mem_addr), + .spec_mem_rmask(spec_insn_binv_mem_rmask), + .spec_mem_wmask(spec_insn_binv_mem_wmask), + .spec_mem_wdata(spec_insn_binv_mem_wdata) + ); + + wire spec_insn_binvi_valid; + wire spec_insn_binvi_trap; + wire [ 4 : 0] spec_insn_binvi_rs1_addr; + wire [ 4 : 0] spec_insn_binvi_rs2_addr; + wire [ 4 : 0] spec_insn_binvi_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_binvi_csr_misa_rmask; +`endif + + rvfi_insn_binvi insn_binvi ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_binvi_csr_misa_rmask), +`endif + .spec_valid(spec_insn_binvi_valid), + .spec_trap(spec_insn_binvi_trap), + .spec_rs1_addr(spec_insn_binvi_rs1_addr), + .spec_rs2_addr(spec_insn_binvi_rs2_addr), + .spec_rd_addr(spec_insn_binvi_rd_addr), + .spec_rd_wdata(spec_insn_binvi_rd_wdata), + .spec_pc_wdata(spec_insn_binvi_pc_wdata), + .spec_mem_addr(spec_insn_binvi_mem_addr), + .spec_mem_rmask(spec_insn_binvi_mem_rmask), + .spec_mem_wmask(spec_insn_binvi_mem_wmask), + .spec_mem_wdata(spec_insn_binvi_mem_wdata) + ); + wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; @@ -609,6 +843,84 @@ module rvfi_isa_rv64ib ( .spec_mem_wdata(spec_insn_bne_mem_wdata) ); + wire spec_insn_bset_valid; + wire spec_insn_bset_trap; + wire [ 4 : 0] spec_insn_bset_rs1_addr; + wire [ 4 : 0] spec_insn_bset_rs2_addr; + wire [ 4 : 0] spec_insn_bset_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bset_csr_misa_rmask; +`endif + + rvfi_insn_bset insn_bset ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bset_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bset_valid), + .spec_trap(spec_insn_bset_trap), + .spec_rs1_addr(spec_insn_bset_rs1_addr), + .spec_rs2_addr(spec_insn_bset_rs2_addr), + .spec_rd_addr(spec_insn_bset_rd_addr), + .spec_rd_wdata(spec_insn_bset_rd_wdata), + .spec_pc_wdata(spec_insn_bset_pc_wdata), + .spec_mem_addr(spec_insn_bset_mem_addr), + .spec_mem_rmask(spec_insn_bset_mem_rmask), + .spec_mem_wmask(spec_insn_bset_mem_wmask), + .spec_mem_wdata(spec_insn_bset_mem_wdata) + ); + + wire spec_insn_bseti_valid; + wire spec_insn_bseti_trap; + wire [ 4 : 0] spec_insn_bseti_rs1_addr; + wire [ 4 : 0] spec_insn_bseti_rs2_addr; + wire [ 4 : 0] spec_insn_bseti_rd_addr; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_rd_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_pc_wdata; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_addr; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_rmask; + wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_wmask; + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_mem_wdata; +`ifdef RISCV_FORMAL_CSR_MISA + wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bseti_csr_misa_rmask; +`endif + + rvfi_insn_bseti insn_bseti ( + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_mem_rdata(rvfi_mem_rdata), +`ifdef RISCV_FORMAL_CSR_MISA + .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), + .spec_csr_misa_rmask(spec_insn_bseti_csr_misa_rmask), +`endif + .spec_valid(spec_insn_bseti_valid), + .spec_trap(spec_insn_bseti_trap), + .spec_rs1_addr(spec_insn_bseti_rs1_addr), + .spec_rs2_addr(spec_insn_bseti_rs2_addr), + .spec_rd_addr(spec_insn_bseti_rd_addr), + .spec_rd_wdata(spec_insn_bseti_rd_wdata), + .spec_pc_wdata(spec_insn_bseti_pc_wdata), + .spec_mem_addr(spec_insn_bseti_mem_addr), + .spec_mem_rmask(spec_insn_bseti_mem_rmask), + .spec_mem_wmask(spec_insn_bseti_mem_wmask), + .spec_mem_wdata(spec_insn_bseti_mem_wdata) + ); + wire spec_insn_clz_valid; wire spec_insn_clz_trap; wire [ 4 : 0] spec_insn_clz_rs1_addr; @@ -3115,12 +3427,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_andn_valid ? spec_insn_andn_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : + spec_insn_bclr_valid ? spec_insn_bclr_valid : + spec_insn_bclri_valid ? spec_insn_bclri_valid : spec_insn_beq_valid ? spec_insn_beq_valid : + spec_insn_bext_valid ? spec_insn_bext_valid : + spec_insn_bexti_valid ? spec_insn_bexti_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : + spec_insn_binv_valid ? spec_insn_binv_valid : + spec_insn_binvi_valid ? spec_insn_binvi_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : + spec_insn_bset_valid ? spec_insn_bset_valid : + spec_insn_bseti_valid ? spec_insn_bseti_valid : spec_insn_clz_valid ? spec_insn_clz_valid : spec_insn_clzw_valid ? spec_insn_clzw_valid : spec_insn_cpop_valid ? spec_insn_cpop_valid : @@ -3195,12 +3515,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_andn_valid ? spec_insn_andn_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : + spec_insn_bclr_valid ? spec_insn_bclr_trap : + spec_insn_bclri_valid ? spec_insn_bclri_trap : spec_insn_beq_valid ? spec_insn_beq_trap : + spec_insn_bext_valid ? spec_insn_bext_trap : + spec_insn_bexti_valid ? spec_insn_bexti_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : + spec_insn_binv_valid ? spec_insn_binv_trap : + spec_insn_binvi_valid ? spec_insn_binvi_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : + spec_insn_bset_valid ? spec_insn_bset_trap : + spec_insn_bseti_valid ? spec_insn_bseti_trap : spec_insn_clz_valid ? spec_insn_clz_trap : spec_insn_clzw_valid ? spec_insn_clzw_trap : spec_insn_cpop_valid ? spec_insn_cpop_trap : @@ -3275,12 +3603,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_andn_valid ? spec_insn_andn_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs1_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : + spec_insn_bext_valid ? spec_insn_bext_rs1_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : + spec_insn_binv_valid ? spec_insn_binv_rs1_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : + spec_insn_bset_valid ? spec_insn_bset_rs1_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs1_addr : spec_insn_clz_valid ? spec_insn_clz_rs1_addr : spec_insn_clzw_valid ? spec_insn_clzw_rs1_addr : spec_insn_cpop_valid ? spec_insn_cpop_rs1_addr : @@ -3355,12 +3691,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_andn_valid ? spec_insn_andn_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rs2_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : + spec_insn_bext_valid ? spec_insn_bext_rs2_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : + spec_insn_binv_valid ? spec_insn_binv_rs2_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : + spec_insn_bset_valid ? spec_insn_bset_rs2_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rs2_addr : spec_insn_clz_valid ? spec_insn_clz_rs2_addr : spec_insn_clzw_valid ? spec_insn_clzw_rs2_addr : spec_insn_cpop_valid ? spec_insn_cpop_rs2_addr : @@ -3435,12 +3779,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_andn_valid ? spec_insn_andn_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : + spec_insn_bclr_valid ? spec_insn_bclr_rd_addr : + spec_insn_bclri_valid ? spec_insn_bclri_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : + spec_insn_bext_valid ? spec_insn_bext_rd_addr : + spec_insn_bexti_valid ? spec_insn_bexti_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : + spec_insn_binv_valid ? spec_insn_binv_rd_addr : + spec_insn_binvi_valid ? spec_insn_binvi_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : + spec_insn_bset_valid ? spec_insn_bset_rd_addr : + spec_insn_bseti_valid ? spec_insn_bseti_rd_addr : spec_insn_clz_valid ? spec_insn_clz_rd_addr : spec_insn_clzw_valid ? spec_insn_clzw_rd_addr : spec_insn_cpop_valid ? spec_insn_cpop_rd_addr : @@ -3515,12 +3867,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_andn_valid ? spec_insn_andn_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_rd_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : + spec_insn_bext_valid ? spec_insn_bext_rd_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : + spec_insn_binv_valid ? spec_insn_binv_rd_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : + spec_insn_bset_valid ? spec_insn_bset_rd_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_rd_wdata : spec_insn_clz_valid ? spec_insn_clz_rd_wdata : spec_insn_clzw_valid ? spec_insn_clzw_rd_wdata : spec_insn_cpop_valid ? spec_insn_cpop_rd_wdata : @@ -3595,12 +3955,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_andn_valid ? spec_insn_andn_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_pc_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : + spec_insn_bext_valid ? spec_insn_bext_pc_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : + spec_insn_binv_valid ? spec_insn_binv_pc_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : + spec_insn_bset_valid ? spec_insn_bset_pc_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_pc_wdata : spec_insn_clz_valid ? spec_insn_clz_pc_wdata : spec_insn_clzw_valid ? spec_insn_clzw_pc_wdata : spec_insn_cpop_valid ? spec_insn_cpop_pc_wdata : @@ -3675,12 +4043,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_andn_valid ? spec_insn_andn_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : + spec_insn_bclr_valid ? spec_insn_bclr_mem_addr : + spec_insn_bclri_valid ? spec_insn_bclri_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : + spec_insn_bext_valid ? spec_insn_bext_mem_addr : + spec_insn_bexti_valid ? spec_insn_bexti_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : + spec_insn_binv_valid ? spec_insn_binv_mem_addr : + spec_insn_binvi_valid ? spec_insn_binvi_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : + spec_insn_bset_valid ? spec_insn_bset_mem_addr : + spec_insn_bseti_valid ? spec_insn_bseti_mem_addr : spec_insn_clz_valid ? spec_insn_clz_mem_addr : spec_insn_clzw_valid ? spec_insn_clzw_mem_addr : spec_insn_cpop_valid ? spec_insn_cpop_mem_addr : @@ -3755,12 +4131,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_andn_valid ? spec_insn_andn_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : + spec_insn_bext_valid ? spec_insn_bext_mem_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : + spec_insn_binv_valid ? spec_insn_binv_mem_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : + spec_insn_bset_valid ? spec_insn_bset_mem_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_rmask : spec_insn_clz_valid ? spec_insn_clz_mem_rmask : spec_insn_clzw_valid ? spec_insn_clzw_mem_rmask : spec_insn_cpop_valid ? spec_insn_cpop_mem_rmask : @@ -3835,12 +4219,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_andn_valid ? spec_insn_andn_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wmask : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : + spec_insn_bext_valid ? spec_insn_bext_mem_wmask : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : + spec_insn_binv_valid ? spec_insn_binv_mem_wmask : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : + spec_insn_bset_valid ? spec_insn_bset_mem_wmask : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wmask : spec_insn_clz_valid ? spec_insn_clz_mem_wmask : spec_insn_clzw_valid ? spec_insn_clzw_mem_wmask : spec_insn_cpop_valid ? spec_insn_cpop_mem_wmask : @@ -3915,12 +4307,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_andn_valid ? spec_insn_andn_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : + spec_insn_bclr_valid ? spec_insn_bclr_mem_wdata : + spec_insn_bclri_valid ? spec_insn_bclri_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : + spec_insn_bext_valid ? spec_insn_bext_mem_wdata : + spec_insn_bexti_valid ? spec_insn_bexti_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : + spec_insn_binv_valid ? spec_insn_binv_mem_wdata : + spec_insn_binvi_valid ? spec_insn_binvi_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : + spec_insn_bset_valid ? spec_insn_bset_mem_wdata : + spec_insn_bseti_valid ? spec_insn_bseti_mem_wdata : spec_insn_clz_valid ? spec_insn_clz_mem_wdata : spec_insn_clzw_valid ? spec_insn_clzw_mem_wdata : spec_insn_cpop_valid ? spec_insn_cpop_mem_wdata : @@ -3996,12 +4396,20 @@ module rvfi_isa_rv64ib ( spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_andn_valid ? spec_insn_andn_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : + spec_insn_bclr_valid ? spec_insn_bclr_csr_misa_rmask : + spec_insn_bclri_valid ? spec_insn_bclri_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : + spec_insn_bext_valid ? spec_insn_bext_csr_misa_rmask : + spec_insn_bexti_valid ? spec_insn_bexti_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : + spec_insn_binv_valid ? spec_insn_binv_csr_misa_rmask : + spec_insn_binvi_valid ? spec_insn_binvi_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : + spec_insn_bset_valid ? spec_insn_bset_csr_misa_rmask : + spec_insn_bseti_valid ? spec_insn_bseti_csr_misa_rmask : spec_insn_clz_valid ? spec_insn_clz_csr_misa_rmask : spec_insn_clzw_valid ? spec_insn_clzw_csr_misa_rmask : spec_insn_cpop_valid ? spec_insn_cpop_csr_misa_rmask : From beef78ceb9e25f6bf51d8fefaa3b63df6ea0c86b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 3 Oct 2024 17:35:19 +1300 Subject: [PATCH 04/11] Bug squashing b extension --- insns/generate.py | 44 +++++++++++++++++++++----------------------- insns/insn_bclr.v | 4 ++-- insns/insn_bclri.v | 6 +++--- insns/insn_bext.v | 4 ++-- insns/insn_bexti.v | 6 +++--- insns/insn_binv.v | 4 ++-- insns/insn_binvi.v | 6 +++--- insns/insn_bset.v | 4 ++-- insns/insn_bseti.v | 6 +++--- insns/insn_clz.v | 2 +- insns/insn_clzw.v | 2 +- insns/insn_cpop.v | 2 +- insns/insn_cpopw.v | 2 +- insns/insn_ctz.v | 2 +- insns/insn_ctzw.v | 2 +- insns/insn_max.v | 2 +- insns/insn_min.v | 2 +- insns/insn_rori.v | 4 ++-- insns/insn_roriw.v | 4 ++-- insns/insn_sext_b.v | 2 +- insns/insn_sext_h.v | 2 +- insns/insn_zext_h.v | 6 +++--- 22 files changed, 58 insertions(+), 60 deletions(-) diff --git a/insns/generate.py b/insns/generate.py index 122b34ca..821b53ae 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -178,7 +178,7 @@ def format_rb(f): print("", file=f) print(" // R-type instruction format (bitwise variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) - print(" wire [6:0] insn_funct7 = rvfi_insn[31:25];", file=f) + print(" wire [6:0] insn_funct6 = rvfi_insn[31:26];", file=f) print(" wire [5:0] insn_shamt = rvfi_insn[25:20];", file=f) print(" wire [4:0] insn_rs2 = rvfi_insn[24:20];", file=f) print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) @@ -1179,7 +1179,6 @@ def insn_count(insn, funct5, trailing=False, pop=False, wmode=False, misa=MISA_B assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b %s && insn_funct3 == 3'b 001 && insn_opcode == 7'b %s" % (funct5, opcode)) assign(f, "spec_rs1_addr", "insn_rs1") - assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_rd_addr", "insn_rd") if wmode: assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0") @@ -1197,28 +1196,27 @@ def insn_ext(insn, funct5, signed=False, bmode=False, misa=MISA_B): if bmode: result_width = "8" - opcode = "0011011" + opcode = "7'b 0011011" else: # hmode result_width = "16" - opcode = "0010011" + opcode = "7'b 0010011" if signed: funct7 = "0110000" funct3 = "001" - opcode = "0010011" + opcode = "7'b 0010011" result_extension = f"result[{result_width}-1]" else: funct7 = "0000100" funct3 = "100" - opcode = "{011, `RISCV_FORMAL_XLEN != 32, 011}" - result_extension = "0" + opcode = "{3'b 011, `RISCV_FORMAL_XLEN != 32, 3'b 011}" + result_extension = "1'b 0" print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [%s-1:0] result = rvfi_rs1_rdata[%s-1:0];" % (result_width, result_width), file=f) - assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct7 == 7'b %s && insn_funct5 == 5'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s" % (funct7, funct5, funct3, opcode)) + assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct7 == 7'b %s && insn_funct5 == 5'b %s && insn_funct3 == 3'b %s && insn_opcode == %s" % (funct7, funct5, funct3, opcode)) assign(f, "spec_rs1_addr", "insn_rs1") - assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-%s{%s}}, result} : 0" % (result_width, result_extension)) assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") @@ -1234,10 +1232,10 @@ def insn_bit(insn, funct6, funct3, expr, imode=False, misa=MISA_B): if imode: opcode = "0010011" xtra_shamt_check = "(!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)" - index = "shamt & (`RISCV_FORMAL_XLEN - 1)" + index = "insn_shamt & (`RISCV_FORMAL_XLEN - 1)" else: opcode = "0110011" - xtra_shamt_check = "1" + xtra_shamt_check = "!insn_shamt[5]" index = "rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1)" print("", file=f) @@ -1419,16 +1417,16 @@ def insn_bit(insn, funct6, funct3, expr, imode=False, misa=MISA_B): insn_count("clz", "00000", misa=MISA_B) insn_count("ctz", "00001", trailing=True, misa=MISA_B) insn_count("cpop", "00010", pop=True, misa=MISA_B) -insn_alu("max", "0000101", "110", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs2_rdata : rvfi_rs1_rdata", misa=MISA_B) +insn_alu("max", "0000101", "110", "($signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)) ? rvfi_rs2_rdata : rvfi_rs1_rdata", misa=MISA_B) insn_alu("maxu", "0000101", "111", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs2_rdata : rvfi_rs1_rdata", misa=MISA_B) -insn_alu("min", "0000101", "100", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs1_rdata : rvfi_rs2_rdata", misa=MISA_B) +insn_alu("min", "0000101", "100", "($signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)) ? rvfi_rs1_rdata : rvfi_rs2_rdata", misa=MISA_B) insn_alu("minu", "0000101", "101", "(rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs1_rdata : rvfi_rs2_rdata", misa=MISA_B) insn_ext("sext_b", "00100", signed=True, bmode=True, misa=MISA_B) insn_ext("sext_h", "00101", signed=True, misa=MISA_B) insn_ext("zext_h", "00000", misa=MISA_B) insn_alu("rol", "0110000", "001", "(rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) insn_alu("ror", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) -insn_shimm("rori", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt))", misa=MISA_B) +insn_shimm("rori", "011000", "101", "(rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - insn_shamt))", misa=MISA_B) # insn_("orc_b", "001010000111", "101", "", misa=MISA_B) # insn_("rev8", "011010011000", "101", "", misa=MISA_B) @@ -1439,20 +1437,20 @@ def insn_bit(insn, funct6, funct3, expr, imode=False, misa=MISA_B): insn_count("cpopw", "00010", pop=True, wmode=True, misa=MISA_B) insn_alu("rolw", "0110000", "001", "(rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) insn_alu("rorw", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) -insn_shimm("roriw", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt))", wmode=True, misa=MISA_B) +insn_shimm("roriw", "011000", "101", "(rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (32 - insn_shamt))", wmode=True, misa=MISA_B) ### Zbs: Single-bit instructions current_isa = ["rv32iZbs"] -insn_bit("bclr", "0100100", "001", "rvfi_rs1_rdata & ~(1 << index)", misa=MISA_B) -insn_bit("bclri", "0100100", "001", "rvfi_rs1_rdata & ~(1 << index)", imode=True, misa=MISA_B) -insn_bit("bext", "0100100", "101", "(rvfi_rs1_rdata >> index) & 1", misa=MISA_B) -insn_bit("bexti", "0100100", "101", "(rvfi_rs1_rdata >> index) & 1", imode=True, misa=MISA_B) -insn_bit("binv", "0110100", "001", "rvfi_rs1_rdata ^ (1 << index)", misa=MISA_B) -insn_bit("binvi", "0110100", "001", "rvfi_rs1_rdata ^ (1 << index)", imode=True, misa=MISA_B) -insn_bit("bset", "0010100", "001", "rvfi_rs1_rdata | (1 << index)", misa=MISA_B) -insn_bit("bseti", "0010100", "001", "rvfi_rs1_rdata | (1 << index)", imode=True, misa=MISA_B) +insn_bit("bclr", "010010", "001", "rvfi_rs1_rdata & ~(1 << index)", misa=MISA_B) +insn_bit("bclri", "010010", "001", "rvfi_rs1_rdata & ~(1 << index)", imode=True, misa=MISA_B) +insn_bit("bext", "010010", "101", "(rvfi_rs1_rdata >> index) & 1", misa=MISA_B) +insn_bit("bexti", "010010", "101", "(rvfi_rs1_rdata >> index) & 1", imode=True, misa=MISA_B) +insn_bit("binv", "011010", "001", "rvfi_rs1_rdata ^ (1 << index)", misa=MISA_B) +insn_bit("binvi", "011010", "001", "rvfi_rs1_rdata ^ (1 << index)", imode=True, misa=MISA_B) +insn_bit("bset", "001010", "001", "rvfi_rs1_rdata | (1 << index)", misa=MISA_B) +insn_bit("bseti", "001010", "001", "rvfi_rs1_rdata | (1 << index)", imode=True, misa=MISA_B) ## Compressed Integer ISA (IC) diff --git a/insns/insn_bclr.v b/insns/insn_bclr.v index 4a8f3f46..25d5242f 100644 --- a/insns/insn_bclr.v +++ b/insns/insn_bclr.v @@ -27,7 +27,7 @@ module rvfi_insn_bclr ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -45,7 +45,7 @@ module rvfi_insn_bclr ( // BCLR instruction wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & ~(1 << index); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && 1; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_bclri.v b/insns/insn_bclri.v index 75fe5a9c..66f77290 100644 --- a/insns/insn_bclri.v +++ b/insns/insn_bclri.v @@ -27,7 +27,7 @@ module rvfi_insn_bclri ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -43,9 +43,9 @@ module rvfi_insn_bclri ( `endif // BCLRI instruction - wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] index = insn_shamt & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & ~(1 << index); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_bext.v b/insns/insn_bext.v index 6dcbd338..5364579c 100644 --- a/insns/insn_bext.v +++ b/insns/insn_bext.v @@ -27,7 +27,7 @@ module rvfi_insn_bext ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -45,7 +45,7 @@ module rvfi_insn_bext ( // BEXT instruction wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> index) & 1; - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011 && 1; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010010 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_bexti.v b/insns/insn_bexti.v index fd7cb697..201b5ed4 100644 --- a/insns/insn_bexti.v +++ b/insns/insn_bexti.v @@ -27,7 +27,7 @@ module rvfi_insn_bexti ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -43,9 +43,9 @@ module rvfi_insn_bexti ( `endif // BEXTI instruction - wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] index = insn_shamt & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> index) & 1; - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0100100 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010010 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_binv.v b/insns/insn_binv.v index 937fdcbe..00424b36 100644 --- a/insns/insn_binv.v +++ b/insns/insn_binv.v @@ -27,7 +27,7 @@ module rvfi_insn_binv ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -45,7 +45,7 @@ module rvfi_insn_binv ( // BINV instruction wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ (1 << index); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && 1; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 011010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_binvi.v b/insns/insn_binvi.v index a0bc75d4..4ba732c9 100644 --- a/insns/insn_binvi.v +++ b/insns/insn_binvi.v @@ -27,7 +27,7 @@ module rvfi_insn_binvi ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -43,9 +43,9 @@ module rvfi_insn_binvi ( `endif // BINVI instruction - wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] index = insn_shamt & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ (1 << index); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 011010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_bset.v b/insns/insn_bset.v index 40deb19d..2dd13f94 100644 --- a/insns/insn_bset.v +++ b/insns/insn_bset.v @@ -27,7 +27,7 @@ module rvfi_insn_bset ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -45,7 +45,7 @@ module rvfi_insn_bset ( // BSET instruction wire [`RISCV_FORMAL_XLEN-1:0] index = rvfi_rs2_rdata & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | (1 << index); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0010100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && 1; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 001010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_bseti.v b/insns/insn_bseti.v index 08a16c56..862b7cbd 100644 --- a/insns/insn_bseti.v +++ b/insns/insn_bseti.v @@ -27,7 +27,7 @@ module rvfi_insn_bseti ( // R-type instruction format (bitwise variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; - wire [6:0] insn_funct7 = rvfi_insn[31:25]; + wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; @@ -43,9 +43,9 @@ module rvfi_insn_bseti ( `endif // BSETI instruction - wire [`RISCV_FORMAL_XLEN-1:0] index = shamt & (`RISCV_FORMAL_XLEN - 1); + wire [`RISCV_FORMAL_XLEN-1:0] index = insn_shamt & (`RISCV_FORMAL_XLEN - 1); wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | (1 << index); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0010100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 001010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_clz.v b/insns/insn_clz.v index 3ee8d348..96968bc5 100644 --- a/insns/insn_clz.v +++ b/insns/insn_clz.v @@ -57,12 +57,12 @@ module rvfi_insn_clz ( end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_clzw.v b/insns/insn_clzw.v index f4974126..9308b3ed 100644 --- a/insns/insn_clzw.v +++ b/insns/insn_clzw.v @@ -57,12 +57,12 @@ module rvfi_insn_clzw ( end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_cpop.v b/insns/insn_cpop.v index 39c881a6..625037dc 100644 --- a/insns/insn_cpop.v +++ b/insns/insn_cpop.v @@ -56,12 +56,12 @@ module rvfi_insn_cpop ( end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_cpopw.v b/insns/insn_cpopw.v index 9b0e81ec..f5c0431e 100644 --- a/insns/insn_cpopw.v +++ b/insns/insn_cpopw.v @@ -56,12 +56,12 @@ module rvfi_insn_cpopw ( end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00010 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_ctz.v b/insns/insn_ctz.v index 3ccb2615..5f106369 100644 --- a/insns/insn_ctz.v +++ b/insns/insn_ctz.v @@ -59,12 +59,12 @@ module rvfi_insn_ctz ( end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_ctzw.v b/insns/insn_ctzw.v index 991d0217..0b5ca5b2 100644 --- a/insns/insn_ctzw.v +++ b/insns/insn_ctzw.v @@ -59,12 +59,12 @@ module rvfi_insn_ctzw ( end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_max.v b/insns/insn_max.v index 45fea18a..4edac763 100644 --- a/insns/insn_max.v +++ b/insns/insn_max.v @@ -42,7 +42,7 @@ module rvfi_insn_max ( `endif // MAX instruction - wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs2_rdata : rvfi_rs1_rdata; + wire [`RISCV_FORMAL_XLEN-1:0] result = ($signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)) ? rvfi_rs2_rdata : rvfi_rs1_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000101 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; diff --git a/insns/insn_min.v b/insns/insn_min.v index 40da856f..9e46051d 100644 --- a/insns/insn_min.v +++ b/insns/insn_min.v @@ -42,7 +42,7 @@ module rvfi_insn_min ( `endif // MIN instruction - wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata < rvfi_rs2_rdata) ? rvfi_rs1_rdata : rvfi_rs2_rdata; + wire [`RISCV_FORMAL_XLEN-1:0] result = ($signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)) ? rvfi_rs1_rdata : rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000101 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; diff --git a/insns/insn_rori.v b/insns/insn_rori.v index 4c5fb393..7bfd76c5 100644 --- a/insns/insn_rori.v +++ b/insns/insn_rori.v @@ -42,8 +42,8 @@ module rvfi_insn_rori ( `endif // RORI instruction - wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt)); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); + wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - insn_shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 011000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; diff --git a/insns/insn_roriw.v b/insns/insn_roriw.v index d1de58de..45fb7ee0 100644 --- a/insns/insn_roriw.v +++ b/insns/insn_roriw.v @@ -42,8 +42,8 @@ module rvfi_insn_roriw ( `endif // RORIW instruction - wire [31:0] result = (rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt)); - assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 0110000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; + wire [31:0] result = (rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (32 - insn_shamt)); + assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 011000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; diff --git a/insns/insn_sext_b.v b/insns/insn_sext_b.v index e5785c4a..d9d090f9 100644 --- a/insns/insn_sext_b.v +++ b/insns/insn_sext_b.v @@ -45,12 +45,12 @@ module rvfi_insn_sext_b ( wire [8-1:0] result = rvfi_rs1_rdata[8-1:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00100 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-8{result[8-1]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_sext_h.v b/insns/insn_sext_h.v index 77c30e9f..a82b0d98 100644 --- a/insns/insn_sext_h.v +++ b/insns/insn_sext_h.v @@ -45,12 +45,12 @@ module rvfi_insn_sext_h ( wire [16-1:0] result = rvfi_rs1_rdata[16-1:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00101 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-16{result[16-1]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; diff --git a/insns/insn_zext_h.v b/insns/insn_zext_h.v index d60c7be4..994eaaf8 100644 --- a/insns/insn_zext_h.v +++ b/insns/insn_zext_h.v @@ -43,14 +43,14 @@ module rvfi_insn_zext_h ( // ZEXT_H instruction wire [16-1:0] result = rvfi_rs1_rdata[16-1:0]; - assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000100 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b {011, `RISCV_FORMAL_XLEN != 32, 011}; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000100 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 100 && insn_opcode == {3'b 011, `RISCV_FORMAL_XLEN != 32, 3'b 011}; assign spec_rs1_addr = insn_rs1; - assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; - assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-16{0}}, result} : 0; + assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-16{1'b 0}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments + assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; From 06e36089f781cc25c05e09759b8ae2aaeec74943 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 3 Oct 2024 17:39:06 +1300 Subject: [PATCH 05/11] WIP b extension for NERV Everything but `clz` `ctz` and `cpop` should work. --- cores/nerv/checks.cfg | 2 +- cores/nerv/nerv.sv | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/cores/nerv/checks.cfg b/cores/nerv/checks.cfg index 12447d8b..a4fabc8f 100644 --- a/cores/nerv/checks.cfg +++ b/cores/nerv/checks.cfg @@ -15,7 +15,7 @@ # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. [options] -isa rv32i +isa rv32ib nbus 2 csr_spec 1.12 diff --git a/cores/nerv/nerv.sv b/cores/nerv/nerv.sv index c26399f9..4fdf2bd5 100644 --- a/cores/nerv/nerv.sv +++ b/cores/nerv/nerv.sv @@ -949,6 +949,23 @@ module nerv #( 10'b 0000000_001 /* SLLI */: begin next_wr = 1; next_rd = rs1_value << insn[24:20]; end 10'b 0000000_101 /* SRLI */: begin next_wr = 1; next_rd = rs1_value >> insn[24:20]; end 10'b 0100000_101 /* SRAI */: begin next_wr = 1; next_rd = $signed(rs1_value) >>> insn[24:20]; end + // Zbb: Basic bit-manipulation + 10'b 0110000_001: begin + casez (insn[24:20]) + // 5'b 00000 /* CLZ */: begin next_wr = 1; next_rd = 0; end + // 5'b 00001 /* CTZ */: begin next_wr = 1; next_rd = 0; end + // 5'b 00010 /* CPOP */: begin next_wr = 1; next_rd = 0; end + 5'b 00100 /* SEXT.B */: begin next_wr = 1; next_rd = $signed(rs1_value[7:0]); end + 5'b 00101 /* SEXT.H */: begin next_wr = 1; next_rd = $signed(rs1_value[15:0]); end + default: illinsn = 1; + endcase + end + 10'b 0110000_101 /* RORI */: begin next_wr = 1; next_rd = rs1_value >> insn[24:20] | (rs1_value << (32 - insn[24:20])); end + // Zbs: Single-bit instructions + 10'b 0100100_001 /* BCLRI */: begin next_wr = 1; next_rd = rs1_value & ~(1 << insn[24:20]); end + 10'b 0100100_101 /* BEXTI */: begin next_wr = 1; next_rd = (rs1_value >> insn[24:20]) & 1; end + 10'b 0110100_001 /* BINVI */: begin next_wr = 1; next_rd = rs1_value ^ (1 << insn[24:20]); end + 10'b 0010100_001 /* BSETI */: begin next_wr = 1; next_rd = rs1_value | (1 << insn[24:20]); end default: illinsn = 1; endcase end @@ -966,6 +983,26 @@ module nerv #( 10'b 0100000_101 /* SRA */: begin next_wr = 1; next_rd = $signed(rs1_value) >>> rs2_value[4:0]; end 10'b 0000000_110 /* OR */: begin next_wr = 1; next_rd = rs1_value | rs2_value; end 10'b 0000000_111 /* AND */: begin next_wr = 1; next_rd = rs1_value & rs2_value; end + // Zba: Address generation + 10'b 0010000_010 /* SH1ADD */: begin next_wr = 1; next_rd = rs2_value + {rs1_value[30:0], 1'b 0}; end + 10'b 0010000_100 /* SH2ADD */: begin next_wr = 1; next_rd = rs2_value + {rs1_value[29:0], 2'b 0}; end + 10'b 0010000_110 /* SH3ADD */: begin next_wr = 1; next_rd = rs2_value + {rs1_value[28:0], 3'b 0}; end + // Zbb: Basic bit-manipulation + 10'b 0100000_111 /* ANDN */: begin next_wr = 1; next_rd = rs1_value & ~rs2_value; end + 10'b 0100000_110 /* ORN */: begin next_wr = 1; next_rd = rs1_value | ~rs2_value; end + 10'b 0100000_100 /* XNOR */: begin next_wr = 1; next_rd = ~(rs1_value ^ rs2_value); end + 10'b 0000101_110 /* MAX */: begin next_wr = 1; next_rd = ($signed(rs1_value) < $signed(rs2_value)) ? rs2_value : rs1_value; end + 10'b 0000101_111 /* MAXU */: begin next_wr = 1; next_rd = (rs1_value < rs2_value) ? rs2_value : rs1_value; end + 10'b 0000101_100 /* MIN */: begin next_wr = 1; next_rd = ($signed(rs1_value) < $signed(rs2_value)) ? rs1_value : rs2_value; end + 10'b 0000101_101 /* MINU */: begin next_wr = 1; next_rd = (rs1_value < rs2_value) ? rs1_value : rs2_value; end + 10'b 0110000_001 /* ROL */: begin next_wr = 1; next_rd = rs1_value << rs2_value[4:0] | (rs1_value >> (32 - rs2_value[4:0])); end + 10'b 0110000_101 /* ROR */: begin next_wr = 1; next_rd = rs1_value >> rs2_value[4:0] | (rs1_value << (32 - rs2_value[4:0])); end + 10'b 0000100_100 /* ZEXT.H */: begin next_wr = 1; next_rd = {16'b 0, rs1_value[15:0]}; end + // Zbs: Single-bit instructions + 10'b 0100100_001 /* BCLR */: begin next_wr = 1; next_rd = rs1_value & ~(1 << rs2_value[4:0]); end + 10'b 0100100_101 /* BEXT */: begin next_wr = 1; next_rd = (rs1_value >> rs2_value[4:0]) & 1; end + 10'b 0110100_001 /* BINV */: begin next_wr = 1; next_rd = rs1_value ^ (1 << rs2_value[4:0]); end + 10'b 0010100_001 /* BSET */: begin next_wr = 1; next_rd = rs1_value | (1 << rs2_value[4:0]); end default: illinsn = 1; endcase end From 3b2b119870eddc66dcdb3dbc2c4539df805a8ab5 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 3 Oct 2024 21:14:18 +1300 Subject: [PATCH 06/11] Drop pseudo instruction zext.w --- insns/generate.py | 1 - 1 file changed, 1 deletion(-) diff --git a/insns/generate.py b/insns/generate.py index 821b53ae..60deae83 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -1405,7 +1405,6 @@ def insn_bit(insn, funct6, funct3, expr, imode=False, misa=MISA_B): insn_alu("sh2add_uw", "0010000", "100", "rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 2)", uwmode=True, misa=MISA_B) insn_alu("sh3add_uw", "0010000", "110", "rvfi_rs2_rdata + (rvfi_rs1_rdata[31:0] << 3)", uwmode=True, misa=MISA_B) insn_shimm("slli_uw", "000010", "001", "rvfi_rs1_rdata[31:0] << insn_shamt", uwmode=True, misa=MISA_B) -# insn_alu("zext_w", wmode=True, misa=MISA_B) # ??? ### Zbb: Basic bit-manipulation From 84c3acc65b476da62764543c740be021094cf91b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 10 Oct 2024 12:24:36 +1300 Subject: [PATCH 07/11] Fix ctz and clz --- insns/generate.py | 6 +++--- insns/insn_clz.v | 6 ++++-- insns/insn_clzw.v | 6 ++++-- insns/insn_ctz.v | 6 ++---- insns/insn_ctzw.v | 6 ++---- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/insns/generate.py b/insns/generate.py index 60deae83..d5362c8d 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -1167,13 +1167,13 @@ def insn_count(insn, funct5, trailing=False, pop=False, wmode=False, misa=MISA_B assert not trailing print(" result = result + rvfi_rs1_rdata[i];", file=f) elif trailing: # count trailing zeros + print(" found = found | rvfi_rs1_rdata[i];", file=f) + print(" result = result + !(rvfi_rs1_rdata[i] | found);", file=f) + else: # count leading zeros print(" if (rvfi_rs1_rdata[i] == 1'b1)", file=f) print(" result = 0;", file=f) print(" else", file=f) print(" result = result + 1;", file=f) - else: # count leading zeros - print(" found = found | rvfi_rs1_rdata[i];", file=f) - print(" result = result + ~(rvfi_rs1_rdata[i] | found);", file=f) print(" end", file=f) print(" end", file=f) diff --git a/insns/insn_clz.v b/insns/insn_clz.v index 96968bc5..0c7cca1e 100644 --- a/insns/insn_clz.v +++ b/insns/insn_clz.v @@ -51,8 +51,10 @@ module rvfi_insn_clz ( found = 0; for (i=0; i<`RISCV_FORMAL_XLEN; i=i+1) begin - found = found | rvfi_rs1_rdata[i]; - result = result + ~(rvfi_rs1_rdata[i] | found); + if (rvfi_rs1_rdata[i] == 1'b1) + result = 0; + else + result = result + 1; end end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; diff --git a/insns/insn_clzw.v b/insns/insn_clzw.v index 9308b3ed..25df3ed2 100644 --- a/insns/insn_clzw.v +++ b/insns/insn_clzw.v @@ -51,8 +51,10 @@ module rvfi_insn_clzw ( found = 0; for (i=0; i<32; i=i+1) begin - found = found | rvfi_rs1_rdata[i]; - result = result + ~(rvfi_rs1_rdata[i] | found); + if (rvfi_rs1_rdata[i] == 1'b1) + result = 0; + else + result = result + 1; end end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; diff --git a/insns/insn_ctz.v b/insns/insn_ctz.v index 5f106369..33d322a8 100644 --- a/insns/insn_ctz.v +++ b/insns/insn_ctz.v @@ -51,10 +51,8 @@ module rvfi_insn_ctz ( found = 0; for (i=0; i<`RISCV_FORMAL_XLEN; i=i+1) begin - if (rvfi_rs1_rdata[i] == 1'b1) - result = 0; - else - result = result + 1; + found = found | rvfi_rs1_rdata[i]; + result = result + !(rvfi_rs1_rdata[i] | found); end end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011; diff --git a/insns/insn_ctzw.v b/insns/insn_ctzw.v index 0b5ca5b2..71836cd1 100644 --- a/insns/insn_ctzw.v +++ b/insns/insn_ctzw.v @@ -51,10 +51,8 @@ module rvfi_insn_ctzw ( found = 0; for (i=0; i<32; i=i+1) begin - if (rvfi_rs1_rdata[i] == 1'b1) - result = 0; - else - result = result + 1; + found = found | rvfi_rs1_rdata[i]; + result = result + !(rvfi_rs1_rdata[i] | found); end end assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct5 == 5'b 00001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011; From 845d3bb526318e8b6428d47438c91eaedb056b1e Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 12 Oct 2024 10:05:24 +1300 Subject: [PATCH 08/11] rev8 and orc_b instructions --- insns/generate.py | 43 ++++++++++++++++- insns/insn_orc_b.v | 68 +++++++++++++++++++++++++++ insns/insn_rev8.v | 68 +++++++++++++++++++++++++++ insns/isa_rv32iZbb.txt | 2 + insns/isa_rv32iZbb.v | 102 +++++++++++++++++++++++++++++++++++++++++ insns/isa_rv32ib.txt | 2 + insns/isa_rv32ib.v | 102 +++++++++++++++++++++++++++++++++++++++++ insns/isa_rv64iZbb.txt | 2 + insns/isa_rv64iZbb.v | 102 +++++++++++++++++++++++++++++++++++++++++ insns/isa_rv64ib.txt | 2 + insns/isa_rv64ib.v | 102 +++++++++++++++++++++++++++++++++++++++++ 11 files changed, 593 insertions(+), 2 deletions(-) create mode 100644 insns/insn_orc_b.v create mode 100644 insns/insn_rev8.v diff --git a/insns/generate.py b/insns/generate.py index d5362c8d..3a3059fd 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -207,6 +207,16 @@ def format_i_shift(f): print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) +def format_iB(f): + print("", file=f) + print(" // I-type instruction format (bytewise variation)", file=f) + print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) + print(" wire [11:0] insn_funct12 = rvfi_insn[31:20];", file=f) + print(" wire [ 4:0] insn_rs1 = rvfi_insn[19:15];", file=f) + print(" wire [ 2:0] insn_funct3 = rvfi_insn[14:12];", file=f) + print(" wire [ 4:0] insn_rd = rvfi_insn[11: 7];", file=f) + print(" wire [ 6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) + def format_b(f): print("", file=f) # TODO: figure out if there is an official name for this format @@ -1251,6 +1261,35 @@ def insn_bit(insn, funct6, funct3, expr, imode=False, misa=MISA_B): footer(f) +def insn_bytes(insn, funct12, funct3, expr, misa=MISA_B): + with open("insn_%s.v" % insn, "w") as f: + header(f, insn) + format_iB(f) + misa_check(f, misa) + + opcode = "0010011" + + print("", file=f) + print(" // %s instruction" % insn.upper(), file=f) + print(" reg [`RISCV_FORMAL_XLEN-1:0] result;", file=f) + print(" integer i;", file=f) + print(" localparam integer nbytes = $clog2(`RISCV_FORMAL_XLEN)-1;", file=f) + print(" always @(rvfi_rs1_rdata)", file=f) + print(" begin", file=f) + print(" result = 0;", file=f) + print(" for (i=0; i> (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) insn_alu("ror", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) insn_shimm("rori", "011000", "101", "(rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - insn_shamt))", misa=MISA_B) -# insn_("orc_b", "001010000111", "101", "", misa=MISA_B) -# insn_("rev8", "011010011000", "101", "", misa=MISA_B) +insn_bytes("orc_b", "001010000111", "101", "{8{|rvfi_rs1_rdata[i*8+:8]}}", misa=MISA_B) +insn_bytes("rev8", "011010011000", "101", "rvfi_rs1_rdata[((nbytes-i)*8)-1-:8]", misa=MISA_B) current_isa = ["rv64iZbb"] diff --git a/insns/insn_orc_b.v b/insns/insn_orc_b.v new file mode 100644 index 00000000..b418920d --- /dev/null +++ b/insns/insn_orc_b.v @@ -0,0 +1,68 @@ +// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py + +module rvfi_insn_orc_b ( + input rvfi_valid, + input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, +`ifdef RISCV_FORMAL_CSR_MISA + input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, +`endif + + output spec_valid, + output spec_trap, + output [ 4 : 0] spec_rs1_addr, + output [ 4 : 0] spec_rs2_addr, + output [ 4 : 0] spec_rd_addr, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, + output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, + output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata +); + + // I-type instruction format (bytewise variation) + wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; + wire [11:0] insn_funct12 = rvfi_insn[31:20]; + wire [ 4:0] insn_rs1 = rvfi_insn[19:15]; + wire [ 2:0] insn_funct3 = rvfi_insn[14:12]; + wire [ 4:0] insn_rd = rvfi_insn[11: 7]; + wire [ 6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // ORC_B instruction + reg [`RISCV_FORMAL_XLEN-1:0] result; + integer i; + localparam integer nbytes = $clog2(`RISCV_FORMAL_XLEN)-1; + always @(rvfi_rs1_rdata) + begin + result = 0; + for (i=0; i> 16 >> 16; + wire [11:0] insn_funct12 = rvfi_insn[31:20]; + wire [ 4:0] insn_rs1 = rvfi_insn[19:15]; + wire [ 2:0] insn_funct3 = rvfi_insn[14:12]; + wire [ 4:0] insn_rd = rvfi_insn[11: 7]; + wire [ 6:0] insn_opcode = rvfi_insn[ 6: 0]; + +`ifdef RISCV_FORMAL_CSR_MISA + wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 2) == `RISCV_FORMAL_XLEN'h 2; + assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 2; +`else + wire misa_ok = 1; +`endif + + // REV8 instruction + reg [`RISCV_FORMAL_XLEN-1:0] result; + integer i; + localparam integer nbytes = $clog2(`RISCV_FORMAL_XLEN)-1; + always @(rvfi_rs1_rdata) + begin + result = 0; + for (i=0; i Date: Sat, 12 Oct 2024 10:36:59 +1300 Subject: [PATCH 09/11] Add extra Zbb instructions CLZ, CTZ, CPOP, ORC.B, and REV8. --- cores/nerv/nerv.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/cores/nerv/nerv.sv b/cores/nerv/nerv.sv index 4fdf2bd5..3a7b8e70 100644 --- a/cores/nerv/nerv.sv +++ b/cores/nerv/nerv.sv @@ -952,15 +952,17 @@ module nerv #( // Zbb: Basic bit-manipulation 10'b 0110000_001: begin casez (insn[24:20]) - // 5'b 00000 /* CLZ */: begin next_wr = 1; next_rd = 0; end - // 5'b 00001 /* CTZ */: begin next_wr = 1; next_rd = 0; end - // 5'b 00010 /* CPOP */: begin next_wr = 1; next_rd = 0; end + 5'b 00000 /* CLZ */: begin next_wr = 1; next_rd = 0; for (int i=0; i<32; i=i+1) next_rd = rs1_value[i] ? 0 : next_rd + 1; end + 5'b 00001 /* CTZ */: begin next_wr = 1; next_rd = 0; for (int i=32; i>0; i=i-1) next_rd = rs1_value[i-1] ? 0 : next_rd + 1; end + 5'b 00010 /* CPOP */: begin next_wr = 1; next_rd = 0; for (int i=0; i<32; i=i+1) next_rd = next_rd + rs1_value[i]; end 5'b 00100 /* SEXT.B */: begin next_wr = 1; next_rd = $signed(rs1_value[7:0]); end 5'b 00101 /* SEXT.H */: begin next_wr = 1; next_rd = $signed(rs1_value[15:0]); end default: illinsn = 1; endcase end - 10'b 0110000_101 /* RORI */: begin next_wr = 1; next_rd = rs1_value >> insn[24:20] | (rs1_value << (32 - insn[24:20])); end + 10'b 0110000_101 /* RORI */: begin next_wr = 1; next_rd = rs1_value >> insn[24:20] | (rs1_value << (32 - insn[24:20])); end + 10'b 0010100_101 /* ORC.B */: begin next_wr = insn[24:20] == 5'b 00111; illinsn = !next_wr; next_rd = 0; for (int i=0; i<4; i=i+1) next_rd[i*8 +: 8] = {8{|rs1_value[i*8 +: 8]}}; end + 10'b 0110100_101 /* REV8 */: begin next_wr = insn[24:20] == 5'b 11000; illinsn = !next_wr; next_rd = 0; for (int i=0; i<4; i=i+1) next_rd[i*8 +: 8] = rs1_value[(4-i)*8 - 1 -: 8]; end // Zbs: Single-bit instructions 10'b 0100100_001 /* BCLRI */: begin next_wr = 1; next_rd = rs1_value & ~(1 << insn[24:20]); end 10'b 0100100_101 /* BEXTI */: begin next_wr = 1; next_rd = (rs1_value >> insn[24:20]) & 1; end From c00c7684d4e57e385d7d801d2ae7a5726b723b62 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 12 Oct 2024 12:33:54 +1300 Subject: [PATCH 10/11] Fixing some 64 bit instructions --- insns/generate.py | 14 +++++++------- insns/insn_orc_b.v | 2 +- insns/insn_rev8.v | 4 ++-- insns/insn_rolw.v | 2 +- insns/insn_roriw.v | 2 +- insns/insn_rorw.v | 2 +- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/insns/generate.py b/insns/generate.py index 3a3059fd..e0fa508b 100644 --- a/insns/generate.py +++ b/insns/generate.py @@ -1273,7 +1273,7 @@ def insn_bytes(insn, funct12, funct3, expr, misa=MISA_B): print(" // %s instruction" % insn.upper(), file=f) print(" reg [`RISCV_FORMAL_XLEN-1:0] result;", file=f) print(" integer i;", file=f) - print(" localparam integer nbytes = $clog2(`RISCV_FORMAL_XLEN)-1;", file=f) + print(" localparam integer nbytes = `RISCV_FORMAL_XLEN / 8;", file=f) print(" always @(rvfi_rs1_rdata)", file=f) print(" begin", file=f) print(" result = 0;", file=f) @@ -1282,7 +1282,7 @@ def insn_bytes(insn, funct12, funct3, expr, misa=MISA_B): print(f" result[i*8+:8] = {expr};", file=f) print(" end", file=f) print(" end", file=f) - assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct12 == 12'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s" % (funct12, funct3, opcode)) + assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct12 == %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s" % (funct12, funct3, opcode)) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") @@ -1465,17 +1465,17 @@ def insn_bytes(insn, funct12, funct3, expr, misa=MISA_B): insn_alu("rol", "0110000", "001", "(rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) insn_alu("ror", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - shamt))", shamt=True, misa=MISA_B) insn_shimm("rori", "011000", "101", "(rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (`RISCV_FORMAL_XLEN - insn_shamt))", misa=MISA_B) -insn_bytes("orc_b", "001010000111", "101", "{8{|rvfi_rs1_rdata[i*8+:8]}}", misa=MISA_B) -insn_bytes("rev8", "011010011000", "101", "rvfi_rs1_rdata[((nbytes-i)*8)-1-:8]", misa=MISA_B) +insn_bytes("orc_b", "12'b 001010000111", "101", "{8{|rvfi_rs1_rdata[i*8+:8]}}", misa=MISA_B) +insn_bytes("rev8", "{6'b 011010, `RISCV_FORMAL_XLEN == 64, 5'b 11000}", "101", "rvfi_rs1_rdata[((nbytes-i)*8)-1-:8]", misa=MISA_B) current_isa = ["rv64iZbb"] insn_count("clzw", "00000", wmode=True, misa=MISA_B) insn_count("ctzw", "00001", trailing=True, wmode=True, misa=MISA_B) insn_count("cpopw", "00010", pop=True, wmode=True, misa=MISA_B) -insn_alu("rolw", "0110000", "001", "(rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) -insn_alu("rorw", "0110000", "101", "(rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) -insn_shimm("roriw", "011000", "101", "(rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (32 - insn_shamt))", wmode=True, misa=MISA_B) +insn_alu("rolw", "0110000", "001", "(rvfi_rs1_rdata[31:0] << shamt) | (rvfi_rs1_rdata[31:0] >> (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) +insn_alu("rorw", "0110000", "101", "(rvfi_rs1_rdata[31:0] >> shamt) | (rvfi_rs1_rdata[31:0] << (32 - shamt))", shamt=True, wmode=True, misa=MISA_B) +insn_shimm("roriw", "011000", "101", "(rvfi_rs1_rdata[31:0] >> insn_shamt) | (rvfi_rs1_rdata[31:0] << (32 - insn_shamt))", wmode=True, misa=MISA_B) ### Zbs: Single-bit instructions diff --git a/insns/insn_orc_b.v b/insns/insn_orc_b.v index b418920d..b4fe9279 100644 --- a/insns/insn_orc_b.v +++ b/insns/insn_orc_b.v @@ -43,7 +43,7 @@ module rvfi_insn_orc_b ( // ORC_B instruction reg [`RISCV_FORMAL_XLEN-1:0] result; integer i; - localparam integer nbytes = $clog2(`RISCV_FORMAL_XLEN)-1; + localparam integer nbytes = `RISCV_FORMAL_XLEN / 8; always @(rvfi_rs1_rdata) begin result = 0; diff --git a/insns/insn_rev8.v b/insns/insn_rev8.v index 26416596..a19dc81c 100644 --- a/insns/insn_rev8.v +++ b/insns/insn_rev8.v @@ -43,7 +43,7 @@ module rvfi_insn_rev8 ( // REV8 instruction reg [`RISCV_FORMAL_XLEN-1:0] result; integer i; - localparam integer nbytes = $clog2(`RISCV_FORMAL_XLEN)-1; + localparam integer nbytes = `RISCV_FORMAL_XLEN / 8; always @(rvfi_rs1_rdata) begin result = 0; @@ -52,7 +52,7 @@ module rvfi_insn_rev8 ( result[i*8+:8] = rvfi_rs1_rdata[((nbytes-i)*8)-1-:8]; end end - assign spec_valid = rvfi_valid && !insn_padding && insn_funct12 == 12'b 011010011000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011; + assign spec_valid = rvfi_valid && !insn_padding && insn_funct12 == {6'b 011010, `RISCV_FORMAL_XLEN == 64, 5'b 11000} && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; diff --git a/insns/insn_rolw.v b/insns/insn_rolw.v index afc2845e..2a3a3f8b 100644 --- a/insns/insn_rolw.v +++ b/insns/insn_rolw.v @@ -43,7 +43,7 @@ module rvfi_insn_rolw ( // ROLW instruction wire [4:0] shamt = rvfi_rs2_rdata[4:0]; - wire [31:0] result = (rvfi_rs1_rdata << shamt) | (rvfi_rs1_rdata >> (32 - shamt)); + wire [31:0] result = (rvfi_rs1_rdata[31:0] << shamt) | (rvfi_rs1_rdata[31:0] >> (32 - shamt)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; diff --git a/insns/insn_roriw.v b/insns/insn_roriw.v index 45fb7ee0..2391e0af 100644 --- a/insns/insn_roriw.v +++ b/insns/insn_roriw.v @@ -42,7 +42,7 @@ module rvfi_insn_roriw ( `endif // RORIW instruction - wire [31:0] result = (rvfi_rs1_rdata >> insn_shamt) | (rvfi_rs1_rdata << (32 - insn_shamt)); + wire [31:0] result = (rvfi_rs1_rdata[31:0] >> insn_shamt) | (rvfi_rs1_rdata[31:0] << (32 - insn_shamt)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 011000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; diff --git a/insns/insn_rorw.v b/insns/insn_rorw.v index b3bf7e24..a459767c 100644 --- a/insns/insn_rorw.v +++ b/insns/insn_rorw.v @@ -43,7 +43,7 @@ module rvfi_insn_rorw ( // RORW instruction wire [4:0] shamt = rvfi_rs2_rdata[4:0]; - wire [31:0] result = (rvfi_rs1_rdata >> shamt) | (rvfi_rs1_rdata << (32 - shamt)); + wire [31:0] result = (rvfi_rs1_rdata[31:0] >> shamt) | (rvfi_rs1_rdata[31:0] << (32 - shamt)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0110000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; From fb3b7a8cda97a17cc71f518b670ebca6151f82a0 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 14 Oct 2024 08:33:52 +1300 Subject: [PATCH 11/11] Disable csr spec tests Having the csr_spec option enables CSR testing, including the misa CSR which uses the define `RISCV_FORMAL_CSR_MISA`. If the CSR_MISA flag is defined then instructions from extensions will check the misa CSR includes the bit flag for the instruction. We don't want that, since NERV misa is all zeros. --- cores/nerv/checks.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/nerv/checks.cfg b/cores/nerv/checks.cfg index a4fabc8f..69b9e3aa 100644 --- a/cores/nerv/checks.cfg +++ b/cores/nerv/checks.cfg @@ -17,7 +17,7 @@ [options] isa rv32ib nbus 2 -csr_spec 1.12 +# csr_spec 1.12 [depth] insn 10