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MorseDecoder_summary.html
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MorseDecoder_summary.html
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>MorseDecoder Project Status (01/16/2022 - 04:14:30)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>FinalProject.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>MorseDecoder</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s500e-4fg320</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\_xmsgs/*.xmsgs?&DataKey=Warning'>9 Warnings (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 <A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>350</TD>
<TD ALIGN=RIGHT>9,312</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>503</TD>
<TD ALIGN=RIGHT>9,312</TD>
<TD ALIGN=RIGHT>5%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>351</TD>
<TD ALIGN=RIGHT>4,656</TD>
<TD ALIGN=RIGHT>7%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>351</TD>
<TD ALIGN=RIGHT>351</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>351</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>648</TD>
<TD ALIGN=RIGHT>9,312</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
<TD ALIGN=RIGHT>503</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as a route-thru</TD>
<TD ALIGN=RIGHT>145</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>8%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.36</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B> </B></TD>
<TD COLSPAN='2'> </TD>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Paz 16. Oca 04:14:03 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\_xmsgs/xst.xmsgs?&DataKey=Warning'>9 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.bld'>Translation Report</A></TD><TD>Current</TD><TD>Paz 16. Oca 04:14:07 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Paz 16. Oca 04:14:11 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\_xmsgs/map.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Paz 16. Oca 04:14:21 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Paz 16. Oca 04:14:24 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\MorseDecoder.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Paz 16. Oca 04:14:28 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\netgen/synthesis/MorseDecoder_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Paz 16. Oca 02:12:15 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Paz 16. Oca 04:14:29 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Ders/FPGA/Workspace/FinalProject\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Paz 16. Oca 04:14:30 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 01/16/2022 - 04:14:30</center>
</BODY></HTML>