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MorseDecoder.syr
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MorseDecoder.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: MorseDecoder.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "MorseDecoder.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "MorseDecoder"
Output Format : NGC
Target Device : xc3s500e-4-fg320
---- Source Options
Top Module Name : MorseDecoder
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "D:/Ders/FPGA/Workspace/FinalProject/ButtonController.vhd" in Library work.
Architecture behavioral of Entity buttoncontroller is up to date.
Compiling vhdl file "D:/Ders/FPGA/Workspace/FinalProject/LCD.vhd" in Library work.
Architecture behavior of Entity lcd is up to date.
Compiling vhdl file "D:/Ders/FPGA/Workspace/FinalProject/MorseLookUpTable.vhd" in Library work.
Architecture behavioral of Entity morselookuptable is up to date.
Compiling vhdl file "D:/Ders/FPGA/Workspace/FinalProject/MorseDecoder.vhd" in Library work.
Architecture behavioral of Entity morsedecoder is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <MorseDecoder> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <ButtonController> in library <work> (architecture <Behavioral>).
Analyzing hierarchy for entity <lcd> in library <work> (architecture <behavior>).
Analyzing hierarchy for entity <MorseLookUpTable> in library <work> (architecture <Behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <MorseDecoder> in library <work> (Architecture <behavioral>).
Entity <MorseDecoder> analyzed. Unit <MorseDecoder> generated.
Analyzing Entity <ButtonController> in library <work> (Architecture <Behavioral>).
Entity <ButtonController> analyzed. Unit <ButtonController> generated.
Analyzing Entity <lcd> in library <work> (Architecture <behavior>).
Entity <lcd> analyzed. Unit <lcd> generated.
Analyzing Entity <MorseLookUpTable> in library <work> (Architecture <Behavioral>).
Entity <MorseLookUpTable> analyzed. Unit <MorseLookUpTable> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <ButtonController>.
Related source file is "D:/Ders/FPGA/Workspace/FinalProject/ButtonController.vhd".
Found 1-bit register for signal <BTN_PRESSED>.
Found 1-bit 4-to-1 multiplexer for signal <BTN_PRESSED$mux0001> created at line 49.
Found 1-bit register for signal <BTN_VAL_PREV>.
Found 1-bit 4-to-1 multiplexer for signal <BTN_VAL_PREV$mux0000>.
Found 1-bit xor2 for signal <BTN_VAL_PREV$xor0000> created at line 52.
Summary:
inferred 2 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <ButtonController> synthesized.
Synthesizing Unit <lcd>.
Related source file is "D:/Ders/FPGA/Workspace/FinalProject/LCD.vhd".
INFO:Xst:1799 - State set_addr_40 is never reached in FSM <cur_state>.
Found finite state machine <FSM_0> for signal <init_state>.
-----------------------------------------------------------------------
| States | 11 |
| Transitions | 21 |
| Inputs | 6 |
| Outputs | 11 |
| Clock | clk (rising_edge) |
| Reset | reset (positive) |
| Reset type | asynchronous |
| Reset State | idle |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <cur_state>.
-----------------------------------------------------------------------
| States | 13 |
| Transitions | 30 |
| Inputs | 8 |
| Outputs | 15 |
| Clock | clk (rising_edge) |
| Reset | reset (positive) |
| Reset type | asynchronous |
| Reset State | function_set |
| Power Up State | init |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_2> for signal <tx_state>.
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 14 |
| Inputs | 5 |
| Outputs | 8 |
| Clock | clk (rising_edge) |
| Reset | reset (positive) |
| Reset type | asynchronous |
| Reset State | done |
| Power Up State | done |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 16x8-bit ROM for signal <line_switch_cmd$mux0004>.
Found 16x8-bit ROM for signal <line_switch_cmd$mux0005>.
Found 32-bit register for signal <bottom_line_cursor>.
Found 32-bit addsub for signal <bottom_line_cursor$share0000> created at line 211.
Found 32-bit comparator greater for signal <cur_state$cmp_gt0000> created at line 171.
Found 32-bit comparator greater for signal <cur_state$cmp_gt0001> created at line 166.
Found 1-bit register for signal <current_line>.
Found 20-bit register for signal <i>.
Found 20-bit adder for signal <i$share0000> created at line 385.
Found 11-bit register for signal <i2>.
Found 11-bit adder for signal <i2$share0000> created at line 300.
Found 17-bit register for signal <i3>.
Found 17-bit adder for signal <i3$addsub0000> created at line 145.
Found 1-bit register for signal <init_done>.
Found 1-bit register for signal <LCD_E0>.
Found 1-bit register for signal <LCD_E1>.
Found 8-bit register for signal <line_switch_cmd>.
Found 4-bit register for signal <SF_D0>.
Found 4-bit register for signal <SF_D1>.
Found 32-bit register for signal <top_line_cursor>.
Found 32-bit addsub for signal <top_line_cursor$share0000> created at line 211.
Summary:
inferred 3 Finite State Machine(s).
inferred 2 ROM(s).
inferred 132 D-type flip-flop(s).
inferred 5 Adder/Subtractor(s).
inferred 2 Comparator(s).
Unit <lcd> synthesized.
Synthesizing Unit <MorseLookUpTable>.
Related source file is "D:/Ders/FPGA/Workspace/FinalProject/MorseLookUpTable.vhd".
Unit <MorseLookUpTable> synthesized.
Synthesizing Unit <MorseDecoder>.
Related source file is "D:/Ders/FPGA/Workspace/FinalProject/MorseDecoder.vhd".
Found finite state machine <FSM_3> for signal <current_state>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 17 |
| Inputs | 5 |
| Outputs | 7 |
| Clock | clk_10ms_flag (rising_edge) |
| Power Up State | reset |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 1-bit register for signal <LED0>.
Found 1-bit register for signal <LED1>.
Found 1-bit register for signal <LED2>.
Found 1-bit register for signal <LED3>.
Found 1-bit register for signal <LED4>.
Found 1-bit register for signal <LED5>.
Found 1-bit register for signal <LED6>.
Found 1-bit register for signal <LED7>.
Found 1-bit register for signal <clk_10ms_flag>.
Found 32-bit up counter for signal <clk_10ms_timer>.
Found 32-bit register for signal <clk_5cycle_timer>.
Found 32-bit adder for signal <clk_5cycle_timer$addsub0000>.
Found 1-bit register for signal <lcd_delete_char_enable>.
Found 32-bit comparator less for signal <lcd_delete_char_enable$cmp_lt0000> created at line 316.
Found 1-bit register for signal <lcd_enable>.
Found 1-bit register for signal <lcd_switch_line_enable>.
Found 32-bit comparator less for signal <LED1$cmp_lt0000> created at line 195.
Found 32-bit comparator less for signal <LED3$cmp_lt0000> created at line 213.
Found 32-bit comparator less for signal <LED5$cmp_lt0000> created at line 230.
Found 32-bit comparator less for signal <LED7$cmp_lt0000> created at line 247.
Found 128-bit register for signal <morse_char>.
Found 8-bit register for signal <morse_encoded>.
Found 2-bit register for signal <morse_idx>.
Found 2-bit adder for signal <morse_idx$addsub0000> created at line 182.
Found 32-bit register for signal <push_timer>.
Found 32-bit adder for signal <push_timer$addsub0000> created at line 173.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 214 D-type flip-flop(s).
inferred 3 Adder/Subtractor(s).
inferred 5 Comparator(s).
Unit <MorseDecoder> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 2
16x8-bit ROM : 2
# Adders/Subtractors : 8
11-bit adder : 1
17-bit adder : 1
2-bit adder : 1
20-bit adder : 1
32-bit adder : 2
32-bit addsub : 2
# Counters : 1
32-bit up counter : 1
# Registers : 49
1-bit register : 34
11-bit register : 1
17-bit register : 1
2-bit register : 1
20-bit register : 1
32-bit register : 8
4-bit register : 2
8-bit register : 1
# Comparators : 7
32-bit comparator greater : 2
32-bit comparator less : 5
# Multiplexers : 10
1-bit 4-to-1 multiplexer : 10
# Xors : 5
1-bit xor2 : 5
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <current_state/FSM> on signal <current_state[1:3]> with gray encoding.
----------------------------
State | Encoding
----------------------------
reset | 000
idle | 001
count_press | 011
save_press | 101
save_character | 010
write_to_lcd | 100
switch_line | 110
delete_char | 111
----------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <LCD_CONTROLLER/tx_state/FSM> on signal <tx_state[1:7]> with one-hot encoding.
------------------------
State | Encoding
------------------------
high_setup | 0000100
high_hold | 0000010
oneus | 0001000
low_setup | 0010000
low_hold | 0100000
fortyus | 1000000
done | 0000001
------------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <LCD_CONTROLLER/cur_state/FSM> on signal <cur_state[1:13]> with one-hot encoding.
-------------------------------------------
State | Encoding
-------------------------------------------
init | 0000000000001
function_set | 0000000000010
entry_set | 0000000000100
set_display | 0000000001000
clr_display | 0000000010000
pause | 0000000100000
set_addr | 0000001000000
set_addr_40 | unreached
write_morse_input | 0000100000000
line_switch | 0001000000000
cursor_shift_left_first | 0100000000000
cursor_shift_left_second | 1000000000000
whitespace | 0010000000000
done | 0000010000000
-------------------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <LCD_CONTROLLER/init_state/FSM> on signal <init_state[1:11]> with one-hot encoding.
--------------------------
State | Encoding
--------------------------
idle | 00000000001
fifteenms | 00000000010
one | 00000000100
two | 00000001000
three | 00000010000
four | 00000100000
five | 00001000000
six | 00010000000
seven | 00100000000
eight | 01000000000
done | 10000000000
--------------------------
WARNING:Xst:1293 - FF/Latch <SF_D1_2> has a constant value of 0 in block <LCD_CONTROLLER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <SF_D1_3> has a constant value of 0 in block <LCD_CONTROLLER>. This FF/Latch will be trimmed during the optimization process.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 4
# ROMs : 2
16x8-bit ROM : 2
# Adders/Subtractors : 8
11-bit adder : 1
17-bit adder : 1
2-bit adder : 1
20-bit adder : 1
32-bit adder : 2
32-bit addsub : 2
# Counters : 1
32-bit up counter : 1
# Registers : 356
Flip-Flops : 356
# Comparators : 7
32-bit comparator greater : 2
32-bit comparator less : 5
# Multiplexers : 10
1-bit 4-to-1 multiplexer : 10
# Xors : 5
1-bit xor2 : 5
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1293 - FF/Latch <SF_D1_2> has a constant value of 0 in block <lcd>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <SF_D1_3> has a constant value of 0 in block <lcd>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <line_switch_cmd_4> has a constant value of 0 in block <lcd>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <line_switch_cmd_5> has a constant value of 0 in block <lcd>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1426 - The value init of the FF/Latch line_switch_cmd_7 hinder the constant cleaning in the block lcd.
You should achieve better results by setting this init to 1.
Optimizing unit <MorseDecoder> ...
Optimizing unit <ButtonController> ...
Optimizing unit <lcd> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block MorseDecoder, actual ratio is 10.
WARNING:Xst:1426 - The value init of the FF/Latch LCD_CONTROLLER/cur_state_FSM_FFd13 hinder the constant cleaning in the block MorseDecoder.
You should achieve better results by setting this init to 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 418
Flip-Flops : 418
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : MorseDecoder.ngr
Top Level Output File Name : MorseDecoder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 22
Cell Usage :
# BELS : 1422
# GND : 1
# INV : 24
# LUT1 : 145
# LUT2 : 109
# LUT2_D : 1
# LUT3 : 47
# LUT3_D : 12
# LUT3_L : 5
# LUT4 : 512
# LUT4_D : 14
# LUT4_L : 2
# MUXCY : 328
# MUXF5 : 13
# VCC : 1
# XORCY : 208
# FlipFlops/Latches : 418
# FD : 213
# FDC : 87
# FDCE : 7
# FDE : 71
# FDP : 2
# FDPE : 1
# FDR : 32
# FDS : 5
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 21
# IBUF : 5
# OBUF : 16
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-4
Number of Slices: 465 out of 4656 9%
Number of Slice Flip Flops: 418 out of 9312 4%
Number of 4 input LUTs: 871 out of 9312 9%
Number of IOs: 22
Number of bonded IOBs: 22 out of 232 9%
Number of GCLKs: 2 out of 24 8%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP | 227 |
clk_10ms_flag1 | BUFG | 191 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
BTN_RESET | IBUF | 97 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 8.678ns (Maximum Frequency: 115.234MHz)
Minimum input arrival time before clock: 5.031ns
Maximum output required time after clock: 7.158ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 8.678ns (frequency: 115.234MHz)
Total number of paths / destination ports: 14638 / 271
-------------------------------------------------------------------------
Delay: 8.678ns (Levels of Logic = 6)
Source: LCD_CONTROLLER/i_18 (FF)
Destination: LCD_CONTROLLER/i_19 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: LCD_CONTROLLER/i_18 to LCD_CONTROLLER/i_19
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 3 0.591 0.706 LCD_CONTROLLER/i_18 (LCD_CONTROLLER/i_18)
LUT4:I0->O 2 0.704 0.482 LCD_CONTROLLER/init_state_cmp_eq0000112 (LCD_CONTROLLER/N26)
LUT4_D:I2->O 2 0.704 0.451 LCD_CONTROLLER/init_state_cmp_eq00011 (LCD_CONTROLLER/N14)
LUT4:I3->O 3 0.704 0.566 LCD_CONTROLLER/init_state_cmp_eq0003 (LCD_CONTROLLER/init_state_cmp_eq0003)
LUT4:I2->O 2 0.704 0.526 LCD_CONTROLLER/i_mux0001<0>145 (LCD_CONTROLLER/i_mux0001<0>145)
LUT3_D:I1->O 9 0.704 0.824 LCD_CONTROLLER/i_mux0001<0>147 (LCD_CONTROLLER/N3)
LUT4:I3->O 1 0.704 0.000 LCD_CONTROLLER/i_mux0001<17>1 (LCD_CONTROLLER/i_mux0001<17>)
FDE:D 0.308 LCD_CONTROLLER/i_2
----------------------------------------
Total 8.678ns (5.123ns logic, 3.555ns route)
(59.0% logic, 41.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk_10ms_flag1'
Clock period: 6.724ns (frequency: 148.715MHz)
Total number of paths / destination ports: 3615 / 199
-------------------------------------------------------------------------
Delay: 6.724ns (Levels of Logic = 3)
Source: current_state_FSM_FFd3 (FF)
Destination: morse_char_0_0 (FF)
Source Clock: clk_10ms_flag1 rising
Destination Clock: clk_10ms_flag1 rising
Data Path: current_state_FSM_FFd3 to morse_char_0_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDS:C->Q 42 0.591 1.440 current_state_FSM_FFd3 (current_state_FSM_FFd3)
LUT3_D:I0->O 8 0.704 0.932 morse_char_0_or000011 (current_state_cmp_eq0006)
LUT4_D:I0->O 31 0.704 1.341 morse_char_3_mux0000<0>11 (N4)
LUT4:I1->O 1 0.704 0.000 morse_char_3_mux0000<9>1 (morse_char_3_mux0000<9>)
FD:D 0.308 morse_char_3_22
----------------------------------------
Total 6.724ns (3.011ns logic, 3.713ns route)
(44.8% logic, 55.2% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_10ms_flag1'
Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Offset: 3.593ns (Levels of Logic = 2)
Source: BTN_RESET (PAD)
Destination: BTN_RESET_CONTROLLER/BTN_PRESSED (FF)
Destination Clock: clk_10ms_flag1 rising
Data Path: BTN_RESET to BTN_RESET_CONTROLLER/BTN_PRESSED
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 101 1.218 1.363 BTN_RESET_IBUF (BTN_RESET_IBUF)
LUT3:I1->O 1 0.704 0.000 BTN_RESET_CONTROLLER/Mmux_BTN_PRESSED_mux000121 (BTN_RESET_CONTROLLER/BTN_PRESSED_mux0001)
FD:D 0.308 BTN_RESET_CONTROLLER/BTN_PRESSED
----------------------------------------
Total 3.593ns (2.230ns logic, 1.363ns route)
(62.1% logic, 37.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Total number of paths / destination ports: 62 / 62
-------------------------------------------------------------------------
Offset: 5.031ns (Levels of Logic = 2)
Source: BTN_RESET (PAD)
Destination: LCD_CONTROLLER/LCD_E0 (FF)
Destination Clock: CLK rising
Data Path: BTN_RESET to LCD_CONTROLLER/LCD_E0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 101 1.218 1.284 BTN_RESET_IBUF (BTN_RESET_IBUF)
INV:I->O 56 0.704 1.270 LCD_CONTROLLER/reset_inv1_INV_0 (LCD_CONTROLLER/reset_inv)
FDE:CE 0.555 LCD_CONTROLLER/SF_D0_0
----------------------------------------
Total 5.031ns (2.477ns logic, 2.554ns route)
(49.2% logic, 50.8% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 21 / 6
-------------------------------------------------------------------------
Offset: 7.158ns (Levels of Logic = 3)
Source: LCD_CONTROLLER/cur_state_FSM_FFd4 (FF)
Destination: LCD_RS (PAD)
Source Clock: CLK rising
Data Path: LCD_CONTROLLER/cur_state_FSM_FFd4 to LCD_RS
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 11 0.591 0.968 LCD_CONTROLLER/cur_state_FSM_FFd4 (LCD_CONTROLLER/cur_state_FSM_FFd4)
LUT4:I2->O 1 0.704 0.499 LCD_CONTROLLER/LCD_RS25 (LCD_CONTROLLER/LCD_RS25)
LUT2:I1->O 1 0.704 0.420 LCD_CONTROLLER/LCD_RS26 (LCD_RS_OBUF)
OBUF:I->O 3.272 LCD_RS_OBUF (LCD_RS)
----------------------------------------
Total 7.158ns (5.271ns logic, 1.887ns route)
(73.6% logic, 26.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_10ms_flag1'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 4.310ns (Levels of Logic = 1)
Source: LED0 (FF)
Destination: LED0 (PAD)
Source Clock: clk_10ms_flag1 rising
Data Path: LED0 to LED0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.591 0.447 LED0 (LED0_OBUF)
OBUF:I->O 3.272 LED0_OBUF (LED0)
----------------------------------------
Total 4.310ns (3.863ns logic, 0.447ns route)
(89.6% logic, 10.4% route)
=========================================================================
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.79 secs
-->
Total memory usage is 4530572 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 8 ( 0 filtered)
Number of infos : 2 ( 0 filtered)