From 739c9978b524f12968e063f60b0beb80ac6c3a47 Mon Sep 17 00:00:00 2001 From: jsxxsj <93038682+jsxxsj@users.noreply.github.com> Date: Wed, 22 May 2024 17:10:19 -0400 Subject: [PATCH] Update 2024.yaml Upload the paper SCARIF to the 2024.yaml --- docs/_data/publications/2024.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/_data/publications/2024.yaml b/docs/_data/publications/2024.yaml index 473afc1..ffa84fb 100644 --- a/docs/_data/publications/2024.yaml +++ b/docs/_data/publications/2024.yaml @@ -55,3 +55,11 @@ link: "https://dl.acm.org/doi/10.1145/3620666.3651347" abstract: | Despite the increasing adoption of FPGAs in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale, multi-die FPGAs to generate accelerators with high frequency and throughput. We propose TAPA-CS, a taskparallel dataflow programming framework which automatically partitions and compiles a large design across a cluster of FPGAs while achieving high frequency and throughput. TAPA-CS has three main contributions. First, it is an open-source framework which allows users to leverage virtually "unlimited" accelerator fabric, high-bandwidth memory (HBM), and on-chip memory. Second, given as input a large design, TAPA-CS automatically partitions the design to map to multiple FPGAs, while ensuring congestion control, resource balancing, and overlapping of communication and computation. Third, TAPA-CS couples coarse-grained floorplanning with interconnect pipelining at the inter- and intraFPGA levels to ensure high frequency. FPGAs in our multiFPGA testbed communicate through a high-speed 100Gbps Ethernet infrastructure. We have evaluated the performance of TAPA-CS on designs, including systolic-array based CNNs, graph processing workloads such as page rank, stencil applications, and KNN. On average, the 2-, 3-, and 4-FPGA designs are 2.1×, 3.2×, and 4.4× faster than the single FPGA baselines generated through Vitis HLS. TAPA-CS also achieves a frequency improvement between 11%-116% compared with Vitis HLS. + +- title: "SCARIF: Towards Carbon Modeling of Cloud Servers with Accelerators" + author: "Shixin Ji" + institution: "University of Pittsburgh, University of Notre Dame" + link: "https://arxiv.org/abs/2401.06270" + github: "https://github.com/arc-research-lab/SCARIF" + abstract: | + Embodied carbon has been widely reported as a significant component in the full system lifecycle of various computing systems green house gas emissions. Many efforts have been undertaken to quantify the elements that comprise this embodied carbon, from tools that evaluate semiconductor manufacturing to those that can quantify different elements of the computing system from commercial and academic sources. However, these tools cannot easily reproduce results reported by server vendors’ product carbon reports and the accuracy can vary substantially due to various assumptions. Furthermore, attempts to determine green house gas contributions using bottom-up methodologies often do not agree with system-level studies and are hard to rectify. Nonetheless, given there is a need to consider all contributions to green house gas emissions in datacenters, we propose SCARIF, the Server Carbon including Accelerator Reporter with Intelligence-based Formulation tool. SCARIF has three main contributions: (1) We first collect reported carbon cost data from server vendors and design statistic models to predict the embodied carbon cost so that users can get the embodied carbon cost for their server configurations. (2) We provide embodied carbon cost if users configure servers with accelerators including GPUs, and FPGAs. (3) By using case studies, we show that certain design choices of data center management might flip by the insight and observation from using SCARIF. Thus, SCARIF provides an opportunity for large-scale datacenter and hyperscaler design. We release SCARIF as an open-source tool at https://github.com/arc-research-lab/SCARIF.