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"xilinx.com:hls:pixel_pack_2:1.0" not found when running "make" for regenerating the Vivado pynq base project #23

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StefQM opened this issue Sep 25, 2022 · 2 comments
Open

"xilinx.com:hls:pixel_pack_2:1.0" not found when running "make" for regenerating the Vivado pynq base project #23

StefQM opened this issue Sep 25, 2022 · 2 comments

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@StefQM
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StefQM commented Sep 25, 2022 •
edited
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I'm trying to recreate the base overlay for Kria-Pynq.
I've got Vivado 2020.2.2 (Windows), which is the only version that should work (as I read here).
When running make (from the base directory), I get the following error:

ERROR: [BD::TCL 103-2012] The following IPs are not found in the IP Catalog:
  xilinx.com:hls:pixel_pack_2:1.0

Step1 of the make process make -C ../../pynq/boards/ZCU104/base/ hls_ip is not giving errors, so seems to be OK.
Step2 of the make process vivado -mode batch -source $(overlay_name).tcl -notrace [$(overlay_name)=base] gives the error of not finding xilinx.com:hls:pixel_pack_2:1.0.

Does anyone have any idea what could be the issue ?

Full log details:

C:\projects\kria\Kria-PYNQ\kv260\base>make
make -C ../../pynq/boards/ZCU104/base/ hls_ip
make[1]: Entering directory 'C:/projects/kria/Kria-PYNQ/pynq/boards/ZCU104/base'
vivado -mode batch -source build_ip.tcl -notrace

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:14:06 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source build_ip.tcl -notrace
Building color_convert_2 IP
Checking color_convert_2
Building pixel_pack_2 IP
Checking pixel_pack_2
Building pixel_unpack_2 IP
Checking pixel_unpack_2
HLS IP builds complete
INFO: [Common 17-206] Exiting Vivado at Sun Sep 25 15:00:00 2022...
make[1]: Leaving directory 'C:/projects/kria/Kria-PYNQ/pynq/boards/ZCU104/base'

vivado -mode batch -source base.tcl -notrace

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:14:06 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source base.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/projects/kria/Kria-PYNQ/pynq/boards/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
INFO: [BD::TCL 103-2003] Currently there is no design <base> in project, so creating one...
Wrote  : <C:\projects\kria\Kria-PYNQ\kv260\base\base\base.srcs\sources_1\bd\base\base.bd>
INFO: [BD::TCL 103-2004] Making design <base> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "base".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
user.org:user:address_remap:1.0 xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_register_slice:2.1 xilinx.com:ip:xlslice:1.0 xilinx.com:ip:mdm:3.2 xilinx.com:ip:util_ds_buf:2.1 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:dfx_axi_shutdown_manager:1.0 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:zynq_ultra_ps_e:3.3 xilinx.com:user:dff_en_reset_vector:1.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:user:io_switch:1.1 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:axi_bram_ctrl:4.1 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:axi_quad_spi:3.2 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_vdma:6.3 xilinx.com:ip:axis_subset_converter:1.1 xilinx.com:ip:v_demosaic:1.1 xilinx.com:ip:v_gamma_lut:1.1 xilinx.com:ip:mipi_csi2_rx_subsystem:5.1 xilinx.com:hls:pixel_pack_2:1.0 xilinx.com:ip:v_proc_ss:2.3 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:lmb_bram_if_cntlr:4.0  .
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD::TCL 103-2012] The following IPs are not found in the IP Catalog:
  xilinx.com:hls:pixel_pack_2:1.0

Resolution: Please add the repository containing the IP(s) to the project.
WARNING: [BD::TCL 103-2023] Will not continue with creation of design due to the error(s) above.

<...log continues, but I guess no relevant info anymore...>
@mariodruiz
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Hi @StefQM,

Did you hit the Y2K22 bug the first time you tried to build the project? If so, please start with a fresh version of the repo.

Mario

@StefQM
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StefQM commented Sep 26, 2022 •
edited
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Hi @mariodruiz,
Thank you for your response! I mistakenly thought the Y2K22 bug patch and the Vivado 2020.2 service pack 2, were one and the same thing. So, I installed the Y2K22 patch and the make file does not throw an error anymore.
[I've created pull request #24 to update the readme with some more details on the required Xilinx tooling versions.]

Unfortunately, the make is not running successfully yet:
The process is stuck at Waiting for impl_1 to finish... (tried it 2x, and waited for 6 hours (resp. 2 hours), then killed the process).

My analysis:
After starting the make, my PC works heavily for about 30 minutes (= several Vivado instances are running in the background), before slowing down to a state where only 1 vivado.exe remains (taking little resources) and vitis_hls.exe (taking average processing time)...). It seems like the Waiting for impl_1 to finish... state does not get triggered to resume after those 30 minutes...

Does anyone have an idea why the process would hang in the Waiting for impl_1 to finish... state ?

My workaround for anyone interested: (I haven't tested the end-result yet, but at least I have an end-result :) )
After interrupting the process, I manually executed all batch/tcl commands (from within the Vivado gui environment) as found after the Waiting for impl_1 to finish... command (see build_bitstream.tcl as refered to by vivado -mode batch -source build_bitstream.tcl -notrace in the make file).

For information, find below the complete log, until the point where it hangs...

C:\projects\kria\Kria-PYNQ\kv260\base>make
make -C ../../pynq/boards/ZCU104/base/ hls_ip
make[1]: Entering directory 'C:/projects/kria/Kria-PYNQ/pynq/boards/ZCU104/base'
vivado -mode batch -source build_ip.tcl -notrace

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:14:06 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source build_ip.tcl -notrace
Building color_convert_2 IP
Checking color_convert_2
Building pixel_pack_2 IP
Checking pixel_pack_2
Building pixel_unpack_2 IP
Checking pixel_unpack_2
HLS IP builds complete
INFO: [Common 17-206] Exiting Vivado at Mon Sep 26 19:45:44 2022...
make[1]: Leaving directory 'C:/projects/kria/Kria-PYNQ/pynq/boards/ZCU104/base'
vivado -mode batch -source base.tcl -notrace

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:14:06 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source base.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/projects/kria/Kria-PYNQ/pynq/boards/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
INFO: [BD::TCL 103-2003] Currently there is no design <base> in project, so creating one...
Wrote  : <C:\projects\kria\Kria-PYNQ\kv260\base\base\base.srcs\sources_1\bd\base\base.bd>
INFO: [BD::TCL 103-2004] Making design <base> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "base".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
user.org:user:address_remap:1.0 xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_register_slice:2.1 xilinx.com:ip:xlslice:1.0 xilinx.com:ip:mdm:3.2 xilinx.com:ip:util_ds_buf:2.1 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:dfx_axi_shutdown_manager:1.0 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:zynq_ultra_ps_e:3.3 xilinx.com:user:dff_en_reset_vector:1.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:user:io_switch:1.1 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:axi_bram_ctrl:4.1 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:axi_quad_spi:3.2 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_vdma:6.3 xilinx.com:ip:axis_subset_converter:1.1 xilinx.com:ip:v_demosaic:1.1 xilinx.com:ip:v_gamma_lut:1.1 xilinx.com:ip:mipi_csi2_rx_subsystem:5.1 xilinx.com:hls:pixel_pack_2:1.0 xilinx.com:ip:v_proc_ss:2.3 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:lmb_bram_if_cntlr:4.0  .
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_0: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_0: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin </iop_pmod0/io_switch_0/io_data_i> is being overridden by the user with net <data_i_1>. This pin will not be connected as a part of interface connection <io>.
WARNING: [BD 41-1306] The connection to interface pin </iop_pmod0/intr/gpio_io_o> is being overridden by the user with net <intr_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </iop_pmod0/io_switch_0/io_data_o> is being overridden by the user with net <io_switch_0_io_data_o>. This pin will not be connected as a part of interface connection <io>.
WARNING: [BD 41-1306] The connection to interface pin </iop_pmod0/io_switch_0/io_tri_o> is being overridden by the user with net <io_switch_0_io_tri_o>. This pin will not be connected as a part of interface connection <io>.
INFO: [Device 21-403] Loading part xck26-sfvc784-2LV-c
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'RX_EQUALIZATION_S' from 'NONE' to 'EQ_NONE' has been ignored for IP 'base_mipi_csi2_rx_subsyst_0/bd_6508/bd_6508_phy_0/bd_6508_phy_0_hssio_rx'
create_bd_cell: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1702.871 ; gain = 593.098
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'RX_EQUALIZATION_S' from 'NONE' to 'EQ_NONE' has been ignored for IP 'base_mipi_csi2_rx_subsyst_0/bd_6508/bd_6508_phy_0/bd_6508_phy_0_hssio_rx'
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axi_mm/gpio_io_o> is being overridden by the user with net <net_reset_sel_axi_mm_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axi_mm/gpio_io_i> is being overridden by the user with net <net_reset_sel_axi_mm_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_o> is being overridden by the user with net <net_reset_sel_axis_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_i> is being overridden by the user with net <net_reset_sel_axis_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </deint_ss/m_axis_tuser> is being overridden by the user with net <net_deint_ss_m_axis_tuser>. This pin will not be connected as a part of interface connection <M_AXIS>.
WARNING: [BD 41-1306] The connection to interface pin </deint_cc/s_axis_tuser> is being overridden by the user with net <net_deint_concat_dout>. This pin will not be connected as a part of interface connection <S_AXIS>.
WARNING: [BD 41-1306] The connection to interface pin </deint_cc/m_axis_tuser> is being overridden by the user with net <net_deint_cc_m_axis_tuser>. This pin will not be connected as a part of interface connection <M_AXIS>.
WARNING: [BD 41-1306] The connection to interface pin </dint/s_axis_video_TUSER> is being overridden by the user with net <net_deint_tuser_tap_Dout>. This pin will not be connected as a part of interface connection <s_axis_video>.
1
true
true
Slave segment '/axi_vdma/S_AXI_LITE/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
Slave segment '/csc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0001_0000 [ 64K ]>.
Slave segment '/dint/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0002_0000 [ 64K ]>.
Slave segment '/hcr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0003_0000 [ 64K ]>.
Slave segment '/hsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0004_0000 [ 64K ]>.
Slave segment '/ltr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0005_0000 [ 64K ]>.
Slave segment '/reset_sel_axi_mm/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0006_0000 [ 64K ]>.
Slave segment '/reset_sel_axis/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0007_0000 [ 64K ]>.
Slave segment '/vcr_i/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0008_0000 [ 64K ]>.
Slave segment '/vcr_o/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0009_0000 [ 64K ]>.
Slave segment '/video_router/xbar/S_AXI_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000A_0000 [ 64K ]>.
Slave segment '/vsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000B_0000 [ 64K ]>.
3
true
true
Slave segment '/csc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
WARNING: [BD 41-1306] The connection to interface pin </mipi/gpio_ip_reset/gpio_io_o> is being overridden by the user with net <gpio_ip_reset_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin </axi_intc/irq> is being overridden by the user with net <axi_intc_irq>. This pin will not be connected as a part of interface connection <interrupt>.
WARNING: [BD 41-1306] The connection to interface pin </zynq_ultra_ps_e_0/emio_gpio_o> is being overridden by the user with net <zynq_ultra_ps_e_0_emio_gpio_o>. This pin will not be connected as a part of interface connection <GPIO_0>.
Slave segment '/zynq_ultra_ps_e_0/SAXIGP6/LPD_DDR_LOW' is being assigned into address space '/address_remap_0/M_AXI_out' at <0x0000_0000 [ 2G ]>.
Slave segment '/axi_iic/S_AXI/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8003_0000 [ 64K ]>.
Slave segment '/axi_intc/S_AXI/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8008_0000 [ 64K ]>.
Slave segment '/mipi/axi_vdma/S_AXI_LITE/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8009_0000 [ 64K ]>.
Slave segment '/mipi/demosaic/s_axi_CTRL/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8004_0000 [ 64K ]>.
Slave segment '/mipi/gamma_lut/s_axi_CTRL/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8005_0000 [ 64K ]>.
Slave segment '/mipi/gpio_ip_reset/S_AXI/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8006_0000 [ 64K ]>.
Slave segment '/iop_pmod0/mb_bram_ctrl/S_AXI/Mem0' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x800A_0000 [ 64K ]>.
Slave segment '/mipi/mipi_csi2_rx_subsyst/csirxss_s_axi/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8000_0000 [ 8K ]>.
Slave segment '/mipi/pixel_pack/s_axi_control/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8007_0000 [ 64K ]>.
Slave segment '/shutdown_LPD/S_AXI_CTRL/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8002_0000 [ 64K ]>.
Slave segment '/mipi/v_proc_sys/s_axi_ctrl/Reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0x8001_0000 [ 64K ]>.
Slave segment '/address_remap_0/S_AXI_in/memory' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x8000_0000 [ 2G ]>.
Slave segment '/iop_pmod0/gpio/S_AXI/Reg' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x4000_0000 [ 64K ]>.
Slave segment '/iop_pmod0/iic/S_AXI/Reg' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x4080_0000 [ 64K ]>.
Slave segment '/iop_pmod0/intc/S_AXI/Reg' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x4120_0000 [ 64K ]>.
Slave segment '/iop_pmod0/intr/S_AXI/Reg' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x4001_0000 [ 64K ]>.
Slave segment '/iop_pmod0/io_switch_0/S_AXI/S_AXI_reg' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x44A2_0000 [ 64K ]>.
Slave segment '/iop_pmod0/microblaze_0_local_memory/lmb_bram_if_cntlr/SLMB1/Mem' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x0000_0000 [ 64K ]>.
Slave segment '/iop_pmod0/microblaze_0_local_memory/lmb_bram_if_cntlr/SLMB/Mem' is being assigned into address space '/iop_pmod0/microblaze_0/Instruction' at <0x0000_0000 [ 64K ]>.
Slave segment '/iop_pmod0/spi/AXI_LITE/Reg' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x44A1_0000 [ 64K ]>.
Slave segment '/iop_pmod0/timer/S_AXI/Reg' is being assigned into address space '/iop_pmod0/microblaze_0/Data' at <0x41C0_0000 [ 64K ]>.
Slave segment '/zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW' is being assigned into address space '/mipi/axi_vdma/Data_S2MM' at <0x0000_0000 [ 2G ]>.
Slave segment '/zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_HIGH' is being assigned into address space '/mipi/axi_vdma/Data_S2MM' at <0x8_0000_0000 [ 4G ]>.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_HIGH from address space /mipi/axi_vdma/Data_S2MM.
Slave segment '/zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM' is being assigned into address space '/mipi/axi_vdma/Data_S2MM' at <0xFF00_0000 [ 16M ]>.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM from address space /mipi/axi_vdma/Data_S2MM.
Slave segment '/zynq_ultra_ps_e_0/SAXIGP3/HP1_QSPI' is being assigned into address space '/mipi/axi_vdma/Data_S2MM' at <0xC000_0000 [ 512M ]>.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP3/HP1_QSPI from address space /mipi/axi_vdma/Data_S2MM.
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_M_AXI_S2MM_DATA_WIDTH(128) on '/mipi/axi_vdma' with propagated value(64). Command ignoredINFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /iop_pmod0/spi
                   #######################################################################################
                   INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
                   ########################################################################################
INFO: [xilinx.com:ip:axi_vdma:6.3-17] /mipi/axi_vdma
                    All clocks connected to AXI VDMA are not identical, therefore configuring AXI-VDMA in ASYNC mode.
WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 3 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.
WARNING: [BD 41-237] Bus Interface property WUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /shutdown_LPD/M_AXI(1)
WARNING: [BD 41-237] Bus Interface property RUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /shutdown_LPD/M_AXI(1)
WARNING: [BD 41-237] Bus Interface property BUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /shutdown_LPD/M_AXI(1)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP1_FPD(1) and /mipi/axi_vdma/M_AXI_S2MM(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP1_FPD(1) and /mipi/axi_vdma/M_AXI_S2MM(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m00_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m00_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /iop_pmod0/mb_bram_ctrl/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /iop_pmod0/mb_bram_ctrl/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mipi/axi_interconnect_1/s00_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/m01_couplers/auto_cc/M_AXI(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mipi/axi_interconnect_1/s00_couplers/auto_pc/S_AXI(0) and /ps8_0_axi_periph/m01_couplers/auto_cc/M_AXI(16)
validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1874.051 ; gain = 23.301
Wrote  : <C:\projects\kria\Kria-PYNQ\kv260\base\base\base.srcs\sources_1\bd\base\base.bd>
INFO: [Common 17-206] Exiting Vivado at Mon Sep 26 19:46:47 2022...
vivado -mode batch -source build_bitstream.tcl -notrace

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:14:06 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source build_bitstream.tcl -notrace
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/projects/kria/Kria-PYNQ/pynq/boards/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
open_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1111.949 ; gain = 0.000
Reading block design file <C:/projects/kria/Kria-PYNQ/kv260/base/base/base.srcs/sources_1/bd/base/base.bd>...
Adding component instance block -- user.org:user:address_remap:1.0 - address_remap_0
Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - axi_iic
Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - axi_intc
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us
Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - axi_register_slice_0
Adding component instance block -- xilinx.com:user:dff_en_reset_vector:1.0 - dff_en_reset_vector_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio
Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - iic
Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - intc
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - intr
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - intr_concat
Adding component instance block -- xilinx.com:user:io_switch:1.1 - io_switch_0
Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - logic_1
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - mb_axi_periph
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - mb_bram_ctrl
Adding component instance block -- xilinx.com:ip:microblaze:11.0 - microblaze_0
Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10
Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram
Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - lmb_bram_if_cntlr
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_100M
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - spi
Adding component instance block -- xilinx.com:ip:axi_timer:2.0 - timer
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod0_intr_ack
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod0_reset
Adding component instance block -- xilinx.com:ip:mdm:3.2 - mdm_0
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_1
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma
Adding component instance block -- xilinx.com:ip:axis_subset_converter:1.1 - axis_channel_swap
Adding component instance block -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter
Adding component instance block -- xilinx.com:ip:v_demosaic:1.1 - demosaic
Adding component instance block -- xilinx.com:ip:v_gamma_lut:1.1 - gamma_lut
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio_ip_reset
Adding component instance block -- xilinx.com:ip:mipi_csi2_rx_subsystem:5.1 - mipi_csi2_rx_subsyst
Adding component instance block -- xilinx.com:hls:pixel_pack_2:1.0 - pixel_pack
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:ip:v_proc_ss:2.3 - v_proc_sys
Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - pmod_buf
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - ps8_0_axi_periph
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_299M
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_99M
Adding component instance block -- xilinx.com:ip:dfx_axi_shutdown_manager:1.0 - shutdown_LPD
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_1
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - zynq_ultra_ps_e_0
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_HIGH from address space /mipi/axi_vdma/Data_S2MM.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM from address space /mipi/axi_vdma/Data_S2MM.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP3/HP1_QSPI from address space /mipi/axi_vdma/Data_S2MM.
Successfully read diagram <base> from block design file <./base/base.srcs/sources_1/bd/base/base.bd>
INFO: [BD 41-1662] The design 'base.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod0/microblaze_0_local_memory/lmb_bram/addrb'(32) to pin: '/iop_pmod0/microblaze_0_local_memory/BRAM_PORTB_addr'(16) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/mipi/demosaic/s_axis_video_TDEST'(1) to pin: '/mipi/axis_subset_converter/m_axis_tdest'(10) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_arid'(6) to pin: '/shutdown_LPD/m_axi_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_awid'(6) to pin: '/shutdown_LPD/m_axi_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected.
VHDL Output written to : c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/synth/base.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod0/microblaze_0_local_memory/lmb_bram/addrb'(32) to pin: '/iop_pmod0/microblaze_0_local_memory/BRAM_PORTB_addr'(16) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/mipi/demosaic/s_axis_video_TDEST'(1) to pin: '/mipi/axis_subset_converter/m_axis_tdest'(10) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_arid'(6) to pin: '/shutdown_LPD/m_axi_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_awid'(6) to pin: '/shutdown_LPD/m_axi_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected.
VHDL Output written to : c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/sim/base.v
VHDL Output written to : c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/hdl/base_wrapper.v
INFO: [Project 1-1716] Could not find the wrapper file ./base/base.srcs/sources_1/bd/base/hdl/base_wrapper.v, checking in project .gen location instead.
INFO: [Vivado 12-12390] Found file ./base/base.gen/sources_1/bd/base/hdl/base_wrapper.v, adding it to Project
INFO: [BD 41-1662] The design 'base.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod0/microblaze_0_local_memory/lmb_bram/addrb'(32) to pin: '/iop_pmod0/microblaze_0_local_memory/BRAM_PORTB_addr'(16) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/mipi/demosaic/s_axis_video_TDEST'(1) to pin: '/mipi/axis_subset_converter/m_axis_tdest'(10) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_arid'(6) to pin: '/shutdown_LPD/m_axi_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_awid'(6) to pin: '/shutdown_LPD/m_axi_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected.
VHDL Output written to : c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/synth/base.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod0/microblaze_0_local_memory/lmb_bram/addrb'(32) to pin: '/iop_pmod0/microblaze_0_local_memory/BRAM_PORTB_addr'(16) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/mipi/demosaic/s_axis_video_TDEST'(1) to pin: '/mipi/axis_subset_converter/m_axis_tdest'(10) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_arid'(6) to pin: '/shutdown_LPD/m_axi_arid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_awid'(6) to pin: '/shutdown_LPD/m_axi_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected.
VHDL Output written to : c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/sim/base.v
VHDL Output written to : c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/hdl/base_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block address_remap_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_pc_0/base_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_us .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_register_slice_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/dff_en_reset_vector_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/gpio .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/iic .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intr .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intr_concat .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/io_switch_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/s00_couplers/auto_us .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/m00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/m01_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/m02_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/m03_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/m04_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/m05_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_axi_periph/m06_couplers/auto_ds .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_bram_ctrl .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_local_memory/dlmb_v10 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_local_memory/ilmb_v10 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_local_memory/lmb_bram .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_local_memory/lmb_bram_if_cntlr .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/proc_sys_reset_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/spi .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_timer_0/base_timer_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/timer .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod0_intr_ack .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod0_reset .
INFO: [Device 21-403] Loading part xck26-sfvc784-2LV-c
INFO: [BD 41-1029] Generation completed for the IP Integrator block mdm_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/axi_interconnect_1/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_pc_1/base_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/axi_interconnect_1/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/axi_interconnect_1/m05_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/axi_interconnect_1/m06_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/axi_vdma .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_axis_channel_swap_0/base_axis_channel_swap_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/axis_channel_swap .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_axis_subset_converter_0/base_axis_subset_converter_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/axis_subset_converter .
WARNING: [IP_Flow 19-1971] File named "sim/base_demosaic_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/demosaic .
WARNING: [IP_Flow 19-1971] File named "sim/base_gamma_lut_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/gamma_lut .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/gpio_ip_reset .
Exporting to file c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_mipi_csi2_rx_subsyst_0/bd_0/hw_handoff/base_mipi_csi2_rx_subsyst_0.hwh
Generated Block Design Tcl file c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_mipi_csi2_rx_subsyst_0/bd_0/hw_handoff/base_mipi_csi2_rx_subsyst_0_bd.tcl
Generated Hardware Definition File c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_mipi_csi2_rx_subsyst_0/bd_0/synth/base_mipi_csi2_rx_subsyst_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/mipi_csi2_rx_subsyst .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/pixel_pack .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/proc_sys_reset_0 .
WARNING: [IP_Flow 19-1971] File named "sim/bd_5b29_csc_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
Exporting to file c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_v_proc_sys_0/bd_0/hw_handoff/base_v_proc_sys_0.hwh
Generated Block Design Tcl file c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_v_proc_sys_0/bd_0/hw_handoff/base_v_proc_sys_0_bd.tcl
Generated Hardware Definition File c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_v_proc_sys_0/bd_0/synth/base_v_proc_sys_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block mipi/v_proc_sys .
INFO: [BD 41-1029] Generation completed for the IP Integrator block pmod_buf .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_pc_2/base_auto_pc_2_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/m00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/m01_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_pc_3/base_auto_pc_3_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/m02_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/ip/base_auto_pc_4/base_auto_pc_4_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/m04_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps8_0_299M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps8_0_99M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block shutdown_LPD .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_1 .
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.3-0] base_zynq_ultra_ps_e_0_0:
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_LPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP1_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_LPD'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block zynq_ultra_ps_e_0 .
Exporting to file c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/hw_handoff/base.hwh
Generated Block Design Tcl file c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/hw_handoff/base_bd.tcl
Generated Hardware Definition File c:/projects/kria/Kria-PYNQ/kv260/base/base/base.gen/sources_1/bd/base/synth/base.hwdef
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_address_remap_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_cc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_cc_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_cc_2
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_ds_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_ds_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_ds_2
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_ds_3
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_ds_4
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_ds_5
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_ds_6
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_pc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_pc_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_pc_2
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_pc_3
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_pc_4
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_us_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_auto_us_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_axi_iic_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_axi_intc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_axi_register_slice_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_axi_vdma_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_axis_channel_swap_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_axis_subset_converter_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_demosaic_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_dff_en_reset_vector_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_dlmb_v10_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_gamma_lut_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_gpio_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_gpio_ip_reset_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_iic_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_ilmb_v10_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_intc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_intr_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_io_switch_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_lmb_bram_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_lmb_bram_if_cntlr_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_mb_bram_ctrl_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_mdm_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_microblaze_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_mipi_csi2_rx_subsyst_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_pixel_pack_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_pmod_buf_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_proc_sys_reset_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_proc_sys_reset_100M_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_rst_ps8_0_299M_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_rst_ps8_0_99M_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_shutdown_LPD_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_spi_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_timer_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_v_proc_sys_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_xbar_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_xbar_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_xbar_2
INFO: [IP_Flow 19-7066] Running IP cache check for IP base_zynq_ultra_ps_e_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP bd_5b29_csc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP bd_6508_phy_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP bd_6508_r_sync_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP bd_6508_rx_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP bd_6508_vfb_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP bd_6508_xbar_0

[Mon Sep 26 19:48:14 2022] Launched bd_5b29_csc_0_synth_1, bd_6508_vfb_0_0_synth_1, bd_6508_xbar_0_synth_1, bd_6508_phy_0_synth_1, bd_6508_r_sync_0_synth_1, bd_6508_rx_0_synth_1, base_proc_sys_reset_100M_0_synth_1, base_mb_bram_ctrl_0_synth_1, base_microblaze_0_0_synth_1, base_dlmb_v10_0_synth_1, base_auto_ds_4_synth_1, base_auto_ds_0_synth_1, base_auto_ds_3_synth_1, base_auto_ds_5_synth_1, base_auto_ds_2_synth_1, base_lmb_bram_0_synth_1, base_xbar_0_synth_1, base_auto_us_1_synth_1, base_auto_ds_6_synth_1, base_auto_ds_1_synth_1, base_ilmb_v10_0_synth_1, base_lmb_bram_if_cntlr_0_synth_1, base_auto_pc_4_synth_1, base_pmod_buf_0_synth_1, base_pixel_pack_0_synth_1, base_shutdown_LPD_0_synth_1, base_rst_ps8_0_299M_0_synth_1, base_auto_pc_2_synth_1, base_rst_ps8_0_99M_0_synth_1, base_xbar_2_synth_1, base_zynq_ultra_ps_e_0_0_synth_1, base_mipi_csi2_rx_subsyst_0_synth_1, base_auto_cc_2_synth_1, base_auto_pc_3_synth_1, base_proc_sys_reset_0_0_synth_1, base_v_proc_sys_0_synth_1, base_axis_channel_swap_0_synth_1, base_timer_0_synth_1, base_auto_pc_1_synth_1, base_auto_cc_0_synth_1, base_axis_subset_converter_0_synth_1, base_gamma_lut_0_synth_1, base_mdm_0_0_synth_1, base_auto_cc_1_synth_1, base_spi_0_synth_1, base_demosaic_0_synth_1, base_gpio_ip_reset_0_synth_1, base_xbar_1_synth_1, base_axi_vdma_0_synth_1, base_iic_0_synth_1, base_intc_0_synth_1, base_dff_en_reset_vector_0_0_synth_1, base_gpio_0_synth_1, base_axi_register_slice_0_0_synth_1, base_intr_0_synth_1, base_io_switch_0_0_synth_1, base_address_remap_0_0_synth_1, base_auto_pc_0_synth_1, base_axi_intc_0_synth_1, base_axi_iic_0_synth_1, base_auto_us_0_synth_1, synth_1...
Run output will be captured here:
bd_5b29_csc_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/bd_5b29_csc_0_synth_1/runme.log
bd_6508_vfb_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/bd_6508_vfb_0_0_synth_1/runme.log
bd_6508_xbar_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/bd_6508_xbar_0_synth_1/runme.log
bd_6508_phy_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/bd_6508_phy_0_synth_1/runme.log
bd_6508_r_sync_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/bd_6508_r_sync_0_synth_1/runme.log
bd_6508_rx_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/bd_6508_rx_0_synth_1/runme.log
base_proc_sys_reset_100M_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_proc_sys_reset_100M_0_synth_1/runme.log
base_mb_bram_ctrl_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_mb_bram_ctrl_0_synth_1/runme.log
base_microblaze_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_microblaze_0_0_synth_1/runme.log
base_dlmb_v10_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_dlmb_v10_0_synth_1/runme.log
base_auto_ds_4_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_ds_4_synth_1/runme.log
base_auto_ds_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_ds_0_synth_1/runme.log
base_auto_ds_3_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_ds_3_synth_1/runme.log
base_auto_ds_5_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_ds_5_synth_1/runme.log
base_auto_ds_2_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_ds_2_synth_1/runme.log
base_lmb_bram_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_lmb_bram_0_synth_1/runme.log
base_xbar_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_xbar_0_synth_1/runme.log
base_auto_us_1_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_us_1_synth_1/runme.log
base_auto_ds_6_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_ds_6_synth_1/runme.log
base_auto_ds_1_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_ds_1_synth_1/runme.log
base_ilmb_v10_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_ilmb_v10_0_synth_1/runme.log
base_lmb_bram_if_cntlr_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_lmb_bram_if_cntlr_0_synth_1/runme.log
base_auto_pc_4_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_pc_4_synth_1/runme.log
base_pmod_buf_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_pmod_buf_0_synth_1/runme.log
base_pixel_pack_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_pixel_pack_0_synth_1/runme.log
base_shutdown_LPD_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_shutdown_LPD_0_synth_1/runme.log
base_rst_ps8_0_299M_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_rst_ps8_0_299M_0_synth_1/runme.log
base_auto_pc_2_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_pc_2_synth_1/runme.log
base_rst_ps8_0_99M_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_rst_ps8_0_99M_0_synth_1/runme.log
base_xbar_2_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_xbar_2_synth_1/runme.log
base_zynq_ultra_ps_e_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_zynq_ultra_ps_e_0_0_synth_1/runme.log
base_mipi_csi2_rx_subsyst_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_mipi_csi2_rx_subsyst_0_synth_1/runme.log
base_auto_cc_2_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_cc_2_synth_1/runme.log
base_auto_pc_3_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_pc_3_synth_1/runme.log
base_proc_sys_reset_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_proc_sys_reset_0_0_synth_1/runme.log
base_v_proc_sys_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_v_proc_sys_0_synth_1/runme.log
base_axis_channel_swap_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_axis_channel_swap_0_synth_1/runme.log
base_timer_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_timer_0_synth_1/runme.log
base_auto_pc_1_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_pc_1_synth_1/runme.log
base_auto_cc_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_cc_0_synth_1/runme.log
base_axis_subset_converter_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_axis_subset_converter_0_synth_1/runme.log
base_gamma_lut_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_gamma_lut_0_synth_1/runme.log
base_mdm_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_mdm_0_0_synth_1/runme.log
base_auto_cc_1_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_cc_1_synth_1/runme.log
base_spi_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_spi_0_synth_1/runme.log
base_demosaic_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_demosaic_0_synth_1/runme.log
base_gpio_ip_reset_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_gpio_ip_reset_0_synth_1/runme.log
base_xbar_1_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_xbar_1_synth_1/runme.log
base_axi_vdma_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_axi_vdma_0_synth_1/runme.log
base_iic_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_iic_0_synth_1/runme.log
base_intc_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_intc_0_synth_1/runme.log
base_dff_en_reset_vector_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_dff_en_reset_vector_0_0_synth_1/runme.log
base_gpio_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_gpio_0_synth_1/runme.log
base_axi_register_slice_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_axi_register_slice_0_0_synth_1/runme.log
base_intr_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_intr_0_synth_1/runme.log
base_io_switch_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_io_switch_0_0_synth_1/runme.log
base_address_remap_0_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_address_remap_0_0_synth_1/runme.log
base_auto_pc_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_pc_0_synth_1/runme.log
base_axi_intc_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_axi_intc_0_synth_1/runme.log
base_axi_iic_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_axi_iic_0_synth_1/runme.log
base_auto_us_0_synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/base_auto_us_0_synth_1/runme.log
synth_1: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/synth_1/runme.log
[Mon Sep 26 19:48:14 2022] Launched impl_1...
Run output will be captured here: C:/projects/kria/Kria-PYNQ/kv260/base/base/base.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:49 ; elapsed = 00:01:05 . Memory (MB): peak = 1788.098 ; gain = 676.148
[Mon Sep 26 19:48:14 2022] Waiting for impl_1 to finish...

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