VSD Research Internship Project

Vending Machine with Change System

I will be implementing an Ideal Vending Machine with Change System. The project aims to match the functional simulation results obtained from the RTL netlist and Gate-Synthesized netlist as closely as possible.

Technology used: Sky130 technology

Through this Repo, I intend to document my weekly learnings & progress of this project and also contribute to the opensource community.

Reach out to me @ LinkedIn

RTL2GDS flow & tools required(VSD openEDA course)

Complete flow toolchain - Qflow

Static Timing Analysis mandatory at every stage,tool - Opentimer

• RTL netlist

Logic Synthesis tool - Yosys open synthesis suite

• Through Logic synthesis you get Logical netlist(gates&flipflops)

IC design flow tool(FP,placement,CTS) - Graywolf

• Floorplanning
• Placement of logical cells

Layout viewer at any stage to correct DRC,tool - MAGIC

• Clock Tree Synthesis(to get the specified skew)

Routing toll - Qrouter

• Routing
• Signoff - gds out to fabrication

Pre/Post layout Simulation,tool - ngSPICE

Schematic editor,tool - eSim

Week1_Task1 (Tool Installation)

Work

To install all the necessary tools required for this project.Refer to the course(VSD openEDA) to install Virtual box with Ubuntu 20.04+,allocate 6-8GB RAM,4CPU and 40GB Disk Space.Install the following tools:

• iverilog

• gtkwave

• yosys

iverilog

sudo apt-get install iverilog

After launch

gtkwave

(paste each line seperately)
sudo apt update
sudo apt install gtkwave

After launch

yosys

(paste each line seperately)
sudo apt-get install git
git clone https://github.com/YosysHQ/yosys.git
cd yosys
sudo apt install make
sudo apt-get install build-essential clang bison flex \libreadline-dev gawk tcl-dev libffi-dev git \
graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev
make config-gcc
make 
sudo make install

After launch

Week1_Task2 (Design Specs)

Specifications

Block Diagram:

S.No	Name of the Port	Direction	Size	Description
1.	Product	Output	1	Successful Transaction(1) or Not(0)
2.	Change	Output	2	Excess Amount that is to be Returned
				Rs.5(01) and Rs.10(10)
3.	Coins	Input	2	Amount Inserted
				Rs.0(00) , Rs.5(01) and Rs.10(10)
4.	Clk	Input	1	Clock Signal-Synchronize
5.	Rst	Input	1	Reset Signal
6.	Current_State	Intermediate	2	Store the Current State
7.	Next_State	Intermediate	2	Store the Next State

Assumptions:

• Only one type product is present in the machine.
• Each Product costs Rs.15.
• Only Currency denominations are Rs.5 and Rs.10.

State Diagram:

• Each state signifies the current amount which is inside the machine.
• Next state is copied to current state for every cycle.
• Ideal Vending machine here means,as shown in S1 to S0 (0/0,c=5) transaction,the machine should return the change when the user does not add the cost amount after waiting for a certain time(here the end of simulation).

Waveforms

rst off at #6,changes starts to reflect from #10(1st posedge of clk after rst=0).

Coin insertion-5,5,5:

Product returned at #35.

Coin insertion-5,10:

Product returned at #25.

Coin insertion-10,10:

Product returned at #25 with change of 5 rs.

Coin insertion-10,0:

Change of 5 rs returned at #25

Week2_Task1 (Basics of Functional Simulation)

Theory

Introduction:

• RTL Design: RTL Design refers to the actual Verilog code or a set of Verilog codes that encapsulates the intended functionality to fulfill specified requirements. Register Transfer Level (RTL) serves as an abstraction for defining the digital aspects of a design, representing a fundamental framework in contemporary electronic system definitions. Often regarded as the cornerstone in the design and verification process, RTL design is typically expressed using hardware description languages (HDL) like Verilog or VHDL.

• Test Bench: A test bench constitutes the environment set up to provide stimuli (test vectors) to the design under evaluation to assess its functionality. By subjecting the design to stimuli and observing its outputs, one ensures compliance with the specified requirements. This process involves verifying whether the design's behavior aligns with the given specifications.

• Simulation: Simulation involves executing the design model written in HDL, following successful compilation and elaboration, based on a specified execution model. Utilizing simulation software (simulator), it verifies the functional correctness of a digital design described in a hardware description language (HDL) such as VHDL or Verilog. It ensures adherence to given specifications.

• Simulator: A tool used for simulating the design, such as "iverilog" in this context. RTL design embodies the required specifications' implementation, and its functionality is verified by simulating the design using a simulator.

• How does a simulator work? A simulator operates by continuously monitoring input changes. Upon any alteration in inputs, the output undergoes re-evaluation. If there is no input change, output evaluation is bypassed. The simulator records input changes and corresponding output states into a file.

Design and Test Bench setup:

• The Verilog code representing the RTL design typically features primary inputs and primary outputs, which may vary in number. These primary inputs and outputs serve as the interfaces between the design and its external environment.

• To validate the functionality of the design, stimuli must be applied to all primary inputs, and the resulting behavior at the primary outputs must be observed. This necessitates the use of a stimulus generator at the input and a stimulus observer at the output.

• In the test bench, the design module is instantiated, allowing stimuli to be applied. It's essential to understand that while the test bench orchestrates the testing process by instantiating the design module and applying stimuli, it itself does not possess any primary inputs or outputs. Instead, it serves as the framework within which the design is tested, facilitating the verification process without directly interacting with the design's primary interfaces.

Simulation Flow:

• Input to Iverilog: Iverilog takes the RTL design (written in Verilog) and the corresponding test bench as input.

• Compilation: Iverilog compiles the RTL design and the test bench, generating an executable file named "a.out".

• Execution: Executing "a.out" triggers the simulation process.

• Simulation Output: During simulation, "a.out" produces simulation data in the form of a value change dump (.vcd) file.

• Visualization with GTKWave: The generated .vcd file is then utilized by GTKWave, a waveform viewer tool.

• Displaying Simulation Waveform: GTKWave interprets the .vcd file and displays the simulation waveform, enabling users to analyze the behavior of the design over time.

Commands

Setup:

git clone https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop.git
cd sky130RTLDesignAndSynthesisWorkshop/

lib: Contains sky130 standard cell library(sky130_fd_sc_hd__tt_025C_1v80.lib)

verilog_model: Contains verilog model of standard cells in lib directory(primitives.v,sky130_fd_sc_hd.v)

cd verilog_files/
ls

Simulation of Multiplexer:

iverilog good_mux.v tb_good_mux.v

ls
./a.out
gtkwave tb_good_mux.vcd

Output Waveforms

Mux Truth table:

Select Signal(sel)	Inputs(i1 i0)	Outputs(y)
0	0 0	0
0	0 1	1
1	1 0	1
1	1 1	1

When sel=0,y=i0

When sel=1,y=i1

Week2_Task2 (Basics of Synthesis,Gate Level Simulation)

Theory

Synthesis:

• The synthesis tool(Yosys) takes the RTL design and the liberty file(.lib) as inputs and synthesize the RTL design into netlist which is the gate level representation of the design in form of the standard cells in .lib.

SKY130 PDK libraries:

There are seven standard cell libraries provided directly by the SkyWater Technology foundry available for use on SKY130 designs, which differ in intended applications and come in three separate cell heights.Libraries in the SKY130 PDK are named using the following scheme:

<Process name> _ <Library Source Abbreviation> _ <Library Type Abbreviation> [_ <Library Name>]	

sky130_fd_sc_hd__tt_025C_1v80.lib:

The sky130_fd_sc_hd library is designed for high density. This library enables higher routed gated density, lower dynamic power consumption, and comparable timing and leakage power. As a trade-off it has lower drive strength.

• Sky130 : It is the name of the process technology.
• fd : It is abbreviation for who created and is responsible for the library, here the SkyWater Foundry.
• sc : It is abbreviation for the type of content found in the library, here the Digital Standard Cells.
• hd : It represents high density.
• tt : It shows the typical process corner.
• 025c : It shows the temperature(25C).
• 1v80 : It shows the operating process voltage.

Liberty file(.lib):

Liberty files are a IEEE Standard for defining PVT Characterization, Relating Input and Output Characteristics, Timing, Power, Noise parameter associated with cells inside the standard cell library of a particular technology node. Liberty is an ASCII format, usually represented in a text file with extension ".lib". It is an industry standard format used to describe library cells of a particular technology. It is a collection of logic module/Standard cells. It includes different types of gates and different flavours of these gates.

Verify the Synthesis:

• Gate Level Simulation (GLS) serves as a crucial step in the verification process of a design implementation. It enhances confidence by validating dynamic circuit behavior, which cannot be accurately verified through static methods alone. GLS is particularly important due to its ability to overcome the limitations of static-timing analysis and address emerging challenges such as low power concerns, complex timing checks, design for test (DFT) insertion at the gate level, and other low-power considerations.

• The term "gate level" in GLS refers to the netlist view of a circuit, typically generated through logic synthesis. Unlike RTL simulation, which occurs pre-synthesis, GLS operates post-synthesis. The netlist view comprises a comprehensive connection list featuring gates and IP models with full functional and timing behavior.

• During GLS, the test bench is executed with the "Synthesized Netlist" as the Design under Test (DUT). Since the netlist maintains logical equivalence with the RTL code, the same test bench used for RTL simulation can often be leveraged.

• It verifies the logical correctness of the design after synthesis, ensuring that the functionality remains intact.It also ensures that the timing requirements of the design are met. This often necessitates running GLS with delay annotation, a practice known as Timing-Aware GLS, which accounts for timing constraints and delays introduced during synthesis.

• Gate level verilog model : It is one of the input to iverilog. It is used to tell iverilog about the standard cell models used in generated netlist after synthesis. The gate level verilog model can be:
  • Functional : It can validates the functionality of the design alone.
  • Timing aware : It can validate functinality and can ensure timing both.

Commands for synthesis

yosys

read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib #read .lib,relative path wrt verilog_files
read_verilog good_mux.v #read design
synth -top good_mux #synthesize the module

read_liberty : It read cells from liberty file as modules into current design. The option "-lib" only create empty blackbox modules.

read_verilog : This command is used to read the verilog desgin file. It load modules from a Verilog file to the current design.

synth : This command runs the default synthesis script. This command does not operate on partly selected designs.

-top : This option use the specified module as top module (default='top'). Here we have module name "good_mux".

gvim good_mux.v

abc -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib  #generate netlist

abc : This pass uses the ABC tool for technology mapping of yosys's internal gate library to a target architecture. This command converts RTL code into gates,cells which is taken from the sky130_fd_sc_hd__tt_025C_1v80.lib file.

-liberty : It generate netlists for the specified cell library (using the liberty file format).

show 

Show : It creates graphviz DOT file for the selected part of the design and compile it to a graphics file (usually SVG or PostScript).It is used to show the logic realized from the verilog code after synthesis.

write_verilog good_mux_netlist.v #write netlist

write_verilog : It write the current design to a Verilog file.

good_mux_netlist.v : File name to which we want to write the netlist.

vim good_mux_netlist.v 

write_verilog -noattr good_mux_netlist.v

-noattr :By using this option no attributes are included in the output.

!gvim good_mux_netlist.v

Waveforms from GLS

Pre-Synthesis Simulation:

iverilog good_mux.v tb_good_mux.v
./a.out
gtkwave tb_good_mux.vcd

Post-Synthesis Simulation:

iverilog good_mux_netlist.v tb_good_mux.v ../my_lib/verilog_model/sky130_fd_sc_hd.v ../my_lib/verilog_model/primitives.v
./a.out
gtkwave tb_good_mux.vcd

We can observe that the results from both functional simulation and gate level simulation match.

Week3_Task1 (VM-Functional Simulation)

Commands

mkdir VM
cd VM
mkdir verilog_codes
cd verilog_codes/
gvim vending_machine.v
gvim vending_machine_tb.v
ls
iverilog vending_machine.v vending_machine_tb.v
ls

./a.out
gtkwave vending_machine_tb.vcd

Output Waveforms

To change the inputs,change the time specifications for input signal in tb.

Coin insertion-5,5,5:

#6 rst = 0;
in = 1;
#11 in = 1;
#16 in = 1;
#25 $finish;

Coin insertion-5,10:

#6 rst = 0;
in = 1;
#11 in = 2;
#25 $finish;

Coin insertion-10,10:

#6 rst = 0;
in = 2;
#11 in = 2;
#25 $finish;

Coin insertion-10,0:

#6 rst = 0;
in = 2;
#11 in = 0;
#25 $finish;

Week3_Task2 (VM-Synthesis,Gate Level Simulation)

Commands for synthesis

yosys

read_liberty -lib /home/varun/sky130RTLDesignAndSynthesisWorkshop/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog vending_machine.v
synth -top vending_machine

dfflibmap -liberty /home/varun/sky130RTLDesignAndSynthesisWorkshop/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

While synthesizing RTL code for flops we need to use this command,because in the library flow, there will be separate library for flops and standard cells. So we need to explicitly tell the tool where to pickup flops in the design from. In our case we have same library for both , so we have used same library path for invoking dfflibmap command.

(command to do all optimizations)
opt_clean -purge

opt_clean : This pass identifies wires and cells that are unused and removes them. Other passes often remove cells but leave the wires in the design or reconnect the wires but leave the old cells in the design. This pass can be used to clean up after the passes that do the actual work.This pass only operates on completely selected modules without processes.

-purge : also remove internal nets if they have a public name.

abc -liberty /home/varun/sky130RTLDesignAndSynthesisWorkshop/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

show 

write_verilog vending_machine_netlist.v

!gvim vending_machine_netlist.v 

write_verilog -noattr vending_machine_netlist.v

!gvim vending_machine_netlist.v 

Waveforms from GLS

Pre-Synthesis Simulation:

iverilog vending_machine.v vending_machine_tb.v
./a.out
gtkwave vending_machine_tb.vcd

Coin insertion-10,0:

Post-Synthesis Simulation:

iverilog vending_machine.v vending_machine_tb.v /home/varun/sky130RTLDesignAndSynthesisWorkshop/my_lib/verilog_model/sky130_fd_sc_hd.v /home/varun/sky130RTLDesignAndSynthesisWorkshop/my_lib/verilog_model/primitives.v
./a.out
gtkwave vending_machine_tb.vcd

Coin insertion-10,0:

We can observe that the results from both functional simulation and gate level simulation match.

References

Refer to this course for all the open source tools installation - VSD openEDA

Link- helped me to understand the working of an ideal vending machine. Also refer to his playlist for more rtl projects in verilog.

Link- about .lib file in vlsi.

Link- good reference documentation.

Link1,Link2,Link3- helped me to understand basic github documentation.Refer to the code of someone's README file to understand the syntax for a particular format that you want to replicate.

Acknowledgement

Mr. Kunal Ghosh

The Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd,India

Internship Completion Certificate